* [PATCH v3 2/5] arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts
[not found] <20220909200256.15981-1-jbx6244@gmail.com>
@ 2022-09-09 20:18 ` Johan Jonker
2022-09-28 13:16 ` Kever Yang
2022-09-09 20:19 ` [PATCH v3 3/5] arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files Johan Jonker
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Johan Jonker @ 2022-09-09 20:18 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot
Bulk convert rk3128 DT gpios to their constant counterparts.
sed -i -f script.sed rk3128.dtsi
sed -i -f script.sed rk3128-evb.dts
================================
/rockchip,pins *=/bcheck
b # to end of script
:append-next-line
N
:check
/^[^;]*$/bappend-next-line
s/<RK_GPIO\([0-9]\) /<\1 /g
s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g
s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g
s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g
s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g
s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g
s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g
s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g
s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g
s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g
s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g
s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g
s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g
s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g
s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g
s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g
s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g
s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g
s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g
s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g
s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g
s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g
s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g
s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g
s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g
s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g
s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g
s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g
s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g
s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g
s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g
s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g
s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g
s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g
s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3128-evb.dts | 4 +-
arch/arm/dts/rk3128.dtsi | 86 ++++++++++++++++++-------------------
2 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts
index 2fb2b0da..a407ac2d 100644
--- a/arch/arm/dts/rk3128-evb.dts
+++ b/arch/arm/dts/rk3128-evb.dts
@@ -82,13 +82,13 @@
&pinctrl {
usb_otg {
otg_vbus_drv: host-vbus-drv {
- rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb_host {
host_vbus_drv: host-vbus-drv {
- rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
index 3c5f54f6..5a1c1547 100644
--- a/arch/arm/dts/rk3128.dtsi
+++ b/arch/arm/dts/rk3128.dtsi
@@ -618,85 +618,85 @@
*/
emmc_clk: emmc-clk {
- rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
};
emmc_cmd: emmc-cmd {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
emmc_pwren: emmc-pwren {
- rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>;
};
emmc_bus8: emmc-bus8 {
- rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
- <1 25 RK_FUNC_2 &pcfg_pull_none>,
- <1 26 RK_FUNC_2 &pcfg_pull_none>,
- <1 27 RK_FUNC_2 &pcfg_pull_none>,
- <1 28 RK_FUNC_2 &pcfg_pull_none>,
- <1 29 RK_FUNC_2 &pcfg_pull_none>,
- <1 30 RK_FUNC_2 &pcfg_pull_none>,
- <1 31 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
+ <1 RK_PD1 2 &pcfg_pull_none>,
+ <1 RK_PD2 2 &pcfg_pull_none>,
+ <1 RK_PD3 2 &pcfg_pull_none>,
+ <1 RK_PD4 2 &pcfg_pull_none>,
+ <1 RK_PD5 2 &pcfg_pull_none>,
+ <1 RK_PD6 2 &pcfg_pull_none>,
+ <1 RK_PD7 2 &pcfg_pull_none>;
};
};
nandc{
nandc_ale:nandc-ale {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_cle:nandc-cle {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_wrn:nandc-wrn {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_rdn:nandc-rdn {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_rdy:nandc-rdy {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_cs0:nandc-cs0 {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
nandc_data: nandc-data {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
- rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
- <0 17 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>,
+ <0 RK_PC1 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
- rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
};
uart0_rts: uart0-rts {
- rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
};
};
uart1 {
uart1_xfer: uart1-xfer {
- rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
- <2 23 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>,
+ <2 RK_PC7 1 &pcfg_pull_none>;
};
};
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
- <1 19 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>,
+ <1 RK_PC3 2 &pcfg_pull_none>;
};
};
@@ -727,75 +727,75 @@
pwm0 {
pwm0_pin: pwm0-pin {
- rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
- rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
- rockchip,pins = <0 1 2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
- rockchip,pins = <0 27 1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
- rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
- <0 1 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
+ <0 RK_PA1 1 &pcfg_pull_none>;
};
};
i2c1 {
i2c1_xfer: i2c1-xfer {
- rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
- <0 3 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
+ <0 RK_PA3 1 &pcfg_pull_none>;
};
};
i2c2 {
i2c2_xfer: i2c2-xfer {
- rockchip,pins = <2 20 3 &pcfg_pull_none>,
- <2 21 3 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
+ <2 RK_PC5 3 &pcfg_pull_none>;
};
};
i2c3 {
i2c3_xfer: i2c3-xfer {
- rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
- <0 7 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
+ <0 RK_PA7 1 &pcfg_pull_none>;
};
};
spi0 {
spi0_txd_mux0:spi0-txd-mux0 {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
spi0_rxd_mux0:spi0-rxd-mux0 {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
spi0_clk_mux0:spi0-clk-mux0 {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
spi0_cs0_mux0:spi0-cs0-mux0 {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
spi0_cs1_mux0:spi0-cs1-mux0 {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
};
};
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 3/5] arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files
[not found] <20220909200256.15981-1-jbx6244@gmail.com>
2022-09-09 20:18 ` [PATCH v3 2/5] arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts Johan Jonker
@ 2022-09-09 20:19 ` Johan Jonker
2022-09-09 20:19 ` [PATCH v3 4/5] arm: dts: rockchip: rk3128: fix DT node names Johan Jonker
2022-09-09 20:20 ` [PATCH v3 5/5] arm: dts: rockchip: rk3128: fix clocks, compatible and phys Johan Jonker
3 siblings, 0 replies; 7+ messages in thread
From: Johan Jonker @ 2022-09-09 20:19 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot
Move all rk3128 u-boot specific properties in separate dtsi files.
Sort emmc node.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
Changed V2:
Keep max-frequency property in dtsi
---
arch/arm/dts/rk3128-evb-u-boot.dtsi | 7 +++++++
arch/arm/dts/rk3128-evb.dts | 10 +++++-----
arch/arm/dts/rk3128-u-boot.dtsi | 19 +++++++++++++++++++
arch/arm/dts/rk3128.dtsi | 9 ---------
4 files changed, 31 insertions(+), 14 deletions(-)
create mode 100644 arch/arm/dts/rk3128-evb-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3128-u-boot.dtsi
diff --git a/arch/arm/dts/rk3128-evb-u-boot.dtsi b/arch/arm/dts/rk3128-evb-u-boot.dtsi
new file mode 100644
index 00000000..8b16bbe4
--- /dev/null
+++ b/arch/arm/dts/rk3128-evb-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rk3128-u-boot.dtsi"
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts
index a407ac2d..e7d8f7c9 100644
--- a/arch/arm/dts/rk3128-evb.dts
+++ b/arch/arm/dts/rk3128-evb.dts
@@ -37,6 +37,11 @@
};
};
+&emmc {
+ fifo-mode;
+ status = "okay";
+};
+
&i2c1 {
status = "okay";
@@ -74,11 +79,6 @@
status = "okay";
};
-&emmc {
- fifo-mode;
- status = "okay";
-};
-
&pinctrl {
usb_otg {
otg_vbus_drv: host-vbus-drv {
diff --git a/arch/arm/dts/rk3128-u-boot.dtsi b/arch/arm/dts/rk3128-u-boot.dtsi
new file mode 100644
index 00000000..4a98e249
--- /dev/null
+++ b/arch/arm/dts/rk3128-u-boot.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ dmc: dmc@20004000 {
+ compatible = "rockchip,rk3128-dmc", "syscon";
+ reg = <0x0 0x20004000 0x0 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
index 5a1c1547..b58804b6 100644
--- a/arch/arm/dts/rk3128.dtsi
+++ b/arch/arm/dts/rk3128.dtsi
@@ -237,14 +237,7 @@
clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
};
- dmc: dmc@20004000 {
- u-boot,dm-pre-reloc;
- compatible = "rockchip,rk3128-dmc", "syscon";
- reg = <0x0 0x20004000 0x0 0x1000>;
- };
-
cru: clock-controller@20000000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3128-cru";
reg = <0x20000000 0x1000>;
rockchip,grf = <&grf>;
@@ -453,7 +446,6 @@
};
emmc: dwmmc@1021c000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
max-frequency = <150000000>;
@@ -538,7 +530,6 @@
};
grf: syscon@20008000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3128-grf", "syscon";
reg = <0x20008000 0x1000>;
};
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 4/5] arm: dts: rockchip: rk3128: fix DT node names
[not found] <20220909200256.15981-1-jbx6244@gmail.com>
2022-09-09 20:18 ` [PATCH v3 2/5] arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts Johan Jonker
2022-09-09 20:19 ` [PATCH v3 3/5] arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files Johan Jonker
@ 2022-09-09 20:19 ` Johan Jonker
2022-09-28 13:22 ` Kever Yang
2022-09-09 20:20 ` [PATCH v3 5/5] arm: dts: rockchip: rk3128: fix clocks, compatible and phys Johan Jonker
3 siblings, 1 reply; 7+ messages in thread
From: Johan Jonker @ 2022-09-09 20:19 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot
The rk3128 DT node names should be generic.
Rename them to the pattern defined in the DT bindings.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3128-evb.dts | 5 +++
arch/arm/dts/rk3128.dtsi | 62 +++++++++++++++++--------------------
2 files changed, 33 insertions(+), 34 deletions(-)
diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts
index e7d8f7c9..93291d78 100644
--- a/arch/arm/dts/rk3128-evb.dts
+++ b/arch/arm/dts/rk3128-evb.dts
@@ -15,6 +15,11 @@
stdout-path = &uart2;
};
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
vcc5v0_otg: vcc5v0-otg-drv {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_otg";
diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
index b58804b6..48833bff 100644
--- a/arch/arm/dts/rk3128.dtsi
+++ b/arch/arm/dts/rk3128.dtsi
@@ -8,7 +8,6 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3128-cru.h>
-#include "skeleton.dtsi"
/ {
compatible = "rockchip,rk3128";
@@ -34,11 +33,6 @@
mmc1 = &sdmmc;
};
- memory {
- device_type = "memory";
- reg = <0x60000000 0x40000000>;
- };
-
arm-pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
@@ -52,10 +46,10 @@
#size-cells = <0>;
enable-method = "rockchip,rk3128-smp";
- cpu0:cpu@0x000 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
- reg = <0x000>;
+ reg = <0x0>;
operating-points = <
/* KHz uV */
816000 1000000
@@ -65,22 +59,22 @@
clocks = <&cru ARMCLK>;
};
- cpu1:cpu@0x001 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
- reg = <0x001>;
+ reg = <0x1>;
};
- cpu2:cpu@0x002 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
- reg = <0x002>;
+ reg = <0x2>;
};
- cpu3:cpu@0x003 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
- reg = <0x003>;
+ reg = <0x3>;
};
};
@@ -165,7 +159,7 @@
interrupt-parent = <&gic>;
ranges;
- pdma: pdma@20078000 {
+ pdma: dma-controller@20078000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20078000 0x4000>;
arm,pl330-broken-no-flushp;//2
@@ -207,7 +201,7 @@
rockchip,broadcast = <1>;
};
- watchdog: wdt@2004c000 {
+ watchdog: watchdog@2004c000 {
compatible = "rockchip,watch dog";
reg = <0x2004c000 0x100>;
clock-names = "pclk_wdt";
@@ -224,7 +218,7 @@
#reset-cells = <1>;
};
- nandc: nandc@10500000 {
+ nandc: nand-controller@10500000 {
compatible = "rockchip,rk-nandc";
reg = <0x10500000 0x4000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -247,7 +241,7 @@
assigned-clock-rates = <594000000>;
};
- uart0: serial0@20060000 {
+ uart0: serial@20060000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20060000 0x100>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -262,7 +256,7 @@
#dma-cells = <2>;
};
- uart1: serial1@20064000 {
+ uart1: serial@20064000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20064000 0x100>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@@ -277,7 +271,7 @@
#dma-cells = <2>;
};
- uart2: serial2@20068000 {
+ uart2: serial@20068000 {
compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
reg = <0x20068000 0x100>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -304,7 +298,7 @@
status = "disabled";
};
- pwm0: pwm0@20050000 {
+ pwm0: pwm@20050000 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <3>;
@@ -314,7 +308,7 @@
clock-names = "pwm";
};
- pwm1: pwm1@20050010 {
+ pwm1: pwm@20050010 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <3>;
@@ -324,7 +318,7 @@
clock-names = "pwm";
};
- pwm2: pwm2@20050020 {
+ pwm2: pwm@20050020 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <3>;
@@ -334,7 +328,7 @@
clock-names = "pwm";
};
- pwm3: pwm3@20050030 {
+ pwm3: pwm@20050030 {
compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
reg = <0x20050030 0x10>;
#pwm-cells = <3>;
@@ -430,7 +424,7 @@
status = "disabled";
};
- sdmmc: dwmmc@10214000 {
+ sdmmc: mmc@10214000 {
compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
max-frequency = <150000000>;
@@ -445,7 +439,7 @@
status = "disabled";
};
- emmc: dwmmc@1021c000 {
+ emmc: mmc@1021c000 {
compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
max-frequency = <150000000>;
@@ -464,7 +458,7 @@
status = "disabled";
};
- i2c0: i2c0@20072000 {
+ i2c0: i2c@20072000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <20072000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -476,7 +470,7 @@
pinctrl-0 = <&i2c0_xfer>;
};
- i2c1: i2c1@20056000 {
+ i2c1: i2c@20056000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x20056000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -488,7 +482,7 @@
pinctrl-0 = <&i2c1_xfer>;
};
- i2c2: i2c2@2005a000 {
+ i2c2: i2c@2005a000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x2005a000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -500,7 +494,7 @@
pinctrl-0 = <&i2c2_xfer>;
};
- i2c3: i2c3@2005e000 {
+ i2c3: i2c@2005e000 {
compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
reg = <0x2005e000 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
@@ -546,7 +540,7 @@
#size-cells = <1>;
ranges;
- gpio0: gpio0@2007c000 {
+ gpio0: gpio@2007c000 {
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
@@ -557,7 +551,7 @@
#interrupt-cells = <2>;
};
- gpio1: gpio1@20080000 {
+ gpio1: gpio@20080000 {
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -568,7 +562,7 @@
#interrupt-cells = <2>;
};
- gpio2: gpio2@20084000 {
+ gpio2: gpio@20084000 {
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -579,7 +573,7 @@
#interrupt-cells = <2>;
};
- gpio3: gpio2@20088000 {
+ gpio3: gpio@20088000 {
compatible = "rockchip,gpio-bank";
reg = <0x20088000 0x100>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v3 5/5] arm: dts: rockchip: rk3128: fix clocks, compatible and phys
[not found] <20220909200256.15981-1-jbx6244@gmail.com>
` (2 preceding siblings ...)
2022-09-09 20:19 ` [PATCH v3 4/5] arm: dts: rockchip: rk3128: fix DT node names Johan Jonker
@ 2022-09-09 20:20 ` Johan Jonker
3 siblings, 0 replies; 7+ messages in thread
From: Johan Jonker @ 2022-09-09 20:20 UTC (permalink / raw)
To: kever.yang; +Cc: sjg, philipp.tomsich, u-boot
Fix rk3128 clocks, compatible and phys, so that they match the bindings.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/dts/rk3128.dtsi | 46 +++++++++++++++++-----------------------
1 file changed, 19 insertions(+), 27 deletions(-)
diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
index 48833bff..3253c640 100644
--- a/arch/arm/dts/rk3128.dtsi
+++ b/arch/arm/dts/rk3128.dtsi
@@ -180,7 +180,6 @@
xin12m: xin12m {
compatible = "fixed-clock";
- clocks = <&xin24m>;
clock-frequency = <12000000>;
clock-output-names = "xin12m";
#clock-cells = <0>;
@@ -202,9 +201,9 @@
};
watchdog: watchdog@2004c000 {
- compatible = "rockchip,watch dog";
+ compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
reg = <0x2004c000 0x100>;
- clock-names = "pclk_wdt";
+ clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
rockchip,irq = <1>;
rockchip,timeout = <60>;
@@ -219,21 +218,20 @@
};
nandc: nand-controller@10500000 {
- compatible = "rockchip,rk-nandc";
+ compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
reg = <0x10500000 0x4000>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
- nandc_id = <0>;
- clocks = <&cru SCLK_NANDC>,
- <&cru HCLK_NANDC>,
- <&cru SRST_NANDC>;
- clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
};
cru: clock-controller@20000000 {
compatible = "rockchip,rk3128-cru";
reg = <0x20000000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -305,7 +303,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
};
pwm1: pwm@20050010 {
@@ -315,7 +312,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
};
pwm2: pwm@20050020 {
@@ -325,7 +321,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
};
pwm3: pwm@20050030 {
@@ -335,7 +330,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
};
sram: sram@10080400 {
@@ -364,7 +358,7 @@
interrupts = <GIC_PPI 9 0xf04>;
};
- u2phy: usb2-phy {
+ u2phy: usb2phy {
compatible = "rockchip,rk3128-usb2phy";
reg = <0x017c 0x0c>;
rockchip,grf = <&grf>;
@@ -372,7 +366,6 @@
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "usb480m_phy";
- #phy-cells = <1>;
status = "disabled";
u2phy_otg: otg-port {
@@ -394,15 +387,14 @@
};
usb_otg: usb@10180000 {
- compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
- "snps,dwc2";
+ compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
reg = <0x10180000 0x40000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
dr_mode = "otg";
- g-use-dma;
- hnp-srp-disable;
- phys = <&u2phy 0>;
- phy-names = "usb";
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
status = "disabled";
};
@@ -410,7 +402,7 @@
compatible = "generic-ehci";
reg = <0x101c0000 0x20000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&u2phy 1>;
+ phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
};
@@ -419,19 +411,19 @@
compatible = "generic-ohci";
reg = <0x101e0000 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&u2phy 1>;
+ phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
};
sdmmc: mmc@10214000 {
- compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
+ compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10214000 0x4000>;
max-frequency = <150000000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
@@ -446,7 +438,7 @@
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
bus-width = <8>;
default-sample-phase = <158>;
num-slots = <1>;
@@ -507,7 +499,7 @@
};
spi0: spi@20074000 {
- compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
+ compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
reg = <0x20074000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
--
2.20.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3 2/5] arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts
2022-09-09 20:18 ` [PATCH v3 2/5] arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts Johan Jonker
@ 2022-09-28 13:16 ` Kever Yang
0 siblings, 0 replies; 7+ messages in thread
From: Kever Yang @ 2022-09-28 13:16 UTC (permalink / raw)
To: Johan Jonker; +Cc: sjg, philipp.tomsich, u-boot
On 2022/9/10 04:18, Johan Jonker wrote:
> Bulk convert rk3128 DT gpios to their constant counterparts.
>
> sed -i -f script.sed rk3128.dtsi
> sed -i -f script.sed rk3128-evb.dts
>
> ================================
>
> /rockchip,pins *=/bcheck
> b # to end of script
> :append-next-line
> N
> :check
> /^[^;]*$/bappend-next-line
> s/<RK_GPIO\([0-9]\) /<\1 /g
> s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g
> s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g
> s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g
> s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g
> s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g
> s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g
> s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g
> s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g
> s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g
> s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g
> s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g
> s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g
> s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g
> s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g
> s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g
> s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g
> s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g
> s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g
> s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g
> s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g
> s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g
> s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g
> s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g
> s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g
> s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g
> s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g
> s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g
> s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g
> s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g
> s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g
> s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g
> s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g
> s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g
> s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/rk3128-evb.dts | 4 +-
> arch/arm/dts/rk3128.dtsi | 86 ++++++++++++++++++-------------------
> 2 files changed, 45 insertions(+), 45 deletions(-)
>
> diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts
> index 2fb2b0da..a407ac2d 100644
> --- a/arch/arm/dts/rk3128-evb.dts
> +++ b/arch/arm/dts/rk3128-evb.dts
> @@ -82,13 +82,13 @@
> &pinctrl {
> usb_otg {
> otg_vbus_drv: host-vbus-drv {
> - rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
>
> usb_host {
> host_vbus_drv: host-vbus-drv {
> - rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
> };
> };
> };
> diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
> index 3c5f54f6..5a1c1547 100644
> --- a/arch/arm/dts/rk3128.dtsi
> +++ b/arch/arm/dts/rk3128.dtsi
> @@ -618,85 +618,85 @@
> */
>
> emmc_clk: emmc-clk {
> - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
> };
>
> emmc_cmd: emmc-cmd {
> - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
> };
>
> emmc_pwren: emmc-pwren {
> - rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>;
> };
>
> emmc_bus8: emmc-bus8 {
> - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
> - <1 25 RK_FUNC_2 &pcfg_pull_none>,
> - <1 26 RK_FUNC_2 &pcfg_pull_none>,
> - <1 27 RK_FUNC_2 &pcfg_pull_none>,
> - <1 28 RK_FUNC_2 &pcfg_pull_none>,
> - <1 29 RK_FUNC_2 &pcfg_pull_none>,
> - <1 30 RK_FUNC_2 &pcfg_pull_none>,
> - <1 31 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
> + <1 RK_PD1 2 &pcfg_pull_none>,
> + <1 RK_PD2 2 &pcfg_pull_none>,
> + <1 RK_PD3 2 &pcfg_pull_none>,
> + <1 RK_PD4 2 &pcfg_pull_none>,
> + <1 RK_PD5 2 &pcfg_pull_none>,
> + <1 RK_PD6 2 &pcfg_pull_none>,
> + <1 RK_PD7 2 &pcfg_pull_none>;
> };
> };
>
> nandc{
> nandc_ale:nandc-ale {
> - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
> };
>
> nandc_cle:nandc-cle {
> - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
> };
>
> nandc_wrn:nandc-wrn {
> - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
> };
>
> nandc_rdn:nandc-rdn {
> - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
> };
>
> nandc_rdy:nandc-rdy {
> - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
> };
>
> nandc_cs0:nandc-cs0 {
> - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
> };
>
> nandc_data: nandc-data {
> - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
> };
> };
>
> uart0 {
> uart0_xfer: uart0-xfer {
> - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
> - <0 17 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>,
> + <0 RK_PC1 1 &pcfg_pull_none>;
> };
>
> uart0_cts: uart0-cts {
> - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>;
> };
>
> uart0_rts: uart0-rts {
> - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
> };
> };
>
> uart1 {
> uart1_xfer: uart1-xfer {
> - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
> - <2 23 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>,
> + <2 RK_PC7 1 &pcfg_pull_none>;
> };
> };
>
> uart2 {
> uart2_xfer: uart2-xfer {
> - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
> - <1 19 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>,
> + <1 RK_PC3 2 &pcfg_pull_none>;
> };
> };
>
> @@ -727,75 +727,75 @@
>
> pwm0 {
> pwm0_pin: pwm0-pin {
> - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
> };
> };
>
> pwm1 {
> pwm1_pin: pwm1-pin {
> - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
> };
> };
>
> pwm2 {
> pwm2_pin: pwm2-pin {
> - rockchip,pins = <0 1 2 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
> };
> };
>
> pwm3 {
> pwm3_pin: pwm3-pin {
> - rockchip,pins = <0 27 1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
> };
> };
>
> i2c0 {
> i2c0_xfer: i2c0-xfer {
> - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
> - <0 1 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
> + <0 RK_PA1 1 &pcfg_pull_none>;
> };
> };
>
> i2c1 {
> i2c1_xfer: i2c1-xfer {
> - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
> - <0 3 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
> + <0 RK_PA3 1 &pcfg_pull_none>;
> };
> };
>
> i2c2 {
> i2c2_xfer: i2c2-xfer {
> - rockchip,pins = <2 20 3 &pcfg_pull_none>,
> - <2 21 3 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
> + <2 RK_PC5 3 &pcfg_pull_none>;
> };
> };
>
> i2c3 {
> i2c3_xfer: i2c3-xfer {
> - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
> - <0 7 RK_FUNC_1 &pcfg_pull_none>;
> + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
> + <0 RK_PA7 1 &pcfg_pull_none>;
> };
> };
>
> spi0 {
> spi0_txd_mux0:spi0-txd-mux0 {
> - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
> };
>
> spi0_rxd_mux0:spi0-rxd-mux0 {
> - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
> };
>
> spi0_clk_mux0:spi0-clk-mux0 {
> - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
> };
>
> spi0_cs0_mux0:spi0-cs0-mux0 {
> - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
> };
>
> spi0_cs1_mux0:spi0-cs1-mux0 {
> - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
> + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
> };
> };
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 4/5] arm: dts: rockchip: rk3128: fix DT node names
2022-09-09 20:19 ` [PATCH v3 4/5] arm: dts: rockchip: rk3128: fix DT node names Johan Jonker
@ 2022-09-28 13:22 ` Kever Yang
2022-09-28 13:39 ` Johan Jonker
0 siblings, 1 reply; 7+ messages in thread
From: Kever Yang @ 2022-09-28 13:22 UTC (permalink / raw)
To: Johan Jonker; +Cc: sjg, philipp.tomsich, u-boot
Hi Johan,
I think it would be good to sync to kernel dts as you have done for
other SoCs,
but not only change the dts separately,
Thansk,
- Kever
On 2022/9/10 04:19, Johan Jonker wrote:
> The rk3128 DT node names should be generic.
> Rename them to the pattern defined in the DT bindings.
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> arch/arm/dts/rk3128-evb.dts | 5 +++
> arch/arm/dts/rk3128.dtsi | 62 +++++++++++++++++--------------------
> 2 files changed, 33 insertions(+), 34 deletions(-)
>
> diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts
> index e7d8f7c9..93291d78 100644
> --- a/arch/arm/dts/rk3128-evb.dts
> +++ b/arch/arm/dts/rk3128-evb.dts
> @@ -15,6 +15,11 @@
> stdout-path = &uart2;
> };
>
> + memory@60000000 {
> + device_type = "memory";
> + reg = <0x60000000 0x40000000>;
> + };
> +
> vcc5v0_otg: vcc5v0-otg-drv {
> compatible = "regulator-fixed";
> regulator-name = "vcc5v0_otg";
> diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
> index b58804b6..48833bff 100644
> --- a/arch/arm/dts/rk3128.dtsi
> +++ b/arch/arm/dts/rk3128.dtsi
> @@ -8,7 +8,6 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> #include <dt-bindings/clock/rk3128-cru.h>
> -#include "skeleton.dtsi"
>
> / {
> compatible = "rockchip,rk3128";
> @@ -34,11 +33,6 @@
> mmc1 = &sdmmc;
> };
>
> - memory {
> - device_type = "memory";
> - reg = <0x60000000 0x40000000>;
> - };
> -
> arm-pmu {
> compatible = "arm,cortex-a7-pmu";
> interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> @@ -52,10 +46,10 @@
> #size-cells = <0>;
> enable-method = "rockchip,rk3128-smp";
>
> - cpu0:cpu@0x000 {
> + cpu0: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> - reg = <0x000>;
> + reg = <0x0>;
> operating-points = <
> /* KHz uV */
> 816000 1000000
> @@ -65,22 +59,22 @@
> clocks = <&cru ARMCLK>;
> };
>
> - cpu1:cpu@0x001 {
> + cpu1: cpu@1 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> - reg = <0x001>;
> + reg = <0x1>;
> };
>
> - cpu2:cpu@0x002 {
> + cpu2: cpu@2 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> - reg = <0x002>;
> + reg = <0x2>;
> };
>
> - cpu3:cpu@0x003 {
> + cpu3: cpu@3 {
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> - reg = <0x003>;
> + reg = <0x3>;
> };
> };
>
> @@ -165,7 +159,7 @@
> interrupt-parent = <&gic>;
> ranges;
>
> - pdma: pdma@20078000 {
> + pdma: dma-controller@20078000 {
> compatible = "arm,pl330", "arm,primecell";
> reg = <0x20078000 0x4000>;
> arm,pl330-broken-no-flushp;//2
> @@ -207,7 +201,7 @@
> rockchip,broadcast = <1>;
> };
>
> - watchdog: wdt@2004c000 {
> + watchdog: watchdog@2004c000 {
> compatible = "rockchip,watch dog";
> reg = <0x2004c000 0x100>;
> clock-names = "pclk_wdt";
> @@ -224,7 +218,7 @@
> #reset-cells = <1>;
> };
>
> - nandc: nandc@10500000 {
> + nandc: nand-controller@10500000 {
> compatible = "rockchip,rk-nandc";
> reg = <0x10500000 0x4000>;
> interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> @@ -247,7 +241,7 @@
> assigned-clock-rates = <594000000>;
> };
>
> - uart0: serial0@20060000 {
> + uart0: serial@20060000 {
> compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
> reg = <0x20060000 0x100>;
> interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> @@ -262,7 +256,7 @@
> #dma-cells = <2>;
> };
>
> - uart1: serial1@20064000 {
> + uart1: serial@20064000 {
> compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
> reg = <0x20064000 0x100>;
> interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> @@ -277,7 +271,7 @@
> #dma-cells = <2>;
> };
>
> - uart2: serial2@20068000 {
> + uart2: serial@20068000 {
> compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
> reg = <0x20068000 0x100>;
> interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> @@ -304,7 +298,7 @@
> status = "disabled";
> };
>
> - pwm0: pwm0@20050000 {
> + pwm0: pwm@20050000 {
> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
> reg = <0x20050000 0x10>;
> #pwm-cells = <3>;
> @@ -314,7 +308,7 @@
> clock-names = "pwm";
> };
>
> - pwm1: pwm1@20050010 {
> + pwm1: pwm@20050010 {
> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
> reg = <0x20050010 0x10>;
> #pwm-cells = <3>;
> @@ -324,7 +318,7 @@
> clock-names = "pwm";
> };
>
> - pwm2: pwm2@20050020 {
> + pwm2: pwm@20050020 {
> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
> reg = <0x20050020 0x10>;
> #pwm-cells = <3>;
> @@ -334,7 +328,7 @@
> clock-names = "pwm";
> };
>
> - pwm3: pwm3@20050030 {
> + pwm3: pwm@20050030 {
> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
> reg = <0x20050030 0x10>;
> #pwm-cells = <3>;
> @@ -430,7 +424,7 @@
> status = "disabled";
> };
>
> - sdmmc: dwmmc@10214000 {
> + sdmmc: mmc@10214000 {
> compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x10214000 0x4000>;
> max-frequency = <150000000>;
> @@ -445,7 +439,7 @@
> status = "disabled";
> };
>
> - emmc: dwmmc@1021c000 {
> + emmc: mmc@1021c000 {
> compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
> reg = <0x1021c000 0x4000>;
> max-frequency = <150000000>;
> @@ -464,7 +458,7 @@
> status = "disabled";
> };
>
> - i2c0: i2c0@20072000 {
> + i2c0: i2c@20072000 {
> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
> reg = <20072000 0x1000>;
> interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> @@ -476,7 +470,7 @@
> pinctrl-0 = <&i2c0_xfer>;
> };
>
> - i2c1: i2c1@20056000 {
> + i2c1: i2c@20056000 {
> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
> reg = <0x20056000 0x1000>;
> interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> @@ -488,7 +482,7 @@
> pinctrl-0 = <&i2c1_xfer>;
> };
>
> - i2c2: i2c2@2005a000 {
> + i2c2: i2c@2005a000 {
> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
> reg = <0x2005a000 0x1000>;
> interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> @@ -500,7 +494,7 @@
> pinctrl-0 = <&i2c2_xfer>;
> };
>
> - i2c3: i2c3@2005e000 {
> + i2c3: i2c@2005e000 {
> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
> reg = <0x2005e000 0x1000>;
> interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> @@ -546,7 +540,7 @@
> #size-cells = <1>;
> ranges;
>
> - gpio0: gpio0@2007c000 {
> + gpio0: gpio@2007c000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x2007c000 0x100>;
> interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> @@ -557,7 +551,7 @@
> #interrupt-cells = <2>;
> };
>
> - gpio1: gpio1@20080000 {
> + gpio1: gpio@20080000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x20080000 0x100>;
> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> @@ -568,7 +562,7 @@
> #interrupt-cells = <2>;
> };
>
> - gpio2: gpio2@20084000 {
> + gpio2: gpio@20084000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x20084000 0x100>;
> interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> @@ -579,7 +573,7 @@
> #interrupt-cells = <2>;
> };
>
> - gpio3: gpio2@20088000 {
> + gpio3: gpio@20088000 {
> compatible = "rockchip,gpio-bank";
> reg = <0x20088000 0x100>;
> interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 4/5] arm: dts: rockchip: rk3128: fix DT node names
2022-09-28 13:22 ` Kever Yang
@ 2022-09-28 13:39 ` Johan Jonker
0 siblings, 0 replies; 7+ messages in thread
From: Johan Jonker @ 2022-09-28 13:39 UTC (permalink / raw)
To: Kever Yang; +Cc: sjg, philipp.tomsich, u-boot
Hi,
There's no kernel rk3128.dtsi
Submitting can better be done by someone with hardware.
There are known hardware boards:
rk3128-evb
Firefly-RK3128
For the rk3128-evb I might produce something, but someone from Rockchip has to give a "Tested-by:" and a quick respons if changes needed or submit it themself.
Recent *-pinctrl .dtsi files were generated with a unknown pin2dts tool. Un able that generate that format, only existing.
Compatible strings are all acked by rob+dt, except for qos nodes (TODO) and board string (TODO).
Let me know what you prefer.
Johan
On 9/28/22 15:22, Kever Yang wrote:
> Hi Johan,
>
> I think it would be good to sync to kernel dts as you have done for other SoCs,
>
> but not only change the dts separately,
>
> Thansk,
>
> - Kever
>
> On 2022/9/10 04:19, Johan Jonker wrote:
>> The rk3128 DT node names should be generic.
>> Rename them to the pattern defined in the DT bindings.
>>
>> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
>> ---
>> arch/arm/dts/rk3128-evb.dts | 5 +++
>> arch/arm/dts/rk3128.dtsi | 62 +++++++++++++++++--------------------
>> 2 files changed, 33 insertions(+), 34 deletions(-)
>>
>> diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts
>> index e7d8f7c9..93291d78 100644
>> --- a/arch/arm/dts/rk3128-evb.dts
>> +++ b/arch/arm/dts/rk3128-evb.dts
>> @@ -15,6 +15,11 @@
>> stdout-path = &uart2;
>> };
>> + memory@60000000 {
>> + device_type = "memory";
>> + reg = <0x60000000 0x40000000>;
>> + };
>> +
>> vcc5v0_otg: vcc5v0-otg-drv {
>> compatible = "regulator-fixed";
>> regulator-name = "vcc5v0_otg";
>> diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi
>> index b58804b6..48833bff 100644
>> --- a/arch/arm/dts/rk3128.dtsi
>> +++ b/arch/arm/dts/rk3128.dtsi
>> @@ -8,7 +8,6 @@
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/pinctrl/rockchip.h>
>> #include <dt-bindings/clock/rk3128-cru.h>
>> -#include "skeleton.dtsi"
>> / {
>> compatible = "rockchip,rk3128";
>> @@ -34,11 +33,6 @@
>> mmc1 = &sdmmc;
>> };
>> - memory {
>> - device_type = "memory";
>> - reg = <0x60000000 0x40000000>;
>> - };
>> -
>> arm-pmu {
>> compatible = "arm,cortex-a7-pmu";
>> interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
>> @@ -52,10 +46,10 @@
>> #size-cells = <0>;
>> enable-method = "rockchip,rk3128-smp";
>> - cpu0:cpu@0x000 {
>> + cpu0: cpu@0 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a7";
>> - reg = <0x000>;
>> + reg = <0x0>;
>> operating-points = <
>> /* KHz uV */
>> 816000 1000000
>> @@ -65,22 +59,22 @@
>> clocks = <&cru ARMCLK>;
>> };
>> - cpu1:cpu@0x001 {
>> + cpu1: cpu@1 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a7";
>> - reg = <0x001>;
>> + reg = <0x1>;
>> };
>> - cpu2:cpu@0x002 {
>> + cpu2: cpu@2 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a7";
>> - reg = <0x002>;
>> + reg = <0x2>;
>> };
>> - cpu3:cpu@0x003 {
>> + cpu3: cpu@3 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a7";
>> - reg = <0x003>;
>> + reg = <0x3>;
>> };
>> };
>> @@ -165,7 +159,7 @@
>> interrupt-parent = <&gic>;
>> ranges;
>> - pdma: pdma@20078000 {
>> + pdma: dma-controller@20078000 {
>> compatible = "arm,pl330", "arm,primecell";
>> reg = <0x20078000 0x4000>;
>> arm,pl330-broken-no-flushp;//2
>> @@ -207,7 +201,7 @@
>> rockchip,broadcast = <1>;
>> };
>> - watchdog: wdt@2004c000 {
>> + watchdog: watchdog@2004c000 {
>> compatible = "rockchip,watch dog";
>> reg = <0x2004c000 0x100>;
>> clock-names = "pclk_wdt";
>> @@ -224,7 +218,7 @@
>> #reset-cells = <1>;
>> };
>> - nandc: nandc@10500000 {
>> + nandc: nand-controller@10500000 {
>> compatible = "rockchip,rk-nandc";
>> reg = <0x10500000 0x4000>;
>> interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -247,7 +241,7 @@
>> assigned-clock-rates = <594000000>;
>> };
>> - uart0: serial0@20060000 {
>> + uart0: serial@20060000 {
>> compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
>> reg = <0x20060000 0x100>;
>> interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -262,7 +256,7 @@
>> #dma-cells = <2>;
>> };
>> - uart1: serial1@20064000 {
>> + uart1: serial@20064000 {
>> compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
>> reg = <0x20064000 0x100>;
>> interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -277,7 +271,7 @@
>> #dma-cells = <2>;
>> };
>> - uart2: serial2@20068000 {
>> + uart2: serial@20068000 {
>> compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
>> reg = <0x20068000 0x100>;
>> interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -304,7 +298,7 @@
>> status = "disabled";
>> };
>> - pwm0: pwm0@20050000 {
>> + pwm0: pwm@20050000 {
>> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
>> reg = <0x20050000 0x10>;
>> #pwm-cells = <3>;
>> @@ -314,7 +308,7 @@
>> clock-names = "pwm";
>> };
>> - pwm1: pwm1@20050010 {
>> + pwm1: pwm@20050010 {
>> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
>> reg = <0x20050010 0x10>;
>> #pwm-cells = <3>;
>> @@ -324,7 +318,7 @@
>> clock-names = "pwm";
>> };
>> - pwm2: pwm2@20050020 {
>> + pwm2: pwm@20050020 {
>> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
>> reg = <0x20050020 0x10>;
>> #pwm-cells = <3>;
>> @@ -334,7 +328,7 @@
>> clock-names = "pwm";
>> };
>> - pwm3: pwm3@20050030 {
>> + pwm3: pwm@20050030 {
>> compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
>> reg = <0x20050030 0x10>;
>> #pwm-cells = <3>;
>> @@ -430,7 +424,7 @@
>> status = "disabled";
>> };
>> - sdmmc: dwmmc@10214000 {
>> + sdmmc: mmc@10214000 {
>> compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
>> reg = <0x10214000 0x4000>;
>> max-frequency = <150000000>;
>> @@ -445,7 +439,7 @@
>> status = "disabled";
>> };
>> - emmc: dwmmc@1021c000 {
>> + emmc: mmc@1021c000 {
>> compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
>> reg = <0x1021c000 0x4000>;
>> max-frequency = <150000000>;
>> @@ -464,7 +458,7 @@
>> status = "disabled";
>> };
>> - i2c0: i2c0@20072000 {
>> + i2c0: i2c@20072000 {
>> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
>> reg = <20072000 0x1000>;
>> interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -476,7 +470,7 @@
>> pinctrl-0 = <&i2c0_xfer>;
>> };
>> - i2c1: i2c1@20056000 {
>> + i2c1: i2c@20056000 {
>> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
>> reg = <0x20056000 0x1000>;
>> interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -488,7 +482,7 @@
>> pinctrl-0 = <&i2c1_xfer>;
>> };
>> - i2c2: i2c2@2005a000 {
>> + i2c2: i2c@2005a000 {
>> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
>> reg = <0x2005a000 0x1000>;
>> interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -500,7 +494,7 @@
>> pinctrl-0 = <&i2c2_xfer>;
>> };
>> - i2c3: i2c3@2005e000 {
>> + i2c3: i2c@2005e000 {
>> compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
>> reg = <0x2005e000 0x1000>;
>> interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -546,7 +540,7 @@
>> #size-cells = <1>;
>> ranges;
>> - gpio0: gpio0@2007c000 {
>> + gpio0: gpio@2007c000 {
>> compatible = "rockchip,gpio-bank";
>> reg = <0x2007c000 0x100>;
>> interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -557,7 +551,7 @@
>> #interrupt-cells = <2>;
>> };
>> - gpio1: gpio1@20080000 {
>> + gpio1: gpio@20080000 {
>> compatible = "rockchip,gpio-bank";
>> reg = <0x20080000 0x100>;
>> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -568,7 +562,7 @@
>> #interrupt-cells = <2>;
>> };
>> - gpio2: gpio2@20084000 {
>> + gpio2: gpio@20084000 {
>> compatible = "rockchip,gpio-bank";
>> reg = <0x20084000 0x100>;
>> interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -579,7 +573,7 @@
>> #interrupt-cells = <2>;
>> };
>> - gpio3: gpio2@20088000 {
>> + gpio3: gpio@20088000 {
>> compatible = "rockchip,gpio-bank";
>> reg = <0x20088000 0x100>;
>> interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-09-28 13:39 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20220909200256.15981-1-jbx6244@gmail.com>
2022-09-09 20:18 ` [PATCH v3 2/5] arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts Johan Jonker
2022-09-28 13:16 ` Kever Yang
2022-09-09 20:19 ` [PATCH v3 3/5] arm: dts: rockchip: move all rk3128 u-boot specific properties in separate dtsi files Johan Jonker
2022-09-09 20:19 ` [PATCH v3 4/5] arm: dts: rockchip: rk3128: fix DT node names Johan Jonker
2022-09-28 13:22 ` Kever Yang
2022-09-28 13:39 ` Johan Jonker
2022-09-09 20:20 ` [PATCH v3 5/5] arm: dts: rockchip: rk3128: fix clocks, compatible and phys Johan Jonker
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