[PATCH 0/3] ARM: da850: new drivers for better LCDC support

[PATCH 0/3] ARM: da850: new drivers for better LCDC support

[Bartosz Golaszewski]

This series adds two new drivers in order to better support the LCDC
rev1 present on the da850 boards.

The first patch adds a new memory driver which allows to write to the
DDR2/mDDR memory controller present on the da8xx SoCs.

The second patch adds a new bus driver which allows to interact with
the SYSCFG module of da8xx SoCs.

Both drivers are incomplete - they currently only implement the
functionalities required to correctly support the LCDC on da850
boards. The first driver only allows to specify the value of the PBBP
register, while the second allows to modify all master peripheral
priorities, but doesn't know about other syscfg registers yet.

Potential extensions of these drivers should be straightforward in the
future.

The last patch adds disabled nodes for the above drivers to da850.dtsi.

Tested on a da850-lcdk with a display connected over VGA.

Bartosz Golaszewski (3):
  ARM: memory: da8xx-ddrctl: new driver
  ARM: bus: da8xx-syscfg: new driver
  ARM: dts: da850: add the syscfg and ddrctl nodes

 .../devicetree/bindings/bus/ti,da850-syscfg.txt    |  63 +++++++
 .../memory-controllers/ti-da8xx-ddrctl.txt         |  25 +++
 arch/arm/boot/dts/da850.dtsi                       |  10 +
 drivers/bus/Kconfig                                |   8 +
 drivers/bus/Makefile                               |   2 +
 drivers/bus/da8xx-syscfg.c                         | 206 +++++++++++++++++++++
 drivers/memory/Kconfig                             |   8 +
 drivers/memory/Makefile                            |   1 +
 drivers/memory/da8xx-ddrctl.c                      |  77 ++++++++
 9 files changed, 400 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
 create mode 100644 drivers/bus/da8xx-syscfg.c
 create mode 100644 drivers/memory/da8xx-ddrctl.c

-- 
2.9.3

[PATCH 0/3] ARM: da850: new drivers for better LCDC support

[Bartosz Golaszewski]

This series adds two new drivers in order to better support the LCDC
rev1 present on the da850 boards.

The first patch adds a new memory driver which allows to write to the
DDR2/mDDR memory controller present on the da8xx SoCs.

The second patch adds a new bus driver which allows to interact with
the SYSCFG module of da8xx SoCs.

Both drivers are incomplete - they currently only implement the
functionalities required to correctly support the LCDC on da850
boards. The first driver only allows to specify the value of the PBBP
register, while the second allows to modify all master peripheral
priorities, but doesn't know about other syscfg registers yet.

Potential extensions of these drivers should be straightforward in the
future.

The last patch adds disabled nodes for the above drivers to da850.dtsi.

Tested on a da850-lcdk with a display connected over VGA.

Bartosz Golaszewski (3):
  ARM: memory: da8xx-ddrctl: new driver
  ARM: bus: da8xx-syscfg: new driver
  ARM: dts: da850: add the syscfg and ddrctl nodes

 .../devicetree/bindings/bus/ti,da850-syscfg.txt    |  63 +++++++
 .../memory-controllers/ti-da8xx-ddrctl.txt         |  25 +++
 arch/arm/boot/dts/da850.dtsi                       |  10 +
 drivers/bus/Kconfig                                |   8 +
 drivers/bus/Makefile                               |   2 +
 drivers/bus/da8xx-syscfg.c                         | 206 +++++++++++++++++++++
 drivers/memory/Kconfig                             |   8 +
 drivers/memory/Makefile                            |   1 +
 drivers/memory/da8xx-ddrctl.c                      |  77 ++++++++
 9 files changed, 400 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
 create mode 100644 drivers/bus/da8xx-syscfg.c
 create mode 100644 drivers/memory/da8xx-ddrctl.c

-- 
2.9.3

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[PATCH 0/3] ARM: da850: new drivers for better LCDC support

[Bartosz Golaszewski]

This series adds two new drivers in order to better support the LCDC
rev1 present on the da850 boards.

The first patch adds a new memory driver which allows to write to the
DDR2/mDDR memory controller present on the da8xx SoCs.

The second patch adds a new bus driver which allows to interact with
the SYSCFG module of da8xx SoCs.

Both drivers are incomplete - they currently only implement the
functionalities required to correctly support the LCDC on da850
boards. The first driver only allows to specify the value of the PBBP
register, while the second allows to modify all master peripheral
priorities, but doesn't know about other syscfg registers yet.

Potential extensions of these drivers should be straightforward in the
future.

The last patch adds disabled nodes for the above drivers to da850.dtsi.

Tested on a da850-lcdk with a display connected over VGA.

Bartosz Golaszewski (3):
  ARM: memory: da8xx-ddrctl: new driver
  ARM: bus: da8xx-syscfg: new driver
  ARM: dts: da850: add the syscfg and ddrctl nodes

 .../devicetree/bindings/bus/ti,da850-syscfg.txt    |  63 +++++++
 .../memory-controllers/ti-da8xx-ddrctl.txt         |  25 +++
 arch/arm/boot/dts/da850.dtsi                       |  10 +
 drivers/bus/Kconfig                                |   8 +
 drivers/bus/Makefile                               |   2 +
 drivers/bus/da8xx-syscfg.c                         | 206 +++++++++++++++++++++
 drivers/memory/Kconfig                             |   8 +
 drivers/memory/Makefile                            |   1 +
 drivers/memory/da8xx-ddrctl.c                      |  77 ++++++++
 9 files changed, 400 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
 create mode 100644 drivers/bus/da8xx-syscfg.c
 create mode 100644 drivers/memory/da8xx-ddrctl.c

-- 
2.9.3

[PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver

[Bartosz Golaszewski]

Create a new driver for the da8xx DDR2/mDDR controller and implement
support for writing to the Peripheral Bus Burst Priority Register.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 .../memory-controllers/ti-da8xx-ddrctl.txt         | 25 +++++++
 drivers/memory/Kconfig                             |  8 +++
 drivers/memory/Makefile                            |  1 +
 drivers/memory/da8xx-ddrctl.c                      | 77 ++++++++++++++++++++++
 4 files changed, 111 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
 create mode 100644 drivers/memory/da8xx-ddrctl.c

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
new file mode 100644
index 0000000..e340404
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
@@ -0,0 +1,25 @@
+* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller
+
+The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs memory
+maps a set of registers which allow to tweak the controller's behavior.
+
+Documentation:
+OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
+
+Required properties:
+
+- compatible:		"ti,da850-ddrctl"
+
+Optional properties:
+
+- ti,pr-old-count:	Priority raise old counter. Specifies the number of
+			memory transfers after which the DDR2/mDDR memory
+			controller will elevate the priority of the oldest
+			command in the command FIFO. Must be between 0-255.
+
+Example for da850 shown below.
+
+ddrctl {
+	compatible = "ti,da850-ddrctl";
+	ti,pr-old-count = <0x20>;
+};
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 4b4c0c3..ec80e35 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -134,6 +134,14 @@ config MTK_SMI
 	  mainly help enable/disable iommu and control the power domain and
 	  clocks for each local arbiter.
 
+config DA8XX_DDRCTL
+	bool "Texas Instruments da8xx DDR2/mDDR driver"
+	depends on ARCH_DAVINCI_DA8XX
+	help
+	  This driver is for the DDR2/mDDR Memory Controller present on
+	  Texas Instruments da8xx SoCs. It's used to tweak various memory
+	  controller configuration options.
+
 source "drivers/memory/samsung/Kconfig"
 source "drivers/memory/tegra/Kconfig"
 
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index b20ae38..e88097fb 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_MVEBU_DEVBUS)	+= mvebu-devbus.o
 obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
 obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
 obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
+obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
 
 obj-$(CONFIG_SAMSUNG_MC)	+= samsung/
 obj-$(CONFIG_TEGRA_MC)		+= tegra/
diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
new file mode 100644
index 0000000..dcd0a61
--- /dev/null
+++ b/drivers/memory/da8xx-ddrctl.c
@@ -0,0 +1,77 @@
+/*
+ * TI da8xx DDR2/mDDR controller driver
+ *
+ * Copyright (C) 2016 BayLibre SAS
+ *
+ * Author:
+ *   Bartosz Golaszewski <bgolaszewski@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#define DA8XX_DDR_CTL_BASE	0xB0000000
+#define DA8XX_PBBPR_OFFSET	0x00000020
+#define DA8XX_PBBPR_REG(p)	((p) + DA8XX_PBBPR_OFFSET)
+
+#define DA8XX_PBBPR_MAX		0xff
+
+static void da8xx_ddrctl_set_pbbpr(void __iomem *ddrctl, struct device *dev)
+{
+	struct device_node *node = dev->of_node;
+	u32 pr_old_count;
+	int ret;
+
+	ret = of_property_read_u32(node, "ti,pr-old-count", &pr_old_count);
+	if (ret)
+		return;
+
+	if (pr_old_count > DA8XX_PBBPR_MAX) {
+		dev_warn(dev, "priority raise old counter value too high\n");
+		return;
+	}
+
+	__raw_writel(pr_old_count, DA8XX_PBBPR_REG(ddrctl));
+}
+
+static int da8xx_ddrctl_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *ddrctl;
+
+	ddrctl = ioremap(DA8XX_DDR_CTL_BASE, SZ_256);
+	if (!ddrctl) {
+		dev_err(dev, "unable to map memory controller registers\n");
+		return -EIO;
+	}
+
+	da8xx_ddrctl_set_pbbpr(ddrctl, dev);
+
+	iounmap(ddrctl);
+
+	return 0;
+}
+
+static const struct of_device_id da8xx_ddrctl_of_match[] = {
+	{ .compatible = "ti,da850-ddrctl", },
+	{ },
+};
+
+static struct platform_driver da8xx_ddrctl_driver = {
+	.probe = da8xx_ddrctl_probe,
+	.driver = {
+		.name = "da8xx-ddrctl",
+		.of_match_table = da8xx_ddrctl_of_match,
+	},
+};
+module_platform_driver(da8xx_ddrctl_driver);
+
+MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
+MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
+MODULE_LICENSE("GPL v2");
-- 
2.9.3

[PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver

[Bartosz Golaszewski]

Create a new driver for the da8xx DDR2/mDDR controller and implement
support for writing to the Peripheral Bus Burst Priority Register.

Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 .../memory-controllers/ti-da8xx-ddrctl.txt         | 25 +++++++
 drivers/memory/Kconfig                             |  8 +++
 drivers/memory/Makefile                            |  1 +
 drivers/memory/da8xx-ddrctl.c                      | 77 ++++++++++++++++++++++
 4 files changed, 111 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
 create mode 100644 drivers/memory/da8xx-ddrctl.c

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
new file mode 100644
index 0000000..e340404
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
@@ -0,0 +1,25 @@
+* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller
+
+The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs memory
+maps a set of registers which allow to tweak the controller's behavior.
+
+Documentation:
+OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
+
+Required properties:
+
+- compatible:		"ti,da850-ddrctl"
+
+Optional properties:
+
+- ti,pr-old-count:	Priority raise old counter. Specifies the number of
+			memory transfers after which the DDR2/mDDR memory
+			controller will elevate the priority of the oldest
+			command in the command FIFO. Must be between 0-255.
+
+Example for da850 shown below.
+
+ddrctl {
+	compatible = "ti,da850-ddrctl";
+	ti,pr-old-count = <0x20>;
+};
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 4b4c0c3..ec80e35 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -134,6 +134,14 @@ config MTK_SMI
 	  mainly help enable/disable iommu and control the power domain and
 	  clocks for each local arbiter.
 
+config DA8XX_DDRCTL
+	bool "Texas Instruments da8xx DDR2/mDDR driver"
+	depends on ARCH_DAVINCI_DA8XX
+	help
+	  This driver is for the DDR2/mDDR Memory Controller present on
+	  Texas Instruments da8xx SoCs. It's used to tweak various memory
+	  controller configuration options.
+
 source "drivers/memory/samsung/Kconfig"
 source "drivers/memory/tegra/Kconfig"
 
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index b20ae38..e88097fb 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_MVEBU_DEVBUS)	+= mvebu-devbus.o
 obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
 obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
 obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
+obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
 
 obj-$(CONFIG_SAMSUNG_MC)	+= samsung/
 obj-$(CONFIG_TEGRA_MC)		+= tegra/
diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
new file mode 100644
index 0000000..dcd0a61
--- /dev/null
+++ b/drivers/memory/da8xx-ddrctl.c
@@ -0,0 +1,77 @@
+/*
+ * TI da8xx DDR2/mDDR controller driver
+ *
+ * Copyright (C) 2016 BayLibre SAS
+ *
+ * Author:
+ *   Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#define DA8XX_DDR_CTL_BASE	0xB0000000
+#define DA8XX_PBBPR_OFFSET	0x00000020
+#define DA8XX_PBBPR_REG(p)	((p) + DA8XX_PBBPR_OFFSET)
+
+#define DA8XX_PBBPR_MAX		0xff
+
+static void da8xx_ddrctl_set_pbbpr(void __iomem *ddrctl, struct device *dev)
+{
+	struct device_node *node = dev->of_node;
+	u32 pr_old_count;
+	int ret;
+
+	ret = of_property_read_u32(node, "ti,pr-old-count", &pr_old_count);
+	if (ret)
+		return;
+
+	if (pr_old_count > DA8XX_PBBPR_MAX) {
+		dev_warn(dev, "priority raise old counter value too high\n");
+		return;
+	}
+
+	__raw_writel(pr_old_count, DA8XX_PBBPR_REG(ddrctl));
+}
+
+static int da8xx_ddrctl_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *ddrctl;
+
+	ddrctl = ioremap(DA8XX_DDR_CTL_BASE, SZ_256);
+	if (!ddrctl) {
+		dev_err(dev, "unable to map memory controller registers\n");
+		return -EIO;
+	}
+
+	da8xx_ddrctl_set_pbbpr(ddrctl, dev);
+
+	iounmap(ddrctl);
+
+	return 0;
+}
+
+static const struct of_device_id da8xx_ddrctl_of_match[] = {
+	{ .compatible = "ti,da850-ddrctl", },
+	{ },
+};
+
+static struct platform_driver da8xx_ddrctl_driver = {
+	.probe = da8xx_ddrctl_probe,
+	.driver = {
+		.name = "da8xx-ddrctl",
+		.of_match_table = da8xx_ddrctl_of_match,
+	},
+};
+module_platform_driver(da8xx_ddrctl_driver);
+
+MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>");
+MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
+MODULE_LICENSE("GPL v2");
-- 
2.9.3

--
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[PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver

[Bartosz Golaszewski]

Create a new driver for the da8xx DDR2/mDDR controller and implement
support for writing to the Peripheral Bus Burst Priority Register.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 .../memory-controllers/ti-da8xx-ddrctl.txt         | 25 +++++++
 drivers/memory/Kconfig                             |  8 +++
 drivers/memory/Makefile                            |  1 +
 drivers/memory/da8xx-ddrctl.c                      | 77 ++++++++++++++++++++++
 4 files changed, 111 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
 create mode 100644 drivers/memory/da8xx-ddrctl.c

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
new file mode 100644
index 0000000..e340404
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
@@ -0,0 +1,25 @@
+* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller
+
+The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs memory
+maps a set of registers which allow to tweak the controller's behavior.
+
+Documentation:
+OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
+
+Required properties:
+
+- compatible:		"ti,da850-ddrctl"
+
+Optional properties:
+
+- ti,pr-old-count:	Priority raise old counter. Specifies the number of
+			memory transfers after which the DDR2/mDDR memory
+			controller will elevate the priority of the oldest
+			command in the command FIFO. Must be between 0-255.
+
+Example for da850 shown below.
+
+ddrctl {
+	compatible = "ti,da850-ddrctl";
+	ti,pr-old-count = <0x20>;
+};
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 4b4c0c3..ec80e35 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -134,6 +134,14 @@ config MTK_SMI
 	  mainly help enable/disable iommu and control the power domain and
 	  clocks for each local arbiter.
 
+config DA8XX_DDRCTL
+	bool "Texas Instruments da8xx DDR2/mDDR driver"
+	depends on ARCH_DAVINCI_DA8XX
+	help
+	  This driver is for the DDR2/mDDR Memory Controller present on
+	  Texas Instruments da8xx SoCs. It's used to tweak various memory
+	  controller configuration options.
+
 source "drivers/memory/samsung/Kconfig"
 source "drivers/memory/tegra/Kconfig"
 
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index b20ae38..e88097fb 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_MVEBU_DEVBUS)	+= mvebu-devbus.o
 obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
 obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
 obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
+obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
 
 obj-$(CONFIG_SAMSUNG_MC)	+= samsung/
 obj-$(CONFIG_TEGRA_MC)		+= tegra/
diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
new file mode 100644
index 0000000..dcd0a61
--- /dev/null
+++ b/drivers/memory/da8xx-ddrctl.c
@@ -0,0 +1,77 @@
+/*
+ * TI da8xx DDR2/mDDR controller driver
+ *
+ * Copyright (C) 2016 BayLibre SAS
+ *
+ * Author:
+ *   Bartosz Golaszewski <bgolaszewski@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#define DA8XX_DDR_CTL_BASE	0xB0000000
+#define DA8XX_PBBPR_OFFSET	0x00000020
+#define DA8XX_PBBPR_REG(p)	((p) + DA8XX_PBBPR_OFFSET)
+
+#define DA8XX_PBBPR_MAX		0xff
+
+static void da8xx_ddrctl_set_pbbpr(void __iomem *ddrctl, struct device *dev)
+{
+	struct device_node *node = dev->of_node;
+	u32 pr_old_count;
+	int ret;
+
+	ret = of_property_read_u32(node, "ti,pr-old-count", &pr_old_count);
+	if (ret)
+		return;
+
+	if (pr_old_count > DA8XX_PBBPR_MAX) {
+		dev_warn(dev, "priority raise old counter value too high\n");
+		return;
+	}
+
+	__raw_writel(pr_old_count, DA8XX_PBBPR_REG(ddrctl));
+}
+
+static int da8xx_ddrctl_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *ddrctl;
+
+	ddrctl = ioremap(DA8XX_DDR_CTL_BASE, SZ_256);
+	if (!ddrctl) {
+		dev_err(dev, "unable to map memory controller registers\n");
+		return -EIO;
+	}
+
+	da8xx_ddrctl_set_pbbpr(ddrctl, dev);
+
+	iounmap(ddrctl);
+
+	return 0;
+}
+
+static const struct of_device_id da8xx_ddrctl_of_match[] = {
+	{ .compatible = "ti,da850-ddrctl", },
+	{ },
+};
+
+static struct platform_driver da8xx_ddrctl_driver = {
+	.probe = da8xx_ddrctl_probe,
+	.driver = {
+		.name = "da8xx-ddrctl",
+		.of_match_table = da8xx_ddrctl_of_match,
+	},
+};
+module_platform_driver(da8xx_ddrctl_driver);
+
+MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
+MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
+MODULE_LICENSE("GPL v2");
-- 
2.9.3

[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Bartosz Golaszewski]

Create the driver for the da8xx System Configuration and implement
support for writing to the three Master Priority registers.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 .../devicetree/bindings/bus/ti,da850-syscfg.txt    |  63 +++++++
 drivers/bus/Kconfig                                |   8 +
 drivers/bus/Makefile                               |   2 +
 drivers/bus/da8xx-syscfg.c                         | 206 +++++++++++++++++++++
 4 files changed, 279 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
 create mode 100644 drivers/bus/da8xx-syscfg.c

diff --git a/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
new file mode 100644
index 0000000..07e5c38
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
@@ -0,0 +1,63 @@
+* Device tree bindings for Texas Instruments da8xx system configuration driver
+
+The system configuration (SYSCFG) module is a system-level module containing
+status and top level control logic required by the device. The system
+configuration module consists of a set of memory-mapped status and control
+registers, accessible by the CPU, supporting all of the following system
+features, and miscellaneous functions and operations.
+
+Documentation:
+OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
+
+Required properties:
+
+- compatible:		"ti,da850-syscfg"
+
+Optional properties:
+
+The below properties are used to specify the priority of master peripherals.
+They must be between 0-7 where 0 is the highest priority and 7 is the lowest.
+
+- ti,pri-arm-i:		ARM_I port priority.
+
+- ti,pri-arm-d:		ARM_D port priority.
+
+- ti,pri-upp:		uPP port priority.
+
+- ti,pri-sata:		SATA port priority.
+
+- ti,pri-pru0:		PRU0 port priority.
+
+- ti,pri-pru1:		PRU1 port priority.
+
+- ti,pri-edma30tc0:	EDMA3_0_TC0 port priority.
+
+- ti,pri-edma30tc1:	EDMA3_0_TC1 port priority.
+
+- ti,pri-edma31tc0:	EDMA3_1_TC0 port priority.
+
+- ti,pri-vpif-dma-0:	VPIF DMA0 port priority.
+
+- ti,pri-vpif-dma-1:	VPIF DMA1 port priority.
+
+- ti,pri-emac:		EMAC port priority.
+
+- ti,pri-usb0cfg:	USB0 CFG port priority.
+
+- ti,pri-usb0cdma:	USB0 CDMA port priority.
+
+- ti,pri-uhpi:		HPI port priority.
+
+- ti,pri-usb1:		USB1 port priority.
+
+- ti,pri-lcdc:		LCDC port priority.
+
+If any of the above properties is absent, the default value will be used as
+defined in the documentation.
+
+Example for da850-lcdk is shown below.
+
+mstpri {
+	compatible = "ti,da850-mstpri";
+	ti,pri-lcdc = 0;
+};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 5a2d47c..6276132 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -165,4 +165,12 @@ config VEXPRESS_CONFIG
 	help
 	  Platform configuration infrastructure for the ARM Ltd.
 	  Versatile Express.
+
+config DA8XX_SYSCFG
+	bool "TI da8xx system configuration driver"
+	depends on ARCH_DAVINCI_DA8XX
+	help
+	  Driver for Texas Instruments da8xx system configuration. Allows to
+	  adjust various SoC configuration options.
+
 endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index c6cfa6b..3cba66a 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -21,3 +21,5 @@ obj-$(CONFIG_SIMPLE_PM_BUS)	+= simple-pm-bus.o
 obj-$(CONFIG_TEGRA_ACONNECT)	+= tegra-aconnect.o
 obj-$(CONFIG_UNIPHIER_SYSTEM_BUS)	+= uniphier-system-bus.o
 obj-$(CONFIG_VEXPRESS_CONFIG)	+= vexpress-config.o
+
+obj-$(CONFIG_DA8XX_SYSCFG)	+= da8xx-syscfg.o
diff --git a/drivers/bus/da8xx-syscfg.c b/drivers/bus/da8xx-syscfg.c
new file mode 100644
index 0000000..8a2cb4f
--- /dev/null
+++ b/drivers/bus/da8xx-syscfg.c
@@ -0,0 +1,206 @@
+/*
+ * TI da8xx System Configuration driver
+ *
+ * Copyright (C) 2016 BayLibre SAS
+ *
+ * Author:
+ *   Bartosz Golaszewski <bgolaszewski@baylibre.com.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#define DA8XX_IO_PHYS			0x01c00000ul
+#define DA8XX_SYSCFG0_BASE		(DA8XX_IO_PHYS + 0x14000)
+
+#define DA8XX_MSTPRI0_REG		0x110
+#define DA8XX_MSTPRI1_REG		0x114
+#define DA8XX_MSTPRI2_REG		0x118
+
+#define DA8XX_MSTPRI_MAX		7
+
+struct da8xx_mstpri_descr {
+	const char *property;
+	int reg;
+	int shift;
+	int mask;
+};
+
+static const struct da8xx_mstpri_descr priorities[] = {
+	{
+		.property = "ti,pri-arm-i",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 0,
+		.mask = 0xfffffff0,
+	},
+	{
+		.property = "ti,pri-arm-d",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 4,
+		.mask = 0xffffff0f,
+	},
+	{
+		.property = "ti,pri-upp",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 16,
+		.mask = 0xfff0ffff,
+	},
+	{
+		.property = "ti,pri-sata",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 20,
+		.mask = 0xff0fffff,
+	},
+	{
+		.property = "ti,pri-pru0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 0,
+		.mask = 0xfffffff0,
+	},
+	{
+		.property = "ti,pri-pru1",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 4,
+		.mask = 0xffffff0f,
+	},
+	{
+		.property = "ti,pri-edma30tc0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 8,
+		.mask = 0xfffff0ff,
+	},
+	{
+		.property = "ti,pri-edma30tc1",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 12,
+		.mask = 0xffff0fff,
+	},
+	{
+		.property = "ti,pri-edma31tc0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 16,
+		.mask = 0xfff0ffff,
+	},
+	{
+		.property = "ti,pri-vpif-dma-0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 24,
+		.mask = 0xf0ffffff,
+	},
+	{
+		.property = "ti,pri-vpif-dma-1",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 28,
+		.mask = 0x0fffffff,
+	},
+	{
+		.property = "ti,pri-emac",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 0,
+		.mask = 0xfffffff0,
+	},
+	{
+		.property = "ti,pri-usb0cfg",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 8,
+		.mask = 0xfffff0ff,
+	},
+	{
+		.property = "ti,pri-usb0cdma",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 12,
+		.mask = 0xffff0fff,
+	},
+	{
+		.property = "ti,pri-uhpi",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 20,
+		.mask = 0xff0fffff,
+	},
+	{
+		.property = "ti,pri-usb1",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 24,
+		.mask = 0xf0ffffff,
+	},
+	{
+		.property = "ti,pri-lcdc",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 28,
+		.mask = 0x0fffffff,
+	},
+};
+
+static void da8xx_syscfg_set_mstpri(void __iomem *syscfg0, struct device *dev)
+{
+	const struct da8xx_mstpri_descr *pri_descr;
+	struct device_node *node = dev->of_node;
+	void __iomem *mstpri;
+	u32 old_pri, new_pri;
+	int ret, i;
+
+	for (i = 0; i < ARRAY_SIZE(priorities); i++) {
+		pri_descr = &priorities[i];
+
+		ret = of_property_read_u32(node, pri_descr->property, &new_pri);
+		if (ret)
+			continue;
+
+		if (new_pri > DA8XX_MSTPRI_MAX) {
+			dev_warn(dev,
+				 "omitting property '%s' - value too high\n",
+				 pri_descr->property);
+			continue;
+		}
+
+		mstpri = syscfg0 + pri_descr->reg;
+		old_pri = __raw_readl(mstpri);
+		old_pri &= pri_descr->mask;
+		new_pri <<= pri_descr->shift;
+		new_pri |= old_pri;
+
+		__raw_writel(new_pri, mstpri);
+	}
+}
+
+static int da8xx_syscfg_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *syscfg0;
+
+	syscfg0 = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+	if (!syscfg0) {
+		dev_err(dev, "unable to map syscfg0\n");
+		return -EIO;
+	}
+
+	da8xx_syscfg_set_mstpri(syscfg0, dev);
+
+	iounmap(syscfg0);
+
+	return 0;
+}
+
+static const struct of_device_id da8xx_syscfg_of_match[] = {
+	{ .compatible = "ti,da850-syscfg", },
+	{ },
+};
+
+static struct platform_driver da8xx_syscfg_driver = {
+	.probe = da8xx_syscfg_probe,
+	.driver = {
+		.name = "da8xx-syscfg",
+		.of_match_table = da8xx_syscfg_of_match,
+	},
+};
+module_platform_driver(da8xx_syscfg_driver);
+
+MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
+MODULE_DESCRIPTION("TI da8xx System Configuration driver");
+MODULE_LICENSE("GPL v2");
-- 
2.9.3

[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Bartosz Golaszewski]

Create the driver for the da8xx System Configuration and implement
support for writing to the three Master Priority registers.

Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
 .../devicetree/bindings/bus/ti,da850-syscfg.txt    |  63 +++++++
 drivers/bus/Kconfig                                |   8 +
 drivers/bus/Makefile                               |   2 +
 drivers/bus/da8xx-syscfg.c                         | 206 +++++++++++++++++++++
 4 files changed, 279 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
 create mode 100644 drivers/bus/da8xx-syscfg.c

diff --git a/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
new file mode 100644
index 0000000..07e5c38
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
@@ -0,0 +1,63 @@
+* Device tree bindings for Texas Instruments da8xx system configuration driver
+
+The system configuration (SYSCFG) module is a system-level module containing
+status and top level control logic required by the device. The system
+configuration module consists of a set of memory-mapped status and control
+registers, accessible by the CPU, supporting all of the following system
+features, and miscellaneous functions and operations.
+
+Documentation:
+OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
+
+Required properties:
+
+- compatible:		"ti,da850-syscfg"
+
+Optional properties:
+
+The below properties are used to specify the priority of master peripherals.
+They must be between 0-7 where 0 is the highest priority and 7 is the lowest.
+
+- ti,pri-arm-i:		ARM_I port priority.
+
+- ti,pri-arm-d:		ARM_D port priority.
+
+- ti,pri-upp:		uPP port priority.
+
+- ti,pri-sata:		SATA port priority.
+
+- ti,pri-pru0:		PRU0 port priority.
+
+- ti,pri-pru1:		PRU1 port priority.
+
+- ti,pri-edma30tc0:	EDMA3_0_TC0 port priority.
+
+- ti,pri-edma30tc1:	EDMA3_0_TC1 port priority.
+
+- ti,pri-edma31tc0:	EDMA3_1_TC0 port priority.
+
+- ti,pri-vpif-dma-0:	VPIF DMA0 port priority.
+
+- ti,pri-vpif-dma-1:	VPIF DMA1 port priority.
+
+- ti,pri-emac:		EMAC port priority.
+
+- ti,pri-usb0cfg:	USB0 CFG port priority.
+
+- ti,pri-usb0cdma:	USB0 CDMA port priority.
+
+- ti,pri-uhpi:		HPI port priority.
+
+- ti,pri-usb1:		USB1 port priority.
+
+- ti,pri-lcdc:		LCDC port priority.
+
+If any of the above properties is absent, the default value will be used as
+defined in the documentation.
+
+Example for da850-lcdk is shown below.
+
+mstpri {
+	compatible = "ti,da850-mstpri";
+	ti,pri-lcdc = 0;
+};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 5a2d47c..6276132 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -165,4 +165,12 @@ config VEXPRESS_CONFIG
 	help
 	  Platform configuration infrastructure for the ARM Ltd.
 	  Versatile Express.
+
+config DA8XX_SYSCFG
+	bool "TI da8xx system configuration driver"
+	depends on ARCH_DAVINCI_DA8XX
+	help
+	  Driver for Texas Instruments da8xx system configuration. Allows to
+	  adjust various SoC configuration options.
+
 endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index c6cfa6b..3cba66a 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -21,3 +21,5 @@ obj-$(CONFIG_SIMPLE_PM_BUS)	+= simple-pm-bus.o
 obj-$(CONFIG_TEGRA_ACONNECT)	+= tegra-aconnect.o
 obj-$(CONFIG_UNIPHIER_SYSTEM_BUS)	+= uniphier-system-bus.o
 obj-$(CONFIG_VEXPRESS_CONFIG)	+= vexpress-config.o
+
+obj-$(CONFIG_DA8XX_SYSCFG)	+= da8xx-syscfg.o
diff --git a/drivers/bus/da8xx-syscfg.c b/drivers/bus/da8xx-syscfg.c
new file mode 100644
index 0000000..8a2cb4f
--- /dev/null
+++ b/drivers/bus/da8xx-syscfg.c
@@ -0,0 +1,206 @@
+/*
+ * TI da8xx System Configuration driver
+ *
+ * Copyright (C) 2016 BayLibre SAS
+ *
+ * Author:
+ *   Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBpdZSXdFL2CA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#define DA8XX_IO_PHYS			0x01c00000ul
+#define DA8XX_SYSCFG0_BASE		(DA8XX_IO_PHYS + 0x14000)
+
+#define DA8XX_MSTPRI0_REG		0x110
+#define DA8XX_MSTPRI1_REG		0x114
+#define DA8XX_MSTPRI2_REG		0x118
+
+#define DA8XX_MSTPRI_MAX		7
+
+struct da8xx_mstpri_descr {
+	const char *property;
+	int reg;
+	int shift;
+	int mask;
+};
+
+static const struct da8xx_mstpri_descr priorities[] = {
+	{
+		.property = "ti,pri-arm-i",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 0,
+		.mask = 0xfffffff0,
+	},
+	{
+		.property = "ti,pri-arm-d",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 4,
+		.mask = 0xffffff0f,
+	},
+	{
+		.property = "ti,pri-upp",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 16,
+		.mask = 0xfff0ffff,
+	},
+	{
+		.property = "ti,pri-sata",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 20,
+		.mask = 0xff0fffff,
+	},
+	{
+		.property = "ti,pri-pru0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 0,
+		.mask = 0xfffffff0,
+	},
+	{
+		.property = "ti,pri-pru1",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 4,
+		.mask = 0xffffff0f,
+	},
+	{
+		.property = "ti,pri-edma30tc0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 8,
+		.mask = 0xfffff0ff,
+	},
+	{
+		.property = "ti,pri-edma30tc1",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 12,
+		.mask = 0xffff0fff,
+	},
+	{
+		.property = "ti,pri-edma31tc0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 16,
+		.mask = 0xfff0ffff,
+	},
+	{
+		.property = "ti,pri-vpif-dma-0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 24,
+		.mask = 0xf0ffffff,
+	},
+	{
+		.property = "ti,pri-vpif-dma-1",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 28,
+		.mask = 0x0fffffff,
+	},
+	{
+		.property = "ti,pri-emac",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 0,
+		.mask = 0xfffffff0,
+	},
+	{
+		.property = "ti,pri-usb0cfg",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 8,
+		.mask = 0xfffff0ff,
+	},
+	{
+		.property = "ti,pri-usb0cdma",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 12,
+		.mask = 0xffff0fff,
+	},
+	{
+		.property = "ti,pri-uhpi",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 20,
+		.mask = 0xff0fffff,
+	},
+	{
+		.property = "ti,pri-usb1",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 24,
+		.mask = 0xf0ffffff,
+	},
+	{
+		.property = "ti,pri-lcdc",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 28,
+		.mask = 0x0fffffff,
+	},
+};
+
+static void da8xx_syscfg_set_mstpri(void __iomem *syscfg0, struct device *dev)
+{
+	const struct da8xx_mstpri_descr *pri_descr;
+	struct device_node *node = dev->of_node;
+	void __iomem *mstpri;
+	u32 old_pri, new_pri;
+	int ret, i;
+
+	for (i = 0; i < ARRAY_SIZE(priorities); i++) {
+		pri_descr = &priorities[i];
+
+		ret = of_property_read_u32(node, pri_descr->property, &new_pri);
+		if (ret)
+			continue;
+
+		if (new_pri > DA8XX_MSTPRI_MAX) {
+			dev_warn(dev,
+				 "omitting property '%s' - value too high\n",
+				 pri_descr->property);
+			continue;
+		}
+
+		mstpri = syscfg0 + pri_descr->reg;
+		old_pri = __raw_readl(mstpri);
+		old_pri &= pri_descr->mask;
+		new_pri <<= pri_descr->shift;
+		new_pri |= old_pri;
+
+		__raw_writel(new_pri, mstpri);
+	}
+}
+
+static int da8xx_syscfg_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *syscfg0;
+
+	syscfg0 = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+	if (!syscfg0) {
+		dev_err(dev, "unable to map syscfg0\n");
+		return -EIO;
+	}
+
+	da8xx_syscfg_set_mstpri(syscfg0, dev);
+
+	iounmap(syscfg0);
+
+	return 0;
+}
+
+static const struct of_device_id da8xx_syscfg_of_match[] = {
+	{ .compatible = "ti,da850-syscfg", },
+	{ },
+};
+
+static struct platform_driver da8xx_syscfg_driver = {
+	.probe = da8xx_syscfg_probe,
+	.driver = {
+		.name = "da8xx-syscfg",
+		.of_match_table = da8xx_syscfg_of_match,
+	},
+};
+module_platform_driver(da8xx_syscfg_driver);
+
+MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>");
+MODULE_DESCRIPTION("TI da8xx System Configuration driver");
+MODULE_LICENSE("GPL v2");
-- 
2.9.3

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[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Bartosz Golaszewski]

Create the driver for the da8xx System Configuration and implement
support for writing to the three Master Priority registers.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 .../devicetree/bindings/bus/ti,da850-syscfg.txt    |  63 +++++++
 drivers/bus/Kconfig                                |   8 +
 drivers/bus/Makefile                               |   2 +
 drivers/bus/da8xx-syscfg.c                         | 206 +++++++++++++++++++++
 4 files changed, 279 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
 create mode 100644 drivers/bus/da8xx-syscfg.c

diff --git a/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
new file mode 100644
index 0000000..07e5c38
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
@@ -0,0 +1,63 @@
+* Device tree bindings for Texas Instruments da8xx system configuration driver
+
+The system configuration (SYSCFG) module is a system-level module containing
+status and top level control logic required by the device. The system
+configuration module consists of a set of memory-mapped status and control
+registers, accessible by the CPU, supporting all of the following system
+features, and miscellaneous functions and operations.
+
+Documentation:
+OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
+
+Required properties:
+
+- compatible:		"ti,da850-syscfg"
+
+Optional properties:
+
+The below properties are used to specify the priority of master peripherals.
+They must be between 0-7 where 0 is the highest priority and 7 is the lowest.
+
+- ti,pri-arm-i:		ARM_I port priority.
+
+- ti,pri-arm-d:		ARM_D port priority.
+
+- ti,pri-upp:		uPP port priority.
+
+- ti,pri-sata:		SATA port priority.
+
+- ti,pri-pru0:		PRU0 port priority.
+
+- ti,pri-pru1:		PRU1 port priority.
+
+- ti,pri-edma30tc0:	EDMA3_0_TC0 port priority.
+
+- ti,pri-edma30tc1:	EDMA3_0_TC1 port priority.
+
+- ti,pri-edma31tc0:	EDMA3_1_TC0 port priority.
+
+- ti,pri-vpif-dma-0:	VPIF DMA0 port priority.
+
+- ti,pri-vpif-dma-1:	VPIF DMA1 port priority.
+
+- ti,pri-emac:		EMAC port priority.
+
+- ti,pri-usb0cfg:	USB0 CFG port priority.
+
+- ti,pri-usb0cdma:	USB0 CDMA port priority.
+
+- ti,pri-uhpi:		HPI port priority.
+
+- ti,pri-usb1:		USB1 port priority.
+
+- ti,pri-lcdc:		LCDC port priority.
+
+If any of the above properties is absent, the default value will be used as
+defined in the documentation.
+
+Example for da850-lcdk is shown below.
+
+mstpri {
+	compatible = "ti,da850-mstpri";
+	ti,pri-lcdc = 0;
+};
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 5a2d47c..6276132 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -165,4 +165,12 @@ config VEXPRESS_CONFIG
 	help
 	  Platform configuration infrastructure for the ARM Ltd.
 	  Versatile Express.
+
+config DA8XX_SYSCFG
+	bool "TI da8xx system configuration driver"
+	depends on ARCH_DAVINCI_DA8XX
+	help
+	  Driver for Texas Instruments da8xx system configuration. Allows to
+	  adjust various SoC configuration options.
+
 endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index c6cfa6b..3cba66a 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -21,3 +21,5 @@ obj-$(CONFIG_SIMPLE_PM_BUS)	+= simple-pm-bus.o
 obj-$(CONFIG_TEGRA_ACONNECT)	+= tegra-aconnect.o
 obj-$(CONFIG_UNIPHIER_SYSTEM_BUS)	+= uniphier-system-bus.o
 obj-$(CONFIG_VEXPRESS_CONFIG)	+= vexpress-config.o
+
+obj-$(CONFIG_DA8XX_SYSCFG)	+= da8xx-syscfg.o
diff --git a/drivers/bus/da8xx-syscfg.c b/drivers/bus/da8xx-syscfg.c
new file mode 100644
index 0000000..8a2cb4f
--- /dev/null
+++ b/drivers/bus/da8xx-syscfg.c
@@ -0,0 +1,206 @@
+/*
+ * TI da8xx System Configuration driver
+ *
+ * Copyright (C) 2016 BayLibre SAS
+ *
+ * Author:
+ *   Bartosz Golaszewski <bgolaszewski@baylibre.com.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#define DA8XX_IO_PHYS			0x01c00000ul
+#define DA8XX_SYSCFG0_BASE		(DA8XX_IO_PHYS + 0x14000)
+
+#define DA8XX_MSTPRI0_REG		0x110
+#define DA8XX_MSTPRI1_REG		0x114
+#define DA8XX_MSTPRI2_REG		0x118
+
+#define DA8XX_MSTPRI_MAX		7
+
+struct da8xx_mstpri_descr {
+	const char *property;
+	int reg;
+	int shift;
+	int mask;
+};
+
+static const struct da8xx_mstpri_descr priorities[] = {
+	{
+		.property = "ti,pri-arm-i",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 0,
+		.mask = 0xfffffff0,
+	},
+	{
+		.property = "ti,pri-arm-d",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 4,
+		.mask = 0xffffff0f,
+	},
+	{
+		.property = "ti,pri-upp",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 16,
+		.mask = 0xfff0ffff,
+	},
+	{
+		.property = "ti,pri-sata",
+		.reg = DA8XX_MSTPRI0_REG,
+		.shift = 20,
+		.mask = 0xff0fffff,
+	},
+	{
+		.property = "ti,pri-pru0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 0,
+		.mask = 0xfffffff0,
+	},
+	{
+		.property = "ti,pri-pru1",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 4,
+		.mask = 0xffffff0f,
+	},
+	{
+		.property = "ti,pri-edma30tc0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 8,
+		.mask = 0xfffff0ff,
+	},
+	{
+		.property = "ti,pri-edma30tc1",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 12,
+		.mask = 0xffff0fff,
+	},
+	{
+		.property = "ti,pri-edma31tc0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 16,
+		.mask = 0xfff0ffff,
+	},
+	{
+		.property = "ti,pri-vpif-dma-0",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 24,
+		.mask = 0xf0ffffff,
+	},
+	{
+		.property = "ti,pri-vpif-dma-1",
+		.reg = DA8XX_MSTPRI1_REG,
+		.shift = 28,
+		.mask = 0x0fffffff,
+	},
+	{
+		.property = "ti,pri-emac",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 0,
+		.mask = 0xfffffff0,
+	},
+	{
+		.property = "ti,pri-usb0cfg",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 8,
+		.mask = 0xfffff0ff,
+	},
+	{
+		.property = "ti,pri-usb0cdma",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 12,
+		.mask = 0xffff0fff,
+	},
+	{
+		.property = "ti,pri-uhpi",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 20,
+		.mask = 0xff0fffff,
+	},
+	{
+		.property = "ti,pri-usb1",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 24,
+		.mask = 0xf0ffffff,
+	},
+	{
+		.property = "ti,pri-lcdc",
+		.reg = DA8XX_MSTPRI2_REG,
+		.shift = 28,
+		.mask = 0x0fffffff,
+	},
+};
+
+static void da8xx_syscfg_set_mstpri(void __iomem *syscfg0, struct device *dev)
+{
+	const struct da8xx_mstpri_descr *pri_descr;
+	struct device_node *node = dev->of_node;
+	void __iomem *mstpri;
+	u32 old_pri, new_pri;
+	int ret, i;
+
+	for (i = 0; i < ARRAY_SIZE(priorities); i++) {
+		pri_descr = &priorities[i];
+
+		ret = of_property_read_u32(node, pri_descr->property, &new_pri);
+		if (ret)
+			continue;
+
+		if (new_pri > DA8XX_MSTPRI_MAX) {
+			dev_warn(dev,
+				 "omitting property '%s' - value too high\n",
+				 pri_descr->property);
+			continue;
+		}
+
+		mstpri = syscfg0 + pri_descr->reg;
+		old_pri = __raw_readl(mstpri);
+		old_pri &= pri_descr->mask;
+		new_pri <<= pri_descr->shift;
+		new_pri |= old_pri;
+
+		__raw_writel(new_pri, mstpri);
+	}
+}
+
+static int da8xx_syscfg_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *syscfg0;
+
+	syscfg0 = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+	if (!syscfg0) {
+		dev_err(dev, "unable to map syscfg0\n");
+		return -EIO;
+	}
+
+	da8xx_syscfg_set_mstpri(syscfg0, dev);
+
+	iounmap(syscfg0);
+
+	return 0;
+}
+
+static const struct of_device_id da8xx_syscfg_of_match[] = {
+	{ .compatible = "ti,da850-syscfg", },
+	{ },
+};
+
+static struct platform_driver da8xx_syscfg_driver = {
+	.probe = da8xx_syscfg_probe,
+	.driver = {
+		.name = "da8xx-syscfg",
+		.of_match_table = da8xx_syscfg_of_match,
+	},
+};
+module_platform_driver(da8xx_syscfg_driver);
+
+MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
+MODULE_DESCRIPTION("TI da8xx System Configuration driver");
+MODULE_LICENSE("GPL v2");
-- 
2.9.3

[PATCH 3/3] ARM: dts: da850: add the syscfg and ddrctl nodes

[Bartosz Golaszewski]

Add the nodes for the System Configuration and DDR2/mDDR memory
controller drivers to da850.dtsi.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 arch/arm/boot/dts/da850.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 6440002..6d56ef2 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -407,6 +407,16 @@
 			interrupts = <52>;
 			status = "disabled";
 		};
+
+		ddrctl: da850-ddrctl {
+			compatible = "ti,da850-ddrctl";
+			status = "disabled";
+		};
+
+		syscfg: da850-syscfg {
+			compatible = "ti,da850-syscfg";
+			status = "disabled";
+		};
 	};
 	aemif: aemif@68000000 {
 		compatible = "ti,da850-aemif";
-- 
2.9.3

[PATCH 3/3] ARM: dts: da850: add the syscfg and ddrctl nodes

[Bartosz Golaszewski]

Add the nodes for the System Configuration and DDR2/mDDR memory
controller drivers to da850.dtsi.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 arch/arm/boot/dts/da850.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 6440002..6d56ef2 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -407,6 +407,16 @@
 			interrupts = <52>;
 			status = "disabled";
 		};
+
+		ddrctl: da850-ddrctl {
+			compatible = "ti,da850-ddrctl";
+			status = "disabled";
+		};
+
+		syscfg: da850-syscfg {
+			compatible = "ti,da850-syscfg";
+			status = "disabled";
+		};
 	};
 	aemif: aemif@68000000 {
 		compatible = "ti,da850-aemif";
-- 
2.9.3

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 3/3] ARM: dts: da850: add the syscfg and ddrctl nodes

[Bartosz Golaszewski]

Add the nodes for the System Configuration and DDR2/mDDR memory
controller drivers to da850.dtsi.

Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
 arch/arm/boot/dts/da850.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 6440002..6d56ef2 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -407,6 +407,16 @@
 			interrupts = <52>;
 			status = "disabled";
 		};
+
+		ddrctl: da850-ddrctl {
+			compatible = "ti,da850-ddrctl";
+			status = "disabled";
+		};
+
+		syscfg: da850-syscfg {
+			compatible = "ti,da850-syscfg";
+			status = "disabled";
+		};
 	};
 	aemif: aemif at 68000000 {
 		compatible = "ti,da850-aemif";
-- 
2.9.3

Re: [PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver

[Kevin Hilman]

Bartosz Golaszewski <bgolaszewski@baylibre.com> writes:

> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

[...]

> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> new file mode 100644
> index 0000000..dcd0a61
> --- /dev/null
> +++ b/drivers/memory/da8xx-ddrctl.c
> @@ -0,0 +1,77 @@
> +/*
> + * TI da8xx DDR2/mDDR controller driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + *   Bartosz Golaszewski <bgolaszewski@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_DDR_CTL_BASE	0xB0000000

This base addr should be the reg property of the node.

> +#define DA8XX_PBBPR_OFFSET	0x00000020
> +#define DA8XX_PBBPR_REG(p)	((p) + DA8XX_PBBPR_OFFSET)

Kevin

Re: [PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver

[Kevin Hilman]

Bartosz Golaszewski <bgolaszewski@baylibre.com> writes:

> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

[...]

> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> new file mode 100644
> index 0000000..dcd0a61
> --- /dev/null
> +++ b/drivers/memory/da8xx-ddrctl.c
> @@ -0,0 +1,77 @@
> +/*
> + * TI da8xx DDR2/mDDR controller driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + *   Bartosz Golaszewski <bgolaszewski@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_DDR_CTL_BASE	0xB0000000

This base addr should be the reg property of the node.

> +#define DA8XX_PBBPR_OFFSET	0x00000020
> +#define DA8XX_PBBPR_REG(p)	((p) + DA8XX_PBBPR_OFFSET)

Kevin
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver

[Kevin Hilman]

Bartosz Golaszewski <bgolaszewski@baylibre.com> writes:

> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

[...]

> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> new file mode 100644
> index 0000000..dcd0a61
> --- /dev/null
> +++ b/drivers/memory/da8xx-ddrctl.c
> @@ -0,0 +1,77 @@
> +/*
> + * TI da8xx DDR2/mDDR controller driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + *   Bartosz Golaszewski <bgolaszewski@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_DDR_CTL_BASE	0xB0000000

This base addr should be the reg property of the node.

> +#define DA8XX_PBBPR_OFFSET	0x00000020
> +#define DA8XX_PBBPR_REG(p)	((p) + DA8XX_PBBPR_OFFSET)

Kevin

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Kevin Hilman]

Bartosz Golaszewski <bgolaszewski@baylibre.com> writes:

> Create the driver for the da8xx System Configuration and implement
> support for writing to the three Master Priority registers.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

[...]

> +#define DA8XX_IO_PHYS			0x01c00000ul
> +#define DA8XX_SYSCFG0_BASE		(DA8XX_IO_PHYS + 0x14000)

The base addr should come from DT.

Kevin

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Kevin Hilman]

Bartosz Golaszewski <bgolaszewski@baylibre.com> writes:

> Create the driver for the da8xx System Configuration and implement
> support for writing to the three Master Priority registers.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

[...]

> +#define DA8XX_IO_PHYS			0x01c00000ul
> +#define DA8XX_SYSCFG0_BASE		(DA8XX_IO_PHYS + 0x14000)

The base addr should come from DT.

Kevin
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[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Kevin Hilman]

Bartosz Golaszewski <bgolaszewski@baylibre.com> writes:

> Create the driver for the da8xx System Configuration and implement
> support for writing to the three Master Priority registers.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

[...]

> +#define DA8XX_IO_PHYS			0x01c00000ul
> +#define DA8XX_SYSCFG0_BASE		(DA8XX_IO_PHYS + 0x14000)

The base addr should come from DT.

Kevin

Re: [PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver

[Laurent Pinchart]

Hi Bartosz,

Thank you for the patch.

On Monday 17 Oct 2016 18:30:48 Bartosz Golaszewski wrote:
> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
> 
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
>  .../memory-controllers/ti-da8xx-ddrctl.txt         | 25 +++++++
>  drivers/memory/Kconfig                             |  8 +++
>  drivers/memory/Makefile                            |  1 +
>  drivers/memory/da8xx-ddrctl.c                      | 77 +++++++++++++++++++
>  4 files changed, 111 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> create mode 100644 drivers/memory/da8xx-ddrctl.c
> 
> diff --git
> a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> new file mode 100644
> index 0000000..e340404
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> @@ -0,0 +1,25 @@
> +* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory
> controller
> +
> +The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs
> memory
> +maps a set of registers which allow to tweak the controller's behavior.
> +
> +Documentation:
> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> +
> +Required properties:
> +
> +- compatible:		"ti,da850-ddrctl"

Don't you need a reg property ?

> +Optional properties:
> +
> +- ti,pr-old-count:	Priority raise old counter. Specifies the number of
> +			memory transfers after which the DDR2/mDDR memory
> +			controller will elevate the priority of the oldest
> +			command in the command FIFO. Must be between 0-255.

Isn't this a system configuration more than a hardware description ?

> +Example for da850 shown below.
> +
> +ddrctl {
> +	compatible = "ti,da850-ddrctl";
> +	ti,pr-old-count = <0x20>;
> +};
> diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
> index 4b4c0c3..ec80e35 100644
> --- a/drivers/memory/Kconfig
> +++ b/drivers/memory/Kconfig
> @@ -134,6 +134,14 @@ config MTK_SMI
>  	  mainly help enable/disable iommu and control the power domain and
>  	  clocks for each local arbiter.
> 
> +config DA8XX_DDRCTL
> +	bool "Texas Instruments da8xx DDR2/mDDR driver"
> +	depends on ARCH_DAVINCI_DA8XX
> +	help
> +	  This driver is for the DDR2/mDDR Memory Controller present on
> +	  Texas Instruments da8xx SoCs. It's used to tweak various memory
> +	  controller configuration options.
> +
>  source "drivers/memory/samsung/Kconfig"
>  source "drivers/memory/tegra/Kconfig"
> 
> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
> index b20ae38..e88097fb 100644
> --- a/drivers/memory/Makefile
> +++ b/drivers/memory/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_MVEBU_DEVBUS)	+= mvebu-devbus.o
>  obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
>  obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
>  obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
> +obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
> 
>  obj-$(CONFIG_SAMSUNG_MC)	+= samsung/
>  obj-$(CONFIG_TEGRA_MC)		+= tegra/
> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> new file mode 100644
> index 0000000..dcd0a61
> --- /dev/null
> +++ b/drivers/memory/da8xx-ddrctl.c
> @@ -0,0 +1,77 @@
> +/*
> + * TI da8xx DDR2/mDDR controller driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + *   Bartosz Golaszewski <bgolaszewski@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_DDR_CTL_BASE	0xB0000000
> +#define DA8XX_PBBPR_OFFSET	0x00000020
> +#define DA8XX_PBBPR_REG(p)	((p) + DA8XX_PBBPR_OFFSET)
> +
> +#define DA8XX_PBBPR_MAX		0xff
> +
> +static void da8xx_ddrctl_set_pbbpr(void __iomem *ddrctl, struct device
> *dev) +{
> +	struct device_node *node = dev->of_node;
> +	u32 pr_old_count;
> +	int ret;
> +
> +	ret = of_property_read_u32(node, "ti,pr-old-count", &pr_old_count);
> +	if (ret)
> +		return;
> +
> +	if (pr_old_count > DA8XX_PBBPR_MAX) {
> +		dev_warn(dev, "priority raise old counter value too high\n");
> +		return;
> +	}
> +
> +	__raw_writel(pr_old_count, DA8XX_PBBPR_REG(ddrctl));
> +}
> +
> +static int da8xx_ddrctl_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	void __iomem *ddrctl;
> +
> +	ddrctl = ioremap(DA8XX_DDR_CTL_BASE, SZ_256);
> +	if (!ddrctl) {
> +		dev_err(dev, "unable to map memory controller registers\n");
> +		return -EIO;
> +	}
> +
> +	da8xx_ddrctl_set_pbbpr(ddrctl, dev);
> +
> +	iounmap(ddrctl);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id da8xx_ddrctl_of_match[] = {
> +	{ .compatible = "ti,da850-ddrctl", },
> +	{ },
> +};
> +
> +static struct platform_driver da8xx_ddrctl_driver = {
> +	.probe = da8xx_ddrctl_probe,
> +	.driver = {
> +		.name = "da8xx-ddrctl",
> +		.of_match_table = da8xx_ddrctl_of_match,
> +	},
> +};
> +module_platform_driver(da8xx_ddrctl_driver);
> +
> +MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
> +MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
> +MODULE_LICENSE("GPL v2");

-- 
Regards,

Laurent Pinchart

Re: [PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver

[Laurent Pinchart]

Hi Bartosz,

Thank you for the patch.

On Monday 17 Oct 2016 18:30:48 Bartosz Golaszewski wrote:
> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
> 
> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
>  .../memory-controllers/ti-da8xx-ddrctl.txt         | 25 +++++++
>  drivers/memory/Kconfig                             |  8 +++
>  drivers/memory/Makefile                            |  1 +
>  drivers/memory/da8xx-ddrctl.c                      | 77 +++++++++++++++++++
>  4 files changed, 111 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> create mode 100644 drivers/memory/da8xx-ddrctl.c
> 
> diff --git
> a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> new file mode 100644
> index 0000000..e340404
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> @@ -0,0 +1,25 @@
> +* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory
> controller
> +
> +The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs
> memory
> +maps a set of registers which allow to tweak the controller's behavior.
> +
> +Documentation:
> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> +
> +Required properties:
> +
> +- compatible:		"ti,da850-ddrctl"

Don't you need a reg property ?

> +Optional properties:
> +
> +- ti,pr-old-count:	Priority raise old counter. Specifies the number of
> +			memory transfers after which the DDR2/mDDR memory
> +			controller will elevate the priority of the oldest
> +			command in the command FIFO. Must be between 0-255.

Isn't this a system configuration more than a hardware description ?

> +Example for da850 shown below.
> +
> +ddrctl {
> +	compatible = "ti,da850-ddrctl";
> +	ti,pr-old-count = <0x20>;
> +};
> diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
> index 4b4c0c3..ec80e35 100644
> --- a/drivers/memory/Kconfig
> +++ b/drivers/memory/Kconfig
> @@ -134,6 +134,14 @@ config MTK_SMI
>  	  mainly help enable/disable iommu and control the power domain and
>  	  clocks for each local arbiter.
> 
> +config DA8XX_DDRCTL
> +	bool "Texas Instruments da8xx DDR2/mDDR driver"
> +	depends on ARCH_DAVINCI_DA8XX
> +	help
> +	  This driver is for the DDR2/mDDR Memory Controller present on
> +	  Texas Instruments da8xx SoCs. It's used to tweak various memory
> +	  controller configuration options.
> +
>  source "drivers/memory/samsung/Kconfig"
>  source "drivers/memory/tegra/Kconfig"
> 
> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
> index b20ae38..e88097fb 100644
> --- a/drivers/memory/Makefile
> +++ b/drivers/memory/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_MVEBU_DEVBUS)	+= mvebu-devbus.o
>  obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
>  obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
>  obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
> +obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
> 
>  obj-$(CONFIG_SAMSUNG_MC)	+= samsung/
>  obj-$(CONFIG_TEGRA_MC)		+= tegra/
> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> new file mode 100644
> index 0000000..dcd0a61
> --- /dev/null
> +++ b/drivers/memory/da8xx-ddrctl.c
> @@ -0,0 +1,77 @@
> +/*
> + * TI da8xx DDR2/mDDR controller driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + *   Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_DDR_CTL_BASE	0xB0000000
> +#define DA8XX_PBBPR_OFFSET	0x00000020
> +#define DA8XX_PBBPR_REG(p)	((p) + DA8XX_PBBPR_OFFSET)
> +
> +#define DA8XX_PBBPR_MAX		0xff
> +
> +static void da8xx_ddrctl_set_pbbpr(void __iomem *ddrctl, struct device
> *dev) +{
> +	struct device_node *node = dev->of_node;
> +	u32 pr_old_count;
> +	int ret;
> +
> +	ret = of_property_read_u32(node, "ti,pr-old-count", &pr_old_count);
> +	if (ret)
> +		return;
> +
> +	if (pr_old_count > DA8XX_PBBPR_MAX) {
> +		dev_warn(dev, "priority raise old counter value too high\n");
> +		return;
> +	}
> +
> +	__raw_writel(pr_old_count, DA8XX_PBBPR_REG(ddrctl));
> +}
> +
> +static int da8xx_ddrctl_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	void __iomem *ddrctl;
> +
> +	ddrctl = ioremap(DA8XX_DDR_CTL_BASE, SZ_256);
> +	if (!ddrctl) {
> +		dev_err(dev, "unable to map memory controller registers\n");
> +		return -EIO;
> +	}
> +
> +	da8xx_ddrctl_set_pbbpr(ddrctl, dev);
> +
> +	iounmap(ddrctl);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id da8xx_ddrctl_of_match[] = {
> +	{ .compatible = "ti,da850-ddrctl", },
> +	{ },
> +};
> +
> +static struct platform_driver da8xx_ddrctl_driver = {
> +	.probe = da8xx_ddrctl_probe,
> +	.driver = {
> +		.name = "da8xx-ddrctl",
> +		.of_match_table = da8xx_ddrctl_of_match,
> +	},
> +};
> +module_platform_driver(da8xx_ddrctl_driver);
> +
> +MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>");
> +MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
> +MODULE_LICENSE("GPL v2");

-- 
Regards,

Laurent Pinchart

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[PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver

[Laurent Pinchart]

Hi Bartosz,

Thank you for the patch.

On Monday 17 Oct 2016 18:30:48 Bartosz Golaszewski wrote:
> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
> 
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
>  .../memory-controllers/ti-da8xx-ddrctl.txt         | 25 +++++++
>  drivers/memory/Kconfig                             |  8 +++
>  drivers/memory/Makefile                            |  1 +
>  drivers/memory/da8xx-ddrctl.c                      | 77 +++++++++++++++++++
>  4 files changed, 111 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> create mode 100644 drivers/memory/da8xx-ddrctl.c
> 
> diff --git
> a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> new file mode 100644
> index 0000000..e340404
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt
> @@ -0,0 +1,25 @@
> +* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory
> controller
> +
> +The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs
> memory
> +maps a set of registers which allow to tweak the controller's behavior.
> +
> +Documentation:
> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> +
> +Required properties:
> +
> +- compatible:		"ti,da850-ddrctl"

Don't you need a reg property ?

> +Optional properties:
> +
> +- ti,pr-old-count:	Priority raise old counter. Specifies the number of
> +			memory transfers after which the DDR2/mDDR memory
> +			controller will elevate the priority of the oldest
> +			command in the command FIFO. Must be between 0-255.

Isn't this a system configuration more than a hardware description ?

> +Example for da850 shown below.
> +
> +ddrctl {
> +	compatible = "ti,da850-ddrctl";
> +	ti,pr-old-count = <0x20>;
> +};
> diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
> index 4b4c0c3..ec80e35 100644
> --- a/drivers/memory/Kconfig
> +++ b/drivers/memory/Kconfig
> @@ -134,6 +134,14 @@ config MTK_SMI
>  	  mainly help enable/disable iommu and control the power domain and
>  	  clocks for each local arbiter.
> 
> +config DA8XX_DDRCTL
> +	bool "Texas Instruments da8xx DDR2/mDDR driver"
> +	depends on ARCH_DAVINCI_DA8XX
> +	help
> +	  This driver is for the DDR2/mDDR Memory Controller present on
> +	  Texas Instruments da8xx SoCs. It's used to tweak various memory
> +	  controller configuration options.
> +
>  source "drivers/memory/samsung/Kconfig"
>  source "drivers/memory/tegra/Kconfig"
> 
> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
> index b20ae38..e88097fb 100644
> --- a/drivers/memory/Makefile
> +++ b/drivers/memory/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_MVEBU_DEVBUS)	+= mvebu-devbus.o
>  obj-$(CONFIG_TEGRA20_MC)	+= tegra20-mc.o
>  obj-$(CONFIG_JZ4780_NEMC)	+= jz4780-nemc.o
>  obj-$(CONFIG_MTK_SMI)		+= mtk-smi.o
> +obj-$(CONFIG_DA8XX_DDRCTL)	+= da8xx-ddrctl.o
> 
>  obj-$(CONFIG_SAMSUNG_MC)	+= samsung/
>  obj-$(CONFIG_TEGRA_MC)		+= tegra/
> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> new file mode 100644
> index 0000000..dcd0a61
> --- /dev/null
> +++ b/drivers/memory/da8xx-ddrctl.c
> @@ -0,0 +1,77 @@
> +/*
> + * TI da8xx DDR2/mDDR controller driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + *   Bartosz Golaszewski <bgolaszewski@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_DDR_CTL_BASE	0xB0000000
> +#define DA8XX_PBBPR_OFFSET	0x00000020
> +#define DA8XX_PBBPR_REG(p)	((p) + DA8XX_PBBPR_OFFSET)
> +
> +#define DA8XX_PBBPR_MAX		0xff
> +
> +static void da8xx_ddrctl_set_pbbpr(void __iomem *ddrctl, struct device
> *dev) +{
> +	struct device_node *node = dev->of_node;
> +	u32 pr_old_count;
> +	int ret;
> +
> +	ret = of_property_read_u32(node, "ti,pr-old-count", &pr_old_count);
> +	if (ret)
> +		return;
> +
> +	if (pr_old_count > DA8XX_PBBPR_MAX) {
> +		dev_warn(dev, "priority raise old counter value too high\n");
> +		return;
> +	}
> +
> +	__raw_writel(pr_old_count, DA8XX_PBBPR_REG(ddrctl));
> +}
> +
> +static int da8xx_ddrctl_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	void __iomem *ddrctl;
> +
> +	ddrctl = ioremap(DA8XX_DDR_CTL_BASE, SZ_256);
> +	if (!ddrctl) {
> +		dev_err(dev, "unable to map memory controller registers\n");
> +		return -EIO;
> +	}
> +
> +	da8xx_ddrctl_set_pbbpr(ddrctl, dev);
> +
> +	iounmap(ddrctl);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id da8xx_ddrctl_of_match[] = {
> +	{ .compatible = "ti,da850-ddrctl", },
> +	{ },
> +};
> +
> +static struct platform_driver da8xx_ddrctl_driver = {
> +	.probe = da8xx_ddrctl_probe,
> +	.driver = {
> +		.name = "da8xx-ddrctl",
> +		.of_match_table = da8xx_ddrctl_of_match,
> +	},
> +};
> +module_platform_driver(da8xx_ddrctl_driver);
> +
> +MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
> +MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver");
> +MODULE_LICENSE("GPL v2");

-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Laurent Pinchart]

Hi Bartosz,

Thank you for the patch.

On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
> Create the driver for the da8xx System Configuration and implement
> support for writing to the three Master Priority registers.
> 
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
>  .../devicetree/bindings/bus/ti,da850-syscfg.txt    |  63 +++++++
>  drivers/bus/Kconfig                                |   8 +
>  drivers/bus/Makefile                               |   2 +
>  drivers/bus/da8xx-syscfg.c                         | 206 ++++++++++++++++++
>  4 files changed, 279 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt create mode
> 100644 drivers/bus/da8xx-syscfg.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
> b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt new file mode
> 100644
> index 0000000..07e5c38
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
> @@ -0,0 +1,63 @@
> +* Device tree bindings for Texas Instruments da8xx system configuration
> driver
> +
> +The system configuration (SYSCFG) module is a system-level module
> containing
> +status and top level control logic required by the device. The system
> +configuration module consists of a set of memory-mapped status and control
> +registers, accessible by the CPU, supporting all of the following system
> +features, and miscellaneous functions and operations.
> +
> +Documentation:
> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> +
> +Required properties:
> +
> +- compatible:		"ti,da850-syscfg"

Don't you need a reg property ?

> +Optional properties:
> +
> +The below properties are used to specify the priority of master
> peripherals.
> +They must be between 0-7 where 0 is the highest priority and 7 is the
> lowest.
> +
> +- ti,pri-arm-i:		ARM_I port priority.
> +
> +- ti,pri-arm-d:		ARM_D port priority.
> +
> +- ti,pri-upp:		uPP port priority.
> +
> +- ti,pri-sata:		SATA port priority.
> +
> +- ti,pri-pru0:		PRU0 port priority.
> +
> +- ti,pri-pru1:		PRU1 port priority.
> +
> +- ti,pri-edma30tc0:	EDMA3_0_TC0 port priority.
> +
> +- ti,pri-edma30tc1:	EDMA3_0_TC1 port priority.
> +
> +- ti,pri-edma31tc0:	EDMA3_1_TC0 port priority.
> +
> +- ti,pri-vpif-dma-0:	VPIF DMA0 port priority.
> +
> +- ti,pri-vpif-dma-1:	VPIF DMA1 port priority.
> +
> +- ti,pri-emac:		EMAC port priority.
> +
> +- ti,pri-usb0cfg:	USB0 CFG port priority.
> +
> +- ti,pri-usb0cdma:	USB0 CDMA port priority.
> +
> +- ti,pri-uhpi:		HPI port priority.
> +
> +- ti,pri-usb1:		USB1 port priority.
> +
> +- ti,pri-lcdc:		LCDC port priority.

I'm afraid this looks more like system configuration than hardware description 
to me.

There was a BoF session about how to support this kind of performance knobs at 
ELCE last week: https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-performance-framework-michael-turquette-baylibre :-)

> +If any of the above properties is absent, the default value will be used as
> +defined in the documentation.
> +
> +Example for da850-lcdk is shown below.
> +
> +mstpri {
> +	compatible = "ti,da850-mstpri";
> +	ti,pri-lcdc = 0;
> +};
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> index 5a2d47c..6276132 100644
> --- a/drivers/bus/Kconfig
> +++ b/drivers/bus/Kconfig
> @@ -165,4 +165,12 @@ config VEXPRESS_CONFIG
>  	help
>  	  Platform configuration infrastructure for the ARM Ltd.
>  	  Versatile Express.
> +
> +config DA8XX_SYSCFG
> +	bool "TI da8xx system configuration driver"
> +	depends on ARCH_DAVINCI_DA8XX
> +	help
> +	  Driver for Texas Instruments da8xx system configuration. Allows to
> +	  adjust various SoC configuration options.
> +
>  endmenu
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> index c6cfa6b..3cba66a 100644
> --- a/drivers/bus/Makefile
> +++ b/drivers/bus/Makefile
> @@ -21,3 +21,5 @@ obj-$(CONFIG_SIMPLE_PM_BUS)	+= simple-pm-bus.o
>  obj-$(CONFIG_TEGRA_ACONNECT)	+= tegra-aconnect.o
>  obj-$(CONFIG_UNIPHIER_SYSTEM_BUS)	+= uniphier-system-bus.o
>  obj-$(CONFIG_VEXPRESS_CONFIG)	+= vexpress-config.o
> +
> +obj-$(CONFIG_DA8XX_SYSCFG)	+= da8xx-syscfg.o
> diff --git a/drivers/bus/da8xx-syscfg.c b/drivers/bus/da8xx-syscfg.c
> new file mode 100644
> index 0000000..8a2cb4f
> --- /dev/null
> +++ b/drivers/bus/da8xx-syscfg.c
> @@ -0,0 +1,206 @@
> +/*
> + * TI da8xx System Configuration driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + *   Bartosz Golaszewski <bgolaszewski@baylibre.com.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_IO_PHYS			0x01c00000ul
> +#define DA8XX_SYSCFG0_BASE		(DA8XX_IO_PHYS + 0x14000)
> +
> +#define DA8XX_MSTPRI0_REG		0x110
> +#define DA8XX_MSTPRI1_REG		0x114
> +#define DA8XX_MSTPRI2_REG		0x118
> +
> +#define DA8XX_MSTPRI_MAX		7
> +
> +struct da8xx_mstpri_descr {
> +	const char *property;
> +	int reg;
> +	int shift;
> +	int mask;
> +};
> +
> +static const struct da8xx_mstpri_descr priorities[] = {
> +	{
> +		.property = "ti,pri-arm-i",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 0,
> +		.mask = 0xfffffff0,
> +	},
> +	{
> +		.property = "ti,pri-arm-d",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 4,
> +		.mask = 0xffffff0f,
> +	},
> +	{
> +		.property = "ti,pri-upp",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 16,
> +		.mask = 0xfff0ffff,
> +	},
> +	{
> +		.property = "ti,pri-sata",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 20,
> +		.mask = 0xff0fffff,
> +	},
> +	{
> +		.property = "ti,pri-pru0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 0,
> +		.mask = 0xfffffff0,
> +	},
> +	{
> +		.property = "ti,pri-pru1",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 4,
> +		.mask = 0xffffff0f,
> +	},
> +	{
> +		.property = "ti,pri-edma30tc0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 8,
> +		.mask = 0xfffff0ff,
> +	},
> +	{
> +		.property = "ti,pri-edma30tc1",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 12,
> +		.mask = 0xffff0fff,
> +	},
> +	{
> +		.property = "ti,pri-edma31tc0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 16,
> +		.mask = 0xfff0ffff,
> +	},
> +	{
> +		.property = "ti,pri-vpif-dma-0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 24,
> +		.mask = 0xf0ffffff,
> +	},
> +	{
> +		.property = "ti,pri-vpif-dma-1",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 28,
> +		.mask = 0x0fffffff,
> +	},
> +	{
> +		.property = "ti,pri-emac",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 0,
> +		.mask = 0xfffffff0,
> +	},
> +	{
> +		.property = "ti,pri-usb0cfg",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 8,
> +		.mask = 0xfffff0ff,
> +	},
> +	{
> +		.property = "ti,pri-usb0cdma",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 12,
> +		.mask = 0xffff0fff,
> +	},
> +	{
> +		.property = "ti,pri-uhpi",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 20,
> +		.mask = 0xff0fffff,
> +	},
> +	{
> +		.property = "ti,pri-usb1",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 24,
> +		.mask = 0xf0ffffff,
> +	},
> +	{
> +		.property = "ti,pri-lcdc",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 28,
> +		.mask = 0x0fffffff,
> +	},
> +};
> +
> +static void da8xx_syscfg_set_mstpri(void __iomem *syscfg0, struct device
> *dev) +{
> +	const struct da8xx_mstpri_descr *pri_descr;
> +	struct device_node *node = dev->of_node;
> +	void __iomem *mstpri;
> +	u32 old_pri, new_pri;
> +	int ret, i;
> +
> +	for (i = 0; i < ARRAY_SIZE(priorities); i++) {
> +		pri_descr = &priorities[i];
> +
> +		ret = of_property_read_u32(node, pri_descr->property, 
&new_pri);
> +		if (ret)
> +			continue;
> +
> +		if (new_pri > DA8XX_MSTPRI_MAX) {
> +			dev_warn(dev,
> +				 "omitting property '%s' - value too high\n",
> +				 pri_descr->property);
> +			continue;
> +		}
> +
> +		mstpri = syscfg0 + pri_descr->reg;
> +		old_pri = __raw_readl(mstpri);
> +		old_pri &= pri_descr->mask;
> +		new_pri <<= pri_descr->shift;
> +		new_pri |= old_pri;
> +
> +		__raw_writel(new_pri, mstpri);
> +	}
> +}
> +
> +static int da8xx_syscfg_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	void __iomem *syscfg0;
> +
> +	syscfg0 = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
> +	if (!syscfg0) {
> +		dev_err(dev, "unable to map syscfg0\n");
> +		return -EIO;
> +	}
> +
> +	da8xx_syscfg_set_mstpri(syscfg0, dev);
> +
> +	iounmap(syscfg0);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id da8xx_syscfg_of_match[] = {
> +	{ .compatible = "ti,da850-syscfg", },
> +	{ },
> +};
> +
> +static struct platform_driver da8xx_syscfg_driver = {
> +	.probe = da8xx_syscfg_probe,
> +	.driver = {
> +		.name = "da8xx-syscfg",
> +		.of_match_table = da8xx_syscfg_of_match,
> +	},
> +};
> +module_platform_driver(da8xx_syscfg_driver);
> +
> +MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
> +MODULE_DESCRIPTION("TI da8xx System Configuration driver");
> +MODULE_LICENSE("GPL v2");

-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Laurent Pinchart]

Hi Bartosz,

Thank you for the patch.

On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
> Create the driver for the da8xx System Configuration and implement
> support for writing to the three Master Priority registers.
> 
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
>  .../devicetree/bindings/bus/ti,da850-syscfg.txt    |  63 +++++++
>  drivers/bus/Kconfig                                |   8 +
>  drivers/bus/Makefile                               |   2 +
>  drivers/bus/da8xx-syscfg.c                         | 206 ++++++++++++++++++
>  4 files changed, 279 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt create mode
> 100644 drivers/bus/da8xx-syscfg.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
> b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt new file mode
> 100644
> index 0000000..07e5c38
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
> @@ -0,0 +1,63 @@
> +* Device tree bindings for Texas Instruments da8xx system configuration
> driver
> +
> +The system configuration (SYSCFG) module is a system-level module
> containing
> +status and top level control logic required by the device. The system
> +configuration module consists of a set of memory-mapped status and control
> +registers, accessible by the CPU, supporting all of the following system
> +features, and miscellaneous functions and operations.
> +
> +Documentation:
> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> +
> +Required properties:
> +
> +- compatible:		"ti,da850-syscfg"

Don't you need a reg property ?

> +Optional properties:
> +
> +The below properties are used to specify the priority of master
> peripherals.
> +They must be between 0-7 where 0 is the highest priority and 7 is the
> lowest.
> +
> +- ti,pri-arm-i:		ARM_I port priority.
> +
> +- ti,pri-arm-d:		ARM_D port priority.
> +
> +- ti,pri-upp:		uPP port priority.
> +
> +- ti,pri-sata:		SATA port priority.
> +
> +- ti,pri-pru0:		PRU0 port priority.
> +
> +- ti,pri-pru1:		PRU1 port priority.
> +
> +- ti,pri-edma30tc0:	EDMA3_0_TC0 port priority.
> +
> +- ti,pri-edma30tc1:	EDMA3_0_TC1 port priority.
> +
> +- ti,pri-edma31tc0:	EDMA3_1_TC0 port priority.
> +
> +- ti,pri-vpif-dma-0:	VPIF DMA0 port priority.
> +
> +- ti,pri-vpif-dma-1:	VPIF DMA1 port priority.
> +
> +- ti,pri-emac:		EMAC port priority.
> +
> +- ti,pri-usb0cfg:	USB0 CFG port priority.
> +
> +- ti,pri-usb0cdma:	USB0 CDMA port priority.
> +
> +- ti,pri-uhpi:		HPI port priority.
> +
> +- ti,pri-usb1:		USB1 port priority.
> +
> +- ti,pri-lcdc:		LCDC port priority.

I'm afraid this looks more like system configuration than hardware description 
to me.

There was a BoF session about how to support this kind of performance knobs at 
ELCE last week: https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-performance-framework-michael-turquette-baylibre :-)

> +If any of the above properties is absent, the default value will be used as
> +defined in the documentation.
> +
> +Example for da850-lcdk is shown below.
> +
> +mstpri {
> +	compatible = "ti,da850-mstpri";
> +	ti,pri-lcdc = 0;
> +};
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> index 5a2d47c..6276132 100644
> --- a/drivers/bus/Kconfig
> +++ b/drivers/bus/Kconfig
> @@ -165,4 +165,12 @@ config VEXPRESS_CONFIG
>  	help
>  	  Platform configuration infrastructure for the ARM Ltd.
>  	  Versatile Express.
> +
> +config DA8XX_SYSCFG
> +	bool "TI da8xx system configuration driver"
> +	depends on ARCH_DAVINCI_DA8XX
> +	help
> +	  Driver for Texas Instruments da8xx system configuration. Allows to
> +	  adjust various SoC configuration options.
> +
>  endmenu
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> index c6cfa6b..3cba66a 100644
> --- a/drivers/bus/Makefile
> +++ b/drivers/bus/Makefile
> @@ -21,3 +21,5 @@ obj-$(CONFIG_SIMPLE_PM_BUS)	+= simple-pm-bus.o
>  obj-$(CONFIG_TEGRA_ACONNECT)	+= tegra-aconnect.o
>  obj-$(CONFIG_UNIPHIER_SYSTEM_BUS)	+= uniphier-system-bus.o
>  obj-$(CONFIG_VEXPRESS_CONFIG)	+= vexpress-config.o
> +
> +obj-$(CONFIG_DA8XX_SYSCFG)	+= da8xx-syscfg.o
> diff --git a/drivers/bus/da8xx-syscfg.c b/drivers/bus/da8xx-syscfg.c
> new file mode 100644
> index 0000000..8a2cb4f
> --- /dev/null
> +++ b/drivers/bus/da8xx-syscfg.c
> @@ -0,0 +1,206 @@
> +/*
> + * TI da8xx System Configuration driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + *   Bartosz Golaszewski <bgolaszewski@baylibre.com.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_IO_PHYS			0x01c00000ul
> +#define DA8XX_SYSCFG0_BASE		(DA8XX_IO_PHYS + 0x14000)
> +
> +#define DA8XX_MSTPRI0_REG		0x110
> +#define DA8XX_MSTPRI1_REG		0x114
> +#define DA8XX_MSTPRI2_REG		0x118
> +
> +#define DA8XX_MSTPRI_MAX		7
> +
> +struct da8xx_mstpri_descr {
> +	const char *property;
> +	int reg;
> +	int shift;
> +	int mask;
> +};
> +
> +static const struct da8xx_mstpri_descr priorities[] = {
> +	{
> +		.property = "ti,pri-arm-i",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 0,
> +		.mask = 0xfffffff0,
> +	},
> +	{
> +		.property = "ti,pri-arm-d",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 4,
> +		.mask = 0xffffff0f,
> +	},
> +	{
> +		.property = "ti,pri-upp",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 16,
> +		.mask = 0xfff0ffff,
> +	},
> +	{
> +		.property = "ti,pri-sata",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 20,
> +		.mask = 0xff0fffff,
> +	},
> +	{
> +		.property = "ti,pri-pru0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 0,
> +		.mask = 0xfffffff0,
> +	},
> +	{
> +		.property = "ti,pri-pru1",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 4,
> +		.mask = 0xffffff0f,
> +	},
> +	{
> +		.property = "ti,pri-edma30tc0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 8,
> +		.mask = 0xfffff0ff,
> +	},
> +	{
> +		.property = "ti,pri-edma30tc1",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 12,
> +		.mask = 0xffff0fff,
> +	},
> +	{
> +		.property = "ti,pri-edma31tc0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 16,
> +		.mask = 0xfff0ffff,
> +	},
> +	{
> +		.property = "ti,pri-vpif-dma-0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 24,
> +		.mask = 0xf0ffffff,
> +	},
> +	{
> +		.property = "ti,pri-vpif-dma-1",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 28,
> +		.mask = 0x0fffffff,
> +	},
> +	{
> +		.property = "ti,pri-emac",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 0,
> +		.mask = 0xfffffff0,
> +	},
> +	{
> +		.property = "ti,pri-usb0cfg",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 8,
> +		.mask = 0xfffff0ff,
> +	},
> +	{
> +		.property = "ti,pri-usb0cdma",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 12,
> +		.mask = 0xffff0fff,
> +	},
> +	{
> +		.property = "ti,pri-uhpi",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 20,
> +		.mask = 0xff0fffff,
> +	},
> +	{
> +		.property = "ti,pri-usb1",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 24,
> +		.mask = 0xf0ffffff,
> +	},
> +	{
> +		.property = "ti,pri-lcdc",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 28,
> +		.mask = 0x0fffffff,
> +	},
> +};
> +
> +static void da8xx_syscfg_set_mstpri(void __iomem *syscfg0, struct device
> *dev) +{
> +	const struct da8xx_mstpri_descr *pri_descr;
> +	struct device_node *node = dev->of_node;
> +	void __iomem *mstpri;
> +	u32 old_pri, new_pri;
> +	int ret, i;
> +
> +	for (i = 0; i < ARRAY_SIZE(priorities); i++) {
> +		pri_descr = &priorities[i];
> +
> +		ret = of_property_read_u32(node, pri_descr->property, 
&new_pri);
> +		if (ret)
> +			continue;
> +
> +		if (new_pri > DA8XX_MSTPRI_MAX) {
> +			dev_warn(dev,
> +				 "omitting property '%s' - value too high\n",
> +				 pri_descr->property);
> +			continue;
> +		}
> +
> +		mstpri = syscfg0 + pri_descr->reg;
> +		old_pri = __raw_readl(mstpri);
> +		old_pri &= pri_descr->mask;
> +		new_pri <<= pri_descr->shift;
> +		new_pri |= old_pri;
> +
> +		__raw_writel(new_pri, mstpri);
> +	}
> +}
> +
> +static int da8xx_syscfg_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	void __iomem *syscfg0;
> +
> +	syscfg0 = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
> +	if (!syscfg0) {
> +		dev_err(dev, "unable to map syscfg0\n");
> +		return -EIO;
> +	}
> +
> +	da8xx_syscfg_set_mstpri(syscfg0, dev);
> +
> +	iounmap(syscfg0);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id da8xx_syscfg_of_match[] = {
> +	{ .compatible = "ti,da850-syscfg", },
> +	{ },
> +};
> +
> +static struct platform_driver da8xx_syscfg_driver = {
> +	.probe = da8xx_syscfg_probe,
> +	.driver = {
> +		.name = "da8xx-syscfg",
> +		.of_match_table = da8xx_syscfg_of_match,
> +	},
> +};
> +module_platform_driver(da8xx_syscfg_driver);
> +
> +MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
> +MODULE_DESCRIPTION("TI da8xx System Configuration driver");
> +MODULE_LICENSE("GPL v2");

-- 
Regards,

Laurent Pinchart

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[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Laurent Pinchart]

Hi Bartosz,

Thank you for the patch.

On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
> Create the driver for the da8xx System Configuration and implement
> support for writing to the three Master Priority registers.
> 
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
>  .../devicetree/bindings/bus/ti,da850-syscfg.txt    |  63 +++++++
>  drivers/bus/Kconfig                                |   8 +
>  drivers/bus/Makefile                               |   2 +
>  drivers/bus/da8xx-syscfg.c                         | 206 ++++++++++++++++++
>  4 files changed, 279 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt create mode
> 100644 drivers/bus/da8xx-syscfg.c
> 
> diff --git a/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
> b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt new file mode
> 100644
> index 0000000..07e5c38
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/ti,da850-syscfg.txt
> @@ -0,0 +1,63 @@
> +* Device tree bindings for Texas Instruments da8xx system configuration
> driver
> +
> +The system configuration (SYSCFG) module is a system-level module
> containing
> +status and top level control logic required by the device. The system
> +configuration module consists of a set of memory-mapped status and control
> +registers, accessible by the CPU, supporting all of the following system
> +features, and miscellaneous functions and operations.
> +
> +Documentation:
> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> +
> +Required properties:
> +
> +- compatible:		"ti,da850-syscfg"

Don't you need a reg property ?

> +Optional properties:
> +
> +The below properties are used to specify the priority of master
> peripherals.
> +They must be between 0-7 where 0 is the highest priority and 7 is the
> lowest.
> +
> +- ti,pri-arm-i:		ARM_I port priority.
> +
> +- ti,pri-arm-d:		ARM_D port priority.
> +
> +- ti,pri-upp:		uPP port priority.
> +
> +- ti,pri-sata:		SATA port priority.
> +
> +- ti,pri-pru0:		PRU0 port priority.
> +
> +- ti,pri-pru1:		PRU1 port priority.
> +
> +- ti,pri-edma30tc0:	EDMA3_0_TC0 port priority.
> +
> +- ti,pri-edma30tc1:	EDMA3_0_TC1 port priority.
> +
> +- ti,pri-edma31tc0:	EDMA3_1_TC0 port priority.
> +
> +- ti,pri-vpif-dma-0:	VPIF DMA0 port priority.
> +
> +- ti,pri-vpif-dma-1:	VPIF DMA1 port priority.
> +
> +- ti,pri-emac:		EMAC port priority.
> +
> +- ti,pri-usb0cfg:	USB0 CFG port priority.
> +
> +- ti,pri-usb0cdma:	USB0 CDMA port priority.
> +
> +- ti,pri-uhpi:		HPI port priority.
> +
> +- ti,pri-usb1:		USB1 port priority.
> +
> +- ti,pri-lcdc:		LCDC port priority.

I'm afraid this looks more like system configuration than hardware description 
to me.

There was a BoF session about how to support this kind of performance knobs at 
ELCE last week: https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-performance-framework-michael-turquette-baylibre :-)

> +If any of the above properties is absent, the default value will be used as
> +defined in the documentation.
> +
> +Example for da850-lcdk is shown below.
> +
> +mstpri {
> +	compatible = "ti,da850-mstpri";
> +	ti,pri-lcdc = 0;
> +};
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> index 5a2d47c..6276132 100644
> --- a/drivers/bus/Kconfig
> +++ b/drivers/bus/Kconfig
> @@ -165,4 +165,12 @@ config VEXPRESS_CONFIG
>  	help
>  	  Platform configuration infrastructure for the ARM Ltd.
>  	  Versatile Express.
> +
> +config DA8XX_SYSCFG
> +	bool "TI da8xx system configuration driver"
> +	depends on ARCH_DAVINCI_DA8XX
> +	help
> +	  Driver for Texas Instruments da8xx system configuration. Allows to
> +	  adjust various SoC configuration options.
> +
>  endmenu
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> index c6cfa6b..3cba66a 100644
> --- a/drivers/bus/Makefile
> +++ b/drivers/bus/Makefile
> @@ -21,3 +21,5 @@ obj-$(CONFIG_SIMPLE_PM_BUS)	+= simple-pm-bus.o
>  obj-$(CONFIG_TEGRA_ACONNECT)	+= tegra-aconnect.o
>  obj-$(CONFIG_UNIPHIER_SYSTEM_BUS)	+= uniphier-system-bus.o
>  obj-$(CONFIG_VEXPRESS_CONFIG)	+= vexpress-config.o
> +
> +obj-$(CONFIG_DA8XX_SYSCFG)	+= da8xx-syscfg.o
> diff --git a/drivers/bus/da8xx-syscfg.c b/drivers/bus/da8xx-syscfg.c
> new file mode 100644
> index 0000000..8a2cb4f
> --- /dev/null
> +++ b/drivers/bus/da8xx-syscfg.c
> @@ -0,0 +1,206 @@
> +/*
> + * TI da8xx System Configuration driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + *   Bartosz Golaszewski <bgolaszewski@baylibre.com.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_IO_PHYS			0x01c00000ul
> +#define DA8XX_SYSCFG0_BASE		(DA8XX_IO_PHYS + 0x14000)
> +
> +#define DA8XX_MSTPRI0_REG		0x110
> +#define DA8XX_MSTPRI1_REG		0x114
> +#define DA8XX_MSTPRI2_REG		0x118
> +
> +#define DA8XX_MSTPRI_MAX		7
> +
> +struct da8xx_mstpri_descr {
> +	const char *property;
> +	int reg;
> +	int shift;
> +	int mask;
> +};
> +
> +static const struct da8xx_mstpri_descr priorities[] = {
> +	{
> +		.property = "ti,pri-arm-i",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 0,
> +		.mask = 0xfffffff0,
> +	},
> +	{
> +		.property = "ti,pri-arm-d",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 4,
> +		.mask = 0xffffff0f,
> +	},
> +	{
> +		.property = "ti,pri-upp",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 16,
> +		.mask = 0xfff0ffff,
> +	},
> +	{
> +		.property = "ti,pri-sata",
> +		.reg = DA8XX_MSTPRI0_REG,
> +		.shift = 20,
> +		.mask = 0xff0fffff,
> +	},
> +	{
> +		.property = "ti,pri-pru0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 0,
> +		.mask = 0xfffffff0,
> +	},
> +	{
> +		.property = "ti,pri-pru1",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 4,
> +		.mask = 0xffffff0f,
> +	},
> +	{
> +		.property = "ti,pri-edma30tc0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 8,
> +		.mask = 0xfffff0ff,
> +	},
> +	{
> +		.property = "ti,pri-edma30tc1",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 12,
> +		.mask = 0xffff0fff,
> +	},
> +	{
> +		.property = "ti,pri-edma31tc0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 16,
> +		.mask = 0xfff0ffff,
> +	},
> +	{
> +		.property = "ti,pri-vpif-dma-0",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 24,
> +		.mask = 0xf0ffffff,
> +	},
> +	{
> +		.property = "ti,pri-vpif-dma-1",
> +		.reg = DA8XX_MSTPRI1_REG,
> +		.shift = 28,
> +		.mask = 0x0fffffff,
> +	},
> +	{
> +		.property = "ti,pri-emac",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 0,
> +		.mask = 0xfffffff0,
> +	},
> +	{
> +		.property = "ti,pri-usb0cfg",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 8,
> +		.mask = 0xfffff0ff,
> +	},
> +	{
> +		.property = "ti,pri-usb0cdma",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 12,
> +		.mask = 0xffff0fff,
> +	},
> +	{
> +		.property = "ti,pri-uhpi",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 20,
> +		.mask = 0xff0fffff,
> +	},
> +	{
> +		.property = "ti,pri-usb1",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 24,
> +		.mask = 0xf0ffffff,
> +	},
> +	{
> +		.property = "ti,pri-lcdc",
> +		.reg = DA8XX_MSTPRI2_REG,
> +		.shift = 28,
> +		.mask = 0x0fffffff,
> +	},
> +};
> +
> +static void da8xx_syscfg_set_mstpri(void __iomem *syscfg0, struct device
> *dev) +{
> +	const struct da8xx_mstpri_descr *pri_descr;
> +	struct device_node *node = dev->of_node;
> +	void __iomem *mstpri;
> +	u32 old_pri, new_pri;
> +	int ret, i;
> +
> +	for (i = 0; i < ARRAY_SIZE(priorities); i++) {
> +		pri_descr = &priorities[i];
> +
> +		ret = of_property_read_u32(node, pri_descr->property, 
&new_pri);
> +		if (ret)
> +			continue;
> +
> +		if (new_pri > DA8XX_MSTPRI_MAX) {
> +			dev_warn(dev,
> +				 "omitting property '%s' - value too high\n",
> +				 pri_descr->property);
> +			continue;
> +		}
> +
> +		mstpri = syscfg0 + pri_descr->reg;
> +		old_pri = __raw_readl(mstpri);
> +		old_pri &= pri_descr->mask;
> +		new_pri <<= pri_descr->shift;
> +		new_pri |= old_pri;
> +
> +		__raw_writel(new_pri, mstpri);
> +	}
> +}
> +
> +static int da8xx_syscfg_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	void __iomem *syscfg0;
> +
> +	syscfg0 = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
> +	if (!syscfg0) {
> +		dev_err(dev, "unable to map syscfg0\n");
> +		return -EIO;
> +	}
> +
> +	da8xx_syscfg_set_mstpri(syscfg0, dev);
> +
> +	iounmap(syscfg0);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id da8xx_syscfg_of_match[] = {
> +	{ .compatible = "ti,da850-syscfg", },
> +	{ },
> +};
> +
> +static struct platform_driver da8xx_syscfg_driver = {
> +	.probe = da8xx_syscfg_probe,
> +	.driver = {
> +		.name = "da8xx-syscfg",
> +		.of_match_table = da8xx_syscfg_of_match,
> +	},
> +};
> +module_platform_driver(da8xx_syscfg_driver);
> +
> +MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
> +MODULE_DESCRIPTION("TI da8xx System Configuration driver");
> +MODULE_LICENSE("GPL v2");

-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Bartosz Golaszewski]

2016-10-18 22:49 GMT+02:00 Laurent Pinchart <laurent.pinchart@ideasonboard.com>:
> Hi Bartosz,
>
> Thank you for the patch.
>
> On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> Create the driver for the da8xx System Configuration and implement
>> support for writing to the three Master Priority registers.
>>
>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

[snip]

>> +
>> +Documentation:
>> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
>> +
>> +Required properties:
>> +
>> +- compatible:                "ti,da850-syscfg"
>
> Don't you need a reg property ?
>

Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].

>> +Optional properties:
>> +
>> +The below properties are used to specify the priority of master
>> peripherals.
>> +They must be between 0-7 where 0 is the highest priority and 7 is the
>> lowest.
>> +
>> +- ti,pri-arm-i:              ARM_I port priority.
>> +
>> +- ti,pri-arm-d:              ARM_D port priority.
>> +
>> +- ti,pri-upp:                uPP port priority.
>> +
>> +- ti,pri-sata:               SATA port priority.
>> +
>> +- ti,pri-pru0:               PRU0 port priority.
>> +
>> +- ti,pri-pru1:               PRU1 port priority.
>> +
>> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
>> +
>> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
>> +
>> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
>> +
>> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
>> +
>> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
>> +
>> +- ti,pri-emac:               EMAC port priority.
>> +
>> +- ti,pri-usb0cfg:    USB0 CFG port priority.
>> +
>> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
>> +
>> +- ti,pri-uhpi:               HPI port priority.
>> +
>> +- ti,pri-usb1:               USB1 port priority.
>> +
>> +- ti,pri-lcdc:               LCDC port priority.
>
> I'm afraid this looks more like system configuration than hardware description
> to me.
>

While you're certainly right, this approach is already implemented in
several other memory and bus drivers and it was also suggested by
Sekhar in one of the tilcdc rev1 threads. There's also no real
alternative that I know of.

> There was a BoF session about how to support this kind of performance knobs at
> ELCE last week: https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-performance-framework-michael-turquette-baylibre :-)
>

I know, I was there. ;)

Unfortunately it was just a discussion about potential approaches -
there's no code yet.

Thanks,
Bartosz

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Bartosz Golaszewski]

2016-10-18 22:49 GMT+02:00 Laurent Pinchart <laurent.pinchart@ideasonboard.com>:
> Hi Bartosz,
>
> Thank you for the patch.
>
> On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> Create the driver for the da8xx System Configuration and implement
>> support for writing to the three Master Priority registers.
>>
>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

[snip]

>> +
>> +Documentation:
>> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
>> +
>> +Required properties:
>> +
>> +- compatible:                "ti,da850-syscfg"
>
> Don't you need a reg property ?
>

Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].

>> +Optional properties:
>> +
>> +The below properties are used to specify the priority of master
>> peripherals.
>> +They must be between 0-7 where 0 is the highest priority and 7 is the
>> lowest.
>> +
>> +- ti,pri-arm-i:              ARM_I port priority.
>> +
>> +- ti,pri-arm-d:              ARM_D port priority.
>> +
>> +- ti,pri-upp:                uPP port priority.
>> +
>> +- ti,pri-sata:               SATA port priority.
>> +
>> +- ti,pri-pru0:               PRU0 port priority.
>> +
>> +- ti,pri-pru1:               PRU1 port priority.
>> +
>> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
>> +
>> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
>> +
>> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
>> +
>> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
>> +
>> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
>> +
>> +- ti,pri-emac:               EMAC port priority.
>> +
>> +- ti,pri-usb0cfg:    USB0 CFG port priority.
>> +
>> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
>> +
>> +- ti,pri-uhpi:               HPI port priority.
>> +
>> +- ti,pri-usb1:               USB1 port priority.
>> +
>> +- ti,pri-lcdc:               LCDC port priority.
>
> I'm afraid this looks more like system configuration than hardware description
> to me.
>

While you're certainly right, this approach is already implemented in
several other memory and bus drivers and it was also suggested by
Sekhar in one of the tilcdc rev1 threads. There's also no real
alternative that I know of.

> There was a BoF session about how to support this kind of performance knobs at
> ELCE last week: https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-performance-framework-michael-turquette-baylibre :-)
>

I know, I was there. ;)

Unfortunately it was just a discussion about potential approaches -
there's no code yet.

Thanks,
Bartosz
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Bartosz Golaszewski]

2016-10-18 22:49 GMT+02:00 Laurent Pinchart <laurent.pinchart@ideasonboard.com>:
> Hi Bartosz,
>
> Thank you for the patch.
>
> On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> Create the driver for the da8xx System Configuration and implement
>> support for writing to the three Master Priority registers.
>>
>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

[snip]

>> +
>> +Documentation:
>> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
>> +
>> +Required properties:
>> +
>> +- compatible:                "ti,da850-syscfg"
>
> Don't you need a reg property ?
>

Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].

>> +Optional properties:
>> +
>> +The below properties are used to specify the priority of master
>> peripherals.
>> +They must be between 0-7 where 0 is the highest priority and 7 is the
>> lowest.
>> +
>> +- ti,pri-arm-i:              ARM_I port priority.
>> +
>> +- ti,pri-arm-d:              ARM_D port priority.
>> +
>> +- ti,pri-upp:                uPP port priority.
>> +
>> +- ti,pri-sata:               SATA port priority.
>> +
>> +- ti,pri-pru0:               PRU0 port priority.
>> +
>> +- ti,pri-pru1:               PRU1 port priority.
>> +
>> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
>> +
>> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
>> +
>> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
>> +
>> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
>> +
>> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
>> +
>> +- ti,pri-emac:               EMAC port priority.
>> +
>> +- ti,pri-usb0cfg:    USB0 CFG port priority.
>> +
>> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
>> +
>> +- ti,pri-uhpi:               HPI port priority.
>> +
>> +- ti,pri-usb1:               USB1 port priority.
>> +
>> +- ti,pri-lcdc:               LCDC port priority.
>
> I'm afraid this looks more like system configuration than hardware description
> to me.
>

While you're certainly right, this approach is already implemented in
several other memory and bus drivers and it was also suggested by
Sekhar in one of the tilcdc rev1 threads. There's also no real
alternative that I know of.

> There was a BoF session about how to support this kind of performance knobs at
> ELCE last week: https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-performance-framework-michael-turquette-baylibre :-)
>

I know, I was there. ;)

Unfortunately it was just a discussion about potential approaches -
there's no code yet.

Thanks,
Bartosz

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Laurent Pinchart]

Hi Bartosz,

On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
> > On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
> >> Create the driver for the da8xx System Configuration and implement
> >> support for writing to the three Master Priority registers.
> >> 
> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> 
> [snip]
> 
> >> +
> >> +Documentation:
> >> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> >> +
> >> +Required properties:
> >> +
> >> +- compatible:                "ti,da850-syscfg"
> > 
> > Don't you need a reg property ?
> 
> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
> 
> >> +Optional properties:
> >> +
> >> +The below properties are used to specify the priority of master
> >> peripherals.
> >> +They must be between 0-7 where 0 is the highest priority and 7 is the
> >> lowest.
> >> +
> >> +- ti,pri-arm-i:              ARM_I port priority.
> >> +
> >> +- ti,pri-arm-d:              ARM_D port priority.
> >> +
> >> +- ti,pri-upp:                uPP port priority.
> >> +
> >> +- ti,pri-sata:               SATA port priority.
> >> +
> >> +- ti,pri-pru0:               PRU0 port priority.
> >> +
> >> +- ti,pri-pru1:               PRU1 port priority.
> >> +
> >> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
> >> +
> >> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
> >> +
> >> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
> >> +
> >> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
> >> +
> >> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
> >> +
> >> +- ti,pri-emac:               EMAC port priority.
> >> +
> >> +- ti,pri-usb0cfg:    USB0 CFG port priority.
> >> +
> >> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
> >> +
> >> +- ti,pri-uhpi:               HPI port priority.
> >> +
> >> +- ti,pri-usb1:               USB1 port priority.
> >> +
> >> +- ti,pri-lcdc:               LCDC port priority.
> > 
> > I'm afraid this looks more like system configuration than hardware
> > description to me.
> 
> While you're certainly right, this approach is already implemented in
> several other memory and bus drivers and it was also suggested by
> Sekhar in one of the tilcdc rev1 threads. There's also no real
> alternative that I know of.

The fact that other drivers get it wrong is no excuse for copying them :-)

> > There was a BoF session about how to support this kind of performance
> > knobs at ELCE last week:
> > https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-perfor
> > mance-framework-michael-turquette-baylibre :-)
>
> I know, I was there. ;)

That's why I mentioned it :-)

> Unfortunately it was just a discussion about potential approaches -
> there's no code yet.

Patches are welcome ;-)

-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Laurent Pinchart]

Hi Bartosz,

On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
> > On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
> >> Create the driver for the da8xx System Configuration and implement
> >> support for writing to the three Master Priority registers.
> >> 
> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> 
> [snip]
> 
> >> +
> >> +Documentation:
> >> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> >> +
> >> +Required properties:
> >> +
> >> +- compatible:                "ti,da850-syscfg"
> > 
> > Don't you need a reg property ?
> 
> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
> 
> >> +Optional properties:
> >> +
> >> +The below properties are used to specify the priority of master
> >> peripherals.
> >> +They must be between 0-7 where 0 is the highest priority and 7 is the
> >> lowest.
> >> +
> >> +- ti,pri-arm-i:              ARM_I port priority.
> >> +
> >> +- ti,pri-arm-d:              ARM_D port priority.
> >> +
> >> +- ti,pri-upp:                uPP port priority.
> >> +
> >> +- ti,pri-sata:               SATA port priority.
> >> +
> >> +- ti,pri-pru0:               PRU0 port priority.
> >> +
> >> +- ti,pri-pru1:               PRU1 port priority.
> >> +
> >> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
> >> +
> >> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
> >> +
> >> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
> >> +
> >> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
> >> +
> >> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
> >> +
> >> +- ti,pri-emac:               EMAC port priority.
> >> +
> >> +- ti,pri-usb0cfg:    USB0 CFG port priority.
> >> +
> >> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
> >> +
> >> +- ti,pri-uhpi:               HPI port priority.
> >> +
> >> +- ti,pri-usb1:               USB1 port priority.
> >> +
> >> +- ti,pri-lcdc:               LCDC port priority.
> > 
> > I'm afraid this looks more like system configuration than hardware
> > description to me.
> 
> While you're certainly right, this approach is already implemented in
> several other memory and bus drivers and it was also suggested by
> Sekhar in one of the tilcdc rev1 threads. There's also no real
> alternative that I know of.

The fact that other drivers get it wrong is no excuse for copying them :-)

> > There was a BoF session about how to support this kind of performance
> > knobs at ELCE last week:
> > https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-perfor
> > mance-framework-michael-turquette-baylibre :-)
>
> I know, I was there. ;)

That's why I mentioned it :-)

> Unfortunately it was just a discussion about potential approaches -
> there's no code yet.

Patches are welcome ;-)

-- 
Regards,

Laurent Pinchart

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Laurent Pinchart]

Hi Bartosz,

On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
> > On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
> >> Create the driver for the da8xx System Configuration and implement
> >> support for writing to the three Master Priority registers.
> >> 
> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> 
> [snip]
> 
> >> +
> >> +Documentation:
> >> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> >> +
> >> +Required properties:
> >> +
> >> +- compatible:                "ti,da850-syscfg"
> > 
> > Don't you need a reg property ?
> 
> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
> 
> >> +Optional properties:
> >> +
> >> +The below properties are used to specify the priority of master
> >> peripherals.
> >> +They must be between 0-7 where 0 is the highest priority and 7 is the
> >> lowest.
> >> +
> >> +- ti,pri-arm-i:              ARM_I port priority.
> >> +
> >> +- ti,pri-arm-d:              ARM_D port priority.
> >> +
> >> +- ti,pri-upp:                uPP port priority.
> >> +
> >> +- ti,pri-sata:               SATA port priority.
> >> +
> >> +- ti,pri-pru0:               PRU0 port priority.
> >> +
> >> +- ti,pri-pru1:               PRU1 port priority.
> >> +
> >> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
> >> +
> >> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
> >> +
> >> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
> >> +
> >> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
> >> +
> >> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
> >> +
> >> +- ti,pri-emac:               EMAC port priority.
> >> +
> >> +- ti,pri-usb0cfg:    USB0 CFG port priority.
> >> +
> >> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
> >> +
> >> +- ti,pri-uhpi:               HPI port priority.
> >> +
> >> +- ti,pri-usb1:               USB1 port priority.
> >> +
> >> +- ti,pri-lcdc:               LCDC port priority.
> > 
> > I'm afraid this looks more like system configuration than hardware
> > description to me.
> 
> While you're certainly right, this approach is already implemented in
> several other memory and bus drivers and it was also suggested by
> Sekhar in one of the tilcdc rev1 threads. There's also no real
> alternative that I know of.

The fact that other drivers get it wrong is no excuse for copying them :-)

> > There was a BoF session about how to support this kind of performance
> > knobs at ELCE last week:
> > https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-perfor
> > mance-framework-michael-turquette-baylibre :-)
>
> I know, I was there. ;)

That's why I mentioned it :-)

> Unfortunately it was just a discussion about potential approaches -
> there's no code yet.

Patches are welcome ;-)

-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Kevin Hilman]

+Arnd, Olof

Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:

> Hi Bartosz,
>
> On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
>> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
>> > On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> >> Create the driver for the da8xx System Configuration and implement
>> >> support for writing to the three Master Priority registers.
>> >> 
>> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>> 
>> [snip]
>> 
>> >> +
>> >> +Documentation:
>> >> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
>> >> +
>> >> +Required properties:
>> >> +
>> >> +- compatible:                "ti,da850-syscfg"
>> > 
>> > Don't you need a reg property ?
>> 
>> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
>> 
>> >> +Optional properties:
>> >> +
>> >> +The below properties are used to specify the priority of master
>> >> peripherals.
>> >> +They must be between 0-7 where 0 is the highest priority and 7 is the
>> >> lowest.
>> >> +
>> >> +- ti,pri-arm-i:              ARM_I port priority.
>> >> +
>> >> +- ti,pri-arm-d:              ARM_D port priority.
>> >> +
>> >> +- ti,pri-upp:                uPP port priority.
>> >> +
>> >> +- ti,pri-sata:               SATA port priority.
>> >> +
>> >> +- ti,pri-pru0:               PRU0 port priority.
>> >> +
>> >> +- ti,pri-pru1:               PRU1 port priority.
>> >> +
>> >> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
>> >> +
>> >> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
>> >> +
>> >> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
>> >> +
>> >> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
>> >> +
>> >> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
>> >> +
>> >> +- ti,pri-emac:               EMAC port priority.
>> >> +
>> >> +- ti,pri-usb0cfg:    USB0 CFG port priority.
>> >> +
>> >> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
>> >> +
>> >> +- ti,pri-uhpi:               HPI port priority.
>> >> +
>> >> +- ti,pri-usb1:               USB1 port priority.
>> >> +
>> >> +- ti,pri-lcdc:               LCDC port priority.
>> > 
>> > I'm afraid this looks more like system configuration than hardware
>> > description to me.
>> 
>> While you're certainly right, this approach is already implemented in
>> several other memory and bus drivers and it was also suggested by
>> Sekhar in one of the tilcdc rev1 threads. There's also no real
>> alternative that I know of.
>
> The fact that other drivers get it wrong is no excuse for copying them :-)

What exactly is "wrong" with the way other drivers are doing it?

I'm sure there may be other ideas, and possibly some better ones, but
that doesn't make it wrong, and doesn't change he fact that the kernel
has existing drivers SoC-bus-specific system performance knobs like
this.

>> > There was a BoF session about how to support this kind of performance
>> > knobs at ELCE last week:
>> > https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-perfor
>> > mance-framework-michael-turquette-baylibre :-)
>>
>> Unfortunately it was just a discussion about potential approaches -
>> there's no code yet.
>
> Patches are welcome ;-)

Any generic perf framework will have to build on the HW-specifics of
individual busses, so IMO, the lack of a generic performance
framework/knobs should not be a reason to block the inclusion of any
bus-specific knobs.

I guess this ultimately would go though arm-soc, so I've added Arnd &
Olof to the thread.

Kevin

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Kevin Hilman]

+Arnd, Olof

Laurent Pinchart <laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org> writes:

> Hi Bartosz,
>
> On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
>> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
>> > On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> >> Create the driver for the da8xx System Configuration and implement
>> >> support for writing to the three Master Priority registers.
>> >> 
>> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
>> 
>> [snip]
>> 
>> >> +
>> >> +Documentation:
>> >> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
>> >> +
>> >> +Required properties:
>> >> +
>> >> +- compatible:                "ti,da850-syscfg"
>> > 
>> > Don't you need a reg property ?
>> 
>> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
>> 
>> >> +Optional properties:
>> >> +
>> >> +The below properties are used to specify the priority of master
>> >> peripherals.
>> >> +They must be between 0-7 where 0 is the highest priority and 7 is the
>> >> lowest.
>> >> +
>> >> +- ti,pri-arm-i:              ARM_I port priority.
>> >> +
>> >> +- ti,pri-arm-d:              ARM_D port priority.
>> >> +
>> >> +- ti,pri-upp:                uPP port priority.
>> >> +
>> >> +- ti,pri-sata:               SATA port priority.
>> >> +
>> >> +- ti,pri-pru0:               PRU0 port priority.
>> >> +
>> >> +- ti,pri-pru1:               PRU1 port priority.
>> >> +
>> >> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
>> >> +
>> >> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
>> >> +
>> >> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
>> >> +
>> >> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
>> >> +
>> >> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
>> >> +
>> >> +- ti,pri-emac:               EMAC port priority.
>> >> +
>> >> +- ti,pri-usb0cfg:    USB0 CFG port priority.
>> >> +
>> >> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
>> >> +
>> >> +- ti,pri-uhpi:               HPI port priority.
>> >> +
>> >> +- ti,pri-usb1:               USB1 port priority.
>> >> +
>> >> +- ti,pri-lcdc:               LCDC port priority.
>> > 
>> > I'm afraid this looks more like system configuration than hardware
>> > description to me.
>> 
>> While you're certainly right, this approach is already implemented in
>> several other memory and bus drivers and it was also suggested by
>> Sekhar in one of the tilcdc rev1 threads. There's also no real
>> alternative that I know of.
>
> The fact that other drivers get it wrong is no excuse for copying them :-)

What exactly is "wrong" with the way other drivers are doing it?

I'm sure there may be other ideas, and possibly some better ones, but
that doesn't make it wrong, and doesn't change he fact that the kernel
has existing drivers SoC-bus-specific system performance knobs like
this.

>> > There was a BoF session about how to support this kind of performance
>> > knobs at ELCE last week:
>> > https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-perfor
>> > mance-framework-michael-turquette-baylibre :-)
>>
>> Unfortunately it was just a discussion about potential approaches -
>> there's no code yet.
>
> Patches are welcome ;-)

Any generic perf framework will have to build on the HW-specifics of
individual busses, so IMO, the lack of a generic performance
framework/knobs should not be a reason to block the inclusion of any
bus-specific knobs.

I guess this ultimately would go though arm-soc, so I've added Arnd &
Olof to the thread.

Kevin
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[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Kevin Hilman]

+Arnd, Olof

Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:

> Hi Bartosz,
>
> On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
>> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
>> > On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> >> Create the driver for the da8xx System Configuration and implement
>> >> support for writing to the three Master Priority registers.
>> >> 
>> >> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>> 
>> [snip]
>> 
>> >> +
>> >> +Documentation:
>> >> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
>> >> +
>> >> +Required properties:
>> >> +
>> >> +- compatible:                "ti,da850-syscfg"
>> > 
>> > Don't you need a reg property ?
>> 
>> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
>> 
>> >> +Optional properties:
>> >> +
>> >> +The below properties are used to specify the priority of master
>> >> peripherals.
>> >> +They must be between 0-7 where 0 is the highest priority and 7 is the
>> >> lowest.
>> >> +
>> >> +- ti,pri-arm-i:              ARM_I port priority.
>> >> +
>> >> +- ti,pri-arm-d:              ARM_D port priority.
>> >> +
>> >> +- ti,pri-upp:                uPP port priority.
>> >> +
>> >> +- ti,pri-sata:               SATA port priority.
>> >> +
>> >> +- ti,pri-pru0:               PRU0 port priority.
>> >> +
>> >> +- ti,pri-pru1:               PRU1 port priority.
>> >> +
>> >> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
>> >> +
>> >> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
>> >> +
>> >> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
>> >> +
>> >> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
>> >> +
>> >> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
>> >> +
>> >> +- ti,pri-emac:               EMAC port priority.
>> >> +
>> >> +- ti,pri-usb0cfg:    USB0 CFG port priority.
>> >> +
>> >> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
>> >> +
>> >> +- ti,pri-uhpi:               HPI port priority.
>> >> +
>> >> +- ti,pri-usb1:               USB1 port priority.
>> >> +
>> >> +- ti,pri-lcdc:               LCDC port priority.
>> > 
>> > I'm afraid this looks more like system configuration than hardware
>> > description to me.
>> 
>> While you're certainly right, this approach is already implemented in
>> several other memory and bus drivers and it was also suggested by
>> Sekhar in one of the tilcdc rev1 threads. There's also no real
>> alternative that I know of.
>
> The fact that other drivers get it wrong is no excuse for copying them :-)

What exactly is "wrong" with the way other drivers are doing it?

I'm sure there may be other ideas, and possibly some better ones, but
that doesn't make it wrong, and doesn't change he fact that the kernel
has existing drivers SoC-bus-specific system performance knobs like
this.

>> > There was a BoF session about how to support this kind of performance
>> > knobs at ELCE last week:
>> > https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-perfor
>> > mance-framework-michael-turquette-baylibre :-)
>>
>> Unfortunately it was just a discussion about potential approaches -
>> there's no code yet.
>
> Patches are welcome ;-)

Any generic perf framework will have to build on the HW-specifics of
individual busses, so IMO, the lack of a generic performance
framework/knobs should not be a reason to block the inclusion of any
bus-specific knobs.

I guess this ultimately would go though arm-soc, so I've added Arnd &
Olof to the thread.

Kevin

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Laurent Pinchart]

Hi Kevin,

On Thursday 20 Oct 2016 09:57:51 Kevin Hilman wrote:
> Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:
> > On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
> >> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
> >>> On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
> >>>> Create the driver for the da8xx System Configuration and implement
> >>>> support for writing to the three Master Priority registers.
> >>>> 
> >>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >> 
> >> [snip]
> >> 
> >>>> +
> >>>> +Documentation:
> >>>> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> >>>> +
> >>>> +Required properties:
> >>>> +
> >>>> +- compatible:                "ti,da850-syscfg"
> >>> 
> >>> Don't you need a reg property ?
> >> 
> >> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
> >> 
> >>>> +Optional properties:
> >>>> +
> >>>> +The below properties are used to specify the priority of master
> >>>> peripherals.
> >>>> +They must be between 0-7 where 0 is the highest priority and 7 is the
> >>>> lowest.
> >>>> +
> >>>> +- ti,pri-arm-i:              ARM_I port priority.
> >>>> +
> >>>> +- ti,pri-arm-d:              ARM_D port priority.
> >>>> +
> >>>> +- ti,pri-upp:                uPP port priority.
> >>>> +
> >>>> +- ti,pri-sata:               SATA port priority.
> >>>> +
> >>>> +- ti,pri-pru0:               PRU0 port priority.
> >>>> +
> >>>> +- ti,pri-pru1:               PRU1 port priority.
> >>>> +
> >>>> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
> >>>> +
> >>>> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
> >>>> +
> >>>> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
> >>>> +
> >>>> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
> >>>> +
> >>>> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
> >>>> +
> >>>> +- ti,pri-emac:               EMAC port priority.
> >>>> +
> >>>> +- ti,pri-usb0cfg:    USB0 CFG port priority.
> >>>> +
> >>>> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
> >>>> +
> >>>> +- ti,pri-uhpi:               HPI port priority.
> >>>> +
> >>>> +- ti,pri-usb1:               USB1 port priority.
> >>>> +
> >>>> +- ti,pri-lcdc:               LCDC port priority.
> >>> 
> >>> I'm afraid this looks more like system configuration than hardware
> >>> description to me.
> >> 
> >> While you're certainly right, this approach is already implemented in
> >> several other memory and bus drivers and it was also suggested by
> >> Sekhar in one of the tilcdc rev1 threads. There's also no real
> >> alternative that I know of.
> > 
> > The fact that other drivers get it wrong is no excuse for copying them :-)
> 
> What exactly is "wrong" with the way other drivers are doing it?
> 
> I'm sure there may be other ideas, and possibly some better ones, but
> that doesn't make it wrong, and doesn't change he fact that the kernel
> has existing drivers SoC-bus-specific system performance knobs like
> this.

It's not the drivers I'm concerned about, but the DT bindings. The proposed DT 
binding contains a large number of properties that don't describe the hardware 
but contain configuration data. If they're accepted you'll have to carry them 
forward forever, while they should be controlled in a more flexible way.

> >>> There was a BoF session about how to support this kind of performance
> >>> knobs at ELCE last week:
> >>> https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-perf
> >>> ormance-framework-michael-turquette-baylibre :-)
> >> 
> >> Unfortunately it was just a discussion about potential approaches -
> >> there's no code yet.
> > 
> > Patches are welcome ;-)
> 
> Any generic perf framework will have to build on the HW-specifics of
> individual busses, so IMO, the lack of a generic performance
> framework/knobs should not be a reason to block the inclusion of any
> bus-specific knobs.
> 
> I guess this ultimately would go though arm-soc, so I've added Arnd &
> Olof to the thread.

-- 
Regards,

Laurent Pinchart

[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Laurent Pinchart]

Hi Kevin,

On Thursday 20 Oct 2016 09:57:51 Kevin Hilman wrote:
> Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:
> > On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
> >> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
> >>> On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
> >>>> Create the driver for the da8xx System Configuration and implement
> >>>> support for writing to the three Master Priority registers.
> >>>> 
> >>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >> 
> >> [snip]
> >> 
> >>>> +
> >>>> +Documentation:
> >>>> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
> >>>> +
> >>>> +Required properties:
> >>>> +
> >>>> +- compatible:                "ti,da850-syscfg"
> >>> 
> >>> Don't you need a reg property ?
> >> 
> >> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
> >> 
> >>>> +Optional properties:
> >>>> +
> >>>> +The below properties are used to specify the priority of master
> >>>> peripherals.
> >>>> +They must be between 0-7 where 0 is the highest priority and 7 is the
> >>>> lowest.
> >>>> +
> >>>> +- ti,pri-arm-i:              ARM_I port priority.
> >>>> +
> >>>> +- ti,pri-arm-d:              ARM_D port priority.
> >>>> +
> >>>> +- ti,pri-upp:                uPP port priority.
> >>>> +
> >>>> +- ti,pri-sata:               SATA port priority.
> >>>> +
> >>>> +- ti,pri-pru0:               PRU0 port priority.
> >>>> +
> >>>> +- ti,pri-pru1:               PRU1 port priority.
> >>>> +
> >>>> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
> >>>> +
> >>>> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
> >>>> +
> >>>> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
> >>>> +
> >>>> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
> >>>> +
> >>>> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
> >>>> +
> >>>> +- ti,pri-emac:               EMAC port priority.
> >>>> +
> >>>> +- ti,pri-usb0cfg:    USB0 CFG port priority.
> >>>> +
> >>>> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
> >>>> +
> >>>> +- ti,pri-uhpi:               HPI port priority.
> >>>> +
> >>>> +- ti,pri-usb1:               USB1 port priority.
> >>>> +
> >>>> +- ti,pri-lcdc:               LCDC port priority.
> >>> 
> >>> I'm afraid this looks more like system configuration than hardware
> >>> description to me.
> >> 
> >> While you're certainly right, this approach is already implemented in
> >> several other memory and bus drivers and it was also suggested by
> >> Sekhar in one of the tilcdc rev1 threads. There's also no real
> >> alternative that I know of.
> > 
> > The fact that other drivers get it wrong is no excuse for copying them :-)
> 
> What exactly is "wrong" with the way other drivers are doing it?
> 
> I'm sure there may be other ideas, and possibly some better ones, but
> that doesn't make it wrong, and doesn't change he fact that the kernel
> has existing drivers SoC-bus-specific system performance knobs like
> this.

It's not the drivers I'm concerned about, but the DT bindings. The proposed DT 
binding contains a large number of properties that don't describe the hardware 
but contain configuration data. If they're accepted you'll have to carry them 
forward forever, while they should be controlled in a more flexible way.

> >>> There was a BoF session about how to support this kind of performance
> >>> knobs at ELCE last week:
> >>> https://openiotelceurope2016.sched.org/event/7rss/bof-linux-device-perf
> >>> ormance-framework-michael-turquette-baylibre :-)
> >> 
> >> Unfortunately it was just a discussion about potential approaches -
> >> there's no code yet.
> > 
> > Patches are welcome ;-)
> 
> Any generic perf framework will have to build on the HW-specifics of
> individual busses, so IMO, the lack of a generic performance
> framework/knobs should not be a reason to block the inclusion of any
> bus-specific knobs.
> 
> I guess this ultimately would go though arm-soc, so I've added Arnd &
> Olof to the thread.

-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Kevin Hilman]

Hi Laurent,

Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:

> On Thursday 20 Oct 2016 09:57:51 Kevin Hilman wrote:
>> Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:
>> > On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
>> >> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
>> >>> On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> >>>> Create the driver for the da8xx System Configuration and implement
>> >>>> support for writing to the three Master Priority registers.
>> >>>> 
>> >>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>> >> 
>> >> [snip]
>> >> 
>> >>>> +
>> >>>> +Documentation:
>> >>>> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
>> >>>> +
>> >>>> +Required properties:
>> >>>> +
>> >>>> +- compatible:                "ti,da850-syscfg"
>> >>> 
>> >>> Don't you need a reg property ?
>> >> 
>> >> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
>> >> 
>> >>>> +Optional properties:
>> >>>> +
>> >>>> +The below properties are used to specify the priority of master
>> >>>> peripherals.
>> >>>> +They must be between 0-7 where 0 is the highest priority and 7 is the
>> >>>> lowest.
>> >>>> +
>> >>>> +- ti,pri-arm-i:              ARM_I port priority.
>> >>>> +
>> >>>> +- ti,pri-arm-d:              ARM_D port priority.
>> >>>> +
>> >>>> +- ti,pri-upp:                uPP port priority.
>> >>>> +
>> >>>> +- ti,pri-sata:               SATA port priority.
>> >>>> +
>> >>>> +- ti,pri-pru0:               PRU0 port priority.
>> >>>> +
>> >>>> +- ti,pri-pru1:               PRU1 port priority.
>> >>>> +
>> >>>> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
>> >>>> +
>> >>>> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
>> >>>> +
>> >>>> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
>> >>>> +
>> >>>> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
>> >>>> +
>> >>>> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
>> >>>> +
>> >>>> +- ti,pri-emac:               EMAC port priority.
>> >>>> +
>> >>>> +- ti,pri-usb0cfg:    USB0 CFG port priority.
>> >>>> +
>> >>>> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
>> >>>> +
>> >>>> +- ti,pri-uhpi:               HPI port priority.
>> >>>> +
>> >>>> +- ti,pri-usb1:               USB1 port priority.
>> >>>> +
>> >>>> +- ti,pri-lcdc:               LCDC port priority.
>> >>> 
>> >>> I'm afraid this looks more like system configuration than hardware
>> >>> description to me.
>> >> 
>> >> While you're certainly right, this approach is already implemented in
>> >> several other memory and bus drivers and it was also suggested by
>> >> Sekhar in one of the tilcdc rev1 threads. There's also no real
>> >> alternative that I know of.
>> > 
>> > The fact that other drivers get it wrong is no excuse for copying them :-)
>> 
>> What exactly is "wrong" with the way other drivers are doing it?
>> 
>> I'm sure there may be other ideas, and possibly some better ones, but
>> that doesn't make it wrong, and doesn't change he fact that the kernel
>> has existing drivers SoC-bus-specific system performance knobs like
>> this.
>
> It's not the drivers I'm concerned about, but the DT bindings.

I see, thanks for the clarification.

> The proposed DT binding contains a large number of properties that
> don't describe the hardware but contain configuration data.

I agree that there ought to be some more generic way for devices to
request performance constraints from their busses at runtime based on
their current operating critera, but unfortunately that doesn't exist
yet.

However, after our discussion on IRC, we'll respin this without the DT
bindings at all.  Next version will just use static configuration data
in the drivers/bus driver based on SoC compatible string, since for the
use-cases I'm aware of, the settings are boot-time only.

Thanks again for the review,

Kevin

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Kevin Hilman]

Hi Laurent,

Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:

> On Thursday 20 Oct 2016 09:57:51 Kevin Hilman wrote:
>> Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:
>> > On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
>> >> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
>> >>> On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> >>>> Create the driver for the da8xx System Configuration and implement
>> >>>> support for writing to the three Master Priority registers.
>> >>>> 
>> >>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>> >> 
>> >> [snip]
>> >> 
>> >>>> +
>> >>>> +Documentation:
>> >>>> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
>> >>>> +
>> >>>> +Required properties:
>> >>>> +
>> >>>> +- compatible:                "ti,da850-syscfg"
>> >>> 
>> >>> Don't you need a reg property ?
>> >> 
>> >> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
>> >> 
>> >>>> +Optional properties:
>> >>>> +
>> >>>> +The below properties are used to specify the priority of master
>> >>>> peripherals.
>> >>>> +They must be between 0-7 where 0 is the highest priority and 7 is the
>> >>>> lowest.
>> >>>> +
>> >>>> +- ti,pri-arm-i:              ARM_I port priority.
>> >>>> +
>> >>>> +- ti,pri-arm-d:              ARM_D port priority.
>> >>>> +
>> >>>> +- ti,pri-upp:                uPP port priority.
>> >>>> +
>> >>>> +- ti,pri-sata:               SATA port priority.
>> >>>> +
>> >>>> +- ti,pri-pru0:               PRU0 port priority.
>> >>>> +
>> >>>> +- ti,pri-pru1:               PRU1 port priority.
>> >>>> +
>> >>>> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
>> >>>> +
>> >>>> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
>> >>>> +
>> >>>> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
>> >>>> +
>> >>>> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
>> >>>> +
>> >>>> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
>> >>>> +
>> >>>> +- ti,pri-emac:               EMAC port priority.
>> >>>> +
>> >>>> +- ti,pri-usb0cfg:    USB0 CFG port priority.
>> >>>> +
>> >>>> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
>> >>>> +
>> >>>> +- ti,pri-uhpi:               HPI port priority.
>> >>>> +
>> >>>> +- ti,pri-usb1:               USB1 port priority.
>> >>>> +
>> >>>> +- ti,pri-lcdc:               LCDC port priority.
>> >>> 
>> >>> I'm afraid this looks more like system configuration than hardware
>> >>> description to me.
>> >> 
>> >> While you're certainly right, this approach is already implemented in
>> >> several other memory and bus drivers and it was also suggested by
>> >> Sekhar in one of the tilcdc rev1 threads. There's also no real
>> >> alternative that I know of.
>> > 
>> > The fact that other drivers get it wrong is no excuse for copying them :-)
>> 
>> What exactly is "wrong" with the way other drivers are doing it?
>> 
>> I'm sure there may be other ideas, and possibly some better ones, but
>> that doesn't make it wrong, and doesn't change he fact that the kernel
>> has existing drivers SoC-bus-specific system performance knobs like
>> this.
>
> It's not the drivers I'm concerned about, but the DT bindings.

I see, thanks for the clarification.

> The proposed DT binding contains a large number of properties that
> don't describe the hardware but contain configuration data.

I agree that there ought to be some more generic way for devices to
request performance constraints from their busses at runtime based on
their current operating critera, but unfortunately that doesn't exist
yet.

However, after our discussion on IRC, we'll respin this without the DT
bindings at all.  Next version will just use static configuration data
in the drivers/bus driver based on SoC compatible string, since for the
use-cases I'm aware of, the settings are boot-time only.

Thanks again for the review,

Kevin




_______________________________________________
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dri-devel@lists.freedesktop.org
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[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Kevin Hilman]

Hi Laurent,

Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:

> On Thursday 20 Oct 2016 09:57:51 Kevin Hilman wrote:
>> Laurent Pinchart <laurent.pinchart@ideasonboard.com> writes:
>> > On Wednesday 19 Oct 2016 10:26:57 Bartosz Golaszewski wrote:
>> >> 2016-10-18 22:49 GMT+02:00 Laurent Pinchart:
>> >>> On Monday 17 Oct 2016 18:30:49 Bartosz Golaszewski wrote:
>> >>>> Create the driver for the da8xx System Configuration and implement
>> >>>> support for writing to the three Master Priority registers.
>> >>>> 
>> >>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>> >> 
>> >> [snip]
>> >> 
>> >>>> +
>> >>>> +Documentation:
>> >>>> +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
>> >>>> +
>> >>>> +Required properties:
>> >>>> +
>> >>>> +- compatible:                "ti,da850-syscfg"
>> >>> 
>> >>> Don't you need a reg property ?
>> >> 
>> >> Yes, Kevin already pointed that out. I'll add it in v2. Same for [1/3].
>> >> 
>> >>>> +Optional properties:
>> >>>> +
>> >>>> +The below properties are used to specify the priority of master
>> >>>> peripherals.
>> >>>> +They must be between 0-7 where 0 is the highest priority and 7 is the
>> >>>> lowest.
>> >>>> +
>> >>>> +- ti,pri-arm-i:              ARM_I port priority.
>> >>>> +
>> >>>> +- ti,pri-arm-d:              ARM_D port priority.
>> >>>> +
>> >>>> +- ti,pri-upp:                uPP port priority.
>> >>>> +
>> >>>> +- ti,pri-sata:               SATA port priority.
>> >>>> +
>> >>>> +- ti,pri-pru0:               PRU0 port priority.
>> >>>> +
>> >>>> +- ti,pri-pru1:               PRU1 port priority.
>> >>>> +
>> >>>> +- ti,pri-edma30tc0:  EDMA3_0_TC0 port priority.
>> >>>> +
>> >>>> +- ti,pri-edma30tc1:  EDMA3_0_TC1 port priority.
>> >>>> +
>> >>>> +- ti,pri-edma31tc0:  EDMA3_1_TC0 port priority.
>> >>>> +
>> >>>> +- ti,pri-vpif-dma-0: VPIF DMA0 port priority.
>> >>>> +
>> >>>> +- ti,pri-vpif-dma-1: VPIF DMA1 port priority.
>> >>>> +
>> >>>> +- ti,pri-emac:               EMAC port priority.
>> >>>> +
>> >>>> +- ti,pri-usb0cfg:    USB0 CFG port priority.
>> >>>> +
>> >>>> +- ti,pri-usb0cdma:   USB0 CDMA port priority.
>> >>>> +
>> >>>> +- ti,pri-uhpi:               HPI port priority.
>> >>>> +
>> >>>> +- ti,pri-usb1:               USB1 port priority.
>> >>>> +
>> >>>> +- ti,pri-lcdc:               LCDC port priority.
>> >>> 
>> >>> I'm afraid this looks more like system configuration than hardware
>> >>> description to me.
>> >> 
>> >> While you're certainly right, this approach is already implemented in
>> >> several other memory and bus drivers and it was also suggested by
>> >> Sekhar in one of the tilcdc rev1 threads. There's also no real
>> >> alternative that I know of.
>> > 
>> > The fact that other drivers get it wrong is no excuse for copying them :-)
>> 
>> What exactly is "wrong" with the way other drivers are doing it?
>> 
>> I'm sure there may be other ideas, and possibly some better ones, but
>> that doesn't make it wrong, and doesn't change he fact that the kernel
>> has existing drivers SoC-bus-specific system performance knobs like
>> this.
>
> It's not the drivers I'm concerned about, but the DT bindings.

I see, thanks for the clarification.

> The proposed DT binding contains a large number of properties that
> don't describe the hardware but contain configuration data.

I agree that there ought to be some more generic way for devices to
request performance constraints from their busses at runtime based on
their current operating critera, but unfortunately that doesn't exist
yet.

However, after our discussion on IRC, we'll respin this without the DT
bindings at all.  Next version will just use static configuration data
in the drivers/bus driver based on SoC compatible string, since for the
use-cases I'm aware of, the settings are boot-time only.

Thanks again for the review,

Kevin

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Tomi Valkeinen]

[-- Attachment #1.1: Type: text/plain, Size: 481 bytes --]

On 20/10/16 22:39, Kevin Hilman wrote:

> However, after our discussion on IRC, we'll respin this without the DT
> bindings at all.  Next version will just use static configuration data
> in the drivers/bus driver based on SoC compatible string, since for the
> use-cases I'm aware of, the settings are boot-time only.

If it's static boot time config, why not do it in the u-boot?

I'm fine either way, but this sounds like quite low level memory bus config.

 Tomi


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Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Tomi Valkeinen]

[-- Attachment #1.1.1: Type: text/plain, Size: 481 bytes --]

On 20/10/16 22:39, Kevin Hilman wrote:

> However, after our discussion on IRC, we'll respin this without the DT
> bindings at all.  Next version will just use static configuration data
> in the drivers/bus driver based on SoC compatible string, since for the
> use-cases I'm aware of, the settings are boot-time only.

If it's static boot time config, why not do it in the u-boot?

I'm fine either way, but this sounds like quite low level memory bus config.

 Tomi


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[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Tomi Valkeinen]

On 20/10/16 22:39, Kevin Hilman wrote:

> However, after our discussion on IRC, we'll respin this without the DT
> bindings at all.  Next version will just use static configuration data
> in the drivers/bus driver based on SoC compatible string, since for the
> use-cases I'm aware of, the settings are boot-time only.

If it's static boot time config, why not do it in the u-boot?

I'm fine either way, but this sounds like quite low level memory bus config.

 Tomi

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Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Sekhar Nori]

On Friday 21 October 2016 02:55 PM, Tomi Valkeinen wrote:
> On 20/10/16 22:39, Kevin Hilman wrote:
> 
>> However, after our discussion on IRC, we'll respin this without the DT
>> bindings at all.  Next version will just use static configuration data
>> in the drivers/bus driver based on SoC compatible string, since for the
>> use-cases I'm aware of, the settings are boot-time only.
> 
> If it's static boot time config, why not do it in the u-boot?

Hardware initialization dependencies with boot-loader are tough to track
and debug. The bootloader thats currently ships with the board may not
have these settings, for example. This forces everyone to update their
bootloader when shifting to mainline kernel.

Thanks,
Sekhar

[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Sekhar Nori]

On Friday 21 October 2016 02:55 PM, Tomi Valkeinen wrote:
> On 20/10/16 22:39, Kevin Hilman wrote:
> 
>> However, after our discussion on IRC, we'll respin this without the DT
>> bindings at all.  Next version will just use static configuration data
>> in the drivers/bus driver based on SoC compatible string, since for the
>> use-cases I'm aware of, the settings are boot-time only.
> 
> If it's static boot time config, why not do it in the u-boot?

Hardware initialization dependencies with boot-loader are tough to track
and debug. The bootloader thats currently ships with the board may not
have these settings, for example. This forces everyone to update their
bootloader when shifting to mainline kernel.

Thanks,
Sekhar

Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Tomi Valkeinen]

[-- Attachment #1.1: Type: text/plain, Size: 913 bytes --]



On 21/10/16 12:53, Sekhar Nori wrote:
> On Friday 21 October 2016 02:55 PM, Tomi Valkeinen wrote:
>> On 20/10/16 22:39, Kevin Hilman wrote:
>>
>>> However, after our discussion on IRC, we'll respin this without the DT
>>> bindings at all.  Next version will just use static configuration data
>>> in the drivers/bus driver based on SoC compatible string, since for the
>>> use-cases I'm aware of, the settings are boot-time only.
>>
>> If it's static boot time config, why not do it in the u-boot?
> 
> Hardware initialization dependencies with boot-loader are tough to track
> and debug. The bootloader thats currently ships with the board may not
> have these settings, for example. This forces everyone to update their
> bootloader when shifting to mainline kernel.

Yep, true... We need something similar for AM335x too. And perhaps for
other SoCs too (AM4 comes to my mind).

 Tomi


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Re: [PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Tomi Valkeinen]

[-- Attachment #1.1.1: Type: text/plain, Size: 913 bytes --]



On 21/10/16 12:53, Sekhar Nori wrote:
> On Friday 21 October 2016 02:55 PM, Tomi Valkeinen wrote:
>> On 20/10/16 22:39, Kevin Hilman wrote:
>>
>>> However, after our discussion on IRC, we'll respin this without the DT
>>> bindings at all.  Next version will just use static configuration data
>>> in the drivers/bus driver based on SoC compatible string, since for the
>>> use-cases I'm aware of, the settings are boot-time only.
>>
>> If it's static boot time config, why not do it in the u-boot?
> 
> Hardware initialization dependencies with boot-loader are tough to track
> and debug. The bootloader thats currently ships with the board may not
> have these settings, for example. This forces everyone to update their
> bootloader when shifting to mainline kernel.

Yep, true... We need something similar for AM335x too. And perhaps for
other SoCs too (AM4 comes to my mind).

 Tomi


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[PATCH 2/3] ARM: bus: da8xx-syscfg: new driver

[Tomi Valkeinen]

On 21/10/16 12:53, Sekhar Nori wrote:
> On Friday 21 October 2016 02:55 PM, Tomi Valkeinen wrote:
>> On 20/10/16 22:39, Kevin Hilman wrote:
>>
>>> However, after our discussion on IRC, we'll respin this without the DT
>>> bindings at all.  Next version will just use static configuration data
>>> in the drivers/bus driver based on SoC compatible string, since for the
>>> use-cases I'm aware of, the settings are boot-time only.
>>
>> If it's static boot time config, why not do it in the u-boot?
> 
> Hardware initialization dependencies with boot-loader are tough to track
> and debug. The bootloader thats currently ships with the board may not
> have these settings, for example. This forces everyone to update their
> bootloader when shifting to mainline kernel.

Yep, true... We need something similar for AM335x too. And perhaps for
other SoCs too (AM4 comes to my mind).

 Tomi

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