[PATCH 0/4] mmc: fsl_esdhc: ls1028a workarounds

[PATCH 0/4] mmc: fsl_esdhc: ls1028a workarounds

[Michael Walle]

This patchset fixes HS400 mode on LS1028A SoC which is broken since commit
8ee802f899ef ("mmc: fsl_esdhc: make sure delay chain locked for HS400").
Well, before it might just have worked by accident.

=> run bootcmd_mmc0
fsl_esdhc: delay chain lock timeout
Select HS400 failed -110
unable to select a mode : -5

Because the sl28 board already uses that mode, MMC boot is broken. The
first patch disables HS400 mode on this board.
Tom, patch 1 should go into the master branch for the 2021.04 release.

Patches 2 and 3 introduce the actual workarounds, patch 4 will then
reenable the HS400 mode on the sl28 board. I don't expect that this will
make it into the next release.

Michael Walle (4):
  board: sl28: disable HS400 mode
  mmc: fsl_esdhc: add workaround for erratum A-011334
  mmc: fsl_esdhc: add pulse width detection workaround
  board: sl28: enable HS400 mode again

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  2 ++
 drivers/mmc/Kconfig                       |  6 +++++
 drivers/mmc/fsl_esdhc.c                   | 31 +++++++++++++++++++++--
 include/fsl_esdhc.h                       |  3 +++
 4 files changed, 40 insertions(+), 2 deletions(-)

-- 
2.20.1

[PATCH 1/4] board: sl28: disable HS400 mode

[Michael Walle]

Since commit 8ee802f899ef ("mmc: fsl_esdhc: make sure delay chain locked
for HS400") HS400 mode is unreliable on LS1028A SoCs. Some workarounds are
missing for this SoC.

Disable HS400 mode for now.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 configs/kontron_sl28_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index 1c781e091c..0c6c1911d9 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -70,7 +70,7 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_I2C_DEFAULT_BUS_NUMBER=0
 CONFIG_I2C_MUX=y
 CONFIG_DM_MMC=y
-CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_FSL_ESDHC=y
 CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
 CONFIG_DM_SPI_FLASH=y
-- 
2.20.1

[PATCH 1/4] board: sl28: disable HS400 mode

[Jaehoon Chung]

On 3/17/21 11:01 PM, Michael Walle wrote:
> Since commit 8ee802f899ef ("mmc: fsl_esdhc: make sure delay chain locked
> for HS400") HS400 mode is unreliable on LS1028A SoCs. Some workarounds are
> missing for this SoC.
> 
> Disable HS400 mode for now.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

It seems that this patch doesn't need. Because CONFIG_MMC_HS400_SUPPORT is re-enabling with [PATCH 4/4].
How about dropping Drop [PATCH 1/4] and [PATCH 4/4]?

Best Regards,
Jaehoon Chung

> ---
>  configs/kontron_sl28_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
> index 1c781e091c..0c6c1911d9 100644
> --- a/configs/kontron_sl28_defconfig
> +++ b/configs/kontron_sl28_defconfig
> @@ -70,7 +70,7 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
>  CONFIG_I2C_DEFAULT_BUS_NUMBER=0
>  CONFIG_I2C_MUX=y
>  CONFIG_DM_MMC=y
> -CONFIG_MMC_HS400_SUPPORT=y
> +CONFIG_MMC_HS200_SUPPORT=y
>  CONFIG_FSL_ESDHC=y
>  CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
>  CONFIG_DM_SPI_FLASH=y
> 

[PATCH 1/4] board: sl28: disable HS400 mode

[Michael Walle]

Am 2021-03-17 23:49, schrieb Jaehoon Chung:
> On 3/17/21 11:01 PM, Michael Walle wrote:
>> Since commit 8ee802f899ef ("mmc: fsl_esdhc: make sure delay chain 
>> locked
>> for HS400") HS400 mode is unreliable on LS1028A SoCs. Some workarounds 
>> are
>> missing for this SoC.
>> 
>> Disable HS400 mode for now.
>> 
>> Signed-off-by: Michael Walle <michael@walle.cc>
> 
> It seems that this patch doesn't need. Because
> CONFIG_MMC_HS400_SUPPORT is re-enabling with [PATCH 4/4].
> How about dropping Drop [PATCH 1/4] and [PATCH 4/4]?

Please read the cover letter, if patch 2/4 and 3/4 will make
it into the 2021.04 relase, sure both can be dropped. But if not,
patch 1/4 is intented to go into the release while 2/4, 3/4 and
4/4 might get into the next relase.

The reason is that I favor a working mmc boot in the next
u-boot release for this board ;)

-michael

[PATCH 1/4] board: sl28: disable HS400 mode

[Jaehoon Chung]

On 3/18/21 7:59 AM, Michael Walle wrote:
> Am 2021-03-17 23:49, schrieb Jaehoon Chung:
>> On 3/17/21 11:01 PM, Michael Walle wrote:
>>> Since commit 8ee802f899ef ("mmc: fsl_esdhc: make sure delay chain locked
>>> for HS400") HS400 mode is unreliable on LS1028A SoCs. Some workarounds are
>>> missing for this SoC.
>>>
>>> Disable HS400 mode for now.
>>>
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>
>> It seems that this patch doesn't need. Because
>> CONFIG_MMC_HS400_SUPPORT is re-enabling with [PATCH 4/4].
>> How about dropping Drop [PATCH 1/4] and [PATCH 4/4]?
> 
> Please read the cover letter, if patch 2/4 and 3/4 will make
> it into the 2021.04 relase, sure both can be dropped. But if not,
> patch 1/4 is intented to go into the release while 2/4, 3/4 and
> 4/4 might get into the next relase.

Sorry. I didn't read your cover-letter. At next time, i will read cover-letter, too. :)

Best Regards,
Jaehoon Chung

> 
> The reason is that I favor a working mmc boot in the next
> u-boot release for this board ;)
> 
> -michael
> 

[PATCH 1/4] board: sl28: disable HS400 mode

[Tom Rini]

On Wed, Mar 17, 2021 at 03:01:35PM +0100, Michael Walle wrote:

> Since commit 8ee802f899ef ("mmc: fsl_esdhc: make sure delay chain locked
> for HS400") HS400 mode is unreliable on LS1028A SoCs. Some workarounds are
> missing for this SoC.
> 
> Disable HS400 mode for now.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>

Applied to u-boot/master, thanks!

-- 
Tom
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[PATCH 2/4] mmc: fsl_esdhc: add workaround for erratum A-011334

[Michael Walle]

LS1028A SoCs are restricted in what divider values are allowed for HS400
mode. This is basically a port from the corresponding linux driver.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  1 +
 drivers/mmc/Kconfig                       |  3 +++
 drivers/mmc/fsl_esdhc.c                   | 25 ++++++++++++++++++++++-
 3 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ae0b7b21e8..c0190a233e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -47,6 +47,7 @@ config ARCH_LS1028A
 	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 	select SYS_FSL_ERRATUM_A050382
+	select SYS_FSL_ERRATUM_A011334
 	select RESV_RAM if GIC_V3_ITS
 	imply PANIC_HANG
 
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f8ca52efb6..0b6755fd90 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -812,3 +812,6 @@ config SYS_FSL_ERRATUM_ESDHC135
 
 config SYS_FSL_ERRATUM_ESDHC_A001
 	bool
+
+config SYS_FSL_ERRATUM_A011334
+	bool
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 6014e1c5ca..09ea1a9de9 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -518,6 +518,24 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
 	while (sdhc_clk / (div * pre_div) > clock && div < 16)
 		div++;
 
+	if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
+	    clock == 200000000 && mmc->selected_mode == MMC_HS_400) {
+		u32 div_ratio = pre_div * div;
+
+		if (div_ratio <= 4) {
+			pre_div = 4;
+			div = 1;
+		} else if (div_ratio <= 8) {
+			pre_div = 4;
+			div = 2;
+		} else if (div_ratio <= 12) {
+			pre_div = 4;
+			div = 3;
+		} else {
+			printf("unsupported clock division.\n");
+		}
+	}
+
 	mmc->clock = sdhc_clk / pre_div / div;
 	priv->clock = mmc->clock;
 
@@ -1063,9 +1081,14 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
 	struct fsl_esdhc_plat *plat = dev_get_plat(dev);
 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
 	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct mmc *mmc = &plat->mmc;
 	u32 val, irqstaten;
 	int i;
 
+	if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
+	    plat->mmc.hs400_tuning)
+		set_sysctl(priv, mmc, mmc->clock);
+
 	esdhc_tuning_block_enable(priv, true);
 	esdhc_setbits32(&regs->autoc12err, EXECUTE_TUNING);
 
@@ -1073,7 +1096,7 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
 	esdhc_write32(&regs->irqstaten, IRQSTATEN_BRR);
 
 	for (i = 0; i < MAX_TUNING_LOOP; i++) {
-		mmc_send_tuning(&plat->mmc, opcode, NULL);
+		mmc_send_tuning(mmc, opcode, NULL);
 		mdelay(1);
 
 		val = esdhc_read32(&regs->autoc12err);
-- 
2.20.1

[PATCH 3/4] mmc: fsl_esdhc: add pulse width detection workaround

[Michael Walle]

HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a
workaroung for the pulse width detection. Apply this workaround in
u-boot, too.

This will make HS400 mode work reliably on the LS1028A SoC.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +
 drivers/mmc/Kconfig                       | 3 +++
 drivers/mmc/fsl_esdhc.c                   | 6 +++++-
 include/fsl_esdhc.h                       | 3 +++
 4 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index c0190a233e..9d1ba4c771 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -48,6 +48,7 @@ config ARCH_LS1028A
 	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 	select SYS_FSL_ERRATUM_A050382
 	select SYS_FSL_ERRATUM_A011334
+	select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
 	select RESV_RAM if GIC_V3_ITS
 	imply PANIC_HANG
 
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 0b6755fd90..f7620c9cd1 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -815,3 +815,6 @@ config SYS_FSL_ERRATUM_ESDHC_A001
 
 config SYS_FSL_ERRATUM_A011334
 	bool
+
+config SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
+	bool
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 09ea1a9de9..7501fdb71e 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -71,7 +71,8 @@ struct fsl_esdhc {
 	uint	sdtimingctl;	/* SD timing control register */
 	char    reserved8[20];	/* reserved */
 	uint	dllcfg0;	/* DLL config 0 register */
-	char	reserved9[12];	/* reserved */
+	uint	dllcfg1;	/* DLL config 1 register */
+	char	reserved9[8];	/* reserved */
 	uint	dllstat0;	/* DLL status 0 register */
 	char    reserved10[664];/* reserved */
 	uint    esdhcctl;	/* eSDHC control register */
@@ -767,6 +768,9 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 	/* Set timout to the maximum value */
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 
+	if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
+		esdhc_clrbits32(&regs->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
+
 	return 0;
 }
 
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 850a304bd7..f86afe5dad 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -190,6 +190,9 @@
 #define DLL_RESET		0x40000000
 #define DLL_FREQ_SEL		0x08000000
 
+/* DLL config 1 register */
+#define DLL_PD_PULSE_STRETCH_SEL 0x80000000
+
 /* DLL status 0 register */
 #define DLL_STS_SLV_LOCK	0x08000000
 
-- 
2.20.1

[PATCH 3/4] mmc: fsl_esdhc: add pulse width detection workaround

[Jaehoon Chung]

On 3/17/21 11:01 PM, Michael Walle wrote:
> HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a
> workaroung for the pulse width detection. Apply this workaround in
> u-boot, too.
> 
> This will make HS400 mode work reliably on the LS1028A SoC.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +
>  drivers/mmc/Kconfig                       | 3 +++
>  drivers/mmc/fsl_esdhc.c                   | 6 +++++-
>  include/fsl_esdhc.h                       | 3 +++
>  4 files changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index c0190a233e..9d1ba4c771 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -48,6 +48,7 @@ config ARCH_LS1028A
>  	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
>  	select SYS_FSL_ERRATUM_A050382
>  	select SYS_FSL_ERRATUM_A011334
> +	select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
>  	select RESV_RAM if GIC_V3_ITS
>  	imply PANIC_HANG
>  
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 0b6755fd90..f7620c9cd1 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -815,3 +815,6 @@ config SYS_FSL_ERRATUM_ESDHC_A001
>  
>  config SYS_FSL_ERRATUM_A011334
>  	bool
> +
> +config SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND

How about using QUIRK instead of WORKAROUD

Best Regards,
Jaehoon Chung

> +	bool
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 09ea1a9de9..7501fdb71e 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -71,7 +71,8 @@ struct fsl_esdhc {
>  	uint	sdtimingctl;	/* SD timing control register */
>  	char    reserved8[20];	/* reserved */
>  	uint	dllcfg0;	/* DLL config 0 register */
> -	char	reserved9[12];	/* reserved */
> +	uint	dllcfg1;	/* DLL config 1 register */
> +	char	reserved9[8];	/* reserved */
>  	uint	dllstat0;	/* DLL status 0 register */
>  	char    reserved10[664];/* reserved */
>  	uint    esdhcctl;	/* eSDHC control register */
> @@ -767,6 +768,9 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
>  	/* Set timout to the maximum value */
>  	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
>  
> +	if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
> +		esdhc_clrbits32(&regs->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
> +
>  	return 0;
>  }
>  
> diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
> index 850a304bd7..f86afe5dad 100644
> --- a/include/fsl_esdhc.h
> +++ b/include/fsl_esdhc.h
> @@ -190,6 +190,9 @@
>  #define DLL_RESET		0x40000000
>  #define DLL_FREQ_SEL		0x08000000
>  
> +/* DLL config 1 register */
> +#define DLL_PD_PULSE_STRETCH_SEL 0x80000000
> +
>  /* DLL status 0 register */
>  #define DLL_STS_SLV_LOCK	0x08000000
>  
> 

[PATCH 3/4] mmc: fsl_esdhc: add pulse width detection workaround

[Michael Walle]

Am 2021-03-17 23:47, schrieb Jaehoon Chung:
> On 3/17/21 11:01 PM, Michael Walle wrote:
>>  config SYS_FSL_ERRATUM_A011334
>>  	bool
>> +
>> +config SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
> 
> How about using QUIRK instead of WORKAROUD

There is already a CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND,
so I chose that for consistency reasons.

-michael

[PATCH 3/4] mmc: fsl_esdhc: add pulse width detection workaround

[Jaehoon Chung]

On 3/18/21 8:01 AM, Michael Walle wrote:
> Am 2021-03-17 23:47, schrieb Jaehoon Chung:
>> On 3/17/21 11:01 PM, Michael Walle wrote:
>>> ?config SYS_FSL_ERRATUM_A011334
>>> ???? bool
>>> +
>>> +config SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
>>
>> How about using QUIRK instead of WORKAROUD
> 
> There is already a CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND,
> so I chose that for consistency reasons.

Then i don't have any objection. Thanks!

Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>

Best Regards,
Jaehoon Chung

> 
> -michael
> 

[PATCH 4/4] board: sl28: enable HS400 mode again

[Michael Walle]

Now that it is working reliable on the LS1028A SoC, reenable support for
it.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 configs/kontron_sl28_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig
index 0c6c1911d9..1c781e091c 100644
--- a/configs/kontron_sl28_defconfig
+++ b/configs/kontron_sl28_defconfig
@@ -70,7 +70,7 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_I2C_DEFAULT_BUS_NUMBER=0
 CONFIG_I2C_MUX=y
 CONFIG_DM_MMC=y
-CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
 CONFIG_FSL_ESDHC=y
 CONFIG_FSL_ESDHC_SUPPORT_ADMA2=y
 CONFIG_DM_SPI_FLASH=y
-- 
2.20.1