From: Maxime Ripard <maxime.ripard@bootlin.com> To: Mark Rutland <mark.rutland@arm.com>, Rob Herring <robh+dt@kernel.org>, Frank Rowand <frowand.list@gmail.com>, Chen-Yu Tsai <wens@csie.org>, Maxime Ripard <maxime.ripard@bootlin.com> Cc: devicetree@vger.kernel.org, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Arnd Bergmann <arnd@arndb.de>, dri-devel@lists.freedesktop.org, Georgi Djakov <georgi.djakov@linaro.org>, Paul Kocialkowski <paul.kocialkowski@bootlin.com>, Yong Deng <yong.deng@magewell.com>, Robin Murphy <robin.murphy@arm.com>, Dave Martin <dave.martin@arm.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 7/7] ARM: dts: sun5i: Add the MBUS controller Date: Wed, 6 Feb 2019 20:41:24 +0100 [thread overview] Message-ID: <03d3f58a2747b06da5d497a77be9b425a7b37528.1549482066.git-series.maxime.ripard@bootlin.com> (raw) In-Reply-To: <cover.ddd928eab0069d426b711e69940918eaf85625ce.1549482066.git-series.maxime.ripard@bootlin.com> The MBUS (and its associated controller) is the bus in the Allwinner SoCs that DMA devices use in the system to access the memory. Among other things (and depending on the SoC generation), it can also enforce priorities or report bandwidth usages on a per-master basis. One of the most notable thing is that instead of having the same mapping for the RAM than the CPU, it maps it at address 0, which means we'll have to do address translation thanks to the dma-ranges property. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> --- arch/arm/boot/dts/sun5i.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 5497d985c54a..a29203b7661d 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -127,6 +127,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + dma-ranges; ranges; system-control@1c00000 { @@ -181,6 +182,14 @@ }; }; + mbus: dram-controller@1c01000 { + compatible = "allwinner,sun5i-a13-mbus"; + reg = <0x01c01000 0x1000>; + clocks = <&ccu CLK_MBUS>; + dma-ranges = <0x00000000 0x40000000 0x20000000>; + #interconnect-cells = <1>; + }; + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; @@ -727,6 +736,8 @@ clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_FE>; + interconnects = <&mbus 19>; + interconnect-names = "dma"; status = "disabled"; ports { @@ -755,6 +766,8 @@ clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_BE>; + interconnects = <&mbus 18>; + interconnect-names = "dma"; status = "disabled"; assigned-clocks = <&ccu CLK_DE_BE>; -- git-series 0.9.1 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: Maxime Ripard <maxime.ripard@bootlin.com> To: Mark Rutland <mark.rutland@arm.com>, Rob Herring <robh+dt@kernel.org>, Frank Rowand <frowand.list@gmail.com>, Chen-Yu Tsai <wens@csie.org>, Maxime Ripard <maxime.ripard@bootlin.com> Cc: devicetree@vger.kernel.org, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Arnd Bergmann <arnd@arndb.de>, dri-devel@lists.freedesktop.org, Georgi Djakov <georgi.djakov@linaro.org>, Paul Kocialkowski <paul.kocialkowski@bootlin.com>, Yong Deng <yong.deng@magewell.com>, Robin Murphy <robin.murphy@arm.com>, Dave Martin <dave.martin@arm.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 7/7] ARM: dts: sun5i: Add the MBUS controller Date: Wed, 6 Feb 2019 20:41:24 +0100 [thread overview] Message-ID: <03d3f58a2747b06da5d497a77be9b425a7b37528.1549482066.git-series.maxime.ripard@bootlin.com> (raw) In-Reply-To: <cover.ddd928eab0069d426b711e69940918eaf85625ce.1549482066.git-series.maxime.ripard@bootlin.com> The MBUS (and its associated controller) is the bus in the Allwinner SoCs that DMA devices use in the system to access the memory. Among other things (and depending on the SoC generation), it can also enforce priorities or report bandwidth usages on a per-master basis. One of the most notable thing is that instead of having the same mapping for the RAM than the CPU, it maps it at address 0, which means we'll have to do address translation thanks to the dma-ranges property. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> --- arch/arm/boot/dts/sun5i.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 5497d985c54a..a29203b7661d 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -127,6 +127,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; + dma-ranges; ranges; system-control@1c00000 { @@ -181,6 +182,14 @@ }; }; + mbus: dram-controller@1c01000 { + compatible = "allwinner,sun5i-a13-mbus"; + reg = <0x01c01000 0x1000>; + clocks = <&ccu CLK_MBUS>; + dma-ranges = <0x00000000 0x40000000 0x20000000>; + #interconnect-cells = <1>; + }; + dma: dma-controller@1c02000 { compatible = "allwinner,sun4i-a10-dma"; reg = <0x01c02000 0x1000>; @@ -727,6 +736,8 @@ clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_FE>; + interconnects = <&mbus 19>; + interconnect-names = "dma"; status = "disabled"; ports { @@ -755,6 +766,8 @@ clock-names = "ahb", "mod", "ram"; resets = <&ccu RST_DE_BE>; + interconnects = <&mbus 18>; + interconnect-names = "dma"; status = "disabled"; assigned-clocks = <&ccu CLK_DE_BE>; -- git-series 0.9.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-02-06 19:41 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-02-06 19:41 [PATCH v2 0/7] sunxi: Add DT representation for the MBUS controller Maxime Ripard 2019-02-06 19:41 ` Maxime Ripard 2019-02-06 19:41 ` [PATCH v2 1/7] dt-bindings: interconnect: Add a dma interconnect name Maxime Ripard 2019-02-06 19:41 ` Maxime Ripard 2019-02-06 19:41 ` [PATCH v2 2/7] dt-bindings: bus: Add binding for the Allwinner MBUS controller Maxime Ripard 2019-02-06 19:41 ` Maxime Ripard 2019-02-06 19:41 ` [PATCH v2 3/7] of: address: Add parent pointer to the __of_translate_address args Maxime Ripard 2019-02-06 19:41 ` Maxime Ripard 2019-02-06 19:41 ` [PATCH v2 4/7] of: address: Add support for the dma-parent property Maxime Ripard 2019-02-06 19:41 ` Maxime Ripard 2019-02-06 20:57 ` Rob Herring 2019-02-06 20:57 ` Rob Herring 2019-02-11 13:09 ` Maxime Ripard 2019-02-11 13:09 ` Maxime Ripard 2019-02-06 19:41 ` [PATCH v2 5/7] drm/sun4i: Rely on dma-parent for our RAM offset Maxime Ripard 2019-02-06 19:41 ` Maxime Ripard 2019-02-06 19:41 ` [PATCH v2 6/7] clk: sunxi-ng: sun5i: Export the MBUS clock Maxime Ripard 2019-02-06 19:41 ` Maxime Ripard 2019-02-06 19:41 ` Maxime Ripard [this message] 2019-02-06 19:41 ` [PATCH v2 7/7] ARM: dts: sun5i: Add the MBUS controller Maxime Ripard
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