* [PATCH V3 0/9] Add minimal boot support for IPQ5332
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
The IPQ5332 is Qualcomm's 802.11ax SoC for Routers, Gateways and
Access Points.
This series adds minimal board boot support for ipq5332-mi01.2 board.
Also, this series depends on the below patch
https://lore.kernel.org/linux-arm-msm/20230120082631.22053-1-quic_kathirav@quicinc.com/
Changes in V3:
- Detailed change log is present in respective patches
- V2 can be found at
https://lore.kernel.org/linux-arm-msm/20230130114702.20606-1-quic_kathirav@quicinc.com/
Changes in V2:
- Rebased on linux-next/master
- Dropped the 'dt-bindings: mmc: sdhci-msm: add IPQ5332 compatible',
since it is already part of linux-next/master
- Added a new patch 'clk: qcom: ipq5332: mark GPLL4 as critical temporarily'
- Detailed change log is present in respective patches
- V1 can be found at
https://lore.kernel.org/linux-arm-msm/20230125104520.89684-1-quic_kathirav@quicinc.com/
Kathiravan T (9):
dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
pinctrl: qcom: Introduce IPQ5332 TLMM driver
clk: qcom: Add STROMER PLUS PLL type for IPQ5332
dt-bindings: clock: Add Qualcomm IPQ5332 GCC
clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
dt-bindings: qcom: add ipq5332 boards
dt-bindings: firmware: qcom,scm: document IPQ5332 SCM
arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
arm64: defconfig: Enable IPQ5332 SoC base configs
.../devicetree/bindings/arm/qcom.yaml | 7 +
.../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +
.../bindings/firmware/qcom,scm.yaml | 1 +
.../bindings/pinctrl/qcom,ipq5332-tlmm.yaml | 134 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 75 +
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 ++
arch/arm64/configs/defconfig | 2 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 11 +
drivers/clk/qcom/clk-alpha-pll.h | 1 +
drivers/clk/qcom/gcc-ipq5332.c | 3850 +++++++++++++++++
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5332.c | 861 ++++
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++
17 files changed, 5648 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi
create mode 100644 drivers/clk/qcom/gcc-ipq5332.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5332.c
create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
--
2.17.1
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH V3 0/9] Add minimal boot support for IPQ5332
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
The IPQ5332 is Qualcomm's 802.11ax SoC for Routers, Gateways and
Access Points.
This series adds minimal board boot support for ipq5332-mi01.2 board.
Also, this series depends on the below patch
https://lore.kernel.org/linux-arm-msm/20230120082631.22053-1-quic_kathirav@quicinc.com/
Changes in V3:
- Detailed change log is present in respective patches
- V2 can be found at
https://lore.kernel.org/linux-arm-msm/20230130114702.20606-1-quic_kathirav@quicinc.com/
Changes in V2:
- Rebased on linux-next/master
- Dropped the 'dt-bindings: mmc: sdhci-msm: add IPQ5332 compatible',
since it is already part of linux-next/master
- Added a new patch 'clk: qcom: ipq5332: mark GPLL4 as critical temporarily'
- Detailed change log is present in respective patches
- V1 can be found at
https://lore.kernel.org/linux-arm-msm/20230125104520.89684-1-quic_kathirav@quicinc.com/
Kathiravan T (9):
dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
pinctrl: qcom: Introduce IPQ5332 TLMM driver
clk: qcom: Add STROMER PLUS PLL type for IPQ5332
dt-bindings: clock: Add Qualcomm IPQ5332 GCC
clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
dt-bindings: qcom: add ipq5332 boards
dt-bindings: firmware: qcom,scm: document IPQ5332 SCM
arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
arm64: defconfig: Enable IPQ5332 SoC base configs
.../devicetree/bindings/arm/qcom.yaml | 7 +
.../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +
.../bindings/firmware/qcom,scm.yaml | 1 +
.../bindings/pinctrl/qcom,ipq5332-tlmm.yaml | 134 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 75 +
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 ++
arch/arm64/configs/defconfig | 2 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 11 +
drivers/clk/qcom/clk-alpha-pll.h | 1 +
drivers/clk/qcom/gcc-ipq5332.c | 3850 +++++++++++++++++
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5332.c | 861 ++++
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++
17 files changed, 5648 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi
create mode 100644 drivers/clk/qcom/gcc-ipq5332.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5332.c
create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH V3 1/9] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 7:12 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Add device tree bindings for IPQ5332 TLMM block.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Grouped the individual pin entries of pta[0-2] and xfem[0-7]
to pta and xfem
- Used the descriptive function names for wci pins to avoid the
ambiguity
- Din't pick up the Reviewed-By tag due to the above changes
Changes in V2:
- Renamed the file name to match with compatible
- Added 'maxItems' for 'interrupt' property
- Fixed the gpio pattern to 0 to 52 GPIOs instead of 0 to 53
GPIOs
- Converted the function names to lowercase and sort it
.../bindings/pinctrl/qcom,ipq5332-tlmm.yaml | 134 ++++++++++++++++++
1 file changed, 134 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
new file mode 100644
index 000000000000..300747252a7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ5332 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description: |
+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5332-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 27
+
+ gpio-line-names:
+ maxItems: 53
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq5332-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq5332-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq5332-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$"
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
+ atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec,
+ audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0,
+ blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
+ blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
+ blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0,
+ cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out,
+ gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1,
+ mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake,
+ pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1,
+ prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3,
+ qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
+ qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
+ qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
+ qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
+ qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
+ qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0,
+ rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd,
+ wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ]
+
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ drive-strength: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5332-tlmm";
+ reg = <0x01000000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ gpio-ranges = <&tlmm 0 0 53>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+
+ serial0-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp0_uart0";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 1/9] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Add device tree bindings for IPQ5332 TLMM block.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Grouped the individual pin entries of pta[0-2] and xfem[0-7]
to pta and xfem
- Used the descriptive function names for wci pins to avoid the
ambiguity
- Din't pick up the Reviewed-By tag due to the above changes
Changes in V2:
- Renamed the file name to match with compatible
- Added 'maxItems' for 'interrupt' property
- Fixed the gpio pattern to 0 to 52 GPIOs instead of 0 to 53
GPIOs
- Converted the function names to lowercase and sort it
.../bindings/pinctrl/qcom,ipq5332-tlmm.yaml | 134 ++++++++++++++++++
1 file changed, 134 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
new file mode 100644
index 000000000000..300747252a7b
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm IPQ5332 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description: |
+ Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5332-tlmm
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 27
+
+ gpio-line-names:
+ maxItems: 53
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-ipq5332-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-ipq5332-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-ipq5332-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$"
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
+ atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec,
+ audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0,
+ blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
+ blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
+ blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0,
+ cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out,
+ gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1,
+ mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake,
+ pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1,
+ prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3,
+ qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
+ qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
+ qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
+ qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
+ qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
+ qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0,
+ rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd,
+ wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ]
+
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ drive-strength: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5332-tlmm";
+ reg = <0x01000000 0x300000>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ gpio-ranges = <&tlmm 0 0 53>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <0x2>;
+
+ serial0-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp0_uart0";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 2/9] pinctrl: qcom: Introduce IPQ5332 TLMM driver
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 7:12 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm
platforms, so add a driver for it.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Grouped the individual pin entries of pta[0-2] and xfem[0-7]
to pta and xfem
- Used the descriptive function names for wci pins to avoid the
ambiguity
- Unwrapped the entries in ipq5332_groups for better
readability
Changes in V2:
- Converted the function names to lowercase and sort it
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5332.c | 861 +++++++++++++++++++++++++
3 files changed, 872 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5332.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 8d4f871e07cf..10a549648819 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -48,6 +48,16 @@ config PINCTRL_IPQ8064
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
+config PINCTRL_IPQ5332
+ tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ depends on PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc IPQ5332 platform.
+
config PINCTRL_IPQ8074
tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
depends on OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 6763aa8d319c..11b14c2805b0 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
+obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c
new file mode 100644
index 000000000000..e78d11292f42
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c
@@ -0,0 +1,861 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
+ .intr_status_reg = 0xc + REG_SIZE * id, \
+ .intr_target_reg = 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+static const struct pinctrl_pin_desc ipq5332_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+
+enum ipq5332_functions {
+ msm_mux_atest_char,
+ msm_mux_atest_char0,
+ msm_mux_atest_char1,
+ msm_mux_atest_char2,
+ msm_mux_atest_char3,
+ msm_mux_atest_tic,
+ msm_mux_audio_pri,
+ msm_mux_audio_pri0,
+ msm_mux_audio_pri1,
+ msm_mux_audio_sec,
+ msm_mux_audio_sec0,
+ msm_mux_audio_sec1,
+ msm_mux_blsp0_i2c,
+ msm_mux_blsp0_spi,
+ msm_mux_blsp0_uart0,
+ msm_mux_blsp0_uart1,
+ msm_mux_blsp1_i2c0,
+ msm_mux_blsp1_i2c1,
+ msm_mux_blsp1_spi0,
+ msm_mux_blsp1_spi1,
+ msm_mux_blsp1_uart0,
+ msm_mux_blsp1_uart1,
+ msm_mux_blsp1_uart2,
+ msm_mux_blsp2_i2c0,
+ msm_mux_blsp2_i2c1,
+ msm_mux_blsp2_spi,
+ msm_mux_blsp2_spi0,
+ msm_mux_blsp2_spi1,
+ msm_mux_core_voltage,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_cri_trng2,
+ msm_mux_cri_trng3,
+ msm_mux_cxc_clk,
+ msm_mux_cxc_data,
+ msm_mux_dbg_out,
+ msm_mux_gcc_plltest,
+ msm_mux_gcc_tlmm,
+ msm_mux_gpio,
+ msm_mux_lock_det,
+ msm_mux_mac0,
+ msm_mux_mac1,
+ msm_mux_mdc0,
+ msm_mux_mdc1,
+ msm_mux_mdio0,
+ msm_mux_mdio1,
+ msm_mux_pc,
+ msm_mux_pcie0_clk,
+ msm_mux_pcie0_wake,
+ msm_mux_pcie1_clk,
+ msm_mux_pcie1_wake,
+ msm_mux_pcie2_clk,
+ msm_mux_pcie2_wake,
+ msm_mux_pll_test,
+ msm_mux_prng_rosc0,
+ msm_mux_prng_rosc1,
+ msm_mux_prng_rosc2,
+ msm_mux_prng_rosc3,
+ msm_mux_pta,
+ msm_mux_pwm0,
+ msm_mux_pwm1,
+ msm_mux_pwm2,
+ msm_mux_pwm3,
+ msm_mux_qdss_cti_trig_in_a0,
+ msm_mux_qdss_cti_trig_in_a1,
+ msm_mux_qdss_cti_trig_in_b0,
+ msm_mux_qdss_cti_trig_in_b1,
+ msm_mux_qdss_cti_trig_out_a0,
+ msm_mux_qdss_cti_trig_out_a1,
+ msm_mux_qdss_cti_trig_out_b0,
+ msm_mux_qdss_cti_trig_out_b1,
+ msm_mux_qdss_traceclk_a,
+ msm_mux_qdss_traceclk_b,
+ msm_mux_qdss_tracectl_a,
+ msm_mux_qdss_tracectl_b,
+ msm_mux_qdss_tracedata_a,
+ msm_mux_qdss_tracedata_b,
+ msm_mux_qspi_data,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs,
+ msm_mux_resout,
+ msm_mux_rx0,
+ msm_mux_rx1,
+ msm_mux_sdc_data,
+ msm_mux_sdc_clk,
+ msm_mux_sdc_cmd,
+ msm_mux_tsens_max,
+ msm_mux_wci_txd,
+ msm_mux_wci_rxd,
+ msm_mux_wsi_clk,
+ msm_mux_wsi_clk3,
+ msm_mux_wsi_data,
+ msm_mux_wsi_data3,
+ msm_mux_wsis_reset,
+ msm_mux_xfem,
+ msm_mux__,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52",
+};
+
+static const char * const atest_char_groups[] = {
+ "gpio46",
+};
+
+static const char * const atest_char0_groups[] = {
+ "gpio0",
+};
+
+static const char * const atest_char1_groups[] = {
+ "gpio1",
+};
+
+static const char * const atest_char2_groups[] = {
+ "gpio2",
+};
+
+static const char * const atest_char3_groups[] = {
+ "gpio3",
+};
+
+static const char * const atest_tic_groups[] = {
+ "gpio9",
+};
+
+static const char * const audio_pri_groups[] = {
+ "gpio29", "gpio30", "gpio31", "gpio32",
+};
+
+static const char * const audio_pri0_groups[] = {
+ "gpio34", "gpio34",
+};
+
+static const char * const audio_pri1_groups[] = {
+ "gpio43", "gpio43",
+};
+
+static const char * const audio_sec_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio36",
+};
+
+static const char * const audio_sec0_groups[] = {
+ "gpio30", "gpio30",
+};
+
+static const char * const audio_sec1_groups[] = {
+ "gpio45", "gpio45",
+};
+
+static const char * const blsp0_i2c_groups[] = {
+ "gpio16", "gpio17",
+};
+
+static const char * const blsp0_spi_groups[] = {
+ "gpio14", "gpio15", "gpio16", "gpio17",
+};
+
+static const char * const blsp0_uart0_groups[] = {
+ "gpio18", "gpio19",
+};
+
+static const char * const blsp0_uart1_groups[] = {
+ "gpio27", "gpio28",
+};
+
+static const char * const blsp1_i2c0_groups[] = {
+ "gpio29", "gpio30",
+};
+
+static const char * const blsp1_i2c1_groups[] = {
+ "gpio40", "gpio41",
+};
+
+static const char * const blsp1_spi0_groups[] = {
+ "gpio29", "gpio30", "gpio31", "gpio32",
+};
+
+static const char * const blsp1_spi1_groups[] = {
+ "gpio25", "gpio26", "gpio27", "gpio28",
+};
+
+static const char * const blsp1_uart0_groups[] = {
+ "gpio14", "gpio15", "gpio16", "gpio17",
+};
+
+static const char * const blsp1_uart1_groups[] = {
+ "gpio25", "gpio26", "gpio27", "gpio28",
+};
+
+static const char * const blsp1_uart2_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio36",
+};
+
+static const char * const blsp2_i2c0_groups[] = {
+ "gpio43", "gpio45",
+};
+
+static const char * const blsp2_i2c1_groups[] = {
+ "gpio33", "gpio34",
+};
+
+static const char * const blsp2_spi_groups[] = {
+ "gpio37",
+};
+
+static const char * const blsp2_spi0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio36",
+};
+
+static const char * const blsp2_spi1_groups[] = {
+ "gpio40", "gpio41", "gpio42", "gpio52",
+};
+
+static const char * const core_voltage_groups[] = {
+ "gpio21", "gpio23",
+};
+
+static const char * const cri_trng0_groups[] = {
+ "gpio17",
+};
+
+static const char * const cri_trng1_groups[] = {
+ "gpio18",
+};
+
+static const char * const cri_trng2_groups[] = {
+ "gpio19",
+};
+
+static const char * const cri_trng3_groups[] = {
+ "gpio20",
+};
+
+static const char * const cxc_clk_groups[] = {
+ "gpio49",
+};
+
+static const char * const cxc_data_groups[] = {
+ "gpio50",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio48",
+};
+
+static const char * const gcc_plltest_groups[] = {
+ "gpio43", "gpio45",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+ "gpio44",
+};
+
+static const char * const lock_det_groups[] = {
+ "gpio51",
+};
+
+static const char * const mac0_groups[] = {
+ "gpio18",
+};
+
+static const char * const mac1_groups[] = {
+ "gpio19",
+};
+
+static const char * const mdc0_groups[] = {
+ "gpio25",
+};
+
+static const char * const mdc1_groups[] = {
+ "gpio27",
+};
+
+static const char * const mdio0_groups[] = {
+ "gpio26",
+};
+
+static const char * const mdio1_groups[] = {
+ "gpio28",
+};
+
+static const char * const pc_groups[] = {
+ "gpio35",
+};
+
+static const char * const pcie0_clk_groups[] = {
+ "gpio37",
+};
+
+static const char * const pcie0_wake_groups[] = {
+ "gpio39",
+};
+
+static const char * const pcie1_clk_groups[] = {
+ "gpio46",
+};
+
+static const char * const pcie1_wake_groups[] = {
+ "gpio48",
+};
+
+static const char * const pcie2_clk_groups[] = {
+ "gpio43",
+};
+
+static const char * const pcie2_wake_groups[] = {
+ "gpio45",
+};
+
+static const char * const pll_test_groups[] = {
+ "gpio49",
+};
+
+static const char * const prng_rosc0_groups[] = {
+ "gpio22",
+};
+
+static const char * const prng_rosc1_groups[] = {
+ "gpio24",
+};
+
+static const char * const prng_rosc2_groups[] = {
+ "gpio25",
+};
+
+static const char * const prng_rosc3_groups[] = {
+ "gpio26",
+};
+
+static const char * const pta_groups[] = {
+ "gpio49", "gpio50", "gpio51",
+};
+
+static const char * const pwm0_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46",
+};
+
+static const char * const pwm1_groups[] = {
+ "gpio29", "gpio30", "gpio31", "gpio32",
+};
+
+static const char * const pwm2_groups[] = {
+ "gpio25", "gpio26", "gpio27", "gpio28",
+};
+
+static const char * const pwm3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+ "gpio5",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+ "gpio7",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+ "gpio47",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+ "gpio49",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+ "gpio4",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+ "gpio6",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+ "gpio46",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+ "gpio48",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+ "gpio8",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+ "gpio45",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+ "gpio9",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+ "gpio44",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+ "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
+ "gpio17", "gpio18", "gpio19", "gpio20", "gpio22", "gpio24", "gpio25",
+ "gpio26", "gpio27",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio52",
+};
+
+static const char * const qspi_clk_groups[] = {
+ "gpio13",
+};
+
+static const char * const qspi_cs_groups[] = {
+ "gpio12",
+};
+
+static const char * const qspi_data_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const resout_groups[] = {
+ "gpio20",
+};
+
+static const char * const rx0_groups[] = {
+ "gpio48",
+};
+
+static const char * const rx1_groups[] = {
+ "gpio45",
+};
+
+static const char * const sdc_clk_groups[] = {
+ "gpio13",
+};
+
+static const char * const sdc_cmd_groups[] = {
+ "gpio12",
+};
+
+static const char * const sdc_data_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const tsens_max_groups[] = {
+ "gpio28",
+};
+
+static const char * const wci_txd_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio36", "gpio43", "gpio45",
+};
+
+static const char * const wci_rxd_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio35", "gpio36", "gpio43", "gpio45",
+};
+
+static const char * const wsi_clk_groups[] = {
+ "gpio40", "gpio42",
+};
+
+static const char * const wsi_clk3_groups[] = {
+ "gpio43",
+};
+
+static const char * const wsi_data_groups[] = {
+ "gpio41", "gpio52",
+};
+
+static const char * const wsi_data3_groups[] = {
+ "gpio44",
+};
+
+static const char * const wsis_reset_groups[] = {
+ "gpio41",
+};
+
+static const char * const xfem_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const struct msm_function ipq5332_functions[] = {
+ FUNCTION(atest_char),
+ FUNCTION(atest_char0),
+ FUNCTION(atest_char1),
+ FUNCTION(atest_char2),
+ FUNCTION(atest_char3),
+ FUNCTION(atest_tic),
+ FUNCTION(audio_pri),
+ FUNCTION(audio_pri0),
+ FUNCTION(audio_pri1),
+ FUNCTION(audio_sec),
+ FUNCTION(audio_sec0),
+ FUNCTION(audio_sec1),
+ FUNCTION(blsp0_i2c),
+ FUNCTION(blsp0_spi),
+ FUNCTION(blsp0_uart0),
+ FUNCTION(blsp0_uart1),
+ FUNCTION(blsp1_i2c0),
+ FUNCTION(blsp1_i2c1),
+ FUNCTION(blsp1_spi0),
+ FUNCTION(blsp1_spi1),
+ FUNCTION(blsp1_uart0),
+ FUNCTION(blsp1_uart1),
+ FUNCTION(blsp1_uart2),
+ FUNCTION(blsp2_i2c0),
+ FUNCTION(blsp2_i2c1),
+ FUNCTION(blsp2_spi),
+ FUNCTION(blsp2_spi0),
+ FUNCTION(blsp2_spi1),
+ FUNCTION(core_voltage),
+ FUNCTION(cri_trng0),
+ FUNCTION(cri_trng1),
+ FUNCTION(cri_trng2),
+ FUNCTION(cri_trng3),
+ FUNCTION(cxc_clk),
+ FUNCTION(cxc_data),
+ FUNCTION(dbg_out),
+ FUNCTION(gcc_plltest),
+ FUNCTION(gcc_tlmm),
+ FUNCTION(gpio),
+ FUNCTION(lock_det),
+ FUNCTION(mac0),
+ FUNCTION(mac1),
+ FUNCTION(mdc0),
+ FUNCTION(mdc1),
+ FUNCTION(mdio0),
+ FUNCTION(mdio1),
+ FUNCTION(pc),
+ FUNCTION(pcie0_clk),
+ FUNCTION(pcie0_wake),
+ FUNCTION(pcie1_clk),
+ FUNCTION(pcie1_wake),
+ FUNCTION(pcie2_clk),
+ FUNCTION(pcie2_wake),
+ FUNCTION(pll_test),
+ FUNCTION(prng_rosc0),
+ FUNCTION(prng_rosc1),
+ FUNCTION(prng_rosc2),
+ FUNCTION(prng_rosc3),
+ FUNCTION(pta),
+ FUNCTION(pwm0),
+ FUNCTION(pwm1),
+ FUNCTION(pwm2),
+ FUNCTION(pwm3),
+ FUNCTION(qdss_cti_trig_in_a0),
+ FUNCTION(qdss_cti_trig_in_a1),
+ FUNCTION(qdss_cti_trig_in_b0),
+ FUNCTION(qdss_cti_trig_in_b1),
+ FUNCTION(qdss_cti_trig_out_a0),
+ FUNCTION(qdss_cti_trig_out_a1),
+ FUNCTION(qdss_cti_trig_out_b0),
+ FUNCTION(qdss_cti_trig_out_b1),
+ FUNCTION(qdss_traceclk_a),
+ FUNCTION(qdss_traceclk_b),
+ FUNCTION(qdss_tracectl_a),
+ FUNCTION(qdss_tracectl_b),
+ FUNCTION(qdss_tracedata_a),
+ FUNCTION(qdss_tracedata_b),
+ FUNCTION(qspi_data),
+ FUNCTION(qspi_clk),
+ FUNCTION(qspi_cs),
+ FUNCTION(resout),
+ FUNCTION(rx0),
+ FUNCTION(rx1),
+ FUNCTION(sdc_data),
+ FUNCTION(sdc_clk),
+ FUNCTION(sdc_cmd),
+ FUNCTION(tsens_max),
+ FUNCTION(wci_txd),
+ FUNCTION(wci_rxd),
+ FUNCTION(wsi_clk),
+ FUNCTION(wsi_clk3),
+ FUNCTION(wsi_data),
+ FUNCTION(wsi_data3),
+ FUNCTION(wsis_reset),
+ FUNCTION(xfem),
+};
+
+static const struct msm_pingroup ipq5332_groups[] = {
+ PINGROUP(0, atest_char0, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(1, atest_char1, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(2, atest_char2, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(3, atest_char3, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(4, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(5, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(6, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(7, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(8, sdc_data, qspi_data, pwm3, qdss_traceclk_a, _, _, _, _, _),
+ PINGROUP(9, sdc_data, qspi_data, pwm3, qdss_tracectl_a, _, atest_tic, _, _, _),
+ PINGROUP(10, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(11, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(12, sdc_cmd, qspi_cs, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(13, sdc_clk, qspi_clk, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(14, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(15, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(16, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(17, blsp0_spi, blsp0_i2c, blsp1_uart0, _, cri_trng0, qdss_tracedata_a, _, _, _),
+ PINGROUP(18, blsp0_uart0, mac0, _, cri_trng1, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(19, blsp0_uart0, mac1, _, cri_trng2, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(20, resout, _, cri_trng3, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(21, core_voltage, _, _, _, _, _, _, _, _),
+ PINGROUP(22, _, prng_rosc0, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(23, core_voltage, _, _, _, _, _, _, _, _),
+ PINGROUP(24, _, prng_rosc1, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(25, mdc0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc2, qdss_tracedata_a, _),
+ PINGROUP(26, mdio0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc3, qdss_tracedata_a, _),
+ PINGROUP(27, mdc1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, _, qdss_tracedata_a, _),
+ PINGROUP(28, mdio1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, tsens_max, _, _),
+ PINGROUP(29, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, _, qdss_tracedata_b, _, _, _),
+ PINGROUP(30, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, audio_sec0, audio_sec0, _, qdss_tracedata_b, _),
+ PINGROUP(31, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(32, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(33, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, _, qdss_tracedata_b, _, _, _),
+ PINGROUP(34, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, audio_pri0, audio_pri0, _, qdss_tracedata_b, _),
+ PINGROUP(35, audio_sec, blsp1_uart2, pc, wci_rxd, blsp2_spi0, _, qdss_tracedata_b, _, _),
+ PINGROUP(36, audio_sec, blsp1_uart2, wci_txd, wci_rxd, blsp2_spi0, _, qdss_tracedata_b, _, _),
+ PINGROUP(37, pcie0_clk, blsp2_spi, _, qdss_tracedata_b, _, _, _, _, _),
+ PINGROUP(38, _, qdss_tracedata_b, _, _, _, _, _, _, _),
+ PINGROUP(39, pcie0_wake, _, qdss_tracedata_b, _, _, _, _, _, _),
+ PINGROUP(40, wsi_clk, blsp1_i2c1, blsp2_spi1, _, _, qdss_tracedata_b, _, _, _),
+ PINGROUP(41, wsi_data, blsp1_i2c1, blsp2_spi1, _, _, qdss_tracedata_b, _, wsis_reset, _),
+ PINGROUP(42, wsi_clk, blsp2_spi1, _, qdss_tracedata_b, _, _, _, _, _),
+ PINGROUP(43, pcie2_clk, wci_txd, wci_rxd, blsp2_i2c0, pwm0, audio_pri1, audio_pri1, _, gcc_plltest),
+ PINGROUP(44, pwm0, _, gcc_tlmm, qdss_tracectl_b, _, wsi_data3, _, _, _),
+ PINGROUP(45, pcie2_wake, wci_txd, wci_rxd, blsp2_i2c0, rx1, pwm0, audio_sec1, audio_sec1, _),
+ PINGROUP(46, pcie1_clk, atest_char, pwm0, _, qdss_cti_trig_out_b0, _, _, _, _),
+ PINGROUP(47, _, qdss_cti_trig_in_b0, _, _, _, _, _, _, _),
+ PINGROUP(48, pcie1_wake, rx0, dbg_out, qdss_cti_trig_out_b1, _, _, _, _, _),
+ PINGROUP(49, pta, cxc_clk, pll_test, _, qdss_cti_trig_in_b1, _, _, _, _),
+ PINGROUP(50, pta, cxc_data, _, _, _, _, _, _, _),
+ PINGROUP(51, pta, lock_det, _, _, _, _, _, _, _),
+ PINGROUP(52, wsi_data, blsp2_spi1, _, qdss_tracedata_b, _, _, _, _, _),
+};
+
+static const struct msm_pinctrl_soc_data ipq5332_pinctrl = {
+ .pins = ipq5332_pins,
+ .npins = ARRAY_SIZE(ipq5332_pins),
+ .functions = ipq5332_functions,
+ .nfunctions = ARRAY_SIZE(ipq5332_functions),
+ .groups = ipq5332_groups,
+ .ngroups = ARRAY_SIZE(ipq5332_groups),
+ .ngpios = 53,
+};
+
+static int ipq5332_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &ipq5332_pinctrl);
+}
+
+static const struct of_device_id ipq5332_pinctrl_of_match[] = {
+ { .compatible = "qcom,ipq5332-tlmm", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ipq5332_pinctrl_of_match);
+
+static struct platform_driver ipq5332_pinctrl_driver = {
+ .driver = {
+ .name = "ipq5332-tlmm",
+ .of_match_table = ipq5332_pinctrl_of_match,
+ },
+ .probe = ipq5332_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init ipq5332_pinctrl_init(void)
+{
+ return platform_driver_register(&ipq5332_pinctrl_driver);
+}
+arch_initcall(ipq5332_pinctrl_init);
+
+static void __exit ipq5332_pinctrl_exit(void)
+{
+ platform_driver_unregister(&ipq5332_pinctrl_driver);
+}
+module_exit(ipq5332_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI IPQ5332 TLMM driver");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 2/9] pinctrl: qcom: Introduce IPQ5332 TLMM driver
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm
platforms, so add a driver for it.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Grouped the individual pin entries of pta[0-2] and xfem[0-7]
to pta and xfem
- Used the descriptive function names for wci pins to avoid the
ambiguity
- Unwrapped the entries in ipq5332_groups for better
readability
Changes in V2:
- Converted the function names to lowercase and sort it
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5332.c | 861 +++++++++++++++++++++++++
3 files changed, 872 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5332.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 8d4f871e07cf..10a549648819 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -48,6 +48,16 @@ config PINCTRL_IPQ8064
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
+config PINCTRL_IPQ5332
+ tristate "Qualcomm Technologies Inc IPQ5332 pin controller driver"
+ depends on OF
+ depends on ARM64 || COMPILE_TEST
+ depends on PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc IPQ5332 platform.
+
config PINCTRL_IPQ8074
tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
depends on OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 6763aa8d319c..11b14c2805b0 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
+obj-$(CONFIG_PINCTRL_IPQ5332) += pinctrl-ipq5332.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5332.c b/drivers/pinctrl/qcom/pinctrl-ipq5332.c
new file mode 100644
index 000000000000..e78d11292f42
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq5332.c
@@ -0,0 +1,861 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = REG_SIZE * id, \
+ .io_reg = 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
+ .intr_status_reg = 0xc + REG_SIZE * id, \
+ .intr_target_reg = 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+static const struct pinctrl_pin_desc ipq5332_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+
+enum ipq5332_functions {
+ msm_mux_atest_char,
+ msm_mux_atest_char0,
+ msm_mux_atest_char1,
+ msm_mux_atest_char2,
+ msm_mux_atest_char3,
+ msm_mux_atest_tic,
+ msm_mux_audio_pri,
+ msm_mux_audio_pri0,
+ msm_mux_audio_pri1,
+ msm_mux_audio_sec,
+ msm_mux_audio_sec0,
+ msm_mux_audio_sec1,
+ msm_mux_blsp0_i2c,
+ msm_mux_blsp0_spi,
+ msm_mux_blsp0_uart0,
+ msm_mux_blsp0_uart1,
+ msm_mux_blsp1_i2c0,
+ msm_mux_blsp1_i2c1,
+ msm_mux_blsp1_spi0,
+ msm_mux_blsp1_spi1,
+ msm_mux_blsp1_uart0,
+ msm_mux_blsp1_uart1,
+ msm_mux_blsp1_uart2,
+ msm_mux_blsp2_i2c0,
+ msm_mux_blsp2_i2c1,
+ msm_mux_blsp2_spi,
+ msm_mux_blsp2_spi0,
+ msm_mux_blsp2_spi1,
+ msm_mux_core_voltage,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_cri_trng2,
+ msm_mux_cri_trng3,
+ msm_mux_cxc_clk,
+ msm_mux_cxc_data,
+ msm_mux_dbg_out,
+ msm_mux_gcc_plltest,
+ msm_mux_gcc_tlmm,
+ msm_mux_gpio,
+ msm_mux_lock_det,
+ msm_mux_mac0,
+ msm_mux_mac1,
+ msm_mux_mdc0,
+ msm_mux_mdc1,
+ msm_mux_mdio0,
+ msm_mux_mdio1,
+ msm_mux_pc,
+ msm_mux_pcie0_clk,
+ msm_mux_pcie0_wake,
+ msm_mux_pcie1_clk,
+ msm_mux_pcie1_wake,
+ msm_mux_pcie2_clk,
+ msm_mux_pcie2_wake,
+ msm_mux_pll_test,
+ msm_mux_prng_rosc0,
+ msm_mux_prng_rosc1,
+ msm_mux_prng_rosc2,
+ msm_mux_prng_rosc3,
+ msm_mux_pta,
+ msm_mux_pwm0,
+ msm_mux_pwm1,
+ msm_mux_pwm2,
+ msm_mux_pwm3,
+ msm_mux_qdss_cti_trig_in_a0,
+ msm_mux_qdss_cti_trig_in_a1,
+ msm_mux_qdss_cti_trig_in_b0,
+ msm_mux_qdss_cti_trig_in_b1,
+ msm_mux_qdss_cti_trig_out_a0,
+ msm_mux_qdss_cti_trig_out_a1,
+ msm_mux_qdss_cti_trig_out_b0,
+ msm_mux_qdss_cti_trig_out_b1,
+ msm_mux_qdss_traceclk_a,
+ msm_mux_qdss_traceclk_b,
+ msm_mux_qdss_tracectl_a,
+ msm_mux_qdss_tracectl_b,
+ msm_mux_qdss_tracedata_a,
+ msm_mux_qdss_tracedata_b,
+ msm_mux_qspi_data,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs,
+ msm_mux_resout,
+ msm_mux_rx0,
+ msm_mux_rx1,
+ msm_mux_sdc_data,
+ msm_mux_sdc_clk,
+ msm_mux_sdc_cmd,
+ msm_mux_tsens_max,
+ msm_mux_wci_txd,
+ msm_mux_wci_rxd,
+ msm_mux_wsi_clk,
+ msm_mux_wsi_clk3,
+ msm_mux_wsi_data,
+ msm_mux_wsi_data3,
+ msm_mux_wsis_reset,
+ msm_mux_xfem,
+ msm_mux__,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52",
+};
+
+static const char * const atest_char_groups[] = {
+ "gpio46",
+};
+
+static const char * const atest_char0_groups[] = {
+ "gpio0",
+};
+
+static const char * const atest_char1_groups[] = {
+ "gpio1",
+};
+
+static const char * const atest_char2_groups[] = {
+ "gpio2",
+};
+
+static const char * const atest_char3_groups[] = {
+ "gpio3",
+};
+
+static const char * const atest_tic_groups[] = {
+ "gpio9",
+};
+
+static const char * const audio_pri_groups[] = {
+ "gpio29", "gpio30", "gpio31", "gpio32",
+};
+
+static const char * const audio_pri0_groups[] = {
+ "gpio34", "gpio34",
+};
+
+static const char * const audio_pri1_groups[] = {
+ "gpio43", "gpio43",
+};
+
+static const char * const audio_sec_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio36",
+};
+
+static const char * const audio_sec0_groups[] = {
+ "gpio30", "gpio30",
+};
+
+static const char * const audio_sec1_groups[] = {
+ "gpio45", "gpio45",
+};
+
+static const char * const blsp0_i2c_groups[] = {
+ "gpio16", "gpio17",
+};
+
+static const char * const blsp0_spi_groups[] = {
+ "gpio14", "gpio15", "gpio16", "gpio17",
+};
+
+static const char * const blsp0_uart0_groups[] = {
+ "gpio18", "gpio19",
+};
+
+static const char * const blsp0_uart1_groups[] = {
+ "gpio27", "gpio28",
+};
+
+static const char * const blsp1_i2c0_groups[] = {
+ "gpio29", "gpio30",
+};
+
+static const char * const blsp1_i2c1_groups[] = {
+ "gpio40", "gpio41",
+};
+
+static const char * const blsp1_spi0_groups[] = {
+ "gpio29", "gpio30", "gpio31", "gpio32",
+};
+
+static const char * const blsp1_spi1_groups[] = {
+ "gpio25", "gpio26", "gpio27", "gpio28",
+};
+
+static const char * const blsp1_uart0_groups[] = {
+ "gpio14", "gpio15", "gpio16", "gpio17",
+};
+
+static const char * const blsp1_uart1_groups[] = {
+ "gpio25", "gpio26", "gpio27", "gpio28",
+};
+
+static const char * const blsp1_uart2_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio36",
+};
+
+static const char * const blsp2_i2c0_groups[] = {
+ "gpio43", "gpio45",
+};
+
+static const char * const blsp2_i2c1_groups[] = {
+ "gpio33", "gpio34",
+};
+
+static const char * const blsp2_spi_groups[] = {
+ "gpio37",
+};
+
+static const char * const blsp2_spi0_groups[] = {
+ "gpio33", "gpio34", "gpio35", "gpio36",
+};
+
+static const char * const blsp2_spi1_groups[] = {
+ "gpio40", "gpio41", "gpio42", "gpio52",
+};
+
+static const char * const core_voltage_groups[] = {
+ "gpio21", "gpio23",
+};
+
+static const char * const cri_trng0_groups[] = {
+ "gpio17",
+};
+
+static const char * const cri_trng1_groups[] = {
+ "gpio18",
+};
+
+static const char * const cri_trng2_groups[] = {
+ "gpio19",
+};
+
+static const char * const cri_trng3_groups[] = {
+ "gpio20",
+};
+
+static const char * const cxc_clk_groups[] = {
+ "gpio49",
+};
+
+static const char * const cxc_data_groups[] = {
+ "gpio50",
+};
+
+static const char * const dbg_out_groups[] = {
+ "gpio48",
+};
+
+static const char * const gcc_plltest_groups[] = {
+ "gpio43", "gpio45",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+ "gpio44",
+};
+
+static const char * const lock_det_groups[] = {
+ "gpio51",
+};
+
+static const char * const mac0_groups[] = {
+ "gpio18",
+};
+
+static const char * const mac1_groups[] = {
+ "gpio19",
+};
+
+static const char * const mdc0_groups[] = {
+ "gpio25",
+};
+
+static const char * const mdc1_groups[] = {
+ "gpio27",
+};
+
+static const char * const mdio0_groups[] = {
+ "gpio26",
+};
+
+static const char * const mdio1_groups[] = {
+ "gpio28",
+};
+
+static const char * const pc_groups[] = {
+ "gpio35",
+};
+
+static const char * const pcie0_clk_groups[] = {
+ "gpio37",
+};
+
+static const char * const pcie0_wake_groups[] = {
+ "gpio39",
+};
+
+static const char * const pcie1_clk_groups[] = {
+ "gpio46",
+};
+
+static const char * const pcie1_wake_groups[] = {
+ "gpio48",
+};
+
+static const char * const pcie2_clk_groups[] = {
+ "gpio43",
+};
+
+static const char * const pcie2_wake_groups[] = {
+ "gpio45",
+};
+
+static const char * const pll_test_groups[] = {
+ "gpio49",
+};
+
+static const char * const prng_rosc0_groups[] = {
+ "gpio22",
+};
+
+static const char * const prng_rosc1_groups[] = {
+ "gpio24",
+};
+
+static const char * const prng_rosc2_groups[] = {
+ "gpio25",
+};
+
+static const char * const prng_rosc3_groups[] = {
+ "gpio26",
+};
+
+static const char * const pta_groups[] = {
+ "gpio49", "gpio50", "gpio51",
+};
+
+static const char * const pwm0_groups[] = {
+ "gpio43", "gpio44", "gpio45", "gpio46",
+};
+
+static const char * const pwm1_groups[] = {
+ "gpio29", "gpio30", "gpio31", "gpio32",
+};
+
+static const char * const pwm2_groups[] = {
+ "gpio25", "gpio26", "gpio27", "gpio28",
+};
+
+static const char * const pwm3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+ "gpio5",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+ "gpio7",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+ "gpio47",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+ "gpio49",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+ "gpio4",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+ "gpio6",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+ "gpio46",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+ "gpio48",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+ "gpio8",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+ "gpio45",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+ "gpio9",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+ "gpio44",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+ "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
+ "gpio17", "gpio18", "gpio19", "gpio20", "gpio22", "gpio24", "gpio25",
+ "gpio26", "gpio27",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio52",
+};
+
+static const char * const qspi_clk_groups[] = {
+ "gpio13",
+};
+
+static const char * const qspi_cs_groups[] = {
+ "gpio12",
+};
+
+static const char * const qspi_data_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const resout_groups[] = {
+ "gpio20",
+};
+
+static const char * const rx0_groups[] = {
+ "gpio48",
+};
+
+static const char * const rx1_groups[] = {
+ "gpio45",
+};
+
+static const char * const sdc_clk_groups[] = {
+ "gpio13",
+};
+
+static const char * const sdc_cmd_groups[] = {
+ "gpio12",
+};
+
+static const char * const sdc_data_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+
+static const char * const tsens_max_groups[] = {
+ "gpio28",
+};
+
+static const char * const wci_txd_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio36", "gpio43", "gpio45",
+};
+
+static const char * const wci_rxd_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio35", "gpio36", "gpio43", "gpio45",
+};
+
+static const char * const wsi_clk_groups[] = {
+ "gpio40", "gpio42",
+};
+
+static const char * const wsi_clk3_groups[] = {
+ "gpio43",
+};
+
+static const char * const wsi_data_groups[] = {
+ "gpio41", "gpio52",
+};
+
+static const char * const wsi_data3_groups[] = {
+ "gpio44",
+};
+
+static const char * const wsis_reset_groups[] = {
+ "gpio41",
+};
+
+static const char * const xfem_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+};
+
+static const struct msm_function ipq5332_functions[] = {
+ FUNCTION(atest_char),
+ FUNCTION(atest_char0),
+ FUNCTION(atest_char1),
+ FUNCTION(atest_char2),
+ FUNCTION(atest_char3),
+ FUNCTION(atest_tic),
+ FUNCTION(audio_pri),
+ FUNCTION(audio_pri0),
+ FUNCTION(audio_pri1),
+ FUNCTION(audio_sec),
+ FUNCTION(audio_sec0),
+ FUNCTION(audio_sec1),
+ FUNCTION(blsp0_i2c),
+ FUNCTION(blsp0_spi),
+ FUNCTION(blsp0_uart0),
+ FUNCTION(blsp0_uart1),
+ FUNCTION(blsp1_i2c0),
+ FUNCTION(blsp1_i2c1),
+ FUNCTION(blsp1_spi0),
+ FUNCTION(blsp1_spi1),
+ FUNCTION(blsp1_uart0),
+ FUNCTION(blsp1_uart1),
+ FUNCTION(blsp1_uart2),
+ FUNCTION(blsp2_i2c0),
+ FUNCTION(blsp2_i2c1),
+ FUNCTION(blsp2_spi),
+ FUNCTION(blsp2_spi0),
+ FUNCTION(blsp2_spi1),
+ FUNCTION(core_voltage),
+ FUNCTION(cri_trng0),
+ FUNCTION(cri_trng1),
+ FUNCTION(cri_trng2),
+ FUNCTION(cri_trng3),
+ FUNCTION(cxc_clk),
+ FUNCTION(cxc_data),
+ FUNCTION(dbg_out),
+ FUNCTION(gcc_plltest),
+ FUNCTION(gcc_tlmm),
+ FUNCTION(gpio),
+ FUNCTION(lock_det),
+ FUNCTION(mac0),
+ FUNCTION(mac1),
+ FUNCTION(mdc0),
+ FUNCTION(mdc1),
+ FUNCTION(mdio0),
+ FUNCTION(mdio1),
+ FUNCTION(pc),
+ FUNCTION(pcie0_clk),
+ FUNCTION(pcie0_wake),
+ FUNCTION(pcie1_clk),
+ FUNCTION(pcie1_wake),
+ FUNCTION(pcie2_clk),
+ FUNCTION(pcie2_wake),
+ FUNCTION(pll_test),
+ FUNCTION(prng_rosc0),
+ FUNCTION(prng_rosc1),
+ FUNCTION(prng_rosc2),
+ FUNCTION(prng_rosc3),
+ FUNCTION(pta),
+ FUNCTION(pwm0),
+ FUNCTION(pwm1),
+ FUNCTION(pwm2),
+ FUNCTION(pwm3),
+ FUNCTION(qdss_cti_trig_in_a0),
+ FUNCTION(qdss_cti_trig_in_a1),
+ FUNCTION(qdss_cti_trig_in_b0),
+ FUNCTION(qdss_cti_trig_in_b1),
+ FUNCTION(qdss_cti_trig_out_a0),
+ FUNCTION(qdss_cti_trig_out_a1),
+ FUNCTION(qdss_cti_trig_out_b0),
+ FUNCTION(qdss_cti_trig_out_b1),
+ FUNCTION(qdss_traceclk_a),
+ FUNCTION(qdss_traceclk_b),
+ FUNCTION(qdss_tracectl_a),
+ FUNCTION(qdss_tracectl_b),
+ FUNCTION(qdss_tracedata_a),
+ FUNCTION(qdss_tracedata_b),
+ FUNCTION(qspi_data),
+ FUNCTION(qspi_clk),
+ FUNCTION(qspi_cs),
+ FUNCTION(resout),
+ FUNCTION(rx0),
+ FUNCTION(rx1),
+ FUNCTION(sdc_data),
+ FUNCTION(sdc_clk),
+ FUNCTION(sdc_cmd),
+ FUNCTION(tsens_max),
+ FUNCTION(wci_txd),
+ FUNCTION(wci_rxd),
+ FUNCTION(wsi_clk),
+ FUNCTION(wsi_clk3),
+ FUNCTION(wsi_data),
+ FUNCTION(wsi_data3),
+ FUNCTION(wsis_reset),
+ FUNCTION(xfem),
+};
+
+static const struct msm_pingroup ipq5332_groups[] = {
+ PINGROUP(0, atest_char0, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(1, atest_char1, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(2, atest_char2, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(3, atest_char3, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(4, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(5, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(6, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(7, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _, _, _),
+ PINGROUP(8, sdc_data, qspi_data, pwm3, qdss_traceclk_a, _, _, _, _, _),
+ PINGROUP(9, sdc_data, qspi_data, pwm3, qdss_tracectl_a, _, atest_tic, _, _, _),
+ PINGROUP(10, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(11, sdc_data, qspi_data, pwm3, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(12, sdc_cmd, qspi_cs, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(13, sdc_clk, qspi_clk, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(14, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(15, blsp0_spi, blsp1_uart0, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(16, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(17, blsp0_spi, blsp0_i2c, blsp1_uart0, _, cri_trng0, qdss_tracedata_a, _, _, _),
+ PINGROUP(18, blsp0_uart0, mac0, _, cri_trng1, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(19, blsp0_uart0, mac1, _, cri_trng2, qdss_tracedata_a, _, _, _, _),
+ PINGROUP(20, resout, _, cri_trng3, qdss_tracedata_a, _, _, _, _, _),
+ PINGROUP(21, core_voltage, _, _, _, _, _, _, _, _),
+ PINGROUP(22, _, prng_rosc0, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(23, core_voltage, _, _, _, _, _, _, _, _),
+ PINGROUP(24, _, prng_rosc1, qdss_tracedata_a, _, _, _, _, _, _),
+ PINGROUP(25, mdc0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc2, qdss_tracedata_a, _),
+ PINGROUP(26, mdio0, blsp1_uart1, blsp1_spi1, pwm2, _, _, prng_rosc3, qdss_tracedata_a, _),
+ PINGROUP(27, mdc1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, _, qdss_tracedata_a, _),
+ PINGROUP(28, mdio1, blsp0_uart1, blsp1_uart1, blsp1_spi1, pwm2, _, tsens_max, _, _),
+ PINGROUP(29, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, _, qdss_tracedata_b, _, _, _),
+ PINGROUP(30, audio_pri, blsp1_spi0, blsp1_i2c0, pwm1, audio_sec0, audio_sec0, _, qdss_tracedata_b, _),
+ PINGROUP(31, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(32, audio_pri, blsp1_spi0, pwm1, _, qdss_tracedata_b, _, _, _, _),
+ PINGROUP(33, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, _, qdss_tracedata_b, _, _, _),
+ PINGROUP(34, audio_sec, blsp1_uart2, blsp2_i2c1, blsp2_spi0, audio_pri0, audio_pri0, _, qdss_tracedata_b, _),
+ PINGROUP(35, audio_sec, blsp1_uart2, pc, wci_rxd, blsp2_spi0, _, qdss_tracedata_b, _, _),
+ PINGROUP(36, audio_sec, blsp1_uart2, wci_txd, wci_rxd, blsp2_spi0, _, qdss_tracedata_b, _, _),
+ PINGROUP(37, pcie0_clk, blsp2_spi, _, qdss_tracedata_b, _, _, _, _, _),
+ PINGROUP(38, _, qdss_tracedata_b, _, _, _, _, _, _, _),
+ PINGROUP(39, pcie0_wake, _, qdss_tracedata_b, _, _, _, _, _, _),
+ PINGROUP(40, wsi_clk, blsp1_i2c1, blsp2_spi1, _, _, qdss_tracedata_b, _, _, _),
+ PINGROUP(41, wsi_data, blsp1_i2c1, blsp2_spi1, _, _, qdss_tracedata_b, _, wsis_reset, _),
+ PINGROUP(42, wsi_clk, blsp2_spi1, _, qdss_tracedata_b, _, _, _, _, _),
+ PINGROUP(43, pcie2_clk, wci_txd, wci_rxd, blsp2_i2c0, pwm0, audio_pri1, audio_pri1, _, gcc_plltest),
+ PINGROUP(44, pwm0, _, gcc_tlmm, qdss_tracectl_b, _, wsi_data3, _, _, _),
+ PINGROUP(45, pcie2_wake, wci_txd, wci_rxd, blsp2_i2c0, rx1, pwm0, audio_sec1, audio_sec1, _),
+ PINGROUP(46, pcie1_clk, atest_char, pwm0, _, qdss_cti_trig_out_b0, _, _, _, _),
+ PINGROUP(47, _, qdss_cti_trig_in_b0, _, _, _, _, _, _, _),
+ PINGROUP(48, pcie1_wake, rx0, dbg_out, qdss_cti_trig_out_b1, _, _, _, _, _),
+ PINGROUP(49, pta, cxc_clk, pll_test, _, qdss_cti_trig_in_b1, _, _, _, _),
+ PINGROUP(50, pta, cxc_data, _, _, _, _, _, _, _),
+ PINGROUP(51, pta, lock_det, _, _, _, _, _, _, _),
+ PINGROUP(52, wsi_data, blsp2_spi1, _, qdss_tracedata_b, _, _, _, _, _),
+};
+
+static const struct msm_pinctrl_soc_data ipq5332_pinctrl = {
+ .pins = ipq5332_pins,
+ .npins = ARRAY_SIZE(ipq5332_pins),
+ .functions = ipq5332_functions,
+ .nfunctions = ARRAY_SIZE(ipq5332_functions),
+ .groups = ipq5332_groups,
+ .ngroups = ARRAY_SIZE(ipq5332_groups),
+ .ngpios = 53,
+};
+
+static int ipq5332_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &ipq5332_pinctrl);
+}
+
+static const struct of_device_id ipq5332_pinctrl_of_match[] = {
+ { .compatible = "qcom,ipq5332-tlmm", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ipq5332_pinctrl_of_match);
+
+static struct platform_driver ipq5332_pinctrl_driver = {
+ .driver = {
+ .name = "ipq5332-tlmm",
+ .of_match_table = ipq5332_pinctrl_of_match,
+ },
+ .probe = ipq5332_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init ipq5332_pinctrl_init(void)
+{
+ return platform_driver_register(&ipq5332_pinctrl_driver);
+}
+arch_initcall(ipq5332_pinctrl_init);
+
+static void __exit ipq5332_pinctrl_exit(void)
+{
+ platform_driver_unregister(&ipq5332_pinctrl_driver);
+}
+module_exit(ipq5332_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI IPQ5332 TLMM driver");
+MODULE_LICENSE("GPL");
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 3/9] clk: qcom: Add STROMER PLUS PLL type for IPQ5332
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 7:12 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Add the support for stromer plus pll, which is found on the IPQ5332
SoCs. Programming sequence is same as the stromer pll, so we can re-use
the same.
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- No changes
Changes in V2:
- Added the Reviewed-by tag
drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 3a79ddbce435..4e15094c05e0 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -216,6 +216,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x34,
[PLL_OFF_STATUS] = 0x28,
},
+ [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_USER_CTL] = 0x08,
+ [PLL_OFF_USER_CTL_U] = 0x0c,
+ [PLL_OFF_CONFIG_CTL] = 0x10,
+ [PLL_OFF_TEST_CTL] = 0x14,
+ [PLL_OFF_TEST_CTL_U] = 0x18,
+ [PLL_OFF_STATUS] = 0x1c,
+ [PLL_OFF_ALPHA_VAL] = 0x24,
+ [PLL_OFF_ALPHA_VAL_U] = 0x28,
+ },
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 21a351ded39d..3a849bfafbb0 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -27,6 +27,7 @@ enum {
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
CLK_ALPHA_PLL_TYPE_STROMER,
+ CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
CLK_ALPHA_PLL_TYPE_MAX,
};
--
2.17.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 3/9] clk: qcom: Add STROMER PLUS PLL type for IPQ5332
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Add the support for stromer plus pll, which is found on the IPQ5332
SoCs. Programming sequence is same as the stromer pll, so we can re-use
the same.
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- No changes
Changes in V2:
- Added the Reviewed-by tag
drivers/clk/qcom/clk-alpha-pll.c | 11 +++++++++++
drivers/clk/qcom/clk-alpha-pll.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 3a79ddbce435..4e15094c05e0 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -216,6 +216,17 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x34,
[PLL_OFF_STATUS] = 0x28,
},
+ [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_USER_CTL] = 0x08,
+ [PLL_OFF_USER_CTL_U] = 0x0c,
+ [PLL_OFF_CONFIG_CTL] = 0x10,
+ [PLL_OFF_TEST_CTL] = 0x14,
+ [PLL_OFF_TEST_CTL_U] = 0x18,
+ [PLL_OFF_STATUS] = 0x1c,
+ [PLL_OFF_ALPHA_VAL] = 0x24,
+ [PLL_OFF_ALPHA_VAL_U] = 0x28,
+ },
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 21a351ded39d..3a849bfafbb0 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -27,6 +27,7 @@ enum {
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
CLK_ALPHA_PLL_TYPE_STROMER,
+ CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
CLK_ALPHA_PLL_TYPE_MAX,
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 7:12 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Add binding for the Qualcomm IPQ5332 Global Clock Controller.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Actually I missed to remove the clocks in V2 which are supposed to
be removed. In V3 I have removed those and they are
GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK
- For the same, didn't add the Reviewed-By tags from Stephen and
Krzysztof
Changes in V2:
- property 'clocks' is marked required
- Renamed the include file name to match with compatible
.../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++
2 files changed, 417 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
new file mode 100644
index 000000000000..961311af400c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on IPQ5332
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on IPQ5332.
+
+ See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5332-gcc
+
+ clocks:
+ items:
+ - description: Board XO clock source
+ - description: Sleep clock source
+ - description: PCIE 2lane PHY pipe clock source
+ - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
+ - description: USB PCIE wrapper pipe clock source
+
+ clock-names:
+ items:
+ - const: xo
+ - const: sleep_clk
+ - const: pcie_2lane_phy_pipe_clk
+ - const: pcie_2lane_phy_pipe_clk_x1
+ - const: usb_pcie_wrapper_pipe_clk
+
+required:
+ - compatible
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@1800000 {
+ compatible = "qcom,ipq5332-gcc";
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <&pcie_2lane_phy_pipe_clk>,
+ <&pcie_2lane_phy_pipe_clk_x1>,
+ <&usb_pcie_wrapper_pipe_clk>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
new file mode 100644
index 000000000000..8a405a0a96d0
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -0,0 +1,356 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
+
+#define GPLL0_MAIN 0
+#define GPLL0 1
+#define GPLL2_MAIN 2
+#define GPLL2 3
+#define GPLL4_MAIN 4
+#define GPLL4 5
+#define GCC_ADSS_PWM_CLK 6
+#define GCC_ADSS_PWM_CLK_SRC 7
+#define GCC_AHB_CLK 8
+#define GCC_APSS_AXI_CLK_SRC 9
+#define GCC_BLSP1_AHB_CLK 10
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 15
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 16
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 17
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 18
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 19
+#define GCC_BLSP1_SLEEP_CLK 20
+#define GCC_BLSP1_UART1_APPS_CLK 21
+#define GCC_BLSP1_UART1_APPS_CLK_SRC 22
+#define GCC_BLSP1_UART2_APPS_CLK 23
+#define GCC_BLSP1_UART2_APPS_CLK_SRC 24
+#define GCC_BLSP1_UART3_APPS_CLK 25
+#define GCC_BLSP1_UART3_APPS_CLK_SRC 26
+#define GCC_CE_AHB_CLK 27
+#define GCC_CE_AXI_CLK 28
+#define GCC_CE_PCNOC_AHB_CLK 29
+#define GCC_CMN_12GPLL_AHB_CLK 30
+#define GCC_CMN_12GPLL_APU_CLK 31
+#define GCC_CMN_12GPLL_SYS_CLK 32
+#define GCC_GP1_CLK 33
+#define GCC_GP1_CLK_SRC 34
+#define GCC_GP2_CLK 35
+#define GCC_GP2_CLK_SRC 36
+#define GCC_LPASS_CORE_AXIM_CLK 37
+#define GCC_LPASS_SWAY_CLK 38
+#define GCC_LPASS_SWAY_CLK_SRC 39
+#define GCC_MDIO_AHB_CLK 40
+#define GCC_MDIO_SLAVE_AHB_CLK 41
+#define GCC_MEM_NOC_Q6_AXI_CLK 42
+#define GCC_MEM_NOC_TS_CLK 43
+#define GCC_NSS_TS_CLK 44
+#define GCC_NSS_TS_CLK_SRC 45
+#define GCC_NSSCC_CLK 46
+#define GCC_NSSCFG_CLK 47
+#define GCC_NSSNOC_ATB_CLK 48
+#define GCC_NSSNOC_NSSCC_CLK 49
+#define GCC_NSSNOC_QOSGEN_REF_CLK 50
+#define GCC_NSSNOC_SNOC_1_CLK 51
+#define GCC_NSSNOC_SNOC_CLK 52
+#define GCC_NSSNOC_TIMEOUT_REF_CLK 53
+#define GCC_NSSNOC_XO_DCD_CLK 54
+#define GCC_PCIE3X1_0_AHB_CLK 55
+#define GCC_PCIE3X1_0_AUX_CLK 56
+#define GCC_PCIE3X1_0_AXI_CLK_SRC 57
+#define GCC_PCIE3X1_0_AXI_M_CLK 58
+#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK 59
+#define GCC_PCIE3X1_0_AXI_S_CLK 60
+#define GCC_PCIE3X1_0_PIPE_CLK 61
+#define GCC_PCIE3X1_0_RCHG_CLK 62
+#define GCC_PCIE3X1_0_RCHG_CLK_SRC 63
+#define GCC_PCIE3X1_1_AHB_CLK 64
+#define GCC_PCIE3X1_1_AUX_CLK 65
+#define GCC_PCIE3X1_1_AXI_CLK_SRC 66
+#define GCC_PCIE3X1_1_AXI_M_CLK 67
+#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK 68
+#define GCC_PCIE3X1_1_AXI_S_CLK 69
+#define GCC_PCIE3X1_1_PIPE_CLK 70
+#define GCC_PCIE3X1_1_RCHG_CLK 71
+#define GCC_PCIE3X1_1_RCHG_CLK_SRC 72
+#define GCC_PCIE3X1_PHY_AHB_CLK 73
+#define GCC_PCIE3X2_AHB_CLK 74
+#define GCC_PCIE3X2_AUX_CLK 75
+#define GCC_PCIE3X2_AXI_M_CLK 76
+#define GCC_PCIE3X2_AXI_M_CLK_SRC 77
+#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK 78
+#define GCC_PCIE3X2_AXI_S_CLK 79
+#define GCC_PCIE3X2_AXI_S_CLK_SRC 80
+#define GCC_PCIE3X2_PHY_AHB_CLK 81
+#define GCC_PCIE3X2_PIPE_CLK 82
+#define GCC_PCIE3X2_RCHG_CLK 83
+#define GCC_PCIE3X2_RCHG_CLK_SRC 84
+#define GCC_PCIE_AUX_CLK_SRC 85
+#define GCC_PCNOC_AT_CLK 86
+#define GCC_PCNOC_BFDCD_CLK_SRC 87
+#define GCC_PCNOC_LPASS_CLK 88
+#define GCC_PRNG_AHB_CLK 89
+#define GCC_Q6_AHB_CLK 90
+#define GCC_Q6_AHB_S_CLK 91
+#define GCC_Q6_AXIM_CLK 92
+#define GCC_Q6_AXIM_CLK_SRC 93
+#define GCC_Q6_AXIS_CLK 94
+#define GCC_Q6_TSCTR_1TO2_CLK 95
+#define GCC_Q6SS_ATBM_CLK 96
+#define GCC_Q6SS_PCLKDBG_CLK 97
+#define GCC_Q6SS_TRIG_CLK 98
+#define GCC_QDSS_AT_CLK 99
+#define GCC_QDSS_AT_CLK_SRC 100
+#define GCC_QDSS_CFG_AHB_CLK 101
+#define GCC_QDSS_DAP_AHB_CLK 102
+#define GCC_QDSS_DAP_CLK 103
+#define GCC_QDSS_DAP_DIV_CLK_SRC 104
+#define GCC_QDSS_ETR_USB_CLK 105
+#define GCC_QDSS_EUD_AT_CLK 106
+#define GCC_QDSS_TSCTR_CLK_SRC 107
+#define GCC_QPIC_AHB_CLK 108
+#define GCC_QPIC_CLK 109
+#define GCC_QPIC_IO_MACRO_CLK 110
+#define GCC_QPIC_IO_MACRO_CLK_SRC 111
+#define GCC_QPIC_SLEEP_CLK 112
+#define GCC_SDCC1_AHB_CLK 113
+#define GCC_SDCC1_APPS_CLK 114
+#define GCC_SDCC1_APPS_CLK_SRC 115
+#define GCC_SLEEP_CLK_SRC 116
+#define GCC_SNOC_LPASS_CFG_CLK 117
+#define GCC_SNOC_NSSNOC_1_CLK 118
+#define GCC_SNOC_NSSNOC_CLK 119
+#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120
+#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121
+#define GCC_SNOC_PCIE3_1LANE_M_CLK 122
+#define GCC_SNOC_PCIE3_1LANE_S_CLK 123
+#define GCC_SNOC_PCIE3_2LANE_M_CLK 124
+#define GCC_SNOC_PCIE3_2LANE_S_CLK 125
+#define GCC_SNOC_USB_CLK 126
+#define GCC_SYS_NOC_AT_CLK 127
+#define GCC_SYS_NOC_WCSS_AHB_CLK 128
+#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129
+#define GCC_UNIPHY0_AHB_CLK 130
+#define GCC_UNIPHY0_SYS_CLK 131
+#define GCC_UNIPHY1_AHB_CLK 132
+#define GCC_UNIPHY1_SYS_CLK 133
+#define GCC_UNIPHY_SYS_CLK_SRC 134
+#define GCC_USB0_AUX_CLK 135
+#define GCC_USB0_AUX_CLK_SRC 136
+#define GCC_USB0_EUD_AT_CLK 137
+#define GCC_USB0_LFPS_CLK 138
+#define GCC_USB0_LFPS_CLK_SRC 139
+#define GCC_USB0_MASTER_CLK 140
+#define GCC_USB0_MASTER_CLK_SRC 141
+#define GCC_USB0_MOCK_UTMI_CLK 142
+#define GCC_USB0_MOCK_UTMI_CLK_SRC 143
+#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 144
+#define GCC_USB0_PHY_CFG_AHB_CLK 145
+#define GCC_USB0_PIPE_CLK 146
+#define GCC_USB0_SLEEP_CLK 147
+#define GCC_WCSS_AHB_CLK_SRC 148
+#define GCC_WCSS_AXIM_CLK 149
+#define GCC_WCSS_AXIS_CLK 150
+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 151
+#define GCC_WCSS_DBG_IFC_APB_CLK 152
+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 153
+#define GCC_WCSS_DBG_IFC_ATB_CLK 154
+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155
+#define GCC_WCSS_DBG_IFC_NTS_CLK 156
+#define GCC_WCSS_ECAHB_CLK 157
+#define GCC_WCSS_MST_ASYNC_BDG_CLK 158
+#define GCC_WCSS_SLV_ASYNC_BDG_CLK 159
+#define GCC_XO_CLK 160
+#define GCC_XO_CLK_SRC 161
+#define GCC_XO_DIV4_CLK 162
+#define GCC_IM_SLEEP_CLK 163
+#define GCC_NSSNOC_PCNOC_1_CLK 164
+#define GCC_MEM_NOC_AHB_CLK 165
+#define GCC_MEM_NOC_APSS_AXI_CLK 166
+#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC 167
+#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK 168
+#define GCC_PCIE3X2_PIPE_CLK_SRC 169
+#define GCC_PCIE3X1_0_PIPE_CLK_SRC 170
+#define GCC_PCIE3X1_1_PIPE_CLK_SRC 171
+#define GCC_USB0_PIPE_CLK_SRC 172
+
+#define GCC_ADSS_BCR 0
+#define GCC_ADSS_PWM_CLK_ARES 1
+#define GCC_AHB_CLK_ARES 2
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 3
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 4
+#define GCC_APSS_AHB_CLK_ARES 5
+#define GCC_APSS_AXI_CLK_ARES 6
+#define GCC_BLSP1_AHB_CLK_ARES 7
+#define GCC_BLSP1_BCR 8
+#define GCC_BLSP1_QUP1_BCR 9
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES 10
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES 11
+#define GCC_BLSP1_QUP2_BCR 12
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES 13
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES 14
+#define GCC_BLSP1_QUP3_BCR 15
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES 16
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES 17
+#define GCC_BLSP1_SLEEP_CLK_ARES 18
+#define GCC_BLSP1_UART1_APPS_CLK_ARES 19
+#define GCC_BLSP1_UART1_BCR 20
+#define GCC_BLSP1_UART2_APPS_CLK_ARES 21
+#define GCC_BLSP1_UART2_BCR 22
+#define GCC_BLSP1_UART3_APPS_CLK_ARES 23
+#define GCC_BLSP1_UART3_BCR 24
+#define GCC_CE_BCR 25
+#define GCC_CMN_BLK_BCR 26
+#define GCC_CMN_LDO0_BCR 27
+#define GCC_CMN_LDO1_BCR 28
+#define GCC_DCC_BCR 29
+#define GCC_GP1_CLK_ARES 30
+#define GCC_GP2_CLK_ARES 31
+#define GCC_LPASS_BCR 32
+#define GCC_LPASS_CORE_AXIM_CLK_ARES 33
+#define GCC_LPASS_SWAY_CLK_ARES 34
+#define GCC_MDIOM_BCR 35
+#define GCC_MDIOS_BCR 36
+#define GCC_NSS_BCR 37
+#define GCC_NSS_TS_CLK_ARES 38
+#define GCC_NSSCC_CLK_ARES 39
+#define GCC_NSSCFG_CLK_ARES 40
+#define GCC_NSSNOC_ATB_CLK_ARES 41
+#define GCC_NSSNOC_NSSCC_CLK_ARES 42
+#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 43
+#define GCC_NSSNOC_SNOC_1_CLK_ARES 44
+#define GCC_NSSNOC_SNOC_CLK_ARES 45
+#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 46
+#define GCC_NSSNOC_XO_DCD_CLK_ARES 47
+#define GCC_PCIE3X1_0_AHB_CLK_ARES 48
+#define GCC_PCIE3X1_0_AUX_CLK_ARES 49
+#define GCC_PCIE3X1_0_AXI_M_CLK_ARES 50
+#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES 51
+#define GCC_PCIE3X1_0_AXI_S_CLK_ARES 52
+#define GCC_PCIE3X1_0_BCR 53
+#define GCC_PCIE3X1_0_LINK_DOWN_BCR 54
+#define GCC_PCIE3X1_0_PHY_BCR 55
+#define GCC_PCIE3X1_0_PHY_PHY_BCR 56
+#define GCC_PCIE3X1_1_AHB_CLK_ARES 57
+#define GCC_PCIE3X1_1_AUX_CLK_ARES 58
+#define GCC_PCIE3X1_1_AXI_M_CLK_ARES 59
+#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES 60
+#define GCC_PCIE3X1_1_AXI_S_CLK_ARES 61
+#define GCC_PCIE3X1_1_BCR 62
+#define GCC_PCIE3X1_1_LINK_DOWN_BCR 63
+#define GCC_PCIE3X1_1_PHY_BCR 64
+#define GCC_PCIE3X1_1_PHY_PHY_BCR 65
+#define GCC_PCIE3X1_PHY_AHB_CLK_ARES 66
+#define GCC_PCIE3X2_AHB_CLK_ARES 67
+#define GCC_PCIE3X2_AUX_CLK_ARES 68
+#define GCC_PCIE3X2_AXI_M_CLK_ARES 69
+#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES 70
+#define GCC_PCIE3X2_AXI_S_CLK_ARES 71
+#define GCC_PCIE3X2_BCR 72
+#define GCC_PCIE3X2_LINK_DOWN_BCR 73
+#define GCC_PCIE3X2_PHY_AHB_CLK_ARES 74
+#define GCC_PCIE3X2_PHY_BCR 75
+#define GCC_PCIE3X2PHY_PHY_BCR 76
+#define GCC_PCNOC_BCR 77
+#define GCC_PCNOC_LPASS_CLK_ARES 78
+#define GCC_PRNG_AHB_CLK_ARES 79
+#define GCC_PRNG_BCR 80
+#define GCC_Q6_AHB_CLK_ARES 81
+#define GCC_Q6_AHB_S_CLK_ARES 82
+#define GCC_Q6_AXIM_CLK_ARES 83
+#define GCC_Q6_AXIS_CLK_ARES 84
+#define GCC_Q6_TSCTR_1TO2_CLK_ARES 85
+#define GCC_Q6SS_ATBM_CLK_ARES 86
+#define GCC_Q6SS_PCLKDBG_CLK_ARES 87
+#define GCC_Q6SS_TRIG_CLK_ARES 88
+#define GCC_QDSS_APB2JTAG_CLK_ARES 89
+#define GCC_QDSS_AT_CLK_ARES 90
+#define GCC_QDSS_BCR 91
+#define GCC_QDSS_CFG_AHB_CLK_ARES 92
+#define GCC_QDSS_DAP_AHB_CLK_ARES 93
+#define GCC_QDSS_DAP_CLK_ARES 94
+#define GCC_QDSS_ETR_USB_CLK_ARES 95
+#define GCC_QDSS_EUD_AT_CLK_ARES 96
+#define GCC_QDSS_STM_CLK_ARES 97
+#define GCC_QDSS_TRACECLKIN_CLK_ARES 98
+#define GCC_QDSS_TS_CLK_ARES 99
+#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 100
+#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 101
+#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 102
+#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 103
+#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 104
+#define GCC_QPIC_AHB_CLK_ARES 105
+#define GCC_QPIC_CLK_ARES 106
+#define GCC_QPIC_BCR 107
+#define GCC_QPIC_IO_MACRO_CLK_ARES 108
+#define GCC_QPIC_SLEEP_CLK_ARES 109
+#define GCC_QUSB2_0_PHY_BCR 110
+#define GCC_SDCC1_AHB_CLK_ARES 111
+#define GCC_SDCC1_APPS_CLK_ARES 112
+#define GCC_SDCC_BCR 113
+#define GCC_SNOC_BCR 114
+#define GCC_SNOC_LPASS_CFG_CLK_ARES 115
+#define GCC_SNOC_NSSNOC_1_CLK_ARES 116
+#define GCC_SNOC_NSSNOC_CLK_ARES 117
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES 118
+#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES 119
+#define GCC_UNIPHY0_AHB_CLK_ARES 120
+#define GCC_UNIPHY0_BCR 121
+#define GCC_UNIPHY0_SYS_CLK_ARES 122
+#define GCC_UNIPHY1_AHB_CLK_ARES 123
+#define GCC_UNIPHY1_BCR 124
+#define GCC_UNIPHY1_SYS_CLK_ARES 125
+#define GCC_USB0_AUX_CLK_ARES 126
+#define GCC_USB0_EUD_AT_CLK_ARES 127
+#define GCC_USB0_LFPS_CLK_ARES 128
+#define GCC_USB0_MASTER_CLK_ARES 129
+#define GCC_USB0_MOCK_UTMI_CLK_ARES 130
+#define GCC_USB0_PHY_BCR 131
+#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 132
+#define GCC_USB0_SLEEP_CLK_ARES 133
+#define GCC_USB3PHY_0_PHY_BCR 134
+#define GCC_USB_BCR 135
+#define GCC_WCSS_AXIM_CLK_ARES 136
+#define GCC_WCSS_AXIS_CLK_ARES 137
+#define GCC_WCSS_BCR 138
+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES 139
+#define GCC_WCSS_DBG_IFC_APB_CLK_ARES 140
+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES 141
+#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES 142
+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES 143
+#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES 144
+#define GCC_WCSS_ECAHB_CLK_ARES 145
+#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES 146
+#define GCC_WCSS_Q6_BCR 147
+#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES 148
+#define GCC_XO_CLK_ARES 149
+#define GCC_XO_DIV4_CLK_ARES 150
+#define GCC_Q6SS_DBG_ARES 151
+#define GCC_WCSS_DBG_BDG_ARES 152
+#define GCC_WCSS_DBG_ARES 153
+#define GCC_WCSS_AXI_S_ARES 154
+#define GCC_WCSS_AXI_M_ARES 155
+#define GCC_WCSSAON_ARES 156
+#define GCC_PCIE3X2_PIPE_ARES 157
+#define GCC_PCIE3X2_CORE_STICKY_ARES 158
+#define GCC_PCIE3X2_AXI_S_STICKY_ARES 159
+#define GCC_PCIE3X2_AXI_M_STICKY_ARES 160
+#define GCC_PCIE3X1_0_PIPE_ARES 161
+#define GCC_PCIE3X1_0_CORE_STICKY_ARES 162
+#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES 163
+#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES 164
+#define GCC_PCIE3X1_1_PIPE_ARES 165
+#define GCC_PCIE3X1_1_CORE_STICKY_ARES 166
+#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES 167
+#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES 168
+#define GCC_IM_SLEEP_CLK_ARES 169
+#define GCC_NSSNOC_PCNOC_1_CLK_ARES 170
+#define GCC_UNIPHY0_XPCS_ARES 171
+#define GCC_UNIPHY1_XPCS_ARES 172
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Add binding for the Qualcomm IPQ5332 Global Clock Controller.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Actually I missed to remove the clocks in V2 which are supposed to
be removed. In V3 I have removed those and they are
GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK
- For the same, didn't add the Reviewed-By tags from Stephen and
Krzysztof
Changes in V2:
- property 'clocks' is marked required
- Renamed the include file name to match with compatible
.../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++
include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++
2 files changed, 417 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
new file mode 100644
index 000000000000..961311af400c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on IPQ5332
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on IPQ5332.
+
+ See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5332-gcc
+
+ clocks:
+ items:
+ - description: Board XO clock source
+ - description: Sleep clock source
+ - description: PCIE 2lane PHY pipe clock source
+ - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
+ - description: USB PCIE wrapper pipe clock source
+
+ clock-names:
+ items:
+ - const: xo
+ - const: sleep_clk
+ - const: pcie_2lane_phy_pipe_clk
+ - const: pcie_2lane_phy_pipe_clk_x1
+ - const: usb_pcie_wrapper_pipe_clk
+
+required:
+ - compatible
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@1800000 {
+ compatible = "qcom,ipq5332-gcc";
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <&pcie_2lane_phy_pipe_clk>,
+ <&pcie_2lane_phy_pipe_clk_x1>,
+ <&usb_pcie_wrapper_pipe_clk>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
new file mode 100644
index 000000000000..8a405a0a96d0
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -0,0 +1,356 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H
+
+#define GPLL0_MAIN 0
+#define GPLL0 1
+#define GPLL2_MAIN 2
+#define GPLL2 3
+#define GPLL4_MAIN 4
+#define GPLL4 5
+#define GCC_ADSS_PWM_CLK 6
+#define GCC_ADSS_PWM_CLK_SRC 7
+#define GCC_AHB_CLK 8
+#define GCC_APSS_AXI_CLK_SRC 9
+#define GCC_BLSP1_AHB_CLK 10
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 11
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 15
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 16
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 17
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 18
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 19
+#define GCC_BLSP1_SLEEP_CLK 20
+#define GCC_BLSP1_UART1_APPS_CLK 21
+#define GCC_BLSP1_UART1_APPS_CLK_SRC 22
+#define GCC_BLSP1_UART2_APPS_CLK 23
+#define GCC_BLSP1_UART2_APPS_CLK_SRC 24
+#define GCC_BLSP1_UART3_APPS_CLK 25
+#define GCC_BLSP1_UART3_APPS_CLK_SRC 26
+#define GCC_CE_AHB_CLK 27
+#define GCC_CE_AXI_CLK 28
+#define GCC_CE_PCNOC_AHB_CLK 29
+#define GCC_CMN_12GPLL_AHB_CLK 30
+#define GCC_CMN_12GPLL_APU_CLK 31
+#define GCC_CMN_12GPLL_SYS_CLK 32
+#define GCC_GP1_CLK 33
+#define GCC_GP1_CLK_SRC 34
+#define GCC_GP2_CLK 35
+#define GCC_GP2_CLK_SRC 36
+#define GCC_LPASS_CORE_AXIM_CLK 37
+#define GCC_LPASS_SWAY_CLK 38
+#define GCC_LPASS_SWAY_CLK_SRC 39
+#define GCC_MDIO_AHB_CLK 40
+#define GCC_MDIO_SLAVE_AHB_CLK 41
+#define GCC_MEM_NOC_Q6_AXI_CLK 42
+#define GCC_MEM_NOC_TS_CLK 43
+#define GCC_NSS_TS_CLK 44
+#define GCC_NSS_TS_CLK_SRC 45
+#define GCC_NSSCC_CLK 46
+#define GCC_NSSCFG_CLK 47
+#define GCC_NSSNOC_ATB_CLK 48
+#define GCC_NSSNOC_NSSCC_CLK 49
+#define GCC_NSSNOC_QOSGEN_REF_CLK 50
+#define GCC_NSSNOC_SNOC_1_CLK 51
+#define GCC_NSSNOC_SNOC_CLK 52
+#define GCC_NSSNOC_TIMEOUT_REF_CLK 53
+#define GCC_NSSNOC_XO_DCD_CLK 54
+#define GCC_PCIE3X1_0_AHB_CLK 55
+#define GCC_PCIE3X1_0_AUX_CLK 56
+#define GCC_PCIE3X1_0_AXI_CLK_SRC 57
+#define GCC_PCIE3X1_0_AXI_M_CLK 58
+#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK 59
+#define GCC_PCIE3X1_0_AXI_S_CLK 60
+#define GCC_PCIE3X1_0_PIPE_CLK 61
+#define GCC_PCIE3X1_0_RCHG_CLK 62
+#define GCC_PCIE3X1_0_RCHG_CLK_SRC 63
+#define GCC_PCIE3X1_1_AHB_CLK 64
+#define GCC_PCIE3X1_1_AUX_CLK 65
+#define GCC_PCIE3X1_1_AXI_CLK_SRC 66
+#define GCC_PCIE3X1_1_AXI_M_CLK 67
+#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK 68
+#define GCC_PCIE3X1_1_AXI_S_CLK 69
+#define GCC_PCIE3X1_1_PIPE_CLK 70
+#define GCC_PCIE3X1_1_RCHG_CLK 71
+#define GCC_PCIE3X1_1_RCHG_CLK_SRC 72
+#define GCC_PCIE3X1_PHY_AHB_CLK 73
+#define GCC_PCIE3X2_AHB_CLK 74
+#define GCC_PCIE3X2_AUX_CLK 75
+#define GCC_PCIE3X2_AXI_M_CLK 76
+#define GCC_PCIE3X2_AXI_M_CLK_SRC 77
+#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK 78
+#define GCC_PCIE3X2_AXI_S_CLK 79
+#define GCC_PCIE3X2_AXI_S_CLK_SRC 80
+#define GCC_PCIE3X2_PHY_AHB_CLK 81
+#define GCC_PCIE3X2_PIPE_CLK 82
+#define GCC_PCIE3X2_RCHG_CLK 83
+#define GCC_PCIE3X2_RCHG_CLK_SRC 84
+#define GCC_PCIE_AUX_CLK_SRC 85
+#define GCC_PCNOC_AT_CLK 86
+#define GCC_PCNOC_BFDCD_CLK_SRC 87
+#define GCC_PCNOC_LPASS_CLK 88
+#define GCC_PRNG_AHB_CLK 89
+#define GCC_Q6_AHB_CLK 90
+#define GCC_Q6_AHB_S_CLK 91
+#define GCC_Q6_AXIM_CLK 92
+#define GCC_Q6_AXIM_CLK_SRC 93
+#define GCC_Q6_AXIS_CLK 94
+#define GCC_Q6_TSCTR_1TO2_CLK 95
+#define GCC_Q6SS_ATBM_CLK 96
+#define GCC_Q6SS_PCLKDBG_CLK 97
+#define GCC_Q6SS_TRIG_CLK 98
+#define GCC_QDSS_AT_CLK 99
+#define GCC_QDSS_AT_CLK_SRC 100
+#define GCC_QDSS_CFG_AHB_CLK 101
+#define GCC_QDSS_DAP_AHB_CLK 102
+#define GCC_QDSS_DAP_CLK 103
+#define GCC_QDSS_DAP_DIV_CLK_SRC 104
+#define GCC_QDSS_ETR_USB_CLK 105
+#define GCC_QDSS_EUD_AT_CLK 106
+#define GCC_QDSS_TSCTR_CLK_SRC 107
+#define GCC_QPIC_AHB_CLK 108
+#define GCC_QPIC_CLK 109
+#define GCC_QPIC_IO_MACRO_CLK 110
+#define GCC_QPIC_IO_MACRO_CLK_SRC 111
+#define GCC_QPIC_SLEEP_CLK 112
+#define GCC_SDCC1_AHB_CLK 113
+#define GCC_SDCC1_APPS_CLK 114
+#define GCC_SDCC1_APPS_CLK_SRC 115
+#define GCC_SLEEP_CLK_SRC 116
+#define GCC_SNOC_LPASS_CFG_CLK 117
+#define GCC_SNOC_NSSNOC_1_CLK 118
+#define GCC_SNOC_NSSNOC_CLK 119
+#define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120
+#define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121
+#define GCC_SNOC_PCIE3_1LANE_M_CLK 122
+#define GCC_SNOC_PCIE3_1LANE_S_CLK 123
+#define GCC_SNOC_PCIE3_2LANE_M_CLK 124
+#define GCC_SNOC_PCIE3_2LANE_S_CLK 125
+#define GCC_SNOC_USB_CLK 126
+#define GCC_SYS_NOC_AT_CLK 127
+#define GCC_SYS_NOC_WCSS_AHB_CLK 128
+#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC 129
+#define GCC_UNIPHY0_AHB_CLK 130
+#define GCC_UNIPHY0_SYS_CLK 131
+#define GCC_UNIPHY1_AHB_CLK 132
+#define GCC_UNIPHY1_SYS_CLK 133
+#define GCC_UNIPHY_SYS_CLK_SRC 134
+#define GCC_USB0_AUX_CLK 135
+#define GCC_USB0_AUX_CLK_SRC 136
+#define GCC_USB0_EUD_AT_CLK 137
+#define GCC_USB0_LFPS_CLK 138
+#define GCC_USB0_LFPS_CLK_SRC 139
+#define GCC_USB0_MASTER_CLK 140
+#define GCC_USB0_MASTER_CLK_SRC 141
+#define GCC_USB0_MOCK_UTMI_CLK 142
+#define GCC_USB0_MOCK_UTMI_CLK_SRC 143
+#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC 144
+#define GCC_USB0_PHY_CFG_AHB_CLK 145
+#define GCC_USB0_PIPE_CLK 146
+#define GCC_USB0_SLEEP_CLK 147
+#define GCC_WCSS_AHB_CLK_SRC 148
+#define GCC_WCSS_AXIM_CLK 149
+#define GCC_WCSS_AXIS_CLK 150
+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 151
+#define GCC_WCSS_DBG_IFC_APB_CLK 152
+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 153
+#define GCC_WCSS_DBG_IFC_ATB_CLK 154
+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155
+#define GCC_WCSS_DBG_IFC_NTS_CLK 156
+#define GCC_WCSS_ECAHB_CLK 157
+#define GCC_WCSS_MST_ASYNC_BDG_CLK 158
+#define GCC_WCSS_SLV_ASYNC_BDG_CLK 159
+#define GCC_XO_CLK 160
+#define GCC_XO_CLK_SRC 161
+#define GCC_XO_DIV4_CLK 162
+#define GCC_IM_SLEEP_CLK 163
+#define GCC_NSSNOC_PCNOC_1_CLK 164
+#define GCC_MEM_NOC_AHB_CLK 165
+#define GCC_MEM_NOC_APSS_AXI_CLK 166
+#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC 167
+#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK 168
+#define GCC_PCIE3X2_PIPE_CLK_SRC 169
+#define GCC_PCIE3X1_0_PIPE_CLK_SRC 170
+#define GCC_PCIE3X1_1_PIPE_CLK_SRC 171
+#define GCC_USB0_PIPE_CLK_SRC 172
+
+#define GCC_ADSS_BCR 0
+#define GCC_ADSS_PWM_CLK_ARES 1
+#define GCC_AHB_CLK_ARES 2
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 3
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES 4
+#define GCC_APSS_AHB_CLK_ARES 5
+#define GCC_APSS_AXI_CLK_ARES 6
+#define GCC_BLSP1_AHB_CLK_ARES 7
+#define GCC_BLSP1_BCR 8
+#define GCC_BLSP1_QUP1_BCR 9
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES 10
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES 11
+#define GCC_BLSP1_QUP2_BCR 12
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES 13
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES 14
+#define GCC_BLSP1_QUP3_BCR 15
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES 16
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES 17
+#define GCC_BLSP1_SLEEP_CLK_ARES 18
+#define GCC_BLSP1_UART1_APPS_CLK_ARES 19
+#define GCC_BLSP1_UART1_BCR 20
+#define GCC_BLSP1_UART2_APPS_CLK_ARES 21
+#define GCC_BLSP1_UART2_BCR 22
+#define GCC_BLSP1_UART3_APPS_CLK_ARES 23
+#define GCC_BLSP1_UART3_BCR 24
+#define GCC_CE_BCR 25
+#define GCC_CMN_BLK_BCR 26
+#define GCC_CMN_LDO0_BCR 27
+#define GCC_CMN_LDO1_BCR 28
+#define GCC_DCC_BCR 29
+#define GCC_GP1_CLK_ARES 30
+#define GCC_GP2_CLK_ARES 31
+#define GCC_LPASS_BCR 32
+#define GCC_LPASS_CORE_AXIM_CLK_ARES 33
+#define GCC_LPASS_SWAY_CLK_ARES 34
+#define GCC_MDIOM_BCR 35
+#define GCC_MDIOS_BCR 36
+#define GCC_NSS_BCR 37
+#define GCC_NSS_TS_CLK_ARES 38
+#define GCC_NSSCC_CLK_ARES 39
+#define GCC_NSSCFG_CLK_ARES 40
+#define GCC_NSSNOC_ATB_CLK_ARES 41
+#define GCC_NSSNOC_NSSCC_CLK_ARES 42
+#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES 43
+#define GCC_NSSNOC_SNOC_1_CLK_ARES 44
+#define GCC_NSSNOC_SNOC_CLK_ARES 45
+#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES 46
+#define GCC_NSSNOC_XO_DCD_CLK_ARES 47
+#define GCC_PCIE3X1_0_AHB_CLK_ARES 48
+#define GCC_PCIE3X1_0_AUX_CLK_ARES 49
+#define GCC_PCIE3X1_0_AXI_M_CLK_ARES 50
+#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES 51
+#define GCC_PCIE3X1_0_AXI_S_CLK_ARES 52
+#define GCC_PCIE3X1_0_BCR 53
+#define GCC_PCIE3X1_0_LINK_DOWN_BCR 54
+#define GCC_PCIE3X1_0_PHY_BCR 55
+#define GCC_PCIE3X1_0_PHY_PHY_BCR 56
+#define GCC_PCIE3X1_1_AHB_CLK_ARES 57
+#define GCC_PCIE3X1_1_AUX_CLK_ARES 58
+#define GCC_PCIE3X1_1_AXI_M_CLK_ARES 59
+#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES 60
+#define GCC_PCIE3X1_1_AXI_S_CLK_ARES 61
+#define GCC_PCIE3X1_1_BCR 62
+#define GCC_PCIE3X1_1_LINK_DOWN_BCR 63
+#define GCC_PCIE3X1_1_PHY_BCR 64
+#define GCC_PCIE3X1_1_PHY_PHY_BCR 65
+#define GCC_PCIE3X1_PHY_AHB_CLK_ARES 66
+#define GCC_PCIE3X2_AHB_CLK_ARES 67
+#define GCC_PCIE3X2_AUX_CLK_ARES 68
+#define GCC_PCIE3X2_AXI_M_CLK_ARES 69
+#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES 70
+#define GCC_PCIE3X2_AXI_S_CLK_ARES 71
+#define GCC_PCIE3X2_BCR 72
+#define GCC_PCIE3X2_LINK_DOWN_BCR 73
+#define GCC_PCIE3X2_PHY_AHB_CLK_ARES 74
+#define GCC_PCIE3X2_PHY_BCR 75
+#define GCC_PCIE3X2PHY_PHY_BCR 76
+#define GCC_PCNOC_BCR 77
+#define GCC_PCNOC_LPASS_CLK_ARES 78
+#define GCC_PRNG_AHB_CLK_ARES 79
+#define GCC_PRNG_BCR 80
+#define GCC_Q6_AHB_CLK_ARES 81
+#define GCC_Q6_AHB_S_CLK_ARES 82
+#define GCC_Q6_AXIM_CLK_ARES 83
+#define GCC_Q6_AXIS_CLK_ARES 84
+#define GCC_Q6_TSCTR_1TO2_CLK_ARES 85
+#define GCC_Q6SS_ATBM_CLK_ARES 86
+#define GCC_Q6SS_PCLKDBG_CLK_ARES 87
+#define GCC_Q6SS_TRIG_CLK_ARES 88
+#define GCC_QDSS_APB2JTAG_CLK_ARES 89
+#define GCC_QDSS_AT_CLK_ARES 90
+#define GCC_QDSS_BCR 91
+#define GCC_QDSS_CFG_AHB_CLK_ARES 92
+#define GCC_QDSS_DAP_AHB_CLK_ARES 93
+#define GCC_QDSS_DAP_CLK_ARES 94
+#define GCC_QDSS_ETR_USB_CLK_ARES 95
+#define GCC_QDSS_EUD_AT_CLK_ARES 96
+#define GCC_QDSS_STM_CLK_ARES 97
+#define GCC_QDSS_TRACECLKIN_CLK_ARES 98
+#define GCC_QDSS_TS_CLK_ARES 99
+#define GCC_QDSS_TSCTR_DIV16_CLK_ARES 100
+#define GCC_QDSS_TSCTR_DIV2_CLK_ARES 101
+#define GCC_QDSS_TSCTR_DIV3_CLK_ARES 102
+#define GCC_QDSS_TSCTR_DIV4_CLK_ARES 103
+#define GCC_QDSS_TSCTR_DIV8_CLK_ARES 104
+#define GCC_QPIC_AHB_CLK_ARES 105
+#define GCC_QPIC_CLK_ARES 106
+#define GCC_QPIC_BCR 107
+#define GCC_QPIC_IO_MACRO_CLK_ARES 108
+#define GCC_QPIC_SLEEP_CLK_ARES 109
+#define GCC_QUSB2_0_PHY_BCR 110
+#define GCC_SDCC1_AHB_CLK_ARES 111
+#define GCC_SDCC1_APPS_CLK_ARES 112
+#define GCC_SDCC_BCR 113
+#define GCC_SNOC_BCR 114
+#define GCC_SNOC_LPASS_CFG_CLK_ARES 115
+#define GCC_SNOC_NSSNOC_1_CLK_ARES 116
+#define GCC_SNOC_NSSNOC_CLK_ARES 117
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES 118
+#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES 119
+#define GCC_UNIPHY0_AHB_CLK_ARES 120
+#define GCC_UNIPHY0_BCR 121
+#define GCC_UNIPHY0_SYS_CLK_ARES 122
+#define GCC_UNIPHY1_AHB_CLK_ARES 123
+#define GCC_UNIPHY1_BCR 124
+#define GCC_UNIPHY1_SYS_CLK_ARES 125
+#define GCC_USB0_AUX_CLK_ARES 126
+#define GCC_USB0_EUD_AT_CLK_ARES 127
+#define GCC_USB0_LFPS_CLK_ARES 128
+#define GCC_USB0_MASTER_CLK_ARES 129
+#define GCC_USB0_MOCK_UTMI_CLK_ARES 130
+#define GCC_USB0_PHY_BCR 131
+#define GCC_USB0_PHY_CFG_AHB_CLK_ARES 132
+#define GCC_USB0_SLEEP_CLK_ARES 133
+#define GCC_USB3PHY_0_PHY_BCR 134
+#define GCC_USB_BCR 135
+#define GCC_WCSS_AXIM_CLK_ARES 136
+#define GCC_WCSS_AXIS_CLK_ARES 137
+#define GCC_WCSS_BCR 138
+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES 139
+#define GCC_WCSS_DBG_IFC_APB_CLK_ARES 140
+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES 141
+#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES 142
+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES 143
+#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES 144
+#define GCC_WCSS_ECAHB_CLK_ARES 145
+#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES 146
+#define GCC_WCSS_Q6_BCR 147
+#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES 148
+#define GCC_XO_CLK_ARES 149
+#define GCC_XO_DIV4_CLK_ARES 150
+#define GCC_Q6SS_DBG_ARES 151
+#define GCC_WCSS_DBG_BDG_ARES 152
+#define GCC_WCSS_DBG_ARES 153
+#define GCC_WCSS_AXI_S_ARES 154
+#define GCC_WCSS_AXI_M_ARES 155
+#define GCC_WCSSAON_ARES 156
+#define GCC_PCIE3X2_PIPE_ARES 157
+#define GCC_PCIE3X2_CORE_STICKY_ARES 158
+#define GCC_PCIE3X2_AXI_S_STICKY_ARES 159
+#define GCC_PCIE3X2_AXI_M_STICKY_ARES 160
+#define GCC_PCIE3X1_0_PIPE_ARES 161
+#define GCC_PCIE3X1_0_CORE_STICKY_ARES 162
+#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES 163
+#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES 164
+#define GCC_PCIE3X1_1_PIPE_ARES 165
+#define GCC_PCIE3X1_1_CORE_STICKY_ARES 166
+#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES 167
+#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES 168
+#define GCC_IM_SLEEP_CLK_ARES 169
+#define GCC_NSSNOC_PCNOC_1_CLK_ARES 170
+#define GCC_UNIPHY0_XPCS_ARES 171
+#define GCC_UNIPHY1_XPCS_ARES 172
+#endif
--
2.17.1
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^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
2023-02-06 7:12 ` Kathiravan T
` (4 preceding siblings ...)
(?)
@ 2023-02-06 7:12 ` Kathiravan T
2023-02-06 9:52 ` Dmitry Baryshkov
` (2 more replies)
-1 siblings, 3 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Add support for the global clock controller found on IPQ5332 SoC.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- As I mentined the bindings, changes need to be done in V2 got
missed out and same has been done in V3, to call out
specifically dropped the CLK_IS_CRITICAL and dropped the
gcc_apss_ahb_clk, its source clock and gcc_apss_axi_clk
- Used gcc_parent_data_xo wherever applicable and dropped the
duplicate entries
- dropped the unused parent_map_10 and parent_data_10
- Used qcom_cc_probe instead of qcom_cc_really_probe
Changes in V2:
- Added the 'dependes on' for Kconfig symbol
- Dropped the CLK_IS_CRITICAL flag throughout the file
- Dropped the gcc_apss_ahb_clk and gcc_apss_axi_clk as these are
managed by bootloaders
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-ipq5332.c | 3850 ++++++++++++++++++++++++++++++++
3 files changed, 3859 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-ipq5332.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5ab4b7dfe3c2..10da46fa702e 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -141,6 +141,14 @@ config IPQ_GCC_4019
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, SD/eMMC, etc.
+config IPQ_GCC_5332
+ tristate "IPQ5332 Global Clock Controller"
+ depends on ARM64 || COMPILE_TEST
+ help
+ Support for the global clock controller on ipq5332 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2c, USB, SD/eMMC, etc.
+
config IPQ_GCC_6018
tristate "IPQ6018 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 3194465dd02c..c238abee3c8e 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
+obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
new file mode 100644
index 000000000000..c8a5fa1bafca
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -0,0 +1,3850 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "reset.h"
+
+enum {
+ DT_SLEEP_CLK,
+ DT_XO,
+ DT_PCIE_2LANE_PHY_PIPE_CLK,
+ DT_PCIE_2LANE_PHY_PIPE_X1_CLK,
+ DT_USB_PCIE_WRAPPER_PIPE_CLK,
+};
+
+enum {
+ P_PCIE3X2_PIPE,
+ P_PCIE3X1_0_PIPE,
+ P_PCIE3X1_1_PIPE,
+ P_USB3PHY_0_PIPE,
+ P_CORE_BI_PLL_TEST_SE,
+ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
+ P_GPLL0_OUT_AUX,
+ P_GPLL0_OUT_MAIN,
+ P_GPLL2_OUT_AUX,
+ P_GPLL2_OUT_MAIN,
+ P_GPLL4_OUT_AUX,
+ P_GPLL4_OUT_MAIN,
+ P_SLEEP_CLK,
+ P_XO,
+};
+
+static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
+
+static struct clk_alpha_pll gpll0_main = {
+ .offset = 0x20000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
+ .clkr = {
+ .enable_reg = 0xb000,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpll0_main",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_div2",
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll0_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x20000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll0_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll gpll2_main = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
+ .clkr = {
+ .enable_reg = 0xb000,
+ .enable_mask = BIT(1),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpll2",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll2 = {
+ .offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll2_main",
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll2_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll gpll4_main = {
+ .offset = 0x22000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
+ .clkr = {
+ .enable_reg = 0xb000,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gpll4_main",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_stromer_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x22000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll4",
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll4_main.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct parent_map gcc_parent_map_xo[] = {
+ { P_XO, 0 },
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_0[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data gcc_parent_data_1[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL4_OUT_MAIN, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_2[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+ { P_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_3[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+ { P_XO, 0 },
+ { P_GPLL4_OUT_MAIN, 1 },
+ { P_GPLL0_OUT_AUX, 2 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_4[] = {
+ { .index = DT_XO },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL2_OUT_AUX, 2 },
+ { P_GPLL4_OUT_AUX, 3 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+ { P_GPLL0_OUT_AUX, 5 },
+};
+
+static const struct clk_parent_data gcc_parent_data_5[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+ { .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_6[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL0_OUT_AUX, 2 },
+ { P_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_6[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_7[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL2_OUT_AUX, 2 },
+ { P_GPLL4_OUT_AUX, 3 },
+ { P_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_7[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_8[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL2_OUT_AUX, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_8[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+};
+
+static const struct parent_map gcc_parent_map_9[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL2_OUT_MAIN, 2 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_9[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_10[] = {
+ { P_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_10[] = {
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_11[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_MAIN, 1 },
+ { P_GPLL4_OUT_MAIN, 2 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
+};
+
+static const struct clk_parent_data gcc_parent_data_11[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_12[] = {
+ { P_XO, 0 },
+ { P_GPLL0_OUT_AUX, 2 },
+ { P_SLEEP_CLK, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_12[] = {
+ { .index = DT_XO },
+ { .hw = &gpll0.clkr.hw },
+ { .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_parent_map_13[] = {
+ { P_XO, 0 },
+ { P_GPLL4_OUT_AUX, 1 },
+ { P_GPLL0_OUT_MAIN, 3 },
+ { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
+};
+
+static const struct clk_parent_data gcc_parent_data_13[] = {
+ { .index = DT_XO },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll0_div2.hw },
+};
+
+static const struct parent_map gcc_parent_map_14[] = {
+ { P_PCIE3X2_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_14[] = {
+ { .index = DT_PCIE_2LANE_PHY_PIPE_CLK },
+ { .index = DT_XO },
+};
+
+static const struct parent_map gcc_parent_map_15[] = {
+ { P_PCIE3X1_0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_15[] = {
+ { .index = DT_USB_PCIE_WRAPPER_PIPE_CLK },
+ { .index = DT_XO },
+};
+
+static const struct parent_map gcc_parent_map_16[] = {
+ { P_PCIE3X1_1_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_parent_data_16[] = {
+ { .index = DT_PCIE_2LANE_PHY_PIPE_X1_CLK },
+ { .index = DT_XO },
+};
+
+static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_adss_pwm_clk_src = {
+ .cmd_rcgr = 0x1c004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_adss_pwm_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
+ F(480000000, P_GPLL4_OUT_MAIN, 2.5, 0, 0),
+ F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_apss_axi_clk_src = {
+ .cmd_rcgr = 0x24004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_5,
+ .freq_tbl = ftbl_gcc_apss_axi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_apss_axi_clk_src",
+ .parent_data = gcc_parent_data_5,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_5),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
+ F(960000, P_XO, 1, 1, 25),
+ F(4800000, P_XO, 5, 0, 0),
+ F(9600000, P_XO, 2.5, 0, 0),
+ F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x3004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x4004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
+ F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625),
+ F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625),
+ F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625),
+ F(24000000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
+ F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
+ F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
+ F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
+ F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
+ F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
+ F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
+ F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
+ F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
+ F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x202c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x302c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
+ .cmd_rcgr = 0x402c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_uart3_apps_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_gp1_clk_src = {
+ .cmd_rcgr = 0x8004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp1_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_gp2_clk_src = {
+ .cmd_rcgr = 0x9004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_3,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp2_clk_src",
+ .parent_data = gcc_parent_data_3,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_3),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_lpass_sway_clk_src = {
+ .cmd_rcgr = 0x27004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_lpass_sway_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_nss_ts_clk_src = {
+ .cmd_rcgr = 0x17088,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo,
+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_nss_ts_clk_src",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie3x1_0_axi_clk_src[] = {
+ F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie3x1_0_axi_clk_src = {
+ .cmd_rcgr = 0x29018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_0_axi_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie3x1_0_rchg_clk_src = {
+ .cmd_rcgr = 0x2907c,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_0_rchg_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_0_rchg_clk = {
+ .halt_reg = 0x2907c,
+ .clkr = {
+ .enable_reg = 0x2907c,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie3x1_0_rchg_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_pcie3x1_0_rchg_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_rcg2 gcc_pcie3x1_1_axi_clk_src = {
+ .cmd_rcgr = 0x2a004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_1_axi_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie3x1_1_rchg_clk_src = {
+ .cmd_rcgr = 0x2a078,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_1_rchg_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_1_rchg_clk = {
+ .halt_reg = 0x2a078,
+ .clkr = {
+ .enable_reg = 0x2a078,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie3x1_1_rchg_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_pcie3x1_1_rchg_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie3x2_axi_m_clk_src[] = {
+ F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie3x2_axi_m_clk_src = {
+ .cmd_rcgr = 0x28018,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_pcie3x2_axi_m_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_axi_m_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie3x2_axi_s_clk_src = {
+ .cmd_rcgr = 0x28084,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_2,
+ .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_axi_s_clk_src",
+ .parent_data = gcc_parent_data_2,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_2),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_pcie3x2_rchg_clk_src = {
+ .cmd_rcgr = 0x28078,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_rchg_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_pcie3x2_rchg_clk = {
+ .halt_reg = 0x28078,
+ .clkr = {
+ .enable_reg = 0x28078,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie3x2_rchg_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_pcie3x2_rchg_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
+ F(2000000, P_XO, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcie_aux_clk_src = {
+ .cmd_rcgr = 0x28004,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_6,
+ .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie_aux_clk_src",
+ .parent_data = gcc_parent_data_6,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_6),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux pcie3x2_pipe_clk_src = {
+ .reg = 0x28064,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_parent_map_14,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie3x2_phy_pipe_clk_src",
+ .parent_data = gcc_parent_data_14,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_14),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_regmap_mux pcie3x1_0_pipe_clk_src = {
+ .reg = 0x29064,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_parent_map_15,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie3x1_0_phy_pipe_clk_src",
+ .parent_data = gcc_parent_data_15,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_15),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_regmap_mux pcie3x1_1_pipe_clk_src = {
+ .reg = 0x2A064,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_parent_map_16,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie3x1_1_phy_pipe_clk_src",
+ .parent_data = gcc_parent_data_16,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_16),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x31004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcnoc_bfdcd_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_q6_axim_clk_src = {
+ .cmd_rcgr = 0x25004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_7,
+ .freq_tbl = ftbl_gcc_apss_axi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_q6_axim_clk_src",
+ .parent_data = gcc_parent_data_7,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_7),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
+ F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qdss_at_clk_src = {
+ .cmd_rcgr = 0x2d004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_4,
+ .freq_tbl = ftbl_gcc_qdss_at_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_qdss_at_clk_src",
+ .parent_data = gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
+ F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
+ .cmd_rcgr = 0x2d01c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_4,
+ .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_qdss_tsctr_clk_src",
+ .parent_data = gcc_parent_data_4,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_4),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qdss_tsctr_div2_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_qdss_tsctr_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
+ .mult = 1,
+ .div = 3,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qdss_tsctr_div3_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_qdss_tsctr_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qdss_tsctr_div4_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_qdss_tsctr_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
+ .mult = 1,
+ .div = 8,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qdss_tsctr_div8_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_qdss_tsctr_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {
+ .mult = 1,
+ .div = 16,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qdss_tsctr_div16_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_qdss_tsctr_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
+ .cmd_rcgr = 0x32004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_8,
+ .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_qpic_io_macro_clk_src",
+ .parent_data = gcc_parent_data_8,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_8),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
+ F(143713, P_XO, 1, 1, 167),
+ F(400000, P_XO, 1, 1, 60),
+ F(24000000, P_XO, 1, 0, 0),
+ F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
+ F(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
+ F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
+ F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x33004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_9,
+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk_src",
+ .parent_data = gcc_parent_data_9,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_9),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
+ F(32000, P_SLEEP_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_sleep_clk_src = {
+ .cmd_rcgr = 0x3400c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_10,
+ .freq_tbl = ftbl_gcc_sleep_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_sleep_clk_src",
+ .parent_data = gcc_parent_data_10,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_10),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
+ F(24000000, P_XO, 1, 0, 0),
+ F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
+ F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+ F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x2e004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_11,
+ .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_system_noc_bfdcd_clk_src",
+ .parent_data = gcc_parent_data_11,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_11),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_system_noc_bfdcd_div2_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
+ .cmd_rcgr = 0x16004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo,
+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_uniphy_sys_clk_src",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_usb0_aux_clk_src = {
+ .cmd_rcgr = 0x2c018,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_12,
+ .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_aux_clk_src",
+ .parent_data = gcc_parent_data_12,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_12),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb0_lfps_clk_src[] = {
+ F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb0_lfps_clk_src = {
+ .cmd_rcgr = 0x2c07c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_usb0_lfps_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_lfps_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_usb0_master_clk_src = {
+ .cmd_rcgr = 0x2c004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_0,
+ .freq_tbl = ftbl_gcc_gp1_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_master_clk_src",
+ .parent_data = gcc_parent_data_0,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_0),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
+ F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
+ { }
+};
+
+static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x2c02c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_13,
+ .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_mock_utmi_clk_src",
+ .parent_data = gcc_parent_data_13,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_13),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux usb0_pipe_clk_src = {
+ .reg = 0x2C074,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_parent_map_15,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "usb0phy_0_cc_pipe_clk_src",
+ .parent_data = gcc_parent_data_15,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_15),
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 gcc_wcss_ahb_clk_src = {
+ .cmd_rcgr = 0x25030,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_1,
+ .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_ahb_clk_src",
+ .parent_data = gcc_parent_data_1,
+ .num_parents = ARRAY_SIZE(gcc_parent_data_1),
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gcc_xo_clk_src = {
+ .cmd_rcgr = 0x34004,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo,
+ .freq_tbl = ftbl_gcc_nss_ts_clk_src,
+ .clkr.hw.init = &(const struct clk_init_data){
+ .name = "gcc_xo_clk_src",
+ .parent_data = &gcc_parent_data_xo,
+ .num_parents = 1,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor gcc_xo_div4_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_xo_div4_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_xo_clk_src.clkr.hw },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap_div gcc_qdss_dap_div_clk_src = {
+ .reg = 0x2d028,
+ .shift = 0,
+ .width = 4,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_qdss_dap_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_tsctr_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
+ .reg = 0x2c040,
+ .shift = 0,
+ .width = 2,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_usb0_mock_utmi_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb0_mock_utmi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch gcc_adss_pwm_clk = {
+ .halt_reg = 0x1c00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1c00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_adss_pwm_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_adss_pwm_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ahb_clk = {
+ .halt_reg = 0x34024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x34024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x1008,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(4),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x2024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x2020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x3024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x3020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x4024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x4020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_sleep_clk = {
+ .halt_reg = 0x1010,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(5),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_sleep_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_sleep_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x2040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_blsp1_uart1_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x3040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_blsp1_uart2_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart3_apps_clk = {
+ .halt_reg = 0x4054,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_blsp1_uart3_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_blsp1_uart3_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ce_ahb_clk = {
+ .halt_reg = 0x25074,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25074,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ce_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ce_axi_clk = {
+ .halt_reg = 0x25068,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ce_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ce_pcnoc_ahb_clk = {
+ .halt_reg = 0x25070,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25070,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_ce_pcnoc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
+ .halt_reg = 0x3a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_cmn_12gpll_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_12gpll_apu_clk = {
+ .halt_reg = 0x3a00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3a00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_cmn_12gpll_apu_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_12gpll_sys_clk = {
+ .halt_reg = 0x3a008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_cmn_12gpll_sys_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_uniphy_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x8018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gp1_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x9018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_gp2_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_core_axim_clk = {
+ .halt_reg = 0x27018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x27018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_lpass_core_axim_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_sway_clk = {
+ .halt_reg = 0x27014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x27014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_lpass_sway_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio_ahb_clk = {
+ .halt_reg = 0x12004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x12004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_mdio_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio_slave_ahb_clk = {
+ .halt_reg = 0x1200c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_mdio_slave_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mem_noc_q6_axi_clk = {
+ .halt_reg = 0x19010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_mem_noc_q6_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_q6_axim_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mem_noc_ts_clk = {
+ .halt_reg = 0x19028,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x19028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_mem_noc_ts_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_tsctr_div8_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ts_clk = {
+ .halt_reg = 0x17018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x17018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nss_ts_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_nss_ts_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nsscc_clk = {
+ .halt_reg = 0x17034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nsscc_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nsscfg_clk = {
+ .halt_reg = 0x1702c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1702c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nsscfg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_atb_clk = {
+ .halt_reg = 0x17014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nssnoc_atb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_nsscc_clk = {
+ .halt_reg = 0x17030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nssnoc_nsscc_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
+ .halt_reg = 0x1701c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1701c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nssnoc_qosgen_ref_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_xo_div4_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_snoc_1_clk = {
+ .halt_reg = 0x1707c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1707c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nssnoc_snoc_1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_snoc_clk = {
+ .halt_reg = 0x17028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nssnoc_snoc_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
+ .halt_reg = 0x17020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nssnoc_timeout_ref_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_xo_div4_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
+ .halt_reg = 0x17074,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17074,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nssnoc_xo_dcd_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_0_ahb_clk = {
+ .halt_reg = 0x29030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_0_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_0_aux_clk = {
+ .halt_reg = 0x29070,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29070,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_0_aux_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_0_axi_m_clk = {
+ .halt_reg = 0x29038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_0_axi_m_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_0_axi_s_bridge_clk = {
+ .halt_reg = 0x29048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_0_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_0_axi_s_clk = {
+ .halt_reg = 0x29040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_0_axi_s_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
+ .halt_reg = 0x29068,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x29068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_0_pipe_clk",
+ .parent_names = (const char *[]){
+ "pcie3x1_0_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_1_ahb_clk = {
+ .halt_reg = 0x2a00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_1_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_1_aux_clk = {
+ .halt_reg = 0x2a070,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a070,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_1_aux_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_1_axi_m_clk = {
+ .halt_reg = 0x2a014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_1_axi_m_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_1_axi_s_bridge_clk = {
+ .halt_reg = 0x2a024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_1_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_1_axi_s_clk = {
+ .halt_reg = 0x2a01c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a01c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_1_axi_s_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_1_pipe_clk = {
+ .halt_reg = 0x2a068,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2a068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_1_pipe_clk",
+ .parent_names = (const char *[]){
+ "pcie3x1_1_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x1_phy_ahb_clk = {
+ .halt_reg = 0x29078,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29078,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x1_phy_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x2_ahb_clk = {
+ .halt_reg = 0x28030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x2_aux_clk = {
+ .halt_reg = 0x28070,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28070,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_aux_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x2_axi_m_clk = {
+ .halt_reg = 0x28038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_axi_m_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x2_axi_m_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x2_axi_s_bridge_clk = {
+ .halt_reg = 0x28048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x2_axi_s_clk = {
+ .halt_reg = 0x28040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_axi_s_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x2_phy_ahb_clk = {
+ .halt_reg = 0x28080,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28080,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_phy_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie3x2_pipe_clk = {
+ .halt_reg = 0x28068,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x28068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcie3x2_pipe_clk",
+ .parent_names = (const char *[]){
+ "pcie3x2_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcnoc_at_clk = {
+ .halt_reg = 0x31024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x31024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcnoc_at_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcnoc_lpass_clk = {
+ .halt_reg = 0x31020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x31020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_pcnoc_lpass_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x13024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(10),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_ahb_clk = {
+ .halt_reg = 0x25014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x25014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_q6_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_ahb_s_clk = {
+ .halt_reg = 0x25018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x25018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_q6_ahb_s_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_axim_clk = {
+ .halt_reg = 0x2500c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_q6_axim_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_q6_axim_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_axis_clk = {
+ .halt_reg = 0x25010,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x25010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_q6_axis_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6_tsctr_1to2_clk = {
+ .halt_reg = 0x25020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x25020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_q6_tsctr_1to2_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_tsctr_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6ss_atbm_clk = {
+ .halt_reg = 0x2501c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2501c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_q6ss_atbm_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6ss_pclkdbg_clk = {
+ .halt_reg = 0x25024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x25024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_q6ss_pclkdbg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_dap_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_q6ss_trig_clk = {
+ .halt_reg = 0x250a0,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x250a0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_q6ss_trig_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_dap_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_at_clk = {
+ .halt_reg = 0x2d038,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2d038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qdss_at_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_cfg_ahb_clk = {
+ .halt_reg = 0x2d06c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2d06c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qdss_cfg_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_dap_ahb_clk = {
+ .halt_reg = 0x2d068,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2d068,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qdss_dap_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_dap_clk = {
+ .halt_reg = 0x2d05c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(2),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qdss_dap_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_dap_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qdss_etr_usb_clk = {
+ .halt_reg = 0x2d064,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2d064,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qdss_etr_usb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
+ .mult = 1,
+ .div = 6,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_eud_at_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_qdss_at_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_branch gcc_qdss_eud_at_clk = {
+ .halt_reg = 0x2d070,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2d070,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qdss_eud_at_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_eud_at_div_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_ahb_clk = {
+ .halt_reg = 0x32010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x32010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qpic_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_clk = {
+ .halt_reg = 0x32014,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x32014,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qpic_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_io_macro_clk = {
+ .halt_reg = 0x3200c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qpic_io_macro_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qpic_io_macro_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qpic_sleep_clk = {
+ .halt_reg = 0x3201c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3201c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_qpic_sleep_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_sleep_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x33034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x33034,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x3302c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3302c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_sdcc1_apps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_lpass_cfg_clk = {
+ .halt_reg = 0x2e028,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e028,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_lpass_cfg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_lpass_sway_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_nssnoc_1_clk = {
+ .halt_reg = 0x17090,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17090,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_nssnoc_1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_nssnoc_clk = {
+ .halt_reg = 0x17084,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17084,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_nssnoc_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = {
+ .halt_reg = 0x2e050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_pcie3_1lane_1_m_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie3_1lane_1_s_clk = {
+ .halt_reg = 0x2e0ac,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e0ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_pcie3_1lane_1_s_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie3_1lane_m_clk = {
+ .halt_reg = 0x2e080,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e080,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_pcie3_1lane_m_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie3_1lane_s_clk = {
+ .halt_reg = 0x2e04c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e04c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_pcie3_1lane_s_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie3_2lane_m_clk = {
+ .halt_reg = 0x2e07c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e07c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_pcie3_2lane_m_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x2_axi_m_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
+ .halt_reg = 0x2e048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_pcie3_2lane_s_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_snoc_usb_clk = {
+ .halt_reg = 0x2e058,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2e058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_snoc_usb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb0_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_at_clk = {
+ .halt_reg = 0x2e038,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2e038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_sys_noc_at_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
+ .halt_reg = 0x2e030,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e030,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_sys_noc_wcss_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_ahb_clk = {
+ .halt_reg = 0x16010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16010,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_uniphy0_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_sys_clk = {
+ .halt_reg = 0x1600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_uniphy0_sys_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_uniphy_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_ahb_clk = {
+ .halt_reg = 0x1601c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1601c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_uniphy1_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_sys_clk = {
+ .halt_reg = 0x16018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_uniphy1_sys_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_uniphy_sys_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_aux_clk = {
+ .halt_reg = 0x2c050,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2c050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_aux_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb0_aux_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_eud_at_clk = {
+ .halt_reg = 0x30004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x30004,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_eud_at_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_eud_at_div_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_lfps_clk = {
+ .halt_reg = 0x2c090,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2c090,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_lfps_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb0_lfps_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_master_clk = {
+ .halt_reg = 0x2c048,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2c048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_master_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb0_master_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_mock_utmi_clk = {
+ .halt_reg = 0x2c054,
+ .clkr = {
+ .enable_reg = 0x2c054,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_mock_utmi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
+ .halt_reg = 0x2c05c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2c05c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_phy_cfg_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x2c078,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2c078,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+ .parent_names = (const char *[]){
+ "usb0_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x2c058,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x2c058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_sleep_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_axim_clk = {
+ .halt_reg = 0x2505c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2505c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_axim_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_axis_clk = {
+ .halt_reg = 0x25060,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25060,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_axis_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
+ .halt_reg = 0x25048,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25048,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_dap_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
+ .halt_reg = 0x25038,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25038,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_dbg_ifc_apb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_dap_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
+ .halt_reg = 0x2504c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2504c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
+ .halt_reg = 0x2503c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2503c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_dbg_ifc_atb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_at_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
+ .halt_reg = 0x25050,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25050,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_tsctr_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
+ .halt_reg = 0x25040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25040,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_dbg_ifc_nts_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_qdss_tsctr_div2_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_ecahb_clk = {
+ .halt_reg = 0x25058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x25058,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_ecahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_wcss_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_mst_async_bdg_clk = {
+ .halt_reg = 0x2e0b0,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e0b0,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_mst_async_bdg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_wcss_slv_async_bdg_clk = {
+ .halt_reg = 0x2e0b4,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2e0b4,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_wcss_slv_async_bdg_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_system_noc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_xo_clk = {
+ .halt_reg = 0x34018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x34018,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_xo_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_xo_div4_clk = {
+ .halt_reg = 0x3401c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3401c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_xo_div4_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_xo_div4_clk_src.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_im_sleep_clk = {
+ .halt_reg = 0x34020,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x34020,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_im_sleep_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_sleep_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
+ .halt_reg = 0x17080,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x17080,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_nssnoc_pcnoc_1_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mem_noc_ahb_clk = {
+ .halt_reg = 0x1900c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1900c,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_mem_noc_ahb_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mem_noc_apss_axi_clk = {
+ .halt_reg = 0x1901c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0xb004,
+ .enable_mask = BIT(6),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_mem_noc_apss_axi_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_apss_axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
+ .reg = 0x2e010,
+ .shift = 0,
+ .width = 2,
+ .clkr.hw.init = &(const struct clk_init_data) {
+ .name = "gcc_snoc_qosgen_extref_div_clk_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_xo_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_regmap_div_ro_ops,
+ },
+};
+
+static struct clk_branch gcc_mem_noc_qosgen_extref_clk = {
+ .halt_reg = 0x19024,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19024,
+ .enable_mask = BIT(0),
+ .hw.init = &(const struct clk_init_data){
+ .name = "gcc_mem_noc_qosgen_extref_clk",
+ .parent_hws = (const struct clk_hw*[]){
+ &gcc_snoc_qosgen_extref_div_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_regmap *gcc_ipq5332_clocks[] = {
+ [GPLL0_MAIN] = &gpll0_main.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL2_MAIN] = &gpll2_main.clkr,
+ [GPLL2] = &gpll2.clkr,
+ [GPLL4_MAIN] = &gpll4_main.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
+ [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
+ [GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
+ [GCC_APSS_AXI_CLK_SRC] = &gcc_apss_axi_clk_src.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
+ [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
+ [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
+ [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
+ [GCC_CE_AHB_CLK] = &gcc_ce_ahb_clk.clkr,
+ [GCC_CE_AXI_CLK] = &gcc_ce_axi_clk.clkr,
+ [GCC_CE_PCNOC_AHB_CLK] = &gcc_ce_pcnoc_ahb_clk.clkr,
+ [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
+ [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
+ [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
+ [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
+ [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
+ [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
+ [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
+ [GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
+ [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
+ [GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
+ [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
+ [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
+ [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
+ [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
+ [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
+ [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
+ [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
+ [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
+ [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
+ [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
+ [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
+ [GCC_PCIE3X1_0_AHB_CLK] = &gcc_pcie3x1_0_ahb_clk.clkr,
+ [GCC_PCIE3X1_0_AUX_CLK] = &gcc_pcie3x1_0_aux_clk.clkr,
+ [GCC_PCIE3X1_0_AXI_CLK_SRC] = &gcc_pcie3x1_0_axi_clk_src.clkr,
+ [GCC_PCIE3X1_0_AXI_M_CLK] = &gcc_pcie3x1_0_axi_m_clk.clkr,
+ [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_0_axi_s_bridge_clk.clkr,
+ [GCC_PCIE3X1_0_AXI_S_CLK] = &gcc_pcie3x1_0_axi_s_clk.clkr,
+ [GCC_PCIE3X1_0_PIPE_CLK] = &gcc_pcie3x1_0_pipe_clk.clkr,
+ [GCC_PCIE3X1_0_RCHG_CLK] = &gcc_pcie3x1_0_rchg_clk.clkr,
+ [GCC_PCIE3X1_0_RCHG_CLK_SRC] = &gcc_pcie3x1_0_rchg_clk_src.clkr,
+ [GCC_PCIE3X1_1_AHB_CLK] = &gcc_pcie3x1_1_ahb_clk.clkr,
+ [GCC_PCIE3X1_1_AUX_CLK] = &gcc_pcie3x1_1_aux_clk.clkr,
+ [GCC_PCIE3X1_1_AXI_CLK_SRC] = &gcc_pcie3x1_1_axi_clk_src.clkr,
+ [GCC_PCIE3X1_1_AXI_M_CLK] = &gcc_pcie3x1_1_axi_m_clk.clkr,
+ [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_1_axi_s_bridge_clk.clkr,
+ [GCC_PCIE3X1_1_AXI_S_CLK] = &gcc_pcie3x1_1_axi_s_clk.clkr,
+ [GCC_PCIE3X1_1_PIPE_CLK] = &gcc_pcie3x1_1_pipe_clk.clkr,
+ [GCC_PCIE3X1_1_RCHG_CLK] = &gcc_pcie3x1_1_rchg_clk.clkr,
+ [GCC_PCIE3X1_1_RCHG_CLK_SRC] = &gcc_pcie3x1_1_rchg_clk_src.clkr,
+ [GCC_PCIE3X1_PHY_AHB_CLK] = &gcc_pcie3x1_phy_ahb_clk.clkr,
+ [GCC_PCIE3X2_AHB_CLK] = &gcc_pcie3x2_ahb_clk.clkr,
+ [GCC_PCIE3X2_AUX_CLK] = &gcc_pcie3x2_aux_clk.clkr,
+ [GCC_PCIE3X2_AXI_M_CLK] = &gcc_pcie3x2_axi_m_clk.clkr,
+ [GCC_PCIE3X2_AXI_M_CLK_SRC] = &gcc_pcie3x2_axi_m_clk_src.clkr,
+ [GCC_PCIE3X2_AXI_S_BRIDGE_CLK] = &gcc_pcie3x2_axi_s_bridge_clk.clkr,
+ [GCC_PCIE3X2_AXI_S_CLK] = &gcc_pcie3x2_axi_s_clk.clkr,
+ [GCC_PCIE3X2_AXI_S_CLK_SRC] = &gcc_pcie3x2_axi_s_clk_src.clkr,
+ [GCC_PCIE3X2_PHY_AHB_CLK] = &gcc_pcie3x2_phy_ahb_clk.clkr,
+ [GCC_PCIE3X2_PIPE_CLK] = &gcc_pcie3x2_pipe_clk.clkr,
+ [GCC_PCIE3X2_RCHG_CLK] = &gcc_pcie3x2_rchg_clk.clkr,
+ [GCC_PCIE3X2_RCHG_CLK_SRC] = &gcc_pcie3x2_rchg_clk_src.clkr,
+ [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
+ [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
+ [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
+ [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
+ [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
+ [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
+ [GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr,
+ [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
+ [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
+ [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
+ [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
+ [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
+ [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
+ [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
+ [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
+ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
+ [GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr,
+ [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
+ [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
+ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
+ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+ [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
+ [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
+ [GCC_QPIC_SLEEP_CLK] = &gcc_qpic_sleep_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
+ [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
+ [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
+ [GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr,
+ [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
+ [GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr,
+ [GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr,
+ [GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr,
+ [GCC_SNOC_PCIE3_1LANE_S_CLK] = &gcc_snoc_pcie3_1lane_s_clk.clkr,
+ [GCC_SNOC_PCIE3_2LANE_M_CLK] = &gcc_snoc_pcie3_2lane_m_clk.clkr,
+ [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
+ [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
+ [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
+ [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
+ [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
+ [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
+ [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
+ [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
+ [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
+ [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
+ [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
+ [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
+ [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
+ [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
+ [GCC_USB0_LFPS_CLK_SRC] = &gcc_usb0_lfps_clk_src.clkr,
+ [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
+ [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
+ [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
+ [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
+ [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
+ [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
+ [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,
+ [GCC_WCSS_AXIM_CLK] = &gcc_wcss_axim_clk.clkr,
+ [GCC_WCSS_AXIS_CLK] = &gcc_wcss_axis_clk.clkr,
+ [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
+ [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
+ [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
+ [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
+ [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
+ [GCC_WCSS_MST_ASYNC_BDG_CLK] = &gcc_wcss_mst_async_bdg_clk.clkr,
+ [GCC_WCSS_SLV_ASYNC_BDG_CLK] = &gcc_wcss_slv_async_bdg_clk.clkr,
+ [GCC_XO_CLK] = &gcc_xo_clk.clkr,
+ [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
+ [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
+ [GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
+ [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
+ [GCC_MEM_NOC_AHB_CLK] = &gcc_mem_noc_ahb_clk.clkr,
+ [GCC_MEM_NOC_APSS_AXI_CLK] = &gcc_mem_noc_apss_axi_clk.clkr,
+ [GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
+ [GCC_MEM_NOC_QOSGEN_EXTREF_CLK] = &gcc_mem_noc_qosgen_extref_clk.clkr,
+ [GCC_PCIE3X2_PIPE_CLK_SRC] = &pcie3x2_pipe_clk_src.clkr,
+ [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &pcie3x1_0_pipe_clk_src.clkr,
+ [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &pcie3x1_1_pipe_clk_src.clkr,
+ [GCC_USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
+};
+
+static const struct qcom_reset_map gcc_ipq5332_resets[] = {
+ [GCC_ADSS_BCR] = { 0x1c000 },
+ [GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 },
+ [GCC_AHB_CLK_ARES] = { 0x34024, 2 },
+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
+ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 },
+ [GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 },
+ [GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 },
+ [GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 },
+ [GCC_BLSP1_BCR] = { 0x1000 },
+ [GCC_BLSP1_QUP1_BCR] = { 0x2000 },
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 },
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 },
+ [GCC_BLSP1_QUP2_BCR] = { 0x3000 },
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 },
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 },
+ [GCC_BLSP1_QUP3_BCR] = { 0x4000 },
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 },
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 },
+ [GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 },
+ [GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 },
+ [GCC_BLSP1_UART1_BCR] = { 0x2028 },
+ [GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 },
+ [GCC_BLSP1_UART2_BCR] = { 0x3028 },
+ [GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 },
+ [GCC_BLSP1_UART3_BCR] = { 0x4028 },
+ [GCC_CE_BCR] = { 0x18008 },
+ [GCC_CMN_BLK_BCR] = { 0x3a000 },
+ [GCC_CMN_LDO0_BCR] = { 0x1d000 },
+ [GCC_CMN_LDO1_BCR] = { 0x1d008 },
+ [GCC_DCC_BCR] = { 0x35000 },
+ [GCC_GP1_CLK_ARES] = { 0x8018, 2 },
+ [GCC_GP2_CLK_ARES] = { 0x9018, 2 },
+ [GCC_LPASS_BCR] = { 0x27000 },
+ [GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 },
+ [GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 },
+ [GCC_MDIOM_BCR] = { 0x12000 },
+ [GCC_MDIOS_BCR] = { 0x12008 },
+ [GCC_NSS_BCR] = { 0x17000 },
+ [GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 },
+ [GCC_NSSCC_CLK_ARES] = { 0x17034, 2 },
+ [GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 },
+ [GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 },
+ [GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 },
+ [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 },
+ [GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 },
+ [GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 },
+ [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 },
+ [GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 },
+ [GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 },
+ [GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 },
+ [GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 },
+ [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 },
+ [GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 },
+ [GCC_PCIE3X1_0_BCR] = { 0x29000 },
+ [GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 },
+ [GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 },
+ [GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c },
+ [GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 },
+ [GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 },
+ [GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 },
+ [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 },
+ [GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 },
+ [GCC_PCIE3X1_1_BCR] = { 0x2a000 },
+ [GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 },
+ [GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 },
+ [GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c },
+ [GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 },
+ [GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 },
+ [GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 },
+ [GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 },
+ [GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 },
+ [GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 },
+ [GCC_PCIE3X2_BCR] = { 0x28000 },
+ [GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 },
+ [GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 },
+ [GCC_PCIE3X2_PHY_BCR] = { 0x28060 },
+ [GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c },
+ [GCC_PCNOC_BCR] = { 0x31000 },
+ [GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 },
+ [GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 },
+ [GCC_PRNG_BCR] = { 0x13020 },
+ [GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 },
+ [GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 },
+ [GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 },
+ [GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 },
+ [GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 },
+ [GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 },
+ [GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 },
+ [GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 },
+ [GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 },
+ [GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 },
+ [GCC_QDSS_BCR] = { 0x2d000 },
+ [GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 },
+ [GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 },
+ [GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 },
+ [GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 },
+ [GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 },
+ [GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 },
+ [GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 },
+ [GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 },
+ [GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 },
+ [GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 },
+ [GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 },
+ [GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 },
+ [GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 },
+ [GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 },
+ [GCC_QPIC_CLK_ARES] = { 0x32014, 2 },
+ [GCC_QPIC_BCR] = { 0x32000 },
+ [GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 },
+ [GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 },
+ [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
+ [GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 },
+ [GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 },
+ [GCC_SDCC_BCR] = { 0x33000 },
+ [GCC_SNOC_BCR] = { 0x2e000 },
+ [GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 },
+ [GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 },
+ [GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 },
+ [GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 },
+ [GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 },
+ [GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 },
+ [GCC_UNIPHY0_BCR] = { 0x16000 },
+ [GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 },
+ [GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 },
+ [GCC_UNIPHY1_BCR] = { 0x16014 },
+ [GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 },
+ [GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 },
+ [GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 },
+ [GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 },
+ [GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 },
+ [GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 },
+ [GCC_USB0_PHY_BCR] = { 0x2c06c },
+ [GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 },
+ [GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 },
+ [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
+ [GCC_USB_BCR] = { 0x2c000 },
+ [GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 },
+ [GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 },
+ [GCC_WCSS_BCR] = { 0x18004 },
+ [GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 },
+ [GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 },
+ [GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 },
+ [GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 },
+ [GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 },
+ [GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 },
+ [GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 },
+ [GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 },
+ [GCC_WCSS_Q6_BCR] = { 0x18000 },
+ [GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 },
+ [GCC_XO_CLK_ARES] = { 0x34018, 2 },
+ [GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 },
+ [GCC_Q6SS_DBG_ARES] = { 0x25094 },
+ [GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 },
+ [GCC_WCSS_DBG_ARES] = { 0x25098, 1 },
+ [GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 },
+ [GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 },
+ [GCC_WCSSAON_ARES] = { 0x2509C },
+ [GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 },
+ [GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 },
+ [GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 },
+ [GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 },
+ [GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 },
+ [GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 },
+ [GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 },
+ [GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 },
+ [GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 },
+ [GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 },
+ [GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
+ [GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 },
+ [GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 },
+ [GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 },
+ [GCC_UNIPHY0_XPCS_ARES] = { 0x16050 },
+ [GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
+};
+
+static const struct regmap_config gcc_ipq5332_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x3f024,
+ .fast_io = true,
+};
+
+static struct clk_hw *gcc_ipq5332_hws[] = {
+ &gpll0_div2.hw,
+ &gcc_xo_div4_clk_src.hw,
+ &gcc_system_noc_bfdcd_div2_clk_src.hw,
+ &gcc_qdss_tsctr_div2_clk_src.hw,
+ &gcc_qdss_tsctr_div3_clk_src.hw,
+ &gcc_qdss_tsctr_div4_clk_src.hw,
+ &gcc_qdss_tsctr_div8_clk_src.hw,
+ &gcc_qdss_tsctr_div16_clk_src.hw,
+ &gcc_eud_at_div_clk_src.hw,
+};
+
+static const struct qcom_cc_desc gcc_ipq5332_desc = {
+ .config = &gcc_ipq5332_regmap_config,
+ .clks = gcc_ipq5332_clocks,
+ .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
+ .resets = gcc_ipq5332_resets,
+ .num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
+ .clk_hws = gcc_ipq5332_hws,
+ .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
+};
+
+static int gcc_ipq5332_probe(struct platform_device *pdev)
+{
+ return qcom_cc_probe(pdev, &gcc_ipq5332_desc);
+}
+
+static const struct of_device_id gcc_ipq5332_match_table[] = {
+ { .compatible = "qcom,ipq5332-gcc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_ipq5332_match_table);
+
+static struct platform_driver gcc_ipq5332_driver = {
+ .probe = gcc_ipq5332_probe,
+ .driver = {
+ .name = "gcc-ipq5332",
+ .of_match_table = gcc_ipq5332_match_table,
+ },
+};
+
+static int __init gcc_ipq5332_init(void)
+{
+ return platform_driver_register(&gcc_ipq5332_driver);
+}
+core_initcall(gcc_ipq5332_init);
+
+static void __exit gcc_ipq5332_exit(void)
+{
+ platform_driver_unregister(&gcc_ipq5332_driver);
+}
+module_exit(gcc_ipq5332_exit);
+
+MODULE_DESCRIPTION("QTI GCC IPQ5332 Driver");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 6/9] dt-bindings: qcom: add ipq5332 boards
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 7:12 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Document the new ipq5332 SoC/board device tree bindings
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Sorted the board name
Changes in V2:
- No changes
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 22553637c519..c8752465d3f6 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -30,6 +30,7 @@ description: |
apq8084
apq8096
ipq4018
+ ipq5332
ipq6018
ipq8074
mdm9615
@@ -79,6 +80,7 @@ description: |
The 'board' element must be one of the following strings:
adp
+ ap-mi01.2
cdp
cp01-c1
dragonboard
@@ -316,6 +318,11 @@ properties:
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
+ - items:
+ - enum:
+ - qcom,ipq5332-ap-mi01.2
+ - const: qcom,ipq5332
+
- items:
- enum:
- mikrotik,rb3011
--
2.17.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 6/9] dt-bindings: qcom: add ipq5332 boards
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Document the new ipq5332 SoC/board device tree bindings
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Sorted the board name
Changes in V2:
- No changes
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 22553637c519..c8752465d3f6 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -30,6 +30,7 @@ description: |
apq8084
apq8096
ipq4018
+ ipq5332
ipq6018
ipq8074
mdm9615
@@ -79,6 +80,7 @@ description: |
The 'board' element must be one of the following strings:
adp
+ ap-mi01.2
cdp
cp01-c1
dragonboard
@@ -316,6 +318,11 @@ properties:
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
+ - items:
+ - enum:
+ - qcom,ipq5332-ap-mi01.2
+ - const: qcom,ipq5332
+
- items:
- enum:
- mikrotik,rb3011
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 7/9] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 7:12 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Document the compatible for IPQ5332 SCM.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- No changes
Changes in V2:
- Added the 'Acked-by' tag
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index 4193492ba73e..02354d06e054 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -24,6 +24,7 @@ properties:
- qcom,scm-apq8064
- qcom,scm-apq8084
- qcom,scm-ipq4019
+ - qcom,scm-ipq5332
- qcom,scm-ipq6018
- qcom,scm-ipq806x
- qcom,scm-ipq8074
--
2.17.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 7/9] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Document the compatible for IPQ5332 SCM.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- No changes
Changes in V2:
- Added the 'Acked-by' tag
Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index 4193492ba73e..02354d06e054 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -24,6 +24,7 @@ properties:
- qcom,scm-apq8064
- qcom,scm-apq8084
- qcom,scm-ipq4019
+ - qcom,scm-ipq5332
- qcom,scm-ipq6018
- qcom,scm-ipq806x
- qcom,scm-ipq8074
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 7:12 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Add initial device tree support for the Qualcomm IPQ5332 SoC and
MI01.2 board.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Updated the V2M node name to reflect the proper address
- In reserved-memory node, changed the order of the 'reg' and
'no-map' property
- Moved the below properties to the board DTS
bus-width = <4>;
max-frequency = <192000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
Changes in V2:
- Changed the license to BSD3 in the file ipq5332-mi01.2.dts
- Updated the model name, not to include the foundry ID
- Used the decimal notation instead of hex for 'cache-level'
property
- Dropped the blank line
- Updated the node name for the TZ reserved region
- Moved the 'compatible' property as first one in the node,
wherever applicable
- Used the decimal notation for *-cells property insrtead of
hex
- Reorganised the properties of memory mapped timer node as
below
- reg
- interrupts
- frame-number
- Fixed the indentation in timer node
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 75 ++++++
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 ++++++++++++++++++++
3 files changed, 344 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 557d77d48dc8..03431cfde6a5 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
new file mode 100644
index 000000000000..702013b867d7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * IPQ5332 AP-MI01.2 board device tree source
+ *
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5332.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";
+ compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
+
+ aliases {
+ serial0 = &blsp1_uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+};
+
+&blsp1_uart0 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdhc {
+ bus-width = <4>;
+ max-frequency = <192000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-0 = <&sdc_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&xo_board {
+ clock-frequency = <24000000>;
+};
+
+/* PINCTRL */
+
+&tlmm {
+ sdc_default_state: sdc-default-state {
+ clk-pins {
+ pins = "gpio13";
+ function = "sdc_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio12";
+ function = "sdc_cmd";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "sdc_data";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
new file mode 100644
index 000000000000..4ded165653c9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * IPQ5332 device tree source
+ *
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&intc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ xo_board: xo-board-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq5332", "qcom,scm";
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x40000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tz_mem: tz@4a600000 {
+ reg = <0x0 0x4a600000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5332-tlmm";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 53>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ serial_0_pins: serial0-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp0_uart0";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ gcc: clock-controller@1800000 {
+ compatible = "qcom,ipq5332-gcc";
+ reg = <0x01800000 0x80000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clock-names = "xo",
+ "sleep_clk",
+ "pcie_2lane_phy_pipe_clk",
+ "pcie_2lane_phy_pipe_clk_x1",
+ "usb_pcie_wrapper_pipe_clk";
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>;
+ };
+
+ sdhc: mmc@7804000 {
+ compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
+
+ interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "core", "xo";
+ status = "disabled";
+ };
+
+ blsp1_uart0: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078af000 0x200>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ reg = <0x0b000000 0x1000>, /* GICD */
+ <0x0b002000 0x1000>, /* GICC */
+ <0x0b001000 0x1000>, /* GICH */
+ <0x0b004000 0x1000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0b00c000 0x3000>;
+
+ v2m0: v2m@0 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00000000 0xffd>;
+ msi-controller;
+ };
+
+ v2m1: v2m@1000 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00001000 0xffd>;
+ msi-controller;
+ };
+
+ v2m2: v2m@2000 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00002000 0xffd>;
+ msi-controller;
+ };
+ };
+
+ timer@b120000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0b120000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ frame@b120000 {
+ reg = <0x0b121000 0x1000>,
+ <0x0b122000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <0>;
+ };
+
+ frame@b123000 {
+ reg = <0x0b123000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <1>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ reg = <0x0b124000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <2>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ reg = <0x0b125000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <3>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ reg = <0x0b126000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <4>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ reg = <0x0b127000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <5>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ reg = <0x0b128000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <6>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Add initial device tree support for the Qualcomm IPQ5332 SoC and
MI01.2 board.
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Updated the V2M node name to reflect the proper address
- In reserved-memory node, changed the order of the 'reg' and
'no-map' property
- Moved the below properties to the board DTS
bus-width = <4>;
max-frequency = <192000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
Changes in V2:
- Changed the license to BSD3 in the file ipq5332-mi01.2.dts
- Updated the model name, not to include the foundry ID
- Used the decimal notation instead of hex for 'cache-level'
property
- Dropped the blank line
- Updated the node name for the TZ reserved region
- Moved the 'compatible' property as first one in the node,
wherever applicable
- Used the decimal notation for *-cells property insrtead of
hex
- Reorganised the properties of memory mapped timer node as
below
- reg
- interrupts
- frame-number
- Fixed the indentation in timer node
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 75 ++++++
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 268 ++++++++++++++++++++
3 files changed, 344 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 557d77d48dc8..03431cfde6a5 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
new file mode 100644
index 000000000000..702013b867d7
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * IPQ5332 AP-MI01.2 board device tree source
+ *
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5332.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";
+ compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
+
+ aliases {
+ serial0 = &blsp1_uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+};
+
+&blsp1_uart0 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sdhc {
+ bus-width = <4>;
+ max-frequency = <192000000>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-0 = <&sdc_default_state>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&sleep_clk {
+ clock-frequency = <32000>;
+};
+
+&xo_board {
+ clock-frequency = <24000000>;
+};
+
+/* PINCTRL */
+
+&tlmm {
+ sdc_default_state: sdc-default-state {
+ clk-pins {
+ pins = "gpio13";
+ function = "sdc_clk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ cmd-pins {
+ pins = "gpio12";
+ function = "sdc_cmd";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ data-pins {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ function = "sdc_data";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
new file mode 100644
index 000000000000..4ded165653c9
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * IPQ5332 device tree source
+ *
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&intc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ xo_board: xo-board-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq5332", "qcom,scm";
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x40000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tz_mem: tz@4a600000 {
+ reg = <0x0 0x4a600000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5332-tlmm";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 53>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ serial_0_pins: serial0-state {
+ pins = "gpio18", "gpio19";
+ function = "blsp0_uart0";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ gcc: clock-controller@1800000 {
+ compatible = "qcom,ipq5332-gcc";
+ reg = <0x01800000 0x80000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clock-names = "xo",
+ "sleep_clk",
+ "pcie_2lane_phy_pipe_clk",
+ "pcie_2lane_phy_pipe_clk_x1",
+ "usb_pcie_wrapper_pipe_clk";
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <0>,
+ <0>,
+ <0>;
+ };
+
+ sdhc: mmc@7804000 {
+ compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
+
+ interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>;
+ clock-names = "iface", "core", "xo";
+ status = "disabled";
+ };
+
+ blsp1_uart0: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078af000 0x200>;
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ reg = <0x0b000000 0x1000>, /* GICD */
+ <0x0b002000 0x1000>, /* GICC */
+ <0x0b001000 0x1000>, /* GICH */
+ <0x0b004000 0x1000>; /* GICV */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0b00c000 0x3000>;
+
+ v2m0: v2m@0 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00000000 0xffd>;
+ msi-controller;
+ };
+
+ v2m1: v2m@1000 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00001000 0xffd>;
+ msi-controller;
+ };
+
+ v2m2: v2m@2000 {
+ compatible = "arm,gic-v2m-frame";
+ reg = <0x00002000 0xffd>;
+ msi-controller;
+ };
+ };
+
+ timer@b120000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0b120000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ frame@b120000 {
+ reg = <0x0b121000 0x1000>,
+ <0x0b122000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <0>;
+ };
+
+ frame@b123000 {
+ reg = <0x0b123000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <1>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ reg = <0x0b124000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <2>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ reg = <0x0b125000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <3>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ reg = <0x0b126000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <4>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ reg = <0x0b127000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <5>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ reg = <0x0b128000 0x1000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ frame-number = <6>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.17.1
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^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 9/9] arm64: defconfig: Enable IPQ5332 SoC base configs
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 7:12 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Enable the clock and pinctrl configs for Qualcomm IPQ5332 SoC
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Updated the commit message
Changed in V2:
- No changes
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index a8c74a419d95..70e45e622ab5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -555,6 +555,7 @@ CONFIG_PINCTRL_IMX8ULP=y
CONFIG_PINCTRL_IMX93=y
CONFIG_PINCTRL_MSM=y
CONFIG_PINCTRL_IPQ8074=y
+CONFIG_PINCTRL_IPQ5332=y
CONFIG_PINCTRL_IPQ6018=y
CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8953=y
@@ -1129,6 +1130,7 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y
CONFIG_QCOM_CLK_APCC_MSM8996=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
+CONFIG_IPQ_GCC_5332=y
CONFIG_IPQ_GCC_6018=y
CONFIG_IPQ_GCC_8074=y
CONFIG_MSM_GCC_8916=y
--
2.17.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH V3 9/9] arm64: defconfig: Enable IPQ5332 SoC base configs
@ 2023-02-06 7:12 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 7:12 UTC (permalink / raw)
To: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara, Kathiravan T
Enable the clock and pinctrl configs for Qualcomm IPQ5332 SoC
Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
---
Changes in V3:
- Updated the commit message
Changed in V2:
- No changes
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index a8c74a419d95..70e45e622ab5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -555,6 +555,7 @@ CONFIG_PINCTRL_IMX8ULP=y
CONFIG_PINCTRL_IMX93=y
CONFIG_PINCTRL_MSM=y
CONFIG_PINCTRL_IPQ8074=y
+CONFIG_PINCTRL_IPQ5332=y
CONFIG_PINCTRL_IPQ6018=y
CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8953=y
@@ -1129,6 +1130,7 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y
CONFIG_QCOM_CLK_APCC_MSM8996=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
+CONFIG_IPQ_GCC_5332=y
CONFIG_IPQ_GCC_6018=y
CONFIG_IPQ_GCC_8074=y
CONFIG_MSM_GCC_8916=y
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH V3 1/9] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 8:26 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 48+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-06 8:26 UTC (permalink / raw)
To: Kathiravan T, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 08:12, Kathiravan T wrote:
> Add device tree bindings for IPQ5332 TLMM block.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 1/9] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
@ 2023-02-06 8:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 48+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-06 8:26 UTC (permalink / raw)
To: Kathiravan T, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 08:12, Kathiravan T wrote:
> Add device tree bindings for IPQ5332 TLMM block.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 8:26 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 48+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-06 8:26 UTC (permalink / raw)
To: Kathiravan T, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 08:12, Kathiravan T wrote:
> Add binding for the Qualcomm IPQ5332 Global Clock Controller.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
> Changes in V3:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
@ 2023-02-06 8:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 48+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-06 8:26 UTC (permalink / raw)
To: Kathiravan T, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 08:12, Kathiravan T wrote:
> Add binding for the Qualcomm IPQ5332 Global Clock Controller.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
> Changes in V3:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 6/9] dt-bindings: qcom: add ipq5332 boards
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 8:27 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 48+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-06 8:27 UTC (permalink / raw)
To: Kathiravan T, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 08:12, Kathiravan T wrote:
> Document the new ipq5332 SoC/board device tree bindings
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 6/9] dt-bindings: qcom: add ipq5332 boards
@ 2023-02-06 8:27 ` Krzysztof Kozlowski
0 siblings, 0 replies; 48+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-06 8:27 UTC (permalink / raw)
To: Kathiravan T, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 08:12, Kathiravan T wrote:
> Document the new ipq5332 SoC/board device tree bindings
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 9:52 ` Dmitry Baryshkov
-1 siblings, 0 replies; 48+ messages in thread
From: Dmitry Baryshkov @ 2023-02-06 9:52 UTC (permalink / raw)
To: Kathiravan T, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 09:12, Kathiravan T wrote:
> Add binding for the Qualcomm IPQ5332 Global Clock Controller.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
> Changes in V3:
> - Actually I missed to remove the clocks in V2 which are supposed to
> be removed. In V3 I have removed those and they are
> GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK
> - For the same, didn't add the Reviewed-By tags from Stephen and
> Krzysztof
>
> Changes in V2:
> - property 'clocks' is marked required
> - Renamed the include file name to match with compatible
>
> .../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++
> include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++
> 2 files changed, 417 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
> create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
> new file mode 100644
> index 000000000000..961311af400c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller on IPQ5332
> +
> +maintainers:
> + - Stephen Boyd <sboyd@kernel.org>
> +
> +description: |
> + Qualcomm global clock control module provides the clocks, resets and power
> + domains on IPQ5332.
> +
> + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
> +
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,ipq5332-gcc
> +
> + clocks:
> + items:
> + - description: Board XO clock source
> + - description: Sleep clock source
> + - description: PCIE 2lane PHY pipe clock source
> + - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
> + - description: USB PCIE wrapper pipe clock source
> +
> + clock-names:
> + items:
> + - const: xo
> + - const: sleep_clk
> + - const: pcie_2lane_phy_pipe_clk
> + - const: pcie_2lane_phy_pipe_clk_x1
> + - const: usb_pcie_wrapper_pipe_clk
pcie3x1_0_pipe_clk_src, pcie3x1_1_pipe_clk_src, pcie3x2_pipe_clk_src
usb0_pipe_clk_src are missing.
> +
> +required:
> + - compatible
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + clock-controller@1800000 {
> + compatible = "qcom,ipq5332-gcc";
> + reg = <0x01800000 0x80000>;
> + clocks = <&xo_board>,
> + <&sleep_clk>,
> + <&pcie_2lane_phy_pipe_clk>,
> + <&pcie_2lane_phy_pipe_clk_x1>,
> + <&usb_pcie_wrapper_pipe_clk>;
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + #reset-cells = <1>;
> + };
> +...
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
@ 2023-02-06 9:52 ` Dmitry Baryshkov
0 siblings, 0 replies; 48+ messages in thread
From: Dmitry Baryshkov @ 2023-02-06 9:52 UTC (permalink / raw)
To: Kathiravan T, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 09:12, Kathiravan T wrote:
> Add binding for the Qualcomm IPQ5332 Global Clock Controller.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
> Changes in V3:
> - Actually I missed to remove the clocks in V2 which are supposed to
> be removed. In V3 I have removed those and they are
> GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK
> - For the same, didn't add the Reviewed-By tags from Stephen and
> Krzysztof
>
> Changes in V2:
> - property 'clocks' is marked required
> - Renamed the include file name to match with compatible
>
> .../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++
> include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++
> 2 files changed, 417 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
> create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
> new file mode 100644
> index 000000000000..961311af400c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller on IPQ5332
> +
> +maintainers:
> + - Stephen Boyd <sboyd@kernel.org>
> +
> +description: |
> + Qualcomm global clock control module provides the clocks, resets and power
> + domains on IPQ5332.
> +
> + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
> +
> +allOf:
> + - $ref: qcom,gcc.yaml#
> +
> +properties:
> + compatible:
> + const: qcom,ipq5332-gcc
> +
> + clocks:
> + items:
> + - description: Board XO clock source
> + - description: Sleep clock source
> + - description: PCIE 2lane PHY pipe clock source
> + - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
> + - description: USB PCIE wrapper pipe clock source
> +
> + clock-names:
> + items:
> + - const: xo
> + - const: sleep_clk
> + - const: pcie_2lane_phy_pipe_clk
> + - const: pcie_2lane_phy_pipe_clk_x1
> + - const: usb_pcie_wrapper_pipe_clk
pcie3x1_0_pipe_clk_src, pcie3x1_1_pipe_clk_src, pcie3x2_pipe_clk_src
usb0_pipe_clk_src are missing.
> +
> +required:
> + - compatible
> + - clocks
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + clock-controller@1800000 {
> + compatible = "qcom,ipq5332-gcc";
> + reg = <0x01800000 0x80000>;
> + clocks = <&xo_board>,
> + <&sleep_clk>,
> + <&pcie_2lane_phy_pipe_clk>,
> + <&pcie_2lane_phy_pipe_clk_x1>,
> + <&usb_pcie_wrapper_pipe_clk>;
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + #reset-cells = <1>;
> + };
> +...
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
2023-02-06 7:12 ` [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Kathiravan T
@ 2023-02-06 9:52 ` Dmitry Baryshkov
2023-02-06 9:56 ` Dmitry Baryshkov
2023-02-07 3:41 ` Bjorn Andersson
2 siblings, 0 replies; 48+ messages in thread
From: Dmitry Baryshkov @ 2023-02-06 9:52 UTC (permalink / raw)
To: Kathiravan T, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 09:12, Kathiravan T wrote:
> Add support for the global clock controller found on IPQ5332 SoC.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
> Changes in V3:
> - As I mentined the bindings, changes need to be done in V2 got
> missed out and same has been done in V3, to call out
> specifically dropped the CLK_IS_CRITICAL and dropped the
> gcc_apss_ahb_clk, its source clock and gcc_apss_axi_clk
> - Used gcc_parent_data_xo wherever applicable and dropped the
> duplicate entries
> - dropped the unused parent_map_10 and parent_data_10
> - Used qcom_cc_probe instead of qcom_cc_really_probe
> Changes in V2:
> - Added the 'dependes on' for Kconfig symbol
> - Dropped the CLK_IS_CRITICAL flag throughout the file
> - Dropped the gcc_apss_ahb_clk and gcc_apss_axi_clk as these are
> managed by bootloaders
>
> drivers/clk/qcom/Kconfig | 8 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-ipq5332.c | 3850 ++++++++++++++++++++++++++++++++
> 3 files changed, 3859 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-ipq5332.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 5ab4b7dfe3c2..10da46fa702e 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -141,6 +141,14 @@ config IPQ_GCC_4019
> Say Y if you want to use peripheral devices such as UART, SPI,
> i2c, USB, SD/eMMC, etc.
>
> +config IPQ_GCC_5332
> + tristate "IPQ5332 Global Clock Controller"
> + depends on ARM64 || COMPILE_TEST
> + help
> + Support for the global clock controller on ipq5332 devices.
> + Say Y if you want to use peripheral devices such as UART, SPI,
> + i2c, USB, SD/eMMC, etc.
> +
> config IPQ_GCC_6018
> tristate "IPQ6018 Global Clock Controller"
> help
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 3194465dd02c..c238abee3c8e 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
> obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
> obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
> obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
> +obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
> obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> new file mode 100644
> index 000000000000..c8a5fa1bafca
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq5332.c
> @@ -0,0 +1,3850 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "reset.h"
> +
> +enum {
> + DT_SLEEP_CLK,
> + DT_XO,
> + DT_PCIE_2LANE_PHY_PIPE_CLK,
> + DT_PCIE_2LANE_PHY_PIPE_X1_CLK,
> + DT_USB_PCIE_WRAPPER_PIPE_CLK,
> +};
> +
> +enum {
> + P_PCIE3X2_PIPE,
> + P_PCIE3X1_0_PIPE,
> + P_PCIE3X1_1_PIPE,
> + P_USB3PHY_0_PIPE,
> + P_CORE_BI_PLL_TEST_SE,
> + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
> + P_GPLL0_OUT_AUX,
> + P_GPLL0_OUT_MAIN,
> + P_GPLL2_OUT_AUX,
> + P_GPLL2_OUT_MAIN,
> + P_GPLL4_OUT_AUX,
> + P_GPLL4_OUT_MAIN,
> + P_SLEEP_CLK,
> + P_XO,
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
> +
> +static struct clk_alpha_pll gpll0_main = {
> + .offset = 0x20000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
> + .clkr = {
> + .enable_reg = 0xb000,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gpll0_main",
> + .parent_data = &gcc_parent_data_xo,
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_stromer_ops,
> + },
> + },
> +};
> +
> +static struct clk_fixed_factor gpll0_div2 = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll0_div2",
> + .parent_hws = (const struct clk_hw *[]){
> + &gpll0_main.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll0 = {
> + .offset = 0x20000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll0",
> + .parent_hws = (const struct clk_hw *[]){
> + &gpll0_main.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll2_main = {
> + .offset = 0x21000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
> + .clkr = {
> + .enable_reg = 0xb000,
> + .enable_mask = BIT(1),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gpll2",
> + .parent_data = &gcc_parent_data_xo,
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_stromer_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll2 = {
> + .offset = 0x21000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll2_main",
> + .parent_hws = (const struct clk_hw *[]){
> + &gpll2_main.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll4_main = {
> + .offset = 0x22000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
> + .clkr = {
> + .enable_reg = 0xb000,
> + .enable_mask = BIT(2),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gpll4_main",
> + .parent_data = &gcc_parent_data_xo,
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_stromer_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll4 = {
> + .offset = 0x22000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
> + .width = 4,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll4",
> + .parent_hws = (const struct clk_hw *[]){
> + &gpll4_main.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ro_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct parent_map gcc_parent_map_xo[] = {
> + { P_XO, 0 },
> +};
> +
> +static const struct parent_map gcc_parent_map_0[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_0[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0_div2.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_1[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_1[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_2[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL4_OUT_MAIN, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_2[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll4.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_3[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
> + { P_SLEEP_CLK, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_3[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0_div2.hw },
> + { .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_4[] = {
> + { P_XO, 0 },
> + { P_GPLL4_OUT_MAIN, 1 },
> + { P_GPLL0_OUT_AUX, 2 },
> + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_4[] = {
> + { .index = DT_XO },
> + { .hw = &gpll4.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0_div2.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_5[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL2_OUT_AUX, 2 },
> + { P_GPLL4_OUT_AUX, 3 },
> + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
> + { P_GPLL0_OUT_AUX, 5 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_5[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll2.clkr.hw },
> + { .hw = &gpll4.clkr.hw },
> + { .hw = &gpll0_div2.hw },
> + { .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_6[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL0_OUT_AUX, 2 },
> + { P_SLEEP_CLK, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_6[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> + { .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_7[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL2_OUT_AUX, 2 },
> + { P_GPLL4_OUT_AUX, 3 },
> + { P_SLEEP_CLK, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_7[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll2.clkr.hw },
> + { .hw = &gpll4.clkr.hw },
> + { .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_8[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL2_OUT_AUX, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_8[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll2.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_9[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL2_OUT_MAIN, 2 },
> + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_9[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll2.clkr.hw },
> + { .hw = &gpll0_div2.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_10[] = {
> + { P_SLEEP_CLK, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_10[] = {
> + { .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_11[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_MAIN, 1 },
> + { P_GPLL4_OUT_MAIN, 2 },
> + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_11[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll4.clkr.hw },
> + { .hw = &gpll0_div2.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_12[] = {
> + { P_XO, 0 },
> + { P_GPLL0_OUT_AUX, 2 },
> + { P_SLEEP_CLK, 6 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_12[] = {
> + { .index = DT_XO },
> + { .hw = &gpll0.clkr.hw },
> + { .index = DT_SLEEP_CLK },
> +};
> +
> +static const struct parent_map gcc_parent_map_13[] = {
> + { P_XO, 0 },
> + { P_GPLL4_OUT_AUX, 1 },
> + { P_GPLL0_OUT_MAIN, 3 },
> + { P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_13[] = {
> + { .index = DT_XO },
> + { .hw = &gpll4.clkr.hw },
> + { .hw = &gpll0.clkr.hw },
> + { .hw = &gpll0_div2.hw },
> +};
> +
> +static const struct parent_map gcc_parent_map_14[] = {
> + { P_PCIE3X2_PIPE, 0 },
> + { P_XO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_14[] = {
> + { .index = DT_PCIE_2LANE_PHY_PIPE_CLK },
> + { .index = DT_XO },
> +};
> +
> +static const struct parent_map gcc_parent_map_15[] = {
> + { P_PCIE3X1_0_PIPE, 0 },
> + { P_XO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_15[] = {
> + { .index = DT_USB_PCIE_WRAPPER_PIPE_CLK },
> + { .index = DT_XO },
> +};
> +
> +static const struct parent_map gcc_parent_map_16[] = {
> + { P_PCIE3X1_1_PIPE, 0 },
> + { P_XO, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_16[] = {
> + { .index = DT_PCIE_2LANE_PHY_PIPE_X1_CLK },
> + { .index = DT_XO },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {
> + F(24000000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_adss_pwm_clk_src = {
> + .cmd_rcgr = 0x1c004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_1,
> + .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_adss_pwm_clk_src",
> + .parent_data = gcc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {
> + F(480000000, P_GPLL4_OUT_MAIN, 2.5, 0, 0),
> + F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_apss_axi_clk_src = {
> + .cmd_rcgr = 0x24004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_5,
> + .freq_tbl = ftbl_gcc_apss_axi_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_apss_axi_clk_src",
> + .parent_data = gcc_parent_data_5,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_5),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {
> + F(960000, P_XO, 1, 1, 25),
> + F(4800000, P_XO, 5, 0, 0),
> + F(9600000, P_XO, 2.5, 0, 0),
> + F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
> + F(24000000, P_XO, 1, 0, 0),
> + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
> + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0x2004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_qup1_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0x3004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_qup2_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0x4004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_qup3_spi_apps_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {
> + F(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625),
> + F(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625),
> + F(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625),
> + F(24000000, P_XO, 1, 0, 0),
> + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
> + F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
> + F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
> + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
> + F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
> + F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
> + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
> + F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
> + F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
> + F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {
> + .cmd_rcgr = 0x202c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_uart1_apps_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {
> + .cmd_rcgr = 0x302c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_uart2_apps_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {
> + .cmd_rcgr = 0x402c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_uart3_apps_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
> + F(24000000, P_XO, 1, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_gp1_clk_src = {
> + .cmd_rcgr = 0x8004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_3,
> + .freq_tbl = ftbl_gcc_gp1_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_gp1_clk_src",
> + .parent_data = gcc_parent_data_3,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_3),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_gp2_clk_src = {
> + .cmd_rcgr = 0x9004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_3,
> + .freq_tbl = ftbl_gcc_gp1_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_gp2_clk_src",
> + .parent_data = gcc_parent_data_3,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_3),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {
> + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_lpass_sway_clk_src = {
> + .cmd_rcgr = 0x27004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_1,
> + .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_lpass_sway_clk_src",
> + .parent_data = gcc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {
> + F(24000000, P_XO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_nss_ts_clk_src = {
> + .cmd_rcgr = 0x17088,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo,
> + .freq_tbl = ftbl_gcc_nss_ts_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_nss_ts_clk_src",
> + .parent_data = &gcc_parent_data_xo,
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pcie3x1_0_axi_clk_src[] = {
> + F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pcie3x1_0_axi_clk_src = {
> + .cmd_rcgr = 0x29018,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_axi_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_pcie3x1_0_rchg_clk_src = {
> + .cmd_rcgr = 0x2907c,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_rchg_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_0_rchg_clk = {
> + .halt_reg = 0x2907c,
> + .clkr = {
> + .enable_reg = 0x2907c,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie3x1_0_rchg_clk",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_pcie3x1_0_rchg_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_rcg2 gcc_pcie3x1_1_axi_clk_src = {
> + .cmd_rcgr = 0x2a004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_1_axi_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_pcie3x1_1_rchg_clk_src = {
> + .cmd_rcgr = 0x2a078,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_1_rchg_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_1_rchg_clk = {
> + .halt_reg = 0x2a078,
> + .clkr = {
> + .enable_reg = 0x2a078,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie3x1_1_rchg_clk",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_pcie3x1_1_rchg_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pcie3x2_axi_m_clk_src[] = {
> + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pcie3x2_axi_m_clk_src = {
> + .cmd_rcgr = 0x28018,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_pcie3x2_axi_m_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_axi_m_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_pcie3x2_axi_s_clk_src = {
> + .cmd_rcgr = 0x28084,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_2,
> + .freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_axi_s_clk_src",
> + .parent_data = gcc_parent_data_2,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_2),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_pcie3x2_rchg_clk_src = {
> + .cmd_rcgr = 0x28078,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_adss_pwm_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_rchg_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x2_rchg_clk = {
> + .halt_reg = 0x28078,
> + .clkr = {
> + .enable_reg = 0x28078,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pcie3x2_rchg_clk",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_pcie3x2_rchg_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
> + F(2000000, P_XO, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pcie_aux_clk_src = {
> + .cmd_rcgr = 0x28004,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_6,
> + .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie_aux_clk_src",
> + .parent_data = gcc_parent_data_6,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_mux pcie3x2_pipe_clk_src = {
> + .reg = 0x28064,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_14,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie3x2_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_14,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_14),
> + .ops = &clk_regmap_mux_closest_ops,
Should we use clk_regmap_phy_mux_ops here instead?
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux pcie3x1_0_pipe_clk_src = {
> + .reg = 0x29064,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_15,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie3x1_0_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_15,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_15),
> + .ops = &clk_regmap_mux_closest_ops,
And clk_regmap_phy_mux_ops here too?
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux pcie3x1_1_pipe_clk_src = {
> + .reg = 0x2A064,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_16,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie3x1_1_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_16,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_16),
> + .ops = &clk_regmap_mux_closest_ops,
And here?
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {
> + F(24000000, P_XO, 1, 0, 0),
> + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {
> + .cmd_rcgr = 0x31004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcnoc_bfdcd_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_q6_axim_clk_src = {
> + .cmd_rcgr = 0x25004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_7,
> + .freq_tbl = ftbl_gcc_apss_axi_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_q6_axim_clk_src",
> + .parent_data = gcc_parent_data_7,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_7),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {
> + F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_qdss_at_clk_src = {
> + .cmd_rcgr = 0x2d004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_4,
> + .freq_tbl = ftbl_gcc_qdss_at_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_qdss_at_clk_src",
> + .parent_data = gcc_parent_data_4,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {
> + F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {
> + .cmd_rcgr = 0x2d01c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_4,
> + .freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_qdss_tsctr_clk_src",
> + .parent_data = gcc_parent_data_4,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_4),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qdss_tsctr_div2_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_qdss_tsctr_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {
> + .mult = 1,
> + .div = 3,
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qdss_tsctr_div3_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_qdss_tsctr_clk_src.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qdss_tsctr_div4_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_qdss_tsctr_clk_src.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {
> + .mult = 1,
> + .div = 8,
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qdss_tsctr_div8_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_qdss_tsctr_clk_src.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {
> + .mult = 1,
> + .div = 16,
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qdss_tsctr_div16_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_qdss_tsctr_clk_src.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {
> + F(24000000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {
> + .cmd_rcgr = 0x32004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_qpic_io_macro_clk_src",
> + .parent_data = gcc_parent_data_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_8),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
> + F(143713, P_XO, 1, 1, 167),
> + F(400000, P_XO, 1, 1, 60),
> + F(24000000, P_XO, 1, 0, 0),
> + F(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2),
> + F(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
> + F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
> + F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
> + .cmd_rcgr = 0x33004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_9,
> + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_sdcc1_apps_clk_src",
> + .parent_data = gcc_parent_data_9,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_9),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {
> + F(32000, P_SLEEP_CLK, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_sleep_clk_src = {
> + .cmd_rcgr = 0x3400c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_10,
> + .freq_tbl = ftbl_gcc_sleep_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_sleep_clk_src",
> + .parent_data = gcc_parent_data_10,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_10),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {
> + F(24000000, P_XO, 1, 0, 0),
> + F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
> + F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
> + F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {
> + .cmd_rcgr = 0x2e004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_11,
> + .freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_system_noc_bfdcd_clk_src",
> + .parent_data = gcc_parent_data_11,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_11),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_system_noc_bfdcd_div2_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_uniphy_sys_clk_src = {
> + .cmd_rcgr = 0x16004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo,
> + .freq_tbl = ftbl_gcc_nss_ts_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_uniphy_sys_clk_src",
> + .parent_data = &gcc_parent_data_xo,
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_usb0_aux_clk_src = {
> + .cmd_rcgr = 0x2c018,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_12,
> + .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_aux_clk_src",
> + .parent_data = gcc_parent_data_12,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_12),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb0_lfps_clk_src[] = {
> + F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_usb0_lfps_clk_src = {
> + .cmd_rcgr = 0x2c07c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_1,
> + .freq_tbl = ftbl_gcc_usb0_lfps_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_lfps_clk_src",
> + .parent_data = gcc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_usb0_master_clk_src = {
> + .cmd_rcgr = 0x2c004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_0,
> + .freq_tbl = ftbl_gcc_gp1_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_master_clk_src",
> + .parent_data = gcc_parent_data_0,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_0),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {
> + F(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {
> + .cmd_rcgr = 0x2c02c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_13,
> + .freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_mock_utmi_clk_src",
> + .parent_data = gcc_parent_data_13,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_13),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_mux usb0_pipe_clk_src = {
> + .reg = 0x2C074,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_15,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "usb0phy_0_cc_pipe_clk_src",
> + .parent_data = gcc_parent_data_15,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_15),
> + .ops = &clk_regmap_mux_closest_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_rcg2 gcc_wcss_ahb_clk_src = {
> + .cmd_rcgr = 0x25030,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_1,
> + .freq_tbl = ftbl_gcc_lpass_sway_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_ahb_clk_src",
> + .parent_data = gcc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gcc_xo_clk_src = {
> + .cmd_rcgr = 0x34004,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo,
> + .freq_tbl = ftbl_gcc_nss_ts_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_xo_clk_src",
> + .parent_data = &gcc_parent_data_xo,
> + .num_parents = 1,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_fixed_factor gcc_xo_div4_clk_src = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_xo_div4_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_xo_clk_src.clkr.hw },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap_div gcc_qdss_dap_div_clk_src = {
> + .reg = 0x2d028,
> + .shift = 0,
> + .width = 4,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_qdss_dap_div_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_tsctr_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = &clk_regmap_div_ro_ops,
> + },
> +};
> +
> +static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {
> + .reg = 0x2c040,
> + .shift = 0,
> + .width = 2,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_usb0_mock_utmi_div_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_usb0_mock_utmi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_regmap_div_ro_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_adss_pwm_clk = {
> + .halt_reg = 0x1c00c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1c00c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_adss_pwm_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_adss_pwm_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ahb_clk = {
> + .halt_reg = 0x34024,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x34024,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_ahb_clk = {
> + .halt_reg = 0x1008,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0xb004,
> + .enable_mask = BIT(4),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> + .halt_reg = 0x2024,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2024,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_qup1_i2c_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> + .halt_reg = 0x2020,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2020,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_qup1_spi_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> + .halt_reg = 0x3024,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3024,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_qup2_i2c_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> + .halt_reg = 0x3020,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3020,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_qup2_spi_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> + .halt_reg = 0x4024,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x4024,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_qup3_i2c_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> + .halt_reg = 0x4020,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x4020,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_qup3_spi_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_sleep_clk = {
> + .halt_reg = 0x1010,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0xb004,
> + .enable_mask = BIT(5),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_sleep_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_sleep_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> + .halt_reg = 0x2040,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2040,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_uart1_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_blsp1_uart1_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> + .halt_reg = 0x3040,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3040,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_uart2_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_blsp1_uart2_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart3_apps_clk = {
> + .halt_reg = 0x4054,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x4054,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_blsp1_uart3_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_blsp1_uart3_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ce_ahb_clk = {
> + .halt_reg = 0x25074,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x25074,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_ce_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_div2_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ce_axi_clk = {
> + .halt_reg = 0x25068,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x25068,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_ce_axi_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ce_pcnoc_ahb_clk = {
> + .halt_reg = 0x25070,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x25070,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_ce_pcnoc_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
> + .halt_reg = 0x3a004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3a004,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_cmn_12gpll_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_cmn_12gpll_apu_clk = {
> + .halt_reg = 0x3a00c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3a00c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_cmn_12gpll_apu_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_cmn_12gpll_sys_clk = {
> + .halt_reg = 0x3a008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3a008,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_cmn_12gpll_sys_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_uniphy_sys_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp1_clk = {
> + .halt_reg = 0x8018,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x8018,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_gp1_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_gp1_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp2_clk = {
> + .halt_reg = 0x9018,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x9018,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_gp2_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_gp2_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_lpass_core_axim_clk = {
> + .halt_reg = 0x27018,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x27018,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_lpass_core_axim_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_lpass_sway_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_lpass_sway_clk = {
> + .halt_reg = 0x27014,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x27014,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_lpass_sway_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_lpass_sway_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mdio_ahb_clk = {
> + .halt_reg = 0x12004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x12004,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_mdio_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mdio_slave_ahb_clk = {
> + .halt_reg = 0x1200c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1200c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_mdio_slave_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mem_noc_q6_axi_clk = {
> + .halt_reg = 0x19010,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x19010,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_mem_noc_q6_axi_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_q6_axim_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mem_noc_ts_clk = {
> + .halt_reg = 0x19028,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x19028,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_mem_noc_ts_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_tsctr_div8_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nss_ts_clk = {
> + .halt_reg = 0x17018,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x17018,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nss_ts_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_nss_ts_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nsscc_clk = {
> + .halt_reg = 0x17034,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x17034,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nsscc_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nsscfg_clk = {
> + .halt_reg = 0x1702c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1702c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nsscfg_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nssnoc_atb_clk = {
> + .halt_reg = 0x17014,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x17014,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nssnoc_atb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nssnoc_nsscc_clk = {
> + .halt_reg = 0x17030,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x17030,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nssnoc_nsscc_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
> + .halt_reg = 0x1701c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1701c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nssnoc_qosgen_ref_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_xo_div4_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nssnoc_snoc_1_clk = {
> + .halt_reg = 0x1707c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1707c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nssnoc_snoc_1_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nssnoc_snoc_clk = {
> + .halt_reg = 0x17028,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x17028,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nssnoc_snoc_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
> + .halt_reg = 0x17020,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x17020,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nssnoc_timeout_ref_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_xo_div4_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
> + .halt_reg = 0x17074,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x17074,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nssnoc_xo_dcd_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_xo_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_0_ahb_clk = {
> + .halt_reg = 0x29030,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x29030,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_0_aux_clk = {
> + .halt_reg = 0x29070,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x29070,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_aux_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_0_axi_m_clk = {
> + .halt_reg = 0x29038,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x29038,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_axi_m_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_0_axi_s_bridge_clk = {
> + .halt_reg = 0x29048,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x29048,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_axi_s_bridge_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_0_axi_s_clk = {
> + .halt_reg = 0x29040,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x29040,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_axi_s_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
> + .halt_reg = 0x29068,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x29068,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_pipe_clk",
> + .parent_names = (const char *[]){
> + "pcie3x1_0_pipe_clk_src"
> + },
Nooo. No parent_names please.
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_1_ahb_clk = {
> + .halt_reg = 0x2a00c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2a00c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_1_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_1_aux_clk = {
> + .halt_reg = 0x2a070,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2a070,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_1_aux_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_1_axi_m_clk = {
> + .halt_reg = 0x2a014,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2a014,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_1_axi_m_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_1_axi_s_bridge_clk = {
> + .halt_reg = 0x2a024,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2a024,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_1_axi_s_bridge_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_1_axi_s_clk = {
> + .halt_reg = 0x2a01c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2a01c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_1_axi_s_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_1_pipe_clk = {
> + .halt_reg = 0x2a068,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x2a068,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_1_pipe_clk",
> + .parent_names = (const char *[]){
> + "pcie3x1_1_pipe_clk_src"
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x1_phy_ahb_clk = {
> + .halt_reg = 0x29078,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x29078,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_phy_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x2_ahb_clk = {
> + .halt_reg = 0x28030,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x28030,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x2_aux_clk = {
> + .halt_reg = 0x28070,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x28070,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_aux_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x2_axi_m_clk = {
> + .halt_reg = 0x28038,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x28038,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_axi_m_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x2_axi_m_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x2_axi_s_bridge_clk = {
> + .halt_reg = 0x28048,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x28048,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_axi_s_bridge_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x2_axi_s_clk = {
> + .halt_reg = 0x28040,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x28040,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_axi_s_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x2_phy_ahb_clk = {
> + .halt_reg = 0x28080,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x28080,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_phy_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcie3x2_pipe_clk = {
> + .halt_reg = 0x28068,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x28068,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x2_pipe_clk",
> + .parent_names = (const char *[]){
> + "pcie3x2_pipe_clk_src"
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcnoc_at_clk = {
> + .halt_reg = 0x31024,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x31024,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcnoc_at_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pcnoc_lpass_clk = {
> + .halt_reg = 0x31020,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x31020,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcnoc_lpass_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_lpass_sway_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_prng_ahb_clk = {
> + .halt_reg = 0x13024,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0xb004,
> + .enable_mask = BIT(10),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_prng_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_ahb_clk = {
> + .halt_reg = 0x25014,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x25014,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_q6_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_ahb_s_clk = {
> + .halt_reg = 0x25018,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x25018,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_q6_ahb_s_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_axim_clk = {
> + .halt_reg = 0x2500c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2500c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_q6_axim_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_q6_axim_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_axis_clk = {
> + .halt_reg = 0x25010,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x25010,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_q6_axis_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6_tsctr_1to2_clk = {
> + .halt_reg = 0x25020,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x25020,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_q6_tsctr_1to2_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_tsctr_div2_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6ss_atbm_clk = {
> + .halt_reg = 0x2501c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2501c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_q6ss_atbm_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6ss_pclkdbg_clk = {
> + .halt_reg = 0x25024,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x25024,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_q6ss_pclkdbg_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_dap_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_q6ss_trig_clk = {
> + .halt_reg = 0x250a0,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x250a0,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_q6ss_trig_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_dap_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_at_clk = {
> + .halt_reg = 0x2d038,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2d038,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qdss_at_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_cfg_ahb_clk = {
> + .halt_reg = 0x2d06c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2d06c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qdss_cfg_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_dap_ahb_clk = {
> + .halt_reg = 0x2d068,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2d068,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qdss_dap_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_dap_clk = {
> + .halt_reg = 0x2d05c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0xb004,
> + .enable_mask = BIT(2),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qdss_dap_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_dap_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_etr_usb_clk = {
> + .halt_reg = 0x2d064,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2d064,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qdss_etr_usb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
> + .mult = 1,
> + .div = 6,
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_eud_at_div_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_qdss_at_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_qdss_eud_at_clk = {
> + .halt_reg = 0x2d070,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2d070,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qdss_eud_at_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_eud_at_div_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qpic_ahb_clk = {
> + .halt_reg = 0x32010,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x32010,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qpic_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qpic_clk = {
> + .halt_reg = 0x32014,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x32014,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qpic_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qpic_io_macro_clk = {
> + .halt_reg = 0x3200c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3200c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qpic_io_macro_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qpic_io_macro_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qpic_sleep_clk = {
> + .halt_reg = 0x3201c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3201c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_qpic_sleep_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_sleep_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc1_ahb_clk = {
> + .halt_reg = 0x33034,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x33034,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_sdcc1_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc1_apps_clk = {
> + .halt_reg = 0x3302c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3302c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_sdcc1_apps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_sdcc1_apps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_lpass_cfg_clk = {
> + .halt_reg = 0x2e028,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e028,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_lpass_cfg_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_lpass_sway_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_nssnoc_1_clk = {
> + .halt_reg = 0x17090,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x17090,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_nssnoc_1_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_nssnoc_clk = {
> + .halt_reg = 0x17084,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x17084,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_nssnoc_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = {
> + .halt_reg = 0x2e050,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e050,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_pcie3_1lane_1_m_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_pcie3_1lane_1_s_clk = {
> + .halt_reg = 0x2e0ac,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e0ac,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_pcie3_1lane_1_s_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_1_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_pcie3_1lane_m_clk = {
> + .halt_reg = 0x2e080,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e080,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_pcie3_1lane_m_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_pcie3_1lane_s_clk = {
> + .halt_reg = 0x2e04c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e04c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_pcie3_1lane_s_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x1_0_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_pcie3_2lane_m_clk = {
> + .halt_reg = 0x2e07c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e07c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_pcie3_2lane_m_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x2_axi_m_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
> + .halt_reg = 0x2e048,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e048,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_pcie3_2lane_s_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcie3x2_axi_s_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_snoc_usb_clk = {
> + .halt_reg = 0x2e058,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2e058,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_snoc_usb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_usb0_master_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_at_clk = {
> + .halt_reg = 0x2e038,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2e038,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_sys_noc_at_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
> + .halt_reg = 0x2e030,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e030,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_sys_noc_wcss_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_uniphy0_ahb_clk = {
> + .halt_reg = 0x16010,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x16010,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_uniphy0_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_uniphy0_sys_clk = {
> + .halt_reg = 0x1600c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1600c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_uniphy0_sys_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_uniphy_sys_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_uniphy1_ahb_clk = {
> + .halt_reg = 0x1601c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1601c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_uniphy1_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_uniphy1_sys_clk = {
> + .halt_reg = 0x16018,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x16018,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_uniphy1_sys_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_uniphy_sys_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_aux_clk = {
> + .halt_reg = 0x2c050,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2c050,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_aux_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_usb0_aux_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_eud_at_clk = {
> + .halt_reg = 0x30004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x30004,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_eud_at_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_eud_at_div_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_lfps_clk = {
> + .halt_reg = 0x2c090,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2c090,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_lfps_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_usb0_lfps_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_master_clk = {
> + .halt_reg = 0x2c048,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2c048,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_master_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_usb0_master_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_mock_utmi_clk = {
> + .halt_reg = 0x2c054,
> + .clkr = {
> + .enable_reg = 0x2c054,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_mock_utmi_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_usb0_mock_utmi_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
> + .halt_reg = 0x2c05c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2c05c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_phy_cfg_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_pipe_clk = {
> + .halt_reg = 0x2c078,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x2c078,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_pipe_clk",
> + .parent_names = (const char *[]){
> + "usb0_pipe_clk_src"
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb0_sleep_clk = {
> + .halt_reg = 0x2c058,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x2c058,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_usb0_sleep_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_sleep_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_axim_clk = {
> + .halt_reg = 0x2505c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2505c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_axim_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_axis_clk = {
> + .halt_reg = 0x25060,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x25060,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_axis_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {
> + .halt_reg = 0x25048,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x25048,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_dbg_ifc_apb_bdg_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_dap_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
> + .halt_reg = 0x25038,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x25038,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_dbg_ifc_apb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_dap_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {
> + .halt_reg = 0x2504c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2504c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_dbg_ifc_atb_bdg_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
> + .halt_reg = 0x2503c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2503c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_dbg_ifc_atb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_at_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {
> + .halt_reg = 0x25050,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x25050,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_dbg_ifc_nts_bdg_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_tsctr_div2_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
> + .halt_reg = 0x25040,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x25040,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_dbg_ifc_nts_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_qdss_tsctr_div2_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_ecahb_clk = {
> + .halt_reg = 0x25058,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x25058,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_ecahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_wcss_ahb_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_mst_async_bdg_clk = {
> + .halt_reg = 0x2e0b0,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e0b0,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_mst_async_bdg_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_wcss_slv_async_bdg_clk = {
> + .halt_reg = 0x2e0b4,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2e0b4,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_wcss_slv_async_bdg_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_system_noc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_xo_clk = {
> + .halt_reg = 0x34018,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x34018,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_xo_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_xo_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_xo_div4_clk = {
> + .halt_reg = 0x3401c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3401c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_xo_div4_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_xo_div4_clk_src.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_im_sleep_clk = {
> + .halt_reg = 0x34020,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x34020,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_im_sleep_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_sleep_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
> + .halt_reg = 0x17080,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x17080,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_nssnoc_pcnoc_1_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mem_noc_ahb_clk = {
> + .halt_reg = 0x1900c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1900c,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_mem_noc_ahb_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_pcnoc_bfdcd_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mem_noc_apss_axi_clk = {
> + .halt_reg = 0x1901c,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0xb004,
> + .enable_mask = BIT(6),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_mem_noc_apss_axi_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_apss_axi_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {
> + .reg = 0x2e010,
> + .shift = 0,
> + .width = 2,
> + .clkr.hw.init = &(const struct clk_init_data) {
> + .name = "gcc_snoc_qosgen_extref_div_clk_src",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_xo_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_regmap_div_ro_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_mem_noc_qosgen_extref_clk = {
> + .halt_reg = 0x19024,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x19024,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_mem_noc_qosgen_extref_clk",
> + .parent_hws = (const struct clk_hw*[]){
> + &gcc_snoc_qosgen_extref_div_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_regmap *gcc_ipq5332_clocks[] = {
> + [GPLL0_MAIN] = &gpll0_main.clkr,
> + [GPLL0] = &gpll0.clkr,
> + [GPLL2_MAIN] = &gpll2_main.clkr,
> + [GPLL2] = &gpll2.clkr,
> + [GPLL4_MAIN] = &gpll4_main.clkr,
> + [GPLL4] = &gpll4.clkr,
> + [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
> + [GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,
> + [GCC_AHB_CLK] = &gcc_ahb_clk.clkr,
> + [GCC_APSS_AXI_CLK_SRC] = &gcc_apss_axi_clk_src.clkr,
> + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
> + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,
> + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,
> + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,
> + [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
> + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
> + [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,
> + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
> + [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,
> + [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
> + [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,
> + [GCC_CE_AHB_CLK] = &gcc_ce_ahb_clk.clkr,
> + [GCC_CE_AXI_CLK] = &gcc_ce_axi_clk.clkr,
> + [GCC_CE_PCNOC_AHB_CLK] = &gcc_ce_pcnoc_ahb_clk.clkr,
> + [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
> + [GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
> + [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
> + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
> + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
> + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
> + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
> + [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,
> + [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,
> + [GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,
> + [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
> + [GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,
> + [GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
> + [GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
> + [GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
> + [GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,
> + [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
> + [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
> + [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
> + [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
> + [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
> + [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
> + [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
> + [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
> + [GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
> + [GCC_PCIE3X1_0_AHB_CLK] = &gcc_pcie3x1_0_ahb_clk.clkr,
> + [GCC_PCIE3X1_0_AUX_CLK] = &gcc_pcie3x1_0_aux_clk.clkr,
> + [GCC_PCIE3X1_0_AXI_CLK_SRC] = &gcc_pcie3x1_0_axi_clk_src.clkr,
> + [GCC_PCIE3X1_0_AXI_M_CLK] = &gcc_pcie3x1_0_axi_m_clk.clkr,
> + [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_0_axi_s_bridge_clk.clkr,
> + [GCC_PCIE3X1_0_AXI_S_CLK] = &gcc_pcie3x1_0_axi_s_clk.clkr,
> + [GCC_PCIE3X1_0_PIPE_CLK] = &gcc_pcie3x1_0_pipe_clk.clkr,
> + [GCC_PCIE3X1_0_RCHG_CLK] = &gcc_pcie3x1_0_rchg_clk.clkr,
> + [GCC_PCIE3X1_0_RCHG_CLK_SRC] = &gcc_pcie3x1_0_rchg_clk_src.clkr,
> + [GCC_PCIE3X1_1_AHB_CLK] = &gcc_pcie3x1_1_ahb_clk.clkr,
> + [GCC_PCIE3X1_1_AUX_CLK] = &gcc_pcie3x1_1_aux_clk.clkr,
> + [GCC_PCIE3X1_1_AXI_CLK_SRC] = &gcc_pcie3x1_1_axi_clk_src.clkr,
> + [GCC_PCIE3X1_1_AXI_M_CLK] = &gcc_pcie3x1_1_axi_m_clk.clkr,
> + [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_1_axi_s_bridge_clk.clkr,
> + [GCC_PCIE3X1_1_AXI_S_CLK] = &gcc_pcie3x1_1_axi_s_clk.clkr,
> + [GCC_PCIE3X1_1_PIPE_CLK] = &gcc_pcie3x1_1_pipe_clk.clkr,
> + [GCC_PCIE3X1_1_RCHG_CLK] = &gcc_pcie3x1_1_rchg_clk.clkr,
> + [GCC_PCIE3X1_1_RCHG_CLK_SRC] = &gcc_pcie3x1_1_rchg_clk_src.clkr,
> + [GCC_PCIE3X1_PHY_AHB_CLK] = &gcc_pcie3x1_phy_ahb_clk.clkr,
> + [GCC_PCIE3X2_AHB_CLK] = &gcc_pcie3x2_ahb_clk.clkr,
> + [GCC_PCIE3X2_AUX_CLK] = &gcc_pcie3x2_aux_clk.clkr,
> + [GCC_PCIE3X2_AXI_M_CLK] = &gcc_pcie3x2_axi_m_clk.clkr,
> + [GCC_PCIE3X2_AXI_M_CLK_SRC] = &gcc_pcie3x2_axi_m_clk_src.clkr,
> + [GCC_PCIE3X2_AXI_S_BRIDGE_CLK] = &gcc_pcie3x2_axi_s_bridge_clk.clkr,
> + [GCC_PCIE3X2_AXI_S_CLK] = &gcc_pcie3x2_axi_s_clk.clkr,
> + [GCC_PCIE3X2_AXI_S_CLK_SRC] = &gcc_pcie3x2_axi_s_clk_src.clkr,
> + [GCC_PCIE3X2_PHY_AHB_CLK] = &gcc_pcie3x2_phy_ahb_clk.clkr,
> + [GCC_PCIE3X2_PIPE_CLK] = &gcc_pcie3x2_pipe_clk.clkr,
> + [GCC_PCIE3X2_RCHG_CLK] = &gcc_pcie3x2_rchg_clk.clkr,
> + [GCC_PCIE3X2_RCHG_CLK_SRC] = &gcc_pcie3x2_rchg_clk_src.clkr,
> + [GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,
> + [GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
> + [GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,
> + [GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,
> + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
> + [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
> + [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
> + [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
> + [GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr,
> + [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,
> + [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
> + [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
> + [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
> + [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
> + [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
> + [GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,
> + [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
> + [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
> + [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
> + [GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr,
> + [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
> + [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
> + [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
> + [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
> + [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
> + [GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,
> + [GCC_QPIC_SLEEP_CLK] = &gcc_qpic_sleep_clk.clkr,
> + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
> + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
> + [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
> + [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
> + [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,
> + [GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr,
> + [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,
> + [GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr,
> + [GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr,
> + [GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr,
> + [GCC_SNOC_PCIE3_1LANE_S_CLK] = &gcc_snoc_pcie3_1lane_s_clk.clkr,
> + [GCC_SNOC_PCIE3_2LANE_M_CLK] = &gcc_snoc_pcie3_2lane_m_clk.clkr,
> + [GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
> + [GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
> + [GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
> + [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
> + [GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,
> + [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
> + [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
> + [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
> + [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
> + [GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,
> + [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
> + [GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,
> + [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
> + [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,
> + [GCC_USB0_LFPS_CLK_SRC] = &gcc_usb0_lfps_clk_src.clkr,
> + [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
> + [GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,
> + [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
> + [GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,
> + [GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,
> + [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
> + [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
> + [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
> + [GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,
> + [GCC_WCSS_AXIM_CLK] = &gcc_wcss_axim_clk.clkr,
> + [GCC_WCSS_AXIS_CLK] = &gcc_wcss_axis_clk.clkr,
> + [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,
> + [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
> + [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,
> + [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
> + [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,
> + [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
> + [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
> + [GCC_WCSS_MST_ASYNC_BDG_CLK] = &gcc_wcss_mst_async_bdg_clk.clkr,
> + [GCC_WCSS_SLV_ASYNC_BDG_CLK] = &gcc_wcss_slv_async_bdg_clk.clkr,
> + [GCC_XO_CLK] = &gcc_xo_clk.clkr,
> + [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
> + [GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
> + [GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,
> + [GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
> + [GCC_MEM_NOC_AHB_CLK] = &gcc_mem_noc_ahb_clk.clkr,
> + [GCC_MEM_NOC_APSS_AXI_CLK] = &gcc_mem_noc_apss_axi_clk.clkr,
> + [GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,
> + [GCC_MEM_NOC_QOSGEN_EXTREF_CLK] = &gcc_mem_noc_qosgen_extref_clk.clkr,
> + [GCC_PCIE3X2_PIPE_CLK_SRC] = &pcie3x2_pipe_clk_src.clkr,
> + [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &pcie3x1_0_pipe_clk_src.clkr,
> + [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &pcie3x1_1_pipe_clk_src.clkr,
> + [GCC_USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
> +};
> +
> +static const struct qcom_reset_map gcc_ipq5332_resets[] = {
> + [GCC_ADSS_BCR] = { 0x1c000 },
> + [GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 },
> + [GCC_AHB_CLK_ARES] = { 0x34024, 2 },
> + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
> + [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 },
> + [GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 },
> + [GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 },
> + [GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 },
> + [GCC_BLSP1_BCR] = { 0x1000 },
> + [GCC_BLSP1_QUP1_BCR] = { 0x2000 },
> + [GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 },
> + [GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 },
> + [GCC_BLSP1_QUP2_BCR] = { 0x3000 },
> + [GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 },
> + [GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 },
> + [GCC_BLSP1_QUP3_BCR] = { 0x4000 },
> + [GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 },
> + [GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 },
> + [GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 },
> + [GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 },
> + [GCC_BLSP1_UART1_BCR] = { 0x2028 },
> + [GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 },
> + [GCC_BLSP1_UART2_BCR] = { 0x3028 },
> + [GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 },
> + [GCC_BLSP1_UART3_BCR] = { 0x4028 },
> + [GCC_CE_BCR] = { 0x18008 },
> + [GCC_CMN_BLK_BCR] = { 0x3a000 },
> + [GCC_CMN_LDO0_BCR] = { 0x1d000 },
> + [GCC_CMN_LDO1_BCR] = { 0x1d008 },
> + [GCC_DCC_BCR] = { 0x35000 },
> + [GCC_GP1_CLK_ARES] = { 0x8018, 2 },
> + [GCC_GP2_CLK_ARES] = { 0x9018, 2 },
> + [GCC_LPASS_BCR] = { 0x27000 },
> + [GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 },
> + [GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 },
> + [GCC_MDIOM_BCR] = { 0x12000 },
> + [GCC_MDIOS_BCR] = { 0x12008 },
> + [GCC_NSS_BCR] = { 0x17000 },
> + [GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 },
> + [GCC_NSSCC_CLK_ARES] = { 0x17034, 2 },
> + [GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 },
> + [GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 },
> + [GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 },
> + [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 },
> + [GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 },
> + [GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 },
> + [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 },
> + [GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 },
> + [GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 },
> + [GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 },
> + [GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 },
> + [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 },
> + [GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 },
> + [GCC_PCIE3X1_0_BCR] = { 0x29000 },
> + [GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 },
> + [GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 },
> + [GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c },
> + [GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 },
> + [GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 },
> + [GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 },
> + [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 },
> + [GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 },
> + [GCC_PCIE3X1_1_BCR] = { 0x2a000 },
> + [GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 },
> + [GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 },
> + [GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c },
> + [GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 },
> + [GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 },
> + [GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 },
> + [GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 },
> + [GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 },
> + [GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 },
> + [GCC_PCIE3X2_BCR] = { 0x28000 },
> + [GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 },
> + [GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 },
> + [GCC_PCIE3X2_PHY_BCR] = { 0x28060 },
> + [GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c },
> + [GCC_PCNOC_BCR] = { 0x31000 },
> + [GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 },
> + [GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 },
> + [GCC_PRNG_BCR] = { 0x13020 },
> + [GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 },
> + [GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 },
> + [GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 },
> + [GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 },
> + [GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 },
> + [GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 },
> + [GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 },
> + [GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 },
> + [GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 },
> + [GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 },
> + [GCC_QDSS_BCR] = { 0x2d000 },
> + [GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 },
> + [GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 },
> + [GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 },
> + [GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 },
> + [GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 },
> + [GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 },
> + [GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 },
> + [GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 },
> + [GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 },
> + [GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 },
> + [GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 },
> + [GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 },
> + [GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 },
> + [GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 },
> + [GCC_QPIC_CLK_ARES] = { 0x32014, 2 },
> + [GCC_QPIC_BCR] = { 0x32000 },
> + [GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 },
> + [GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 },
> + [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
> + [GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 },
> + [GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 },
> + [GCC_SDCC_BCR] = { 0x33000 },
> + [GCC_SNOC_BCR] = { 0x2e000 },
> + [GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 },
> + [GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 },
> + [GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 },
> + [GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 },
> + [GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 },
> + [GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 },
> + [GCC_UNIPHY0_BCR] = { 0x16000 },
> + [GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 },
> + [GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 },
> + [GCC_UNIPHY1_BCR] = { 0x16014 },
> + [GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 },
> + [GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 },
> + [GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 },
> + [GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 },
> + [GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 },
> + [GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 },
> + [GCC_USB0_PHY_BCR] = { 0x2c06c },
> + [GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 },
> + [GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 },
> + [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
> + [GCC_USB_BCR] = { 0x2c000 },
> + [GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 },
> + [GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 },
> + [GCC_WCSS_BCR] = { 0x18004 },
> + [GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 },
> + [GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 },
> + [GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 },
> + [GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 },
> + [GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 },
> + [GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 },
> + [GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 },
> + [GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 },
> + [GCC_WCSS_Q6_BCR] = { 0x18000 },
> + [GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 },
> + [GCC_XO_CLK_ARES] = { 0x34018, 2 },
> + [GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 },
> + [GCC_Q6SS_DBG_ARES] = { 0x25094 },
> + [GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 },
> + [GCC_WCSS_DBG_ARES] = { 0x25098, 1 },
> + [GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 },
> + [GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 },
> + [GCC_WCSSAON_ARES] = { 0x2509C },
> + [GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 },
> + [GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 },
> + [GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 },
> + [GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 },
> + [GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 },
> + [GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 },
> + [GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 },
> + [GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 },
> + [GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 },
> + [GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 },
> + [GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
> + [GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 },
> + [GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 },
> + [GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 },
> + [GCC_UNIPHY0_XPCS_ARES] = { 0x16050 },
> + [GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
> +};
> +
> +static const struct regmap_config gcc_ipq5332_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x3f024,
> + .fast_io = true,
> +};
> +
> +static struct clk_hw *gcc_ipq5332_hws[] = {
> + &gpll0_div2.hw,
> + &gcc_xo_div4_clk_src.hw,
> + &gcc_system_noc_bfdcd_div2_clk_src.hw,
> + &gcc_qdss_tsctr_div2_clk_src.hw,
> + &gcc_qdss_tsctr_div3_clk_src.hw,
> + &gcc_qdss_tsctr_div4_clk_src.hw,
> + &gcc_qdss_tsctr_div8_clk_src.hw,
> + &gcc_qdss_tsctr_div16_clk_src.hw,
> + &gcc_eud_at_div_clk_src.hw,
> +};
> +
> +static const struct qcom_cc_desc gcc_ipq5332_desc = {
> + .config = &gcc_ipq5332_regmap_config,
> + .clks = gcc_ipq5332_clocks,
> + .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
> + .resets = gcc_ipq5332_resets,
> + .num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
> + .clk_hws = gcc_ipq5332_hws,
> + .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
> +};
> +
> +static int gcc_ipq5332_probe(struct platform_device *pdev)
> +{
> + return qcom_cc_probe(pdev, &gcc_ipq5332_desc);
> +}
> +
> +static const struct of_device_id gcc_ipq5332_match_table[] = {
> + { .compatible = "qcom,ipq5332-gcc" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, gcc_ipq5332_match_table);
> +
> +static struct platform_driver gcc_ipq5332_driver = {
> + .probe = gcc_ipq5332_probe,
> + .driver = {
> + .name = "gcc-ipq5332",
> + .of_match_table = gcc_ipq5332_match_table,
> + },
> +};
> +
> +static int __init gcc_ipq5332_init(void)
> +{
> + return platform_driver_register(&gcc_ipq5332_driver);
> +}
> +core_initcall(gcc_ipq5332_init);
> +
> +static void __exit gcc_ipq5332_exit(void)
> +{
> + platform_driver_unregister(&gcc_ipq5332_driver);
> +}
> +module_exit(gcc_ipq5332_exit);
> +
> +MODULE_DESCRIPTION("QTI GCC IPQ5332 Driver");
> +MODULE_LICENSE("GPL");
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 9/9] arm64: defconfig: Enable IPQ5332 SoC base configs
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 9:53 ` Dmitry Baryshkov
-1 siblings, 0 replies; 48+ messages in thread
From: Dmitry Baryshkov @ 2023-02-06 9:53 UTC (permalink / raw)
To: Kathiravan T, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 09:12, Kathiravan T wrote:
> Enable the clock and pinctrl configs for Qualcomm IPQ5332 SoC
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 9/9] arm64: defconfig: Enable IPQ5332 SoC base configs
@ 2023-02-06 9:53 ` Dmitry Baryshkov
0 siblings, 0 replies; 48+ messages in thread
From: Dmitry Baryshkov @ 2023-02-06 9:53 UTC (permalink / raw)
To: Kathiravan T, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 09:12, Kathiravan T wrote:
> Enable the clock and pinctrl configs for Qualcomm IPQ5332 SoC
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
2023-02-06 7:12 ` [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Kathiravan T
@ 2023-02-06 9:56 ` Dmitry Baryshkov
2023-02-06 9:56 ` Dmitry Baryshkov
2023-02-07 3:41 ` Bjorn Andersson
2 siblings, 0 replies; 48+ messages in thread
From: Dmitry Baryshkov @ 2023-02-06 9:56 UTC (permalink / raw)
To: Kathiravan T, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 09:12, Kathiravan T wrote:
> Add support for the global clock controller found on IPQ5332 SoC.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
> Changes in V3:
> - As I mentined the bindings, changes need to be done in V2 got
> missed out and same has been done in V3, to call out
> specifically dropped the CLK_IS_CRITICAL and dropped the
> gcc_apss_ahb_clk, its source clock and gcc_apss_axi_clk
> - Used gcc_parent_data_xo wherever applicable and dropped the
> duplicate entries
> - dropped the unused parent_map_10 and parent_data_10
> - Used qcom_cc_probe instead of qcom_cc_really_probe
> Changes in V2:
> - Added the 'dependes on' for Kconfig symbol
> - Dropped the CLK_IS_CRITICAL flag throughout the file
> - Dropped the gcc_apss_ahb_clk and gcc_apss_axi_clk as these are
> managed by bootloaders
[skipped]
> +static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
> + F(2000000, P_XO, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pcie_aux_clk_src = {
> + .cmd_rcgr = 0x28004,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_6,
> + .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie_aux_clk_src",
> + .parent_data = gcc_parent_data_6,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_mux pcie3x2_pipe_clk_src = {
> + .reg = 0x28064,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_14,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie3x2_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_14,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_14),
> + .ops = &clk_regmap_mux_closest_ops,
Should we use clk_regmap_phy_mux_ops here instead?
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux pcie3x1_0_pipe_clk_src = {
> + .reg = 0x29064,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_15,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie3x1_0_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_15,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_15),
> + .ops = &clk_regmap_mux_closest_ops,
And clk_regmap_phy_mux_ops here too?
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux pcie3x1_1_pipe_clk_src = {
> + .reg = 0x2A064,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_16,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie3x1_1_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_16,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_16),
> + .ops = &clk_regmap_mux_closest_ops,
And here?
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
[skipped]
> +
> +static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
> + .halt_reg = 0x29068,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x29068,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_pipe_clk",
> + .parent_names = (const char *[]){
> + "pcie3x1_0_pipe_clk_src"
> + },
Nooo. No parent_names please. You have several of them in the driver
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
@ 2023-02-06 9:56 ` Dmitry Baryshkov
0 siblings, 0 replies; 48+ messages in thread
From: Dmitry Baryshkov @ 2023-02-06 9:56 UTC (permalink / raw)
To: Kathiravan T, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 06/02/2023 09:12, Kathiravan T wrote:
> Add support for the global clock controller found on IPQ5332 SoC.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> ---
> Changes in V3:
> - As I mentined the bindings, changes need to be done in V2 got
> missed out and same has been done in V3, to call out
> specifically dropped the CLK_IS_CRITICAL and dropped the
> gcc_apss_ahb_clk, its source clock and gcc_apss_axi_clk
> - Used gcc_parent_data_xo wherever applicable and dropped the
> duplicate entries
> - dropped the unused parent_map_10 and parent_data_10
> - Used qcom_cc_probe instead of qcom_cc_really_probe
> Changes in V2:
> - Added the 'dependes on' for Kconfig symbol
> - Dropped the CLK_IS_CRITICAL flag throughout the file
> - Dropped the gcc_apss_ahb_clk and gcc_apss_axi_clk as these are
> managed by bootloaders
[skipped]
> +static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
> + F(2000000, P_XO, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_pcie_aux_clk_src = {
> + .cmd_rcgr = 0x28004,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_6,
> + .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
> + .clkr.hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie_aux_clk_src",
> + .parent_data = gcc_parent_data_6,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_regmap_mux pcie3x2_pipe_clk_src = {
> + .reg = 0x28064,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_14,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie3x2_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_14,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_14),
> + .ops = &clk_regmap_mux_closest_ops,
Should we use clk_regmap_phy_mux_ops here instead?
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux pcie3x1_0_pipe_clk_src = {
> + .reg = 0x29064,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_15,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie3x1_0_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_15,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_15),
> + .ops = &clk_regmap_mux_closest_ops,
And clk_regmap_phy_mux_ops here too?
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
> +static struct clk_regmap_mux pcie3x1_1_pipe_clk_src = {
> + .reg = 0x2A064,
> + .shift = 8,
> + .width = 2,
> + .parent_map = gcc_parent_map_16,
> + .clkr = {
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie3x1_1_phy_pipe_clk_src",
> + .parent_data = gcc_parent_data_16,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_16),
> + .ops = &clk_regmap_mux_closest_ops,
And here?
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> +};
> +
[skipped]
> +
> +static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
> + .halt_reg = 0x29068,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x29068,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
> + .name = "gcc_pcie3x1_0_pipe_clk",
> + .parent_names = (const char *[]){
> + "pcie3x1_0_pipe_clk_src"
> + },
Nooo. No parent_names please. You have several of them in the driver
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 0/9] Add minimal boot support for IPQ5332
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-06 11:25 ` Linus Walleij
-1 siblings, 0 replies; 48+ messages in thread
From: Linus Walleij @ 2023-02-06 11:25 UTC (permalink / raw)
To: Kathiravan T
Cc: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, catalin.marinas, will,
shawnguo, arnd, dmitry.baryshkov, marcel.ziswiler, nfraprado,
robimarko, quic_gurus, linux-arm-msm, devicetree, linux-kernel,
linux-clk, linux-gpio, linux-arm-kernel, quic_varada,
quic_srichara
Hi Kathiravan,
thanks for your patches!
On Mon, Feb 6, 2023 at 8:12 AM Kathiravan T <quic_kathirav@quicinc.com> wrote:
> Kathiravan T (9):
> dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
> pinctrl: qcom: Introduce IPQ5332 TLMM driver
I have applied these two patches to the pin control tree for v6.3.
I see no reason to wait for more review since Krzysztof acked the
bindings and the driver isn't invasive at all, any problems can certainly
be fixed up in-tree.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 0/9] Add minimal boot support for IPQ5332
@ 2023-02-06 11:25 ` Linus Walleij
0 siblings, 0 replies; 48+ messages in thread
From: Linus Walleij @ 2023-02-06 11:25 UTC (permalink / raw)
To: Kathiravan T
Cc: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, catalin.marinas, will,
shawnguo, arnd, dmitry.baryshkov, marcel.ziswiler, nfraprado,
robimarko, quic_gurus, linux-arm-msm, devicetree, linux-kernel,
linux-clk, linux-gpio, linux-arm-kernel, quic_varada,
quic_srichara
Hi Kathiravan,
thanks for your patches!
On Mon, Feb 6, 2023 at 8:12 AM Kathiravan T <quic_kathirav@quicinc.com> wrote:
> Kathiravan T (9):
> dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
> pinctrl: qcom: Introduce IPQ5332 TLMM driver
I have applied these two patches to the pin control tree for v6.3.
I see no reason to wait for more review since Krzysztof acked the
bindings and the driver isn't invasive at all, any problems can certainly
be fixed up in-tree.
Yours,
Linus Walleij
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 0/9] Add minimal boot support for IPQ5332
2023-02-06 11:25 ` Linus Walleij
@ 2023-02-06 11:42 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 11:42 UTC (permalink / raw)
To: Linus Walleij
Cc: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, catalin.marinas, will,
shawnguo, arnd, dmitry.baryshkov, marcel.ziswiler, nfraprado,
robimarko, quic_gurus, linux-arm-msm, devicetree, linux-kernel,
linux-clk, linux-gpio, linux-arm-kernel, quic_varada,
quic_srichara
On 2/6/2023 4:55 PM, Linus Walleij wrote:
> Hi Kathiravan,
>
> thanks for your patches!
>
> On Mon, Feb 6, 2023 at 8:12 AM Kathiravan T <quic_kathirav@quicinc.com> wrote:
>
>> Kathiravan T (9):
>> dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
>> pinctrl: qcom: Introduce IPQ5332 TLMM driver
> I have applied these two patches to the pin control tree for v6.3.
Thanks a lot Linus!
>
> I see no reason to wait for more review since Krzysztof acked the
> bindings and the driver isn't invasive at all, any problems can certainly
> be fixed up in-tree.
>
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 0/9] Add minimal boot support for IPQ5332
@ 2023-02-06 11:42 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-06 11:42 UTC (permalink / raw)
To: Linus Walleij
Cc: krzysztof.kozlowski, agross, andersson, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, catalin.marinas, will,
shawnguo, arnd, dmitry.baryshkov, marcel.ziswiler, nfraprado,
robimarko, quic_gurus, linux-arm-msm, devicetree, linux-kernel,
linux-clk, linux-gpio, linux-arm-kernel, quic_varada,
quic_srichara
On 2/6/2023 4:55 PM, Linus Walleij wrote:
> Hi Kathiravan,
>
> thanks for your patches!
>
> On Mon, Feb 6, 2023 at 8:12 AM Kathiravan T <quic_kathirav@quicinc.com> wrote:
>
>> Kathiravan T (9):
>> dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
>> pinctrl: qcom: Introduce IPQ5332 TLMM driver
> I have applied these two patches to the pin control tree for v6.3.
Thanks a lot Linus!
>
> I see no reason to wait for more review since Krzysztof acked the
> bindings and the driver isn't invasive at all, any problems can certainly
> be fixed up in-tree.
>
> Yours,
> Linus Walleij
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 2/9] pinctrl: qcom: Introduce IPQ5332 TLMM driver
2023-02-06 7:12 ` Kathiravan T
@ 2023-02-07 3:34 ` Bjorn Andersson
-1 siblings, 0 replies; 48+ messages in thread
From: Bjorn Andersson @ 2023-02-07 3:34 UTC (permalink / raw)
To: Kathiravan T
Cc: krzysztof.kozlowski, agross, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel, quic_varada, quic_srichara
On Mon, Feb 06, 2023 at 12:42:10PM +0530, Kathiravan T wrote:
> The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm
> platforms, so add a driver for it.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 2/9] pinctrl: qcom: Introduce IPQ5332 TLMM driver
@ 2023-02-07 3:34 ` Bjorn Andersson
0 siblings, 0 replies; 48+ messages in thread
From: Bjorn Andersson @ 2023-02-07 3:34 UTC (permalink / raw)
To: Kathiravan T
Cc: krzysztof.kozlowski, agross, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel, quic_varada, quic_srichara
On Mon, Feb 06, 2023 at 12:42:10PM +0530, Kathiravan T wrote:
> The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm
> platforms, so add a driver for it.
>
> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
2023-02-06 7:12 ` [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Kathiravan T
@ 2023-02-07 3:41 ` Bjorn Andersson
2023-02-06 9:56 ` Dmitry Baryshkov
2023-02-07 3:41 ` Bjorn Andersson
2 siblings, 0 replies; 48+ messages in thread
From: Bjorn Andersson @ 2023-02-07 3:41 UTC (permalink / raw)
To: Kathiravan T
Cc: krzysztof.kozlowski, agross, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel, quic_varada, quic_srichara
On Mon, Feb 06, 2023 at 12:42:13PM +0530, Kathiravan T wrote:
> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
[..]
> +
> +enum {
> + DT_SLEEP_CLK,
> + DT_XO,
> + DT_PCIE_2LANE_PHY_PIPE_CLK,
> + DT_PCIE_2LANE_PHY_PIPE_X1_CLK,
> + DT_USB_PCIE_WRAPPER_PIPE_CLK,
This list does not match the clocks as defined in the binding.
> +};
> +
> +enum {
> + P_PCIE3X2_PIPE,
> + P_PCIE3X1_0_PIPE,
> + P_PCIE3X1_1_PIPE,
> + P_USB3PHY_0_PIPE,
> + P_CORE_BI_PLL_TEST_SE,
> + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
> + P_GPLL0_OUT_AUX,
> + P_GPLL0_OUT_MAIN,
> + P_GPLL2_OUT_AUX,
> + P_GPLL2_OUT_MAIN,
> + P_GPLL4_OUT_AUX,
> + P_GPLL4_OUT_MAIN,
> + P_SLEEP_CLK,
> + P_XO,
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
> +
> +static struct clk_alpha_pll gpll0_main = {
> + .offset = 0x20000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
> + .clkr = {
> + .enable_reg = 0xb000,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
Please add a space between ')' and '{ on all these.
> + .name = "gpll0_main",
> + .parent_data = &gcc_parent_data_xo,
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_stromer_ops,
> + },
> + },
> +};
[..]
> +static const struct qcom_cc_desc gcc_ipq5332_desc = {
> + .config = &gcc_ipq5332_regmap_config,
> + .clks = gcc_ipq5332_clocks,
> + .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
> + .resets = gcc_ipq5332_resets,
> + .num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
> + .clk_hws = gcc_ipq5332_hws,
> + .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
No GDSCs?
Regards,
Bjorn
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
@ 2023-02-07 3:41 ` Bjorn Andersson
0 siblings, 0 replies; 48+ messages in thread
From: Bjorn Andersson @ 2023-02-07 3:41 UTC (permalink / raw)
To: Kathiravan T
Cc: krzysztof.kozlowski, agross, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel, quic_varada, quic_srichara
On Mon, Feb 06, 2023 at 12:42:13PM +0530, Kathiravan T wrote:
> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
[..]
> +
> +enum {
> + DT_SLEEP_CLK,
> + DT_XO,
> + DT_PCIE_2LANE_PHY_PIPE_CLK,
> + DT_PCIE_2LANE_PHY_PIPE_X1_CLK,
> + DT_USB_PCIE_WRAPPER_PIPE_CLK,
This list does not match the clocks as defined in the binding.
> +};
> +
> +enum {
> + P_PCIE3X2_PIPE,
> + P_PCIE3X1_0_PIPE,
> + P_PCIE3X1_1_PIPE,
> + P_USB3PHY_0_PIPE,
> + P_CORE_BI_PLL_TEST_SE,
> + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
> + P_GPLL0_OUT_AUX,
> + P_GPLL0_OUT_MAIN,
> + P_GPLL2_OUT_AUX,
> + P_GPLL2_OUT_MAIN,
> + P_GPLL4_OUT_AUX,
> + P_GPLL4_OUT_MAIN,
> + P_SLEEP_CLK,
> + P_XO,
> +};
> +
> +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
> +
> +static struct clk_alpha_pll gpll0_main = {
> + .offset = 0x20000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
> + .clkr = {
> + .enable_reg = 0xb000,
> + .enable_mask = BIT(0),
> + .hw.init = &(const struct clk_init_data){
Please add a space between ')' and '{ on all these.
> + .name = "gpll0_main",
> + .parent_data = &gcc_parent_data_xo,
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_stromer_ops,
> + },
> + },
> +};
[..]
> +static const struct qcom_cc_desc gcc_ipq5332_desc = {
> + .config = &gcc_ipq5332_regmap_config,
> + .clks = gcc_ipq5332_clocks,
> + .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
> + .resets = gcc_ipq5332_resets,
> + .num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
> + .clk_hws = gcc_ipq5332_hws,
> + .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
No GDSCs?
Regards,
Bjorn
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
2023-02-06 9:52 ` Dmitry Baryshkov
@ 2023-02-07 4:26 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-07 4:26 UTC (permalink / raw)
To: Dmitry Baryshkov, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
Thanks Dmirty for taking time to review the patch.
On 2/6/2023 3:22 PM, Dmitry Baryshkov wrote:
> On 06/02/2023 09:12, Kathiravan T wrote:
>> Add binding for the Qualcomm IPQ5332 Global Clock Controller.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>> Changes in V3:
>> - Actually I missed to remove the clocks in V2 which are supposed to
>> be removed. In V3 I have removed those and they are
>> GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK
>> - For the same, didn't add the Reviewed-By tags from Stephen and
>> Krzysztof
>>
>> Changes in V2:
>> - property 'clocks' is marked required
>> - Renamed the include file name to match with compatible
>>
>> .../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++
>> include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++
>> 2 files changed, 417 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
>>
>> diff --git
>> a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> new file mode 100644
>> index 000000000000..961311af400c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> @@ -0,0 +1,61 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Global Clock & Reset Controller on IPQ5332
>> +
>> +maintainers:
>> + - Stephen Boyd <sboyd@kernel.org>
>> +
>> +description: |
>> + Qualcomm global clock control module provides the clocks, resets
>> and power
>> + domains on IPQ5332.
>> +
>> + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
>> +
>> +allOf:
>> + - $ref: qcom,gcc.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: qcom,ipq5332-gcc
>> +
>> + clocks:
>> + items:
>> + - description: Board XO clock source
>> + - description: Sleep clock source
>> + - description: PCIE 2lane PHY pipe clock source
>> + - description: PCIE 2lane x1 PHY pipe clock source (For second
>> lane)
>> + - description: USB PCIE wrapper pipe clock source
>> +
>> + clock-names:
>> + items:
>> + - const: xo
>> + - const: sleep_clk
>> + - const: pcie_2lane_phy_pipe_clk
>> + - const: pcie_2lane_phy_pipe_clk_x1
>> + - const: usb_pcie_wrapper_pipe_clk
>
> pcie3x1_0_pipe_clk_src, pcie3x1_1_pipe_clk_src, pcie3x2_pipe_clk_src
> usb0_pipe_clk_src are missing.
Here is the mapping,
pcie_2lane_phy_pipe_clk is the source for pcie3x2,
pcie_2lane_phy_pipe_clk_x1 is the source for pcie3x1_1,
usb_pcie_wrapper_pipe_clk is the source for pcie3x1_0_pipe_clk_src and
usb0_pipe_clk_src.
Is this what you are expecting or am I missing something here?
Thanks,
Kathiravan T.
>
>> +
>> +required:
>> + - compatible
>> + - clocks
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + clock-controller@1800000 {
>> + compatible = "qcom,ipq5332-gcc";
>> + reg = <0x01800000 0x80000>;
>> + clocks = <&xo_board>,
>> + <&sleep_clk>,
>> + <&pcie_2lane_phy_pipe_clk>,
>> + <&pcie_2lane_phy_pipe_clk_x1>,
>> + <&usb_pcie_wrapper_pipe_clk>;
>> + #clock-cells = <1>;
>> + #power-domain-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +...
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
@ 2023-02-07 4:26 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-07 4:26 UTC (permalink / raw)
To: Dmitry Baryshkov, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
Thanks Dmirty for taking time to review the patch.
On 2/6/2023 3:22 PM, Dmitry Baryshkov wrote:
> On 06/02/2023 09:12, Kathiravan T wrote:
>> Add binding for the Qualcomm IPQ5332 Global Clock Controller.
>>
>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>> ---
>> Changes in V3:
>> - Actually I missed to remove the clocks in V2 which are supposed to
>> be removed. In V3 I have removed those and they are
>> GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK
>> - For the same, didn't add the Reviewed-By tags from Stephen and
>> Krzysztof
>>
>> Changes in V2:
>> - property 'clocks' is marked required
>> - Renamed the include file name to match with compatible
>>
>> .../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++
>> include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++
>> 2 files changed, 417 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
>>
>> diff --git
>> a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> new file mode 100644
>> index 000000000000..961311af400c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>> @@ -0,0 +1,61 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Global Clock & Reset Controller on IPQ5332
>> +
>> +maintainers:
>> + - Stephen Boyd <sboyd@kernel.org>
>> +
>> +description: |
>> + Qualcomm global clock control module provides the clocks, resets
>> and power
>> + domains on IPQ5332.
>> +
>> + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
>> +
>> +allOf:
>> + - $ref: qcom,gcc.yaml#
>> +
>> +properties:
>> + compatible:
>> + const: qcom,ipq5332-gcc
>> +
>> + clocks:
>> + items:
>> + - description: Board XO clock source
>> + - description: Sleep clock source
>> + - description: PCIE 2lane PHY pipe clock source
>> + - description: PCIE 2lane x1 PHY pipe clock source (For second
>> lane)
>> + - description: USB PCIE wrapper pipe clock source
>> +
>> + clock-names:
>> + items:
>> + - const: xo
>> + - const: sleep_clk
>> + - const: pcie_2lane_phy_pipe_clk
>> + - const: pcie_2lane_phy_pipe_clk_x1
>> + - const: usb_pcie_wrapper_pipe_clk
>
> pcie3x1_0_pipe_clk_src, pcie3x1_1_pipe_clk_src, pcie3x2_pipe_clk_src
> usb0_pipe_clk_src are missing.
Here is the mapping,
pcie_2lane_phy_pipe_clk is the source for pcie3x2,
pcie_2lane_phy_pipe_clk_x1 is the source for pcie3x1_1,
usb_pcie_wrapper_pipe_clk is the source for pcie3x1_0_pipe_clk_src and
usb0_pipe_clk_src.
Is this what you are expecting or am I missing something here?
Thanks,
Kathiravan T.
>
>> +
>> +required:
>> + - compatible
>> + - clocks
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> + - |
>> + clock-controller@1800000 {
>> + compatible = "qcom,ipq5332-gcc";
>> + reg = <0x01800000 0x80000>;
>> + clocks = <&xo_board>,
>> + <&sleep_clk>,
>> + <&pcie_2lane_phy_pipe_clk>,
>> + <&pcie_2lane_phy_pipe_clk_x1>,
>> + <&usb_pcie_wrapper_pipe_clk>;
>> + #clock-cells = <1>;
>> + #power-domain-cells = <1>;
>> + #reset-cells = <1>;
>> + };
>> +...
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
2023-02-06 9:56 ` Dmitry Baryshkov
@ 2023-02-07 4:29 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-07 4:29 UTC (permalink / raw)
To: Dmitry Baryshkov, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
Thanks Dmirty for the review!
On 2/6/2023 3:26 PM, Dmitry Baryshkov wrote:
> On 06/02/2023 09:12, Kathiravan T wrote:
> > Add support for the global clock controller found on IPQ5332 SoC.
> >
> > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> > ---
> > Changes in V3:
> > - As I mentined the bindings, changes need to be done in V2 got
> > missed out and same has been done in V3, to call out
> > specifically dropped the CLK_IS_CRITICAL and dropped the
> > gcc_apss_ahb_clk, its source clock and gcc_apss_axi_clk
> > - Used gcc_parent_data_xo wherever applicable and dropped the
> > duplicate entries
> > - dropped the unused parent_map_10 and parent_data_10
> > - Used qcom_cc_probe instead of qcom_cc_really_probe
> > Changes in V2:
> > - Added the 'dependes on' for Kconfig symbol
> > - Dropped the CLK_IS_CRITICAL flag throughout the file
> > - Dropped the gcc_apss_ahb_clk and gcc_apss_axi_clk as these are
> > managed by bootloaders
>
>
> [skipped]
>
> > +static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
> > + F(2000000, P_XO, 12, 0, 0),
> > + { }
> > +};
> > +
> > +static struct clk_rcg2 gcc_pcie_aux_clk_src = {
> > + .cmd_rcgr = 0x28004,
> > + .mnd_width = 16,
> > + .hid_width = 5,
> > + .parent_map = gcc_parent_map_6,
> > + .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
> > + .clkr.hw.init = &(const struct clk_init_data){
> > + .name = "gcc_pcie_aux_clk_src",
> > + .parent_data = gcc_parent_data_6,
> > + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> > + .ops = &clk_rcg2_ops,
> > + },
> > +};
> > +
> > +static struct clk_regmap_mux pcie3x2_pipe_clk_src = {
> > + .reg = 0x28064,
> > + .shift = 8,
> > + .width = 2,
> > + .parent_map = gcc_parent_map_14,
> > + .clkr = {
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie3x2_phy_pipe_clk_src",
> > + .parent_data = gcc_parent_data_14,
> > + .num_parents = ARRAY_SIZE(gcc_parent_data_14),
> > + .ops = &clk_regmap_mux_closest_ops,
>
> Should we use clk_regmap_phy_mux_ops here instead?
Sure, I will check this one. Also looking at the commit, 74e4190cdebe
("clk: qcom: regmap: add PHY clock source implementation"), looks like I
can use the clk_regmap_phy_mux struct instead of clk_regmap_mux. I will
check into this and update accordingly.
>
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > + },
> > +};
> > +
> > +static struct clk_regmap_mux pcie3x1_0_pipe_clk_src = {
> > + .reg = 0x29064,
> > + .shift = 8,
> > + .width = 2,
> > + .parent_map = gcc_parent_map_15,
> > + .clkr = {
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie3x1_0_phy_pipe_clk_src",
> > + .parent_data = gcc_parent_data_15,
> > + .num_parents = ARRAY_SIZE(gcc_parent_data_15),
> > + .ops = &clk_regmap_mux_closest_ops,
>
> And clk_regmap_phy_mux_ops here too?
Ack.
>
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > + },
> > +};
> > +
> > +static struct clk_regmap_mux pcie3x1_1_pipe_clk_src = {
> > + .reg = 0x2A064,
> > + .shift = 8,
> > + .width = 2,
> > + .parent_map = gcc_parent_map_16,
> > + .clkr = {
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie3x1_1_phy_pipe_clk_src",
> > + .parent_data = gcc_parent_data_16,
> > + .num_parents = ARRAY_SIZE(gcc_parent_data_16),
> > + .ops = &clk_regmap_mux_closest_ops,
>
> And here?
Ack.
>
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > + },
> > +};
> > +
>
> [skipped]
>
>
> > +
> > +static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
> > + .halt_reg = 0x29068,
> > + .halt_check = BRANCH_HALT_DELAY,
> > + .clkr = {
> > + .enable_reg = 0x29068,
> > + .enable_mask = BIT(0),
> > + .hw.init = &(const struct clk_init_data){
> > + .name = "gcc_pcie3x1_0_pipe_clk",
> > + .parent_names = (const char *[]){
> > + "pcie3x1_0_pipe_clk_src"
> > + },
>
> Nooo. No parent_names please. You have several of them in the driver
I missed this. I will fix in next spin.
>
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + .ops = &clk_branch2_ops,
> > + },
> > + },
> > +};
> > +
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
@ 2023-02-07 4:29 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-07 4:29 UTC (permalink / raw)
To: Dmitry Baryshkov, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
Thanks Dmirty for the review!
On 2/6/2023 3:26 PM, Dmitry Baryshkov wrote:
> On 06/02/2023 09:12, Kathiravan T wrote:
> > Add support for the global clock controller found on IPQ5332 SoC.
> >
> > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
> > ---
> > Changes in V3:
> > - As I mentined the bindings, changes need to be done in V2 got
> > missed out and same has been done in V3, to call out
> > specifically dropped the CLK_IS_CRITICAL and dropped the
> > gcc_apss_ahb_clk, its source clock and gcc_apss_axi_clk
> > - Used gcc_parent_data_xo wherever applicable and dropped the
> > duplicate entries
> > - dropped the unused parent_map_10 and parent_data_10
> > - Used qcom_cc_probe instead of qcom_cc_really_probe
> > Changes in V2:
> > - Added the 'dependes on' for Kconfig symbol
> > - Dropped the CLK_IS_CRITICAL flag throughout the file
> > - Dropped the gcc_apss_ahb_clk and gcc_apss_axi_clk as these are
> > managed by bootloaders
>
>
> [skipped]
>
> > +static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {
> > + F(2000000, P_XO, 12, 0, 0),
> > + { }
> > +};
> > +
> > +static struct clk_rcg2 gcc_pcie_aux_clk_src = {
> > + .cmd_rcgr = 0x28004,
> > + .mnd_width = 16,
> > + .hid_width = 5,
> > + .parent_map = gcc_parent_map_6,
> > + .freq_tbl = ftbl_gcc_pcie_aux_clk_src,
> > + .clkr.hw.init = &(const struct clk_init_data){
> > + .name = "gcc_pcie_aux_clk_src",
> > + .parent_data = gcc_parent_data_6,
> > + .num_parents = ARRAY_SIZE(gcc_parent_data_6),
> > + .ops = &clk_rcg2_ops,
> > + },
> > +};
> > +
> > +static struct clk_regmap_mux pcie3x2_pipe_clk_src = {
> > + .reg = 0x28064,
> > + .shift = 8,
> > + .width = 2,
> > + .parent_map = gcc_parent_map_14,
> > + .clkr = {
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie3x2_phy_pipe_clk_src",
> > + .parent_data = gcc_parent_data_14,
> > + .num_parents = ARRAY_SIZE(gcc_parent_data_14),
> > + .ops = &clk_regmap_mux_closest_ops,
>
> Should we use clk_regmap_phy_mux_ops here instead?
Sure, I will check this one. Also looking at the commit, 74e4190cdebe
("clk: qcom: regmap: add PHY clock source implementation"), looks like I
can use the clk_regmap_phy_mux struct instead of clk_regmap_mux. I will
check into this and update accordingly.
>
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > + },
> > +};
> > +
> > +static struct clk_regmap_mux pcie3x1_0_pipe_clk_src = {
> > + .reg = 0x29064,
> > + .shift = 8,
> > + .width = 2,
> > + .parent_map = gcc_parent_map_15,
> > + .clkr = {
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie3x1_0_phy_pipe_clk_src",
> > + .parent_data = gcc_parent_data_15,
> > + .num_parents = ARRAY_SIZE(gcc_parent_data_15),
> > + .ops = &clk_regmap_mux_closest_ops,
>
> And clk_regmap_phy_mux_ops here too?
Ack.
>
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > + },
> > +};
> > +
> > +static struct clk_regmap_mux pcie3x1_1_pipe_clk_src = {
> > + .reg = 0x2A064,
> > + .shift = 8,
> > + .width = 2,
> > + .parent_map = gcc_parent_map_16,
> > + .clkr = {
> > + .hw.init = &(struct clk_init_data){
> > + .name = "pcie3x1_1_phy_pipe_clk_src",
> > + .parent_data = gcc_parent_data_16,
> > + .num_parents = ARRAY_SIZE(gcc_parent_data_16),
> > + .ops = &clk_regmap_mux_closest_ops,
>
> And here?
Ack.
>
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > + },
> > +};
> > +
>
> [skipped]
>
>
> > +
> > +static struct clk_branch gcc_pcie3x1_0_pipe_clk = {
> > + .halt_reg = 0x29068,
> > + .halt_check = BRANCH_HALT_DELAY,
> > + .clkr = {
> > + .enable_reg = 0x29068,
> > + .enable_mask = BIT(0),
> > + .hw.init = &(const struct clk_init_data){
> > + .name = "gcc_pcie3x1_0_pipe_clk",
> > + .parent_names = (const char *[]){
> > + "pcie3x1_0_pipe_clk_src"
> > + },
>
> Nooo. No parent_names please. You have several of them in the driver
I missed this. I will fix in next spin.
>
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + .ops = &clk_branch2_ops,
> > + },
> > + },
> > +};
> > +
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
2023-02-07 3:41 ` Bjorn Andersson
@ 2023-02-07 4:31 ` Kathiravan T
-1 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-07 4:31 UTC (permalink / raw)
To: Bjorn Andersson
Cc: krzysztof.kozlowski, agross, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel, quic_varada, quic_srichara
Thanks Bjorn for the review!
On 2/7/2023 9:11 AM, Bjorn Andersson wrote:
> On Mon, Feb 06, 2023 at 12:42:13PM +0530, Kathiravan T wrote:
>> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> [..]
>> +
>> +enum {
>> + DT_SLEEP_CLK,
>> + DT_XO,
>> + DT_PCIE_2LANE_PHY_PIPE_CLK,
>> + DT_PCIE_2LANE_PHY_PIPE_X1_CLK,
>> + DT_USB_PCIE_WRAPPER_PIPE_CLK,
> This list does not match the clocks as defined in the binding.
Ack. will fix this in next spin.
>
>> +};
>> +
>> +enum {
>> + P_PCIE3X2_PIPE,
>> + P_PCIE3X1_0_PIPE,
>> + P_PCIE3X1_1_PIPE,
>> + P_USB3PHY_0_PIPE,
>> + P_CORE_BI_PLL_TEST_SE,
>> + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
>> + P_GPLL0_OUT_AUX,
>> + P_GPLL0_OUT_MAIN,
>> + P_GPLL2_OUT_AUX,
>> + P_GPLL2_OUT_MAIN,
>> + P_GPLL4_OUT_AUX,
>> + P_GPLL4_OUT_MAIN,
>> + P_SLEEP_CLK,
>> + P_XO,
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
>> +
>> +static struct clk_alpha_pll gpll0_main = {
>> + .offset = 0x20000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
>> + .clkr = {
>> + .enable_reg = 0xb000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(const struct clk_init_data){
> Please add a space between ')' and '{ on all these.
Ack.
>
>> + .name = "gpll0_main",
>> + .parent_data = &gcc_parent_data_xo,
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_stromer_ops,
>> + },
>> + },
>> +};
> [..]
>> +static const struct qcom_cc_desc gcc_ipq5332_desc = {
>> + .config = &gcc_ipq5332_regmap_config,
>> + .clks = gcc_ipq5332_clocks,
>> + .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
>> + .resets = gcc_ipq5332_resets,
>> + .num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
>> + .clk_hws = gcc_ipq5332_hws,
>> + .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
> No GDSCs?
No, there is no GDSC support.
>
> Regards,
> Bjorn
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC
@ 2023-02-07 4:31 ` Kathiravan T
0 siblings, 0 replies; 48+ messages in thread
From: Kathiravan T @ 2023-02-07 4:31 UTC (permalink / raw)
To: Bjorn Andersson
Cc: krzysztof.kozlowski, agross, konrad.dybcio, robh+dt,
krzysztof.kozlowski+dt, mturquette, sboyd, linus.walleij,
catalin.marinas, will, shawnguo, arnd, dmitry.baryshkov,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel, quic_varada, quic_srichara
Thanks Bjorn for the review!
On 2/7/2023 9:11 AM, Bjorn Andersson wrote:
> On Mon, Feb 06, 2023 at 12:42:13PM +0530, Kathiravan T wrote:
>> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
> [..]
>> +
>> +enum {
>> + DT_SLEEP_CLK,
>> + DT_XO,
>> + DT_PCIE_2LANE_PHY_PIPE_CLK,
>> + DT_PCIE_2LANE_PHY_PIPE_X1_CLK,
>> + DT_USB_PCIE_WRAPPER_PIPE_CLK,
> This list does not match the clocks as defined in the binding.
Ack. will fix this in next spin.
>
>> +};
>> +
>> +enum {
>> + P_PCIE3X2_PIPE,
>> + P_PCIE3X1_0_PIPE,
>> + P_PCIE3X1_1_PIPE,
>> + P_USB3PHY_0_PIPE,
>> + P_CORE_BI_PLL_TEST_SE,
>> + P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,
>> + P_GPLL0_OUT_AUX,
>> + P_GPLL0_OUT_MAIN,
>> + P_GPLL2_OUT_AUX,
>> + P_GPLL2_OUT_MAIN,
>> + P_GPLL4_OUT_AUX,
>> + P_GPLL4_OUT_MAIN,
>> + P_SLEEP_CLK,
>> + P_XO,
>> +};
>> +
>> +static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };
>> +
>> +static struct clk_alpha_pll gpll0_main = {
>> + .offset = 0x20000,
>> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
>> + .clkr = {
>> + .enable_reg = 0xb000,
>> + .enable_mask = BIT(0),
>> + .hw.init = &(const struct clk_init_data){
> Please add a space between ')' and '{ on all these.
Ack.
>
>> + .name = "gpll0_main",
>> + .parent_data = &gcc_parent_data_xo,
>> + .num_parents = 1,
>> + .ops = &clk_alpha_pll_stromer_ops,
>> + },
>> + },
>> +};
> [..]
>> +static const struct qcom_cc_desc gcc_ipq5332_desc = {
>> + .config = &gcc_ipq5332_regmap_config,
>> + .clks = gcc_ipq5332_clocks,
>> + .num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),
>> + .resets = gcc_ipq5332_resets,
>> + .num_resets = ARRAY_SIZE(gcc_ipq5332_resets),
>> + .clk_hws = gcc_ipq5332_hws,
>> + .num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),
> No GDSCs?
No, there is no GDSC support.
>
> Regards,
> Bjorn
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
2023-02-07 4:26 ` Kathiravan T
@ 2023-02-07 10:05 ` Dmitry Baryshkov
-1 siblings, 0 replies; 48+ messages in thread
From: Dmitry Baryshkov @ 2023-02-07 10:05 UTC (permalink / raw)
To: Kathiravan T, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 07/02/2023 06:26, Kathiravan T wrote:
> Thanks Dmirty for taking time to review the patch.
>
>
> On 2/6/2023 3:22 PM, Dmitry Baryshkov wrote:
>> On 06/02/2023 09:12, Kathiravan T wrote:
>>> Add binding for the Qualcomm IPQ5332 Global Clock Controller.
>>>
>>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>>> ---
>>> Changes in V3:
>>> - Actually I missed to remove the clocks in V2 which are supposed to
>>> be removed. In V3 I have removed those and they are
>>> GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK
>>> - For the same, didn't add the Reviewed-By tags from Stephen and
>>> Krzysztof
>>>
>>> Changes in V2:
>>> - property 'clocks' is marked required
>>> - Renamed the include file name to match with compatible
>>>
>>> .../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++
>>> include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++
>>> 2 files changed, 417 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>>> create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>>> b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>>> new file mode 100644
>>> index 000000000000..961311af400c
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>>> @@ -0,0 +1,61 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Qualcomm Global Clock & Reset Controller on IPQ5332
>>> +
>>> +maintainers:
>>> + - Stephen Boyd <sboyd@kernel.org>
>>> +
>>> +description: |
>>> + Qualcomm global clock control module provides the clocks, resets
>>> and power
>>> + domains on IPQ5332.
>>> +
>>> + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
>>> +
>>> +allOf:
>>> + - $ref: qcom,gcc.yaml#
>>> +
>>> +properties:
>>> + compatible:
>>> + const: qcom,ipq5332-gcc
>>> +
>>> + clocks:
>>> + items:
>>> + - description: Board XO clock source
>>> + - description: Sleep clock source
>>> + - description: PCIE 2lane PHY pipe clock source
>>> + - description: PCIE 2lane x1 PHY pipe clock source (For second
>>> lane)
>>> + - description: USB PCIE wrapper pipe clock source
>>> +
>>> + clock-names:
>>> + items:
>>> + - const: xo
>>> + - const: sleep_clk
>>> + - const: pcie_2lane_phy_pipe_clk
>>> + - const: pcie_2lane_phy_pipe_clk_x1
>>> + - const: usb_pcie_wrapper_pipe_clk
>>
>> pcie3x1_0_pipe_clk_src, pcie3x1_1_pipe_clk_src, pcie3x2_pipe_clk_src
>> usb0_pipe_clk_src are missing.
>
>
> Here is the mapping,
>
> pcie_2lane_phy_pipe_clk is the source for pcie3x2,
>
> pcie_2lane_phy_pipe_clk_x1 is the source for pcie3x1_1,
>
> usb_pcie_wrapper_pipe_clk is the source for pcie3x1_0_pipe_clk_src and
> usb0_pipe_clk_src.
>
> Is this what you are expecting or am I missing something here?
Yes. There were three parent_name entries in your driver. So I can
assume that the binding might also be incorrect.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC
@ 2023-02-07 10:05 ` Dmitry Baryshkov
0 siblings, 0 replies; 48+ messages in thread
From: Dmitry Baryshkov @ 2023-02-07 10:05 UTC (permalink / raw)
To: Kathiravan T, krzysztof.kozlowski, agross, andersson,
konrad.dybcio, robh+dt, krzysztof.kozlowski+dt, mturquette,
sboyd, linus.walleij, catalin.marinas, will, shawnguo, arnd,
marcel.ziswiler, nfraprado, robimarko, quic_gurus, linux-arm-msm,
devicetree, linux-kernel, linux-clk, linux-gpio,
linux-arm-kernel
Cc: quic_varada, quic_srichara
On 07/02/2023 06:26, Kathiravan T wrote:
> Thanks Dmirty for taking time to review the patch.
>
>
> On 2/6/2023 3:22 PM, Dmitry Baryshkov wrote:
>> On 06/02/2023 09:12, Kathiravan T wrote:
>>> Add binding for the Qualcomm IPQ5332 Global Clock Controller.
>>>
>>> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
>>> ---
>>> Changes in V3:
>>> - Actually I missed to remove the clocks in V2 which are supposed to
>>> be removed. In V3 I have removed those and they are
>>> GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK
>>> - For the same, didn't add the Reviewed-By tags from Stephen and
>>> Krzysztof
>>>
>>> Changes in V2:
>>> - property 'clocks' is marked required
>>> - Renamed the include file name to match with compatible
>>>
>>> .../bindings/clock/qcom,ipq5332-gcc.yaml | 61 +++
>>> include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++
>>> 2 files changed, 417 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>>> create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>>> b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>>> new file mode 100644
>>> index 000000000000..961311af400c
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
>>> @@ -0,0 +1,61 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: Qualcomm Global Clock & Reset Controller on IPQ5332
>>> +
>>> +maintainers:
>>> + - Stephen Boyd <sboyd@kernel.org>
>>> +
>>> +description: |
>>> + Qualcomm global clock control module provides the clocks, resets
>>> and power
>>> + domains on IPQ5332.
>>> +
>>> + See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
>>> +
>>> +allOf:
>>> + - $ref: qcom,gcc.yaml#
>>> +
>>> +properties:
>>> + compatible:
>>> + const: qcom,ipq5332-gcc
>>> +
>>> + clocks:
>>> + items:
>>> + - description: Board XO clock source
>>> + - description: Sleep clock source
>>> + - description: PCIE 2lane PHY pipe clock source
>>> + - description: PCIE 2lane x1 PHY pipe clock source (For second
>>> lane)
>>> + - description: USB PCIE wrapper pipe clock source
>>> +
>>> + clock-names:
>>> + items:
>>> + - const: xo
>>> + - const: sleep_clk
>>> + - const: pcie_2lane_phy_pipe_clk
>>> + - const: pcie_2lane_phy_pipe_clk_x1
>>> + - const: usb_pcie_wrapper_pipe_clk
>>
>> pcie3x1_0_pipe_clk_src, pcie3x1_1_pipe_clk_src, pcie3x2_pipe_clk_src
>> usb0_pipe_clk_src are missing.
>
>
> Here is the mapping,
>
> pcie_2lane_phy_pipe_clk is the source for pcie3x2,
>
> pcie_2lane_phy_pipe_clk_x1 is the source for pcie3x1_1,
>
> usb_pcie_wrapper_pipe_clk is the source for pcie3x1_0_pipe_clk_src and
> usb0_pipe_clk_src.
>
> Is this what you are expecting or am I missing something here?
Yes. There were three parent_name entries in your driver. So I can
assume that the binding might also be incorrect.
--
With best wishes
Dmitry
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2023-02-07 10:06 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-06 7:12 [PATCH V3 0/9] Add minimal boot support for IPQ5332 Kathiravan T
2023-02-06 7:12 ` Kathiravan T
2023-02-06 7:12 ` [PATCH V3 1/9] dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl Kathiravan T
2023-02-06 7:12 ` Kathiravan T
2023-02-06 8:26 ` Krzysztof Kozlowski
2023-02-06 8:26 ` Krzysztof Kozlowski
2023-02-06 7:12 ` [PATCH V3 2/9] pinctrl: qcom: Introduce IPQ5332 TLMM driver Kathiravan T
2023-02-06 7:12 ` Kathiravan T
2023-02-07 3:34 ` Bjorn Andersson
2023-02-07 3:34 ` Bjorn Andersson
2023-02-06 7:12 ` [PATCH V3 3/9] clk: qcom: Add STROMER PLUS PLL type for IPQ5332 Kathiravan T
2023-02-06 7:12 ` Kathiravan T
2023-02-06 7:12 ` [PATCH V3 4/9] dt-bindings: clock: Add Qualcomm IPQ5332 GCC Kathiravan T
2023-02-06 7:12 ` Kathiravan T
2023-02-06 8:26 ` Krzysztof Kozlowski
2023-02-06 8:26 ` Krzysztof Kozlowski
2023-02-06 9:52 ` Dmitry Baryshkov
2023-02-06 9:52 ` Dmitry Baryshkov
2023-02-07 4:26 ` Kathiravan T
2023-02-07 4:26 ` Kathiravan T
2023-02-07 10:05 ` Dmitry Baryshkov
2023-02-07 10:05 ` Dmitry Baryshkov
2023-02-06 7:12 ` [PATCH V3 5/9] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC Kathiravan T
2023-02-06 9:52 ` Dmitry Baryshkov
2023-02-06 9:56 ` Dmitry Baryshkov
2023-02-06 9:56 ` Dmitry Baryshkov
2023-02-07 4:29 ` Kathiravan T
2023-02-07 4:29 ` Kathiravan T
2023-02-07 3:41 ` Bjorn Andersson
2023-02-07 3:41 ` Bjorn Andersson
2023-02-07 4:31 ` Kathiravan T
2023-02-07 4:31 ` Kathiravan T
2023-02-06 7:12 ` [PATCH V3 6/9] dt-bindings: qcom: add ipq5332 boards Kathiravan T
2023-02-06 7:12 ` Kathiravan T
2023-02-06 8:27 ` Krzysztof Kozlowski
2023-02-06 8:27 ` Krzysztof Kozlowski
2023-02-06 7:12 ` [PATCH V3 7/9] dt-bindings: firmware: qcom,scm: document IPQ5332 SCM Kathiravan T
2023-02-06 7:12 ` Kathiravan T
2023-02-06 7:12 ` [PATCH V3 8/9] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support Kathiravan T
2023-02-06 7:12 ` Kathiravan T
2023-02-06 7:12 ` [PATCH V3 9/9] arm64: defconfig: Enable IPQ5332 SoC base configs Kathiravan T
2023-02-06 7:12 ` Kathiravan T
2023-02-06 9:53 ` Dmitry Baryshkov
2023-02-06 9:53 ` Dmitry Baryshkov
2023-02-06 11:25 ` [PATCH V3 0/9] Add minimal boot support for IPQ5332 Linus Walleij
2023-02-06 11:25 ` Linus Walleij
2023-02-06 11:42 ` Kathiravan T
2023-02-06 11:42 ` Kathiravan T
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