* [PATCH] ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema
@ 2020-06-26 8:06 Krzysztof Kozlowski
2020-07-06 18:58 ` Dinh Nguyen
0 siblings, 1 reply; 2+ messages in thread
From: Krzysztof Kozlowski @ 2020-06-26 8:06 UTC (permalink / raw)
To: linux-kernel; +Cc: Krzysztof Kozlowski, Dinh Nguyen, Rob Herring, devicetree
Fix dtschema validator warnings like:
l2-cache@fffff000: $nodename:0:
'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/socfpga.dtsi | 2 +-
arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index c2b54af417a2..78f3267d9cbf 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -726,7 +726,7 @@
};
};
- L2: l2-cache@fffef000 {
+ L2: cache-controller@fffef000 {
compatible = "arm,pl310-cache";
reg = <0xfffef000 0x1000>;
interrupts = <0 38 0x04>;
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 3b8571b8b412..8f614c4b0e3e 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -636,7 +636,7 @@
reg = <0xffcfb100 0x80>;
};
- L2: l2-cache@fffff000 {
+ L2: cache-controller@fffff000 {
compatible = "arm,pl310-cache";
reg = <0xfffff000 0x1000>;
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema
2020-06-26 8:06 [PATCH] ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema Krzysztof Kozlowski
@ 2020-07-06 18:58 ` Dinh Nguyen
0 siblings, 0 replies; 2+ messages in thread
From: Dinh Nguyen @ 2020-07-06 18:58 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-kernel; +Cc: Rob Herring, devicetree
On 6/26/20 3:06 AM, Krzysztof Kozlowski wrote:
> Fix dtschema validator warnings like:
> l2-cache@fffff000: $nodename:0:
> 'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> arch/arm/boot/dts/socfpga.dtsi | 2 +-
> arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index c2b54af417a2..78f3267d9cbf 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -726,7 +726,7 @@
> };
> };
>
> - L2: l2-cache@fffef000 {
> + L2: cache-controller@fffef000 {
> compatible = "arm,pl310-cache";
> reg = <0xfffef000 0x1000>;
> interrupts = <0 38 0x04>;
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index 3b8571b8b412..8f614c4b0e3e 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -636,7 +636,7 @@
> reg = <0xffcfb100 0x80>;
> };
>
> - L2: l2-cache@fffff000 {
> + L2: cache-controller@fffff000 {
> compatible = "arm,pl310-cache";
> reg = <0xfffff000 0x1000>;
> interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
>
Added the correct Fixes annotation and applied, thanks!
Dinh
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2020-06-26 8:06 [PATCH] ARM: dts: socfpga: Align L2 cache-controller nodename with dtschema Krzysztof Kozlowski
2020-07-06 18:58 ` Dinh Nguyen
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