Re: [PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec support

Re: [PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec support

[Andrew Lunn]

On Mon, Jul 11, 2022 at 07:44:34PM +1000, Wei Fang wrote:
> Enable the fec on i.MX8ULP EVK board.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>
> ---
> V2 change:
> Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
> ---
>  arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
>  1 file changed, 57 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> index 33e84c4e9ed8..ebce716b10e6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -19,6 +19,21 @@ memory@80000000 {
>  		device_type = "memory";
>  		reg = <0x0 0x80000000 0 0x80000000>;
>  	};
> +
> +	clock_ext_rmii: clock-ext-rmii {
> +		compatible = "fixed-clock";
> +		clock-frequency = <50000000>;
> +		clock-output-names = "ext_rmii_clk";
> +		#clock-cells = <0>;
> +	};
> +
> +	clock_ext_ts: clock-ext-ts {
> +		compatible = "fixed-clock";
> +		/* External ts clock is 50MHZ from PHY on EVK board. */
> +		clock-frequency = <50000000>;
> +		clock-output-names = "ext_ts_clk";
> +		#clock-cells = <0>;
> +	};

Do you need any PHY properties to turn this clock on? Or is it
strapped to be always on?

I'm surprised it is limited to Fast Ethernet. I know the Vybrid and
some of the older SoCs are Fast Ethernet only, but i thought all the
newer supported 1G?

	 Andrew

Re: [PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec support

[Andrew Lunn]

On Mon, Jul 11, 2022 at 07:44:34PM +1000, Wei Fang wrote:
> Enable the fec on i.MX8ULP EVK board.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>
> ---
> V2 change:
> Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
> ---
>  arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
>  1 file changed, 57 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> index 33e84c4e9ed8..ebce716b10e6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> @@ -19,6 +19,21 @@ memory@80000000 {
>  		device_type = "memory";
>  		reg = <0x0 0x80000000 0 0x80000000>;
>  	};
> +
> +	clock_ext_rmii: clock-ext-rmii {
> +		compatible = "fixed-clock";
> +		clock-frequency = <50000000>;
> +		clock-output-names = "ext_rmii_clk";
> +		#clock-cells = <0>;
> +	};
> +
> +	clock_ext_ts: clock-ext-ts {
> +		compatible = "fixed-clock";
> +		/* External ts clock is 50MHZ from PHY on EVK board. */
> +		clock-frequency = <50000000>;
> +		clock-output-names = "ext_ts_clk";
> +		#clock-cells = <0>;
> +	};

Do you need any PHY properties to turn this clock on? Or is it
strapped to be always on?

I'm surprised it is limited to Fast Ethernet. I know the Vybrid and
some of the older SoCs are Fast Ethernet only, but i thought all the
newer supported 1G?

	 Andrew


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RE: [EXT] Re: [PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec support

[Wei Fang]

> -----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: 2022年7月11日 15:02
> To: Wei Fang <wei.fang@nxp.com>
> Cc: davem@davemloft.net; edumazet@google.com; kuba@kernel.org;
> pabeni@redhat.com; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> shawnguo@kernel.org; s.hauer@pengutronix.de; netdev@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; Peng Fan <peng.fan@nxp.com>; Jacky Bai
> <ping.bai@nxp.com>; sudeep.holla@arm.com;
> linux-arm-kernel@lists.infradead.org; Aisheng Dong <aisheng.dong@nxp.com>
> Subject: [EXT] Re: [PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec
> support
> 
> Caution: EXT Email
> 
> On Mon, Jul 11, 2022 at 07:44:34PM +1000, Wei Fang wrote:
> > Enable the fec on i.MX8ULP EVK board.
> >
> > Signed-off-by: Wei Fang <wei.fang@nxp.com>
> > ---
> > V2 change:
> > Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
> > ---
> >  arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57
> > +++++++++++++++++++
> >  1 file changed, 57 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > index 33e84c4e9ed8..ebce716b10e6 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > @@ -19,6 +19,21 @@ memory@80000000 {
> >               device_type = "memory";
> >               reg = <0x0 0x80000000 0 0x80000000>;
> >       };
> > +
> > +     clock_ext_rmii: clock-ext-rmii {
> > +             compatible = "fixed-clock";
> > +             clock-frequency = <50000000>;
> > +             clock-output-names = "ext_rmii_clk";
> > +             #clock-cells = <0>;
> > +     };
> > +
> > +     clock_ext_ts: clock-ext-ts {
> > +             compatible = "fixed-clock";
> > +             /* External ts clock is 50MHZ from PHY on EVK board. */
> > +             clock-frequency = <50000000>;
> > +             clock-output-names = "ext_ts_clk";
> > +             #clock-cells = <0>;
> > +     };
> 
> Do you need any PHY properties to turn this clock on? Or is it strapped to be
> always on?
> 
Yes, the clock is strapped to be always on, so any PHY property is not required.

> I'm surprised it is limited to Fast Ethernet. I know the Vybrid and some of the
> older SoCs are Fast Ethernet only, but i thought all the newer supported 1G?
> 
>          Andrew

The FEC of imx8ulp is reused from imx6ul , it supports 10/100 Mbit/s full-duplex and configurable half-duplex operation, do not support 1G.

RE: [EXT] Re: [PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec support

[Wei Fang]

> -----Original Message-----
> From: Andrew Lunn <andrew@lunn.ch>
> Sent: 2022年7月11日 15:02
> To: Wei Fang <wei.fang@nxp.com>
> Cc: davem@davemloft.net; edumazet@google.com; kuba@kernel.org;
> pabeni@redhat.com; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> shawnguo@kernel.org; s.hauer@pengutronix.de; netdev@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; Peng Fan <peng.fan@nxp.com>; Jacky Bai
> <ping.bai@nxp.com>; sudeep.holla@arm.com;
> linux-arm-kernel@lists.infradead.org; Aisheng Dong <aisheng.dong@nxp.com>
> Subject: [EXT] Re: [PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec
> support
> 
> Caution: EXT Email
> 
> On Mon, Jul 11, 2022 at 07:44:34PM +1000, Wei Fang wrote:
> > Enable the fec on i.MX8ULP EVK board.
> >
> > Signed-off-by: Wei Fang <wei.fang@nxp.com>
> > ---
> > V2 change:
> > Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
> > ---
> >  arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57
> > +++++++++++++++++++
> >  1 file changed, 57 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > index 33e84c4e9ed8..ebce716b10e6 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
> > @@ -19,6 +19,21 @@ memory@80000000 {
> >               device_type = "memory";
> >               reg = <0x0 0x80000000 0 0x80000000>;
> >       };
> > +
> > +     clock_ext_rmii: clock-ext-rmii {
> > +             compatible = "fixed-clock";
> > +             clock-frequency = <50000000>;
> > +             clock-output-names = "ext_rmii_clk";
> > +             #clock-cells = <0>;
> > +     };
> > +
> > +     clock_ext_ts: clock-ext-ts {
> > +             compatible = "fixed-clock";
> > +             /* External ts clock is 50MHZ from PHY on EVK board. */
> > +             clock-frequency = <50000000>;
> > +             clock-output-names = "ext_ts_clk";
> > +             #clock-cells = <0>;
> > +     };
> 
> Do you need any PHY properties to turn this clock on? Or is it strapped to be
> always on?
> 
Yes, the clock is strapped to be always on, so any PHY property is not required.

> I'm surprised it is limited to Fast Ethernet. I know the Vybrid and some of the
> older SoCs are Fast Ethernet only, but i thought all the newer supported 1G?
> 
>          Andrew

The FEC of imx8ulp is reused from imx6ul , it supports 10/100 Mbit/s full-duplex and configurable half-duplex operation, do not support 1G.
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[PATCH V2 0/3] Add the fec node on i.MX8ULP platform

[Wei Fang]

Add the fec node on i.MX8ULP platfroms.
And enable the fec support on i.MX8ULP EVK boards.

Wei Fang (3):
  dt-bindings: net: fsl,fec: Add i.MX8ULP FEC items
  arm64: dts: imx8ulp: Add the fec support
  arm64: dts: imx8ulp-evk: Add the fec support

 .../devicetree/bindings/net/fsl,fec.yaml      |  5 ++
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 11 ++++
 3 files changed, 73 insertions(+)

-- 
2.25.1

[PATCH V2 0/3] Add the fec node on i.MX8ULP platform

[Wei Fang]

Add the fec node on i.MX8ULP platfroms.
And enable the fec support on i.MX8ULP EVK boards.

Wei Fang (3):
  dt-bindings: net: fsl,fec: Add i.MX8ULP FEC items
  arm64: dts: imx8ulp: Add the fec support
  arm64: dts: imx8ulp-evk: Add the fec support

 .../devicetree/bindings/net/fsl,fec.yaml      |  5 ++
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi    | 11 ++++
 3 files changed, 73 insertions(+)

-- 
2.25.1


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[PATCH V2 1/3] dt-bindings: net: fsl,fec: Add i.MX8ULP FEC items

[Wei Fang]

Add fsl,imx8ulp-fec for i.MX8ULP platform.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
V2 change:
Add fsl,imx6q-fec
---
 Documentation/devicetree/bindings/net/fsl,fec.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml
index daa2f79a294f..4d2454ade3b6 100644
--- a/Documentation/devicetree/bindings/net/fsl,fec.yaml
+++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml
@@ -58,6 +58,11 @@ properties:
               - fsl,imx8qxp-fec
           - const: fsl,imx8qm-fec
           - const: fsl,imx6sx-fec
+      - items:
+          - enum:
+              - fsl,imx8ulp-fec
+          - const: fsl,imx6ul-fec
+          - const: fsl,imx6q-fec
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH V2 1/3] dt-bindings: net: fsl,fec: Add i.MX8ULP FEC items

[Wei Fang]

Add fsl,imx8ulp-fec for i.MX8ULP platform.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
V2 change:
Add fsl,imx6q-fec
---
 Documentation/devicetree/bindings/net/fsl,fec.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml
index daa2f79a294f..4d2454ade3b6 100644
--- a/Documentation/devicetree/bindings/net/fsl,fec.yaml
+++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml
@@ -58,6 +58,11 @@ properties:
               - fsl,imx8qxp-fec
           - const: fsl,imx8qm-fec
           - const: fsl,imx6sx-fec
+      - items:
+          - enum:
+              - fsl,imx8ulp-fec
+          - const: fsl,imx6ul-fec
+          - const: fsl,imx6q-fec
 
   reg:
     maxItems: 1
-- 
2.25.1


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[PATCH V2 2/3] arm64: dts: imx8ulp: Add the fec support

[Wei Fang]

Add the fec support on i.MX8ULP platforms.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
V2 change:
Remove the external clocks which is related to specific board.
---
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 60c1b018bf03..3e8a1e4f0fc2 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -16,6 +16,7 @@ / {
 	#size-cells = <2>;
 
 	aliases {
+		ethernet0 = &fec;
 		gpio0 = &gpiod;
 		gpio1 = &gpioe;
 		gpio2 = &gpiof;
@@ -365,6 +366,16 @@ usdhc2: mmc@298f0000 {
 				bus-width = <4>;
 				status = "disabled";
 			};
+
+			fec: ethernet@29950000 {
+				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
+				reg = <0x29950000 0x10000>;
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "int0";
+				fsl,num-tx-queues = <1>;
+				fsl,num-rx-queues = <1>;
+				status = "disabled";
+			};
 		};
 
 		gpioe: gpio@2d000080 {
-- 
2.25.1

[PATCH V2 2/3] arm64: dts: imx8ulp: Add the fec support

[Wei Fang]

Add the fec support on i.MX8ULP platforms.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
V2 change:
Remove the external clocks which is related to specific board.
---
 arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 60c1b018bf03..3e8a1e4f0fc2 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -16,6 +16,7 @@ / {
 	#size-cells = <2>;
 
 	aliases {
+		ethernet0 = &fec;
 		gpio0 = &gpiod;
 		gpio1 = &gpioe;
 		gpio2 = &gpiof;
@@ -365,6 +366,16 @@ usdhc2: mmc@298f0000 {
 				bus-width = <4>;
 				status = "disabled";
 			};
+
+			fec: ethernet@29950000 {
+				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
+				reg = <0x29950000 0x10000>;
+				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "int0";
+				fsl,num-tx-queues = <1>;
+				fsl,num-rx-queues = <1>;
+				status = "disabled";
+			};
 		};
 
 		gpioe: gpio@2d000080 {
-- 
2.25.1


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[PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec support

[Wei Fang]

Enable the fec on i.MX8ULP EVK board.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
V2 change:
Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
---
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index 33e84c4e9ed8..ebce716b10e6 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -19,6 +19,21 @@ memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0 0x80000000>;
 	};
+
+	clock_ext_rmii: clock-ext-rmii {
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+		clock-output-names = "ext_rmii_clk";
+		#clock-cells = <0>;
+	};
+
+	clock_ext_ts: clock-ext-ts {
+		compatible = "fixed-clock";
+		/* External ts clock is 50MHZ from PHY on EVK board. */
+		clock-frequency = <50000000>;
+		clock-output-names = "ext_ts_clk";
+		#clock-cells = <0>;
+	};
 };
 
 &lpuart5 {
@@ -38,7 +53,49 @@ &usdhc0 {
 	status = "okay";
 };
 
+&fec {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_enet>;
+	pinctrl-1 = <&pinctrl_enet>;
+	clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+		 <&pcc4 IMX8ULP_CLK_ENET>,
+		 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
+		 <&clock_ext_rmii>;
+	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
+	assigned-clock-parents = <&clock_ext_ts>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy: ethernet-phy {
+			reg = <1>;
+			micrel,led-mode = <1>;
+		};
+	};
+};
+
 &iomuxc1 {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
+			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
+			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
+			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
+			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
+			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
+			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
+			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
+			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
+			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
+			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
+		>;
+	};
+
 	pinctrl_lpuart5: lpuart5grp {
 		fsl,pins = <
 			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
-- 
2.25.1

[PATCH V2 3/3] arm64: dts: imx8ulp-evk: Add the fec support

[Wei Fang]

Enable the fec on i.MX8ULP EVK board.

Signed-off-by: Wei Fang <wei.fang@nxp.com>
---
V2 change:
Add clock_ext_rmii and clock_ext_ts. They are both related to EVK board.
---
 arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 57 +++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index 33e84c4e9ed8..ebce716b10e6 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -19,6 +19,21 @@ memory@80000000 {
 		device_type = "memory";
 		reg = <0x0 0x80000000 0 0x80000000>;
 	};
+
+	clock_ext_rmii: clock-ext-rmii {
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+		clock-output-names = "ext_rmii_clk";
+		#clock-cells = <0>;
+	};
+
+	clock_ext_ts: clock-ext-ts {
+		compatible = "fixed-clock";
+		/* External ts clock is 50MHZ from PHY on EVK board. */
+		clock-frequency = <50000000>;
+		clock-output-names = "ext_ts_clk";
+		#clock-cells = <0>;
+	};
 };
 
 &lpuart5 {
@@ -38,7 +53,49 @@ &usdhc0 {
 	status = "okay";
 };
 
+&fec {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_enet>;
+	pinctrl-1 = <&pinctrl_enet>;
+	clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+		 <&pcc4 IMX8ULP_CLK_ENET>,
+		 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
+		 <&clock_ext_rmii>;
+	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
+	assigned-clock-parents = <&clock_ext_ts>;
+	phy-mode = "rmii";
+	phy-handle = <&ethphy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy: ethernet-phy {
+			reg = <1>;
+			micrel,led-mode = <1>;
+		};
+	};
+};
+
 &iomuxc1 {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
+			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
+			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
+			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
+			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
+			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
+			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
+			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
+			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
+			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
+			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
+		>;
+	};
+
 	pinctrl_lpuart5: lpuart5grp {
 		fsl,pins = <
 			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
-- 
2.25.1


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Re: [PATCH V2 1/3] dt-bindings: net: fsl,fec: Add i.MX8ULP FEC items

[Krzysztof Kozlowski]

On 11/07/2022 11:44, Wei Fang wrote:
> Add fsl,imx8ulp-fec for i.MX8ULP platform.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>
> ---
> V2 change:
> Add fsl,imx6q-fec
> ---
>  Documentation/devicetree/bindings/net/fsl,fec.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml
> index daa2f79a294f..4d2454ade3b6 100644
> --- a/Documentation/devicetree/bindings/net/fsl,fec.yaml
> +++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml
> @@ -58,6 +58,11 @@ properties:
>                - fsl,imx8qxp-fec
>            - const: fsl,imx8qm-fec
>            - const: fsl,imx6sx-fec
> +      - items:
> +          - enum:
> +              - fsl,imx8ulp-fec
> +          - const: fsl,imx6ul-fec
> +          - const: fsl,imx6q-fec


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

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Re: [PATCH V2 1/3] dt-bindings: net: fsl,fec: Add i.MX8ULP FEC items

[Krzysztof Kozlowski]

On 11/07/2022 11:44, Wei Fang wrote:
> Add fsl,imx8ulp-fec for i.MX8ULP platform.
> 
> Signed-off-by: Wei Fang <wei.fang@nxp.com>
> ---
> V2 change:
> Add fsl,imx6q-fec
> ---
>  Documentation/devicetree/bindings/net/fsl,fec.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/fsl,fec.yaml b/Documentation/devicetree/bindings/net/fsl,fec.yaml
> index daa2f79a294f..4d2454ade3b6 100644
> --- a/Documentation/devicetree/bindings/net/fsl,fec.yaml
> +++ b/Documentation/devicetree/bindings/net/fsl,fec.yaml
> @@ -58,6 +58,11 @@ properties:
>                - fsl,imx8qxp-fec
>            - const: fsl,imx8qm-fec
>            - const: fsl,imx6sx-fec
> +      - items:
> +          - enum:
> +              - fsl,imx8ulp-fec
> +          - const: fsl,imx6ul-fec
> +          - const: fsl,imx6q-fec


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH V2 0/3] Add the fec node on i.MX8ULP platform

[Jakub Kicinski]

On Mon, 11 Jul 2022 19:44:31 +1000 Wei Fang wrote:
> Add the fec node on i.MX8ULP platfroms.
> And enable the fec support on i.MX8ULP EVK boards.

Something odd happened to this posting, there are multiple emails
with the same Message-ID. Could you please collect the acks and post 
a clean v3? If the intention is for the patches to go via the
networking tree please repost them with the tree name in the subject 
tag i.e. [PATCH net-next]

Re: [PATCH V2 0/3] Add the fec node on i.MX8ULP platform

[Jakub Kicinski]

On Mon, 11 Jul 2022 19:44:31 +1000 Wei Fang wrote:
> Add the fec node on i.MX8ULP platfroms.
> And enable the fec support on i.MX8ULP EVK boards.

Something odd happened to this posting, there are multiple emails
with the same Message-ID. Could you please collect the acks and post 
a clean v3? If the intention is for the patches to go via the
networking tree please repost them with the tree name in the subject 
tag i.e. [PATCH net-next]

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RE: [EXT] Re: [PATCH V2 0/3] Add the fec node on i.MX8ULP platform

[Wei Fang]

> -----Original Message-----
> From: Jakub Kicinski <kuba@kernel.org>
> Sent: 2022年7月14日 10:47
> To: Wei Fang <wei.fang@nxp.com>
> Cc: davem@davemloft.net; edumazet@google.com; pabeni@redhat.com;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> shawnguo@kernel.org; s.hauer@pengutronix.de; netdev@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; Peng Fan <peng.fan@nxp.com>; Jacky Bai
> <ping.bai@nxp.com>; sudeep.holla@arm.com;
> linux-arm-kernel@lists.infradead.org; Aisheng Dong <aisheng.dong@nxp.com>
> Subject: [EXT] Re: [PATCH V2 0/3] Add the fec node on i.MX8ULP platform
> 
> Caution: EXT Email
> 
> On Mon, 11 Jul 2022 19:44:31 +1000 Wei Fang wrote:
> > Add the fec node on i.MX8ULP platfroms.
> > And enable the fec support on i.MX8ULP EVK boards.
> 
> Something odd happened to this posting, there are multiple emails with the
> same Message-ID. Could you please collect the acks and post a clean v3? If the
> intention is for the patches to go via the networking tree please repost them
> with the tree name in the subject tag i.e. [PATCH net-next]

Ok, I'll repost the patches. Thank you.

RE: [EXT] Re: [PATCH V2 0/3] Add the fec node on i.MX8ULP platform

[Wei Fang]

> -----Original Message-----
> From: Jakub Kicinski <kuba@kernel.org>
> Sent: 2022年7月14日 10:47
> To: Wei Fang <wei.fang@nxp.com>
> Cc: davem@davemloft.net; edumazet@google.com; pabeni@redhat.com;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> shawnguo@kernel.org; s.hauer@pengutronix.de; netdev@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; festevam@gmail.com; dl-linux-imx
> <linux-imx@nxp.com>; Peng Fan <peng.fan@nxp.com>; Jacky Bai
> <ping.bai@nxp.com>; sudeep.holla@arm.com;
> linux-arm-kernel@lists.infradead.org; Aisheng Dong <aisheng.dong@nxp.com>
> Subject: [EXT] Re: [PATCH V2 0/3] Add the fec node on i.MX8ULP platform
> 
> Caution: EXT Email
> 
> On Mon, 11 Jul 2022 19:44:31 +1000 Wei Fang wrote:
> > Add the fec node on i.MX8ULP platfroms.
> > And enable the fec support on i.MX8ULP EVK boards.
> 
> Something odd happened to this posting, there are multiple emails with the
> same Message-ID. Could you please collect the acks and post a clean v3? If the
> intention is for the patches to go via the networking tree please repost them
> with the tree name in the subject tag i.e. [PATCH net-next]

Ok, I'll repost the patches. Thank you.
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