* [PATCH 10/20] arm64: dts: Update cache properties for marvell
@ 2022-10-31 9:20 ` Pierre Gondois
0 siblings, 0 replies; 8+ messages in thread
From: Pierre Gondois @ 2022-10-31 9:20 UTC (permalink / raw)
To: linux-kernel
Cc: pierre.gondois, Rob.Herring, Rob Herring, Krzysztof Kozlowski,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Vadym Kochan, Chris Packham, devicetree, linux-arm-kernel
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The recently added init_of_cache_level() function checks
these properties. Add them if missing.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
4 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
index 80b44c7df56a..d4770acec6ac 100644
--- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
@@ -49,6 +49,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index fcab5173fe67..990f70303fe6 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -51,6 +51,7 @@ l2: l2-cache {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 3db427122f9e..a7b8e001cc9c 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -81,6 +81,7 @@ l2_0: l2-cache0 {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
@@ -88,6 +89,7 @@ l2_1: l2-cache1 {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
index 68782f161f12..7740098fd108 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
@@ -81,6 +81,7 @@ l2_0: l2-cache0 {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
@@ -88,6 +89,7 @@ l2_1: l2-cache1 {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 10/20] arm64: dts: Update cache properties for marvell
@ 2022-10-31 9:20 ` Pierre Gondois
0 siblings, 0 replies; 8+ messages in thread
From: Pierre Gondois @ 2022-10-31 9:20 UTC (permalink / raw)
To: linux-kernel
Cc: pierre.gondois, Rob.Herring, Rob Herring, Krzysztof Kozlowski,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Vadym Kochan, Chris Packham, devicetree, linux-arm-kernel
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The recently added init_of_cache_level() function checks
these properties. Add them if missing.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
4 files changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
index 80b44c7df56a..d4770acec6ac 100644
--- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
@@ -49,6 +49,7 @@ cpu1: cpu@1 {
l2: l2-cache {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index fcab5173fe67..990f70303fe6 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -51,6 +51,7 @@ l2: l2-cache {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 3db427122f9e..a7b8e001cc9c 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -81,6 +81,7 @@ l2_0: l2-cache0 {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
@@ -88,6 +89,7 @@ l2_1: l2-cache1 {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
index 68782f161f12..7740098fd108 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
@@ -81,6 +81,7 @@ l2_0: l2-cache0 {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
l2_1: l2-cache1 {
@@ -88,6 +89,7 @@ l2_1: l2-cache1 {
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
+ cache-level = <2>;
};
};
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 10/20] arm64: dts: Update cache properties for marvell
2022-10-31 9:20 ` Pierre Gondois
@ 2022-10-31 20:12 ` Chris Packham
-1 siblings, 0 replies; 8+ messages in thread
From: Chris Packham @ 2022-10-31 20:12 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob.Herring, Rob Herring, Krzysztof Kozlowski, Andrew Lunn,
Gregory Clement, Sebastian Hesselbarth, Vadym Kochan, devicetree,
linux-arm-kernel
On 31/10/22 22:20, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
For ac5-98dx25xx.dtsi
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
> arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
> 4 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> index 80b44c7df56a..d4770acec6ac 100644
> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -49,6 +49,7 @@ cpu1: cpu@1 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> index fcab5173fe67..990f70303fe6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> @@ -51,6 +51,7 @@ l2: l2-cache {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> index 3db427122f9e..a7b8e001cc9c 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
>
> l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
> };
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> index 68782f161f12..7740098fd108 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
>
> l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
> };
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 10/20] arm64: dts: Update cache properties for marvell
@ 2022-10-31 20:12 ` Chris Packham
0 siblings, 0 replies; 8+ messages in thread
From: Chris Packham @ 2022-10-31 20:12 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob.Herring, Rob Herring, Krzysztof Kozlowski, Andrew Lunn,
Gregory Clement, Sebastian Hesselbarth, Vadym Kochan, devicetree,
linux-arm-kernel
On 31/10/22 22:20, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
For ac5-98dx25xx.dtsi
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
> arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
> 4 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> index 80b44c7df56a..d4770acec6ac 100644
> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -49,6 +49,7 @@ cpu1: cpu@1 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> index fcab5173fe67..990f70303fe6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> @@ -51,6 +51,7 @@ l2: l2-cache {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> index 3db427122f9e..a7b8e001cc9c 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
>
> l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
> };
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> index 68782f161f12..7740098fd108 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
>
> l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
> };
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 10/20] arm64: dts: Update cache properties for marvell
2022-10-31 9:20 ` Pierre Gondois
@ 2022-11-02 20:47 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:47 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob.Herring, Rob Herring, Krzysztof Kozlowski, Andrew Lunn,
Gregory Clement, Sebastian Hesselbarth, Vadym Kochan,
Chris Packham, devicetree, linux-arm-kernel
On 31/10/2022 05:20, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Your threading is broken.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 10/20] arm64: dts: Update cache properties for marvell
@ 2022-11-02 20:47 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-02 20:47 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: Rob.Herring, Rob Herring, Krzysztof Kozlowski, Andrew Lunn,
Gregory Clement, Sebastian Hesselbarth, Vadym Kochan,
Chris Packham, devicetree, linux-arm-kernel
On 31/10/2022 05:20, Pierre Gondois wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Your threading is broken.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 10/20] arm64: dts: Update cache properties for marvell
2022-10-31 9:20 ` Pierre Gondois
@ 2022-11-28 0:09 ` Gregory CLEMENT
-1 siblings, 0 replies; 8+ messages in thread
From: Gregory CLEMENT @ 2022-11-28 0:09 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: pierre.gondois, Rob.Herring, Rob Herring, Krzysztof Kozlowski,
Andrew Lunn, Sebastian Hesselbarth, Vadym Kochan, Chris Packham,
devicetree, linux-arm-kernel
Pierre Gondois <pierre.gondois@arm.com> writes:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
> arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
> 4 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> index 80b44c7df56a..d4770acec6ac 100644
> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -49,6 +49,7 @@ cpu1: cpu@1 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> index fcab5173fe67..990f70303fe6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> @@ -51,6 +51,7 @@ l2: l2-cache {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> index 3db427122f9e..a7b8e001cc9c 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
>
> l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
> };
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> index 68782f161f12..7740098fd108 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
>
> l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
> };
> --
> 2.25.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 10/20] arm64: dts: Update cache properties for marvell
@ 2022-11-28 0:09 ` Gregory CLEMENT
0 siblings, 0 replies; 8+ messages in thread
From: Gregory CLEMENT @ 2022-11-28 0:09 UTC (permalink / raw)
To: Pierre Gondois, linux-kernel
Cc: pierre.gondois, Rob.Herring, Rob Herring, Krzysztof Kozlowski,
Andrew Lunn, Sebastian Hesselbarth, Vadym Kochan, Chris Packham,
devicetree, linux-arm-kernel
Pierre Gondois <pierre.gondois@arm.com> writes:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>
> The recently added init_of_cache_level() function checks
> these properties. Add them if missing.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi | 2 ++
> arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi | 2 ++
> 4 files changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> index 80b44c7df56a..d4770acec6ac 100644
> --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -49,6 +49,7 @@ cpu1: cpu@1 {
>
> l2: l2-cache {
> compatible = "cache";
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> index fcab5173fe67..990f70303fe6 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
> @@ -51,6 +51,7 @@ l2: l2-cache {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> index 3db427122f9e..a7b8e001cc9c 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
>
> l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
> };
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> index 68782f161f12..7740098fd108 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
> @@ -81,6 +81,7 @@ l2_0: l2-cache0 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
>
> l2_1: l2-cache1 {
> @@ -88,6 +89,7 @@ l2_1: l2-cache1 {
> cache-size = <0x80000>;
> cache-line-size = <64>;
> cache-sets = <512>;
> + cache-level = <2>;
> };
> };
> };
> --
> 2.25.1
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-11-28 0:10 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-31 9:20 [PATCH 10/20] arm64: dts: Update cache properties for marvell Pierre Gondois
2022-10-31 9:20 ` Pierre Gondois
2022-10-31 20:12 ` Chris Packham
2022-10-31 20:12 ` Chris Packham
2022-11-02 20:47 ` Krzysztof Kozlowski
2022-11-02 20:47 ` Krzysztof Kozlowski
2022-11-28 0:09 ` Gregory CLEMENT
2022-11-28 0:09 ` Gregory CLEMENT
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