* [PATCH 0/3] Quartz64-A fixes and enablement from 5.17-rc1 @ 2022-01-27 1:00 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) Cc: Peter Geis, Rob Herring, Heiko Stuebner, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Good Evening, This is the first of several patch series for further expanding Quartz64-A support. This series has the following patches: Fix the ddr regulator voltage. Add pmu_io_domains to permit sdio and high speed emmc support. Add sdmmc1 node for wifi support. Please review and apply. Very Respectfully, Peter Geis Peter Geis (3): arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage arm64: dts: rockchip: add Quartz64-A pmu_io_domains arm64: dts: rockchip: add Quartz64-A sdmmc1 node .../boot/dts/rockchip/rk3566-quartz64-a.dts | 60 ++++++++++++++++++- 1 file changed, 58 insertions(+), 2 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 0/3] Quartz64-A fixes and enablement from 5.17-rc1 @ 2022-01-27 1:00 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) Cc: Peter Geis, Rob Herring, Heiko Stuebner, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Good Evening, This is the first of several patch series for further expanding Quartz64-A support. This series has the following patches: Fix the ddr regulator voltage. Add pmu_io_domains to permit sdio and high speed emmc support. Add sdmmc1 node for wifi support. Please review and apply. Very Respectfully, Peter Geis Peter Geis (3): arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage arm64: dts: rockchip: add Quartz64-A pmu_io_domains arm64: dts: rockchip: add Quartz64-A sdmmc1 node .../boot/dts/rockchip/rk3566-quartz64-a.dts | 60 ++++++++++++++++++- 1 file changed, 58 insertions(+), 2 deletions(-) -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 0/3] Quartz64-A fixes and enablement from 5.17-rc1 @ 2022-01-27 1:00 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) Cc: Peter Geis, Rob Herring, Heiko Stuebner, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Good Evening, This is the first of several patch series for further expanding Quartz64-A support. This series has the following patches: Fix the ddr regulator voltage. Add pmu_io_domains to permit sdio and high speed emmc support. Add sdmmc1 node for wifi support. Please review and apply. Very Respectfully, Peter Geis Peter Geis (3): arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage arm64: dts: rockchip: add Quartz64-A pmu_io_domains arm64: dts: rockchip: add Quartz64-A sdmmc1 node .../boot/dts/rockchip/rk3566-quartz64-a.dts | 60 ++++++++++++++++++- 1 file changed, 58 insertions(+), 2 deletions(-) -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/3] arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage 2022-01-27 1:00 ` Peter Geis (?) @ 2022-01-27 1:00 ` Peter Geis -1 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner, Peter Geis Cc: Rob Herring, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel The Quartz64 Model A uses a voltage divider to ensure ddr voltage is within specification from the default regulator configuration. Adjusting this voltage is detrimental, and currently causes the ddr voltage to be about 0.8v. Remove the min and max voltage setpoints for the ddr regulator. Fixes: b33a22a1e7c4 ("arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A") Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 166399b7f13f..d9eb92d59099 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -285,8 +285,6 @@ regulator-state-mem { vcc_ddr: DCDC_REG3 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; regulator-initial-mode = <0x2>; regulator-name = "vcc_ddr"; regulator-state-mem { -- 2.25.1 ^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 1/3] arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage @ 2022-01-27 1:00 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner, Peter Geis Cc: Rob Herring, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel The Quartz64 Model A uses a voltage divider to ensure ddr voltage is within specification from the default regulator configuration. Adjusting this voltage is detrimental, and currently causes the ddr voltage to be about 0.8v. Remove the min and max voltage setpoints for the ddr regulator. Fixes: b33a22a1e7c4 ("arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A") Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 166399b7f13f..d9eb92d59099 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -285,8 +285,6 @@ regulator-state-mem { vcc_ddr: DCDC_REG3 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; regulator-initial-mode = <0x2>; regulator-name = "vcc_ddr"; regulator-state-mem { -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 1/3] arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage @ 2022-01-27 1:00 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner, Peter Geis Cc: Rob Herring, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel The Quartz64 Model A uses a voltage divider to ensure ddr voltage is within specification from the default regulator configuration. Adjusting this voltage is detrimental, and currently causes the ddr voltage to be about 0.8v. Remove the min and max voltage setpoints for the ddr regulator. Fixes: b33a22a1e7c4 ("arm64: dts: rockchip: add basic dts for Pine64 Quartz64-A") Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 166399b7f13f..d9eb92d59099 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -285,8 +285,6 @@ regulator-state-mem { vcc_ddr: DCDC_REG3 { regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; regulator-initial-mode = <0x2>; regulator-name = "vcc_ddr"; regulator-state-mem { -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains 2022-01-27 1:00 ` Peter Geis (?) @ 2022-01-27 1:00 ` Peter Geis -1 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner Cc: Peter Geis, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Several io power domains on the Quartz64-A operate at 1.8v. Add the pmu_io_domains definition to enable support for this. This permits the enablement of the following features: sdio - wifi support sdhci - mmc-hs200-1_8v Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index d9eb92d59099..33c2c18caaa9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h { }; }; +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + &sdhci { bus-width = <8>; mmc-hs200-1_8v; -- 2.25.1 ^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains @ 2022-01-27 1:00 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner Cc: Peter Geis, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Several io power domains on the Quartz64-A operate at 1.8v. Add the pmu_io_domains definition to enable support for this. This permits the enablement of the following features: sdio - wifi support sdhci - mmc-hs200-1_8v Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index d9eb92d59099..33c2c18caaa9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h { }; }; +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + &sdhci { bus-width = <8>; mmc-hs200-1_8v; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains @ 2022-01-27 1:00 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner Cc: Peter Geis, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Several io power domains on the Quartz64-A operate at 1.8v. Add the pmu_io_domains definition to enable support for this. This permits the enablement of the following features: sdio - wifi support sdhci - mmc-hs200-1_8v Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index d9eb92d59099..33c2c18caaa9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h { }; }; +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + &sdhci { bus-width = <8>; mmc-hs200-1_8v; -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains 2022-01-27 1:00 ` Peter Geis (?) @ 2022-01-27 5:57 ` Johan Jonker -1 siblings, 0 replies; 30+ messages in thread From: Johan Jonker @ 2022-01-27 5:57 UTC (permalink / raw) To: Peter Geis, Rob Herring, Heiko Stuebner Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Hi Peter, On 1/27/22 02:00, Peter Geis wrote: > Several io power domains on the Quartz64-A operate at 1.8v. > Add the pmu_io_domains definition to enable support for this. > This permits the enablement of the following features: > sdio - wifi support > sdhci - mmc-hs200-1_8v > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > index d9eb92d59099..33c2c18caaa9 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > @@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h { > }; > }; > https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Could you check with the IO Power Domain Map? > +&pmu_io_domains { > + pmuio1-supply = <&vcc3v3_pmu>; VCC3V3_PMU > + pmuio2-supply = <&vcc3v3_pmu>; VCC3V3_PMU > + vccio1-supply = <&vccio_acodec>; VCCIO_ACODEC > + vccio2-supply = <&vcc_1v8>; VCC_1V8 > + vccio3-supply = <&vccio_sd>; VCCIO_SD > + vccio4-supply = <&vcc_1v8>; ==> VCC1V8_PMU > + vccio5-supply = <&vcc_3v3>; ==> VCC_1V8 > + vccio6-supply = <&vcc1v8_dvp>; VCC1V8_DVP > + vccio7-supply = <&vcc_3v3>; VCC_3V3 > + status = "okay"; > +}; > + > &sdhci { > bus-width = <8>; > mmc-hs200-1_8v; ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains @ 2022-01-27 5:57 ` Johan Jonker 0 siblings, 0 replies; 30+ messages in thread From: Johan Jonker @ 2022-01-27 5:57 UTC (permalink / raw) To: Peter Geis, Rob Herring, Heiko Stuebner Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Hi Peter, On 1/27/22 02:00, Peter Geis wrote: > Several io power domains on the Quartz64-A operate at 1.8v. > Add the pmu_io_domains definition to enable support for this. > This permits the enablement of the following features: > sdio - wifi support > sdhci - mmc-hs200-1_8v > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > index d9eb92d59099..33c2c18caaa9 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > @@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h { > }; > }; > https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Could you check with the IO Power Domain Map? > +&pmu_io_domains { > + pmuio1-supply = <&vcc3v3_pmu>; VCC3V3_PMU > + pmuio2-supply = <&vcc3v3_pmu>; VCC3V3_PMU > + vccio1-supply = <&vccio_acodec>; VCCIO_ACODEC > + vccio2-supply = <&vcc_1v8>; VCC_1V8 > + vccio3-supply = <&vccio_sd>; VCCIO_SD > + vccio4-supply = <&vcc_1v8>; ==> VCC1V8_PMU > + vccio5-supply = <&vcc_3v3>; ==> VCC_1V8 > + vccio6-supply = <&vcc1v8_dvp>; VCC1V8_DVP > + vccio7-supply = <&vcc_3v3>; VCC_3V3 > + status = "okay"; > +}; > + > &sdhci { > bus-width = <8>; > mmc-hs200-1_8v; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains @ 2022-01-27 5:57 ` Johan Jonker 0 siblings, 0 replies; 30+ messages in thread From: Johan Jonker @ 2022-01-27 5:57 UTC (permalink / raw) To: Peter Geis, Rob Herring, Heiko Stuebner Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Hi Peter, On 1/27/22 02:00, Peter Geis wrote: > Several io power domains on the Quartz64-A operate at 1.8v. > Add the pmu_io_domains definition to enable support for this. > This permits the enablement of the following features: > sdio - wifi support > sdhci - mmc-hs200-1_8v > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > index d9eb92d59099..33c2c18caaa9 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > @@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h { > }; > }; > https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf Could you check with the IO Power Domain Map? > +&pmu_io_domains { > + pmuio1-supply = <&vcc3v3_pmu>; VCC3V3_PMU > + pmuio2-supply = <&vcc3v3_pmu>; VCC3V3_PMU > + vccio1-supply = <&vccio_acodec>; VCCIO_ACODEC > + vccio2-supply = <&vcc_1v8>; VCC_1V8 > + vccio3-supply = <&vccio_sd>; VCCIO_SD > + vccio4-supply = <&vcc_1v8>; ==> VCC1V8_PMU > + vccio5-supply = <&vcc_3v3>; ==> VCC_1V8 > + vccio6-supply = <&vcc1v8_dvp>; VCC1V8_DVP > + vccio7-supply = <&vcc_3v3>; VCC_3V3 > + status = "okay"; > +}; > + > &sdhci { > bus-width = <8>; > mmc-hs200-1_8v; _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains 2022-01-27 5:57 ` Johan Jonker (?) @ 2022-01-27 9:52 ` Peter Geis -1 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 9:52 UTC (permalink / raw) To: Johan Jonker Cc: Rob Herring, Heiko Stuebner, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List On Thu, Jan 27, 2022 at 12:57 AM Johan Jonker <jbx6244@gmail.com> wrote: > > Hi Peter, Good Morning, The Rockchip schematics IO Power Domain Map is rarely *if ever* 100% accurate, you need to check the actual schematic for ground truth. > > On 1/27/22 02:00, Peter Geis wrote: > > Several io power domains on the Quartz64-A operate at 1.8v. > > Add the pmu_io_domains definition to enable support for this. > > This permits the enablement of the following features: > > sdio - wifi support > > sdhci - mmc-hs200-1_8v > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > index d9eb92d59099..33c2c18caaa9 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > @@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h { > > }; > > }; > > > > https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf > > Could you check with the IO Power Domain Map? > > > +&pmu_io_domains { > > + pmuio1-supply = <&vcc3v3_pmu>; > VCC3V3_PMU > > > + pmuio2-supply = <&vcc3v3_pmu>; > VCC3V3_PMU > > > + vccio1-supply = <&vccio_acodec>; > VCCIO_ACODEC > > > + vccio2-supply = <&vcc_1v8>; > VCC_1V8 > > > + vccio3-supply = <&vccio_sd>; > VCCIO_SD > > > + vccio4-supply = <&vcc_1v8>; > ==> VCC1V8_PMU Page 16 of the schematic, VCCIO4 is tied to VCC_1V8 via R1519 > > > + vccio5-supply = <&vcc_3v3>; > ==> VCC_1V8 Page 20 of the schematic, VCCIO5 is tied to VCC_3V3 via R1800 > > > + vccio6-supply = <&vcc1v8_dvp>; > VCC1V8_DVP > > > + vccio7-supply = <&vcc_3v3>; > VCC_3V3 > > > + status = "okay"; > > +}; > > + > > &sdhci { > > bus-width = <8>; > > mmc-hs200-1_8v; Thanks for double checking, Peter ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains @ 2022-01-27 9:52 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 9:52 UTC (permalink / raw) To: Johan Jonker Cc: Rob Herring, Heiko Stuebner, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List On Thu, Jan 27, 2022 at 12:57 AM Johan Jonker <jbx6244@gmail.com> wrote: > > Hi Peter, Good Morning, The Rockchip schematics IO Power Domain Map is rarely *if ever* 100% accurate, you need to check the actual schematic for ground truth. > > On 1/27/22 02:00, Peter Geis wrote: > > Several io power domains on the Quartz64-A operate at 1.8v. > > Add the pmu_io_domains definition to enable support for this. > > This permits the enablement of the following features: > > sdio - wifi support > > sdhci - mmc-hs200-1_8v > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > index d9eb92d59099..33c2c18caaa9 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > @@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h { > > }; > > }; > > > > https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf > > Could you check with the IO Power Domain Map? > > > +&pmu_io_domains { > > + pmuio1-supply = <&vcc3v3_pmu>; > VCC3V3_PMU > > > + pmuio2-supply = <&vcc3v3_pmu>; > VCC3V3_PMU > > > + vccio1-supply = <&vccio_acodec>; > VCCIO_ACODEC > > > + vccio2-supply = <&vcc_1v8>; > VCC_1V8 > > > + vccio3-supply = <&vccio_sd>; > VCCIO_SD > > > + vccio4-supply = <&vcc_1v8>; > ==> VCC1V8_PMU Page 16 of the schematic, VCCIO4 is tied to VCC_1V8 via R1519 > > > + vccio5-supply = <&vcc_3v3>; > ==> VCC_1V8 Page 20 of the schematic, VCCIO5 is tied to VCC_3V3 via R1800 > > > + vccio6-supply = <&vcc1v8_dvp>; > VCC1V8_DVP > > > + vccio7-supply = <&vcc_3v3>; > VCC_3V3 > > > + status = "okay"; > > +}; > > + > > &sdhci { > > bus-width = <8>; > > mmc-hs200-1_8v; Thanks for double checking, Peter _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains @ 2022-01-27 9:52 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 9:52 UTC (permalink / raw) To: Johan Jonker Cc: Rob Herring, Heiko Stuebner, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List On Thu, Jan 27, 2022 at 12:57 AM Johan Jonker <jbx6244@gmail.com> wrote: > > Hi Peter, Good Morning, The Rockchip schematics IO Power Domain Map is rarely *if ever* 100% accurate, you need to check the actual schematic for ground truth. > > On 1/27/22 02:00, Peter Geis wrote: > > Several io power domains on the Quartz64-A operate at 1.8v. > > Add the pmu_io_domains definition to enable support for this. > > This permits the enablement of the following features: > > sdio - wifi support > > sdhci - mmc-hs200-1_8v > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > index d9eb92d59099..33c2c18caaa9 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > @@ -482,6 +482,19 @@ vcc_sd_h: vcc-sd-h { > > }; > > }; > > > > https://files.pine64.org/doc/quartz64/Quartz64_model-A_schematic_v2.0_20210427.pdf > > Could you check with the IO Power Domain Map? > > > +&pmu_io_domains { > > + pmuio1-supply = <&vcc3v3_pmu>; > VCC3V3_PMU > > > + pmuio2-supply = <&vcc3v3_pmu>; > VCC3V3_PMU > > > + vccio1-supply = <&vccio_acodec>; > VCCIO_ACODEC > > > + vccio2-supply = <&vcc_1v8>; > VCC_1V8 > > > + vccio3-supply = <&vccio_sd>; > VCCIO_SD > > > + vccio4-supply = <&vcc_1v8>; > ==> VCC1V8_PMU Page 16 of the schematic, VCCIO4 is tied to VCC_1V8 via R1519 > > > + vccio5-supply = <&vcc_3v3>; > ==> VCC_1V8 Page 20 of the schematic, VCCIO5 is tied to VCC_3V3 via R1800 > > > + vccio6-supply = <&vcc1v8_dvp>; > VCC1V8_DVP > > > + vccio7-supply = <&vcc_3v3>; > VCC_3V3 > > > + status = "okay"; > > +}; > > + > > &sdhci { > > bus-width = <8>; > > mmc-hs200-1_8v; Thanks for double checking, Peter _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node 2022-01-27 1:00 ` Peter Geis (?) @ 2022-01-27 1:00 ` Peter Geis -1 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner Cc: Peter Geis, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel The sdmmc1 node on Quartz64-A supports the optional wifi module from Pine64. Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on the Quartz64-A. Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 33c2c18caaa9..1d73ac6557c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -91,6 +91,18 @@ simple-audio-card,codec { }; }; + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + }; + vcc12v_dcin: vcc12v_dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -147,6 +159,17 @@ vcc_sys: vcc_sys { regulator-max-microvolt = <4400000>; vin-supply = <&vbus>; }; + + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ + vcc_wl: vcc_wl { + compatible = "regulator-fixed"; + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; }; &cpu0 { @@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l { }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc_sd { vcc_sd_h: vcc-sd-h { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -516,6 +545,22 @@ &sdmmc0 { status = "okay"; }; +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + &spdif { status = "okay"; }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 1:00 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner Cc: Peter Geis, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel The sdmmc1 node on Quartz64-A supports the optional wifi module from Pine64. Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on the Quartz64-A. Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 33c2c18caaa9..1d73ac6557c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -91,6 +91,18 @@ simple-audio-card,codec { }; }; + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + }; + vcc12v_dcin: vcc12v_dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -147,6 +159,17 @@ vcc_sys: vcc_sys { regulator-max-microvolt = <4400000>; vin-supply = <&vbus>; }; + + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ + vcc_wl: vcc_wl { + compatible = "regulator-fixed"; + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; }; &cpu0 { @@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l { }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc_sd { vcc_sd_h: vcc-sd-h { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -516,6 +545,22 @@ &sdmmc0 { status = "okay"; }; +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + &spdif { status = "okay"; }; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 1:00 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 1:00 UTC (permalink / raw) To: Rob Herring, Heiko Stuebner Cc: Peter Geis, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel The sdmmc1 node on Quartz64-A supports the optional wifi module from Pine64. Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on the Quartz64-A. Signed-off-by: Peter Geis <pgwipeout@gmail.com> --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 33c2c18caaa9..1d73ac6557c5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -91,6 +91,18 @@ simple-audio-card,codec { }; }; + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + }; + vcc12v_dcin: vcc12v_dcin { compatible = "regulator-fixed"; regulator-name = "vcc12v_dcin"; @@ -147,6 +159,17 @@ vcc_sys: vcc_sys { regulator-max-microvolt = <4400000>; vin-supply = <&vbus>; }; + + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ + vcc_wl: vcc_wl { + compatible = "regulator-fixed"; + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; }; &cpu0 { @@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l { }; }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc_sd { vcc_sd_h: vcc-sd-h { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -516,6 +545,22 @@ &sdmmc0 { status = "okay"; }; +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + &spdif { status = "okay"; }; -- 2.25.1 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node 2022-01-27 1:00 ` Peter Geis (?) @ 2022-01-27 6:18 ` Johan Jonker -1 siblings, 0 replies; 30+ messages in thread From: Johan Jonker @ 2022-01-27 6:18 UTC (permalink / raw) To: Peter Geis, Rob Herring, Heiko Stuebner Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 1/27/22 02:00, Peter Geis wrote: > The sdmmc1 node on Quartz64-A supports the optional wifi module from > Pine64. > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > the Quartz64-A. > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > index 33c2c18caaa9..1d73ac6557c5 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > @@ -91,6 +91,18 @@ simple-audio-card,codec { > }; > }; > > + sdio_pwrseq: sdio-pwrseq { > + status = "okay"; When a node is not previously disabled, then there's no need for "okay". > + compatible = "mmc-pwrseq-simple"; > + clocks = <&rk817 1>; > + clock-names = "ext_clock"; > + pinctrl-names = "default"; > + pinctrl-0 = <&wifi_enable_h>; > + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; > + post-power-on-delay-ms = <100>; > + power-off-delay-us = <5000000>; > + }; > + > vcc12v_dcin: vcc12v_dcin { > compatible = "regulator-fixed"; > regulator-name = "vcc12v_dcin"; > @@ -147,6 +159,17 @@ vcc_sys: vcc_sys { > regulator-max-microvolt = <4400000>; > vin-supply = <&vbus>; > }; > + > + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ > + vcc_wl: vcc_wl { > + compatible = "regulator-fixed"; > + regulator-name = "vcc_wl"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + vin-supply = <&vcc_sys>; > + }; > }; > > &cpu0 { > @@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l { > }; > }; > > + sdio-pwrseq { > + wifi_enable_h: wifi-enable-h { > + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > + > vcc_sd { > vcc_sd_h: vcc-sd-h { > rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; > @@ -516,6 +545,22 @@ &sdmmc0 { > status = "okay"; > }; > > +&sdmmc1 { > + bus-width = <4>; > + cap-sd-highspeed; > + cap-sdio-irq; > + disable-wp; From mmc-controller.yaml: disable-wp: $ref: /schemas/types.yaml#/definitions/flag description: When set, no physical write-protect line is present. This property should only be specified when the controller has a dedicated write-protect detection logic. If a GPIO is always used for the write-protect detection logic, it is sufficient to not specify the wp-gpios property in the absence of a write-protect line. Not used in combination with eMMC or SDIO. > + keep-power-in-suspend; > + mmc-pwrseq = <&sdio_pwrseq>; > + non-removable; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; > + sd-uhs-sdr104; > + vmmc-supply = <&vcc_wl>; > + vqmmc-supply = <&vcc_1v8>; > + status = "okay"; > +}; > + > &spdif { > status = "okay"; > }; ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 6:18 ` Johan Jonker 0 siblings, 0 replies; 30+ messages in thread From: Johan Jonker @ 2022-01-27 6:18 UTC (permalink / raw) To: Peter Geis, Rob Herring, Heiko Stuebner Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 1/27/22 02:00, Peter Geis wrote: > The sdmmc1 node on Quartz64-A supports the optional wifi module from > Pine64. > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > the Quartz64-A. > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > index 33c2c18caaa9..1d73ac6557c5 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > @@ -91,6 +91,18 @@ simple-audio-card,codec { > }; > }; > > + sdio_pwrseq: sdio-pwrseq { > + status = "okay"; When a node is not previously disabled, then there's no need for "okay". > + compatible = "mmc-pwrseq-simple"; > + clocks = <&rk817 1>; > + clock-names = "ext_clock"; > + pinctrl-names = "default"; > + pinctrl-0 = <&wifi_enable_h>; > + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; > + post-power-on-delay-ms = <100>; > + power-off-delay-us = <5000000>; > + }; > + > vcc12v_dcin: vcc12v_dcin { > compatible = "regulator-fixed"; > regulator-name = "vcc12v_dcin"; > @@ -147,6 +159,17 @@ vcc_sys: vcc_sys { > regulator-max-microvolt = <4400000>; > vin-supply = <&vbus>; > }; > + > + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ > + vcc_wl: vcc_wl { > + compatible = "regulator-fixed"; > + regulator-name = "vcc_wl"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + vin-supply = <&vcc_sys>; > + }; > }; > > &cpu0 { > @@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l { > }; > }; > > + sdio-pwrseq { > + wifi_enable_h: wifi-enable-h { > + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > + > vcc_sd { > vcc_sd_h: vcc-sd-h { > rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; > @@ -516,6 +545,22 @@ &sdmmc0 { > status = "okay"; > }; > > +&sdmmc1 { > + bus-width = <4>; > + cap-sd-highspeed; > + cap-sdio-irq; > + disable-wp; From mmc-controller.yaml: disable-wp: $ref: /schemas/types.yaml#/definitions/flag description: When set, no physical write-protect line is present. This property should only be specified when the controller has a dedicated write-protect detection logic. If a GPIO is always used for the write-protect detection logic, it is sufficient to not specify the wp-gpios property in the absence of a write-protect line. Not used in combination with eMMC or SDIO. > + keep-power-in-suspend; > + mmc-pwrseq = <&sdio_pwrseq>; > + non-removable; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; > + sd-uhs-sdr104; > + vmmc-supply = <&vcc_wl>; > + vqmmc-supply = <&vcc_1v8>; > + status = "okay"; > +}; > + > &spdif { > status = "okay"; > }; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 6:18 ` Johan Jonker 0 siblings, 0 replies; 30+ messages in thread From: Johan Jonker @ 2022-01-27 6:18 UTC (permalink / raw) To: Peter Geis, Rob Herring, Heiko Stuebner Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 1/27/22 02:00, Peter Geis wrote: > The sdmmc1 node on Quartz64-A supports the optional wifi module from > Pine64. > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > the Quartz64-A. > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > index 33c2c18caaa9..1d73ac6557c5 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > @@ -91,6 +91,18 @@ simple-audio-card,codec { > }; > }; > > + sdio_pwrseq: sdio-pwrseq { > + status = "okay"; When a node is not previously disabled, then there's no need for "okay". > + compatible = "mmc-pwrseq-simple"; > + clocks = <&rk817 1>; > + clock-names = "ext_clock"; > + pinctrl-names = "default"; > + pinctrl-0 = <&wifi_enable_h>; > + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; > + post-power-on-delay-ms = <100>; > + power-off-delay-us = <5000000>; > + }; > + > vcc12v_dcin: vcc12v_dcin { > compatible = "regulator-fixed"; > regulator-name = "vcc12v_dcin"; > @@ -147,6 +159,17 @@ vcc_sys: vcc_sys { > regulator-max-microvolt = <4400000>; > vin-supply = <&vbus>; > }; > + > + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ > + vcc_wl: vcc_wl { > + compatible = "regulator-fixed"; > + regulator-name = "vcc_wl"; > + regulator-always-on; > + regulator-boot-on; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + vin-supply = <&vcc_sys>; > + }; > }; > > &cpu0 { > @@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l { > }; > }; > > + sdio-pwrseq { > + wifi_enable_h: wifi-enable-h { > + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + }; > + > vcc_sd { > vcc_sd_h: vcc-sd-h { > rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; > @@ -516,6 +545,22 @@ &sdmmc0 { > status = "okay"; > }; > > +&sdmmc1 { > + bus-width = <4>; > + cap-sd-highspeed; > + cap-sdio-irq; > + disable-wp; From mmc-controller.yaml: disable-wp: $ref: /schemas/types.yaml#/definitions/flag description: When set, no physical write-protect line is present. This property should only be specified when the controller has a dedicated write-protect detection logic. If a GPIO is always used for the write-protect detection logic, it is sufficient to not specify the wp-gpios property in the absence of a write-protect line. Not used in combination with eMMC or SDIO. > + keep-power-in-suspend; > + mmc-pwrseq = <&sdio_pwrseq>; > + non-removable; > + pinctrl-names = "default"; > + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; > + sd-uhs-sdr104; > + vmmc-supply = <&vcc_wl>; > + vqmmc-supply = <&vcc_1v8>; > + status = "okay"; > +}; > + > &spdif { > status = "okay"; > }; _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node 2022-01-27 6:18 ` Johan Jonker (?) @ 2022-01-27 9:55 ` Peter Geis -1 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 9:55 UTC (permalink / raw) To: Johan Jonker Cc: Rob Herring, Heiko Stuebner, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List On Thu, Jan 27, 2022 at 1:18 AM Johan Jonker <jbx6244@gmail.com> wrote: > > > > On 1/27/22 02:00, Peter Geis wrote: > > The sdmmc1 node on Quartz64-A supports the optional wifi module from > > Pine64. > > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > > the Quartz64-A. > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > > 1 file changed, 45 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > index 33c2c18caaa9..1d73ac6557c5 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > @@ -91,6 +91,18 @@ simple-audio-card,codec { > > }; > > }; > > > > + sdio_pwrseq: sdio-pwrseq { > > > + status = "okay"; > > When a node is not previously disabled, then there's no need for "okay". Thanks, this is here in case an end user wants to easily hack the board to use this for other purposes. > > > + compatible = "mmc-pwrseq-simple"; > > + clocks = <&rk817 1>; > > + clock-names = "ext_clock"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&wifi_enable_h>; > > + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; > > + post-power-on-delay-ms = <100>; > > + power-off-delay-us = <5000000>; > > + }; > > + > > vcc12v_dcin: vcc12v_dcin { > > compatible = "regulator-fixed"; > > regulator-name = "vcc12v_dcin"; > > @@ -147,6 +159,17 @@ vcc_sys: vcc_sys { > > regulator-max-microvolt = <4400000>; > > vin-supply = <&vbus>; > > }; > > + > > + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ > > + vcc_wl: vcc_wl { > > + compatible = "regulator-fixed"; > > + regulator-name = "vcc_wl"; > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + vin-supply = <&vcc_sys>; > > + }; > > }; > > > > &cpu0 { > > @@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l { > > }; > > }; > > > > + sdio-pwrseq { > > + wifi_enable_h: wifi-enable-h { > > + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; > > + }; > > + }; > > + > > vcc_sd { > > vcc_sd_h: vcc-sd-h { > > rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; > > @@ -516,6 +545,22 @@ &sdmmc0 { > > status = "okay"; > > }; > > > > +&sdmmc1 { > > + bus-width = <4>; > > + cap-sd-highspeed; > > + cap-sdio-irq; > > > + disable-wp; > > From mmc-controller.yaml: > > disable-wp: > $ref: /schemas/types.yaml#/definitions/flag > description: > When set, no physical write-protect line is present. This > property should only be specified when the controller has a > dedicated write-protect detection logic. If a GPIO is always used > for the write-protect detection logic, it is sufficient to not > specify the wp-gpios property in the absence of a write-protect > line. Not used in combination with eMMC or SDIO. Appreciate it, I will drop this. > > > + keep-power-in-suspend; > > + mmc-pwrseq = <&sdio_pwrseq>; > > + non-removable; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; > > + sd-uhs-sdr104; > > + vmmc-supply = <&vcc_wl>; > > + vqmmc-supply = <&vcc_1v8>; > > + status = "okay"; > > +}; > > + > > &spdif { > > status = "okay"; > > }; ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 9:55 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 9:55 UTC (permalink / raw) To: Johan Jonker Cc: Rob Herring, Heiko Stuebner, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List On Thu, Jan 27, 2022 at 1:18 AM Johan Jonker <jbx6244@gmail.com> wrote: > > > > On 1/27/22 02:00, Peter Geis wrote: > > The sdmmc1 node on Quartz64-A supports the optional wifi module from > > Pine64. > > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > > the Quartz64-A. > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > > 1 file changed, 45 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > index 33c2c18caaa9..1d73ac6557c5 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > @@ -91,6 +91,18 @@ simple-audio-card,codec { > > }; > > }; > > > > + sdio_pwrseq: sdio-pwrseq { > > > + status = "okay"; > > When a node is not previously disabled, then there's no need for "okay". Thanks, this is here in case an end user wants to easily hack the board to use this for other purposes. > > > + compatible = "mmc-pwrseq-simple"; > > + clocks = <&rk817 1>; > > + clock-names = "ext_clock"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&wifi_enable_h>; > > + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; > > + post-power-on-delay-ms = <100>; > > + power-off-delay-us = <5000000>; > > + }; > > + > > vcc12v_dcin: vcc12v_dcin { > > compatible = "regulator-fixed"; > > regulator-name = "vcc12v_dcin"; > > @@ -147,6 +159,17 @@ vcc_sys: vcc_sys { > > regulator-max-microvolt = <4400000>; > > vin-supply = <&vbus>; > > }; > > + > > + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ > > + vcc_wl: vcc_wl { > > + compatible = "regulator-fixed"; > > + regulator-name = "vcc_wl"; > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + vin-supply = <&vcc_sys>; > > + }; > > }; > > > > &cpu0 { > > @@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l { > > }; > > }; > > > > + sdio-pwrseq { > > + wifi_enable_h: wifi-enable-h { > > + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; > > + }; > > + }; > > + > > vcc_sd { > > vcc_sd_h: vcc-sd-h { > > rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; > > @@ -516,6 +545,22 @@ &sdmmc0 { > > status = "okay"; > > }; > > > > +&sdmmc1 { > > + bus-width = <4>; > > + cap-sd-highspeed; > > + cap-sdio-irq; > > > + disable-wp; > > From mmc-controller.yaml: > > disable-wp: > $ref: /schemas/types.yaml#/definitions/flag > description: > When set, no physical write-protect line is present. This > property should only be specified when the controller has a > dedicated write-protect detection logic. If a GPIO is always used > for the write-protect detection logic, it is sufficient to not > specify the wp-gpios property in the absence of a write-protect > line. Not used in combination with eMMC or SDIO. Appreciate it, I will drop this. > > > + keep-power-in-suspend; > > + mmc-pwrseq = <&sdio_pwrseq>; > > + non-removable; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; > > + sd-uhs-sdr104; > > + vmmc-supply = <&vcc_wl>; > > + vqmmc-supply = <&vcc_1v8>; > > + status = "okay"; > > +}; > > + > > &spdif { > > status = "okay"; > > }; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 9:55 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 9:55 UTC (permalink / raw) To: Johan Jonker Cc: Rob Herring, Heiko Stuebner, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List On Thu, Jan 27, 2022 at 1:18 AM Johan Jonker <jbx6244@gmail.com> wrote: > > > > On 1/27/22 02:00, Peter Geis wrote: > > The sdmmc1 node on Quartz64-A supports the optional wifi module from > > Pine64. > > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > > the Quartz64-A. > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > > 1 file changed, 45 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > index 33c2c18caaa9..1d73ac6557c5 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > @@ -91,6 +91,18 @@ simple-audio-card,codec { > > }; > > }; > > > > + sdio_pwrseq: sdio-pwrseq { > > > + status = "okay"; > > When a node is not previously disabled, then there's no need for "okay". Thanks, this is here in case an end user wants to easily hack the board to use this for other purposes. > > > + compatible = "mmc-pwrseq-simple"; > > + clocks = <&rk817 1>; > > + clock-names = "ext_clock"; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&wifi_enable_h>; > > + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; > > + post-power-on-delay-ms = <100>; > > + power-off-delay-us = <5000000>; > > + }; > > + > > vcc12v_dcin: vcc12v_dcin { > > compatible = "regulator-fixed"; > > regulator-name = "vcc12v_dcin"; > > @@ -147,6 +159,17 @@ vcc_sys: vcc_sys { > > regulator-max-microvolt = <4400000>; > > vin-supply = <&vbus>; > > }; > > + > > + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ > > + vcc_wl: vcc_wl { > > + compatible = "regulator-fixed"; > > + regulator-name = "vcc_wl"; > > + regulator-always-on; > > + regulator-boot-on; > > + regulator-min-microvolt = <3300000>; > > + regulator-max-microvolt = <3300000>; > > + vin-supply = <&vcc_sys>; > > + }; > > }; > > > > &cpu0 { > > @@ -475,6 +498,12 @@ pmic_int_l: pmic-int-l { > > }; > > }; > > > > + sdio-pwrseq { > > + wifi_enable_h: wifi-enable-h { > > + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; > > + }; > > + }; > > + > > vcc_sd { > > vcc_sd_h: vcc-sd-h { > > rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; > > @@ -516,6 +545,22 @@ &sdmmc0 { > > status = "okay"; > > }; > > > > +&sdmmc1 { > > + bus-width = <4>; > > + cap-sd-highspeed; > > + cap-sdio-irq; > > > + disable-wp; > > From mmc-controller.yaml: > > disable-wp: > $ref: /schemas/types.yaml#/definitions/flag > description: > When set, no physical write-protect line is present. This > property should only be specified when the controller has a > dedicated write-protect detection logic. If a GPIO is always used > for the write-protect detection logic, it is sufficient to not > specify the wp-gpios property in the absence of a write-protect > line. Not used in combination with eMMC or SDIO. Appreciate it, I will drop this. > > > + keep-power-in-suspend; > > + mmc-pwrseq = <&sdio_pwrseq>; > > + non-removable; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; > > + sd-uhs-sdr104; > > + vmmc-supply = <&vcc_wl>; > > + vqmmc-supply = <&vcc_1v8>; > > + status = "okay"; > > +}; > > + > > &spdif { > > status = "okay"; > > }; _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node 2022-01-27 9:55 ` Peter Geis (?) @ 2022-01-27 10:15 ` Heiko Stübner -1 siblings, 0 replies; 30+ messages in thread From: Heiko Stübner @ 2022-01-27 10:15 UTC (permalink / raw) To: Johan Jonker, Peter Geis Cc: Rob Herring, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List Am Donnerstag, 27. Januar 2022, 10:55:13 CET schrieb Peter Geis: > On Thu, Jan 27, 2022 at 1:18 AM Johan Jonker <jbx6244@gmail.com> wrote: > > > > > > > > On 1/27/22 02:00, Peter Geis wrote: > > > The sdmmc1 node on Quartz64-A supports the optional wifi module from > > > Pine64. > > > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > > > the Quartz64-A. > > > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > > --- > > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > > > 1 file changed, 45 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > index 33c2c18caaa9..1d73ac6557c5 100644 > > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > @@ -91,6 +91,18 @@ simple-audio-card,codec { > > > }; > > > }; > > > > > > + sdio_pwrseq: sdio-pwrseq { > > > > > + status = "okay"; > > > > When a node is not previously disabled, then there's no need for "okay". > > Thanks, this is here in case an end user wants to easily hack the > board to use this for other purposes. but please drop it here as well. A user "hacking" a devicetree should be able to also just _add_ a status "disabled" :-) . ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 10:15 ` Heiko Stübner 0 siblings, 0 replies; 30+ messages in thread From: Heiko Stübner @ 2022-01-27 10:15 UTC (permalink / raw) To: Johan Jonker, Peter Geis Cc: Rob Herring, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List Am Donnerstag, 27. Januar 2022, 10:55:13 CET schrieb Peter Geis: > On Thu, Jan 27, 2022 at 1:18 AM Johan Jonker <jbx6244@gmail.com> wrote: > > > > > > > > On 1/27/22 02:00, Peter Geis wrote: > > > The sdmmc1 node on Quartz64-A supports the optional wifi module from > > > Pine64. > > > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > > > the Quartz64-A. > > > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > > --- > > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > > > 1 file changed, 45 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > index 33c2c18caaa9..1d73ac6557c5 100644 > > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > @@ -91,6 +91,18 @@ simple-audio-card,codec { > > > }; > > > }; > > > > > > + sdio_pwrseq: sdio-pwrseq { > > > > > + status = "okay"; > > > > When a node is not previously disabled, then there's no need for "okay". > > Thanks, this is here in case an end user wants to easily hack the > board to use this for other purposes. but please drop it here as well. A user "hacking" a devicetree should be able to also just _add_ a status "disabled" :-) . _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 10:15 ` Heiko Stübner 0 siblings, 0 replies; 30+ messages in thread From: Heiko Stübner @ 2022-01-27 10:15 UTC (permalink / raw) To: Johan Jonker, Peter Geis Cc: Rob Herring, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List Am Donnerstag, 27. Januar 2022, 10:55:13 CET schrieb Peter Geis: > On Thu, Jan 27, 2022 at 1:18 AM Johan Jonker <jbx6244@gmail.com> wrote: > > > > > > > > On 1/27/22 02:00, Peter Geis wrote: > > > The sdmmc1 node on Quartz64-A supports the optional wifi module from > > > Pine64. > > > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > > > the Quartz64-A. > > > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > > --- > > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > > > 1 file changed, 45 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > index 33c2c18caaa9..1d73ac6557c5 100644 > > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > @@ -91,6 +91,18 @@ simple-audio-card,codec { > > > }; > > > }; > > > > > > + sdio_pwrseq: sdio-pwrseq { > > > > > + status = "okay"; > > > > When a node is not previously disabled, then there's no need for "okay". > > Thanks, this is here in case an end user wants to easily hack the > board to use this for other purposes. but please drop it here as well. A user "hacking" a devicetree should be able to also just _add_ a status "disabled" :-) . _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node 2022-01-27 10:15 ` Heiko Stübner (?) @ 2022-01-27 23:32 ` Peter Geis -1 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 23:32 UTC (permalink / raw) To: Heiko Stübner Cc: Johan Jonker, Rob Herring, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List On Thu, Jan 27, 2022 at 5:15 AM Heiko Stübner <heiko@sntech.de> wrote: > > Am Donnerstag, 27. Januar 2022, 10:55:13 CET schrieb Peter Geis: > > On Thu, Jan 27, 2022 at 1:18 AM Johan Jonker <jbx6244@gmail.com> wrote: > > > > > > > > > > > > On 1/27/22 02:00, Peter Geis wrote: > > > > The sdmmc1 node on Quartz64-A supports the optional wifi module from > > > > Pine64. > > > > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > > > > the Quartz64-A. > > > > > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > > > --- > > > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > > > > 1 file changed, 45 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > > index 33c2c18caaa9..1d73ac6557c5 100644 > > > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > > @@ -91,6 +91,18 @@ simple-audio-card,codec { > > > > }; > > > > }; > > > > > > > > + sdio_pwrseq: sdio-pwrseq { > > > > > > > + status = "okay"; > > > > > > When a node is not previously disabled, then there's no need for "okay". > > > > Thanks, this is here in case an end user wants to easily hack the > > board to use this for other purposes. > > but please drop it here as well. > > A user "hacking" a devicetree should be able to also just _add_ > a status "disabled" :-) . Understood, will do. Thanks! > > ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 23:32 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 23:32 UTC (permalink / raw) To: Heiko Stübner Cc: Johan Jonker, Rob Herring, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List On Thu, Jan 27, 2022 at 5:15 AM Heiko Stübner <heiko@sntech.de> wrote: > > Am Donnerstag, 27. Januar 2022, 10:55:13 CET schrieb Peter Geis: > > On Thu, Jan 27, 2022 at 1:18 AM Johan Jonker <jbx6244@gmail.com> wrote: > > > > > > > > > > > > On 1/27/22 02:00, Peter Geis wrote: > > > > The sdmmc1 node on Quartz64-A supports the optional wifi module from > > > > Pine64. > > > > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > > > > the Quartz64-A. > > > > > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > > > --- > > > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > > > > 1 file changed, 45 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > > index 33c2c18caaa9..1d73ac6557c5 100644 > > > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > > @@ -91,6 +91,18 @@ simple-audio-card,codec { > > > > }; > > > > }; > > > > > > > > + sdio_pwrseq: sdio-pwrseq { > > > > > > > + status = "okay"; > > > > > > When a node is not previously disabled, then there's no need for "okay". > > > > Thanks, this is here in case an end user wants to easily hack the > > board to use this for other purposes. > > but please drop it here as well. > > A user "hacking" a devicetree should be able to also just _add_ > a status "disabled" :-) . Understood, will do. Thanks! > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node @ 2022-01-27 23:32 ` Peter Geis 0 siblings, 0 replies; 30+ messages in thread From: Peter Geis @ 2022-01-27 23:32 UTC (permalink / raw) To: Heiko Stübner Cc: Johan Jonker, Rob Herring, devicetree, arm-mail-list, open list:ARM/Rockchip SoC..., Linux Kernel Mailing List On Thu, Jan 27, 2022 at 5:15 AM Heiko Stübner <heiko@sntech.de> wrote: > > Am Donnerstag, 27. Januar 2022, 10:55:13 CET schrieb Peter Geis: > > On Thu, Jan 27, 2022 at 1:18 AM Johan Jonker <jbx6244@gmail.com> wrote: > > > > > > > > > > > > On 1/27/22 02:00, Peter Geis wrote: > > > > The sdmmc1 node on Quartz64-A supports the optional wifi module from > > > > Pine64. > > > > Add the sdmmc1 node and requisite sdio_pwrseq to enable wifi support on > > > > the Quartz64-A. > > > > > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > > > --- > > > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 45 +++++++++++++++++++ > > > > 1 file changed, 45 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > > index 33c2c18caaa9..1d73ac6557c5 100644 > > > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > > > @@ -91,6 +91,18 @@ simple-audio-card,codec { > > > > }; > > > > }; > > > > > > > > + sdio_pwrseq: sdio-pwrseq { > > > > > > > + status = "okay"; > > > > > > When a node is not previously disabled, then there's no need for "okay". > > > > Thanks, this is here in case an end user wants to easily hack the > > board to use this for other purposes. > > but please drop it here as well. > > A user "hacking" a devicetree should be able to also just _add_ > a status "disabled" :-) . Understood, will do. Thanks! > > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2022-01-27 23:34 UTC | newest] Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-01-27 1:00 [PATCH 0/3] Quartz64-A fixes and enablement from 5.17-rc1 Peter Geis 2022-01-27 1:00 ` Peter Geis 2022-01-27 1:00 ` Peter Geis 2022-01-27 1:00 ` [PATCH 1/3] arm64: dts: rockchip: fix Quartz64-A ddr regulator voltage Peter Geis 2022-01-27 1:00 ` Peter Geis 2022-01-27 1:00 ` Peter Geis 2022-01-27 1:00 ` [PATCH 2/3] arm64: dts: rockchip: add Quartz64-A pmu_io_domains Peter Geis 2022-01-27 1:00 ` Peter Geis 2022-01-27 1:00 ` Peter Geis 2022-01-27 5:57 ` Johan Jonker 2022-01-27 5:57 ` Johan Jonker 2022-01-27 5:57 ` Johan Jonker 2022-01-27 9:52 ` Peter Geis 2022-01-27 9:52 ` Peter Geis 2022-01-27 9:52 ` Peter Geis 2022-01-27 1:00 ` [PATCH 3/3] arm64: dts: rockchip: add Quartz64-A sdmmc1 node Peter Geis 2022-01-27 1:00 ` Peter Geis 2022-01-27 1:00 ` Peter Geis 2022-01-27 6:18 ` Johan Jonker 2022-01-27 6:18 ` Johan Jonker 2022-01-27 6:18 ` Johan Jonker 2022-01-27 9:55 ` Peter Geis 2022-01-27 9:55 ` Peter Geis 2022-01-27 9:55 ` Peter Geis 2022-01-27 10:15 ` Heiko Stübner 2022-01-27 10:15 ` Heiko Stübner 2022-01-27 10:15 ` Heiko Stübner 2022-01-27 23:32 ` Peter Geis 2022-01-27 23:32 ` Peter Geis 2022-01-27 23:32 ` Peter Geis
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