[PATCH v2 0/5] i915 pvmmio to improve GVTg performance

[PATCH v2 0/5] i915 pvmmio to improve GVTg performance

[Xiaolin Zhang]

To improve GVTg performance, it could reduce the mmio access trap
numbers within guest driver in some certain scenarios since mmio
access trap will introuduce vm exit/vm enter cost.

the solution in this patch set is to setup a shared memory region
which accessed both by guest and GVTg without trap cost. the shared
memory region is allocated by guest driver and guest driver will
pass the region's memory guest physical address to GVTg through
PVINFO register and later GVTg can access this region directly without
trap cost to achieve data exchange purpose between guest and GVTg.

in this patch set, 3 kind of pvmmio optimization implemented which is
controlled by enable_pvmmio PVINO register with different level flag.
1. workload submission (context submission): reduce 4 traps to 1 trap.
2. master irq: reduce 2 traps to 1 trap. 
3. ppgtt update: eliminate the cost of ppgtt write protection. 

based on the experiment, the performance was gained 4 percent (average)
improvment with regard to both media and 3D workload benchmarks.

based on the pvmmio framework, it could achive more sceneario optimization
such as globle GTT update, display plane and water mark update with guest.

v0: RFC patch set
v1: addressed RFC review comments
v2: addressed v1 review comments, added pv callbacks for pv operations

Xiaolin Zhang (5):
  drm/i915: introduced pv capability for vgpu
  drm/i915: get ready of memory for pvmmio
  drm/i915: context submission pvmmio optimization
  drm/i915: master irq pvmmio optimization
  drm/i915: ppgtt update pvmmio optimization

 drivers/gpu/drm/i915/i915_drv.c         |  2 +
 drivers/gpu/drm/i915/i915_drv.h         | 15 +++++-
 drivers/gpu/drm/i915/i915_gem_gtt.c     | 67 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_irq.c         | 82 ++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_pvinfo.h      | 43 +++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.c        | 44 ++++++++++++++++-
 drivers/gpu/drm/i915/intel_lrc.c        | 88 +++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_ringbuffer.h |  3 ++
 8 files changed, 333 insertions(+), 11 deletions(-)

-- 
2.7.4

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[PATCH v2 1/5] drm/i915: introduced pv capability for vgpu

[Xiaolin Zhang]

This u32 pv_caps field is used to control the different
level pvmmio feature for MMIO emulation in GVT.

This field is default zero, no pvmmio feature enabled.

it also add VGT_CAPS_PVMMIO capability BIT for guest to check GVTg
can support PV feature or not.

v0: RFC, introudced enable_pvmmio module parameter.
v1: addressed RFC comment to remove enable_pvmmio module parameter
by pv capability check.
v2: rebase

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    | 11 +++++++++++
 drivers/gpu/drm/i915/i915_pvinfo.h | 17 ++++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 19 +++++++++++++++++--
 3 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3017ef0..7b2d7cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -56,6 +56,7 @@
 
 #include "i915_params.h"
 #include "i915_reg.h"
+#include "i915_pvinfo.h"
 #include "i915_utils.h"
 
 #include "intel_bios.h"
@@ -1343,6 +1344,7 @@ struct i915_workarounds {
 struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
+	u32 pv_caps;
 };
 
 /* used in computing the new watermarks state */
@@ -2853,6 +2855,11 @@ static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.active;
 }
 
+static inline bool intel_vgpu_has_pvmmio(struct drm_i915_private *dev_priv)
+{
+	return dev_priv->vgpu.caps & VGT_CAPS_PVMMIO;
+}
+
 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 			      enum pipe pipe);
 void
@@ -3878,4 +3885,8 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
 		return I915_HWS_CSB_WRITE_INDEX;
 }
 
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level)	\
+	(intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+			&& (dev_priv->vgpu.pv_caps & level))
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d5..26709e8 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,12 +49,26 @@ enum vgt_g2v_type {
 	VGT_G2V_MAX,
 };
 
+#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
+
 /*
  * VGT capabilities type
  */
 #define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
+#define VGT_CAPS_PVMMIO		BIT(5)
+
+/*
+ * define different levels of PVMMIO optimization
+ */
+enum pvmmio_levels {
+	PVMMIO_ELSP_SUBMIT = 0x1,
+	PVMMIO_PLANE_UPDATE = 0x2,
+	PVMMIO_PLANE_WM_UPDATE = 0x4,
+	PVMMIO_MASTER_IRQ = 0x8,
+	PVMMIO_PPGTT_UPDATE = 0x10,
+};
 
 struct vgt_if {
 	u64 magic;		/* VGT_MAGIC */
@@ -106,8 +120,9 @@ struct vgt_if {
 
 	u32 execlist_context_descriptor_lo;
 	u32 execlist_context_descriptor_hi;
+	u32 enable_pvmmio;
 
-	u32  rsv7[0x200 - 24];    /* pad to one page */
+	u32  rsv7[0x200 - 25];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a..907bbd2 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -76,9 +76,24 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	}
 
 	dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
-
 	dev_priv->vgpu.active = true;
-	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+
+	if (!intel_vgpu_has_pvmmio(dev_priv)) {
+		DRM_INFO("Virtual GPU for Intel GVT-g detected\n");
+		return;
+	}
+
+	/* If guest wants to enable pvmmio, it needs to enable it explicitly
+	 * through vgt_if interface, and then read back the enable state from
+	 * gvt layer.
+	 */
+	__raw_i915_write32(dev_priv, vgtif_reg(enable_pvmmio),
+			dev_priv->vgpu.pv_caps);
+	dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
+			vgtif_reg(enable_pvmmio));
+
+	DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+			dev_priv->vgpu.pv_caps);
 }
 
 bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
-- 
2.7.4

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[PATCH v2 2/5] drm/i915: get ready of memory for pvmmio

[Xiaolin Zhang]

To enable pvmmio feature, we need to prepare one 4K shared page
which will be accessed by both guest and backend i915 driver.

guest i915 allocate one page memory and then the guest physical address is
passed to backend i915 driver through PVINFO register so that backend i915
driver can access this shared page without hypeviser trap cost for shared
data exchagne via hyperviser read_gpa functionality.

v0: RFC
v1: addressed RFC comment to move both shared_page_lock and shared_page
to i915_virtual_gpu structure
v2: packed i915_virtual_gpu structure

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c    |  2 ++
 drivers/gpu/drm/i915/i915_drv.h    |  4 +++-
 drivers/gpu/drm/i915/i915_pvinfo.h | 24 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 24 +++++++++++++++++++++++-
 4 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index baac35f..557ab67 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -987,6 +987,8 @@ static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 
 	intel_teardown_mchbar(dev_priv);
 	pci_iounmap(pdev, dev_priv->regs);
+	if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.shared_page)
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7b2d7cb..d7a972f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1345,7 +1345,9 @@ struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
 	u32 pv_caps;
-};
+	spinlock_t shared_page_lock;
+	struct gvt_shared_page *shared_page;
+} __packed;
 
 /* used in computing the new watermarks state */
 struct intel_wm_config {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 26709e8..179d558 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,6 +49,24 @@ enum vgt_g2v_type {
 	VGT_G2V_MAX,
 };
 
+struct pv_ppgtt_update {
+	u64 pdp;
+	u64 start;
+	u64 length;
+	u32 cache_level;
+};
+
+/*
+ * shared page(4KB) between gvt and VM, could be allocated by guest driver
+ * or a fixed location in PCI bar 0 region
+ */
+struct gvt_shared_page {
+	u32 elsp_data[4];
+	u32 reg_addr;
+	u32 disable_irq;
+	struct pv_ppgtt_update pv_ppgtt;
+};
+
 #define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
 
 /*
@@ -121,8 +139,12 @@ struct vgt_if {
 	u32 execlist_context_descriptor_lo;
 	u32 execlist_context_descriptor_hi;
 	u32 enable_pvmmio;
+	struct {
+		u32 lo;
+		u32 hi;
+	} shared_page_gpa;
 
-	u32  rsv7[0x200 - 25];    /* pad to one page */
+	u32  rsv7[0x200 - 27];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 907bbd2..cb409d5 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -62,6 +62,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 {
 	u64 magic;
 	u16 version_major;
+	u64 gpa;
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
@@ -91,7 +92,28 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 			dev_priv->vgpu.pv_caps);
 	dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
 			vgtif_reg(enable_pvmmio));
-
+	if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.pv_caps) {
+		dev_priv->vgpu.shared_page =  (struct gvt_shared_page *)
+				get_zeroed_page(GFP_KERNEL);
+		if (!dev_priv->vgpu.shared_page) {
+			DRM_ERROR("out of memory for shared page memory\n");
+			return;
+		}
+		gpa = __pa(dev_priv->vgpu.shared_page);
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.lo),
+				lower_32_bits(gpa));
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.hi),
+				upper_32_bits(gpa));
+		if (gpa != __raw_i915_read64(dev_priv,
+				vgtif_reg(shared_page_gpa))) {
+			DRM_ERROR("vgpu: passed shared_page_gpa failed\n");
+			free_page((unsigned long)dev_priv->vgpu.shared_page);
+			dev_priv->vgpu.pv_caps = 0;
+			return;
+		}
+		spin_lock_init(&dev_priv->vgpu.shared_page_lock);
+		DRM_INFO("VGPU shared page enabled\n");
+	}
 	DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
 			dev_priv->vgpu.pv_caps);
 }
-- 
2.7.4

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[PATCH v2 3/5] drm/i915: context submission pvmmio optimization

[Xiaolin Zhang]

It is performance optimization to reduce mmio trap numbers from 4 to
1 durning ELSP porting writing (context submission).

When context subission, to cache elsp_data[4] values in
the shared page, the last elsp_data[0] port writing will be trapped
to gvt for real context submission.

Use PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization.

v0: RFC
v1: rebase
v2: added pv ops for pv context submission. to maximize code resuse,
introduced 2 more ops (submit_ports & preempt_context) instead of 1 op
(set_default_submission) in engine structure. pv version of
submit_ports and preempt_context implemented.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_vgpu.c        |  2 +
 drivers/gpu/drm/i915/intel_lrc.c        | 88 +++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_ringbuffer.h |  3 ++
 3 files changed, 90 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index cb409d5..9870ea6 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,6 +66,8 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
+	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT;
+
 	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)
 		return;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8..9e6ccf9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -460,6 +460,60 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
 	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
+static void execlists_submit_ports_pv(struct intel_engine_cs *engine)
+{
+	struct intel_engine_execlists *execlists = &engine->execlists;
+	struct execlist_port *port = execlists->port;
+	u32 __iomem *elsp =
+		engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+	u32 *elsp_data;
+	unsigned int n;
+	u32 descs[4];
+	int i = 0;
+
+	/*
+	 * ELSQ note: the submit queue is not cleared after being submitted
+	 * to the HW so we need to make sure we always clean it up. This is
+	 * currently ensured by the fact that we always write the same number
+	 * of elsq entries, keep this in mind before changing the loop below.
+	 */
+	for (n = execlists_num_ports(execlists); n--; ) {
+		struct i915_request *rq;
+		unsigned int count;
+		u64 desc;
+
+		rq = port_unpack(&port[n], &count);
+		if (rq) {
+			GEM_BUG_ON(count > !n);
+			if (!count++)
+				execlists_context_schedule_in(rq);
+			port_set(&port[n], port_pack(rq, count));
+			desc = execlists_update_context(rq);
+		} else {
+			GEM_BUG_ON(!n);
+			desc = 0;
+		}
+		GEM_BUG_ON(i >= 4);
+		descs[i] = upper_32_bits(desc);
+		descs[i + 1] = lower_32_bits(desc);
+		i += 2;
+	}
+
+	spin_lock(&engine->i915->vgpu.shared_page_lock);
+	elsp_data = engine->i915->vgpu.shared_page->elsp_data;
+	*elsp_data = descs[0];
+	*(elsp_data + 1) = descs[1];
+	*(elsp_data + 2) = descs[2];
+	writel(descs[3], elsp);
+	spin_unlock(&engine->i915->vgpu.shared_page_lock);
+
+	/* we need to manually load the submit queue */
+	if (execlists->ctrl_reg)
+		writel(EL_CTRL_LOAD, execlists->ctrl_reg);
+
+	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
+}
+
 static bool ctx_single_port_submission(const struct intel_context *ce)
 {
 	return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
@@ -497,7 +551,6 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
 
 	GEM_BUG_ON(execlists->preempt_complete_status !=
 		   upper_32_bits(ce->lrc_desc));
-
 	/*
 	 * Switch to our empty preempt context so
 	 * the state of the GPU is known (idle).
@@ -516,6 +569,27 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
 	execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
 }
 
+static void inject_preempt_context_pv(struct intel_engine_cs *engine)
+{
+	struct intel_engine_execlists *execlists = &engine->execlists;
+	struct intel_context *ce =
+		to_intel_context(engine->i915->preempt_context, engine);
+	u32 __iomem *elsp =
+		engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+	u32 *elsp_data;
+
+	GEM_BUG_ON(execlists->preempt_complete_status !=
+		   upper_32_bits(ce->lrc_desc));
+
+	spin_lock(&engine->i915->vgpu.shared_page_lock);
+	elsp_data = engine->i915->vgpu.shared_page->elsp_data;
+	*elsp_data = 0;
+	*(elsp_data + 1) = 0;
+	*(elsp_data + 2) = upper_32_bits(ce->lrc_desc);
+	writel(lower_32_bits(ce->lrc_desc), elsp);
+	spin_unlock(&engine->i915->vgpu.shared_page_lock);
+}
+
 static void complete_preempt_context(struct intel_engine_execlists *execlists)
 {
 	GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
@@ -583,7 +657,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 			return;
 
 		if (need_preempt(engine, last, execlists->queue_priority)) {
-			inject_preempt_context(engine);
+			engine->preempt_context(engine);
 			return;
 		}
 
@@ -705,7 +779,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 
 	if (submit) {
 		port_assign(port, last);
-		execlists_submit_ports(engine);
+		engine->submit_ports(engine);
 	}
 
 	/* We must always keep the beast fed if we have work piled up */
@@ -2134,6 +2208,14 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
 
 	engine->reset.prepare = execlists_reset_prepare;
 
+	engine->preempt_context = inject_preempt_context;
+	engine->submit_ports = execlists_submit_ports;
+
+	if (PVMMIO_LEVEL_ENABLE(engine->i915, PVMMIO_ELSP_SUBMIT)) {
+		engine->preempt_context = inject_preempt_context_pv;
+		engine->submit_ports = execlists_submit_ports_pv;
+	}
+
 	engine->park = NULL;
 	engine->unpark = NULL;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f6ec48a..e9895bf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -523,6 +523,9 @@ struct intel_engine_cs {
 	void		(*irq_seqno_barrier)(struct intel_engine_cs *engine);
 	void		(*cleanup)(struct intel_engine_cs *engine);
 
+	void		(*preempt_context)(struct intel_engine_cs *engine);
+	void		(*submit_ports)(struct intel_engine_cs *engine);
+
 	/* GEN8 signal/wait table - never trust comments!
 	 *	  signal to	signal to    signal to   signal to      signal to
 	 *	    RCS		   VCS          BCS        VECS		 VCS2
-- 
2.7.4

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[PATCH v2 4/5] drm/i915: master irq pvmmio optimization

[Xiaolin Zhang]

Master irq register is accessed twice every irq handling, then trapped
to SOS very frequently. Optimize it by moving master irq register
to share page, writing don't need be trapped.

When need enable irq to let SOS inject irq timely, use another pvmmio
register to achieve this purpose. So avoid one trap when we disable
master irq.

Use PVMMIO_MASTER_IRQ to control this level of pvmmio optimization.

v0: RFC
v1: rebase
v2: added pv version callbacks for irq_{irq_handler, irq_preinstall,
irq_postinstall}

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c    | 82 ++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_pvinfo.h |  3 +-
 drivers/gpu/drm/i915/i915_vgpu.c   |  2 +-
 3 files changed, 81 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d1f537..95ed2e7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2938,6 +2938,40 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
+static irqreturn_t gen8_irq_handler_pv(int irq, void *arg)
+{
+	struct drm_i915_private *dev_priv = to_i915(arg);
+	u32 master_ctl;
+	u32 gt_iir[4];
+
+	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+
+	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
+	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
+	if (!master_ctl)
+		return IRQ_NONE;
+
+	dev_priv->vgpu.shared_page->disable_irq = 1;
+
+	/* Find, clear, then process each source of interrupt */
+	gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
+
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
+	if (master_ctl & ~GEN8_GT_IRQS) {
+		disable_rpm_wakeref_asserts(dev_priv);
+		gen8_de_irq_handler(dev_priv, master_ctl);
+		enable_rpm_wakeref_asserts(dev_priv);
+	}
+
+	dev_priv->vgpu.shared_page->disable_irq = 0;
+	__raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+
+	gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
+
+	return IRQ_HANDLED;
+}
+
 struct wedge_me {
 	struct delayed_work work;
 	struct drm_i915_private *i915;
@@ -3626,13 +3660,11 @@ static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
 	GEN8_IRQ_RESET_NDX(GT, 3);
 }
 
-static void gen8_irq_reset(struct drm_device *dev)
+static void gen8_irq_reset_common(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int pipe;
 
-	gen8_master_intr_disable(dev_priv->regs);
-
 	gen8_gt_irq_reset(dev_priv);
 
 	I915_WRITE(EDP_PSR_IMR, 0xffffffff);
@@ -3651,6 +3683,22 @@ static void gen8_irq_reset(struct drm_device *dev)
 		ibx_irq_reset(dev_priv);
 }
 
+static void gen8_irq_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	gen8_master_intr_disable(dev_priv->regs);
+	gen8_irq_reset_common(dev);
+}
+
+static void gen8_irq_reset_pv(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	dev_priv->vgpu.shared_page->disable_irq = 1;
+	gen8_irq_reset_common(dev);
+}
+
 static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
 {
 	/* Disable RCS, BCS, VCS and VECS class engines. */
@@ -4262,7 +4310,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	}
 }
 
-static int gen8_irq_postinstall(struct drm_device *dev)
+static int gen8_irq_postinstall_common(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
@@ -4275,11 +4323,32 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 	if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_postinstall(dev);
 
+	return 0;
+}
+
+static int gen8_irq_postinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	gen8_irq_postinstall_common(dev);
+
 	gen8_master_intr_enable(dev_priv->regs);
 
 	return 0;
 }
 
+static int gen8_irq_postinstall_pv(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	gen8_irq_postinstall_common(dev);
+
+	dev_priv->vgpu.shared_page->disable_irq = 0;
+	__raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+
+	return 0;
+}
+
 static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
 {
 	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
@@ -4895,6 +4964,11 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->irq_handler = gen8_irq_handler;
 		dev->driver->irq_preinstall = gen8_irq_reset;
 		dev->driver->irq_postinstall = gen8_irq_postinstall;
+		if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ)) {
+			dev->driver->irq_handler = gen8_irq_handler_pv;
+			dev->driver->irq_preinstall = gen8_irq_reset_pv;
+			dev->driver->irq_postinstall = gen8_irq_postinstall_pv;
+		}
 		dev->driver->irq_uninstall = gen8_irq_reset;
 		dev->driver->enable_vblank = gen8_enable_vblank;
 		dev->driver->disable_vblank = gen8_disable_vblank;
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 179d558..1e24c45 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -143,8 +143,9 @@ struct vgt_if {
 		u32 lo;
 		u32 hi;
 	} shared_page_gpa;
+	u32 check_pending_irq;
 
-	u32  rsv7[0x200 - 27];    /* pad to one page */
+	u32  rsv7[0x200 - 28];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 9870ea6..013d329 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,7 +66,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
-	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT;
+	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ;
 
 	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)
-- 
2.7.4

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[PATCH v2 5/5] drm/i915: ppgtt update pvmmio optimization

[Xiaolin Zhang]

This patch extends g2v notification to notify host GVT-g of
ppgtt update from guest, including alloc_4lvl, clear_4lv4 and
insert_4lvl. It uses shared page to pass the additional params.
This patch also add one new pvmmio level to control ppgtt update.

Use PVMMIO_PPGTT_UPDATE to control this level of pvmmio optimization.

v0: RFC
v1: rebase
v2: added pv callbacks for vm.{allocate_va_range, insert_entries,
clear_range} within ppgtt.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 67 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_pvinfo.h  |  3 ++
 drivers/gpu/drm/i915/i915_vgpu.c    |  3 +-
 3 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 98d9a1e..b529f53 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -956,6 +956,25 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
 	}
 }
 
+static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
+				  u64 start, u64 length)
+{
+	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+	struct i915_pml4 *pml4 = &ppgtt->pml4;
+	struct drm_i915_private *dev_priv = vm->i915;
+	struct pv_ppgtt_update *pv_ppgtt =
+			&dev_priv->vgpu.shared_page->pv_ppgtt;
+	u64 orig_start = start;
+	u64 orig_length = length;
+
+	gen8_ppgtt_clear_4lvl(vm, start, length);
+
+	pv_ppgtt->pdp = px_dma(pml4);
+	pv_ppgtt->start = orig_start;
+	pv_ppgtt->length = orig_length;
+	I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR);
+}
+
 static inline struct sgt_dma {
 	struct scatterlist *sg;
 	dma_addr_t dma, max;
@@ -1197,6 +1216,25 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
 	}
 }
 
+static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
+				   struct i915_vma *vma,
+				   enum i915_cache_level cache_level,
+				   u32 flags)
+{
+	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+	struct drm_i915_private *dev_priv = vm->i915;
+	struct pv_ppgtt_update *pv_ppgtt =
+			&dev_priv->vgpu.shared_page->pv_ppgtt;
+
+	gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags);
+
+	pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
+	pv_ppgtt->start = vma->node.start;
+	pv_ppgtt->length = vma->node.size;
+	pv_ppgtt->cache_level = cache_level;
+	I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT);
+}
+
 static void gen8_free_page_tables(struct i915_address_space *vm,
 				  struct i915_page_directory *pd)
 {
@@ -1466,6 +1504,30 @@ static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
 	return -ENOMEM;
 }
 
+static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm,
+				 u64 start, u64 length)
+{
+	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+	struct i915_pml4 *pml4 = &ppgtt->pml4;
+	struct drm_i915_private *dev_priv = vm->i915;
+	struct pv_ppgtt_update *pv_ppgtt =
+			&dev_priv->vgpu.shared_page->pv_ppgtt;
+	int ret;
+	u64 orig_start = start;
+	u64 orig_length = length;
+
+	ret = gen8_ppgtt_alloc_4lvl(vm, start, length);
+	if (ret)
+		return ret;
+
+	pv_ppgtt->pdp = px_dma(pml4);
+	pv_ppgtt->start = orig_start;
+	pv_ppgtt->length = orig_length;
+	I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_ALLOC);
+
+	return 0;
+}
+
 static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt,
 			  struct i915_page_directory_pointer *pdp,
 			  u64 start, u64 length,
@@ -1631,6 +1693,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
 		ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
 		ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
 		ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
+		if (PVMMIO_LEVEL_ENABLE(i915, PVMMIO_PPGTT_UPDATE)) {
+			ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl_pv;
+			ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl_pv;
+			ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl_pv;
+		}
 	} else {
 		err = __pdp_init(&ppgtt->vm, &ppgtt->pdp);
 		if (err)
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 1e24c45..790db50 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,9 @@ enum vgt_g2v_type {
 	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
 	VGT_G2V_EXECLIST_CONTEXT_CREATE,
 	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+	VGT_G2V_PPGTT_L4_ALLOC,
+	VGT_G2V_PPGTT_L4_CLEAR,
+	VGT_G2V_PPGTT_L4_INSERT,
 	VGT_G2V_MAX,
 };
 
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 013d329..e11dcd8 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,7 +66,8 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
-	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ;
+	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT
+			| PVMMIO_MASTER_IRQ | PVMMIO_PPGTT_UPDATE;
 
 	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)
-- 
2.7.4

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✗ Fi.CI.CHECKPATCH: warning for i915 pvmmio to improve GVTg performance

[Patchwork]

== Series Details ==

Series: i915 pvmmio to improve GVTg performance
URL   : https://patchwork.freedesktop.org/series/51235/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d9bbdfcc803c drm/i915: introduced pv capability for vgpu
-:66: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#66: FILE: drivers/gpu/drm/i915/i915_drv.h:3888:
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level)	\
+	(intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+			&& (dev_priv->vgpu.pv_caps & level))

-:66: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'level' may be better as '(level)' to avoid precedence issues
#66: FILE: drivers/gpu/drm/i915/i915_drv.h:3888:
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level)	\
+	(intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+			&& (dev_priv->vgpu.pv_caps & level))

-:68: CHECK:LOGICAL_CONTINUATIONS: Logical continuations should be on the previous line
#68: FILE: drivers/gpu/drm/i915/i915_drv.h:3890:
+	(intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+			&& (dev_priv->vgpu.pv_caps & level))

-:135: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#135: FILE: drivers/gpu/drm/i915/i915_vgpu.c:91:
+	__raw_i915_write32(dev_priv, vgtif_reg(enable_pvmmio),
+			dev_priv->vgpu.pv_caps);

-:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#137: FILE: drivers/gpu/drm/i915/i915_vgpu.c:93:
+	dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
+			vgtif_reg(enable_pvmmio));

-:140: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#140: FILE: drivers/gpu/drm/i915/i915_vgpu.c:96:
+	DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+			dev_priv->vgpu.pv_caps);

total: 0 errors, 0 warnings, 6 checks, 95 lines checked
299416ad92bb drm/i915: get ready of memory for pvmmio
-:52: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#52: FILE: drivers/gpu/drm/i915/i915_drv.h:1348:
+	spinlock_t shared_page_lock;

-:127: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#127: FILE: drivers/gpu/drm/i915/i915_vgpu.c:104:
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.lo),
+				lower_32_bits(gpa));

-:129: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#129: FILE: drivers/gpu/drm/i915/i915_vgpu.c:106:
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.hi),
+				upper_32_bits(gpa));

-:131: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#131: FILE: drivers/gpu/drm/i915/i915_vgpu.c:108:
+		if (gpa != __raw_i915_read64(dev_priv,
+				vgtif_reg(shared_page_gpa))) {

total: 0 errors, 0 warnings, 4 checks, 91 lines checked
894384390637 drm/i915: context submission pvmmio optimization
3b2302382036 drm/i915: master irq pvmmio optimization
ec509230b0ea drm/i915: ppgtt update pvmmio optimization
-:38: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#38: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:960:
+static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
+				  u64 start, u64 length)

-:64: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#64: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:1220:
+static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
+				   struct i915_vma *vma,

-:90: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#90: FILE: drivers/gpu/drm/i915/i915_gem_gtt.c:1508:
+static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm,
+				 u64 start, u64 length)

total: 0 errors, 0 warnings, 3 checks, 109 lines checked

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✗ Fi.CI.SPARSE: warning for i915 pvmmio to improve GVTg performance

[Patchwork]

== Series Details ==

Series: i915 pvmmio to improve GVTg performance
URL   : https://patchwork.freedesktop.org/series/51235/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: introduced pv capability for vgpu
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3725:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3732:16: warning: expression using sizeof(void)

Commit: drm/i915: get ready of memory for pvmmio
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3732:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3734:16: warning: expression using sizeof(void)

Commit: drm/i915: context submission pvmmio optimization
Okay!

Commit: drm/i915: master irq pvmmio optimization
Okay!

Commit: drm/i915: ppgtt update pvmmio optimization
Okay!

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✓ Fi.CI.BAT: success for i915 pvmmio to improve GVTg performance

[Patchwork]

== Series Details ==

Series: i915 pvmmio to improve GVTg performance
URL   : https://patchwork.freedesktop.org/series/51235/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5015 -> Patchwork_10512 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/51235/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10512 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
      fi-byt-clapper:     PASS -> FAIL (fdo#107362)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
      fi-byt-clapper:     PASS -> FAIL (fdo#103191, fdo#107362) +1

    
    ==== Possible fixes ====

    igt@gem_exec_suspend@basic-s4-devices:
      fi-blb-e6850:       INCOMPLETE (fdo#107718) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-icl-u2:          FAIL (fdo#103167) -> PASS
      fi-byt-clapper:     FAIL (fdo#103167) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-a:
      fi-byt-clapper:     FAIL (fdo#107362) -> PASS

    
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (52 -> 46) ==

  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-icl-u 


== Build changes ==

    * Linux: CI_DRM_5015 -> Patchwork_10512

  CI_DRM_5015: ec78bedc9006e9e56067eb6524bbd3064475a055 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4685: 78619fde4008424c472906041edb1d204e014f7c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10512: ec509230b0ea62391b5c4c24d8f2e8455174b76d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ec509230b0ea drm/i915: ppgtt update pvmmio optimization
3b2302382036 drm/i915: master irq pvmmio optimization
894384390637 drm/i915: context submission pvmmio optimization
299416ad92bb drm/i915: get ready of memory for pvmmio
d9bbdfcc803c drm/i915: introduced pv capability for vgpu

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10512/issues.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for i915 pvmmio to improve GVTg performance

[Patchwork]

== Series Details ==

Series: i915 pvmmio to improve GVTg performance
URL   : https://patchwork.freedesktop.org/series/51235/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_5015_full -> Patchwork_10512_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10512_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10512_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10512_full:

  === IGT changes ===

    ==== Warnings ====

    igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack:
      shard-hsw:          SKIP -> PASS

    igt@perf_pmu@rc6:
      shard-kbl:          SKIP -> PASS

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10512_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_ppgtt@blt-vs-render-ctx0:
      shard-kbl:          PASS -> INCOMPLETE (fdo#106023, fdo#103665)

    igt@gem_sync@basic-each:
      shard-snb:          PASS -> INCOMPLETE (fdo#105411)

    igt@gem_workarounds@suspend-resume:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665)

    igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
      shard-kbl:          PASS -> DMESG-WARN (fdo#107956)

    igt@kms_color@pipe-a-legacy-gamma:
      shard-skl:          PASS -> FAIL (fdo#104782, fdo#108145)

    igt@kms_color@pipe-c-legacy-gamma:
      shard-apl:          PASS -> FAIL (fdo#104782)

    igt@kms_cursor_crc@cursor-64x21-onscreen:
      shard-glk:          PASS -> FAIL (fdo#103232)

    igt@kms_cursor_crc@cursor-64x64-sliding:
      shard-apl:          PASS -> FAIL (fdo#103232) +1

    igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
      shard-glk:          PASS -> FAIL (fdo#104873)

    igt@kms_draw_crc@draw-method-rgb565-blt-xtiled:
      shard-skl:          PASS -> FAIL (fdo#103184) +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
      shard-apl:          PASS -> FAIL (fdo#103167) +1

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
      shard-glk:          PASS -> FAIL (fdo#103167) +3

    igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render:
      shard-skl:          PASS -> FAIL (fdo#103167) +3

    igt@kms_plane@pixel-format-pipe-b-planes:
      shard-skl:          NOTRUN -> DMESG-FAIL (fdo#103166, fdo#106885)

    igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
      shard-skl:          PASS -> FAIL (fdo#103166)

    igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
      shard-skl:          PASS -> FAIL (fdo#107815, fdo#108145)

    igt@kms_plane_alpha_blend@pipe-c-alpha-transparant-fb:
      shard-skl:          NOTRUN -> FAIL (fdo#108145)

    igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
      shard-skl:          NOTRUN -> FAIL (fdo#108146)

    igt@pm_rpm@dpms-non-lpsp:
      shard-skl:          SKIP -> INCOMPLETE (fdo#107807)

    
    ==== Possible fixes ====

    igt@gem_exec_await@wide-contexts:
      shard-apl:          FAIL (fdo#106680) -> PASS

    igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
      shard-glk:          FAIL (fdo#108145) -> PASS

    igt@kms_cursor_crc@cursor-256x256-dpms:
      shard-apl:          FAIL (fdo#103232) -> PASS +1

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-glk:          FAIL (fdo#103232) -> PASS

    igt@kms_flip@plain-flip-fb-recreate-interruptible:
      shard-glk:          FAIL (fdo#100368) -> PASS

    igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
      shard-glk:          FAIL (fdo#103167) -> PASS

    igt@kms_plane@plane-position-covered-pipe-a-planes:
      shard-glk:          FAIL (fdo#103166) -> PASS +1

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS

    igt@pm_rpm@gem-mmap-cpu:
      shard-skl:          INCOMPLETE (fdo#107807) -> PASS

    igt@pm_rps@reset:
      shard-apl:          FAIL (fdo#102250) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
  fdo#104873 https://bugs.freedesktop.org/show_bug.cgi?id=104873
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023
  fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680
  fdo#106885 https://bugs.freedesktop.org/show_bug.cgi?id=106885
  fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
  fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815
  fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
  fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
  fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 6) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_5015 -> Patchwork_10512

  CI_DRM_5015: ec78bedc9006e9e56067eb6524bbd3064475a055 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4685: 78619fde4008424c472906041edb1d204e014f7c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10512: ec509230b0ea62391b5c4c24d8f2e8455174b76d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10512/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 0/5] i915 pvmmio to improve GVTg performance

[Zhang, Xiaolin]

Would like to ask ping for review patch set v2. thanks very much.

BRs, Xiaolin


On 10/19/2018 03:27 PM, Zhang, Xiaolin wrote:
> To improve GVTg performance, it could reduce the mmio access trap
> numbers within guest driver in some certain scenarios since mmio
> access trap will introuduce vm exit/vm enter cost.
>
> the solution in this patch set is to setup a shared memory region
> which accessed both by guest and GVTg without trap cost. the shared
> memory region is allocated by guest driver and guest driver will
> pass the region's memory guest physical address to GVTg through
> PVINFO register and later GVTg can access this region directly without
> trap cost to achieve data exchange purpose between guest and GVTg.
>
> in this patch set, 3 kind of pvmmio optimization implemented which is
> controlled by enable_pvmmio PVINO register with different level flag.
> 1. workload submission (context submission): reduce 4 traps to 1 trap.
> 2. master irq: reduce 2 traps to 1 trap. 
> 3. ppgtt update: eliminate the cost of ppgtt write protection. 
>
> based on the experiment, the performance was gained 4 percent (average)
> improvment with regard to both media and 3D workload benchmarks.
>
> based on the pvmmio framework, it could achive more sceneario optimization
> such as globle GTT update, display plane and water mark update with guest.
>
> v0: RFC patch set
> v1: addressed RFC review comments
> v2: addressed v1 review comments, added pv callbacks for pv operations
>
> Xiaolin Zhang (5):
>   drm/i915: introduced pv capability for vgpu
>   drm/i915: get ready of memory for pvmmio
>   drm/i915: context submission pvmmio optimization
>   drm/i915: master irq pvmmio optimization
>   drm/i915: ppgtt update pvmmio optimization
>
>  drivers/gpu/drm/i915/i915_drv.c         |  2 +
>  drivers/gpu/drm/i915/i915_drv.h         | 15 +++++-
>  drivers/gpu/drm/i915/i915_gem_gtt.c     | 67 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_irq.c         | 82 ++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_pvinfo.h      | 43 +++++++++++++++-
>  drivers/gpu/drm/i915/i915_vgpu.c        | 44 ++++++++++++++++-
>  drivers/gpu/drm/i915/intel_lrc.c        | 88 +++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/intel_ringbuffer.h |  3 ++
>  8 files changed, 333 insertions(+), 11 deletions(-)
>

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH v2 1/5] drm/i915: introduced pv capability for vgpu

[Zhang, Xiaolin]

Ping review. Thanks very much. 

BRs
Xiaolin

-----Original Message-----
From: Zhang, Xiaolin 
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-dev@lists.freedesktop.org; Zhang, Xiaolin <xiaolin.zhang@intel.com>; Zhenyu Wang <zhenyuw@linux.intel.com>; Wang, Zhi A <zhi.a.wang@intel.com>; Chris Wilson <chris@chris-wilson.co.uk>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; He; He, Min <min.he@intel.com>; Jiang; Jiang, Fei <fei.jiang@intel.com>; Gong; Gong, Zhipeng <zhipeng.gong@intel.com>; Yuan; Yuan, Hang <hang.yuan@intel.com>; Lv, Zhiyuan <zhiyuan.lv@intel.com>
Subject: [PATCH v2 1/5] drm/i915: introduced pv capability for vgpu

This u32 pv_caps field is used to control the different level pvmmio feature for MMIO emulation in GVT.

This field is default zero, no pvmmio feature enabled.

it also add VGT_CAPS_PVMMIO capability BIT for guest to check GVTg can support PV feature or not.

v0: RFC, introudced enable_pvmmio module parameter.
v1: addressed RFC comment to remove enable_pvmmio module parameter by pv capability check.
v2: rebase

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    | 11 +++++++++++
 drivers/gpu/drm/i915/i915_pvinfo.h | 17 ++++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 19 +++++++++++++++++--
 3 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3017ef0..7b2d7cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -56,6 +56,7 @@
 
 #include "i915_params.h"
 #include "i915_reg.h"
+#include "i915_pvinfo.h"
 #include "i915_utils.h"
 
 #include "intel_bios.h"
@@ -1343,6 +1344,7 @@ struct i915_workarounds {  struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
+	u32 pv_caps;
 };
 
 /* used in computing the new watermarks state */ @@ -2853,6 +2855,11 @@ static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
 	return dev_priv->vgpu.active;
 }
 
+static inline bool intel_vgpu_has_pvmmio(struct drm_i915_private 
+*dev_priv) {
+	return dev_priv->vgpu.caps & VGT_CAPS_PVMMIO; }
+
 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 			      enum pipe pipe);
 void
@@ -3878,4 +3885,8 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
 		return I915_HWS_CSB_WRITE_INDEX;
 }
 
+#define PVMMIO_LEVEL_ENABLE(dev_priv, level)	\
+	(intel_vgpu_active(dev_priv) && intel_vgpu_has_pvmmio(dev_priv) \
+			&& (dev_priv->vgpu.pv_caps & level))
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index eeaa3d5..26709e8 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,12 +49,26 @@ enum vgt_g2v_type {
 	VGT_G2V_MAX,
 };
 
+#define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
+
 /*
  * VGT capabilities type
  */
 #define VGT_CAPS_FULL_48BIT_PPGTT	BIT(2)
 #define VGT_CAPS_HWSP_EMULATION		BIT(3)
 #define VGT_CAPS_HUGE_GTT		BIT(4)
+#define VGT_CAPS_PVMMIO		BIT(5)
+
+/*
+ * define different levels of PVMMIO optimization  */ enum 
+pvmmio_levels {
+	PVMMIO_ELSP_SUBMIT = 0x1,
+	PVMMIO_PLANE_UPDATE = 0x2,
+	PVMMIO_PLANE_WM_UPDATE = 0x4,
+	PVMMIO_MASTER_IRQ = 0x8,
+	PVMMIO_PPGTT_UPDATE = 0x10,
+};
 
 struct vgt_if {
 	u64 magic;		/* VGT_MAGIC */
@@ -106,8 +120,9 @@ struct vgt_if {
 
 	u32 execlist_context_descriptor_lo;
 	u32 execlist_context_descriptor_hi;
+	u32 enable_pvmmio;
 
-	u32  rsv7[0x200 - 24];    /* pad to one page */
+	u32  rsv7[0x200 - 25];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 869cf4a..907bbd2 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -76,9 +76,24 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 	}
 
 	dev_priv->vgpu.caps = __raw_i915_read32(dev_priv, vgtif_reg(vgt_caps));
-
 	dev_priv->vgpu.active = true;
-	DRM_INFO("Virtual GPU for Intel GVT-g detected.\n");
+
+	if (!intel_vgpu_has_pvmmio(dev_priv)) {
+		DRM_INFO("Virtual GPU for Intel GVT-g detected\n");
+		return;
+	}
+
+	/* If guest wants to enable pvmmio, it needs to enable it explicitly
+	 * through vgt_if interface, and then read back the enable state from
+	 * gvt layer.
+	 */
+	__raw_i915_write32(dev_priv, vgtif_reg(enable_pvmmio),
+			dev_priv->vgpu.pv_caps);
+	dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
+			vgtif_reg(enable_pvmmio));
+
+	DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
+			dev_priv->vgpu.pv_caps);
 }
 
 bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv)
--
2.7.4

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Re: [PATCH v2 2/5] drm/i915: get ready of memory for pvmmio

[Zhang, Xiaolin]

Ping review. Thanks very much. 

BRs, Xiaolin 

-----Original Message-----
From: Zhang, Xiaolin 
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-dev@lists.freedesktop.org; Zhang, Xiaolin <xiaolin.zhang@intel.com>; Zhenyu Wang <zhenyuw@linux.intel.com>; Wang, Zhi A <zhi.a.wang@intel.com>; Chris Wilson <chris@chris-wilson.co.uk>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; He; He, Min <min.he@intel.com>; Jiang; Jiang, Fei <fei.jiang@intel.com>; Gong; Gong, Zhipeng <zhipeng.gong@intel.com>; Yuan; Yuan, Hang <hang.yuan@intel.com>; Lv, Zhiyuan <zhiyuan.lv@intel.com>
Subject: [PATCH v2 2/5] drm/i915: get ready of memory for pvmmio

To enable pvmmio feature, we need to prepare one 4K shared page which will be accessed by both guest and backend i915 driver.

guest i915 allocate one page memory and then the guest physical address is passed to backend i915 driver through PVINFO register so that backend i915 driver can access this shared page without hypeviser trap cost for shared data exchagne via hyperviser read_gpa functionality.

v0: RFC
v1: addressed RFC comment to move both shared_page_lock and shared_page to i915_virtual_gpu structure
v2: packed i915_virtual_gpu structure

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c    |  2 ++
 drivers/gpu/drm/i915/i915_drv.h    |  4 +++-
 drivers/gpu/drm/i915/i915_pvinfo.h | 24 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_vgpu.c   | 24 +++++++++++++++++++++++-
 4 files changed, 51 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index baac35f..557ab67 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -987,6 +987,8 @@ static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
 
 	intel_teardown_mchbar(dev_priv);
 	pci_iounmap(pdev, dev_priv->regs);
+	if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.shared_page)
+		free_page((unsigned long)dev_priv->vgpu.shared_page);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7b2d7cb..d7a972f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1345,7 +1345,9 @@ struct i915_virtual_gpu {
 	bool active;
 	u32 caps;
 	u32 pv_caps;
-};
+	spinlock_t shared_page_lock;
+	struct gvt_shared_page *shared_page;
+} __packed;
 
 /* used in computing the new watermarks state */  struct intel_wm_config { diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 26709e8..179d558 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -49,6 +49,24 @@ enum vgt_g2v_type {
 	VGT_G2V_MAX,
 };
 
+struct pv_ppgtt_update {
+	u64 pdp;
+	u64 start;
+	u64 length;
+	u32 cache_level;
+};
+
+/*
+ * shared page(4KB) between gvt and VM, could be allocated by guest 
+driver
+ * or a fixed location in PCI bar 0 region  */ struct gvt_shared_page {
+	u32 elsp_data[4];
+	u32 reg_addr;
+	u32 disable_irq;
+	struct pv_ppgtt_update pv_ppgtt;
+};
+
 #define VGPU_PVMMIO(vgpu) vgpu_vreg_t(vgpu, vgtif_reg(enable_pvmmio))
 
 /*
@@ -121,8 +139,12 @@ struct vgt_if {
 	u32 execlist_context_descriptor_lo;
 	u32 execlist_context_descriptor_hi;
 	u32 enable_pvmmio;
+	struct {
+		u32 lo;
+		u32 hi;
+	} shared_page_gpa;
 
-	u32  rsv7[0x200 - 25];    /* pad to one page */
+	u32  rsv7[0x200 - 27];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 907bbd2..cb409d5 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -62,6 +62,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)  {
 	u64 magic;
 	u16 version_major;
+	u64 gpa;
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
@@ -91,7 +92,28 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 			dev_priv->vgpu.pv_caps);
 	dev_priv->vgpu.pv_caps = __raw_i915_read32(dev_priv,
 			vgtif_reg(enable_pvmmio));
-
+	if (intel_vgpu_active(dev_priv) && dev_priv->vgpu.pv_caps) {
+		dev_priv->vgpu.shared_page =  (struct gvt_shared_page *)
+				get_zeroed_page(GFP_KERNEL);
+		if (!dev_priv->vgpu.shared_page) {
+			DRM_ERROR("out of memory for shared page memory\n");
+			return;
+		}
+		gpa = __pa(dev_priv->vgpu.shared_page);
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.lo),
+				lower_32_bits(gpa));
+		__raw_i915_write32(dev_priv, vgtif_reg(shared_page_gpa.hi),
+				upper_32_bits(gpa));
+		if (gpa != __raw_i915_read64(dev_priv,
+				vgtif_reg(shared_page_gpa))) {
+			DRM_ERROR("vgpu: passed shared_page_gpa failed\n");
+			free_page((unsigned long)dev_priv->vgpu.shared_page);
+			dev_priv->vgpu.pv_caps = 0;
+			return;
+		}
+		spin_lock_init(&dev_priv->vgpu.shared_page_lock);
+		DRM_INFO("VGPU shared page enabled\n");
+	}
 	DRM_INFO("Virtual GPU for Intel GVT-g detected with pvmmio 0x%x\n",
 			dev_priv->vgpu.pv_caps);
 }
--
2.7.4

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Re: [PATCH v2 3/5] drm/i915: context submission pvmmio optimization

[Zhang, Xiaolin]

Ping review, thanks very much. 

BRs, Xiaolin 

-----Original Message-----
From: Zhang, Xiaolin 
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-dev@lists.freedesktop.org; Zhang, Xiaolin <xiaolin.zhang@intel.com>; Zhenyu Wang <zhenyuw@linux.intel.com>; Wang, Zhi A <zhi.a.wang@intel.com>; Chris Wilson <chris@chris-wilson.co.uk>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; He; He, Min <min.he@intel.com>; Jiang; Jiang, Fei <fei.jiang@intel.com>; Gong; Gong, Zhipeng <zhipeng.gong@intel.com>; Yuan; Yuan, Hang <hang.yuan@intel.com>; Lv, Zhiyuan <zhiyuan.lv@intel.com>
Subject: [PATCH v2 3/5] drm/i915: context submission pvmmio optimization

It is performance optimization to reduce mmio trap numbers from 4 to
1 durning ELSP porting writing (context submission).

When context subission, to cache elsp_data[4] values in the shared page, the last elsp_data[0] port writing will be trapped to gvt for real context submission.

Use PVMMIO_ELSP_SUBMIT to control this level of pvmmio optimization.

v0: RFC
v1: rebase
v2: added pv ops for pv context submission. to maximize code resuse, introduced 2 more ops (submit_ports & preempt_context) instead of 1 op
(set_default_submission) in engine structure. pv version of submit_ports and preempt_context implemented.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_vgpu.c        |  2 +
 drivers/gpu/drm/i915/intel_lrc.c        | 88 +++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_ringbuffer.h |  3 ++
 3 files changed, 90 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index cb409d5..9870ea6 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,6 +66,8 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
+	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT;
+
 	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)
 		return;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 22b57b8..9e6ccf9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -460,6 +460,60 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
 	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);  }
 
+static void execlists_submit_ports_pv(struct intel_engine_cs *engine) {
+	struct intel_engine_execlists *execlists = &engine->execlists;
+	struct execlist_port *port = execlists->port;
+	u32 __iomem *elsp =
+		engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+	u32 *elsp_data;
+	unsigned int n;
+	u32 descs[4];
+	int i = 0;
+
+	/*
+	 * ELSQ note: the submit queue is not cleared after being submitted
+	 * to the HW so we need to make sure we always clean it up. This is
+	 * currently ensured by the fact that we always write the same number
+	 * of elsq entries, keep this in mind before changing the loop below.
+	 */
+	for (n = execlists_num_ports(execlists); n--; ) {
+		struct i915_request *rq;
+		unsigned int count;
+		u64 desc;
+
+		rq = port_unpack(&port[n], &count);
+		if (rq) {
+			GEM_BUG_ON(count > !n);
+			if (!count++)
+				execlists_context_schedule_in(rq);
+			port_set(&port[n], port_pack(rq, count));
+			desc = execlists_update_context(rq);
+		} else {
+			GEM_BUG_ON(!n);
+			desc = 0;
+		}
+		GEM_BUG_ON(i >= 4);
+		descs[i] = upper_32_bits(desc);
+		descs[i + 1] = lower_32_bits(desc);
+		i += 2;
+	}
+
+	spin_lock(&engine->i915->vgpu.shared_page_lock);
+	elsp_data = engine->i915->vgpu.shared_page->elsp_data;
+	*elsp_data = descs[0];
+	*(elsp_data + 1) = descs[1];
+	*(elsp_data + 2) = descs[2];
+	writel(descs[3], elsp);
+	spin_unlock(&engine->i915->vgpu.shared_page_lock);
+
+	/* we need to manually load the submit queue */
+	if (execlists->ctrl_reg)
+		writel(EL_CTRL_LOAD, execlists->ctrl_reg);
+
+	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK); }
+
 static bool ctx_single_port_submission(const struct intel_context *ce)  {
 	return (IS_ENABLED(CONFIG_DRM_I915_GVT) && @@ -497,7 +551,6 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
 
 	GEM_BUG_ON(execlists->preempt_complete_status !=
 		   upper_32_bits(ce->lrc_desc));
-
 	/*
 	 * Switch to our empty preempt context so
 	 * the state of the GPU is known (idle).
@@ -516,6 +569,27 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
 	execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);  }
 
+static void inject_preempt_context_pv(struct intel_engine_cs *engine) {
+	struct intel_engine_execlists *execlists = &engine->execlists;
+	struct intel_context *ce =
+		to_intel_context(engine->i915->preempt_context, engine);
+	u32 __iomem *elsp =
+		engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+	u32 *elsp_data;
+
+	GEM_BUG_ON(execlists->preempt_complete_status !=
+		   upper_32_bits(ce->lrc_desc));
+
+	spin_lock(&engine->i915->vgpu.shared_page_lock);
+	elsp_data = engine->i915->vgpu.shared_page->elsp_data;
+	*elsp_data = 0;
+	*(elsp_data + 1) = 0;
+	*(elsp_data + 2) = upper_32_bits(ce->lrc_desc);
+	writel(lower_32_bits(ce->lrc_desc), elsp);
+	spin_unlock(&engine->i915->vgpu.shared_page_lock);
+}
+
 static void complete_preempt_context(struct intel_engine_execlists *execlists)  {
 	GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT)); @@ -583,7 +657,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 			return;
 
 		if (need_preempt(engine, last, execlists->queue_priority)) {
-			inject_preempt_context(engine);
+			engine->preempt_context(engine);
 			return;
 		}
 
@@ -705,7 +779,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 
 	if (submit) {
 		port_assign(port, last);
-		execlists_submit_ports(engine);
+		engine->submit_ports(engine);
 	}
 
 	/* We must always keep the beast fed if we have work piled up */ @@ -2134,6 +2208,14 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
 
 	engine->reset.prepare = execlists_reset_prepare;
 
+	engine->preempt_context = inject_preempt_context;
+	engine->submit_ports = execlists_submit_ports;
+
+	if (PVMMIO_LEVEL_ENABLE(engine->i915, PVMMIO_ELSP_SUBMIT)) {
+		engine->preempt_context = inject_preempt_context_pv;
+		engine->submit_ports = execlists_submit_ports_pv;
+	}
+
 	engine->park = NULL;
 	engine->unpark = NULL;
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f6ec48a..e9895bf 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -523,6 +523,9 @@ struct intel_engine_cs {
 	void		(*irq_seqno_barrier)(struct intel_engine_cs *engine);
 	void		(*cleanup)(struct intel_engine_cs *engine);
 
+	void		(*preempt_context)(struct intel_engine_cs *engine);
+	void		(*submit_ports)(struct intel_engine_cs *engine);
+
 	/* GEN8 signal/wait table - never trust comments!
 	 *	  signal to	signal to    signal to   signal to      signal to
 	 *	    RCS		   VCS          BCS        VECS		 VCS2
--
2.7.4

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Re: [PATCH v2 4/5] drm/i915: master irq pvmmio optimization

[Zhang, Xiaolin]

Ping review. Thanks very much. 

BRs, Xiaolin

-----Original Message-----
From: Zhang, Xiaolin 
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-dev@lists.freedesktop.org; Zhang, Xiaolin <xiaolin.zhang@intel.com>; Zhenyu Wang <zhenyuw@linux.intel.com>; Wang, Zhi A <zhi.a.wang@intel.com>; Chris Wilson <chris@chris-wilson.co.uk>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; He; He, Min <min.he@intel.com>; Jiang; Jiang, Fei <fei.jiang@intel.com>; Gong; Gong, Zhipeng <zhipeng.gong@intel.com>; Yuan; Yuan, Hang <hang.yuan@intel.com>; Lv, Zhiyuan <zhiyuan.lv@intel.com>
Subject: [PATCH v2 4/5] drm/i915: master irq pvmmio optimization

Master irq register is accessed twice every irq handling, then trapped to SOS very frequently. Optimize it by moving master irq register to share page, writing don't need be trapped.

When need enable irq to let SOS inject irq timely, use another pvmmio register to achieve this purpose. So avoid one trap when we disable master irq.

Use PVMMIO_MASTER_IRQ to control this level of pvmmio optimization.

v0: RFC
v1: rebase
v2: added pv version callbacks for irq_{irq_handler, irq_preinstall, irq_postinstall}

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c    | 82 ++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_pvinfo.h |  3 +-
 drivers/gpu/drm/i915/i915_vgpu.c   |  2 +-
 3 files changed, 81 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 5d1f537..95ed2e7 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2938,6 +2938,40 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
+static irqreturn_t gen8_irq_handler_pv(int irq, void *arg) {
+	struct drm_i915_private *dev_priv = to_i915(arg);
+	u32 master_ctl;
+	u32 gt_iir[4];
+
+	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+
+	master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
+	master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
+	if (!master_ctl)
+		return IRQ_NONE;
+
+	dev_priv->vgpu.shared_page->disable_irq = 1;
+
+	/* Find, clear, then process each source of interrupt */
+	gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
+
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
+	if (master_ctl & ~GEN8_GT_IRQS) {
+		disable_rpm_wakeref_asserts(dev_priv);
+		gen8_de_irq_handler(dev_priv, master_ctl);
+		enable_rpm_wakeref_asserts(dev_priv);
+	}
+
+	dev_priv->vgpu.shared_page->disable_irq = 0;
+	__raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+
+	gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
+
+	return IRQ_HANDLED;
+}
+
 struct wedge_me {
 	struct delayed_work work;
 	struct drm_i915_private *i915;
@@ -3626,13 +3660,11 @@ static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
 	GEN8_IRQ_RESET_NDX(GT, 3);
 }
 
-static void gen8_irq_reset(struct drm_device *dev)
+static void gen8_irq_reset_common(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int pipe;
 
-	gen8_master_intr_disable(dev_priv->regs);
-
 	gen8_gt_irq_reset(dev_priv);
 
 	I915_WRITE(EDP_PSR_IMR, 0xffffffff);
@@ -3651,6 +3683,22 @@ static void gen8_irq_reset(struct drm_device *dev)
 		ibx_irq_reset(dev_priv);
 }
 
+static void gen8_irq_reset(struct drm_device *dev) {
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	gen8_master_intr_disable(dev_priv->regs);
+	gen8_irq_reset_common(dev);
+}
+
+static void gen8_irq_reset_pv(struct drm_device *dev) {
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	dev_priv->vgpu.shared_page->disable_irq = 1;
+	gen8_irq_reset_common(dev);
+}
+
 static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)  {
 	/* Disable RCS, BCS, VCS and VECS class engines. */ @@ -4262,7 +4310,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	}
 }
 
-static int gen8_irq_postinstall(struct drm_device *dev)
+static int gen8_irq_postinstall_common(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
@@ -4275,11 +4323,32 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 	if (HAS_PCH_SPLIT(dev_priv))
 		ibx_irq_postinstall(dev);
 
+	return 0;
+}
+
+static int gen8_irq_postinstall(struct drm_device *dev) {
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	gen8_irq_postinstall_common(dev);
+
 	gen8_master_intr_enable(dev_priv->regs);
 
 	return 0;
 }
 
+static int gen8_irq_postinstall_pv(struct drm_device *dev) {
+	struct drm_i915_private *dev_priv = to_i915(dev);
+
+	gen8_irq_postinstall_common(dev);
+
+	dev_priv->vgpu.shared_page->disable_irq = 0;
+	__raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+
+	return 0;
+}
+
 static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)  {
 	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT; @@ -4895,6 +4964,11 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->irq_handler = gen8_irq_handler;
 		dev->driver->irq_preinstall = gen8_irq_reset;
 		dev->driver->irq_postinstall = gen8_irq_postinstall;
+		if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ)) {
+			dev->driver->irq_handler = gen8_irq_handler_pv;
+			dev->driver->irq_preinstall = gen8_irq_reset_pv;
+			dev->driver->irq_postinstall = gen8_irq_postinstall_pv;
+		}
 		dev->driver->irq_uninstall = gen8_irq_reset;
 		dev->driver->enable_vblank = gen8_enable_vblank;
 		dev->driver->disable_vblank = gen8_disable_vblank; diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 179d558..1e24c45 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -143,8 +143,9 @@ struct vgt_if {
 		u32 lo;
 		u32 hi;
 	} shared_page_gpa;
+	u32 check_pending_irq;
 
-	u32  rsv7[0x200 - 27];    /* pad to one page */
+	u32  rsv7[0x200 - 28];    /* pad to one page */
 } __packed;
 
 #define vgtif_reg(x) \
diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 9870ea6..013d329 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,7 +66,7 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)
 
 	BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
 
-	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT;
+	dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ;
 
 	magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
 	if (magic != VGT_MAGIC)
--
2.7.4

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Re: [PATCH v2 5/5] drm/i915: ppgtt update pvmmio optimization

[Zhang, Xiaolin]

Ping review, thanks very much.

BRs, Xiaolin

-----Original Message-----
From: Zhang, Xiaolin
Sent: Friday, October 19, 2018 3:27 PM
To: intel-gfx@lists.freedesktop.org
Cc: intel-gvt-dev@lists.freedesktop.org; Zhang, Xiaolin <xiaolin.zhang@intel.com>; Zhenyu Wang <zhenyuw@linux.intel.com>; Wang, Zhi A <zhi.a.wang@intel.com>; Chris Wilson <chris@chris-wilson.co.uk>; Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; He; He, Min <min.he@intel.com>; Jiang; Jiang, Fei <fei.jiang@intel.com>; Gong; Gong, Zhipeng <zhipeng.gong@intel.com>; Yuan; Yuan, Hang <hang.yuan@intel.com>; Lv, Zhiyuan <zhiyuan.lv@intel.com>
Subject: [PATCH v2 5/5] drm/i915: ppgtt update pvmmio optimization

This patch extends g2v notification to notify host GVT-g of ppgtt update from guest, including alloc_4lvl, clear_4lv4 and insert_4lvl. It uses shared page to pass the additional params.
This patch also add one new pvmmio level to control ppgtt update.

Use PVMMIO_PPGTT_UPDATE to control this level of pvmmio optimization.

v0: RFC
v1: rebase
v2: added pv callbacks for vm.{allocate_va_range, insert_entries, clear_range} within ppgtt.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: He, Min <min.he@intel.com>
Cc: Jiang, Fei <fei.jiang@intel.com>
Cc: Gong, Zhipeng <zhipeng.gong@intel.com>
Cc: Yuan, Hang <hang.yuan@intel.com>
Cc: Zhiyuan Lv <zhiyuan.lv@intel.com>
Signed-off-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 67 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_pvinfo.h  |  3 ++
 drivers/gpu/drm/i915/i915_vgpu.c    |  3 +-
 3 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 98d9a1e..b529f53 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -956,6 +956,25 @@ static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
        }
 }

+static void gen8_ppgtt_clear_4lvl_pv(struct i915_address_space *vm,
+                                 u64 start, u64 length)
+{
+       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+       struct i915_pml4 *pml4 = &ppgtt->pml4;
+       struct drm_i915_private *dev_priv = vm->i915;
+       struct pv_ppgtt_update *pv_ppgtt =
+                       &dev_priv->vgpu.shared_page->pv_ppgtt;
+       u64 orig_start = start;
+       u64 orig_length = length;
+
+       gen8_ppgtt_clear_4lvl(vm, start, length);
+
+       pv_ppgtt->pdp = px_dma(pml4);
+       pv_ppgtt->start = orig_start;
+       pv_ppgtt->length = orig_length;
+       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_CLEAR); }
+
 static inline struct sgt_dma {
        struct scatterlist *sg;
        dma_addr_t dma, max;
@@ -1197,6 +1216,25 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
        }
 }

+static void gen8_ppgtt_insert_4lvl_pv(struct i915_address_space *vm,
+                                  struct i915_vma *vma,
+                                  enum i915_cache_level cache_level,
+                                  u32 flags)
+{
+       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+       struct drm_i915_private *dev_priv = vm->i915;
+       struct pv_ppgtt_update *pv_ppgtt =
+                       &dev_priv->vgpu.shared_page->pv_ppgtt;
+
+       gen8_ppgtt_insert_4lvl(vm, vma, cache_level, flags);
+
+       pv_ppgtt->pdp = px_dma(&ppgtt->pml4);
+       pv_ppgtt->start = vma->node.start;
+       pv_ppgtt->length = vma->node.size;
+       pv_ppgtt->cache_level = cache_level;
+       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_INSERT); }
+
 static void gen8_free_page_tables(struct i915_address_space *vm,
                                  struct i915_page_directory *pd)
 {
@@ -1466,6 +1504,30 @@ static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
        return -ENOMEM;
 }

+static int gen8_ppgtt_alloc_4lvl_pv(struct i915_address_space *vm,
+                                u64 start, u64 length)
+{
+       struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
+       struct i915_pml4 *pml4 = &ppgtt->pml4;
+       struct drm_i915_private *dev_priv = vm->i915;
+       struct pv_ppgtt_update *pv_ppgtt =
+                       &dev_priv->vgpu.shared_page->pv_ppgtt;
+       int ret;
+       u64 orig_start = start;
+       u64 orig_length = length;
+
+       ret = gen8_ppgtt_alloc_4lvl(vm, start, length);
+       if (ret)
+               return ret;
+
+       pv_ppgtt->pdp = px_dma(pml4);
+       pv_ppgtt->start = orig_start;
+       pv_ppgtt->length = orig_length;
+       I915_WRITE(vgtif_reg(g2v_notify), VGT_G2V_PPGTT_L4_ALLOC);
+
+       return 0;
+}
+
 static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt,
                          struct i915_page_directory_pointer *pdp,
                          u64 start, u64 length,
@@ -1631,6 +1693,11 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct drm_i915_private *i915)
                ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl;
                ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl;
                ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl;
+               if (PVMMIO_LEVEL_ENABLE(i915, PVMMIO_PPGTT_UPDATE)) {
+                       ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc_4lvl_pv;
+                       ppgtt->vm.insert_entries = gen8_ppgtt_insert_4lvl_pv;
+                       ppgtt->vm.clear_range = gen8_ppgtt_clear_4lvl_pv;
+               }
        } else {
                err = __pdp_init(&ppgtt->vm, &ppgtt->pdp);
                if (err)
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
index 1e24c45..790db50 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -46,6 +46,9 @@ enum vgt_g2v_type {
        VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
        VGT_G2V_EXECLIST_CONTEXT_CREATE,
        VGT_G2V_EXECLIST_CONTEXT_DESTROY,
+       VGT_G2V_PPGTT_L4_ALLOC,
+       VGT_G2V_PPGTT_L4_CLEAR,
+       VGT_G2V_PPGTT_L4_INSERT,
        VGT_G2V_MAX,
 };

diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c
index 013d329..e11dcd8 100644
--- a/drivers/gpu/drm/i915/i915_vgpu.c
+++ b/drivers/gpu/drm/i915/i915_vgpu.c
@@ -66,7 +66,8 @@ void i915_check_vgpu(struct drm_i915_private *dev_priv)

        BUILD_BUG_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);

-       dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ;
+       dev_priv->vgpu.pv_caps = PVMMIO_ELSP_SUBMIT
+                       | PVMMIO_MASTER_IRQ | PVMMIO_PPGTT_UPDATE;

        magic = __raw_i915_read64(dev_priv, vgtif_reg(magic));
        if (magic != VGT_MAGIC)
--
2.7.4

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✗ Fi.CI.BAT: failure for i915 pvmmio to improve GVTg performance (rev6)

[Patchwork]

== Series Details ==

Series: i915 pvmmio to improve GVTg performance (rev6)
URL   : https://patchwork.freedesktop.org/series/51235/
State : failure

== Summary ==

Applying: drm/i915: introduced pv capability for vgpu
error: patch fragment without header at line 38: @@ -3878,4 +3885,8 @@ static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
error: could not build fake ancestor
Patch failed at 0001 drm/i915: introduced pv capability for vgpu
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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