All of lore.kernel.org
 help / color / mirror / Atom feed
From: Julien Thierry <julien.thierry@arm.com>
To: Joel Fernandes <joel.opensrc@gmail.com>
Cc: Linux ARM Kernel List <linux-arm-kernel@lists.infradead.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	mark.rutland@arm.com, marc.zyngier@arm.com, james.morse@arm.com,
	daniel.thompson@linaro.org, Joel Fernandes <joelaf@google.com>
Subject: Re: [PATCH v2 0/6] arm64: provide pseudo NMI with GICv3
Date: Mon, 30 Apr 2018 10:53:17 +0100	[thread overview]
Message-ID: <07a0b8c1-3d87-0cae-61df-dbff782be301@arm.com> (raw)
In-Reply-To: <CAEi0qNkt75cqF=03HrQ81+pDdWVOpzGiHrk8_cTNTJo9os9D8Q@mail.gmail.com>



On 29/04/18 07:37, Joel Fernandes wrote:
> On Wed, Jan 17, 2018 at 4:10 AM, Julien Thierry <julien.thierry@arm.com> wrote:
>> Hi,
>>
>> On 17/01/18 11:54, Julien Thierry wrote:
>>>
>>> This series is a continuation of the work started by Daniel [1]. The goal
>>> is to use GICv3 interrupt priorities to simulate an NMI.
>>>
>>
>>
>> I have submitted a separate series making use of this feature for the ARM
>> PMUv3 interrupt [1].
> 
> I guess the hard lockup detector using NMI could be a nice next step
> to see how well it works with lock up detection. That's the main
> usecase for my interest. However, perf profiling is also a strong one.
> 

 From my understanding, Linux's hardlockup detector already uses the ARM 
PMU interrupt to check whether some task is stuck. I haven't looked at 
the details of the implementation yet, but in theory having the PMU 
interrupt as NMI should make the hard lockup detector use the NMI.

When I do the v3, I'll have a look at this to check whether the 
hardlockup detector works fine when using NMI.

Cheers,

-- 
Julien Thierry

WARNING: multiple messages have this Message-ID (diff)
From: julien.thierry@arm.com (Julien Thierry)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 0/6] arm64: provide pseudo NMI with GICv3
Date: Mon, 30 Apr 2018 10:53:17 +0100	[thread overview]
Message-ID: <07a0b8c1-3d87-0cae-61df-dbff782be301@arm.com> (raw)
In-Reply-To: <CAEi0qNkt75cqF=03HrQ81+pDdWVOpzGiHrk8_cTNTJo9os9D8Q@mail.gmail.com>



On 29/04/18 07:37, Joel Fernandes wrote:
> On Wed, Jan 17, 2018 at 4:10 AM, Julien Thierry <julien.thierry@arm.com> wrote:
>> Hi,
>>
>> On 17/01/18 11:54, Julien Thierry wrote:
>>>
>>> This series is a continuation of the work started by Daniel [1]. The goal
>>> is to use GICv3 interrupt priorities to simulate an NMI.
>>>
>>
>>
>> I have submitted a separate series making use of this feature for the ARM
>> PMUv3 interrupt [1].
> 
> I guess the hard lockup detector using NMI could be a nice next step
> to see how well it works with lock up detection. That's the main
> usecase for my interest. However, perf profiling is also a strong one.
> 

 From my understanding, Linux's hardlockup detector already uses the ARM 
PMU interrupt to check whether some task is stuck. I haven't looked at 
the details of the implementation yet, but in theory having the PMU 
interrupt as NMI should make the hard lockup detector use the NMI.

When I do the v3, I'll have a look at this to check whether the 
hardlockup detector works fine when using NMI.

Cheers,

-- 
Julien Thierry

  reply	other threads:[~2018-04-30  9:53 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-17 11:54 [PATCH v2 0/6] arm64: provide pseudo NMI with GICv3 Julien Thierry
2018-01-17 11:54 ` Julien Thierry
2018-01-17 11:54 ` [PATCH v2 1/6] arm64: cpufeature: Allow early detect of specific features Julien Thierry
2018-01-17 11:54   ` Julien Thierry
2018-01-22 12:05   ` Suzuki K Poulose
2018-01-22 12:05     ` Suzuki K Poulose
2018-01-22 12:21     ` Julien Thierry
2018-01-22 12:21       ` Julien Thierry
2018-01-22 13:38       ` Daniel Thompson
2018-01-22 13:38         ` Daniel Thompson
2018-01-22 13:57         ` Marc Zyngier
2018-01-22 13:57           ` Marc Zyngier
2018-01-22 14:14           ` Julien Thierry
2018-01-22 14:14             ` Julien Thierry
2018-01-22 14:20             ` Marc Zyngier
2018-01-22 14:20               ` Marc Zyngier
2018-01-22 14:45       ` Suzuki K Poulose
2018-01-22 14:45         ` Suzuki K Poulose
2018-01-22 15:01         ` Julien Thierry
2018-01-22 15:01           ` Julien Thierry
2018-01-22 15:13           ` Suzuki K Poulose
2018-01-22 15:13             ` Suzuki K Poulose
2018-01-22 15:23             ` Julien Thierry
2018-01-22 15:23               ` Julien Thierry
2018-01-22 15:34               ` Suzuki K Poulose
2018-01-22 15:34                 ` Suzuki K Poulose
2018-01-17 11:54 ` [PATCH v2 2/6] arm64: alternative: Apply alternatives early in boot process Julien Thierry
2018-01-17 11:54   ` Julien Thierry
2018-05-04 10:06   ` Julien Thierry
2018-05-04 10:06     ` Julien Thierry
2018-05-09 14:27     ` Daniel Thompson
2018-05-09 14:27       ` Daniel Thompson
2018-05-09 21:52     ` Suzuki K Poulose
2018-05-09 21:52       ` Suzuki K Poulose
2018-05-11  8:12       ` Julien Thierry
2018-05-11  8:12         ` Julien Thierry
2018-05-11  9:19         ` Suzuki K Poulose
2018-05-11  9:19           ` Suzuki K Poulose
2018-01-17 11:54 ` [PATCH v2 3/6] arm64: irqflags: Use ICC sysregs to implement IRQ masking Julien Thierry
2018-01-17 11:54   ` Julien Thierry
2018-01-17 11:54 ` [PATCH v2 4/6] irqchip/gic: Add functions to access irq priorities Julien Thierry
2018-01-17 11:54   ` Julien Thierry
2018-01-17 11:54 ` [PATCH v2 5/6] arm64: Detect current view of GIC priorities Julien Thierry
2018-01-17 11:54   ` Julien Thierry
2018-02-03  3:01   ` Yang Yingliang
2018-02-03  3:01     ` Yang Yingliang
2018-01-17 11:54 ` [PATCH v2 6/6] arm64: Add support for pseudo-NMIs Julien Thierry
2018-01-17 11:54   ` Julien Thierry
2018-01-17 12:10 ` [PATCH v2 0/6] arm64: provide pseudo NMI with GICv3 Julien Thierry
2018-01-17 12:10   ` Julien Thierry
2018-04-29  6:37   ` Joel Fernandes
2018-04-29  6:37     ` Joel Fernandes
2018-04-30  9:53     ` Julien Thierry [this message]
2018-04-30  9:53       ` Julien Thierry
2018-04-30 10:55       ` Daniel Thompson
2018-04-30 10:55         ` Daniel Thompson
2018-05-01 18:18         ` Joel Fernandes
2018-05-01 18:18           ` Joel Fernandes
2018-05-02 11:02           ` Daniel Thompson
2018-05-02 11:02             ` Daniel Thompson
     [not found] ` <8315db11-7899-008d-f37a-c311b278a1c4@hisilicon.com>
     [not found]   ` <7ec201a4-e2dc-8a1e-e8a1-f2b10bd41cd4@huawei.com>
     [not found]     ` <afb46ee0-4f26-fd1a-2fd1-866dc0b25175@arm.com>
2018-03-27 12:48       ` dongbo (E)
2018-03-27 13:02         ` Marc Zyngier
2018-03-27 13:09         ` Julien Thierry
2018-04-29  6:35 ` Joel Fernandes
2018-04-29  6:35   ` Joel Fernandes
2018-04-30  9:46   ` Julien Thierry
2018-04-30  9:46     ` Julien Thierry
2018-05-01 20:51     ` Joel Fernandes
2018-05-01 20:51       ` Joel Fernandes
2018-05-02 11:08       ` Marc Zyngier
2018-05-02 11:08         ` Marc Zyngier

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=07a0b8c1-3d87-0cae-61df-dbff782be301@arm.com \
    --to=julien.thierry@arm.com \
    --cc=daniel.thompson@linaro.org \
    --cc=james.morse@arm.com \
    --cc=joel.opensrc@gmail.com \
    --cc=joelaf@google.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=marc.zyngier@arm.com \
    --cc=mark.rutland@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.