[PATCH 0/5] EHL port programming

[PATCH 0/5] EHL port programming

[Matt Roper]

EHL is a bit unique because it's the only platform where multiple DDI's
can share the same PHY.  This makes some of the output programming a bit
confusing given that we tend to use the term 'port' today when talking
about both DDI's and PHY's.  The fourth patch here starts to try to
separate those two concepts.

Cc: José Roberto de Souza <jose.souza@intel.com>

Matt Roper (5):
  drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()
  drm/i915/ehl: Add third combo PHY offset
  drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
  drm/i915/gen11: Start distinguishing 'phy' from 'port'
  drm/i915/ehl: Enable DDI-D

 drivers/gpu/drm/i915/display/icl_dsi.c        |  17 ++-
 drivers/gpu/drm/i915/display/intel_bios.c     |   4 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    | 132 ++++++++++--------
 .../gpu/drm/i915/display/intel_combo_phy.h    |   3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 107 +++++++-------
 drivers/gpu/drm/i915/display/intel_display.c  |  37 +++--
 drivers/gpu/drm/i915/display/intel_display.h  |  16 +++
 drivers/gpu/drm/i915/display/intel_dp.c       |  12 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   8 +-
 drivers/gpu/drm/i915/i915_reg.h               |  22 +--
 drivers/gpu/drm/i915/intel_drv.h              |   4 +-
 11 files changed, 217 insertions(+), 145 deletions(-)

-- 
2.17.2

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[PATCH 1/5] drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()

[Matt Roper]

The port parameter hasn't been used since the last bspec phy programming
update.  Drop it to make some upcoming changes simpler.

References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7925a176f900..593806d44ad4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -846,8 +846,8 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
 }
 
 static const struct cnl_ddi_buf_trans *
-icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
-			int type, int rate, int *n_entries)
+icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
+			int *n_entries)
 {
 	if (type == INTEL_OUTPUT_HDMI) {
 		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
@@ -872,7 +872,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
 
 	if (INTEL_GEN(dev_priv) >= 11) {
 		if (intel_port_is_combophy(dev_priv, port))
-			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
+			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 						0, &n_entries);
 		else
 			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
@@ -2231,7 +2231,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 
 	if (INTEL_GEN(dev_priv) >= 11) {
 		if (intel_port_is_combophy(dev_priv, port))
-			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
+			icl_get_combo_buf_trans(dev_priv, encoder->type,
 						intel_dp->link_rate, &n_entries);
 		else
 			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
@@ -2420,8 +2420,8 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
 	u32 n_entries, val;
 	int ln;
 
-	ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
-						   rate, &n_entries);
+	ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
+						   &n_entries);
 	if (!ddi_translations)
 		return;
 
-- 
2.17.2

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Re: [PATCH 1/5] drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()

[Clinton Taylor]

Logical, since its not being used.

Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>

-Clint


On 6/20/19 7:01 PM, Matt Roper wrote:
> The port parameter hasn't been used since the last bspec phy programming
> update.  Drop it to make some upcoming changes simpler.
>
> References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_ddi.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 7925a176f900..593806d44ad4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -846,8 +846,8 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
>   }
>   
>   static const struct cnl_ddi_buf_trans *
> -icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
> -			int type, int rate, int *n_entries)
> +icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
> +			int *n_entries)
>   {
>   	if (type == INTEL_OUTPUT_HDMI) {
>   		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
> @@ -872,7 +872,7 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
>   
>   	if (INTEL_GEN(dev_priv) >= 11) {
>   		if (intel_port_is_combophy(dev_priv, port))
> -			icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
> +			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
>   						0, &n_entries);
>   		else
>   			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
> @@ -2231,7 +2231,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
>   
>   	if (INTEL_GEN(dev_priv) >= 11) {
>   		if (intel_port_is_combophy(dev_priv, port))
> -			icl_get_combo_buf_trans(dev_priv, port, encoder->type,
> +			icl_get_combo_buf_trans(dev_priv, encoder->type,
>   						intel_dp->link_rate, &n_entries);
>   		else
>   			n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
> @@ -2420,8 +2420,8 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
>   	u32 n_entries, val;
>   	int ln;
>   
> -	ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
> -						   rate, &n_entries);
> +	ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate,
> +						   &n_entries);
>   	if (!ddi_translations)
>   		return;
>   
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[PATCH 2/5] drm/i915/ehl: Add third combo PHY offset

[Matt Roper]

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e6009cefb18..7e748bb3f324 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1793,8 +1793,10 @@ enum i915_power_well_id {
  */
 #define _ICL_COMBOPHY_A			0x162000
 #define _ICL_COMBOPHY_B			0x6C000
+#define _ICL_COMBOPHY_C_EHL		0x160000
 #define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
-					      _ICL_COMBOPHY_B)
+					      _ICL_COMBOPHY_B, \
+					      _ICL_COMBOPHY_C_EHL)
 
 /* CNL/ICL Port CL_DW registers */
 #define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
-- 
2.17.2

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Re: [PATCH 2/5] drm/i915/ehl: Add third combo PHY offset

[Souza, Jose]

On Thu, 2019-06-20 at 19:01 -0700, Matt Roper wrote:
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 7e6009cefb18..7e748bb3f324 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1793,8 +1793,10 @@ enum i915_power_well_id {
>   */
>  #define _ICL_COMBOPHY_A			0x162000
>  #define _ICL_COMBOPHY_B			0x6C000
> +#define _ICL_COMBOPHY_C_EHL		0x160000
>  #define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
> -					      _ICL_COMBOPHY_B)
> +					      _ICL_COMBOPHY_B, \
> +					      _ICL_COMBOPHY_C_EHL)
>  

Rename to _EHL_COMBOPHY_C.

With that: Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

>  /* CNL/ICL Port CL_DW registers */
>  #define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
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[PATCH 3/5] drm/i915/ehl: Don't program PHY_MISC on EHL PHY C

[Matt Roper]

Although EHL added a third combo PHY, no PHY_MISC register was added for
PHY C.  The bspec indicates that there's no need to program the "DE to
IO Comp Pwr Down" setting for this PHY that we usually need to set in
PHY_MISC.

Bspec: 33148
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../gpu/drm/i915/display/intel_combo_phy.c    | 53 +++++++++++++------
 1 file changed, 36 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index 075bab2500eb..da590f1a998b 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -183,9 +183,13 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
 				  enum port port)
 {
-	return !(I915_READ(ICL_PHY_MISC(port)) &
-		 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
-		(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
+	/* The PHY C added by EHL has no PHY_MISC register */
+	if (port == PORT_C)
+		return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
+	else
+		return !(I915_READ(ICL_PHY_MISC(port)) &
+			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
+			(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
 }
 
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
@@ -300,18 +304,26 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		}
 
 		/*
-		 * EHL's combo PHY A can be hooked up to either an external
-		 * display (via DDI-D) or an internal display (via DDI-A or
-		 * the DSI DPHY).  This is a motherboard design decision that
-		 * can't be changed on the fly, so initialize the PHY's mux
-		 * based on whether our VBT indicates the presence of any
-		 * "internal" child devices.
+		 * Although EHL adds a combo PHY C, there's no PHY_MISC
+		 * register for it and no need to program the
+		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
 		 */
-		val = I915_READ(ICL_PHY_MISC(port));
-		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
-			val = ehl_combo_phy_a_mux(dev_priv, val);
-		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-		I915_WRITE(ICL_PHY_MISC(port), val);
+		if (port != PORT_C) {
+			/*
+			 * EHL's combo PHY A can be hooked up to either an
+			 * external display (via DDI-D) or an internal display
+			 * (via DDI-A or the DSI DPHY).  This is a motherboard
+			 * design decision that can't be changed on the fly, so
+			 * initialize the PHY's mux based on whether our VBT
+			 * indicates the presence of any "internal" child
+			 * devices.
+			 */
+			val = I915_READ(ICL_PHY_MISC(port));
+			if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
+				val = ehl_combo_phy_a_mux(dev_priv, val);
+			val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
+			I915_WRITE(ICL_PHY_MISC(port), val);
+		}
 
 		cnl_set_procmon_ref_values(dev_priv, port);
 
@@ -343,9 +355,16 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 			DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n",
 				 port_name(port));
 
-		val = I915_READ(ICL_PHY_MISC(port));
-		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-		I915_WRITE(ICL_PHY_MISC(port), val);
+		/*
+		 * Although EHL adds a combo PHY C, there's no PHY_MISC
+		 * register for it and no need to program the
+		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
+		 */
+		if (port != PORT_C) {
+			val = I915_READ(ICL_PHY_MISC(port));
+			val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
+			I915_WRITE(ICL_PHY_MISC(port), val);
+		}
 
 		val = I915_READ(ICL_PORT_COMP_DW0(port));
 		val &= ~COMP_INIT;
-- 
2.17.2

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Re: [PATCH 3/5] drm/i915/ehl: Don't program PHY_MISC on EHL PHY C

[Souza, Jose]

On Thu, 2019-06-20 at 19:01 -0700, Matt Roper wrote:
> Although EHL added a third combo PHY, no PHY_MISC register was added
> for
> PHY C.  The bspec indicates that there's no need to program the "DE
> to
> IO Comp Pwr Down" setting for this PHY that we usually need to set in
> PHY_MISC.
> 
> Bspec: 33148
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_combo_phy.c    | 53 +++++++++++++--
> ----
>  1 file changed, 36 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index 075bab2500eb..da590f1a998b 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -183,9 +183,13 @@ static void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
>  				  enum port port)
>  {
> -	return !(I915_READ(ICL_PHY_MISC(port)) &
> -		 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> -		(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
> +	/* The PHY C added by EHL has no PHY_MISC register */
> +	if (port == PORT_C)
> +		return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;

Please add IS_ELKHARTLAKE() to the if, this is a particularity of EHL,
future platforms will reuse this function and they have PHY_MISC.

> +	else
> +		return !(I915_READ(ICL_PHY_MISC(port)) &
> +			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> +			(I915_READ(ICL_PORT_COMP_DW0(port)) &
> COMP_INIT);
>  }
>  
>  static bool icl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv,
> @@ -300,18 +304,26 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  		}
>  
>  		/*
> -		 * EHL's combo PHY A can be hooked up to either an
> external
> -		 * display (via DDI-D) or an internal display (via DDI-
> A or
> -		 * the DSI DPHY).  This is a motherboard design
> decision that
> -		 * can't be changed on the fly, so initialize the PHY's
> mux
> -		 * based on whether our VBT indicates the presence of
> any
> -		 * "internal" child devices.
> +		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> +		 * register for it and no need to program the
> +		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
>  		 */
> -		val = I915_READ(ICL_PHY_MISC(port));
> -		if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
> -			val = ehl_combo_phy_a_mux(dev_priv, val);
> -		val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> -		I915_WRITE(ICL_PHY_MISC(port), val);
> +		if (port != PORT_C) {

Something as above here too.

Maybe something with less changes like:

if (IS_ELKHARTLAKE(dev_priv) && port == PORT_C)
	goto skip_phy_misc;

> +			/*
> +			 * EHL's combo PHY A can be hooked up to either
> an
> +			 * external display (via DDI-D) or an internal
> display
> +			 * (via DDI-A or the DSI DPHY).  This is a
> motherboard
> +			 * design decision that can't be changed on the
> fly, so
> +			 * initialize the PHY's mux based on whether
> our VBT
> +			 * indicates the presence of any "internal"
> child
> +			 * devices.
> +			 */
> +			val = I915_READ(ICL_PHY_MISC(port));
> +			if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
> +				val = ehl_combo_phy_a_mux(dev_priv,
> val);
> +			val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> +			I915_WRITE(ICL_PHY_MISC(port), val);
> +		}
>  
>  		cnl_set_procmon_ref_values(dev_priv, port);
>  
> @@ -343,9 +355,16 @@ static void icl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>  			DRM_WARN("Port %c combo PHY HW state changed
> unexpectedly\n",
>  				 port_name(port));
>  
> -		val = I915_READ(ICL_PHY_MISC(port));
> -		val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> -		I915_WRITE(ICL_PHY_MISC(port), val);
> +		/*
> +		 * Although EHL adds a combo PHY C, there's no PHY_MISC
> +		 * register for it and no need to program the
> +		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
> +		 */
> +		if (port != PORT_C) {
> +			val = I915_READ(ICL_PHY_MISC(port));
> +			val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> +			I915_WRITE(ICL_PHY_MISC(port), val);
> +		}

Same as above.

>  
>  		val = I915_READ(ICL_PORT_COMP_DW0(port));
>  		val &= ~COMP_INIT;
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[PATCH 4/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'

[Matt Roper]

Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
Because of this, both the bspec documentation and our i915 code has used
the term "port" when talking about either DDI's or PHY's; it was always
easy to tell what terms like "Port A" were referring to from the
context.

Unfortunately this is starting to break down now that EHL allows PHY-A
to be driven by either DDI-A or DDI-D.  Is a setup with DDI-D driving
PHY-A considered "Port A" or "Port D?"  The answer depends on which
register we're working with, and even the bspec doesn't do a great job
of clarifying this.

Let's try to be more explicit about whether we're talking about the DDI
or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
new 'enum phy' namespace to refer to the PHY in use.

A few general notes:

 - ICL_PORT_COMP_* and ICL_PORT_CL_* belong to the actual combo PHY so
   they should always be programmed according to the PHY in use,
   regardless of which DDI is driving it.

 - The pipe part of the hardware expects "port" to refer to the
   DDI, so registers like TRANS_CLK_SEL and TRANS_DDI_FUNC_CTL should
   set bits according to the desired DDI (e.g., DDI-D) rather than the
   PHY (PHY-A).

 - Non-pipe registers refer to the PHY.  Notably, DPCLKA_CFGCR0_ICL
   needs to set bits according to the PHY.

Most of the changes here are on the combo PHY side.  I didn't touch most
of the TC port code yet, so it still refers to everything as ports.
That's okay for now since there's no TC on EHL, but we'll probably want
to separate out the DDI vs PHY terminology for TC in the future as well
to avoid confusion.

Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
Lucas, I hear you're going to be posting a large patch series soon and I
suspect this patch may conflict with that.  Let me know if you want me
to sit on this for a while.

 drivers/gpu/drm/i915/display/icl_dsi.c        | 17 +++-
 drivers/gpu/drm/i915/display/intel_bios.c     |  4 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    | 93 +++++++++---------
 .../gpu/drm/i915/display/intel_combo_phy.h    |  3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 95 +++++++++++--------
 drivers/gpu/drm/i915/display/intel_display.c  | 36 ++++---
 drivers/gpu/drm/i915/display/intel_display.h  | 16 ++++
 drivers/gpu/drm/i915/display/intel_dp.c       | 12 ++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  8 +-
 drivers/gpu/drm/i915/i915_reg.h               | 18 ++--
 drivers/gpu/drm/i915/intel_drv.h              |  4 +-
 11 files changed, 178 insertions(+), 128 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b8673debf932..2063435cff13 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -560,11 +560,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
 	enum port port;
+	enum phy phy;
 
 	mutex_lock(&dev_priv->dpll_lock);
 	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_dsi_port(port, intel_dsi->ports) {
-		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		phy = intel_port_to_phy(dev_priv, port);
+		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 
 	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -577,11 +579,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
 	enum port port;
+	enum phy phy;
 
 	mutex_lock(&dev_priv->dpll_lock);
 	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_dsi_port(port, intel_dsi->ports) {
-		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		phy = intel_port_to_phy(dev_priv, port);
+		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 
 	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -595,19 +599,22 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port;
+	enum phy phy;
 	u32 val;
 
 	mutex_lock(&dev_priv->dpll_lock);
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_dsi_port(port, intel_dsi->ports) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+		phy = intel_port_to_phy(dev_priv, port);
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 	}
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		phy = intel_port_to_phy(dev_priv, port);
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..4fdbb5c35d87 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -28,6 +28,7 @@
 #include <drm/drm_dp_helper.h>
 #include <drm/i915_drm.h>
 
+#include "display/intel_display.h"
 #include "display/intel_gmbus.h"
 
 #include "i915_drv.h"
@@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
 	for (port = PORT_A; port < I915_MAX_PORTS; port++) {
 		struct ddi_vbt_port_info *info =
 			&dev_priv->vbt.ddi_port_info[port];
+		enum phy phy = intel_port_to_phy(dev_priv, port);
 
 		/*
 		 * VBT has the TypeC mode (native,TBT/USB) and we don't want
 		 * to detect it.
 		 */
-		if (intel_port_is_tc(dev_priv, port))
+		if (intel_phy_is_tc(dev_priv, phy))
 			continue;
 
 		info->supports_dvi = (port != PORT_A && port != PORT_E);
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index da590f1a998b..f95986a9cf76 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -6,13 +6,13 @@
 #include "intel_combo_phy.h"
 #include "intel_drv.h"
 
-#define for_each_combo_port(__dev_priv, __port) \
-	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_phy(__dev_priv, __phy) \
+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
 
-#define for_each_combo_port_reverse(__dev_priv, __port) \
-	for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
 
 enum {
 	PROCMON_0_85V_DOT_0,
@@ -38,10 +38,9 @@ static const struct cnl_procmon {
 };
 
 /*
- * CNL has just one set of registers, while ICL has two sets: one for port A and
- * the other for port B. The CNL registers are equivalent to the ICL port A
- * registers, that's why we call the ICL macros even though the function has CNL
- * on its name.
+ * CNL has just one set of registers, while gen11 has a set for each combo PHY.
+ * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
+ * call the ICL macros even though the function has CNL on its name.
  */
 static const struct cnl_procmon *
 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
@@ -193,27 +192,27 @@ static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
 }
 
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
-				       enum port port)
+				       enum phy phy)
 {
 	bool ret;
 
-	if (!icl_combo_phy_enabled(dev_priv, port))
+	if (!icl_combo_phy_enabled(dev_priv, phy))
 		return false;
 
-	ret = cnl_verify_procmon_ref_values(dev_priv, port);
+	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 
-	if (port == PORT_A)
-		ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port),
+	if (phy == PHY_A)
+		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 
 	return ret;
 }
 
 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
-				    enum port port, bool is_dsi,
+				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal)
 {
 	u8 lane_mask;
@@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
 		}
 	}
 
-	val = I915_READ(ICL_PORT_CL_DW10(port));
+	val = I915_READ(ICL_PORT_CL_DW10(phy));
 	val &= ~PWR_DOWN_LN_MASK;
 	val |= lane_mask << PWR_DOWN_LN_SHIFT;
-	I915_WRITE(ICL_PORT_CL_DW10(port), val);
+	I915_WRITE(ICL_PORT_CL_DW10(phy), val);
 }
 
 static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
@@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
 
 static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 {
-	enum port port;
+	enum phy phy;
 
-	for_each_combo_port(dev_priv, port) {
+	for_each_combo_phy(dev_priv, phy) {
 		u32 val;
 
-		if (icl_combo_phy_verify_state(dev_priv, port)) {
-			DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n",
-					 port_name(port));
+		if (icl_combo_phy_verify_state(dev_priv, phy)) {
+			DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n",
+					 port_name(phy));
 			continue;
 		}
 
@@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		 * register for it and no need to program the
 		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
 		 */
-		if (port != PORT_C) {
+		if (phy != PHY_C) {
 			/*
 			 * EHL's combo PHY A can be hooked up to either an
 			 * external display (via DDI-D) or an internal display
@@ -318,57 +317,57 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 			 * indicates the presence of any "internal" child
 			 * devices.
 			 */
-			val = I915_READ(ICL_PHY_MISC(port));
-			if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
+			val = I915_READ(ICL_PHY_MISC(phy));
+			if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
 				val = ehl_combo_phy_a_mux(dev_priv, val);
 			val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-			I915_WRITE(ICL_PHY_MISC(port), val);
+			I915_WRITE(ICL_PHY_MISC(phy), val);
 		}
 
-		cnl_set_procmon_ref_values(dev_priv, port);
+		cnl_set_procmon_ref_values(dev_priv, phy);
 
-		if (port == PORT_A) {
-			val = I915_READ(ICL_PORT_COMP_DW8(port));
+		if (phy == PHY_A) {
+			val = I915_READ(ICL_PORT_COMP_DW8(phy));
 			val |= IREFGEN;
-			I915_WRITE(ICL_PORT_COMP_DW8(port), val);
+			I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
 		}
 
-		val = I915_READ(ICL_PORT_COMP_DW0(port));
+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
 		val |= COMP_INIT;
-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
 
-		val = I915_READ(ICL_PORT_CL_DW5(port));
+		val = I915_READ(ICL_PORT_CL_DW5(phy));
 		val |= CL_POWER_DOWN_ENABLE;
-		I915_WRITE(ICL_PORT_CL_DW5(port), val);
+		I915_WRITE(ICL_PORT_CL_DW5(phy), val);
 	}
 }
 
 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 {
-	enum port port;
+	enum phy phy;
 
-	for_each_combo_port_reverse(dev_priv, port) {
+	for_each_combo_phy_reverse(dev_priv, phy) {
 		u32 val;
 
-		if (port == PORT_A &&
-		    !icl_combo_phy_verify_state(dev_priv, port))
-			DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n",
-				 port_name(port));
+		if (phy == PHY_A &&
+		    !icl_combo_phy_verify_state(dev_priv, phy))
+			DRM_WARN("Combo PHY %c HW state changed unexpectedly\n",
+				 phy_name(phy));
 
 		/*
 		 * Although EHL adds a combo PHY C, there's no PHY_MISC
 		 * register for it and no need to program the
 		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
 		 */
-		if (port != PORT_C) {
-			val = I915_READ(ICL_PHY_MISC(port));
+		if (phy != PHY_C) {
+			val = I915_READ(ICL_PHY_MISC(phy));
 			val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-			I915_WRITE(ICL_PHY_MISC(port), val);
+			I915_WRITE(ICL_PHY_MISC(phy), val);
 		}
 
-		val = I915_READ(ICL_PORT_COMP_DW0(port));
+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
 		val &= ~COMP_INIT;
-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h b/drivers/gpu/drm/i915/display/intel_combo_phy.h
index e6e195a83b19..80a1386b4c87 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h
@@ -10,11 +10,12 @@
 #include <drm/i915_drm.h>
 
 struct drm_i915_private;
+enum phy;
 
 void intel_combo_phy_init(struct drm_i915_private *dev_priv);
 void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
-				    enum port port, bool is_dsi,
+				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal);
 
 #endif /* __INTEL_COMBO_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 593806d44ad4..8ee55ba2c91b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -867,11 +867,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 {
 	int n_entries, level, default_entry;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (intel_port_is_combophy(dev_priv, port))
+		if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 						0, &n_entries);
 		else
@@ -1486,9 +1487,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int link_clock;
 
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
 	} else {
 		enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
@@ -2085,6 +2087,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	/*
 	 * TODO: Add support for MST encoders. Atm, the following should never
@@ -2102,7 +2105,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 	 * ports.
 	 */
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_port_is_tc(dev_priv, encoder->port))
+	    intel_phy_is_tc(dev_priv, phy))
 		intel_display_power_get(dev_priv,
 					intel_ddi_main_link_aux_domain(dig_port));
 
@@ -2227,10 +2230,11 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int n_entries;
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (intel_port_is_combophy(dev_priv, port))
+		if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(dev_priv, encoder->type,
 						intel_dp->link_rate, &n_entries);
 		else
@@ -2663,9 +2667,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
 				    enum intel_output_type type)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
-	if (intel_port_is_combophy(dev_priv, port))
+	if (intel_phy_is_combo(dev_priv, phy))
 		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
 	else
 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2728,12 +2732,12 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp)
 
 static inline
 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
-			      enum port port)
+			      enum phy phy)
 {
-	if (intel_port_is_combophy(dev_priv, port)) {
-		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
-	} else if (intel_port_is_tc(dev_priv, port)) {
-		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+	if (intel_phy_is_combo(dev_priv, phy)) {
+		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+	} else if (intel_phy_is_tc(dev_priv, phy)) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv, phy);
 
 		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
 	}
@@ -2746,22 +2750,22 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	u32 val;
 
 	mutex_lock(&dev_priv->dpll_lock);
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
-	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
 
-	if (intel_port_is_combophy(dev_priv, port)) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+	if (intel_phy_is_combo(dev_priv, phy)) {
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 		POSTING_READ(DPCLKA_CFGCR0_ICL);
 	}
 
-	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	mutex_unlock(&dev_priv->dpll_lock);
@@ -2770,13 +2774,13 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	u32 val;
 
 	mutex_lock(&dev_priv->dpll_lock);
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
-	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	mutex_unlock(&dev_priv->dpll_lock);
@@ -2863,6 +2867,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	u32 val;
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 
@@ -2872,14 +2877,14 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 	mutex_lock(&dev_priv->dpll_lock);
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_port_is_combophy(dev_priv, port))
-			I915_WRITE(DDI_CLK_SEL(port),
+		if (!intel_phy_is_combo(dev_priv, phy))
+			I915_WRITE(DDI_CLK_SEL(phy),
 				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
 		val = I915_READ(DPCLKA_CFGCR0);
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 		I915_WRITE(DPCLKA_CFGCR0, val);
 
 		/*
@@ -2888,21 +2893,21 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 		 * register writes.
 		 */
 		val = I915_READ(DPCLKA_CFGCR0);
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 		I915_WRITE(DPCLKA_CFGCR0, val);
 	} else if (IS_GEN9_BC(dev_priv)) {
 		/* DDI -> PLL mapping  */
 		val = I915_READ(DPLL_CTRL2);
 
-		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-			 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
-			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
+		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(phy) |
+			 DPLL_CTRL2_DDI_CLK_SEL_MASK(phy));
+		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, phy) |
+			DPLL_CTRL2_DDI_SEL_OVERRIDE(phy));
 
 		I915_WRITE(DPLL_CTRL2, val);
 
 	} else if (INTEL_GEN(dev_priv) < 9) {
-		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
+		I915_WRITE(PORT_CLK_SEL(phy), hsw_pll_to_ddi_pll_sel(pll));
 	}
 
 	mutex_unlock(&dev_priv->dpll_lock);
@@ -2912,18 +2917,19 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_port_is_combophy(dev_priv, port))
-			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
+		if (!intel_phy_is_combo(dev_priv, phy))
+			I915_WRITE(DDI_CLK_SEL(phy), DDI_CLK_SEL_NONE);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
-			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+			   DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 	} else if (IS_GEN9_BC(dev_priv)) {
 		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
-			   DPLL_CTRL2_DDI_CLK_OFF(port));
+			   DPLL_CTRL2_DDI_CLK_OFF(phy));
 	} else if (INTEL_GEN(dev_priv) < 9) {
-		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
+		I915_WRITE(PORT_CLK_SEL(phy), PORT_CLK_SEL_NONE);
 	}
 }
 
@@ -3110,6 +3116,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
 	int level = intel_ddi_dp_level(intel_dp);
@@ -3138,11 +3145,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	else
 		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		bool lane_reversal =
 			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
 
-		intel_combo_phy_power_up_lanes(dev_priv, port, false,
+		intel_combo_phy_power_up_lanes(dev_priv, phy, false,
 					       crtc_state->lane_count,
 					       lane_reversal);
 	}
@@ -3630,7 +3637,7 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
 	enum port port = encoder->port;
 
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_port_is_tc(dev_priv, encoder->port))
+	    intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
 		intel_display_power_get(dev_priv,
 					intel_ddi_main_link_aux_domain(dig_port));
 
@@ -3656,9 +3663,10 @@ intel_ddi_post_pll_disable(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_port_is_tc(dev_priv, encoder->port))
+	    intel_phy_is_tc(dev_priv, phy))
 		intel_display_power_put_unchecked(dev_priv,
 						  intel_ddi_main_link_aux_domain(dig_port));
 }
@@ -3934,8 +3942,9 @@ static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
 	struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
-	if (intel_port_is_tc(i915, dig_port->base.port))
+	if (intel_phy_is_tc(i915, phy))
 		intel_digital_port_connected(&dig_port->base);
 
 	intel_dp_encoder_reset(drm_encoder);
@@ -3945,10 +3954,11 @@ static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *i915 = to_i915(encoder->dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
 	intel_dp_encoder_flush_work(encoder);
 
-	if (intel_port_is_tc(i915, dig_port->base.port))
+	if (intel_phy_is_tc(i915, phy))
 		icl_tc_phy_disconnect(i915, dig_port);
 
 	drm_encoder_cleanup(encoder);
@@ -4198,6 +4208,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	struct drm_encoder *encoder;
 	bool init_hdmi, init_dp, init_lspcon = false;
 	enum pipe pipe;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
 	init_dp = port_info->supports_dp;
@@ -4261,7 +4272,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
 	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
 
-	intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
+	intel_dig_port->tc_legacy_port = intel_phy_is_tc(dev_priv, phy) &&
 					 !port_info->supports_typec_usb &&
 					 !port_info->supports_tbt;
 
@@ -4324,7 +4335,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 
 	intel_infoframe_init(intel_dig_port);
 
-	if (intel_port_is_tc(dev_priv, port))
+	if (intel_phy_is_tc(dev_priv, phy))
 		intel_digital_port_connected(intel_encoder);
 
 	return;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8592a7d422de..e72ace42327c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6560,31 +6560,39 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 	I915_WRITE(BCLRPAT(crtc->pipe), 0);
 }
 
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (port == PORT_NONE)
+	if (phy == PHY_NONE)
 		return false;
 
 	if (IS_ELKHARTLAKE(dev_priv))
-		return port <= PORT_C;
+		return phy <= PHY_C;
 
 	if (INTEL_GEN(dev_priv) >= 11)
-		return port <= PORT_B;
+		return phy <= PHY_B;
 
 	return false;
 }
 
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
-		return port >= PORT_C && port <= PORT_F;
+		return phy >= PHY_C && phy <= PHY_F;
 
 	return false;
 }
 
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
+{
+	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+		return PHY_A;
+
+	return (enum phy)port;
+}
+
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 {
-	if (!intel_port_is_tc(dev_priv, port))
+	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
 		return PORT_TC_NONE;
 
 	return port - PORT_C;
@@ -9922,9 +9930,10 @@ static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
 {
 	enum intel_dpll_id id;
 	u32 temp;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
-	temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
+	temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
 
 	if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
 		return;
@@ -9936,15 +9945,16 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
 				enum port port,
 				struct intel_crtc_state *pipe_config)
 {
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	enum intel_dpll_id id;
 	u32 temp;
 
 	/* TODO: TBT pll not implemented. */
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		temp = I915_READ(DPCLKA_CFGCR0_ICL) &
-		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
-	} else if (intel_port_is_tc(dev_priv, port)) {
+		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
 	} else {
 		WARN(1, "Invalid port %x\n", port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ee6b8194a459..f89b0b779f18 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -229,6 +229,21 @@ struct intel_link_m_n {
 	u32 link_n;
 };
 
+enum phy {
+	PHY_NONE = -1,
+
+	PHY_A = 0,
+	PHY_B,
+	PHY_C,
+	PHY_D,
+	PHY_E,
+	PHY_F,
+
+	I915_MAX_PHYS
+};
+
+#define phy_name(a) ((a) + 'A')
+
 #define for_each_pipe(__dev_priv, __p) \
 	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 
@@ -357,5 +372,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4336df46fe78..577538132a80 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -329,9 +329,9 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-	enum port port = dig_port->base.port;
+	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
-	if (intel_port_is_combophy(dev_priv, port) &&
+	if (intel_phy_is_combo(dev_priv, phy) &&
 	    !IS_ELKHARTLAKE(dev_priv) &&
 	    !intel_dp_is_edp(intel_dp))
 		return 540000;
@@ -5425,10 +5425,11 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
-	if (intel_port_is_combophy(dev_priv, encoder->port))
+	if (intel_phy_is_combo(dev_priv, phy))
 		return icl_combo_port_connected(dev_priv, dig_port);
-	else if (intel_port_is_tc(dev_priv, encoder->port))
+	else if (intel_phy_is_tc(dev_priv, phy))
 		return icl_tc_port_connected(dev_priv, dig_port);
 	else
 		MISSING_CASE(encoder->hpd_pin);
@@ -7332,6 +7333,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	struct drm_device *dev = intel_encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum port port = intel_encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int type;
 
 	/* Initialize the work for modeset in case of link train failure */
@@ -7358,7 +7360,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		 * Currently we don't support eDP on TypeC ports, although in
 		 * theory it could work on TypeC legacy ports.
 		 */
-		WARN_ON(intel_port_is_tc(dev_priv, port));
+		WARN_ON(intel_phy_is_tc(dev_priv, phy));
 		type = DRM_MODE_CONNECTOR_eDP;
 	} else {
 		type = DRM_MODE_CONNECTOR_DisplayPort;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2d4e7b9a7b9d..7bf697848055 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2513,7 +2513,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
 	struct skl_wrpll_params pll_params = { 0 };
 	bool ret;
 
-	if (intel_port_is_tc(dev_priv, encoder->port))
+	if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
+							encoder->port)))
 		ret = icl_calc_tbt_pll(crtc_state, &pll_params);
 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 		 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -2800,14 +2801,15 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
 	struct intel_digital_port *intel_dig_port;
 	struct intel_shared_dpll *pll;
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	enum intel_dpll_id min, max;
 	bool ret;
 
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		min = DPLL_ID_ICL_DPLL0;
 		max = DPLL_ID_ICL_DPLL1;
 		ret = icl_calc_dpll_state(crtc_state, encoder);
-	} else if (intel_port_is_tc(dev_priv, port)) {
+	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		if (encoder->type == INTEL_OUTPUT_DP_MST) {
 			struct intel_dp_mst_encoder *mst_encoder;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e748bb3f324..2a557895ec71 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,12 +1794,12 @@ enum i915_power_well_id {
 #define _ICL_COMBOPHY_A			0x162000
 #define _ICL_COMBOPHY_B			0x6C000
 #define _ICL_COMBOPHY_C_EHL		0x160000
-#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
+#define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
 					      _ICL_COMBOPHY_B, \
 					      _ICL_COMBOPHY_C_EHL)
 
 /* CNL/ICL Port CL_DW registers */
-#define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
 					 4 * (dw))
 
 #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
@@ -9681,15 +9681,15 @@ enum skl_power_gate {
  */
 #define DPCLKA_CFGCR0				_MMIO(0x6C200)
 #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
-#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
-						      (port) + 10))
-#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
+#define  DPCLKA_CFGCR0_DDI_CLK_OFF(phy)		(1 << ((phy) == PHY_F ? 23 : \
+						      (phy) + 10))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 25))
 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
 						      21 : (tc_port) + 12))
-#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
-						(port) * 2)
-#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
-#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) == PHY_F ? 21 : \
+						(phy) * 2)
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d58f7ec5d84..8c174bb767ba 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1473,8 +1473,8 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder);
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 			      enum port port);
 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
-- 
2.17.2

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 4/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'

[Matt Roper]

Our past DDI-based Intel platforms have had a fixed DDI<->PHY mapping.
Because of this, both the bspec documentation and our i915 code has used
the term "port" when talking about either DDI's or PHY's; it was always
easy to tell what terms like "Port A" were referring to from the
context.

Unfortunately this is starting to break down now that EHL allows PHY-A
to be driven by either DDI-A or DDI-D.  Is a setup with DDI-D driving
PHY-A considered "Port A" or "Port D?"  The answer depends on which
register we're working with, and even the bspec doesn't do a great job
of clarifying this.

Let's try to be more explicit about whether we're talking about the DDI
or the PHY on gen11+ by using 'port' to refer to the DDI and creating a
new 'enum phy' namespace to refer to the PHY in use.

A few general notes:

 - ICL_PORT_COMP_* and ICL_PORT_CL_* belong to the actual combo PHY so
   they should always be programmed according to the PHY in use,
   regardless of which DDI is driving it.

 - The pipe part of the hardware expects "port" to refer to the
   DDI, so registers like TRANS_CLK_SEL and TRANS_DDI_FUNC_CTL should
   set bits according to the desired DDI (e.g., DDI-D) rather than the
   PHY (PHY-A).

 - Non-pipe registers refer to the PHY.  Notably, DPCLKA_CFGCR0_ICL
   needs to set bits according to the PHY.

Most of the changes here are on the combo PHY side.  I didn't touch most
of the TC port code yet, so it still refers to everything as ports.
That's okay for now since there's no TC on EHL, but we'll probably want
to separate out the DDI vs PHY terminology for TC in the future as well
to avoid confusion.

v2:
 - Convert a few more 'port' uses to 'phy.' (Sparse)

Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c        |  24 ++-
 drivers/gpu/drm/i915/display/intel_bios.c     |   4 +-
 .../gpu/drm/i915/display/intel_combo_phy.c    | 143 +++++++++---------
 .../gpu/drm/i915/display/intel_combo_phy.h    |   3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      | 106 +++++++------
 drivers/gpu/drm/i915/display/intel_display.c  |  36 +++--
 drivers/gpu/drm/i915/display/intel_display.h  |  16 ++
 drivers/gpu/drm/i915/display/intel_dp.c       |  12 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   8 +-
 drivers/gpu/drm/i915/i915_reg.h               |  18 +--
 drivers/gpu/drm/i915/intel_drv.h              |   4 +-
 11 files changed, 215 insertions(+), 159 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index b8673debf932..b338746003ea 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -365,10 +365,13 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
+	enum phy phy;
 
-	for_each_dsi_port(port, intel_dsi->ports)
-		intel_combo_phy_power_up_lanes(dev_priv, port, true,
+	for_each_dsi_port(port, intel_dsi->ports) {
+		phy = intel_port_to_phy(dev_priv, port);
+		intel_combo_phy_power_up_lanes(dev_priv, phy, true,
 					       intel_dsi->lane_count, false);
+	}
 }
 
 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
@@ -560,11 +563,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
 	enum port port;
+	enum phy phy;
 
 	mutex_lock(&dev_priv->dpll_lock);
 	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_dsi_port(port, intel_dsi->ports) {
-		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		phy = intel_port_to_phy(dev_priv, port);
+		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 
 	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -577,11 +582,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 tmp;
 	enum port port;
+	enum phy phy;
 
 	mutex_lock(&dev_priv->dpll_lock);
 	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_dsi_port(port, intel_dsi->ports) {
-		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		phy = intel_port_to_phy(dev_priv, port);
+		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 
 	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
@@ -595,19 +602,22 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port;
+	enum phy phy;
 	u32 val;
 
 	mutex_lock(&dev_priv->dpll_lock);
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_dsi_port(port, intel_dsi->ports) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+		phy = intel_port_to_phy(dev_priv, port);
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 	}
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		phy = intel_port_to_phy(dev_priv, port);
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 	}
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 0c9808132d67..4fdbb5c35d87 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -28,6 +28,7 @@
 #include <drm/drm_dp_helper.h>
 #include <drm/i915_drm.h>
 
+#include "display/intel_display.h"
 #include "display/intel_gmbus.h"
 
 #include "i915_drv.h"
@@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct drm_i915_private *dev_priv)
 	for (port = PORT_A; port < I915_MAX_PORTS; port++) {
 		struct ddi_vbt_port_info *info =
 			&dev_priv->vbt.ddi_port_info[port];
+		enum phy phy = intel_port_to_phy(dev_priv, port);
 
 		/*
 		 * VBT has the TypeC mode (native,TBT/USB) and we don't want
 		 * to detect it.
 		 */
-		if (intel_port_is_tc(dev_priv, port))
+		if (intel_phy_is_tc(dev_priv, phy))
 			continue;
 
 		info->supports_dvi = (port != PORT_A && port != PORT_E);
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c
index da590f1a998b..7b3047335d91 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
@@ -6,13 +6,13 @@
 #include "intel_combo_phy.h"
 #include "intel_drv.h"
 
-#define for_each_combo_port(__dev_priv, __port) \
-	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_phy(__dev_priv, __phy) \
+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
 
-#define for_each_combo_port_reverse(__dev_priv, __port) \
-	for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
-		for_each_if(intel_port_is_combophy(__dev_priv, __port))
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
 
 enum {
 	PROCMON_0_85V_DOT_0,
@@ -38,18 +38,17 @@ static const struct cnl_procmon {
 };
 
 /*
- * CNL has just one set of registers, while ICL has two sets: one for port A and
- * the other for port B. The CNL registers are equivalent to the ICL port A
- * registers, that's why we call the ICL macros even though the function has CNL
- * on its name.
+ * CNL has just one set of registers, while gen11 has a set for each combo PHY.
+ * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
+ * call the ICL macros even though the function has CNL on its name.
  */
 static const struct cnl_procmon *
-cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
+cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	const struct cnl_procmon *procmon;
 	u32 val;
 
-	val = I915_READ(ICL_PORT_COMP_DW3(port));
+	val = I915_READ(ICL_PORT_COMP_DW3(phy));
 	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
 	default:
 		MISSING_CASE(val);
@@ -75,32 +74,32 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum port port)
 }
 
 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
-				       enum port port)
+				       enum phy phy)
 {
 	const struct cnl_procmon *procmon;
 	u32 val;
 
-	procmon = cnl_get_procmon_ref_values(dev_priv, port);
+	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
 
-	val = I915_READ(ICL_PORT_COMP_DW1(port));
+	val = I915_READ(ICL_PORT_COMP_DW1(phy));
 	val &= ~((0xff << 16) | 0xff);
 	val |= procmon->dw1;
-	I915_WRITE(ICL_PORT_COMP_DW1(port), val);
+	I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
 
-	I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
-	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
+	I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
+	I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
 }
 
 static bool check_phy_reg(struct drm_i915_private *dev_priv,
-			  enum port port, i915_reg_t reg, u32 mask,
+			  enum phy phy, i915_reg_t reg, u32 mask,
 			  u32 expected_val)
 {
 	u32 val = I915_READ(reg);
 
 	if ((val & mask) != expected_val) {
-		DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state mismatch: "
+		DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: "
 				 "current %08x mask %08x expected %08x\n",
-				 port_name(port),
+				 phy_name(phy),
 				 reg.reg, val, mask, expected_val);
 		return false;
 	}
@@ -109,18 +108,18 @@ static bool check_phy_reg(struct drm_i915_private *dev_priv,
 }
 
 static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv,
-					  enum port port)
+					  enum phy phy)
 {
 	const struct cnl_procmon *procmon;
 	bool ret;
 
-	procmon = cnl_get_procmon_ref_values(dev_priv, port);
+	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
 
-	ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
+	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
 			    (0xff << 16) | 0xff, procmon->dw1);
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
 			     -1U, procmon->dw9);
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
 			     -1U, procmon->dw10);
 
 	return ret;
@@ -134,15 +133,15 @@ static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv)
 
 static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
 {
-	enum port port = PORT_A;
+	enum phy phy = PHY_A;
 	bool ret;
 
 	if (!cnl_combo_phy_enabled(dev_priv))
 		return false;
 
-	ret = cnl_verify_procmon_ref_values(dev_priv, port);
+	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 
-	ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
+	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 
 	return ret;
@@ -157,7 +156,7 @@ static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
 	I915_WRITE(CHICKEN_MISC_2, val);
 
 	/* Dummy PORT_A to get the correct CNL register from the ICL macro */
-	cnl_set_procmon_ref_values(dev_priv, PORT_A);
+	cnl_set_procmon_ref_values(dev_priv, PHY_A);
 
 	val = I915_READ(CNL_PORT_COMP_DW0);
 	val |= COMP_INIT;
@@ -181,39 +180,39 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 }
 
 static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
-				  enum port port)
+				  enum phy phy)
 {
 	/* The PHY C added by EHL has no PHY_MISC register */
-	if (port == PORT_C)
-		return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
+	if (phy == PHY_C)
+		return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
 	else
-		return !(I915_READ(ICL_PHY_MISC(port)) &
+		return !(I915_READ(ICL_PHY_MISC(phy)) &
 			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
-			(I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT);
+			(I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT);
 }
 
 static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv,
-				       enum port port)
+				       enum phy phy)
 {
 	bool ret;
 
-	if (!icl_combo_phy_enabled(dev_priv, port))
+	if (!icl_combo_phy_enabled(dev_priv, phy))
 		return false;
 
-	ret = cnl_verify_procmon_ref_values(dev_priv, port);
+	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
 
-	if (port == PORT_A)
-		ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW8(port),
+	if (phy == PHY_A)
+		ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy),
 				     IREFGEN, IREFGEN);
 
-	ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
+	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
 			     CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE);
 
 	return ret;
 }
 
 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
-				    enum port port, bool is_dsi,
+				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal)
 {
 	u8 lane_mask;
@@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
 		}
 	}
 
-	val = I915_READ(ICL_PORT_CL_DW10(port));
+	val = I915_READ(ICL_PORT_CL_DW10(phy));
 	val &= ~PWR_DOWN_LN_MASK;
 	val |= lane_mask << PWR_DOWN_LN_SHIFT;
-	I915_WRITE(ICL_PORT_CL_DW10(port), val);
+	I915_WRITE(ICL_PORT_CL_DW10(phy), val);
 }
 
 static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
@@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val)
 
 static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 {
-	enum port port;
+	enum phy phy;
 
-	for_each_combo_port(dev_priv, port) {
+	for_each_combo_phy(dev_priv, phy) {
 		u32 val;
 
-		if (icl_combo_phy_verify_state(dev_priv, port)) {
-			DRM_DEBUG_DRIVER("Port %c combo PHY already enabled, won't reprogram it.\n",
-					 port_name(port));
+		if (icl_combo_phy_verify_state(dev_priv, phy)) {
+			DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n",
+					 phy_name(phy));
 			continue;
 		}
 
@@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 		 * register for it and no need to program the
 		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
 		 */
-		if (port != PORT_C) {
+		if (phy != PHY_C) {
 			/*
 			 * EHL's combo PHY A can be hooked up to either an
 			 * external display (via DDI-D) or an internal display
@@ -318,57 +317,57 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
 			 * indicates the presence of any "internal" child
 			 * devices.
 			 */
-			val = I915_READ(ICL_PHY_MISC(port));
-			if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
+			val = I915_READ(ICL_PHY_MISC(phy));
+			if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
 				val = ehl_combo_phy_a_mux(dev_priv, val);
 			val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-			I915_WRITE(ICL_PHY_MISC(port), val);
+			I915_WRITE(ICL_PHY_MISC(phy), val);
 		}
 
-		cnl_set_procmon_ref_values(dev_priv, port);
+		cnl_set_procmon_ref_values(dev_priv, phy);
 
-		if (port == PORT_A) {
-			val = I915_READ(ICL_PORT_COMP_DW8(port));
+		if (phy == PHY_A) {
+			val = I915_READ(ICL_PORT_COMP_DW8(phy));
 			val |= IREFGEN;
-			I915_WRITE(ICL_PORT_COMP_DW8(port), val);
+			I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
 		}
 
-		val = I915_READ(ICL_PORT_COMP_DW0(port));
+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
 		val |= COMP_INIT;
-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
 
-		val = I915_READ(ICL_PORT_CL_DW5(port));
+		val = I915_READ(ICL_PORT_CL_DW5(phy));
 		val |= CL_POWER_DOWN_ENABLE;
-		I915_WRITE(ICL_PORT_CL_DW5(port), val);
+		I915_WRITE(ICL_PORT_CL_DW5(phy), val);
 	}
 }
 
 static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
 {
-	enum port port;
+	enum phy phy;
 
-	for_each_combo_port_reverse(dev_priv, port) {
+	for_each_combo_phy_reverse(dev_priv, phy) {
 		u32 val;
 
-		if (port == PORT_A &&
-		    !icl_combo_phy_verify_state(dev_priv, port))
-			DRM_WARN("Port %c combo PHY HW state changed unexpectedly\n",
-				 port_name(port));
+		if (phy == PHY_A &&
+		    !icl_combo_phy_verify_state(dev_priv, phy))
+			DRM_WARN("Combo PHY %c HW state changed unexpectedly\n",
+				 phy_name(phy));
 
 		/*
 		 * Although EHL adds a combo PHY C, there's no PHY_MISC
 		 * register for it and no need to program the
 		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
 		 */
-		if (port != PORT_C) {
-			val = I915_READ(ICL_PHY_MISC(port));
+		if (phy != PHY_C) {
+			val = I915_READ(ICL_PHY_MISC(phy));
 			val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
-			I915_WRITE(ICL_PHY_MISC(port), val);
+			I915_WRITE(ICL_PHY_MISC(phy), val);
 		}
 
-		val = I915_READ(ICL_PORT_COMP_DW0(port));
+		val = I915_READ(ICL_PORT_COMP_DW0(phy));
 		val &= ~COMP_INIT;
-		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
+		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h b/drivers/gpu/drm/i915/display/intel_combo_phy.h
index e6e195a83b19..80a1386b4c87 100644
--- a/drivers/gpu/drm/i915/display/intel_combo_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h
@@ -10,11 +10,12 @@
 #include <drm/i915_drm.h>
 
 struct drm_i915_private;
+enum phy;
 
 void intel_combo_phy_init(struct drm_i915_private *dev_priv);
 void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
 void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
-				    enum port port, bool is_dsi,
+				    enum phy phy, bool is_dsi,
 				    int lane_count, bool lane_reversal);
 
 #endif /* __INTEL_COMBO_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 593806d44ad4..06998198c648 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -867,11 +867,12 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate,
 static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
 {
 	int n_entries, level, default_entry;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (intel_port_is_combophy(dev_priv, port))
+		if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI,
 						0, &n_entries);
 		else
@@ -1486,9 +1487,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int link_clock;
 
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
 	} else {
 		enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv,
@@ -2085,6 +2087,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	/*
 	 * TODO: Add support for MST encoders. Atm, the following should never
@@ -2102,7 +2105,7 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 	 * ports.
 	 */
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_port_is_tc(dev_priv, encoder->port))
+	    intel_phy_is_tc(dev_priv, phy))
 		intel_display_power_get(dev_priv,
 					intel_ddi_main_link_aux_domain(dig_port));
 
@@ -2227,10 +2230,11 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int n_entries;
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (intel_port_is_combophy(dev_priv, port))
+		if (intel_phy_is_combo(dev_priv, phy))
 			icl_get_combo_buf_trans(dev_priv, encoder->type,
 						intel_dp->link_rate, &n_entries);
 		else
@@ -2663,9 +2667,9 @@ static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
 				    enum intel_output_type type)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
-	if (intel_port_is_combophy(dev_priv, port))
+	if (intel_phy_is_combo(dev_priv, phy))
 		icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
 	else
 		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level);
@@ -2728,12 +2732,13 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp)
 
 static inline
 u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
-			      enum port port)
+			      enum phy phy)
 {
-	if (intel_port_is_combophy(dev_priv, port)) {
-		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
-	} else if (intel_port_is_tc(dev_priv, port)) {
-		enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+	if (intel_phy_is_combo(dev_priv, phy)) {
+		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
+	} else if (intel_phy_is_tc(dev_priv, phy)) {
+		enum tc_port tc_port = intel_port_to_tc(dev_priv,
+							(enum port)phy);
 
 		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
 	}
@@ -2746,22 +2751,22 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
-	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	u32 val;
 
 	mutex_lock(&dev_priv->dpll_lock);
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
-	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) == 0);
+	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
 
-	if (intel_port_is_combophy(dev_priv, port)) {
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+	if (intel_phy_is_combo(dev_priv, phy)) {
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 		POSTING_READ(DPCLKA_CFGCR0_ICL);
 	}
 
-	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	mutex_unlock(&dev_priv->dpll_lock);
@@ -2770,13 +2775,13 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	u32 val;
 
 	mutex_lock(&dev_priv->dpll_lock);
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
-	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 
 	mutex_unlock(&dev_priv->dpll_lock);
@@ -2837,9 +2842,11 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 
 	val = I915_READ(DPCLKA_CFGCR0_ICL);
 	for_each_port_masked(port, port_mask) {
+		enum phy phy = intel_port_to_phy(dev_priv, port);
+
 		bool ddi_clk_ungated = !(val &
 					 icl_dpclka_cfgcr0_clk_off(dev_priv,
-								   port));
+								   phy));
 
 		if (ddi_clk_needed == ddi_clk_ungated)
 			continue;
@@ -2851,9 +2858,9 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 		if (WARN_ON(ddi_clk_needed))
 			continue;
 
-		DRM_NOTE("Port %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
-			 port_name(port));
-		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
+		DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
+			 phy_name(port));
+		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
 		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
 	}
 }
@@ -2863,6 +2870,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	u32 val;
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 
@@ -2872,14 +2880,14 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 	mutex_lock(&dev_priv->dpll_lock);
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_port_is_combophy(dev_priv, port))
-			I915_WRITE(DDI_CLK_SEL(port),
+		if (!intel_phy_is_combo(dev_priv, phy))
+			I915_WRITE(DDI_CLK_SEL(phy),
 				   icl_pll_to_ddi_clk_sel(encoder, crtc_state));
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
 		val = I915_READ(DPCLKA_CFGCR0);
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 		I915_WRITE(DPCLKA_CFGCR0, val);
 
 		/*
@@ -2888,21 +2896,21 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
 		 * register writes.
 		 */
 		val = I915_READ(DPCLKA_CFGCR0);
-		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
+		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 		I915_WRITE(DPCLKA_CFGCR0, val);
 	} else if (IS_GEN9_BC(dev_priv)) {
 		/* DDI -> PLL mapping  */
 		val = I915_READ(DPLL_CTRL2);
 
-		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-			 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
-			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
+		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(phy) |
+			 DPLL_CTRL2_DDI_CLK_SEL_MASK(phy));
+		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, phy) |
+			DPLL_CTRL2_DDI_SEL_OVERRIDE(phy));
 
 		I915_WRITE(DPLL_CTRL2, val);
 
 	} else if (INTEL_GEN(dev_priv) < 9) {
-		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
+		I915_WRITE(PORT_CLK_SEL(phy), hsw_pll_to_ddi_pll_sel(pll));
 	}
 
 	mutex_unlock(&dev_priv->dpll_lock);
@@ -2912,18 +2920,19 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	if (INTEL_GEN(dev_priv) >= 11) {
-		if (!intel_port_is_combophy(dev_priv, port))
-			I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
+		if (!intel_phy_is_combo(dev_priv, phy))
+			I915_WRITE(DDI_CLK_SEL(phy), DDI_CLK_SEL_NONE);
 	} else if (IS_CANNONLAKE(dev_priv)) {
 		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
-			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+			   DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 	} else if (IS_GEN9_BC(dev_priv)) {
 		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
-			   DPLL_CTRL2_DDI_CLK_OFF(port));
+			   DPLL_CTRL2_DDI_CLK_OFF(phy));
 	} else if (INTEL_GEN(dev_priv) < 9) {
-		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
+		I915_WRITE(PORT_CLK_SEL(phy), PORT_CLK_SEL_NONE);
 	}
 }
 
@@ -3110,6 +3119,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
 	int level = intel_ddi_dp_level(intel_dp);
@@ -3138,11 +3148,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	else
 		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
 
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		bool lane_reversal =
 			dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
 
-		intel_combo_phy_power_up_lanes(dev_priv, port, false,
+		intel_combo_phy_power_up_lanes(dev_priv, phy, false,
 					       crtc_state->lane_count,
 					       lane_reversal);
 	}
@@ -3630,7 +3640,7 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder,
 	enum port port = encoder->port;
 
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_port_is_tc(dev_priv, encoder->port))
+	    intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
 		intel_display_power_get(dev_priv,
 					intel_ddi_main_link_aux_domain(dig_port));
 
@@ -3656,9 +3666,10 @@ intel_ddi_post_pll_disable(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
 	if (intel_crtc_has_dp_encoder(crtc_state) ||
-	    intel_port_is_tc(dev_priv, encoder->port))
+	    intel_phy_is_tc(dev_priv, phy))
 		intel_display_power_put_unchecked(dev_priv,
 						  intel_ddi_main_link_aux_domain(dig_port));
 }
@@ -3934,8 +3945,9 @@ static void intel_ddi_encoder_reset(struct drm_encoder *drm_encoder)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(drm_encoder);
 	struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
-	if (intel_port_is_tc(i915, dig_port->base.port))
+	if (intel_phy_is_tc(i915, phy))
 		intel_digital_port_connected(&dig_port->base);
 
 	intel_dp_encoder_reset(drm_encoder);
@@ -3945,10 +3957,11 @@ static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *i915 = to_i915(encoder->dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
 
 	intel_dp_encoder_flush_work(encoder);
 
-	if (intel_port_is_tc(i915, dig_port->base.port))
+	if (intel_phy_is_tc(i915, phy))
 		icl_tc_phy_disconnect(i915, dig_port);
 
 	drm_encoder_cleanup(encoder);
@@ -4198,6 +4211,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	struct drm_encoder *encoder;
 	bool init_hdmi, init_dp, init_lspcon = false;
 	enum pipe pipe;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
 	init_hdmi = port_info->supports_dvi || port_info->supports_hdmi;
 	init_dp = port_info->supports_dp;
@@ -4261,7 +4275,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 	intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
 	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
 
-	intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv, port) &&
+	intel_dig_port->tc_legacy_port = intel_phy_is_tc(dev_priv, phy) &&
 					 !port_info->supports_typec_usb &&
 					 !port_info->supports_tbt;
 
@@ -4324,7 +4338,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
 
 	intel_infoframe_init(intel_dig_port);
 
-	if (intel_port_is_tc(dev_priv, port))
+	if (intel_phy_is_tc(dev_priv, phy))
 		intel_digital_port_connected(intel_encoder);
 
 	return;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8592a7d422de..e72ace42327c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6560,31 +6560,39 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
 	I915_WRITE(BCLRPAT(crtc->pipe), 0);
 }
 
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port)
+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (port == PORT_NONE)
+	if (phy == PHY_NONE)
 		return false;
 
 	if (IS_ELKHARTLAKE(dev_priv))
-		return port <= PORT_C;
+		return phy <= PHY_C;
 
 	if (INTEL_GEN(dev_priv) >= 11)
-		return port <= PORT_B;
+		return phy <= PHY_B;
 
 	return false;
 }
 
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port)
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
 	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
-		return port >= PORT_C && port <= PORT_F;
+		return phy >= PHY_C && phy <= PHY_F;
 
 	return false;
 }
 
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
+{
+	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
+		return PHY_A;
+
+	return (enum phy)port;
+}
+
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
 {
-	if (!intel_port_is_tc(dev_priv, port))
+	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
 		return PORT_TC_NONE;
 
 	return port - PORT_C;
@@ -9922,9 +9930,10 @@ static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv,
 {
 	enum intel_dpll_id id;
 	u32 temp;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 
-	temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
+	temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
 
 	if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
 		return;
@@ -9936,15 +9945,16 @@ static void icelake_get_ddi_pll(struct drm_i915_private *dev_priv,
 				enum port port,
 				struct intel_crtc_state *pipe_config)
 {
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	enum intel_dpll_id id;
 	u32 temp;
 
 	/* TODO: TBT pll not implemented. */
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		temp = I915_READ(DPCLKA_CFGCR0_ICL) &
-		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
-	} else if (intel_port_is_tc(dev_priv, port)) {
+		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
+		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
+	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port));
 	} else {
 		WARN(1, "Invalid port %x\n", port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index ee6b8194a459..f89b0b779f18 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -229,6 +229,21 @@ struct intel_link_m_n {
 	u32 link_n;
 };
 
+enum phy {
+	PHY_NONE = -1,
+
+	PHY_A = 0,
+	PHY_B,
+	PHY_C,
+	PHY_D,
+	PHY_E,
+	PHY_F,
+
+	I915_MAX_PHYS
+};
+
+#define phy_name(a) ((a) + 'A')
+
 #define for_each_pipe(__dev_priv, __p) \
 	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 
@@ -357,5 +372,6 @@ void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 			      u32 pixel_format, u64 modifier);
 bool intel_plane_can_remap(const struct intel_plane_state *plane_state);
+enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4336df46fe78..577538132a80 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -329,9 +329,9 @@ static int icl_max_source_rate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
-	enum port port = dig_port->base.port;
+	enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 
-	if (intel_port_is_combophy(dev_priv, port) &&
+	if (intel_phy_is_combo(dev_priv, phy) &&
 	    !IS_ELKHARTLAKE(dev_priv) &&
 	    !intel_dp_is_edp(intel_dp))
 		return 540000;
@@ -5425,10 +5425,11 @@ static bool icl_digital_port_connected(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 
-	if (intel_port_is_combophy(dev_priv, encoder->port))
+	if (intel_phy_is_combo(dev_priv, phy))
 		return icl_combo_port_connected(dev_priv, dig_port);
-	else if (intel_port_is_tc(dev_priv, encoder->port))
+	else if (intel_phy_is_tc(dev_priv, phy))
 		return icl_tc_port_connected(dev_priv, dig_port);
 	else
 		MISSING_CASE(encoder->hpd_pin);
@@ -7332,6 +7333,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 	struct drm_device *dev = intel_encoder->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	enum port port = intel_encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	int type;
 
 	/* Initialize the work for modeset in case of link train failure */
@@ -7358,7 +7360,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		 * Currently we don't support eDP on TypeC ports, although in
 		 * theory it could work on TypeC legacy ports.
 		 */
-		WARN_ON(intel_port_is_tc(dev_priv, port));
+		WARN_ON(intel_phy_is_tc(dev_priv, phy));
 		type = DRM_MODE_CONNECTOR_eDP;
 	} else {
 		type = DRM_MODE_CONNECTOR_DisplayPort;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2d4e7b9a7b9d..7bf697848055 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2513,7 +2513,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
 	struct skl_wrpll_params pll_params = { 0 };
 	bool ret;
 
-	if (intel_port_is_tc(dev_priv, encoder->port))
+	if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
+							encoder->port)))
 		ret = icl_calc_tbt_pll(crtc_state, &pll_params);
 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
 		 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
@@ -2800,14 +2801,15 @@ icl_get_dpll(struct intel_crtc_state *crtc_state,
 	struct intel_digital_port *intel_dig_port;
 	struct intel_shared_dpll *pll;
 	enum port port = encoder->port;
+	enum phy phy = intel_port_to_phy(dev_priv, port);
 	enum intel_dpll_id min, max;
 	bool ret;
 
-	if (intel_port_is_combophy(dev_priv, port)) {
+	if (intel_phy_is_combo(dev_priv, phy)) {
 		min = DPLL_ID_ICL_DPLL0;
 		max = DPLL_ID_ICL_DPLL1;
 		ret = icl_calc_dpll_state(crtc_state, encoder);
-	} else if (intel_port_is_tc(dev_priv, port)) {
+	} else if (intel_phy_is_tc(dev_priv, phy)) {
 		if (encoder->type == INTEL_OUTPUT_DP_MST) {
 			struct intel_dp_mst_encoder *mst_encoder;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e748bb3f324..2a557895ec71 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1794,12 +1794,12 @@ enum i915_power_well_id {
 #define _ICL_COMBOPHY_A			0x162000
 #define _ICL_COMBOPHY_B			0x6C000
 #define _ICL_COMBOPHY_C_EHL		0x160000
-#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
+#define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
 					      _ICL_COMBOPHY_B, \
 					      _ICL_COMBOPHY_C_EHL)
 
 /* CNL/ICL Port CL_DW registers */
-#define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
+#define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
 					 4 * (dw))
 
 #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
@@ -9681,15 +9681,15 @@ enum skl_power_gate {
  */
 #define DPCLKA_CFGCR0				_MMIO(0x6C200)
 #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
-#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
-						      (port) + 10))
-#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
+#define  DPCLKA_CFGCR0_DDI_CLK_OFF(phy)		(1 << ((phy) == PHY_F ? 23 : \
+						      (phy) + 10))
+#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10, 11, 25))
 #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) == PORT_TC4 ? \
 						      21 : (tc_port) + 12))
-#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
-						(port) * 2)
-#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
-#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) == PHY_F ? 21 : \
+						(phy) * 2)
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
 
 /* CNL PLL */
 #define DPLL0_ENABLE		0x46010
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d58f7ec5d84..8c174bb767ba 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1473,8 +1473,8 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder);
-bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum port port);
-bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
+bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
+bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
 			      enum port port);
 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
-- 
2.17.2

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Intel-gfx@lists.freedesktop.org
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Re: [PATCH 4/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'

[Souza, Jose]

On Fri, 2019-06-21 at 07:08 -0700, Matt Roper wrote:
> Our past DDI-based Intel platforms have had a fixed DDI<->PHY
> mapping.
> Because of this, both the bspec documentation and our i915 code has
> used
> the term "port" when talking about either DDI's or PHY's; it was
> always
> easy to tell what terms like "Port A" were referring to from the
> context.
> 
> Unfortunately this is starting to break down now that EHL allows PHY-
> A
> to be driven by either DDI-A or DDI-D.  Is a setup with DDI-D driving
> PHY-A considered "Port A" or "Port D?"  The answer depends on which
> register we're working with, and even the bspec doesn't do a great
> job
> of clarifying this.
> 
> Let's try to be more explicit about whether we're talking about the
> DDI
> or the PHY on gen11+ by using 'port' to refer to the DDI and creating
> a
> new 'enum phy' namespace to refer to the PHY in use.
> 
> A few general notes:
> 
>  - ICL_PORT_COMP_* and ICL_PORT_CL_* belong to the actual combo PHY
> so
>    they should always be programmed according to the PHY in use,
>    regardless of which DDI is driving it.
> 
>  - The pipe part of the hardware expects "port" to refer to the
>    DDI, so registers like TRANS_CLK_SEL and TRANS_DDI_FUNC_CTL should
>    set bits according to the desired DDI (e.g., DDI-D) rather than
> the
>    PHY (PHY-A).
> 
>  - Non-pipe registers refer to the PHY.  Notably, DPCLKA_CFGCR0_ICL
>    needs to set bits according to the PHY.
> 
> Most of the changes here are on the combo PHY side.  I didn't touch
> most
> of the TC port code yet, so it still refers to everything as ports.
> That's okay for now since there's no TC on EHL, but we'll probably
> want
> to separate out the DDI vs PHY terminology for TC in the future as
> well
> to avoid confusion.
> 
> v2:
>  - Convert a few more 'port' uses to 'phy.' (Sparse)
> 
> Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c        |  24 ++-
>  drivers/gpu/drm/i915/display/intel_bios.c     |   4 +-
>  .../gpu/drm/i915/display/intel_combo_phy.c    | 143 +++++++++-------
> --
>  .../gpu/drm/i915/display/intel_combo_phy.h    |   3 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 106 +++++++------
>  drivers/gpu/drm/i915/display/intel_display.c  |  36 +++--
>  drivers/gpu/drm/i915/display/intel_display.h  |  16 ++
>  drivers/gpu/drm/i915/display/intel_dp.c       |  12 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   8 +-
>  drivers/gpu/drm/i915/i915_reg.h               |  18 +--
>  drivers/gpu/drm/i915/intel_drv.h              |   4 +-
>  11 files changed, 215 insertions(+), 159 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b8673debf932..b338746003ea 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -365,10 +365,13 @@ static void gen11_dsi_power_up_lanes(struct
> intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	enum port port;
> +	enum phy phy;
>  
> -	for_each_dsi_port(port, intel_dsi->ports)
> -		intel_combo_phy_power_up_lanes(dev_priv, port, true,
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +		phy = intel_port_to_phy(dev_priv, port);
> +		intel_combo_phy_power_up_lanes(dev_priv, phy, true,
>  					       intel_dsi->lane_count,
> false);
> +	}
>  }
>  
>  static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
> *encoder)
> @@ -560,11 +563,13 @@ static void gen11_dsi_gate_clocks(struct
> intel_encoder *encoder)
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u32 tmp;
>  	enum port port;
> +	enum phy phy;
>  
>  	mutex_lock(&dev_priv->dpll_lock);
>  	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> +		phy = intel_port_to_phy(dev_priv, port);
> +		tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>  	}
>  
>  	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -577,11 +582,13 @@ static void gen11_dsi_ungate_clocks(struct
> intel_encoder *encoder)
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u32 tmp;
>  	enum port port;
> +	enum phy phy;
>  
>  	mutex_lock(&dev_priv->dpll_lock);
>  	tmp = I915_READ(DPCLKA_CFGCR0_ICL);
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> +		phy = intel_port_to_phy(dev_priv, port);
> +		tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>  	}
>  
>  	I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -595,19 +602,22 @@ static void gen11_dsi_map_pll(struct
> intel_encoder *encoder,
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>  	enum port port;
> +	enum phy phy;
>  	u32 val;
>  
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	val = I915_READ(DPCLKA_CFGCR0_ICL);
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> -		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> +		phy = intel_port_to_phy(dev_priv, port);
> +		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
>  	}
>  	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> +		phy = intel_port_to_phy(dev_priv, port);
> +		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>  	}
>  	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 0c9808132d67..4fdbb5c35d87 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -28,6 +28,7 @@
>  #include <drm/drm_dp_helper.h>
>  #include <drm/i915_drm.h>
>  
> +#include "display/intel_display.h"
>  #include "display/intel_gmbus.h"
>  
>  #include "i915_drv.h"
> @@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct
> drm_i915_private *dev_priv)
>  	for (port = PORT_A; port < I915_MAX_PORTS; port++) {
>  		struct ddi_vbt_port_info *info =
>  			&dev_priv->vbt.ddi_port_info[port];
> +		enum phy phy = intel_port_to_phy(dev_priv, port);
>  
>  		/*
>  		 * VBT has the TypeC mode (native,TBT/USB) and we don't
> want
>  		 * to detect it.
>  		 */
> -		if (intel_port_is_tc(dev_priv, port))
> +		if (intel_phy_is_tc(dev_priv, phy))
>  			continue;
>  
>  		info->supports_dvi = (port != PORT_A && port !=
> PORT_E);
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index da590f1a998b..7b3047335d91 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -6,13 +6,13 @@
>  #include "intel_combo_phy.h"
>  #include "intel_drv.h"
>  
> -#define for_each_combo_port(__dev_priv, __port) \
> -	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	
> \
> -		for_each_if(intel_port_is_combophy(__dev_priv, __port))
> +#define for_each_combo_phy(__dev_priv, __phy) \
> +	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
> +		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
>  
> -#define for_each_combo_port_reverse(__dev_priv, __port) \
> -	for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
> -		for_each_if(intel_port_is_combophy(__dev_priv, __port))
> +#define for_each_combo_phy_reverse(__dev_priv, __phy) \
> +	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
> +		for_each_if(intel_phy_is_combo(__dev_priv, __phy))
>  
>  enum {
>  	PROCMON_0_85V_DOT_0,
> @@ -38,18 +38,17 @@ static const struct cnl_procmon {
>  };
>  
>  /*
> - * CNL has just one set of registers, while ICL has two sets: one
> for port A and
> - * the other for port B. The CNL registers are equivalent to the ICL
> port A
> - * registers, that's why we call the ICL macros even though the
> function has CNL
> - * on its name.
> + * CNL has just one set of registers, while gen11 has a set for each
> combo PHY.
> + * The CNL registers are equivalent to the gen11 PHY A registers,
> that's why we
> + * call the ICL macros even though the function has CNL on its name.
>   */
>  static const struct cnl_procmon *
> -cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum
> port port)
> +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum
> phy phy)
>  {
>  	const struct cnl_procmon *procmon;
>  	u32 val;
>  
> -	val = I915_READ(ICL_PORT_COMP_DW3(port));
> +	val = I915_READ(ICL_PORT_COMP_DW3(phy));
>  	switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
>  	default:
>  		MISSING_CASE(val);
> @@ -75,32 +74,32 @@ cnl_get_procmon_ref_values(struct
> drm_i915_private *dev_priv, enum port port)
>  }
>  
>  static void cnl_set_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> -				       enum port port)
> +				       enum phy phy)
>  {
>  	const struct cnl_procmon *procmon;
>  	u32 val;
>  
> -	procmon = cnl_get_procmon_ref_values(dev_priv, port);
> +	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
>  
> -	val = I915_READ(ICL_PORT_COMP_DW1(port));
> +	val = I915_READ(ICL_PORT_COMP_DW1(phy));
>  	val &= ~((0xff << 16) | 0xff);
>  	val |= procmon->dw1;
> -	I915_WRITE(ICL_PORT_COMP_DW1(port), val);
> +	I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
>  
> -	I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
> -	I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> +	I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
> +	I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
>  }
>  
>  static bool check_phy_reg(struct drm_i915_private *dev_priv,
> -			  enum port port, i915_reg_t reg, u32 mask,
> +			  enum phy phy, i915_reg_t reg, u32 mask,
>  			  u32 expected_val)
>  {
>  	u32 val = I915_READ(reg);
>  
>  	if ((val & mask) != expected_val) {
> -		DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state
> mismatch: "
> +		DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch:
> "
>  				 "current %08x mask %08x expected
> %08x\n",
> -				 port_name(port),
> +				 phy_name(phy),
>  				 reg.reg, val, mask, expected_val);
>  		return false;
>  	}
> @@ -109,18 +108,18 @@ static bool check_phy_reg(struct
> drm_i915_private *dev_priv,
>  }
>  
>  static bool cnl_verify_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> -					  enum port port)
> +					  enum phy phy)
>  {
>  	const struct cnl_procmon *procmon;
>  	bool ret;
>  
> -	procmon = cnl_get_procmon_ref_values(dev_priv, port);
> +	procmon = cnl_get_procmon_ref_values(dev_priv, phy);
>  
> -	ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
> +	ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
>  			    (0xff << 16) | 0xff, procmon->dw1);
> -	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
> +	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
>  			     -1U, procmon->dw9);
> -	ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
> +	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
>  			     -1U, procmon->dw10);
>  
>  	return ret;
> @@ -134,15 +133,15 @@ static bool cnl_combo_phy_enabled(struct
> drm_i915_private *dev_priv)
>  
>  static bool cnl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv)
>  {
> -	enum port port = PORT_A;
> +	enum phy phy = PHY_A;
>  	bool ret;
>  
>  	if (!cnl_combo_phy_enabled(dev_priv))
>  		return false;
>  
> -	ret = cnl_verify_procmon_ref_values(dev_priv, port);
> +	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
>  
> -	ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
> +	ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
>  			     CL_POWER_DOWN_ENABLE,
> CL_POWER_DOWN_ENABLE);
>  
>  	return ret;
> @@ -157,7 +156,7 @@ static void cnl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  	I915_WRITE(CHICKEN_MISC_2, val);
>  
>  	/* Dummy PORT_A to get the correct CNL register from the ICL
> macro */
> -	cnl_set_procmon_ref_values(dev_priv, PORT_A);
> +	cnl_set_procmon_ref_values(dev_priv, PHY_A);
>  
>  	val = I915_READ(CNL_PORT_COMP_DW0);
>  	val |= COMP_INIT;
> @@ -181,39 +180,39 @@ static void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
>  }
>  
>  static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> -				  enum port port)
> +				  enum phy phy)
>  {
>  	/* The PHY C added by EHL has no PHY_MISC register */
> -	if (port == PORT_C)
> -		return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
> +	if (phy == PHY_C)
> +		return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
>  	else
> -		return !(I915_READ(ICL_PHY_MISC(port)) &
> +		return !(I915_READ(ICL_PHY_MISC(phy)) &
>  			 ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> -			(I915_READ(ICL_PORT_COMP_DW0(port)) &
> COMP_INIT);
> +			(I915_READ(ICL_PORT_COMP_DW0(phy)) &
> COMP_INIT);
>  }
>  
>  static bool icl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv,
> -				       enum port port)
> +				       enum phy phy)
>  {
>  	bool ret;
>  
> -	if (!icl_combo_phy_enabled(dev_priv, port))
> +	if (!icl_combo_phy_enabled(dev_priv, phy))
>  		return false;
>  
> -	ret = cnl_verify_procmon_ref_values(dev_priv, port);
> +	ret = cnl_verify_procmon_ref_values(dev_priv, phy);
>  
> -	if (port == PORT_A)
> -		ret &= check_phy_reg(dev_priv, port,
> ICL_PORT_COMP_DW8(port),
> +	if (phy == PHY_A)
> +		ret &= check_phy_reg(dev_priv, phy,
> ICL_PORT_COMP_DW8(phy),
>  				     IREFGEN, IREFGEN);
>  
> -	ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
> +	ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
>  			     CL_POWER_DOWN_ENABLE,
> CL_POWER_DOWN_ENABLE);
>  
>  	return ret;
>  }
>  
>  void intel_combo_phy_power_up_lanes(struct drm_i915_private
> *dev_priv,
> -				    enum port port, bool is_dsi,
> +				    enum phy phy, bool is_dsi,
>  				    int lane_count, bool lane_reversal)
>  {
>  	u8 lane_mask;
> @@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct
> drm_i915_private *dev_priv,
>  		}
>  	}
>  
> -	val = I915_READ(ICL_PORT_CL_DW10(port));
> +	val = I915_READ(ICL_PORT_CL_DW10(phy));
>  	val &= ~PWR_DOWN_LN_MASK;
>  	val |= lane_mask << PWR_DOWN_LN_SHIFT;
> -	I915_WRITE(ICL_PORT_CL_DW10(port), val);
> +	I915_WRITE(ICL_PORT_CL_DW10(phy), val);
>  }
>  
>  static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32
> val)
> @@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct
> drm_i915_private *i915, u32 val)
>  
>  static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
>  {
> -	enum port port;
> +	enum phy phy;
>  
> -	for_each_combo_port(dev_priv, port) {
> +	for_each_combo_phy(dev_priv, phy) {
>  		u32 val;
>  
> -		if (icl_combo_phy_verify_state(dev_priv, port)) {
> -			DRM_DEBUG_DRIVER("Port %c combo PHY already
> enabled, won't reprogram it.\n",
> -					 port_name(port));
> +		if (icl_combo_phy_verify_state(dev_priv, phy)) {
> +			DRM_DEBUG_DRIVER("Combo PHY %c already enabled,
> won't reprogram it.\n",
> +					 phy_name(phy));
>  			continue;
>  		}
>  
> @@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  		 * register for it and no need to program the
>  		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
>  		 */
> -		if (port != PORT_C) {
> +		if (phy != PHY_C) {
>  			/*
>  			 * EHL's combo PHY A can be hooked up to either
> an
>  			 * external display (via DDI-D) or an internal
> display
> @@ -318,57 +317,57 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
>  			 * indicates the presence of any "internal"
> child
>  			 * devices.
>  			 */
> -			val = I915_READ(ICL_PHY_MISC(port));
> -			if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
> +			val = I915_READ(ICL_PHY_MISC(phy));
> +			if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
>  				val = ehl_combo_phy_a_mux(dev_priv,
> val);
>  			val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> -			I915_WRITE(ICL_PHY_MISC(port), val);
> +			I915_WRITE(ICL_PHY_MISC(phy), val);
>  		}
>  
> -		cnl_set_procmon_ref_values(dev_priv, port);
> +		cnl_set_procmon_ref_values(dev_priv, phy);
>  
> -		if (port == PORT_A) {
> -			val = I915_READ(ICL_PORT_COMP_DW8(port));
> +		if (phy == PHY_A) {
> +			val = I915_READ(ICL_PORT_COMP_DW8(phy));
>  			val |= IREFGEN;
> -			I915_WRITE(ICL_PORT_COMP_DW8(port), val);
> +			I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
>  		}
>  
> -		val = I915_READ(ICL_PORT_COMP_DW0(port));
> +		val = I915_READ(ICL_PORT_COMP_DW0(phy));
>  		val |= COMP_INIT;
> -		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
> +		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
>  
> -		val = I915_READ(ICL_PORT_CL_DW5(port));
> +		val = I915_READ(ICL_PORT_CL_DW5(phy));
>  		val |= CL_POWER_DOWN_ENABLE;
> -		I915_WRITE(ICL_PORT_CL_DW5(port), val);
> +		I915_WRITE(ICL_PORT_CL_DW5(phy), val);
>  	}
>  }
>  
>  static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
>  {
> -	enum port port;
> +	enum phy phy;
>  
> -	for_each_combo_port_reverse(dev_priv, port) {
> +	for_each_combo_phy_reverse(dev_priv, phy) {
>  		u32 val;
>  
> -		if (port == PORT_A &&
> -		    !icl_combo_phy_verify_state(dev_priv, port))
> -			DRM_WARN("Port %c combo PHY HW state changed
> unexpectedly\n",
> -				 port_name(port));
> +		if (phy == PHY_A &&
> +		    !icl_combo_phy_verify_state(dev_priv, phy))
> +			DRM_WARN("Combo PHY %c HW state changed
> unexpectedly\n",
> +				 phy_name(phy));
>  
>  		/*
>  		 * Although EHL adds a combo PHY C, there's no PHY_MISC
>  		 * register for it and no need to program the
>  		 * DE_IO_COMP_PWR_DOWN setting on PHY C.
>  		 */
> -		if (port != PORT_C) {
> -			val = I915_READ(ICL_PHY_MISC(port));
> +		if (phy != PHY_C) {
> +			val = I915_READ(ICL_PHY_MISC(phy));
>  			val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> -			I915_WRITE(ICL_PHY_MISC(port), val);
> +			I915_WRITE(ICL_PHY_MISC(phy), val);
>  		}
>  
> -		val = I915_READ(ICL_PORT_COMP_DW0(port));
> +		val = I915_READ(ICL_PORT_COMP_DW0(phy));
>  		val &= ~COMP_INIT;
> -		I915_WRITE(ICL_PORT_COMP_DW0(port), val);
> +		I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h
> b/drivers/gpu/drm/i915/display/intel_combo_phy.h
> index e6e195a83b19..80a1386b4c87 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h
> @@ -10,11 +10,12 @@
>  #include <drm/i915_drm.h>
>  
>  struct drm_i915_private;
> +enum phy;
>  
>  void intel_combo_phy_init(struct drm_i915_private *dev_priv);
>  void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
>  void intel_combo_phy_power_up_lanes(struct drm_i915_private
> *dev_priv,
> -				    enum port port, bool is_dsi,
> +				    enum phy phy, bool is_dsi,
>  				    int lane_count, bool
> lane_reversal);
>  
>  #endif /* __INTEL_COMBO_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 593806d44ad4..06998198c648 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -867,11 +867,12 @@ icl_get_combo_buf_trans(struct drm_i915_private
> *dev_priv, int type, int rate,
>  static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv,
> enum port port)
>  {
>  	int n_entries, level, default_entry;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  
>  	level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>  
>  	if (INTEL_GEN(dev_priv) >= 11) {
> -		if (intel_port_is_combophy(dev_priv, port))
> +		if (intel_phy_is_combo(dev_priv, phy))
>  			icl_get_combo_buf_trans(dev_priv,
> INTEL_OUTPUT_HDMI,
>  						0, &n_entries);
>  		else
> @@ -1486,9 +1487,10 @@ static void icl_ddi_clock_get(struct
> intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dpll_hw_state *pll_state = &pipe_config-
> >dpll_hw_state;
>  	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	int link_clock;
>  
> -	if (intel_port_is_combophy(dev_priv, port)) {
> +	if (intel_phy_is_combo(dev_priv, phy)) {
>  		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
>  	} else {
>  		enum intel_dpll_id pll_id =
> intel_get_shared_dpll_id(dev_priv,
> @@ -2085,6 +2087,7 @@ static void intel_ddi_get_power_domains(struct
> intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port;
> +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  
>  	/*
>  	 * TODO: Add support for MST encoders. Atm, the following
> should never
> @@ -2102,7 +2105,7 @@ static void intel_ddi_get_power_domains(struct
> intel_encoder *encoder,
>  	 * ports.
>  	 */
>  	if (intel_crtc_has_dp_encoder(crtc_state) ||
> -	    intel_port_is_tc(dev_priv, encoder->port))
> +	    intel_phy_is_tc(dev_priv, phy))
>  		intel_display_power_get(dev_priv,
>  					intel_ddi_main_link_aux_domain(
> dig_port));
>  
> @@ -2227,10 +2230,11 @@ u8 intel_ddi_dp_voltage_max(struct
> intel_encoder *encoder)
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	int n_entries;
>  
>  	if (INTEL_GEN(dev_priv) >= 11) {
> -		if (intel_port_is_combophy(dev_priv, port))
> +		if (intel_phy_is_combo(dev_priv, phy))
>  			icl_get_combo_buf_trans(dev_priv, encoder-
> >type,
>  						intel_dp->link_rate,
> &n_entries);
>  		else
> @@ -2663,9 +2667,9 @@ static void icl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
>  				    enum intel_output_type type)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  
> -	if (intel_port_is_combophy(dev_priv, port))
> +	if (intel_phy_is_combo(dev_priv, phy))
>  		icl_combo_phy_ddi_vswing_sequence(encoder, level,
> type);
>  	else
>  		icl_mg_phy_ddi_vswing_sequence(encoder, link_clock,
> level);
> @@ -2728,12 +2732,13 @@ u32 ddi_signal_levels(struct intel_dp
> *intel_dp)
>  
>  static inline
>  u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> -			      enum port port)
> +			      enum phy phy)
>  {
> -	if (intel_port_is_combophy(dev_priv, port)) {
> -		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> -	} else if (intel_port_is_tc(dev_priv, port)) {
> -		enum tc_port tc_port = intel_port_to_tc(dev_priv,
> port);
> +	if (intel_phy_is_combo(dev_priv, phy)) {
> +		return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> +	} else if (intel_phy_is_tc(dev_priv, phy)) {
> +		enum tc_port tc_port = intel_port_to_tc(dev_priv,
> +							(enum
> port)phy);
>  
>  		return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
>  	}
> @@ -2746,22 +2751,22 @@ static void icl_map_plls_to_ports(struct
> intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> -	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  	u32 val;
>  
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	val = I915_READ(DPCLKA_CFGCR0_ICL);
> -	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) ==
> 0);
> +	WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
>  
> -	if (intel_port_is_combophy(dev_priv, port)) {
> -		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> -		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> +	if (intel_phy_is_combo(dev_priv, phy)) {
> +		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
>  		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>  		POSTING_READ(DPCLKA_CFGCR0_ICL);
>  	}
>  
> -	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> +	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
>  	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>  
>  	mutex_unlock(&dev_priv->dpll_lock);
> @@ -2770,13 +2775,13 @@ static void icl_map_plls_to_ports(struct
> intel_encoder *encoder,
>  static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  	u32 val;
>  
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	val = I915_READ(DPCLKA_CFGCR0_ICL);
> -	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> +	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
>  	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>  
>  	mutex_unlock(&dev_priv->dpll_lock);
> @@ -2837,9 +2842,11 @@ void icl_sanitize_encoder_pll_mapping(struct
> intel_encoder *encoder)
>  
>  	val = I915_READ(DPCLKA_CFGCR0_ICL);
>  	for_each_port_masked(port, port_mask) {
> +		enum phy phy = intel_port_to_phy(dev_priv, port);
> +
>  		bool ddi_clk_ungated = !(val &
>  					 icl_dpclka_cfgcr0_clk_off(dev_
> priv,
> -								   port
> ));
> +								   phy)
> );
>  
>  		if (ddi_clk_needed == ddi_clk_ungated)
>  			continue;
> @@ -2851,9 +2858,9 @@ void icl_sanitize_encoder_pll_mapping(struct
> intel_encoder *encoder)
>  		if (WARN_ON(ddi_clk_needed))
>  			continue;
>  
> -		DRM_NOTE("Port %c is disabled/in DSI mode with an
> ungated DDI clock, gate it\n",
> -			 port_name(port));
> -		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> +		DRM_NOTE("PHY %c is disabled/in DSI mode with an
> ungated DDI clock, gate it\n",
> +			 phy_name(port));
> +		val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
>  		I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>  	}
>  }
> @@ -2863,6 +2870,7 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	u32 val;
>  	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>  
> @@ -2872,14 +2880,14 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
>  	mutex_lock(&dev_priv->dpll_lock);
>  
>  	if (INTEL_GEN(dev_priv) >= 11) {
> -		if (!intel_port_is_combophy(dev_priv, port))
> -			I915_WRITE(DDI_CLK_SEL(port),
> +		if (!intel_phy_is_combo(dev_priv, phy))
> +			I915_WRITE(DDI_CLK_SEL(phy),
>  				   icl_pll_to_ddi_clk_sel(encoder,
> crtc_state));
>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI.
> */
>  		val = I915_READ(DPCLKA_CFGCR0);
> -		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> -		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> +		val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> +		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
>  		I915_WRITE(DPCLKA_CFGCR0, val);
>  
>  		/*
> @@ -2888,21 +2896,21 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
>  		 * register writes.
>  		 */
>  		val = I915_READ(DPCLKA_CFGCR0);
> -		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> +		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>  		I915_WRITE(DPCLKA_CFGCR0, val);
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		/* DDI -> PLL mapping  */
>  		val = I915_READ(DPLL_CTRL2);
>  
> -		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
> -			 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
> -		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
> -			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
> +		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(phy) |
> +			 DPLL_CTRL2_DDI_CLK_SEL_MASK(phy));
> +		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, phy) |
> +			DPLL_CTRL2_DDI_SEL_OVERRIDE(phy));
>  
>  		I915_WRITE(DPLL_CTRL2, val);
>  
>  	} else if (INTEL_GEN(dev_priv) < 9) {
> -		I915_WRITE(PORT_CLK_SEL(port),
> hsw_pll_to_ddi_pll_sel(pll));
> +		I915_WRITE(PORT_CLK_SEL(phy),
> hsw_pll_to_ddi_pll_sel(pll));
>  	}
>  
>  	mutex_unlock(&dev_priv->dpll_lock);
> @@ -2912,18 +2920,19 @@ static void intel_ddi_clk_disable(struct
> intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  
>  	if (INTEL_GEN(dev_priv) >= 11) {
> -		if (!intel_port_is_combophy(dev_priv, port))
> -			I915_WRITE(DDI_CLK_SEL(port),
> DDI_CLK_SEL_NONE);
> +		if (!intel_phy_is_combo(dev_priv, phy))
> +			I915_WRITE(DDI_CLK_SEL(phy), DDI_CLK_SEL_NONE);


DDI_CLK_SEL() sets the clock to DDI so it should be port.

Same for the registers bellow


>  	} else if (IS_CANNONLAKE(dev_priv)) {
>  		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> -			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> +			   DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
>  	} else if (IS_GEN9_BC(dev_priv)) {
>  		I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
> -			   DPLL_CTRL2_DDI_CLK_OFF(port));
> +			   DPLL_CTRL2_DDI_CLK_OFF(phy));
>  	} else if (INTEL_GEN(dev_priv) < 9) {
> -		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
> +		I915_WRITE(PORT_CLK_SEL(phy), PORT_CLK_SEL_NONE);
>  	}
>  }
>  
> @@ -3110,6 +3119,7 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
>  	bool is_mst = intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_DP_MST);
>  	int level = intel_ddi_dp_level(intel_dp);
> @@ -3138,11 +3148,11 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
>  	else
>  		intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>  
> -	if (intel_port_is_combophy(dev_priv, port)) {
> +	if (intel_phy_is_combo(dev_priv, phy)) {
>  		bool lane_reversal =
>  			dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
>  
> -		intel_combo_phy_power_up_lanes(dev_priv, port, false,
> +		intel_combo_phy_power_up_lanes(dev_priv, phy, false,
>  					       crtc_state->lane_count,
>  					       lane_reversal);
>  	}
> @@ -3630,7 +3640,7 @@ intel_ddi_pre_pll_enable(struct intel_encoder
> *encoder,
>  	enum port port = encoder->port;
>  
>  	if (intel_crtc_has_dp_encoder(crtc_state) ||
> -	    intel_port_is_tc(dev_priv, encoder->port))
> +	    intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> port)))
>  		intel_display_power_get(dev_priv,
>  					intel_ddi_main_link_aux_domain(
> dig_port));
>  
> @@ -3656,9 +3666,10 @@ intel_ddi_post_pll_disable(struct
> intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  
>  	if (intel_crtc_has_dp_encoder(crtc_state) ||
> -	    intel_port_is_tc(dev_priv, encoder->port))
> +	    intel_phy_is_tc(dev_priv, phy))
>  		intel_display_power_put_unchecked(dev_priv,
>  						  intel_ddi_main_link_a
> ux_domain(dig_port));
>  }
> @@ -3934,8 +3945,9 @@ static void intel_ddi_encoder_reset(struct
> drm_encoder *drm_encoder)
>  {
>  	struct intel_digital_port *dig_port =
> enc_to_dig_port(drm_encoder);
>  	struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>  
> -	if (intel_port_is_tc(i915, dig_port->base.port))
> +	if (intel_phy_is_tc(i915, phy))
>  		intel_digital_port_connected(&dig_port->base);
>  
>  	intel_dp_encoder_reset(drm_encoder);
> @@ -3945,10 +3957,11 @@ static void intel_ddi_encoder_destroy(struct
> drm_encoder *encoder)
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct drm_i915_private *i915 = to_i915(encoder->dev);
> +	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>  
>  	intel_dp_encoder_flush_work(encoder);
>  
> -	if (intel_port_is_tc(i915, dig_port->base.port))
> +	if (intel_phy_is_tc(i915, phy))
>  		icl_tc_phy_disconnect(i915, dig_port);
>  
>  	drm_encoder_cleanup(encoder);
> @@ -4198,6 +4211,7 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
>  	struct drm_encoder *encoder;
>  	bool init_hdmi, init_dp, init_lspcon = false;
>  	enum pipe pipe;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  
>  	init_hdmi = port_info->supports_dvi || port_info-
> >supports_hdmi;
>  	init_dp = port_info->supports_dp;
> @@ -4261,7 +4275,7 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
>  	intel_dig_port->max_lanes =
> intel_ddi_max_lanes(intel_dig_port);
>  	intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv,
> port);
>  
> -	intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv,
> port) &&
> +	intel_dig_port->tc_legacy_port = intel_phy_is_tc(dev_priv, phy)
> &&
>  					 !port_info->supports_typec_usb 
> &&
>  					 !port_info->supports_tbt;
>  
> @@ -4324,7 +4338,7 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
>  
>  	intel_infoframe_init(intel_dig_port);
>  
> -	if (intel_port_is_tc(dev_priv, port))
> +	if (intel_phy_is_tc(dev_priv, phy))
>  		intel_digital_port_connected(intel_encoder);
>  
>  	return;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8592a7d422de..e72ace42327c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6560,31 +6560,39 @@ static void i9xx_pfit_enable(const struct
> intel_crtc_state *crtc_state)
>  	I915_WRITE(BCLRPAT(crtc->pipe), 0);
>  }
>  
> -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
> port port)
> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> phy)
>  {
> -	if (port == PORT_NONE)
> +	if (phy == PHY_NONE)
>  		return false;
>  
>  	if (IS_ELKHARTLAKE(dev_priv))
> -		return port <= PORT_C;
> +		return phy <= PHY_C;
>  
>  	if (INTEL_GEN(dev_priv) >= 11)
> -		return port <= PORT_B;
> +		return phy <= PHY_B;
>  
>  	return false;
>  }
>  
> -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port)
> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> phy)
>  {
>  	if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> -		return port >= PORT_C && port <= PORT_F;
> +		return phy >= PHY_C && phy <= PHY_F;
>  
>  	return false;
>  }
>  
> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port
> port)
> +{
> +	if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> +		return PHY_A;
> +
> +	return (enum phy)port;
> +}
> +
>  enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port)
>  {
> -	if (!intel_port_is_tc(dev_priv, port))
> +	if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> port)))
>  		return PORT_TC_NONE;
>  
>  	return port - PORT_C;
> @@ -9922,9 +9930,10 @@ static void cannonlake_get_ddi_pll(struct
> drm_i915_private *dev_priv,
>  {
>  	enum intel_dpll_id id;
>  	u32 temp;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  
> -	temp = I915_READ(DPCLKA_CFGCR0) &
> DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> -	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> +	temp = I915_READ(DPCLKA_CFGCR0) &
> DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> +	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);


Should be port, same for the icelake_get_ddi_pll()


>  
>  	if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
>  		return;
> @@ -9936,15 +9945,16 @@ static void icelake_get_ddi_pll(struct
> drm_i915_private *dev_priv,
>  				enum port port,
>  				struct intel_crtc_state *pipe_config)
>  {
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	enum intel_dpll_id id;
>  	u32 temp;
>  
>  	/* TODO: TBT pll not implemented. */
> -	if (intel_port_is_combophy(dev_priv, port)) {
> +	if (intel_phy_is_combo(dev_priv, phy)) {
>  		temp = I915_READ(DPCLKA_CFGCR0_ICL) &
> -		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> -		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> -	} else if (intel_port_is_tc(dev_priv, port)) {
> +		       DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> +		id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> +	} else if (intel_phy_is_tc(dev_priv, phy)) {
>  		id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
> port));
>  	} else {
>  		WARN(1, "Invalid port %x\n", port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index ee6b8194a459..f89b0b779f18 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -229,6 +229,21 @@ struct intel_link_m_n {
>  	u32 link_n;
>  };
>  
> +enum phy {
> +	PHY_NONE = -1,
> +
> +	PHY_A = 0,
> +	PHY_B,
> +	PHY_C,
> +	PHY_D,
> +	PHY_E,
> +	PHY_F,
> +
> +	I915_MAX_PHYS
> +};
> +
> +#define phy_name(a) ((a) + 'A')
> +
>  #define for_each_pipe(__dev_priv, __p) \
>  	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes;
> (__p)++)
>  
> @@ -357,5 +372,6 @@ void lpt_disable_clkout_dp(struct
> drm_i915_private *dev_priv);
>  u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
>  			      u32 pixel_format, u64 modifier);
>  bool intel_plane_can_remap(const struct intel_plane_state
> *plane_state);
> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port
> port);
>  
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4336df46fe78..577538132a80 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -329,9 +329,9 @@ static int icl_max_source_rate(struct intel_dp
> *intel_dp)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> -	enum port port = dig_port->base.port;
> +	enum phy phy = intel_port_to_phy(dev_priv, dig_port-
> >base.port);
>  
> -	if (intel_port_is_combophy(dev_priv, port) &&
> +	if (intel_phy_is_combo(dev_priv, phy) &&
>  	    !IS_ELKHARTLAKE(dev_priv) &&
>  	    !intel_dp_is_edp(intel_dp))
>  		return 540000;
> @@ -5425,10 +5425,11 @@ static bool icl_digital_port_connected(struct
> intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> +	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>  
> -	if (intel_port_is_combophy(dev_priv, encoder->port))
> +	if (intel_phy_is_combo(dev_priv, phy))
>  		return icl_combo_port_connected(dev_priv, dig_port);
> -	else if (intel_port_is_tc(dev_priv, encoder->port))
> +	else if (intel_phy_is_tc(dev_priv, phy))
>  		return icl_tc_port_connected(dev_priv, dig_port);
>  	else
>  		MISSING_CASE(encoder->hpd_pin);
> @@ -7332,6 +7333,7 @@ intel_dp_init_connector(struct
> intel_digital_port *intel_dig_port,
>  	struct drm_device *dev = intel_encoder->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	enum port port = intel_encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	int type;
>  
>  	/* Initialize the work for modeset in case of link train
> failure */
> @@ -7358,7 +7360,7 @@ intel_dp_init_connector(struct
> intel_digital_port *intel_dig_port,
>  		 * Currently we don't support eDP on TypeC ports,
> although in
>  		 * theory it could work on TypeC legacy ports.
>  		 */
> -		WARN_ON(intel_port_is_tc(dev_priv, port));
> +		WARN_ON(intel_phy_is_tc(dev_priv, phy));
>  		type = DRM_MODE_CONNECTOR_eDP;
>  	} else {
>  		type = DRM_MODE_CONNECTOR_DisplayPort;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 2d4e7b9a7b9d..7bf697848055 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2513,7 +2513,8 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
>  	struct skl_wrpll_params pll_params = { 0 };
>  	bool ret;
>  
> -	if (intel_port_is_tc(dev_priv, encoder->port))
> +	if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> +							encoder-
> >port)))
>  		ret = icl_calc_tbt_pll(crtc_state, &pll_params);
>  	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
>  		 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> @@ -2800,14 +2801,15 @@ icl_get_dpll(struct intel_crtc_state
> *crtc_state,
>  	struct intel_digital_port *intel_dig_port;
>  	struct intel_shared_dpll *pll;
>  	enum port port = encoder->port;
> +	enum phy phy = intel_port_to_phy(dev_priv, port);
>  	enum intel_dpll_id min, max;
>  	bool ret;
>  
> -	if (intel_port_is_combophy(dev_priv, port)) {
> +	if (intel_phy_is_combo(dev_priv, phy)) {
>  		min = DPLL_ID_ICL_DPLL0;
>  		max = DPLL_ID_ICL_DPLL1;
>  		ret = icl_calc_dpll_state(crtc_state, encoder);
> -	} else if (intel_port_is_tc(dev_priv, port)) {
> +	} else if (intel_phy_is_tc(dev_priv, phy)) {
>  		if (encoder->type == INTEL_OUTPUT_DP_MST) {
>  			struct intel_dp_mst_encoder *mst_encoder;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 7e748bb3f324..2a557895ec71 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,12 +1794,12 @@ enum i915_power_well_id {
>  #define _ICL_COMBOPHY_A			0x162000
>  #define _ICL_COMBOPHY_B			0x6C000
>  #define _ICL_COMBOPHY_C_EHL		0x160000
> -#define _ICL_COMBOPHY(port)		_PICK(port, _ICL_COMBOPHY_A, \
> +#define _ICL_COMBOPHY(phy)		_PICK(phy, _ICL_COMBOPHY_A, \
>  					      _ICL_COMBOPHY_B, \
>  					      _ICL_COMBOPHY_C_EHL)
>  
>  /* CNL/ICL Port CL_DW registers */
> -#define _ICL_PORT_CL_DW(dw, port)	(_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_CL_DW(dw, phy)	(_ICL_COMBOPHY(phy) + \
>  					 4 * (dw))
>  
>  #define CNL_PORT_CL1CM_DW5		_MMIO(0x162014)
> @@ -9681,15 +9681,15 @@ enum skl_power_gate {
>   */
>  #define DPCLKA_CFGCR0				_MMIO(0x6C200)
>  #define DPCLKA_CFGCR0_ICL			_MMIO(0x164280)
> -#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)
> ==  PORT_F ? 23 : \
> -						      (port) + 10))
> -#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port)   (1 << ((port) + 10))
> +#define  DPCLKA_CFGCR0_DDI_CLK_OFF(phy)		(1 << ((phy) ==
> PHY_F ? 23 : \
> +						      (phy) + 10))
> +#define  ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)	(1 << _PICK(phy, 10,
> 11, 25))
>  #define  ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
> PORT_TC4 ? \
>  						      21 : (tc_port) +
> 12))
> -#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) ==
> PORT_F ? 21 : \
> -						(port) * 2)
> -#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> -#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) == PHY_F
> ? 21 : \
> +						(phy) * 2)
> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(3 <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy)	((pll) <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>  
>  /* CNL PLL */
>  #define DPLL0_ENABLE		0x46010
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 1d58f7ec5d84..8c174bb767ba 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1473,8 +1473,8 @@ void intel_pps_unlock_regs_wa(struct
> drm_i915_private *dev_priv);
>  void intel_encoder_destroy(struct drm_encoder *encoder);
>  struct drm_display_mode *
>  intel_encoder_current_mode(struct intel_encoder *encoder);
> -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
> port port);
> -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port);
> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> phy);
> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> phy);
>  enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
>  			      enum port port);
>  int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void
> *data,

Other than those above looks good but as this is a big change would be
nice to have another set of eyes reviewing.

+ Imre Deak <imre.deak@intel.com>
This will conflict with this type-c/TBT patches and he worked in combo
phy changes recently.

+ Ville and Jani



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Re: [PATCH 4/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'

[Ville Syrjälä]

On Sat, Jun 22, 2019 at 12:24:10AM +0000, Souza, Jose wrote:
> On Fri, 2019-06-21 at 07:08 -0700, Matt Roper wrote:
> > @@ -2912,18 +2920,19 @@ static void intel_ddi_clk_disable(struct
> > intel_encoder *encoder)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> >  	enum port port = encoder->port;
> > +	enum phy phy = intel_port_to_phy(dev_priv, port);
> >  
> >  	if (INTEL_GEN(dev_priv) >= 11) {
> > -		if (!intel_port_is_combophy(dev_priv, port))
> > -			I915_WRITE(DDI_CLK_SEL(port),
> > DDI_CLK_SEL_NONE);
> > +		if (!intel_phy_is_combo(dev_priv, phy))
> > +			I915_WRITE(DDI_CLK_SEL(phy), DDI_CLK_SEL_NONE);
> 
> 
> DDI_CLK_SEL() sets the clock to DDI so it should be port.
> 
> Same for the registers bellow

I guess the rought guideline should be the register offset:

0x6Cxxx / 0x16xxxx -> phy
everything else -> port

or at least that's the impression I got from the quick read
of the spec.

-- 
Ville Syrjälä
Intel
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Re: [PATCH 4/5] drm/i915/gen11: Start distinguishing 'phy' from 'port'

[Matt Roper]

On Fri, Jun 21, 2019 at 05:24:10PM -0700, Souza, Jose wrote:
> On Fri, 2019-06-21 at 07:08 -0700, Matt Roper wrote:
> > Our past DDI-based Intel platforms have had a fixed DDI<->PHY
> > mapping.
> > Because of this, both the bspec documentation and our i915 code has
> > used
> > the term "port" when talking about either DDI's or PHY's; it was
> > always
> > easy to tell what terms like "Port A" were referring to from the
> > context.
> > 
> > Unfortunately this is starting to break down now that EHL allows PHY-
> > A
> > to be driven by either DDI-A or DDI-D.  Is a setup with DDI-D driving
> > PHY-A considered "Port A" or "Port D?"  The answer depends on which
> > register we're working with, and even the bspec doesn't do a great
> > job
> > of clarifying this.
> > 
> > Let's try to be more explicit about whether we're talking about the
> > DDI
> > or the PHY on gen11+ by using 'port' to refer to the DDI and creating
> > a
> > new 'enum phy' namespace to refer to the PHY in use.
> > 
> > A few general notes:
> > 
> >  - ICL_PORT_COMP_* and ICL_PORT_CL_* belong to the actual combo PHY
> > so
> >    they should always be programmed according to the PHY in use,
> >    regardless of which DDI is driving it.
> > 
> >  - The pipe part of the hardware expects "port" to refer to the
> >    DDI, so registers like TRANS_CLK_SEL and TRANS_DDI_FUNC_CTL should
> >    set bits according to the desired DDI (e.g., DDI-D) rather than
> > the
> >    PHY (PHY-A).
> > 
> >  - Non-pipe registers refer to the PHY.  Notably, DPCLKA_CFGCR0_ICL
> >    needs to set bits according to the PHY.
> > 
> > Most of the changes here are on the combo PHY side.  I didn't touch
> > most
> > of the TC port code yet, so it still refers to everything as ports.
> > That's okay for now since there's no TC on EHL, but we'll probably
> > want
> > to separate out the DDI vs PHY terminology for TC in the future as
> > well
> > to avoid confusion.
> > 
> > v2:
> >  - Convert a few more 'port' uses to 'phy.' (Sparse)
> > 
> > Suggested-by: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
...
> > @@ -9922,9 +9930,10 @@ static void cannonlake_get_ddi_pll(struct
> > drm_i915_private *dev_priv,
> >  {
> >  	enum intel_dpll_id id;
> >  	u32 temp;
> > +	enum phy phy = intel_port_to_phy(dev_priv, port);
> >  
> > -	temp = I915_READ(DPCLKA_CFGCR0) &
> > DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> > -	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> > +	temp = I915_READ(DPCLKA_CFGCR0) &
> > DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> > +	id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> 
> 
> Should be port, same for the icelake_get_ddi_pll()

I agree with your other corrections, but I think the
icelake_get_ddi_pll() one needs to stay with PHY.  Bspec page 33148
indicates

        "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA Clock
        Select chooses the PLL for both DDIA and DDID and drives port A
        in all cases."

DPCLKA_CFGCR0_ICL doesn't have any clock select bits that correspond to
a "port D" (according to bspec page 15726) so I believe passing the PHY
to DPCLKA_CFGCR0_DDI_CLK_SEL is the right thing to do.  I should
probably add a comment clarifying this in the code.

For the cannonlake function I just used phy for consistency with the ICL
code (port=phy in all cases for CNL), but that's probably just adding
confusion so I'll switch it back to port in that one.


Matt

-- 
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IoTG Platform Enabling & Development
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(916) 356-2795
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[PATCH 5/5] drm/i915/ehl: Enable DDI-D

[Matt Roper]

EHL has four DDI's (DDI-A and DDI-D share combo PHY A).

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e72ace42327c..74cd180360f4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15128,6 +15128,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_B);
 		intel_ddi_init(dev_priv, PORT_C);
+		intel_ddi_init(dev_priv, PORT_D);
 		icl_dsi_init(dev_priv);
 	} else if (INTEL_GEN(dev_priv) >= 11) {
 		intel_ddi_init(dev_priv, PORT_A);
-- 
2.17.2

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Re: [PATCH 5/5] drm/i915/ehl: Enable DDI-D

[Souza, Jose]

On Thu, 2019-06-20 at 19:01 -0700, Matt Roper wrote:
> EHL has four DDI's (DDI-A and DDI-D share combo PHY A).
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e72ace42327c..74cd180360f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15128,6 +15128,7 @@ static void intel_setup_outputs(struct
> drm_i915_private *dev_priv)
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_B);
>  		intel_ddi_init(dev_priv, PORT_C);
> +		intel_ddi_init(dev_priv, PORT_D);

Here we should only initialize only the one that is going to be used A
or D at this point we already have that information and the mux set.

>  		icl_dsi_init(dev_priv);
>  	} else if (INTEL_GEN(dev_priv) >= 11) {
>  		intel_ddi_init(dev_priv, PORT_A);
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Re: [PATCH 5/5] drm/i915/ehl: Enable DDI-D

[Matt Roper]

On Fri, Jun 21, 2019 at 01:52:16PM -0700, Souza, Jose wrote:
> On Thu, 2019-06-20 at 19:01 -0700, Matt Roper wrote:
> > EHL has four DDI's (DDI-A and DDI-D share combo PHY A).
> > 
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index e72ace42327c..74cd180360f4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15128,6 +15128,7 @@ static void intel_setup_outputs(struct
> > drm_i915_private *dev_priv)
> >  		intel_ddi_init(dev_priv, PORT_A);
> >  		intel_ddi_init(dev_priv, PORT_B);
> >  		intel_ddi_init(dev_priv, PORT_C);
> > +		intel_ddi_init(dev_priv, PORT_D);
> 
> Here we should only initialize only the one that is going to be used A
> or D at this point we already have that information and the mux set.

Doesn't intel_ddi_init() already take care of this for us?  I.e.,
init_hdmi and init_dp will both be false for whichever DDI isn't in use
so the function should just bail out with a DRM_DEBUG_KMS() message and
not really do anything if I'm understanding correctly.


Matt

> 
> >  		icl_dsi_init(dev_priv);
> >  	} else if (INTEL_GEN(dev_priv) >= 11) {
> >  		intel_ddi_init(dev_priv, PORT_A);

-- 
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IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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Re: [PATCH 5/5] drm/i915/ehl: Enable DDI-D

[Souza, Jose]

On Tue, 2019-06-25 at 15:19 -0700, Matt Roper wrote:
> On Fri, Jun 21, 2019 at 01:52:16PM -0700, Souza, Jose wrote:
> > On Thu, 2019-06-20 at 19:01 -0700, Matt Roper wrote:
> > > EHL has four DDI's (DDI-A and DDI-D share combo PHY A).
> > > 
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index e72ace42327c..74cd180360f4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -15128,6 +15128,7 @@ static void intel_setup_outputs(struct
> > > drm_i915_private *dev_priv)
> > >  		intel_ddi_init(dev_priv, PORT_A);
> > >  		intel_ddi_init(dev_priv, PORT_B);
> > >  		intel_ddi_init(dev_priv, PORT_C);
> > > +		intel_ddi_init(dev_priv, PORT_D);
> > 
> > Here we should only initialize only the one that is going to be
> > used A
> > or D at this point we already have that information and the mux
> > set.
> 
> Doesn't intel_ddi_init() already take care of this for us?  I.e.,
> init_hdmi and init_dp will both be false for whichever DDI isn't in
> use
> so the function should just bail out with a DRM_DEBUG_KMS() message
> and
> not really do anything if I'm understanding correctly.

Good point, lets hope that VBT is set this clean.

> 
> 
> Matt
> 
> > >  		icl_dsi_init(dev_priv);
> > >  	} else if (INTEL_GEN(dev_priv) >= 11) {
> > >  		intel_ddi_init(dev_priv, PORT_A);
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✗ Fi.CI.CHECKPATCH: warning for EHL port programming

[Patchwork]

== Series Details ==

Series: EHL port programming
URL   : https://patchwork.freedesktop.org/series/62492/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e8826f32a876 drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10: 
References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")

-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")'
#10: 
References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")

total: 1 errors, 1 warnings, 0 checks, 36 lines checked
518c8457a26b drm/i915/ehl: Add third combo PHY offset
1b989ddfe119 drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
10865d66217d drm/i915/gen11: Start distinguishing 'phy' from 'port'
-:148: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#148: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:9:
+#define for_each_combo_phy(__dev_priv, __phy) \
+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))

-:155: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#155: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:13:
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))

-:881: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#881: FILE: drivers/gpu/drm/i915/i915_reg.h:9684:
+#define  DPCLKA_CFGCR0_DDI_CLK_OFF(phy)		(1 << ((phy) == PHY_F ? 23 : \
+						      (phy) + 10))

-:890: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#890: FILE: drivers/gpu/drm/i915/i915_reg.h:9689:
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) == PHY_F ? 21 : \
+						(phy) * 2)

total: 0 errors, 0 warnings, 4 checks, 769 lines checked
8d9e8e6a8ceb drm/i915/ehl: Enable DDI-D

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✗ Fi.CI.SPARSE: warning for EHL port programming

[Patchwork]

== Series Details ==

Series: EHL port programming
URL   : https://patchwork.freedesktop.org/series/62492/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()
Okay!

Commit: drm/i915/ehl: Add third combo PHY offset
Okay!

Commit: drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
Okay!

Commit: drm/i915/gen11: Start distinguishing 'phy' from 'port'
+drivers/gpu/drm/i915/display/icl_dsi.c:370:58:     int enum phy 
+drivers/gpu/drm/i915/display/icl_dsi.c:370:58:     int enum port  versus
+drivers/gpu/drm/i915/display/icl_dsi.c:370:58: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_combo_phy.c:199:46:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_combo_phy.c:199:46:     int enum port 
+drivers/gpu/drm/i915/display/intel_combo_phy.c:199:46: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_combo_phy.c:202:55:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_combo_phy.c:202:55:     int enum port 
+drivers/gpu/drm/i915/display/intel_combo_phy.c:202:55: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_combo_phy.c:205:48:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_combo_phy.c:205:48:     int enum port 
+drivers/gpu/drm/i915/display/intel_combo_phy.c:205:48: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_combo_phy.c:208:40:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_combo_phy.c:208:40:     int enum port 
+drivers/gpu/drm/i915/display/intel_combo_phy.c:208:40: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_combo_phy.c:327:54:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_combo_phy.c:327:54:     int enum port 
+drivers/gpu/drm/i915/display/intel_combo_phy.c:327:54: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum phy  versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum port 
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum port 
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum port 
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum port 
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67:     int enum port 
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2740:67: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2846:68:     int enum phy 
+drivers/gpu/drm/i915/display/intel_ddi.c:2846:68:     int enum port  versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2846:68: warning: mixing different enum types
+drivers/gpu/drm/i915/display/intel_ddi.c:2860:60:     int enum phy 
+drivers/gpu/drm/i915/display/intel_ddi.c:2860:60:     int enum port  versus
+drivers/gpu/drm/i915/display/intel_ddi.c:2860:60: warning: mixing different enum types

Commit: drm/i915/ehl: Enable DDI-D
Okay!

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✓ Fi.CI.BAT: success for EHL port programming

[Patchwork]

== Series Details ==

Series: EHL port programming
URL   : https://patchwork.freedesktop.org/series/62492/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6319 -> Patchwork_13379
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/

Known issues
------------

  Here are the changes found in Patchwork_13379 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_switch@basic-default:
    - fi-icl-guc:         [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#108569])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-icl-guc/igt@gem_ctx_switch@basic-default.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-icl-guc/igt@gem_ctx_switch@basic-default.html

  * igt@gem_mmap_gtt@basic-write-no-prefault:
    - fi-icl-u3:          [PASS][3] -> [DMESG-WARN][4] ([fdo#107724])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-icl-u3/igt@gem_mmap_gtt@basic-write-no-prefault.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-icl-u3/igt@gem_mmap_gtt@basic-write-no-prefault.html

  * igt@i915_module_load@reload-with-fault-injection:
    - fi-icl-dsi:         [PASS][5] -> [INCOMPLETE][6] ([fdo#107713])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-icl-dsi/igt@i915_module_load@reload-with-fault-injection.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-icl-dsi/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-skl-6600u:       [PASS][7] -> [FAIL][8] ([fdo#107707])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-skl-6600u/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_selftest@live_blt:
    - fi-skl-iommu:       [PASS][9] -> [INCOMPLETE][10] ([fdo#108602])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-skl-iommu/igt@i915_selftest@live_blt.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-skl-iommu/igt@i915_selftest@live_blt.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][11] -> [FAIL][12] ([fdo#109485])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_execlists:
    - fi-cfl-8109u:       [INCOMPLETE][13] -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-cfl-8109u/igt@i915_selftest@live_execlists.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-cfl-8109u/igt@i915_selftest@live_execlists.html

  * igt@kms_addfb_basic@addfb25-x-tiled:
    - fi-icl-u3:          [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-icl-u3/igt@kms_addfb_basic@addfb25-x-tiled.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-icl-u3/igt@kms_addfb_basic@addfb25-x-tiled.html

  * igt@kms_busy@basic-flip-b:
    - fi-icl-dsi:         [DMESG-WARN][17] ([fdo#106107]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-icl-dsi/igt@kms_busy@basic-flip-b.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-icl-dsi/igt@kms_busy@basic-flip-b.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [DMESG-WARN][19] ([fdo#102614]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
    - fi-icl-u2:          [FAIL][21] ([fdo#103167]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-blb-e6850:       [INCOMPLETE][23] ([fdo#107718]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#107707]: https://bugs.freedesktop.org/show_bug.cgi?id=107707
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485


Participating hosts (51 -> 44)
------------------------------

  Additional (1): fi-bxt-j4205 
  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6319 -> Patchwork_13379

  CI_DRM_6319: 6f4aab2bf0b6001dd7d66f14b7014996ad2d06e4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13379: 8d9e8e6a8ceb6c86097a4a3715cbf616a3bd471b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8d9e8e6a8ceb drm/i915/ehl: Enable DDI-D
10865d66217d drm/i915/gen11: Start distinguishing 'phy' from 'port'
1b989ddfe119 drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
518c8457a26b drm/i915/ehl: Add third combo PHY offset
e8826f32a876 drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for EHL port programming

[Patchwork]

== Series Details ==

Series: EHL port programming
URL   : https://patchwork.freedesktop.org/series/62492/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6319_full -> Patchwork_13379_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13379_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@execbuf:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#110913 ]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-apl3/igt@gem_eio@execbuf.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-apl5/igt@gem_eio@execbuf.html

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          [PASS][3] -> [FAIL][4] ([fdo#109661])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-snb4/igt@gem_eio@unwedge-stress.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-snb1/igt@gem_eio@unwedge-stress.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-snb:          [PASS][5] -> [DMESG-WARN][6] ([fdo#110789] / [fdo#110913 ])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-snb7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-snb2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-kbl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#110913 ]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-kbl7/igt@gem_persistent_relocs@forked-thrashing.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-kbl2/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +4 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-apl2/igt@gem_softpin@noreloc-s3.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-apl7/igt@gem_softpin@noreloc-s3.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-skl:          [PASS][11] -> [INCOMPLETE][12] ([fdo#104108])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-skl3/igt@kms_fbcon_fbt@psr-suspend.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-skl2/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-snb:          [PASS][13] -> [INCOMPLETE][14] ([fdo#105411])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-glk:          [PASS][15] -> [FAIL][16] ([fdo#100368])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-glk6/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-glk8/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite:
    - shard-hsw:          [PASS][17] -> [SKIP][18] ([fdo#109271]) +19 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-hsw8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [PASS][19] -> [FAIL][20] ([fdo#103167]) +7 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-skl:          [PASS][21] -> [INCOMPLETE][22] ([fdo#104108] / [fdo#106978])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-skl10/igt@kms_frontbuffer_tracking@psr-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-skl3/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_plane_lowres@pipe-a-tiling-y:
    - shard-iclb:         [PASS][23] -> [FAIL][24] ([fdo#103166])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-y.html

  * igt@kms_psr@psr2_sprite_plane_onoff:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109441])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-iclb8/igt@kms_psr@psr2_sprite_plane_onoff.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [PASS][27] -> [FAIL][28] ([fdo#99912])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-kbl1/igt@kms_setmode@basic.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-kbl7/igt@kms_setmode@basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-hsw:          [PASS][29] -> [FAIL][30] ([fdo#100047])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-hsw8/igt@kms_sysfs_edid_timing.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-hsw1/igt@kms_sysfs_edid_timing.html

  
#### Possible fixes ####

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-apl:          [DMESG-WARN][31] ([fdo#110913 ]) -> [PASS][32] +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-apl2/igt@gem_persistent_relocs@forked-thrashing.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-apl7/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-snb:          [DMESG-WARN][33] ([fdo#110913 ]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-kbl:          [DMESG-WARN][35] ([fdo#110913 ]) -> [PASS][36] +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-kbl6/igt@gem_userptr_blits@sync-unmap-cycles.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-kbl6/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-kbl:          [DMESG-WARN][37] ([fdo#103313]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-kbl2/igt@i915_suspend@fence-restore-untiled.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
    - shard-hsw:          [SKIP][39] ([fdo#109271]) -> [PASS][40] +25 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-hsw5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [FAIL][41] ([fdo#103167]) -> [PASS][42] +7 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [SKIP][43] ([fdo#109441]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb6/igt@kms_psr@psr2_sprite_blt.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-kbl:          [FAIL][45] ([fdo#109016]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-kbl3/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-kbl2/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [FAIL][47] ([fdo#99912]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-hsw1/igt@kms_setmode@basic.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-hsw1/igt@kms_setmode@basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         [FAIL][49] ([fdo#100047]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-iclb2/igt@kms_sysfs_edid_timing.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-iclb4/igt@kms_sysfs_edid_timing.html

  * igt@perf_pmu@rc6:
    - shard-kbl:          [SKIP][51] ([fdo#109271]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-kbl2/igt@perf_pmu@rc6.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-kbl3/igt@perf_pmu@rc6.html

  * igt@prime_busy@hang-bsd:
    - shard-glk:          [INCOMPLETE][53] ([fdo#103359] / [k.org#198133]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6319/shard-glk6/igt@prime_busy@hang-bsd.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/shard-glk8/igt@prime_busy@hang-bsd.html

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109016]: https://bugs.freedesktop.org/show_bug.cgi?id=109016
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913 
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6319 -> Patchwork_13379

  CI_DRM_6319: 6f4aab2bf0b6001dd7d66f14b7014996ad2d06e4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13379: 8d9e8e6a8ceb6c86097a4a3715cbf616a3bd471b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13379/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for EHL port programming (rev2)

[Patchwork]

== Series Details ==

Series: EHL port programming (rev2)
URL   : https://patchwork.freedesktop.org/series/62492/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5685d98b6706 drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#10: 
References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")

-:10: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")'
#10: 
References: 9659c1af451a ("drm/i915/icl: combo port vswing programming changes per BSPEC")

total: 1 errors, 1 warnings, 0 checks, 36 lines checked
a396b4e39927 drm/i915/ehl: Add third combo PHY offset
83b87151a761 drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
be24fefad142 drm/i915/gen11: Start distinguishing 'phy' from 'port'
-:167: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#167: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:9:
+#define for_each_combo_phy(__dev_priv, __phy) \
+	for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++)	\
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))

-:174: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__phy' - possible side-effects?
#174: FILE: drivers/gpu/drm/i915/display/intel_combo_phy.c:13:
+#define for_each_combo_phy_reverse(__dev_priv, __phy) \
+	for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
+		for_each_if(intel_phy_is_combo(__dev_priv, __phy))

-:1048: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#1048: FILE: drivers/gpu/drm/i915/i915_reg.h:9684:
+#define  DPCLKA_CFGCR0_DDI_CLK_OFF(phy)		(1 << ((phy) == PHY_F ? 23 : \
+						      (phy) + 10))

-:1057: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'phy' - possible side-effects?
#1057: FILE: drivers/gpu/drm/i915/i915_reg.h:9689:
+#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	((phy) == PHY_F ? 21 : \
+						(phy) * 2)

total: 0 errors, 0 warnings, 4 checks, 926 lines checked
4b99477f1916 drm/i915/ehl: Enable DDI-D

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for EHL port programming (rev2)

[Patchwork]

== Series Details ==

Series: EHL port programming (rev2)
URL   : https://patchwork.freedesktop.org/series/62492/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6323 -> Patchwork_13387
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/

Known issues
------------

  Here are the changes found in Patchwork_13387 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-skl-6600u:       [PASS][1] -> [FAIL][2] ([fdo#108800])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-skl-6600u/igt@i915_pm_rpm@basic-rte.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/fi-skl-6600u/igt@i915_pm_rpm@basic-rte.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [PASS][3] -> [FAIL][4] ([fdo#103167])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800


Participating hosts (50 -> 43)
------------------------------

  Additional (3): fi-icl-guc fi-icl-dsi fi-apl-guc 
  Missing    (10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ivb-3770 fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6323 -> Patchwork_13387

  CI_DRM_6323: b440a8f975a5d9ea7807517e4228077bc795e91e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13387: 4b99477f19165b4d454bf8fc2aeb112447dceb95 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4b99477f1916 drm/i915/ehl: Enable DDI-D
be24fefad142 drm/i915/gen11: Start distinguishing 'phy' from 'port'
83b87151a761 drm/i915/ehl: Don't program PHY_MISC on EHL PHY C
a396b4e39927 drm/i915/ehl: Add third combo PHY offset
5685d98b6706 drm/i915/icl: Drop port parameter to icl_get_combo_buf_trans()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/
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✗ Fi.CI.IGT: failure for EHL port programming (rev2)

[Patchwork]

== Series Details ==

Series: EHL port programming (rev2)
URL   : https://patchwork.freedesktop.org/series/62492/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_6323_full -> Patchwork_13387_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_13387_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_13387_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_13387_full:

### IGT changes ###

#### Possible regressions ####

  * igt@perf_pmu@busy-double-start-vecs0:
    - shard-skl:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-skl7/igt@perf_pmu@busy-double-start-vecs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-skl4/igt@perf_pmu@busy-double-start-vecs0.html

  
Known issues
------------

  Here are the changes found in Patchwork_13387_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-suspend:
    - shard-kbl:          [PASS][3] -> [FAIL][4] ([fdo#110667])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-kbl6/igt@gem_eio@in-flight-suspend.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-kbl6/igt@gem_eio@in-flight-suspend.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6] ([fdo#110913 ])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-kbl2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#110913 ]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-apl8/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-apl7/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][9] -> [DMESG-WARN][10] ([fdo#108566])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-snb:          [PASS][11] -> [INCOMPLETE][12] ([fdo#105411])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite:
    - shard-hsw:          [PASS][13] -> [SKIP][14] ([fdo#109271]) +15 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-hsw8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-badstride:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([fdo#103167]) +5 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-badstride.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-badstride.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-iclb1/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_sysfs_edid_timing:
    - shard-hsw:          [PASS][19] -> [FAIL][20] ([fdo#100047])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-hsw8/igt@kms_sysfs_edid_timing.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-hsw1/igt@kms_sysfs_edid_timing.html

  
#### Possible fixes ####

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          [FAIL][21] ([fdo#109661]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-snb5/igt@gem_eio@unwedge-stress.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-snb1/igt@gem_eio@unwedge-stress.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
    - shard-apl:          [DMESG-WARN][23] ([fdo#110913 ]) -> [PASS][24] +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-apl3/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-apl4/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [DMESG-WARN][25] ([fdo#108686]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-apl2/igt@gem_tiled_swapping@non-threaded.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-apl1/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-kbl:          [DMESG-WARN][27] ([fdo#110913 ]) -> [PASS][28] +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-kbl2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-kbl6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [DMESG-WARN][29] ([fdo#110913 ]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-snb2/igt@gem_userptr_blits@sync-unmap-cycles.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-snb4/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +2 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-apl1/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-skl:          [INCOMPLETE][33] ([fdo#104108]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-skl2/igt@kms_fbcon_fbt@fbc-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-skl10/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite:
    - shard-hsw:          [SKIP][35] ([fdo#109271]) -> [PASS][36] +15 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-hsw4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
    - shard-iclb:         [FAIL][37] ([fdo#103167]) -> [PASS][38] +7 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [FAIL][39] ([fdo#108145]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_dpms:
    - shard-iclb:         [SKIP][41] ([fdo#109441]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-iclb7/igt@kms_psr@psr2_dpms.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-iclb2/igt@kms_psr@psr2_dpms.html

  * igt@perf_pmu@rc6:
    - shard-kbl:          [SKIP][43] ([fdo#109271]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-kbl2/igt@perf_pmu@rc6.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-kbl4/igt@perf_pmu@rc6.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
    - shard-hsw:          [INCOMPLETE][45] ([fdo#103540]) -> [SKIP][46] ([fdo#109271])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6323/shard-hsw8/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/shard-hsw1/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
  [fdo#110667]: https://bugs.freedesktop.org/show_bug.cgi?id=110667
  [fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913 


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6323 -> Patchwork_13387

  CI_DRM_6323: b440a8f975a5d9ea7807517e4228077bc795e91e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5064: 22850c1906550fb97b405c019275dcfb34be8cf7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13387: 4b99477f19165b4d454bf8fc2aeb112447dceb95 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13387/
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