[PATCH 0/4] dt-bindings: display/msm: schema fixes for gpu, gmu and mdp4

[PATCH 0/4] dt-bindings: display/msm: schema fixes for gpu, gmu and mdp4

[Dmitry Baryshkov]

Fix several issues in MSM display schema.

Dmitry Baryshkov (4):
  dt-bindings: display/msm/gpu: allow specifying several IOMMU nodes
  dt-bindings: display/msm/gpu: document using the amd,imageon adreno
    too
  dt-bindings: display/msm/gmu: account for different GMU variants
  dt-bindings: display/msm/mdp4: require 4 IOMMUs

 .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
 .../devicetree/bindings/display/msm/gpu.yaml  |   9 +-
 .../devicetree/bindings/display/msm/mdp4.yaml |   2 +-
 3 files changed, 155 insertions(+), 22 deletions(-)

-- 
2.35.1

[PATCH 0/4] dt-bindings: display/msm: schema fixes for gpu, gmu and mdp4

[Dmitry Baryshkov]

Fix several issues in MSM display schema.

Dmitry Baryshkov (4):
  dt-bindings: display/msm/gpu: allow specifying several IOMMU nodes
  dt-bindings: display/msm/gpu: document using the amd,imageon adreno
    too
  dt-bindings: display/msm/gmu: account for different GMU variants
  dt-bindings: display/msm/mdp4: require 4 IOMMUs

 .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
 .../devicetree/bindings/display/msm/gpu.yaml  |   9 +-
 .../devicetree/bindings/display/msm/mdp4.yaml |   2 +-
 3 files changed, 155 insertions(+), 22 deletions(-)

-- 
2.35.1

[PATCH 1/4] dt-bindings: display/msm/gpu: allow specifying several IOMMU nodes

[Dmitry Baryshkov]

Different platforms require different amounts of IOMMUs. The APQ8064
uses 64 IOMMU instances for GPU, adjust the schema accordingly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/gpu.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 3397bc31d087..346aabdccf7b 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -58,7 +58,8 @@ properties:
       - const: ocmem
 
   iommus:
-    maxItems: 1
+    minItems: 1
+    maxItems: 64
 
   sram:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-- 
2.35.1

[PATCH 1/4] dt-bindings: display/msm/gpu: allow specifying several IOMMU nodes

[Dmitry Baryshkov]

Different platforms require different amounts of IOMMUs. The APQ8064
uses 64 IOMMU instances for GPU, adjust the schema accordingly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/gpu.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 3397bc31d087..346aabdccf7b 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -58,7 +58,8 @@ properties:
       - const: ocmem
 
   iommus:
-    maxItems: 1
+    minItems: 1
+    maxItems: 64
 
   sram:
     $ref: /schemas/types.yaml#/definitions/phandle-array
-- 
2.35.1

Re: [PATCH 1/4] dt-bindings: display/msm/gpu: allow specifying several IOMMU nodes

[Krzysztof Kozlowski]

On 06/07/2022 16:52, Dmitry Baryshkov wrote:
> Different platforms require different amounts of IOMMUs. The APQ8064
> uses 64 IOMMU instances for GPU, adjust the schema accordingly.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: display/msm/gpu: allow specifying several IOMMU nodes

[Krzysztof Kozlowski]

On 06/07/2022 16:52, Dmitry Baryshkov wrote:
> Different platforms require different amounts of IOMMUs. The APQ8064
> uses 64 IOMMU instances for GPU, adjust the schema accordingly.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

[PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too

[Dmitry Baryshkov]

The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
have been using amd,imageon with newer (Adreno) GPUs to describe the
headless setup, when the platform does not (yet) have the display DT
nodes (and no display support). Document this trick in the schema.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 346aabdccf7b..e006da95462c 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -16,9 +16,13 @@ properties:
       - description: |
           The driver is parsing the compat string for Adreno to
           figure out the gpu-id and patch level.
+          Optional amd,imageon compatibility string enables using Adreno
+          without the display node.
         items:
           - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
           - const: qcom,adreno
+          - const: amd,imageon
+        minItems: 2
       - description: |
           The driver is parsing the compat string for Imageon to
           figure out the gpu-id and patch level.
@@ -148,6 +152,8 @@ allOf:
                 description: GPU 3D engine clock
               - const: rbbmtimer
                 description: GPU RBBM Timer for Adreno 5xx series
+              - const: rbcpr
+                description: GPU RB CPR clock
           minItems: 2
           maxItems: 7
 
-- 
2.35.1

[PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd, imageon adreno too

[Dmitry Baryshkov]

The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
have been using amd,imageon with newer (Adreno) GPUs to describe the
headless setup, when the platform does not (yet) have the display DT
nodes (and no display support). Document this trick in the schema.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 346aabdccf7b..e006da95462c 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -16,9 +16,13 @@ properties:
       - description: |
           The driver is parsing the compat string for Adreno to
           figure out the gpu-id and patch level.
+          Optional amd,imageon compatibility string enables using Adreno
+          without the display node.
         items:
           - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
           - const: qcom,adreno
+          - const: amd,imageon
+        minItems: 2
       - description: |
           The driver is parsing the compat string for Imageon to
           figure out the gpu-id and patch level.
@@ -148,6 +152,8 @@ allOf:
                 description: GPU 3D engine clock
               - const: rbbmtimer
                 description: GPU RBBM Timer for Adreno 5xx series
+              - const: rbcpr
+                description: GPU RB CPR clock
           minItems: 2
           maxItems: 7
 
-- 
2.35.1

Re: [PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too

[Krzysztof Kozlowski]

On 06/07/2022 16:52, Dmitry Baryshkov wrote:
> The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
> have been using amd,imageon with newer (Adreno) GPUs to describe the
> headless setup, when the platform does not (yet) have the display DT

Does not have "yet"? So later it will have and you drop a compatible?

> nodes (and no display support). Document this trick in the schema.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> index 346aabdccf7b..e006da95462c 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> @@ -16,9 +16,13 @@ properties:
>        - description: |
>            The driver is parsing the compat string for Adreno to
>            figure out the gpu-id and patch level.
> +          Optional amd,imageon compatibility string enables using Adreno
> +          without the display node.
>          items:
>            - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
>            - const: qcom,adreno
> +          - const: amd,imageon
> +        minItems: 2

This is too unspecific. You allow any device to be and not to be
compatible with amd,imageon.

>        - description: |
>            The driver is parsing the compat string for Imageon to
>            figure out the gpu-id and patch level.
> @@ -148,6 +152,8 @@ allOf:
>                  description: GPU 3D engine clock
>                - const: rbbmtimer
>                  description: GPU RBBM Timer for Adreno 5xx series
> +              - const: rbcpr
> +                description: GPU RB CPR clock
>            minItems: 2
>            maxItems: 7

Do 8 items work with maxItems:7?


Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too

[Krzysztof Kozlowski]

On 06/07/2022 16:52, Dmitry Baryshkov wrote:
> The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
> have been using amd,imageon with newer (Adreno) GPUs to describe the
> headless setup, when the platform does not (yet) have the display DT

Does not have "yet"? So later it will have and you drop a compatible?

> nodes (and no display support). Document this trick in the schema.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> index 346aabdccf7b..e006da95462c 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> @@ -16,9 +16,13 @@ properties:
>        - description: |
>            The driver is parsing the compat string for Adreno to
>            figure out the gpu-id and patch level.
> +          Optional amd,imageon compatibility string enables using Adreno
> +          without the display node.
>          items:
>            - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
>            - const: qcom,adreno
> +          - const: amd,imageon
> +        minItems: 2

This is too unspecific. You allow any device to be and not to be
compatible with amd,imageon.

>        - description: |
>            The driver is parsing the compat string for Imageon to
>            figure out the gpu-id and patch level.
> @@ -148,6 +152,8 @@ allOf:
>                  description: GPU 3D engine clock
>                - const: rbbmtimer
>                  description: GPU RBBM Timer for Adreno 5xx series
> +              - const: rbcpr
> +                description: GPU RB CPR clock
>            minItems: 2
>            maxItems: 7

Do 8 items work with maxItems:7?


Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too

[Dmitry Baryshkov]

On 06/07/2022 18:50, Krzysztof Kozlowski wrote:
> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>> The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
>> have been using amd,imageon with newer (Adreno) GPUs to describe the
>> headless setup, when the platform does not (yet) have the display DT
> 
> Does not have "yet"? So later it will have and you drop a compatible?

Yes. For example see the arch/arm64/boot/dts/qcom/8150.dtsi, which 
currently has only GPU node. Once we add MDSS/DPU/DSI/etc. nodes, we are 
going to drop the compat string.

> 
>> nodes (and no display support). Document this trick in the schema.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> index 346aabdccf7b..e006da95462c 100644
>> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> @@ -16,9 +16,13 @@ properties:
>>         - description: |
>>             The driver is parsing the compat string for Adreno to
>>             figure out the gpu-id and patch level.
>> +          Optional amd,imageon compatibility string enables using Adreno
>> +          without the display node.
>>           items:
>>             - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
>>             - const: qcom,adreno
>> +          - const: amd,imageon
>> +        minItems: 2
> 
> This is too unspecific. You allow any device to be and not to be
> compatible with amd,imageon.

Yes, this is expected (kind of). Would you have any 
alternatives/suggestions?

> 
>>         - description: |
>>             The driver is parsing the compat string for Imageon to
>>             figure out the gpu-id and patch level.
>> @@ -148,6 +152,8 @@ allOf:
>>                   description: GPU 3D engine clock
>>                 - const: rbbmtimer
>>                   description: GPU RBBM Timer for Adreno 5xx series
>> +              - const: rbcpr
>> +                description: GPU RB CPR clock
>>             minItems: 2
>>             maxItems: 7
> 
> Do 8 items work with maxItems:7?

You would have guessed, yes, they do.

-- 
With best wishes
Dmitry

Re: [PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too

[Dmitry Baryshkov]

On 06/07/2022 18:50, Krzysztof Kozlowski wrote:
> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>> The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
>> have been using amd,imageon with newer (Adreno) GPUs to describe the
>> headless setup, when the platform does not (yet) have the display DT
> 
> Does not have "yet"? So later it will have and you drop a compatible?

Yes. For example see the arch/arm64/boot/dts/qcom/8150.dtsi, which 
currently has only GPU node. Once we add MDSS/DPU/DSI/etc. nodes, we are 
going to drop the compat string.

> 
>> nodes (and no display support). Document this trick in the schema.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
>>   1 file changed, 6 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> index 346aabdccf7b..e006da95462c 100644
>> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>> @@ -16,9 +16,13 @@ properties:
>>         - description: |
>>             The driver is parsing the compat string for Adreno to
>>             figure out the gpu-id and patch level.
>> +          Optional amd,imageon compatibility string enables using Adreno
>> +          without the display node.
>>           items:
>>             - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
>>             - const: qcom,adreno
>> +          - const: amd,imageon
>> +        minItems: 2
> 
> This is too unspecific. You allow any device to be and not to be
> compatible with amd,imageon.

Yes, this is expected (kind of). Would you have any 
alternatives/suggestions?

> 
>>         - description: |
>>             The driver is parsing the compat string for Imageon to
>>             figure out the gpu-id and patch level.
>> @@ -148,6 +152,8 @@ allOf:
>>                   description: GPU 3D engine clock
>>                 - const: rbbmtimer
>>                   description: GPU RBBM Timer for Adreno 5xx series
>> +              - const: rbcpr
>> +                description: GPU RB CPR clock
>>             minItems: 2
>>             maxItems: 7
> 
> Do 8 items work with maxItems:7?

You would have guessed, yes, they do.

-- 
With best wishes
Dmitry

Re: [PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too

[Krzysztof Kozlowski]

On 06/07/2022 18:00, Dmitry Baryshkov wrote:
> On 06/07/2022 18:50, Krzysztof Kozlowski wrote:
>> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>>> The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
>>> have been using amd,imageon with newer (Adreno) GPUs to describe the
>>> headless setup, when the platform does not (yet) have the display DT
>>
>> Does not have "yet"? So later it will have and you drop a compatible?
> 
> Yes. For example see the arch/arm64/boot/dts/qcom/8150.dtsi, which 
> currently has only GPU node. Once we add MDSS/DPU/DSI/etc. nodes, we are 
> going to drop the compat string.
> 
>>
>>> nodes (and no display support). Document this trick in the schema.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>>   Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
>>>   1 file changed, 6 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>> index 346aabdccf7b..e006da95462c 100644
>>> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>> @@ -16,9 +16,13 @@ properties:
>>>         - description: |
>>>             The driver is parsing the compat string for Adreno to
>>>             figure out the gpu-id and patch level.
>>> +          Optional amd,imageon compatibility string enables using Adreno
>>> +          without the display node.
>>>           items:
>>>             - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
>>>             - const: qcom,adreno
>>> +          - const: amd,imageon
>>> +        minItems: 2
>>
>> This is too unspecific. You allow any device to be and not to be
>> compatible with amd,imageon.
> 
> Yes, this is expected (kind of). Would you have any 
> alternatives/suggestions?

Using compatible for this kind of breaks the entire idea behind
compatibles, because the device does not stop being compatible with
amd,imageon. Either it is or it is not. I would understand that drop the
compatible per boards which physically do not have display, physically
are headless. But the comment in sm8250:
"make sure to remove it when display node is added"
is just confusing.

The typical solution would be to just check the properties of the device
and choose different mode if display is missing (via port graph or some
other way how the gpu is actually linked to the display).


Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too

[Krzysztof Kozlowski]

On 06/07/2022 18:00, Dmitry Baryshkov wrote:
> On 06/07/2022 18:50, Krzysztof Kozlowski wrote:
>> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>>> The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
>>> have been using amd,imageon with newer (Adreno) GPUs to describe the
>>> headless setup, when the platform does not (yet) have the display DT
>>
>> Does not have "yet"? So later it will have and you drop a compatible?
> 
> Yes. For example see the arch/arm64/boot/dts/qcom/8150.dtsi, which 
> currently has only GPU node. Once we add MDSS/DPU/DSI/etc. nodes, we are 
> going to drop the compat string.
> 
>>
>>> nodes (and no display support). Document this trick in the schema.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>>   Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
>>>   1 file changed, 6 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>> index 346aabdccf7b..e006da95462c 100644
>>> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>> @@ -16,9 +16,13 @@ properties:
>>>         - description: |
>>>             The driver is parsing the compat string for Adreno to
>>>             figure out the gpu-id and patch level.
>>> +          Optional amd,imageon compatibility string enables using Adreno
>>> +          without the display node.
>>>           items:
>>>             - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
>>>             - const: qcom,adreno
>>> +          - const: amd,imageon
>>> +        minItems: 2
>>
>> This is too unspecific. You allow any device to be and not to be
>> compatible with amd,imageon.
> 
> Yes, this is expected (kind of). Would you have any 
> alternatives/suggestions?

Using compatible for this kind of breaks the entire idea behind
compatibles, because the device does not stop being compatible with
amd,imageon. Either it is or it is not. I would understand that drop the
compatible per boards which physically do not have display, physically
are headless. But the comment in sm8250:
"make sure to remove it when display node is added"
is just confusing.

The typical solution would be to just check the properties of the device
and choose different mode if display is missing (via port graph or some
other way how the gpu is actually linked to the display).


Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too

[Dmitry Baryshkov]

On 06/07/2022 19:19, Krzysztof Kozlowski wrote:
> On 06/07/2022 18:00, Dmitry Baryshkov wrote:
>> On 06/07/2022 18:50, Krzysztof Kozlowski wrote:
>>> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>>>> The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
>>>> have been using amd,imageon with newer (Adreno) GPUs to describe the
>>>> headless setup, when the platform does not (yet) have the display DT
>>>
>>> Does not have "yet"? So later it will have and you drop a compatible?
>>
>> Yes. For example see the arch/arm64/boot/dts/qcom/8150.dtsi, which
>> currently has only GPU node. Once we add MDSS/DPU/DSI/etc. nodes, we are
>> going to drop the compat string.
>>
>>>
>>>> nodes (and no display support). Document this trick in the schema.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>>    Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
>>>>    1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>>> index 346aabdccf7b..e006da95462c 100644
>>>> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>>> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>>> @@ -16,9 +16,13 @@ properties:
>>>>          - description: |
>>>>              The driver is parsing the compat string for Adreno to
>>>>              figure out the gpu-id and patch level.
>>>> +          Optional amd,imageon compatibility string enables using Adreno
>>>> +          without the display node.
>>>>            items:
>>>>              - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
>>>>              - const: qcom,adreno
>>>> +          - const: amd,imageon
>>>> +        minItems: 2
>>>
>>> This is too unspecific. You allow any device to be and not to be
>>> compatible with amd,imageon.
>>
>> Yes, this is expected (kind of). Would you have any
>> alternatives/suggestions?
> 
> Using compatible for this kind of breaks the entire idea behind
> compatibles, because the device does not stop being compatible with
> amd,imageon. Either it is or it is not. I would understand that drop the
> compatible per boards which physically do not have display, physically
> are headless. But the comment in sm8250:
> "make sure to remove it when display node is added"
> is just confusing.
> 
> The typical solution would be to just check the properties of the device
> and choose different mode if display is missing (via port graph or some
> other way how the gpu is actually linked to the display).

The problem is that the gpu doesn't get linked to the display per se.

On imx5 platforms the GPU (compatible with amd,imageon) is a standalone 
device. On qcom platforms the GPU (qcom,adreno) is used as a component 
in multi-component device. By enlisting qmd,imageon for newer Adreno 
devices we just enforce non-standard probing sequence, because all other 
components just do not exist.

So, yes, this is hack around compatibles. However probably the only 
viable alternative around it would be to check in probe path if there is 
any device node compatible with "qcom,foo-mdss".

-- 
With best wishes
Dmitry

Re: [PATCH 2/4] dt-bindings: display/msm/gpu: document using the amd,imageon adreno too

[Dmitry Baryshkov]

On 06/07/2022 19:19, Krzysztof Kozlowski wrote:
> On 06/07/2022 18:00, Dmitry Baryshkov wrote:
>> On 06/07/2022 18:50, Krzysztof Kozlowski wrote:
>>> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>>>> The DT binding desribes using amd,imageon only for Imageon 2xx GPUs. We
>>>> have been using amd,imageon with newer (Adreno) GPUs to describe the
>>>> headless setup, when the platform does not (yet) have the display DT
>>>
>>> Does not have "yet"? So later it will have and you drop a compatible?
>>
>> Yes. For example see the arch/arm64/boot/dts/qcom/8150.dtsi, which
>> currently has only GPU node. Once we add MDSS/DPU/DSI/etc. nodes, we are
>> going to drop the compat string.
>>
>>>
>>>> nodes (and no display support). Document this trick in the schema.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>>    Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++
>>>>    1 file changed, 6 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>>> index 346aabdccf7b..e006da95462c 100644
>>>> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>>> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
>>>> @@ -16,9 +16,13 @@ properties:
>>>>          - description: |
>>>>              The driver is parsing the compat string for Adreno to
>>>>              figure out the gpu-id and patch level.
>>>> +          Optional amd,imageon compatibility string enables using Adreno
>>>> +          without the display node.
>>>>            items:
>>>>              - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
>>>>              - const: qcom,adreno
>>>> +          - const: amd,imageon
>>>> +        minItems: 2
>>>
>>> This is too unspecific. You allow any device to be and not to be
>>> compatible with amd,imageon.
>>
>> Yes, this is expected (kind of). Would you have any
>> alternatives/suggestions?
> 
> Using compatible for this kind of breaks the entire idea behind
> compatibles, because the device does not stop being compatible with
> amd,imageon. Either it is or it is not. I would understand that drop the
> compatible per boards which physically do not have display, physically
> are headless. But the comment in sm8250:
> "make sure to remove it when display node is added"
> is just confusing.
> 
> The typical solution would be to just check the properties of the device
> and choose different mode if display is missing (via port graph or some
> other way how the gpu is actually linked to the display).

The problem is that the gpu doesn't get linked to the display per se.

On imx5 platforms the GPU (compatible with amd,imageon) is a standalone 
device. On qcom platforms the GPU (qcom,adreno) is used as a component 
in multi-component device. By enlisting qmd,imageon for newer Adreno 
devices we just enforce non-standard probing sequence, because all other 
components just do not exist.

So, yes, this is hack around compatibles. However probably the only 
viable alternative around it would be to check in probe path if there is 
any device node compatible with "qcom,foo-mdss".

-- 
With best wishes
Dmitry

[PATCH 3/4] dt-bindings: display/msm/gmu: account for different GMU variants

[Dmitry Baryshkov]

Make display/msm/gmu.yaml describe all existing GMU variants rather than
just the 630.2 (SDM845) version of it.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
 1 file changed, 146 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index fe55611d2603..67fdeeabae0c 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -20,35 +20,24 @@ description: |
 properties:
   compatible:
     items:
-      - enum:
-          - qcom,adreno-gmu-630.2
+      - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
       - const: qcom,adreno-gmu
 
   reg:
-    items:
-      - description: Core GMU registers
-      - description: GMU PDC registers
-      - description: GMU PDC sequence registers
+    minItems: 3
+    maxItems: 4
 
   reg-names:
-    items:
-      - const: gmu
-      - const: gmu_pdc
-      - const: gmu_pdc_seq
+    minItems: 3
+    maxItems: 4
 
   clocks:
-    items:
-      - description: GMU clock
-      - description: GPU CX clock
-      - description: GPU AXI clock
-      - description: GPU MEMNOC clock
+    minItems: 4
+    maxItems: 7
 
   clock-names:
-    items:
-      - const: gmu
-      - const: cxo
-      - const: axi
-      - const: memnoc
+    minItems: 4
+    maxItems: 7
 
   interrupts:
     items:
@@ -76,6 +65,9 @@ properties:
 
   operating-points-v2: true
 
+  opp-table:
+    type: object
+
 required:
   - compatible
   - reg
@@ -91,6 +83,140 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-618.0
+              - qcom,adreno-gmu-630.2
+    then:
+      properties:
+        reg:
+          items:
+            - description: Core GMU registers
+            - description: GMU PDC registers
+            - description: GMU PDC sequence registers
+        reg-names:
+          items:
+            - const: gmu
+            - const: gmu_pdc
+            - const: gmu_pdc_seq
+        clocks:
+          items:
+            - description: GMU clock
+            - description: GPU CX clock
+            - description: GPU AXI clock
+            - description: GPU MEMNOC clock
+        clock-names:
+          items:
+            - const: gmu
+            - const: cxo
+            - const: axi
+            - const: memnoc
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-635.0
+    then:
+      properties:
+        reg:
+          items:
+            - description: Core GMU registers
+            - description: Resource controller registers
+            - description: GMU PDC registers
+        reg-names:
+          items:
+            - const: gmu
+            - const: rscc
+            - const: gmu_pdc
+        clocks:
+          items:
+            - description: GMU clock
+            - description: GPU CX clock
+            - description: GPU AXI clock
+            - description: GPU MEMNOC clock
+            - description: GPU AHB clock
+            - description: GPU HUB CX clock
+            - description: GPU SMMU vote clock
+        clock-names:
+          items:
+            - const: gmu
+            - const: cxo
+            - const: axi
+            - const: memnoc
+            - const: ahb
+            - const: hub
+            - const: smmu_vote
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-640.1
+    then:
+      properties:
+        reg:
+          items:
+            - description: Core GMU registers
+            - description: GMU PDC registers
+            - description: GMU PDC sequence registers
+        reg-names:
+          items:
+            - const: gmu
+            - const: gmu_pdc
+            - const: gmu_pdc_seq
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-650.2
+    then:
+      properties:
+        reg:
+          items:
+            - description: Core GMU registers
+            - description: Resource controller registers
+            - description: GMU PDC registers
+            - description: GMU PDC sequence registers
+        reg-names:
+          items:
+            - const: gmu
+            - const: rscc
+            - const: gmu_pdc
+            - const: gmu_pdc_seq
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-640.1
+              - qcom,adreno-gmu-650.2
+    then:
+      properties:
+        clocks:
+          items:
+            - description: GPU AHB clock
+            - description: GMU clock
+            - description: GPU CX clock
+            - description: GPU AXI clock
+            - description: GPU MEMNOC clock
+        clock-names:
+          items:
+            - const: ahb
+            - const: gmu
+            - const: cxo
+            - const: axi
+            - const: memnoc
+
 examples:
   - |
     #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
-- 
2.35.1

[PATCH 3/4] dt-bindings: display/msm/gmu: account for different GMU variants

[Dmitry Baryshkov]

Make display/msm/gmu.yaml describe all existing GMU variants rather than
just the 630.2 (SDM845) version of it.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
 1 file changed, 146 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index fe55611d2603..67fdeeabae0c 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -20,35 +20,24 @@ description: |
 properties:
   compatible:
     items:
-      - enum:
-          - qcom,adreno-gmu-630.2
+      - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
       - const: qcom,adreno-gmu
 
   reg:
-    items:
-      - description: Core GMU registers
-      - description: GMU PDC registers
-      - description: GMU PDC sequence registers
+    minItems: 3
+    maxItems: 4
 
   reg-names:
-    items:
-      - const: gmu
-      - const: gmu_pdc
-      - const: gmu_pdc_seq
+    minItems: 3
+    maxItems: 4
 
   clocks:
-    items:
-      - description: GMU clock
-      - description: GPU CX clock
-      - description: GPU AXI clock
-      - description: GPU MEMNOC clock
+    minItems: 4
+    maxItems: 7
 
   clock-names:
-    items:
-      - const: gmu
-      - const: cxo
-      - const: axi
-      - const: memnoc
+    minItems: 4
+    maxItems: 7
 
   interrupts:
     items:
@@ -76,6 +65,9 @@ properties:
 
   operating-points-v2: true
 
+  opp-table:
+    type: object
+
 required:
   - compatible
   - reg
@@ -91,6 +83,140 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-618.0
+              - qcom,adreno-gmu-630.2
+    then:
+      properties:
+        reg:
+          items:
+            - description: Core GMU registers
+            - description: GMU PDC registers
+            - description: GMU PDC sequence registers
+        reg-names:
+          items:
+            - const: gmu
+            - const: gmu_pdc
+            - const: gmu_pdc_seq
+        clocks:
+          items:
+            - description: GMU clock
+            - description: GPU CX clock
+            - description: GPU AXI clock
+            - description: GPU MEMNOC clock
+        clock-names:
+          items:
+            - const: gmu
+            - const: cxo
+            - const: axi
+            - const: memnoc
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-635.0
+    then:
+      properties:
+        reg:
+          items:
+            - description: Core GMU registers
+            - description: Resource controller registers
+            - description: GMU PDC registers
+        reg-names:
+          items:
+            - const: gmu
+            - const: rscc
+            - const: gmu_pdc
+        clocks:
+          items:
+            - description: GMU clock
+            - description: GPU CX clock
+            - description: GPU AXI clock
+            - description: GPU MEMNOC clock
+            - description: GPU AHB clock
+            - description: GPU HUB CX clock
+            - description: GPU SMMU vote clock
+        clock-names:
+          items:
+            - const: gmu
+            - const: cxo
+            - const: axi
+            - const: memnoc
+            - const: ahb
+            - const: hub
+            - const: smmu_vote
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-640.1
+    then:
+      properties:
+        reg:
+          items:
+            - description: Core GMU registers
+            - description: GMU PDC registers
+            - description: GMU PDC sequence registers
+        reg-names:
+          items:
+            - const: gmu
+            - const: gmu_pdc
+            - const: gmu_pdc_seq
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-650.2
+    then:
+      properties:
+        reg:
+          items:
+            - description: Core GMU registers
+            - description: Resource controller registers
+            - description: GMU PDC registers
+            - description: GMU PDC sequence registers
+        reg-names:
+          items:
+            - const: gmu
+            - const: rscc
+            - const: gmu_pdc
+            - const: gmu_pdc_seq
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,adreno-gmu-640.1
+              - qcom,adreno-gmu-650.2
+    then:
+      properties:
+        clocks:
+          items:
+            - description: GPU AHB clock
+            - description: GMU clock
+            - description: GPU CX clock
+            - description: GPU AXI clock
+            - description: GPU MEMNOC clock
+        clock-names:
+          items:
+            - const: ahb
+            - const: gmu
+            - const: cxo
+            - const: axi
+            - const: memnoc
+
 examples:
   - |
     #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
-- 
2.35.1

Re: [PATCH 3/4] dt-bindings: display/msm/gmu: account for different GMU variants

[Krzysztof Kozlowski]

On 06/07/2022 16:52, Dmitry Baryshkov wrote:
> Make display/msm/gmu.yaml describe all existing GMU variants rather than
> just the 630.2 (SDM845) version of it.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
>  1 file changed, 146 insertions(+), 20 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> index fe55611d2603..67fdeeabae0c 100644
> --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> @@ -20,35 +20,24 @@ description: |
>  properties:
>    compatible:
>      items:
> -      - enum:
> -          - qcom,adreno-gmu-630.2
> +      - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
>        - const: qcom,adreno-gmu
>  
>    reg:
> -    items:
> -      - description: Core GMU registers
> -      - description: GMU PDC registers
> -      - description: GMU PDC sequence registers
> +    minItems: 3
> +    maxItems: 4
>  
>    reg-names:
> -    items:
> -      - const: gmu
> -      - const: gmu_pdc
> -      - const: gmu_pdc_seq
> +    minItems: 3
> +    maxItems: 4
>  
>    clocks:
> -    items:
> -      - description: GMU clock
> -      - description: GPU CX clock
> -      - description: GPU AXI clock
> -      - description: GPU MEMNOC clock
> +    minItems: 4
> +    maxItems: 7
>  
>    clock-names:
> -    items:
> -      - const: gmu
> -      - const: cxo
> -      - const: axi
> -      - const: memnoc
> +    minItems: 4
> +    maxItems: 7
>  
>    interrupts:
>      items:
> @@ -76,6 +65,9 @@ properties:
>  
>    operating-points-v2: true
>  
> +  opp-table:
> +    type: object

instead: opp-table:true

> +

Best regards,
Krzysztof

Re: [PATCH 3/4] dt-bindings: display/msm/gmu: account for different GMU variants

[Krzysztof Kozlowski]

On 06/07/2022 16:52, Dmitry Baryshkov wrote:
> Make display/msm/gmu.yaml describe all existing GMU variants rather than
> just the 630.2 (SDM845) version of it.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
>  1 file changed, 146 insertions(+), 20 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> index fe55611d2603..67fdeeabae0c 100644
> --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> @@ -20,35 +20,24 @@ description: |
>  properties:
>    compatible:
>      items:
> -      - enum:
> -          - qcom,adreno-gmu-630.2
> +      - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
>        - const: qcom,adreno-gmu
>  
>    reg:
> -    items:
> -      - description: Core GMU registers
> -      - description: GMU PDC registers
> -      - description: GMU PDC sequence registers
> +    minItems: 3
> +    maxItems: 4
>  
>    reg-names:
> -    items:
> -      - const: gmu
> -      - const: gmu_pdc
> -      - const: gmu_pdc_seq
> +    minItems: 3
> +    maxItems: 4
>  
>    clocks:
> -    items:
> -      - description: GMU clock
> -      - description: GPU CX clock
> -      - description: GPU AXI clock
> -      - description: GPU MEMNOC clock
> +    minItems: 4
> +    maxItems: 7
>  
>    clock-names:
> -    items:
> -      - const: gmu
> -      - const: cxo
> -      - const: axi
> -      - const: memnoc
> +    minItems: 4
> +    maxItems: 7
>  
>    interrupts:
>      items:
> @@ -76,6 +65,9 @@ properties:
>  
>    operating-points-v2: true
>  
> +  opp-table:
> +    type: object

instead: opp-table:true

> +

Best regards,
Krzysztof

Re: [PATCH 3/4] dt-bindings: display/msm/gmu: account for different GMU variants

[Dmitry Baryshkov]

On 06/07/2022 18:52, Krzysztof Kozlowski wrote:
> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>> Make display/msm/gmu.yaml describe all existing GMU variants rather than
>> just the 630.2 (SDM845) version of it.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
>>   1 file changed, 146 insertions(+), 20 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
>> index fe55611d2603..67fdeeabae0c 100644
>> --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
>> @@ -20,35 +20,24 @@ description: |
>>   properties:
>>     compatible:
>>       items:
>> -      - enum:
>> -          - qcom,adreno-gmu-630.2
>> +      - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
>>         - const: qcom,adreno-gmu
>>   
>>     reg:
>> -    items:
>> -      - description: Core GMU registers
>> -      - description: GMU PDC registers
>> -      - description: GMU PDC sequence registers
>> +    minItems: 3
>> +    maxItems: 4
>>   
>>     reg-names:
>> -    items:
>> -      - const: gmu
>> -      - const: gmu_pdc
>> -      - const: gmu_pdc_seq
>> +    minItems: 3
>> +    maxItems: 4
>>   
>>     clocks:
>> -    items:
>> -      - description: GMU clock
>> -      - description: GPU CX clock
>> -      - description: GPU AXI clock
>> -      - description: GPU MEMNOC clock
>> +    minItems: 4
>> +    maxItems: 7
>>   
>>     clock-names:
>> -    items:
>> -      - const: gmu
>> -      - const: cxo
>> -      - const: axi
>> -      - const: memnoc
>> +    minItems: 4
>> +    maxItems: 7
>>   
>>     interrupts:
>>       items:
>> @@ -76,6 +65,9 @@ properties:
>>   
>>     operating-points-v2: true
>>   
>> +  opp-table:
>> +    type: object
> 
> instead: opp-table:true

Wouldn't this allow e.g. using just 'opp-table;' as a flag?

> 
>> +
> 
> Best regards,
> Krzysztof

-- 
With best wishes
Dmitry

Re: [PATCH 3/4] dt-bindings: display/msm/gmu: account for different GMU variants

[Dmitry Baryshkov]

On 06/07/2022 18:52, Krzysztof Kozlowski wrote:
> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>> Make display/msm/gmu.yaml describe all existing GMU variants rather than
>> just the 630.2 (SDM845) version of it.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>>   .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
>>   1 file changed, 146 insertions(+), 20 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
>> index fe55611d2603..67fdeeabae0c 100644
>> --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
>> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
>> @@ -20,35 +20,24 @@ description: |
>>   properties:
>>     compatible:
>>       items:
>> -      - enum:
>> -          - qcom,adreno-gmu-630.2
>> +      - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
>>         - const: qcom,adreno-gmu
>>   
>>     reg:
>> -    items:
>> -      - description: Core GMU registers
>> -      - description: GMU PDC registers
>> -      - description: GMU PDC sequence registers
>> +    minItems: 3
>> +    maxItems: 4
>>   
>>     reg-names:
>> -    items:
>> -      - const: gmu
>> -      - const: gmu_pdc
>> -      - const: gmu_pdc_seq
>> +    minItems: 3
>> +    maxItems: 4
>>   
>>     clocks:
>> -    items:
>> -      - description: GMU clock
>> -      - description: GPU CX clock
>> -      - description: GPU AXI clock
>> -      - description: GPU MEMNOC clock
>> +    minItems: 4
>> +    maxItems: 7
>>   
>>     clock-names:
>> -    items:
>> -      - const: gmu
>> -      - const: cxo
>> -      - const: axi
>> -      - const: memnoc
>> +    minItems: 4
>> +    maxItems: 7
>>   
>>     interrupts:
>>       items:
>> @@ -76,6 +65,9 @@ properties:
>>   
>>     operating-points-v2: true
>>   
>> +  opp-table:
>> +    type: object
> 
> instead: opp-table:true

Wouldn't this allow e.g. using just 'opp-table;' as a flag?

> 
>> +
> 
> Best regards,
> Krzysztof

-- 
With best wishes
Dmitry

Re: [PATCH 3/4] dt-bindings: display/msm/gmu: account for different GMU variants

[Krzysztof Kozlowski]

On 22/08/2022 20:58, Dmitry Baryshkov wrote:
> On 06/07/2022 18:52, Krzysztof Kozlowski wrote:
>> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>>> Make display/msm/gmu.yaml describe all existing GMU variants rather than
>>> just the 630.2 (SDM845) version of it.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>>   .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
>>>   1 file changed, 146 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
>>> index fe55611d2603..67fdeeabae0c 100644
>>> --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
>>> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
>>> @@ -20,35 +20,24 @@ description: |
>>>   properties:
>>>     compatible:
>>>       items:
>>> -      - enum:
>>> -          - qcom,adreno-gmu-630.2
>>> +      - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
>>>         - const: qcom,adreno-gmu
>>>   
>>>     reg:
>>> -    items:
>>> -      - description: Core GMU registers
>>> -      - description: GMU PDC registers
>>> -      - description: GMU PDC sequence registers
>>> +    minItems: 3
>>> +    maxItems: 4
>>>   
>>>     reg-names:
>>> -    items:
>>> -      - const: gmu
>>> -      - const: gmu_pdc
>>> -      - const: gmu_pdc_seq
>>> +    minItems: 3
>>> +    maxItems: 4
>>>   
>>>     clocks:
>>> -    items:
>>> -      - description: GMU clock
>>> -      - description: GPU CX clock
>>> -      - description: GPU AXI clock
>>> -      - description: GPU MEMNOC clock
>>> +    minItems: 4
>>> +    maxItems: 7
>>>   
>>>     clock-names:
>>> -    items:
>>> -      - const: gmu
>>> -      - const: cxo
>>> -      - const: axi
>>> -      - const: memnoc
>>> +    minItems: 4
>>> +    maxItems: 7
>>>   
>>>     interrupts:
>>>       items:
>>> @@ -76,6 +65,9 @@ properties:
>>>   
>>>     operating-points-v2: true
>>>   
>>> +  opp-table:
>>> +    type: object
>>
>> instead: opp-table:true
> 
> Wouldn't this allow e.g. using just 'opp-table;' as a flag?

You're right and Rob also corrected me. Your original patch was correct
(type:object).

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 3/4] dt-bindings: display/msm/gmu: account for different GMU variants

[Krzysztof Kozlowski]

On 22/08/2022 20:58, Dmitry Baryshkov wrote:
> On 06/07/2022 18:52, Krzysztof Kozlowski wrote:
>> On 06/07/2022 16:52, Dmitry Baryshkov wrote:
>>> Make display/msm/gmu.yaml describe all existing GMU variants rather than
>>> just the 630.2 (SDM845) version of it.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>>   .../devicetree/bindings/display/msm/gmu.yaml  | 166 +++++++++++++++---
>>>   1 file changed, 146 insertions(+), 20 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
>>> index fe55611d2603..67fdeeabae0c 100644
>>> --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
>>> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
>>> @@ -20,35 +20,24 @@ description: |
>>>   properties:
>>>     compatible:
>>>       items:
>>> -      - enum:
>>> -          - qcom,adreno-gmu-630.2
>>> +      - pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
>>>         - const: qcom,adreno-gmu
>>>   
>>>     reg:
>>> -    items:
>>> -      - description: Core GMU registers
>>> -      - description: GMU PDC registers
>>> -      - description: GMU PDC sequence registers
>>> +    minItems: 3
>>> +    maxItems: 4
>>>   
>>>     reg-names:
>>> -    items:
>>> -      - const: gmu
>>> -      - const: gmu_pdc
>>> -      - const: gmu_pdc_seq
>>> +    minItems: 3
>>> +    maxItems: 4
>>>   
>>>     clocks:
>>> -    items:
>>> -      - description: GMU clock
>>> -      - description: GPU CX clock
>>> -      - description: GPU AXI clock
>>> -      - description: GPU MEMNOC clock
>>> +    minItems: 4
>>> +    maxItems: 7
>>>   
>>>     clock-names:
>>> -    items:
>>> -      - const: gmu
>>> -      - const: cxo
>>> -      - const: axi
>>> -      - const: memnoc
>>> +    minItems: 4
>>> +    maxItems: 7
>>>   
>>>     interrupts:
>>>       items:
>>> @@ -76,6 +65,9 @@ properties:
>>>   
>>>     operating-points-v2: true
>>>   
>>> +  opp-table:
>>> +    type: object
>>
>> instead: opp-table:true
> 
> Wouldn't this allow e.g. using just 'opp-table;' as a flag?

You're right and Rob also corrected me. Your original patch was correct
(type:object).

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

[PATCH 4/4] dt-bindings: display/msm/mdp4: require 4 IOMMUs

[Dmitry Baryshkov]

APQ8064, the only supported mdp4 platform, uses 4 IOMMUs for the MDP4
device. Update schema accordingly. When we have other MDP4 platforms,
this spec can be updated accordingly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/mdp4.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.yaml b/Documentation/devicetree/bindings/display/msm/mdp4.yaml
index f63f60fea27c..58c13f5277b6 100644
--- a/Documentation/devicetree/bindings/display/msm/mdp4.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdp4.yaml
@@ -36,7 +36,7 @@ properties:
     maxItems: 1
 
   iommus:
-    maxItems: 1
+    maxItems: 4
 
   ports:
     $ref: /schemas/graph.yaml#/properties/ports
-- 
2.35.1

[PATCH 4/4] dt-bindings: display/msm/mdp4: require 4 IOMMUs

[Dmitry Baryshkov]

APQ8064, the only supported mdp4 platform, uses 4 IOMMUs for the MDP4
device. Update schema accordingly. When we have other MDP4 platforms,
this spec can be updated accordingly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 Documentation/devicetree/bindings/display/msm/mdp4.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.yaml b/Documentation/devicetree/bindings/display/msm/mdp4.yaml
index f63f60fea27c..58c13f5277b6 100644
--- a/Documentation/devicetree/bindings/display/msm/mdp4.yaml
+++ b/Documentation/devicetree/bindings/display/msm/mdp4.yaml
@@ -36,7 +36,7 @@ properties:
     maxItems: 1
 
   iommus:
-    maxItems: 1
+    maxItems: 4
 
   ports:
     $ref: /schemas/graph.yaml#/properties/ports
-- 
2.35.1

Re: [PATCH 4/4] dt-bindings: display/msm/mdp4: require 4 IOMMUs

[Krzysztof Kozlowski]

On 06/07/2022 16:52, Dmitry Baryshkov wrote:
> APQ8064, the only supported mdp4 platform, uses 4 IOMMUs for the MDP4
> device. Update schema accordingly. When we have other MDP4 platforms,
> this spec can be updated accordingly.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 4/4] dt-bindings: display/msm/mdp4: require 4 IOMMUs

[Krzysztof Kozlowski]

On 06/07/2022 16:52, Dmitry Baryshkov wrote:
> APQ8064, the only supported mdp4 platform, uses 4 IOMMUs for the MDP4
> device. Update schema accordingly. When we have other MDP4 platforms,
> this spec can be updated accordingly.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof