[PATCH 1/2] ARM: realview: Fix PBX-A9 cache description

[PATCH 1/2] ARM: realview: Fix PBX-A9 cache description

[Robin Murphy]

Clearly QEMU is very permissive in how its PL310 model may be set up,
but the real hardware turns out to be far more particular about things
actually being correct. Fix up the DT description so that the real
thing actually boots:

- The arm,data-latency and arm,tag-latency properties need 3 cells to
  be valid, otherwise we end up retaining the default 8-cycle latencies
  which leads pretty quickly to lockup.
- The arm,dirty-latency property is only relevant to L210/L220, so get
  rid of it.
- The cache geometry override also leads to lockup and/or general
  misbehaviour. Irritatingly, the manual doesn't state the actual PL310
  configuration, but based on the boardfile code and poking registers
  from the Boot Monitor, it would seem to be 8 sets of 16KB ways.

With that, we can successfully boot to enjoy the fun of mismatched FPUs...

Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/arm-realview-pbx-a9.dts | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
index db808f92dd79..90d00b407f85 100644
--- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts
+++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
@@ -70,13 +70,12 @@
 		 * associativity as these may be erroneously set
 		 * up by boot loader(s).
 		 */
-		cache-size = <1048576>; // 1MB
-		cache-sets = <4096>;
+		cache-size = <131072>; // 128KB
+		cache-sets = <512>;
 		cache-line-size = <32>;
 		arm,parity-disable;
-		arm,tag-latency = <1>;
-		arm,data-latency = <1 1>;
-		arm,dirty-latency = <1>;
+		arm,tag-latency = <1 1 1>;
+		arm,data-latency = <1 1 1>;
 	};
 
 	scu: scu@1f000000 {
-- 
2.8.1.dirty

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[PATCH 1/2] ARM: realview: Fix PBX-A9 cache description

[Robin Murphy]

Clearly QEMU is very permissive in how its PL310 model may be set up,
but the real hardware turns out to be far more particular about things
actually being correct. Fix up the DT description so that the real
thing actually boots:

- The arm,data-latency and arm,tag-latency properties need 3 cells to
  be valid, otherwise we end up retaining the default 8-cycle latencies
  which leads pretty quickly to lockup.
- The arm,dirty-latency property is only relevant to L210/L220, so get
  rid of it.
- The cache geometry override also leads to lockup and/or general
  misbehaviour. Irritatingly, the manual doesn't state the actual PL310
  configuration, but based on the boardfile code and poking registers
  from the Boot Monitor, it would seem to be 8 sets of 16KB ways.

With that, we can successfully boot to enjoy the fun of mismatched FPUs...

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm/boot/dts/arm-realview-pbx-a9.dts | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
index db808f92dd79..90d00b407f85 100644
--- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts
+++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
@@ -70,13 +70,12 @@
 		 * associativity as these may be erroneously set
 		 * up by boot loader(s).
 		 */
-		cache-size = <1048576>; // 1MB
-		cache-sets = <4096>;
+		cache-size = <131072>; // 128KB
+		cache-sets = <512>;
 		cache-line-size = <32>;
 		arm,parity-disable;
-		arm,tag-latency = <1>;
-		arm,data-latency = <1 1>;
-		arm,dirty-latency = <1>;
+		arm,tag-latency = <1 1 1>;
+		arm,data-latency = <1 1 1>;
 	};
 
 	scu: scu at 1f000000 {
-- 
2.8.1.dirty

[PATCH 2/2] ARM: realview: Extend PBX family memory description

[Robin Murphy]

All three platforms sharing the later RealView Platform Baseboard memory
map - PBX-A9, PB-A8 and PB11MPCore, provide 512MB of DDR SDRAM on the
baseboard, of which the boot alias at 0x0 maps the first 256MB. Expand
the size of the default memory node to refelect that, and describe the
full memory regions in each board's DTS, but leave those commented by
default to avoid breaking existing bootloaders.

Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm/boot/dts/arm-realview-pba8.dts   | 8 ++++++++
 arch/arm/boot/dts/arm-realview-pbx-a9.dts | 9 +++++++++
 arch/arm/boot/dts/arm-realview-pbx.dtsi   | 4 ++--
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/arm-realview-pba8.dts b/arch/arm/boot/dts/arm-realview-pba8.dts
index d3238c252b59..9f6c92b84f9f 100644
--- a/arch/arm/boot/dts/arm-realview-pba8.dts
+++ b/arch/arm/boot/dts/arm-realview-pba8.dts
@@ -40,6 +40,14 @@
 		};
 	};
 
+	/*
+	 * Using the full 512MB of RAM will require bootloader
+	 * changes to not load the kernel to the alias at 0x0.
+	 */
+	memory {
+		/*reg = <0x70000000 0x20000000>; /* 512 MiB baseboard DDR */
+	};
+
 	pmu: pmu@0 {
 		compatible = "arm,cortex-a8-pmu";
 		interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
index 90d00b407f85..9fef9188660a 100644
--- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts
+++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
@@ -60,6 +60,15 @@
 		};
 	};
 
+	/*
+	 * There is 1GB of RAM total, but using all of it will require
+	 * bootloader changes to not load the kernel to the alias at 0x0.
+	 */
+	memory {
+		/*reg = <0x20000000 0x20000000>, /* 512 MiB daughterboard DDR2 */
+		/*      <0x70000000 0x20000000>; /* 512 MiB baseboard DDR */
+	};
+
 	L2: l2-cache {
 		compatible = "arm,pl310-cache";
 		reg = <0x1f002000 0x1000>;
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index aeb49c4bd773..8477f667d27c 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -38,8 +38,8 @@
 	};
 
 	memory {
-		/* 128 MiB memory @ 0x0 */
-		reg = <0x00000000 0x08000000>;
+		/* 256 MiB alias of baseboard DDR @ 0x0 */
+		reg = <0x00000000 0x10000000>;
 	};
 
 	/* The voltage to the MMC card is hardwired at 3.3V */
-- 
2.8.1.dirty

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[PATCH 2/2] ARM: realview: Extend PBX family memory description

[Robin Murphy]

All three platforms sharing the later RealView Platform Baseboard memory
map - PBX-A9, PB-A8 and PB11MPCore, provide 512MB of DDR SDRAM on the
baseboard, of which the boot alias at 0x0 maps the first 256MB. Expand
the size of the default memory node to refelect that, and describe the
full memory regions in each board's DTS, but leave those commented by
default to avoid breaking existing bootloaders.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm/boot/dts/arm-realview-pba8.dts   | 8 ++++++++
 arch/arm/boot/dts/arm-realview-pbx-a9.dts | 9 +++++++++
 arch/arm/boot/dts/arm-realview-pbx.dtsi   | 4 ++--
 3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/arm-realview-pba8.dts b/arch/arm/boot/dts/arm-realview-pba8.dts
index d3238c252b59..9f6c92b84f9f 100644
--- a/arch/arm/boot/dts/arm-realview-pba8.dts
+++ b/arch/arm/boot/dts/arm-realview-pba8.dts
@@ -40,6 +40,14 @@
 		};
 	};
 
+	/*
+	 * Using the full 512MB of RAM will require bootloader
+	 * changes to not load the kernel to the alias at 0x0.
+	 */
+	memory {
+		/*reg = <0x70000000 0x20000000>; /* 512 MiB baseboard DDR */
+	};
+
 	pmu: pmu at 0 {
 		compatible = "arm,cortex-a8-pmu";
 		interrupt-parent = <&intc>;
diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
index 90d00b407f85..9fef9188660a 100644
--- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts
+++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
@@ -60,6 +60,15 @@
 		};
 	};
 
+	/*
+	 * There is 1GB of RAM total, but using all of it will require
+	 * bootloader changes to not load the kernel to the alias at 0x0.
+	 */
+	memory {
+		/*reg = <0x20000000 0x20000000>, /* 512 MiB daughterboard DDR2 */
+		/*      <0x70000000 0x20000000>; /* 512 MiB baseboard DDR */
+	};
+
 	L2: l2-cache {
 		compatible = "arm,pl310-cache";
 		reg = <0x1f002000 0x1000>;
diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi
index aeb49c4bd773..8477f667d27c 100644
--- a/arch/arm/boot/dts/arm-realview-pbx.dtsi
+++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi
@@ -38,8 +38,8 @@
 	};
 
 	memory {
-		/* 128 MiB memory @ 0x0 */
-		reg = <0x00000000 0x08000000>;
+		/* 256 MiB alias of baseboard DDR @ 0x0 */
+		reg = <0x00000000 0x10000000>;
 	};
 
 	/* The voltage to the MMC card is hardwired at 3.3V */
-- 
2.8.1.dirty

Re: [PATCH 1/2] ARM: realview: Fix PBX-A9 cache description

[Robin Murphy]

On 15/07/16 13:19, Robin Murphy wrote:
> Clearly QEMU is very permissive in how its PL310 model may be set up,
> but the real hardware turns out to be far more particular about things
> actually being correct. Fix up the DT description so that the real
> thing actually boots:
> 
> - The arm,data-latency and arm,tag-latency properties need 3 cells to
>   be valid, otherwise we end up retaining the default 8-cycle latencies
>   which leads pretty quickly to lockup.
> - The arm,dirty-latency property is only relevant to L210/L220, so get
>   rid of it.
> - The cache geometry override also leads to lockup and/or general
>   misbehaviour. Irritatingly, the manual doesn't state the actual PL310
>   configuration, but based on the boardfile code and poking registers
>   from the Boot Monitor, it would seem to be 8 sets of 16KB ways.

FWIW, after an afternoon of bothering people I've tracked down the
original spec for the test chip, and can confirm that the configuration
is indeed 8x16KB with parity disabled.

Robin.

> With that, we can successfully boot to enjoy the fun of mismatched FPUs...
> 
> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
> ---
>  arch/arm/boot/dts/arm-realview-pbx-a9.dts | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> index db808f92dd79..90d00b407f85 100644
> --- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> +++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> @@ -70,13 +70,12 @@
>  		 * associativity as these may be erroneously set
>  		 * up by boot loader(s).
>  		 */
> -		cache-size = <1048576>; // 1MB
> -		cache-sets = <4096>;
> +		cache-size = <131072>; // 128KB
> +		cache-sets = <512>;
>  		cache-line-size = <32>;
>  		arm,parity-disable;
> -		arm,tag-latency = <1>;
> -		arm,data-latency = <1 1>;
> -		arm,dirty-latency = <1>;
> +		arm,tag-latency = <1 1 1>;
> +		arm,data-latency = <1 1 1>;
>  	};
>  
>  	scu: scu@1f000000 {
> 

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[PATCH 1/2] ARM: realview: Fix PBX-A9 cache description

[Robin Murphy]

On 15/07/16 13:19, Robin Murphy wrote:
> Clearly QEMU is very permissive in how its PL310 model may be set up,
> but the real hardware turns out to be far more particular about things
> actually being correct. Fix up the DT description so that the real
> thing actually boots:
> 
> - The arm,data-latency and arm,tag-latency properties need 3 cells to
>   be valid, otherwise we end up retaining the default 8-cycle latencies
>   which leads pretty quickly to lockup.
> - The arm,dirty-latency property is only relevant to L210/L220, so get
>   rid of it.
> - The cache geometry override also leads to lockup and/or general
>   misbehaviour. Irritatingly, the manual doesn't state the actual PL310
>   configuration, but based on the boardfile code and poking registers
>   from the Boot Monitor, it would seem to be 8 sets of 16KB ways.

FWIW, after an afternoon of bothering people I've tracked down the
original spec for the test chip, and can confirm that the configuration
is indeed 8x16KB with parity disabled.

Robin.

> With that, we can successfully boot to enjoy the fun of mismatched FPUs...
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>  arch/arm/boot/dts/arm-realview-pbx-a9.dts | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> index db808f92dd79..90d00b407f85 100644
> --- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> +++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> @@ -70,13 +70,12 @@
>  		 * associativity as these may be erroneously set
>  		 * up by boot loader(s).
>  		 */
> -		cache-size = <1048576>; // 1MB
> -		cache-sets = <4096>;
> +		cache-size = <131072>; // 128KB
> +		cache-sets = <512>;
>  		cache-line-size = <32>;
>  		arm,parity-disable;
> -		arm,tag-latency = <1>;
> -		arm,data-latency = <1 1>;
> -		arm,dirty-latency = <1>;
> +		arm,tag-latency = <1 1 1>;
> +		arm,data-latency = <1 1 1>;
>  	};
>  
>  	scu: scu at 1f000000 {
> 

Re: [PATCH 1/2] ARM: realview: Fix PBX-A9 cache description

[Mark Rutland]

On Fri, Jul 15, 2016 at 01:19:12PM +0100, Robin Murphy wrote:
> Clearly QEMU is very permissive in how its PL310 model may be set up,
> but the real hardware turns out to be far more particular about things
> actually being correct. Fix up the DT description so that the real
> thing actually boots:
> 
> - The arm,data-latency and arm,tag-latency properties need 3 cells to
>   be valid, otherwise we end up retaining the default 8-cycle latencies
>   which leads pretty quickly to lockup.
> - The arm,dirty-latency property is only relevant to L210/L220, so get
>   rid of it.
> - The cache geometry override also leads to lockup and/or general
>   misbehaviour. Irritatingly, the manual doesn't state the actual PL310
>   configuration, but based on the boardfile code and poking registers
>   from the Boot Monitor, it would seem to be 8 sets of 16KB ways.
> 
> With that, we can successfully boot to enjoy the fun of mismatched FPUs...
> 
> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>

Prior to this patch, v4.7-rc6 would lock up immediately after:

[    0.000000] L2C OF: override cache size: 1048576 bytes (1024KB)
[    0.000000] L2C OF: override line size: 32 bytes
[    0.000000] L2C OF: override way size: 131072 bytes (128KB)
[    0.000000] L2C OF: override associativity: 8
[    0.000000] L2C: DT/platform modifies aux control register: 0x02020000 -> 0x02080000
[    0.000000] L2C: DT/platform tries to modify or specify cache size
[    0.000000] L2C-310 errata 588369 769419 enabled
[    0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[    0.000000] L2C-310 cache controller enabled, 8 ways, 1024 kB

With this patch, I make it all the way to userspace. I have a Debian Wheezy
armel image which seems happy on the board so far.

So FWIW:

Tested-by: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>

Thanks,
Mark.

> ---
>  arch/arm/boot/dts/arm-realview-pbx-a9.dts | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> index db808f92dd79..90d00b407f85 100644
> --- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> +++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> @@ -70,13 +70,12 @@
>  		 * associativity as these may be erroneously set
>  		 * up by boot loader(s).
>  		 */
> -		cache-size = <1048576>; // 1MB
> -		cache-sets = <4096>;
> +		cache-size = <131072>; // 128KB
> +		cache-sets = <512>;
>  		cache-line-size = <32>;
>  		arm,parity-disable;
> -		arm,tag-latency = <1>;
> -		arm,data-latency = <1 1>;
> -		arm,dirty-latency = <1>;
> +		arm,tag-latency = <1 1 1>;
> +		arm,data-latency = <1 1 1>;
>  	};
>  
>  	scu: scu@1f000000 {
> -- 
> 2.8.1.dirty
> 
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[PATCH 1/2] ARM: realview: Fix PBX-A9 cache description

[Mark Rutland]

On Fri, Jul 15, 2016 at 01:19:12PM +0100, Robin Murphy wrote:
> Clearly QEMU is very permissive in how its PL310 model may be set up,
> but the real hardware turns out to be far more particular about things
> actually being correct. Fix up the DT description so that the real
> thing actually boots:
> 
> - The arm,data-latency and arm,tag-latency properties need 3 cells to
>   be valid, otherwise we end up retaining the default 8-cycle latencies
>   which leads pretty quickly to lockup.
> - The arm,dirty-latency property is only relevant to L210/L220, so get
>   rid of it.
> - The cache geometry override also leads to lockup and/or general
>   misbehaviour. Irritatingly, the manual doesn't state the actual PL310
>   configuration, but based on the boardfile code and poking registers
>   from the Boot Monitor, it would seem to be 8 sets of 16KB ways.
> 
> With that, we can successfully boot to enjoy the fun of mismatched FPUs...
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

Prior to this patch, v4.7-rc6 would lock up immediately after:

[    0.000000] L2C OF: override cache size: 1048576 bytes (1024KB)
[    0.000000] L2C OF: override line size: 32 bytes
[    0.000000] L2C OF: override way size: 131072 bytes (128KB)
[    0.000000] L2C OF: override associativity: 8
[    0.000000] L2C: DT/platform modifies aux control register: 0x02020000 -> 0x02080000
[    0.000000] L2C: DT/platform tries to modify or specify cache size
[    0.000000] L2C-310 errata 588369 769419 enabled
[    0.000000] L2C-310 full line of zeros enabled for Cortex-A9
[    0.000000] L2C-310 cache controller enabled, 8 ways, 1024 kB

With this patch, I make it all the way to userspace. I have a Debian Wheezy
armel image which seems happy on the board so far.

So FWIW:

Tested-by: Mark Rutland <mark.rutland@arm.com>

Thanks,
Mark.

> ---
>  arch/arm/boot/dts/arm-realview-pbx-a9.dts | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> index db808f92dd79..90d00b407f85 100644
> --- a/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> +++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts
> @@ -70,13 +70,12 @@
>  		 * associativity as these may be erroneously set
>  		 * up by boot loader(s).
>  		 */
> -		cache-size = <1048576>; // 1MB
> -		cache-sets = <4096>;
> +		cache-size = <131072>; // 128KB
> +		cache-sets = <512>;
>  		cache-line-size = <32>;
>  		arm,parity-disable;
> -		arm,tag-latency = <1>;
> -		arm,data-latency = <1 1>;
> -		arm,dirty-latency = <1>;
> +		arm,tag-latency = <1 1 1>;
> +		arm,data-latency = <1 1 1>;
>  	};
>  
>  	scu: scu at 1f000000 {
> -- 
> 2.8.1.dirty
> 

Re: [PATCH 1/2] ARM: realview: Fix PBX-A9 cache description

[Linus Walleij]

On Fri, Jul 15, 2016 at 2:19 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:

> Clearly QEMU is very permissive in how its PL310 model may be set up,
> but the real hardware turns out to be far more particular about things
> actually being correct. Fix up the DT description so that the real
> thing actually boots:
>
> - The arm,data-latency and arm,tag-latency properties need 3 cells to
>   be valid, otherwise we end up retaining the default 8-cycle latencies
>   which leads pretty quickly to lockup.
> - The arm,dirty-latency property is only relevant to L210/L220, so get
>   rid of it.
> - The cache geometry override also leads to lockup and/or general
>   misbehaviour. Irritatingly, the manual doesn't state the actual PL310
>   configuration, but based on the boardfile code and poking registers
>   from the Boot Monitor, it would seem to be 8 sets of 16KB ways.
>
> With that, we can successfully boot to enjoy the fun of mismatched FPUs...
>
> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>

Sorry for screwing things up! :(

Patch applied with Rutland's Test tag, I will carry this to ARM SoC as a fix.

Yours,
Linus Walleij
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[PATCH 1/2] ARM: realview: Fix PBX-A9 cache description

[Linus Walleij]

On Fri, Jul 15, 2016 at 2:19 PM, Robin Murphy <robin.murphy@arm.com> wrote:

> Clearly QEMU is very permissive in how its PL310 model may be set up,
> but the real hardware turns out to be far more particular about things
> actually being correct. Fix up the DT description so that the real
> thing actually boots:
>
> - The arm,data-latency and arm,tag-latency properties need 3 cells to
>   be valid, otherwise we end up retaining the default 8-cycle latencies
>   which leads pretty quickly to lockup.
> - The arm,dirty-latency property is only relevant to L210/L220, so get
>   rid of it.
> - The cache geometry override also leads to lockup and/or general
>   misbehaviour. Irritatingly, the manual doesn't state the actual PL310
>   configuration, but based on the boardfile code and poking registers
>   from the Boot Monitor, it would seem to be 8 sets of 16KB ways.
>
> With that, we can successfully boot to enjoy the fun of mismatched FPUs...
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

Sorry for screwing things up! :(

Patch applied with Rutland's Test tag, I will carry this to ARM SoC as a fix.

Yours,
Linus Walleij

Re: [PATCH 2/2] ARM: realview: Extend PBX family memory description

[Linus Walleij]

On Fri, Jul 15, 2016 at 2:19 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:

> All three platforms sharing the later RealView Platform Baseboard memory
> map - PBX-A9, PB-A8 and PB11MPCore, provide 512MB of DDR SDRAM on the
> baseboard, of which the boot alias at 0x0 maps the first 256MB. Expand
> the size of the default memory node to refelect that, and describe the
> full memory regions in each board's DTS, but leave those commented by
> default to avoid breaking existing bootloaders.
>
> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>

I've applied this patch for the next kernel cycle. Tweaked the commit
text a bit (removed spelling mistake and prefixed with dts:).

Yours,
Linus Walleij
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[PATCH 2/2] ARM: realview: Extend PBX family memory description

[Linus Walleij]

On Fri, Jul 15, 2016 at 2:19 PM, Robin Murphy <robin.murphy@arm.com> wrote:

> All three platforms sharing the later RealView Platform Baseboard memory
> map - PBX-A9, PB-A8 and PB11MPCore, provide 512MB of DDR SDRAM on the
> baseboard, of which the boot alias at 0x0 maps the first 256MB. Expand
> the size of the default memory node to refelect that, and describe the
> full memory regions in each board's DTS, but leave those commented by
> default to avoid breaking existing bootloaders.
>
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

I've applied this patch for the next kernel cycle. Tweaked the commit
text a bit (removed spelling mistake and prefixed with dts:).

Yours,
Linus Walleij

Re: [PATCH 2/2] ARM: realview: Extend PBX family memory description

[Robin Murphy]

On 22/07/16 16:06, Linus Walleij wrote:
> On Fri, Jul 15, 2016 at 2:19 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:
> 
>> All three platforms sharing the later RealView Platform Baseboard memory
>> map - PBX-A9, PB-A8 and PB11MPCore, provide 512MB of DDR SDRAM on the
>> baseboard, of which the boot alias at 0x0 maps the first 256MB. Expand
>> the size of the default memory node to refelect that, and describe the
>> full memory regions in each board's DTS, but leave those commented by
>> default to avoid breaking existing bootloaders.
>>
>> Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
> 
> I've applied this patch for the next kernel cycle. Tweaked the commit
> text a bit (removed spelling mistake and prefixed with dts:).

Thanks! (and for the other patch too)

I shall now go away and "refelect" on my carelessness here... ;)

Robin.
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[PATCH 2/2] ARM: realview: Extend PBX family memory description

[Robin Murphy]

On 22/07/16 16:06, Linus Walleij wrote:
> On Fri, Jul 15, 2016 at 2:19 PM, Robin Murphy <robin.murphy@arm.com> wrote:
> 
>> All three platforms sharing the later RealView Platform Baseboard memory
>> map - PBX-A9, PB-A8 and PB11MPCore, provide 512MB of DDR SDRAM on the
>> baseboard, of which the boot alias at 0x0 maps the first 256MB. Expand
>> the size of the default memory node to refelect that, and describe the
>> full memory regions in each board's DTS, but leave those commented by
>> default to avoid breaking existing bootloaders.
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> 
> I've applied this patch for the next kernel cycle. Tweaked the commit
> text a bit (removed spelling mistake and prefixed with dts:).

Thanks! (and for the other patch too)

I shall now go away and "refelect" on my carelessness here... ;)

Robin.