From: Julien Thierry <julien.thierry@arm.com> To: Catalin Marinas <catalin.marinas@arm.com> Cc: linux-arm-kernel@lists.infradead.org, mark.rutland@arm.com, daniel.thompson@linaro.org, marc.zyngier@arm.com, Ard Biesheuvel <ard.biesheuvel@linaro.org>, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, Oleg Nesterov <oleg@redhat.com>, joel@joelfernandes.org Subject: Re: [PATCH v8 12/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Date: Fri, 18 Jan 2019 16:57:32 +0000 [thread overview] Message-ID: <0af2d75e-9a61-e53b-b2df-3d08d3f63d9c@arm.com> (raw) In-Reply-To: <20190118160920.GF118707@arrakis.emea.arm.com> Hi Catalin, On 18/01/2019 16:09, Catalin Marinas wrote: > Hi Julien, > > On Tue, Jan 08, 2019 at 02:07:30PM +0000, Julien Thierry wrote: >> + * Having two ways to control interrupt status is a bit complicated. Some >> + * locations like exception entries will have PSR.I bit set by the architecture >> + * while PMR is unmasked. >> + * We need the irqflags to represent that interrupts are disabled in such cases. >> + * >> + * For this, we lower the value read from PMR when the I bit is set so it is >> + * considered as an irq masking priority. (With PMR, lower value means masking >> + * more interrupts). >> + */ >> +#define _get_irqflags(daif_bits, pmr) \ >> +({ \ >> + unsigned long flags; \ >> + \ >> + BUILD_BUG_ON(GIC_PRIO_IRQOFF < (GIC_PRIO_IRQON & ~PSR_I_BIT)); \ >> + asm volatile(ALTERNATIVE( \ >> + "mov %0, %1\n" \ >> + "nop\n" \ >> + "nop", \ >> + "and %0, %1, #" __stringify(PSR_I_BIT) "\n" \ >> + "mvn %0, %0\n" \ >> + "and %0, %0, %2", \ >> + ARM64_HAS_IRQ_PRIO_MASKING) \ > > Can you write the last two instructions as a single: > > bic %0, %2, %0 Yes, makes sense. Although we won't need it anymore with your suggestion below. > >> + : "=&r" (flags) \ >> + : "r" (daif_bits), "r" (pmr) \ >> + : "memory"); \ >> + \ >> + flags; \ >> +}) >> + >> +/* >> * Save the current interrupt enable state. >> */ >> static inline unsigned long arch_local_save_flags(void) >> { >> - unsigned long flags; >> - asm volatile( >> - "mrs %0, daif // arch_local_save_flags" >> - : "=r" (flags) >> + unsigned long daif_bits; >> + unsigned long pmr; // Only used if alternative is on >> + >> + daif_bits = read_sysreg(daif); >> + >> + // Get PMR > > Nitpick: don't use C++ (or arm asm) comment style in C code. Noted. > >> + asm volatile(ALTERNATIVE( >> + "nop", >> + "mrs_s %0, " __stringify(SYS_ICC_PMR_EL1), >> + ARM64_HAS_IRQ_PRIO_MASKING) >> + : "=&r" (pmr) >> : >> : "memory"); >> + >> + return _get_irqflags(daif_bits, pmr); >> +} > > I find this confusing spread over two inline asm statements. IIUC, you > want something like below (it could be written as inline asm but I need > to understand it first): > > daif_bits = read_sysreg(daif); > > if (system_uses_irq_prio_masking()) { > pmr = read_gicreg(ICC_PMR_EL1); > flags = pmr & ~(daif_bits & PSR_I_BIT); > } else { > flags = daif_bits; > } > > return flags; > > In the case where the interrupts are disabled at the PSR level, is the > PMR value still relevant? Could we just return the GIC_PRIO_IRQOFF? > Something like: > > flags = read_sysreg(daif); > > if (system_uses_irq_prio_masking()) > flags = flags & PSR_I_BIT ? > GIC_PRIO_IRQOFF : read_gicreg(ICC_PMR_EL1); > You're right, returning GIC_PRIO_IRQOFF should be good enough (it is actually what happens in this version because GIC_PRIO_IRQOFF == GIC_PRIO_IRQON & ~PSR_I_BIT happens to be true). Your suggestion would make things easier to reason about. Maybe something like: static inline unsigned long arch_local_save_flags(void) { unsigned long daif_bits; unsigned long prio_off = GIC_PRIO_IRQOFF; daif_bits = read_sysreg(daif); asm volatile(ALTERNATIVE( "mov %0, %1\n" "nop\n" "nop", "mrs %0, SYS_ICC_PMR_EL1\n" "ands %1, %1, PSR_I_BIT\n" "csel %0, %0, %2, eq") : "=&r" (flags) : "r" (daif_bits), "r" (prio_off) : "memory"); return flags; } (Looks like it removes one nop from the alternative as well, unless I messed up something) Does that seem better to you? Thanks, -- Julien Thierry
WARNING: multiple messages have this Message-ID (diff)
From: Julien Thierry <julien.thierry@arm.com> To: Catalin Marinas <catalin.marinas@arm.com> Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, Ard Biesheuvel <ard.biesheuvel@linaro.org>, marc.zyngier@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, christoffer.dall@arm.com, james.morse@arm.com, Oleg Nesterov <oleg@redhat.com>, joel@joelfernandes.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v8 12/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Date: Fri, 18 Jan 2019 16:57:32 +0000 [thread overview] Message-ID: <0af2d75e-9a61-e53b-b2df-3d08d3f63d9c@arm.com> (raw) In-Reply-To: <20190118160920.GF118707@arrakis.emea.arm.com> Hi Catalin, On 18/01/2019 16:09, Catalin Marinas wrote: > Hi Julien, > > On Tue, Jan 08, 2019 at 02:07:30PM +0000, Julien Thierry wrote: >> + * Having two ways to control interrupt status is a bit complicated. Some >> + * locations like exception entries will have PSR.I bit set by the architecture >> + * while PMR is unmasked. >> + * We need the irqflags to represent that interrupts are disabled in such cases. >> + * >> + * For this, we lower the value read from PMR when the I bit is set so it is >> + * considered as an irq masking priority. (With PMR, lower value means masking >> + * more interrupts). >> + */ >> +#define _get_irqflags(daif_bits, pmr) \ >> +({ \ >> + unsigned long flags; \ >> + \ >> + BUILD_BUG_ON(GIC_PRIO_IRQOFF < (GIC_PRIO_IRQON & ~PSR_I_BIT)); \ >> + asm volatile(ALTERNATIVE( \ >> + "mov %0, %1\n" \ >> + "nop\n" \ >> + "nop", \ >> + "and %0, %1, #" __stringify(PSR_I_BIT) "\n" \ >> + "mvn %0, %0\n" \ >> + "and %0, %0, %2", \ >> + ARM64_HAS_IRQ_PRIO_MASKING) \ > > Can you write the last two instructions as a single: > > bic %0, %2, %0 Yes, makes sense. Although we won't need it anymore with your suggestion below. > >> + : "=&r" (flags) \ >> + : "r" (daif_bits), "r" (pmr) \ >> + : "memory"); \ >> + \ >> + flags; \ >> +}) >> + >> +/* >> * Save the current interrupt enable state. >> */ >> static inline unsigned long arch_local_save_flags(void) >> { >> - unsigned long flags; >> - asm volatile( >> - "mrs %0, daif // arch_local_save_flags" >> - : "=r" (flags) >> + unsigned long daif_bits; >> + unsigned long pmr; // Only used if alternative is on >> + >> + daif_bits = read_sysreg(daif); >> + >> + // Get PMR > > Nitpick: don't use C++ (or arm asm) comment style in C code. Noted. > >> + asm volatile(ALTERNATIVE( >> + "nop", >> + "mrs_s %0, " __stringify(SYS_ICC_PMR_EL1), >> + ARM64_HAS_IRQ_PRIO_MASKING) >> + : "=&r" (pmr) >> : >> : "memory"); >> + >> + return _get_irqflags(daif_bits, pmr); >> +} > > I find this confusing spread over two inline asm statements. IIUC, you > want something like below (it could be written as inline asm but I need > to understand it first): > > daif_bits = read_sysreg(daif); > > if (system_uses_irq_prio_masking()) { > pmr = read_gicreg(ICC_PMR_EL1); > flags = pmr & ~(daif_bits & PSR_I_BIT); > } else { > flags = daif_bits; > } > > return flags; > > In the case where the interrupts are disabled at the PSR level, is the > PMR value still relevant? Could we just return the GIC_PRIO_IRQOFF? > Something like: > > flags = read_sysreg(daif); > > if (system_uses_irq_prio_masking()) > flags = flags & PSR_I_BIT ? > GIC_PRIO_IRQOFF : read_gicreg(ICC_PMR_EL1); > You're right, returning GIC_PRIO_IRQOFF should be good enough (it is actually what happens in this version because GIC_PRIO_IRQOFF == GIC_PRIO_IRQON & ~PSR_I_BIT happens to be true). Your suggestion would make things easier to reason about. Maybe something like: static inline unsigned long arch_local_save_flags(void) { unsigned long daif_bits; unsigned long prio_off = GIC_PRIO_IRQOFF; daif_bits = read_sysreg(daif); asm volatile(ALTERNATIVE( "mov %0, %1\n" "nop\n" "nop", "mrs %0, SYS_ICC_PMR_EL1\n" "ands %1, %1, PSR_I_BIT\n" "csel %0, %0, %2, eq") : "=&r" (flags) : "r" (daif_bits), "r" (prio_off) : "memory"); return flags; } (Looks like it removes one nop from the alternative as well, unless I messed up something) Does that seem better to you? Thanks, -- Julien Thierry _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-01-18 16:57 UTC|newest] Thread overview: 117+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-01-08 14:07 [PATCH v8 00/26] arm64: provide pseudo NMI with GICv3 Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 01/26] arm64: Fix HCR.TGE status for NMI contexts Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-14 15:56 ` Catalin Marinas 2019-01-14 15:56 ` Catalin Marinas 2019-01-14 16:12 ` Julien Thierry 2019-01-14 16:12 ` Julien Thierry 2019-01-14 17:25 ` James Morse 2019-01-14 17:25 ` James Morse 2019-01-16 13:35 ` Sasha Levin 2019-01-16 13:35 ` Sasha Levin 2019-01-28 9:16 ` Marc Zyngier 2019-01-28 9:16 ` Marc Zyngier 2019-01-28 9:16 ` Marc Zyngier 2019-01-08 14:07 ` [PATCH v8 02/26] arm64: Remove unused daif related functions/macros Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 03/26] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 04/26] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 05/26] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 06/26] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 07/26] arm64: ptrace: Provide definitions for PMR values Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-14 16:12 ` Catalin Marinas 2019-01-14 16:12 ` Catalin Marinas 2019-01-08 14:07 ` [PATCH v8 08/26] arm64: Make PMR part of task context Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-18 16:10 ` Catalin Marinas 2019-01-18 16:10 ` Catalin Marinas 2019-01-08 14:07 ` [PATCH v8 09/26] arm64: Unmask PMR before going idle Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-18 16:23 ` Catalin Marinas 2019-01-18 16:23 ` Catalin Marinas 2019-01-18 17:17 ` Julien Thierry 2019-01-18 17:17 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 10/26] arm64: kvm: Unmask PMR before entering guest Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-18 16:25 ` Catalin Marinas 2019-01-18 16:25 ` Catalin Marinas 2019-01-08 14:07 ` [PATCH v8 11/26] efi: Let architectures decide the flags that should be saved/restored Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-18 16:26 ` Catalin Marinas 2019-01-18 16:26 ` Catalin Marinas 2019-01-08 14:07 ` [PATCH v8 12/26] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 15:40 ` Dave Martin 2019-01-08 15:40 ` Dave Martin 2019-01-08 15:51 ` Marc Zyngier 2019-01-08 15:51 ` Marc Zyngier 2019-01-08 16:45 ` Dave Martin 2019-01-08 16:45 ` Dave Martin 2019-01-08 17:16 ` Marc Zyngier 2019-01-08 17:16 ` Marc Zyngier 2019-01-08 18:01 ` Dave Martin 2019-01-08 18:01 ` Dave Martin 2019-01-08 17:58 ` Julien Thierry 2019-01-08 17:58 ` Julien Thierry 2019-01-08 18:37 ` Dave Martin 2019-01-08 18:37 ` Dave Martin 2019-01-18 16:09 ` Catalin Marinas 2019-01-18 16:09 ` Catalin Marinas 2019-01-18 16:57 ` Julien Thierry [this message] 2019-01-18 16:57 ` Julien Thierry 2019-01-18 17:30 ` Catalin Marinas 2019-01-18 17:30 ` Catalin Marinas 2019-01-18 17:33 ` Catalin Marinas 2019-01-18 17:33 ` Catalin Marinas 2019-01-21 8:45 ` Julien Thierry 2019-01-21 8:45 ` Julien Thierry 2019-01-18 16:35 ` Dave Martin 2019-01-18 16:35 ` Dave Martin 2019-01-18 17:27 ` Julien Thierry 2019-01-18 17:27 ` Julien Thierry 2019-01-18 18:23 ` Dave Martin 2019-01-18 18:23 ` Dave Martin 2019-01-08 14:07 ` [PATCH v8 13/26] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-18 16:43 ` Catalin Marinas 2019-01-18 16:43 ` Catalin Marinas 2019-01-08 14:07 ` [PATCH v8 14/26] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 15/26] arm64: alternative: Apply alternatives early in boot process Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:51 ` Suzuki K Poulose 2019-01-08 14:51 ` Suzuki K Poulose 2019-01-08 15:20 ` Julien Thierry 2019-01-08 15:20 ` Julien Thierry 2019-01-08 17:40 ` Suzuki K Poulose 2019-01-08 17:40 ` Suzuki K Poulose 2019-01-10 10:50 ` Julien Thierry 2019-01-10 10:50 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 16/26] irqchip/gic-v3: Factor group0 detection into functions Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 17/26] arm64: Switch to PMR masking when starting CPUs Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 18/26] arm64: gic-v3: Implement arch support for priority masking Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 19/26] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 20/26] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 21/26] irqchip/gic: Add functions to access irq priorities Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 22/26] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 23/26] arm64: Handle serror in NMI context Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 24/26] arm64: Skip preemption when exiting an NMI Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 25/26] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry 2019-01-08 14:07 ` Julien Thierry 2019-01-08 14:07 ` [PATCH v8 26/26] arm64: Enable the support of pseudo-NMIs Julien Thierry 2019-01-08 14:07 ` Julien Thierry
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