* [PATCH 1/2] util/log: Add vu to dump content of vector unit
@ 2022-07-08 8:57 Kito Cheng
2022-07-08 8:57 ` [PATCH 2/2] target/riscv: Implement dump content of vector register Kito Cheng
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Kito Cheng @ 2022-07-08 8:57 UTC (permalink / raw)
To: alistair.francis, palmer, frank.chang, qemu-devel, qemu-riscv,
liweiwei, richard.henderson
Cc: Kito Cheng
Add new option for -d vu to dump the content of vector unit, many target
has vector register, but there is no easy way to dump the content, we
use this on downstream for a while to help debug, and I feel that's
really useful, so I think it would be great to upstream that to save debug time
for other people :)
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
accel/tcg/cpu-exec.c | 3 +++
include/hw/core/cpu.h | 2 ++
include/qemu/log.h | 1 +
util/log.c | 2 ++
4 files changed, 8 insertions(+)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index a565a3f8ec..2cbec0a6ed 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -221,6 +221,9 @@ static inline void log_cpu_exec(target_ulong pc, CPUState *cpu,
if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
flags |= CPU_DUMP_FPU;
}
+ if (qemu_loglevel_mask(CPU_LOG_TB_VU)) {
+ flags |= CPU_DUMP_VU;
+ }
#if defined(TARGET_I386)
flags |= CPU_DUMP_CCOP;
#endif
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 996f94059f..7a767e17cd 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -535,11 +535,13 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
* @CPU_DUMP_CODE:
* @CPU_DUMP_FPU: dump FPU register state, not just integer
* @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
+ * @CPU_DUMP_VU: dump vector register state
*/
enum CPUDumpFlags {
CPU_DUMP_CODE = 0x00010000,
CPU_DUMP_FPU = 0x00020000,
CPU_DUMP_CCOP = 0x00040000,
+ CPU_DUMP_VU = 0x00080000,
};
/**
diff --git a/include/qemu/log.h b/include/qemu/log.h
index c5643d8dd5..49bd0b0fbc 100644
--- a/include/qemu/log.h
+++ b/include/qemu/log.h
@@ -35,6 +35,7 @@ bool qemu_log_separate(void);
/* LOG_STRACE is used for user-mode strace logging. */
#define LOG_STRACE (1 << 19)
#define LOG_PER_THREAD (1 << 20)
+#define CPU_LOG_TB_VU (1 << 21)
/* Lock/unlock output. */
diff --git a/util/log.c b/util/log.c
index d6eb0378c3..775d122c2e 100644
--- a/util/log.c
+++ b/util/log.c
@@ -441,6 +441,8 @@ const QEMULogItem qemu_log_items[] = {
#ifdef CONFIG_PLUGIN
{ CPU_LOG_PLUGIN, "plugin", "output from TCG plugins\n"},
#endif
+ { CPU_LOG_TB_VU, "vu",
+ "include vector unit registers in the 'cpu' logging" },
{ LOG_STRACE, "strace",
"log every user-mode syscall, its input, and its result" },
{ LOG_PER_THREAD, "tid",
--
2.34.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] target/riscv: Implement dump content of vector register
2022-07-08 8:57 [PATCH 1/2] util/log: Add vu to dump content of vector unit Kito Cheng
@ 2022-07-08 8:57 ` Kito Cheng
2022-07-09 9:09 ` Weiwei Li
2022-07-11 8:15 ` [PATCH 1/2] util/log: Add vu to dump content of vector unit Frank Chang
2022-07-11 11:53 ` Víctor Colombo
2 siblings, 1 reply; 5+ messages in thread
From: Kito Cheng @ 2022-07-08 8:57 UTC (permalink / raw)
To: alistair.francis, palmer, frank.chang, qemu-devel, qemu-riscv,
liweiwei, richard.henderson
Cc: Kito Cheng
Implement -d cpu,vu to dump content of vector register.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c1b96da7da..97b289d277 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -72,6 +72,15 @@ const char * const riscv_fpr_regnames[] = {
"f30/ft10", "f31/ft11"
};
+const char * const riscv_vr_regnames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5",
+ "v6", "v7", "v8", "v9", "v10", "v11",
+ "v12", "v13", "v14", "v15", "v16", "v17",
+ "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "v29",
+ "v30", "v31"
+};
+
static const char * const riscv_excp_names[] = {
"misaligned_fetch",
"fault_fetch",
@@ -375,6 +384,28 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
}
+ if (flags & CPU_DUMP_VU) {
+ int vlen = cpu->cfg.vlen;
+ int n_chunk = vlen / 64;
+ if (vlen == 32) {
+ for (i = 0; i < 32; i++) {
+ qemu_fprintf(f, "0x%08" PRIx64 "\n", env->vreg[i]);
+ }
+ } else {
+ for (i = 0; i < 32; i++) {
+ qemu_fprintf(f, " %-8s ",
+ riscv_vr_regnames[i]);
+
+ int vec_reg_offset = i * vlen / 64;
+ qemu_fprintf(f, "0x");
+ for (int j = n_chunk - 1; j >= 0; --j) {
+ qemu_fprintf(f, "%016" PRIx64,
+ env->vreg[vec_reg_offset + j]);
+ }
+ qemu_fprintf(f, "\n");
+ }
+ }
+ }
}
static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
--
2.34.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] target/riscv: Implement dump content of vector register
2022-07-08 8:57 ` [PATCH 2/2] target/riscv: Implement dump content of vector register Kito Cheng
@ 2022-07-09 9:09 ` Weiwei Li
0 siblings, 0 replies; 5+ messages in thread
From: Weiwei Li @ 2022-07-09 9:09 UTC (permalink / raw)
To: Kito Cheng, alistair.francis, palmer, frank.chang, qemu-devel,
qemu-riscv, liweiwei, richard.henderson
在 2022/7/8 下午4:57, Kito Cheng 写道:
> Implement -d cpu,vu to dump content of vector register.
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c1b96da7da..97b289d277 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -72,6 +72,15 @@ const char * const riscv_fpr_regnames[] = {
> "f30/ft10", "f31/ft11"
> };
>
> +const char * const riscv_vr_regnames[] = {
> + "v0", "v1", "v2", "v3", "v4", "v5",
> + "v6", "v7", "v8", "v9", "v10", "v11",
> + "v12", "v13", "v14", "v15", "v16", "v17",
> + "v18", "v19", "v20", "v21", "v22", "v23",
> + "v24", "v25", "v26", "v27", "v28", "v29",
> + "v30", "v31"
> +};
> +
> static const char * const riscv_excp_names[] = {
> "misaligned_fetch",
> "fault_fetch",
> @@ -375,6 +384,28 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> }
> }
> }
> + if (flags & CPU_DUMP_VU) {
> + int vlen = cpu->cfg.vlen;
> + int n_chunk = vlen / 64;
> + if (vlen == 32) {
> + for (i = 0; i < 32; i++) {
> + qemu_fprintf(f, "0x%08" PRIx64 "\n", env->vreg[i]);
> + }
Seems forget to dump the riscv_vr_regnames here.
Just another question: whether is it necessary to dump the vector
related csrs too?
Regards,
Weiwei Li
> + } else {
> + for (i = 0; i < 32; i++) {
> + qemu_fprintf(f, " %-8s ",
> + riscv_vr_regnames[i]);
> +
> + int vec_reg_offset = i * vlen / 64;
> + qemu_fprintf(f, "0x");
> + for (int j = n_chunk - 1; j >= 0; --j) {
> + qemu_fprintf(f, "%016" PRIx64,
> + env->vreg[vec_reg_offset + j]);
> + }
> + qemu_fprintf(f, "\n");
> + }
> + }
> + }
> }
>
> static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] util/log: Add vu to dump content of vector unit
2022-07-08 8:57 [PATCH 1/2] util/log: Add vu to dump content of vector unit Kito Cheng
2022-07-08 8:57 ` [PATCH 2/2] target/riscv: Implement dump content of vector register Kito Cheng
@ 2022-07-11 8:15 ` Frank Chang
2022-07-11 11:53 ` Víctor Colombo
2 siblings, 0 replies; 5+ messages in thread
From: Frank Chang @ 2022-07-11 8:15 UTC (permalink / raw)
To: Kito Cheng
Cc: alistair.francis, palmer, qemu-devel, qemu-riscv, liweiwei,
richard.henderson
[-- Attachment #1: Type: text/plain, Size: 2824 bytes --]
On Fri, Jul 8, 2022 at 4:57 PM Kito Cheng <kito.cheng@sifive.com> wrote:
> Add new option for -d vu to dump the content of vector unit, many target
> has vector register, but there is no easy way to dump the content, we
> use this on downstream for a while to help debug, and I feel that's
> really useful, so I think it would be great to upstream that to save debug
> time
> for other people :)
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> accel/tcg/cpu-exec.c | 3 +++
> include/hw/core/cpu.h | 2 ++
> include/qemu/log.h | 1 +
> util/log.c | 2 ++
> 4 files changed, 8 insertions(+)
>
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index a565a3f8ec..2cbec0a6ed 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -221,6 +221,9 @@ static inline void log_cpu_exec(target_ulong pc,
> CPUState *cpu,
> if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
> flags |= CPU_DUMP_FPU;
> }
> + if (qemu_loglevel_mask(CPU_LOG_TB_VU)) {
> + flags |= CPU_DUMP_VU;
> + }
> #if defined(TARGET_I386)
> flags |= CPU_DUMP_CCOP;
> #endif
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 996f94059f..7a767e17cd 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -535,11 +535,13 @@ GuestPanicInformation *cpu_get_crash_info(CPUState
> *cpu);
> * @CPU_DUMP_CODE:
> * @CPU_DUMP_FPU: dump FPU register state, not just integer
> * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization
> state
> + * @CPU_DUMP_VU: dump vector register state
> */
> enum CPUDumpFlags {
> CPU_DUMP_CODE = 0x00010000,
> CPU_DUMP_FPU = 0x00020000,
> CPU_DUMP_CCOP = 0x00040000,
> + CPU_DUMP_VU = 0x00080000,
> };
>
> /**
> diff --git a/include/qemu/log.h b/include/qemu/log.h
> index c5643d8dd5..49bd0b0fbc 100644
> --- a/include/qemu/log.h
> +++ b/include/qemu/log.h
> @@ -35,6 +35,7 @@ bool qemu_log_separate(void);
> /* LOG_STRACE is used for user-mode strace logging. */
> #define LOG_STRACE (1 << 19)
> #define LOG_PER_THREAD (1 << 20)
> +#define CPU_LOG_TB_VU (1 << 21)
>
> /* Lock/unlock output. */
>
> diff --git a/util/log.c b/util/log.c
> index d6eb0378c3..775d122c2e 100644
> --- a/util/log.c
> +++ b/util/log.c
> @@ -441,6 +441,8 @@ const QEMULogItem qemu_log_items[] = {
> #ifdef CONFIG_PLUGIN
> { CPU_LOG_PLUGIN, "plugin", "output from TCG plugins\n"},
> #endif
> + { CPU_LOG_TB_VU, "vu",
> + "include vector unit registers in the 'cpu' logging" },
> { LOG_STRACE, "strace",
> "log every user-mode syscall, its input, and its result" },
> { LOG_PER_THREAD, "tid",
> --
> 2.34.0
>
>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
[-- Attachment #2: Type: text/html, Size: 3694 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] util/log: Add vu to dump content of vector unit
2022-07-08 8:57 [PATCH 1/2] util/log: Add vu to dump content of vector unit Kito Cheng
2022-07-08 8:57 ` [PATCH 2/2] target/riscv: Implement dump content of vector register Kito Cheng
2022-07-11 8:15 ` [PATCH 1/2] util/log: Add vu to dump content of vector unit Frank Chang
@ 2022-07-11 11:53 ` Víctor Colombo
2 siblings, 0 replies; 5+ messages in thread
From: Víctor Colombo @ 2022-07-11 11:53 UTC (permalink / raw)
To: Kito Cheng, alistair.francis, palmer, frank.chang, qemu-devel,
qemu-riscv, liweiwei, richard.henderson
On 08/07/2022 05:57, Kito Cheng wrote:
> Add new option for -d vu to dump the content of vector unit, many target
> has vector register, but there is no easy way to dump the content, we
> use this on downstream for a while to help debug, and I feel that's
> really useful, so I think it would be great to upstream that to save debug time
> for other people :)
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> accel/tcg/cpu-exec.c | 3 +++
> include/hw/core/cpu.h | 2 ++
> include/qemu/log.h | 1 +
> util/log.c | 2 ++
> 4 files changed, 8 insertions(+)
>
> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
> index a565a3f8ec..2cbec0a6ed 100644
> --- a/accel/tcg/cpu-exec.c
> +++ b/accel/tcg/cpu-exec.c
> @@ -221,6 +221,9 @@ static inline void log_cpu_exec(target_ulong pc, CPUState *cpu,
> if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
> flags |= CPU_DUMP_FPU;
> }
> + if (qemu_loglevel_mask(CPU_LOG_TB_VU)) {
> + flags |= CPU_DUMP_VU;
> + }
> #if defined(TARGET_I386)
> flags |= CPU_DUMP_CCOP;
> #endif
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 996f94059f..7a767e17cd 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -535,11 +535,13 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu);
> * @CPU_DUMP_CODE:
> * @CPU_DUMP_FPU: dump FPU register state, not just integer
> * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
> + * @CPU_DUMP_VU: dump vector register state
> */
> enum CPUDumpFlags {
> CPU_DUMP_CODE = 0x00010000,
> CPU_DUMP_FPU = 0x00020000,
> CPU_DUMP_CCOP = 0x00040000,
> + CPU_DUMP_VU = 0x00080000,
> };
>
> /**
> diff --git a/include/qemu/log.h b/include/qemu/log.h
> index c5643d8dd5..49bd0b0fbc 100644
> --- a/include/qemu/log.h
> +++ b/include/qemu/log.h
> @@ -35,6 +35,7 @@ bool qemu_log_separate(void);
> /* LOG_STRACE is used for user-mode strace logging. */
> #define LOG_STRACE (1 << 19)
> #define LOG_PER_THREAD (1 << 20)
> +#define CPU_LOG_TB_VU (1 << 21)
>
> /* Lock/unlock output. */
>
> diff --git a/util/log.c b/util/log.c
> index d6eb0378c3..775d122c2e 100644
> --- a/util/log.c
> +++ b/util/log.c
> @@ -441,6 +441,8 @@ const QEMULogItem qemu_log_items[] = {
> #ifdef CONFIG_PLUGIN
> { CPU_LOG_PLUGIN, "plugin", "output from TCG plugins\n"},
> #endif
> + { CPU_LOG_TB_VU, "vu",
> + "include vector unit registers in the 'cpu' logging" },
> { LOG_STRACE, "strace",
> "log every user-mode syscall, its input, and its result" },
> { LOG_PER_THREAD, "tid",
> --
> 2.34.0
>
>
I think this looks like a good idea, can see myself using it.
I see a lot of places in the code where cpu_dump_state() is
used with CPU_DUMP_FPU flag as a parameter. Do you think it
is also the case to add this new flag CPU_DUMP_VU there too?
Best regards,
--
Víctor Cora Colombo
Instituto de Pesquisas ELDORADO
Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
^ permalink raw reply [flat|nested] 5+ messages in thread
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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-08 8:57 [PATCH 1/2] util/log: Add vu to dump content of vector unit Kito Cheng
2022-07-08 8:57 ` [PATCH 2/2] target/riscv: Implement dump content of vector register Kito Cheng
2022-07-09 9:09 ` Weiwei Li
2022-07-11 8:15 ` [PATCH 1/2] util/log: Add vu to dump content of vector unit Frank Chang
2022-07-11 11:53 ` Víctor Colombo
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