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From: Juergen Gross <jgross@suse.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Andy Lutomirski <luto@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	xen-devel@lists.xenproject.org, x86@kernel.org,
	linux-kernel@vger.kernel.org, intel-gfx@lists.freedesktop.org,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 2/2] x86/pat: add functions to query specific cache mode availability
Date: Wed, 4 May 2022 11:14:03 +0200	[thread overview]
Message-ID: <0dcb05d0-108f-6252-e768-f75b393a7f5c@suse.com> (raw)
In-Reply-To: <1d86d8ff-6878-5488-e8c4-cbe8a5e8f624@suse.com>


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On 04.05.22 10:31, Jan Beulich wrote:
> On 03.05.2022 15:22, Juergen Gross wrote:
>> Some drivers are using pat_enabled() in order to test availability of
>> special caching modes (WC and UC-). This will lead to false negatives
>> in case the system was booted e.g. with the "nopat" variant and the
>> BIOS did setup the PAT MSR supporting the queried mode, or if the
>> system is running as a Xen PV guest.
> 
> While, as per my earlier patch, I agree with the Xen PV case, I'm not
> convinced "nopat" is supposed to honor firmware-provided settings. In
> fact in my patch I did arrange for "nopat" to also take effect under
> Xen PV.

Depends on what the wanted semantics for "nopat" are.

Right now "nopat" will result in the PAT MSR left unchanged and the
cache mode translation tables be initialized accordingly.

So does "nopat" mean that the PAT MSR shouldn't be changed, or that
PAGE_BIT_PAT will never be set?

>> Add test functions for those caching modes instead and use them at the
>> appropriate places.
>>
>> For symmetry reasons export the already existing x86_has_pat_wp() for
>> modules, too.
>>
>> Fixes: bdd8b6c98239 ("drm/i915: replace X86_FEATURE_PAT with pat_enabled()")
>> Fixes: ae749c7ab475 ("PCI: Add arch_can_pci_mmap_wc() macro")
>> Signed-off-by: Juergen Gross <jgross@suse.com>
> 
> I think this wants a Reported-by as well.

Okay.

> 
>> --- a/arch/x86/include/asm/pci.h
>> +++ b/arch/x86/include/asm/pci.h
>> @@ -94,7 +94,7 @@ int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
>>   
>>   
>>   #define HAVE_PCI_MMAP
>> -#define arch_can_pci_mmap_wc()	pat_enabled()
>> +#define arch_can_pci_mmap_wc()	x86_has_pat_wc()
> 
> Besides this and ...
> 
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>> @@ -76,7 +76,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
>>   	if (args->flags & ~(I915_MMAP_WC))
>>   		return -EINVAL;
>>   
>> -	if (args->flags & I915_MMAP_WC && !pat_enabled())
>> +	if (args->flags & I915_MMAP_WC && !x86_has_pat_wc())
>>   		return -ENODEV;
>>   
>>   	obj = i915_gem_object_lookup(file, args->handle);
>> @@ -757,7 +757,7 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
>>   
>>   	if (HAS_LMEM(to_i915(dev)))
>>   		mmap_type = I915_MMAP_TYPE_FIXED;
>> -	else if (pat_enabled())
>> +	else if (x86_has_pat_wc())
>>   		mmap_type = I915_MMAP_TYPE_WC;
>>   	else if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
>>   		return -ENODEV;
>> @@ -813,7 +813,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
>>   		break;
>>   
>>   	case I915_MMAP_OFFSET_WC:
>> -		if (!pat_enabled())
>> +		if (!x86_has_pat_wc())
>>   			return -ENODEV;
>>   		type = I915_MMAP_TYPE_WC;
>>   		break;
>> @@ -823,7 +823,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
>>   		break;
>>   
>>   	case I915_MMAP_OFFSET_UC:
>> -		if (!pat_enabled())
>> +		if (!x86_has_pat_uc_minus())
>>   			return -ENODEV;
>>   		type = I915_MMAP_TYPE_UC;
>>   		break;
> 
> ... these uses there are several more. You say nothing on why those want
> leaving unaltered. When preparing my earlier patch I did inspect them
> and came to the conclusion that these all would also better observe the
> adjusted behavior (or else I couldn't have left pat_enabled() as the only
> predicate). In fact, as said in the description of my earlier patch, in
> my debugging I did find the use in i915_gem_object_pin_map() to be the
> problematic one, which you leave alone.

Oh, I missed that one, sorry.

I wanted to be rather defensive in my changes, but I agree at least the
case in arch_phys_wc_add() might want to be changed, too.

kvm_is_mmio_pfn() should not really matter at least for the Xen case.

With the other use cases in memtype.c I'm rather on the edge.

In case the x86 maintainers think those should be changed, too, I agree
that your approach might be the better one.


Juergen

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WARNING: multiple messages have this Message-ID (diff)
From: Juergen Gross <jgross@suse.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	intel-gfx@lists.freedesktop.org,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org,
	David Airlie <airlied@linux.ie>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	dri-devel@lists.freedesktop.org,
	Andy Lutomirski <luto@kernel.org>,
	"H. Peter Anvin" <hpa@zytor.com>,
	xen-devel@lists.xenproject.org,
	Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH 2/2] x86/pat: add functions to query specific cache mode availability
Date: Wed, 4 May 2022 11:14:03 +0200	[thread overview]
Message-ID: <0dcb05d0-108f-6252-e768-f75b393a7f5c@suse.com> (raw)
In-Reply-To: <1d86d8ff-6878-5488-e8c4-cbe8a5e8f624@suse.com>


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On 04.05.22 10:31, Jan Beulich wrote:
> On 03.05.2022 15:22, Juergen Gross wrote:
>> Some drivers are using pat_enabled() in order to test availability of
>> special caching modes (WC and UC-). This will lead to false negatives
>> in case the system was booted e.g. with the "nopat" variant and the
>> BIOS did setup the PAT MSR supporting the queried mode, or if the
>> system is running as a Xen PV guest.
> 
> While, as per my earlier patch, I agree with the Xen PV case, I'm not
> convinced "nopat" is supposed to honor firmware-provided settings. In
> fact in my patch I did arrange for "nopat" to also take effect under
> Xen PV.

Depends on what the wanted semantics for "nopat" are.

Right now "nopat" will result in the PAT MSR left unchanged and the
cache mode translation tables be initialized accordingly.

So does "nopat" mean that the PAT MSR shouldn't be changed, or that
PAGE_BIT_PAT will never be set?

>> Add test functions for those caching modes instead and use them at the
>> appropriate places.
>>
>> For symmetry reasons export the already existing x86_has_pat_wp() for
>> modules, too.
>>
>> Fixes: bdd8b6c98239 ("drm/i915: replace X86_FEATURE_PAT with pat_enabled()")
>> Fixes: ae749c7ab475 ("PCI: Add arch_can_pci_mmap_wc() macro")
>> Signed-off-by: Juergen Gross <jgross@suse.com>
> 
> I think this wants a Reported-by as well.

Okay.

> 
>> --- a/arch/x86/include/asm/pci.h
>> +++ b/arch/x86/include/asm/pci.h
>> @@ -94,7 +94,7 @@ int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
>>   
>>   
>>   #define HAVE_PCI_MMAP
>> -#define arch_can_pci_mmap_wc()	pat_enabled()
>> +#define arch_can_pci_mmap_wc()	x86_has_pat_wc()
> 
> Besides this and ...
> 
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>> @@ -76,7 +76,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
>>   	if (args->flags & ~(I915_MMAP_WC))
>>   		return -EINVAL;
>>   
>> -	if (args->flags & I915_MMAP_WC && !pat_enabled())
>> +	if (args->flags & I915_MMAP_WC && !x86_has_pat_wc())
>>   		return -ENODEV;
>>   
>>   	obj = i915_gem_object_lookup(file, args->handle);
>> @@ -757,7 +757,7 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
>>   
>>   	if (HAS_LMEM(to_i915(dev)))
>>   		mmap_type = I915_MMAP_TYPE_FIXED;
>> -	else if (pat_enabled())
>> +	else if (x86_has_pat_wc())
>>   		mmap_type = I915_MMAP_TYPE_WC;
>>   	else if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
>>   		return -ENODEV;
>> @@ -813,7 +813,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
>>   		break;
>>   
>>   	case I915_MMAP_OFFSET_WC:
>> -		if (!pat_enabled())
>> +		if (!x86_has_pat_wc())
>>   			return -ENODEV;
>>   		type = I915_MMAP_TYPE_WC;
>>   		break;
>> @@ -823,7 +823,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
>>   		break;
>>   
>>   	case I915_MMAP_OFFSET_UC:
>> -		if (!pat_enabled())
>> +		if (!x86_has_pat_uc_minus())
>>   			return -ENODEV;
>>   		type = I915_MMAP_TYPE_UC;
>>   		break;
> 
> ... these uses there are several more. You say nothing on why those want
> leaving unaltered. When preparing my earlier patch I did inspect them
> and came to the conclusion that these all would also better observe the
> adjusted behavior (or else I couldn't have left pat_enabled() as the only
> predicate). In fact, as said in the description of my earlier patch, in
> my debugging I did find the use in i915_gem_object_pin_map() to be the
> problematic one, which you leave alone.

Oh, I missed that one, sorry.

I wanted to be rather defensive in my changes, but I agree at least the
case in arch_phys_wc_add() might want to be changed, too.

kvm_is_mmio_pfn() should not really matter at least for the Xen case.

With the other use cases in memtype.c I'm rather on the edge.

In case the x86 maintainers think those should be changed, too, I agree
that your approach might be the better one.


Juergen

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WARNING: multiple messages have this Message-ID (diff)
From: Juergen Gross <jgross@suse.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
	intel-gfx@lists.freedesktop.org,
	Dave Hansen <dave.hansen@linux.intel.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org,
	David Airlie <airlied@linux.ie>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	dri-devel@lists.freedesktop.org,
	Andy Lutomirski <luto@kernel.org>,
	"H. Peter Anvin" <hpa@zytor.com>,
	xen-devel@lists.xenproject.org,
	Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [Intel-gfx] [PATCH 2/2] x86/pat: add functions to query specific cache mode availability
Date: Wed, 4 May 2022 11:14:03 +0200	[thread overview]
Message-ID: <0dcb05d0-108f-6252-e768-f75b393a7f5c@suse.com> (raw)
In-Reply-To: <1d86d8ff-6878-5488-e8c4-cbe8a5e8f624@suse.com>


[-- Attachment #1.1.1: Type: text/plain, Size: 4029 bytes --]

On 04.05.22 10:31, Jan Beulich wrote:
> On 03.05.2022 15:22, Juergen Gross wrote:
>> Some drivers are using pat_enabled() in order to test availability of
>> special caching modes (WC and UC-). This will lead to false negatives
>> in case the system was booted e.g. with the "nopat" variant and the
>> BIOS did setup the PAT MSR supporting the queried mode, or if the
>> system is running as a Xen PV guest.
> 
> While, as per my earlier patch, I agree with the Xen PV case, I'm not
> convinced "nopat" is supposed to honor firmware-provided settings. In
> fact in my patch I did arrange for "nopat" to also take effect under
> Xen PV.

Depends on what the wanted semantics for "nopat" are.

Right now "nopat" will result in the PAT MSR left unchanged and the
cache mode translation tables be initialized accordingly.

So does "nopat" mean that the PAT MSR shouldn't be changed, or that
PAGE_BIT_PAT will never be set?

>> Add test functions for those caching modes instead and use them at the
>> appropriate places.
>>
>> For symmetry reasons export the already existing x86_has_pat_wp() for
>> modules, too.
>>
>> Fixes: bdd8b6c98239 ("drm/i915: replace X86_FEATURE_PAT with pat_enabled()")
>> Fixes: ae749c7ab475 ("PCI: Add arch_can_pci_mmap_wc() macro")
>> Signed-off-by: Juergen Gross <jgross@suse.com>
> 
> I think this wants a Reported-by as well.

Okay.

> 
>> --- a/arch/x86/include/asm/pci.h
>> +++ b/arch/x86/include/asm/pci.h
>> @@ -94,7 +94,7 @@ int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
>>   
>>   
>>   #define HAVE_PCI_MMAP
>> -#define arch_can_pci_mmap_wc()	pat_enabled()
>> +#define arch_can_pci_mmap_wc()	x86_has_pat_wc()
> 
> Besides this and ...
> 
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
>> @@ -76,7 +76,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
>>   	if (args->flags & ~(I915_MMAP_WC))
>>   		return -EINVAL;
>>   
>> -	if (args->flags & I915_MMAP_WC && !pat_enabled())
>> +	if (args->flags & I915_MMAP_WC && !x86_has_pat_wc())
>>   		return -ENODEV;
>>   
>>   	obj = i915_gem_object_lookup(file, args->handle);
>> @@ -757,7 +757,7 @@ i915_gem_dumb_mmap_offset(struct drm_file *file,
>>   
>>   	if (HAS_LMEM(to_i915(dev)))
>>   		mmap_type = I915_MMAP_TYPE_FIXED;
>> -	else if (pat_enabled())
>> +	else if (x86_has_pat_wc())
>>   		mmap_type = I915_MMAP_TYPE_WC;
>>   	else if (!i915_ggtt_has_aperture(to_gt(i915)->ggtt))
>>   		return -ENODEV;
>> @@ -813,7 +813,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
>>   		break;
>>   
>>   	case I915_MMAP_OFFSET_WC:
>> -		if (!pat_enabled())
>> +		if (!x86_has_pat_wc())
>>   			return -ENODEV;
>>   		type = I915_MMAP_TYPE_WC;
>>   		break;
>> @@ -823,7 +823,7 @@ i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data,
>>   		break;
>>   
>>   	case I915_MMAP_OFFSET_UC:
>> -		if (!pat_enabled())
>> +		if (!x86_has_pat_uc_minus())
>>   			return -ENODEV;
>>   		type = I915_MMAP_TYPE_UC;
>>   		break;
> 
> ... these uses there are several more. You say nothing on why those want
> leaving unaltered. When preparing my earlier patch I did inspect them
> and came to the conclusion that these all would also better observe the
> adjusted behavior (or else I couldn't have left pat_enabled() as the only
> predicate). In fact, as said in the description of my earlier patch, in
> my debugging I did find the use in i915_gem_object_pin_map() to be the
> problematic one, which you leave alone.

Oh, I missed that one, sorry.

I wanted to be rather defensive in my changes, but I agree at least the
case in arch_phys_wc_add() might want to be changed, too.

kvm_is_mmio_pfn() should not really matter at least for the Xen case.

With the other use cases in memtype.c I'm rather on the edge.

In case the x86 maintainers think those should be changed, too, I agree
that your approach might be the better one.


Juergen

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  reply	other threads:[~2022-05-04  9:14 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03 13:22 [PATCH 0/2] x86/pat: fix querying available caching modes Juergen Gross
2022-05-03 13:22 ` [Intel-gfx] " Juergen Gross
2022-05-03 13:22 ` Juergen Gross
2022-05-03 13:22 ` [PATCH 1/2] x86/pat: fix x86_has_pat_wp() Juergen Gross
2022-05-27 10:21   ` Juergen Gross
2022-06-14 15:09   ` Juergen Gross
2022-06-20  5:22     ` Thorsten Leemhuis
2022-06-20  5:30       ` Juergen Gross
2022-06-20  6:15         ` Thorsten Leemhuis
2022-06-20 10:26   ` Borislav Petkov
2022-06-20 10:41     ` Juergen Gross
2022-06-20 15:27       ` Dave Hansen
2022-06-20 15:34         ` Juergen Gross
2022-05-03 13:22 ` [PATCH 2/2] x86/pat: add functions to query specific cache mode availability Juergen Gross
2022-05-03 13:22   ` [Intel-gfx] " Juergen Gross
2022-05-03 13:22   ` Juergen Gross
2022-05-04  8:31   ` Jan Beulich
2022-05-04  8:31     ` [Intel-gfx] " Jan Beulich
2022-05-04  8:31     ` Jan Beulich
2022-05-04  9:14     ` Juergen Gross [this message]
2022-05-04  9:14       ` [Intel-gfx] " Juergen Gross
2022-05-04  9:14       ` Juergen Gross
2022-05-04  9:51       ` Jan Beulich
2022-05-04  9:51         ` [Intel-gfx] " Jan Beulich
2022-05-04  9:51         ` Jan Beulich
2022-05-20  4:43       ` Chuck Zmudzinski
2022-05-20  4:43         ` Chuck Zmudzinski
2022-05-20  5:56         ` Chuck Zmudzinski
2022-05-20  5:56           ` Chuck Zmudzinski
2022-05-20  6:05         ` Jan Beulich
2022-05-20  6:05           ` Jan Beulich
2022-05-20  6:59           ` Chuck Zmudzinski
2022-05-20  6:59             ` Chuck Zmudzinski
2022-05-20  8:30             ` Chuck Zmudzinski
2022-05-20  8:30               ` Chuck Zmudzinski
2022-05-20  9:41               ` Jan Beulich
2022-05-20  9:41                 ` Jan Beulich
2022-05-20 13:33                 ` Chuck Zmudzinski
2022-05-20 13:33                   ` Chuck Zmudzinski
2022-05-20 14:06                   ` Jan Beulich
2022-05-20 14:06                     ` Jan Beulich
2022-05-20 14:48                     ` Chuck Zmudzinski
2022-05-20 14:48                       ` Chuck Zmudzinski
2022-05-21 10:47                       ` Thorsten Leemhuis
2022-05-21 10:47                         ` [Intel-gfx] " Thorsten Leemhuis
2022-05-21 10:47                         ` Thorsten Leemhuis
2022-05-24 18:32                         ` Chuck Zmudzinski
2022-05-24 18:32                           ` [Intel-gfx] " Chuck Zmudzinski
2022-05-24 18:32                           ` Chuck Zmudzinski
2022-05-25  7:45                           ` [Intel-gfx] " Thorsten Leemhuis
2022-05-25  7:45                             ` Thorsten Leemhuis
2022-05-25  7:45                             ` Thorsten Leemhuis
2022-05-25  8:04                             ` Juergen Gross
2022-05-25  8:04                               ` [Intel-gfx] " Juergen Gross
2022-05-25  8:04                               ` Juergen Gross
2022-05-25  8:37                             ` Jan Beulich
2022-05-25  8:37                               ` Jan Beulich
2022-05-25  8:51                               ` Thorsten Leemhuis
2022-05-25  8:51                                 ` [Intel-gfx] " Thorsten Leemhuis
2022-05-25  8:51                                 ` Thorsten Leemhuis
2022-05-25 19:25                             ` Chuck Zmudzinski
2022-05-25 19:25                               ` [Intel-gfx] " Chuck Zmudzinski
2022-05-25 19:25                               ` Chuck Zmudzinski
2022-05-20 15:46                     ` [REGRESSION} " Chuck Zmudzinski
2022-05-20 15:46                       ` Chuck Zmudzinski
2022-05-20 17:13                       ` Chuck Zmudzinski
2022-05-20 17:13                         ` Chuck Zmudzinski
2022-05-20 17:17                         ` Chuck Zmudzinski
2022-05-20 17:17                           ` Chuck Zmudzinski
2022-05-18 13:45   ` Christoph Hellwig
2022-05-18 13:45     ` [Intel-gfx] " Christoph Hellwig
2022-05-20  2:15   ` Chuck Zmudzinski
2022-05-20  2:15     ` Chuck Zmudzinski
2022-05-20  2:21     ` Chuck Zmudzinski
2022-05-20  2:21       ` Chuck Zmudzinski
2022-05-21 13:24   ` Chuck Zmudzinski
2022-05-21 13:24     ` Chuck Zmudzinski
2022-07-11  9:46 ` [tip: x86/urgent] x86/pat: Fix x86_has_pat_wp() tip-bot2 for Juergen Gross
2022-07-13 10:45 ` tip-bot2 for Juergen Gross
2022-07-13 10:52 ` tip-bot2 for Juergen Gross

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