* [PATCH RESEND 0/4] PHYTEC i.MX 6UL/ULL devicetree patches
@ 2022-01-31 8:05 ` Andrej Picej
0 siblings, 0 replies; 20+ messages in thread
From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw)
To: devicetree, linux-arm-kernel
Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski,
festevam, linux, arnd, linux-imx, y.bas
Hi all,
this patch series contains PHYTEC i.MX 6UL/ULL devicetree patches not
yet upstreamed.
First and second patch add devicetree for relatively new phyGATE
Tauri-S, which is based on i.MX 6ULL.
Third patch changes USB LDO voltage for i.MX 6UL/ULL phyCORE devices so
they match USB Full-speed compliance.
The fourth patch moves from using 2 pwm-cell to default 3 cell pwm
property.
Best regards,
Andrej
Alexander Bauer (1):
ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX
6ULL
Andrej Picej (2):
dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL
ARM: dts: imx6ul: peb-av-02: move to 3 cell pwm
Yunus Bas (1):
ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance
.../devicetree/bindings/arm/fsl.yaml | 9 +
arch/arm/boot/dts/Makefile | 2 +
.../boot/dts/imx6ul-phytec-phycore-som.dtsi | 5 +
.../dts/imx6ul-phytec-segin-peb-av-02.dtsi | 3 +-
.../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 +
.../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 +
arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 605 ++++++++++++++++++
7 files changed, 662 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts
create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi
--
2.25.1
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH RESEND 0/4] PHYTEC i.MX 6UL/ULL devicetree patches @ 2022-01-31 8:05 ` Andrej Picej 0 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw) To: devicetree, linux-arm-kernel Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas Hi all, this patch series contains PHYTEC i.MX 6UL/ULL devicetree patches not yet upstreamed. First and second patch add devicetree for relatively new phyGATE Tauri-S, which is based on i.MX 6ULL. Third patch changes USB LDO voltage for i.MX 6UL/ULL phyCORE devices so they match USB Full-speed compliance. The fourth patch moves from using 2 pwm-cell to default 3 cell pwm property. Best regards, Andrej Alexander Bauer (1): ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL Andrej Picej (2): dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL ARM: dts: imx6ul: peb-av-02: move to 3 cell pwm Yunus Bas (1): ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance .../devicetree/bindings/arm/fsl.yaml | 9 + arch/arm/boot/dts/Makefile | 2 + .../boot/dts/imx6ul-phytec-phycore-som.dtsi | 5 + .../dts/imx6ul-phytec-segin-peb-av-02.dtsi | 3 +- .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 605 ++++++++++++++++++ 7 files changed, 662 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH RESEND 1/4] dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL 2022-01-31 8:05 ` Andrej Picej @ 2022-01-31 8:05 ` Andrej Picej -1 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw) To: devicetree, linux-arm-kernel Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas Add devicetree bindings for phyGATE Tauri board with phyCORE-i.MX6 ULL. Signed-off-by: Andrej Picej <andrej.picej@norik.com> --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 97f6eebad76a..aca681477e1e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -640,6 +640,15 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyGATE-Tauri + items: + - enum: + - phytec,imx6ull-phygate-tauri-emmc + - phytec,imx6ull-phygate-tauri-nand + - const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL + - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: -- 2.25.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH RESEND 1/4] dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL @ 2022-01-31 8:05 ` Andrej Picej 0 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw) To: devicetree, linux-arm-kernel Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas Add devicetree bindings for phyGATE Tauri board with phyCORE-i.MX6 ULL. Signed-off-by: Andrej Picej <andrej.picej@norik.com> --- Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 97f6eebad76a..aca681477e1e 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -640,6 +640,15 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyGATE-Tauri + items: + - enum: + - phytec,imx6ull-phygate-tauri-emmc + - phytec,imx6ull-phygate-tauri-nand + - const: phytec,imx6ull-phygate-tauri # PHYTEC phyGATE-Tauri with i.MX6 ULL + - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 1/4] dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL 2022-01-31 8:05 ` Andrej Picej @ 2022-02-11 13:26 ` Rob Herring -1 siblings, 0 replies; 20+ messages in thread From: Rob Herring @ 2022-02-11 13:26 UTC (permalink / raw) To: Andrej Picej Cc: y.bas, linux-arm-kernel, krzysztof.kozlowski, arnd, kernel, devicetree, robh+dt, linux-imx, festevam, linux, leoyang.li, shawnguo On Mon, 31 Jan 2022 09:05:23 +0100, Andrej Picej wrote: > Add devicetree bindings for phyGATE Tauri board with phyCORE-i.MX6 ULL. > > Signed-off-by: Andrej Picej <andrej.picej@norik.com> > --- > Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 1/4] dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL @ 2022-02-11 13:26 ` Rob Herring 0 siblings, 0 replies; 20+ messages in thread From: Rob Herring @ 2022-02-11 13:26 UTC (permalink / raw) To: Andrej Picej Cc: y.bas, linux-arm-kernel, krzysztof.kozlowski, arnd, kernel, devicetree, robh+dt, linux-imx, festevam, linux, leoyang.li, shawnguo On Mon, 31 Jan 2022 09:05:23 +0100, Andrej Picej wrote: > Add devicetree bindings for phyGATE Tauri board with phyCORE-i.MX6 ULL. > > Signed-off-by: Andrej Picej <andrej.picej@norik.com> > --- > Documentation/devicetree/bindings/arm/fsl.yaml | 9 +++++++++ > 1 file changed, 9 insertions(+) > Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH RESEND 2/4] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL 2022-01-31 8:05 ` Andrej Picej @ 2022-01-31 8:05 ` Andrej Picej -1 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw) To: devicetree, linux-arm-kernel Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas From: Alexander Bauer <a.bauer@phytec.de> Add support for the PHYTEC phyGATE-Tauri-S with i.MX 6ULL with eMMC or NAND. Supported features: * eMMC/NAND * i2c RTC * i2c TEMP * PMIC * PWM * debug UART * CAN * SD card * 2x 1Gbit Ethernet * RS232/RS485 * USB 2.0 Host * TPM * SPI-NOR Signed-off-by: Alexander Bauer <a.bauer@phytec.de> Signed-off-by: Jens Lang <j.lang@phytec.de> Signed-off-by: Andrej Picej <andrej.picej@norik.com> --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 605 ++++++++++++++++++ 4 files changed, 647 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 235ad559acb2..f50270b9965a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -704,6 +704,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-phytec-tauri-nand.dtb \ + imx6ull-phytec-tauri-emmc.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts new file mode 100644 index 000000000000..14adb87da911 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer <a.bauer@phytec.de> + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-emmc", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* EMMC-Version */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts new file mode 100644 index 000000000000..ae396ac63443 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer <a.bauer@phytec.de> + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-nand", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* NAND-Version */ +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi new file mode 100644 index 000000000000..62a70d80c009 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi @@ -0,0 +1,605 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer <a.bauer@phytec.de> + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" + +/ { + + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key { + label = "KEY-A"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = <30>; + wakeup-source; + }; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_s25fl064_hold: regulator-s25fl064-hold { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_s25fl064_hold>; + compatible = "regulator-fixed"; + regulator-name = "s25fl064_hold"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_hub_vbus: regulator-hub-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhubpwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_hub_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>, + <&pinctrl_user_leds_snvs>; + + user-led1 { + label = "yellow"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + + user-led2 { + label = "red"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, + <&pinctrl_ecspi1_cs>; + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, + <&gpio3 10 GPIO_ACTIVE_LOW>, + <&gpio3 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + spi_dev0: spi@0 { + compatible = "linux,spidev"; + spi-max-frequency = <57600000>; + reg = <0>; + }; + + tpm_tis: tpm@1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + compatible = "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + }; + +/* S25FL064P */ + s25fl064: flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = " jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <40000000>; + m25p,fast-read; + status = "disabled"; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + dmas = <&sdma 7 8 0>, + <&sdma 8 8 0>; + dma-names = "rx", "tx"; + status = "okay"; + + spi_dev1: spi@0 { + compatible = "linux,spidev"; + spi-max-frequency = <57600000>; + reg = <0>; + }; +}; + +ðphy1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + + tmp102: tmp@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + status = "okay"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 * RS485 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* UART5 * RS232 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_hub_vbus>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&iomuxc_snvs { + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_usbhubpwr: usbhubpwrgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 + >; + }; + + pinctrl_user_leds_snvs: user_ledsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; +}; + +&iomuxc { + + pinctrl_gpio: gpio_gpiogrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 + >; + }; + + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 + >; + }; + + princtrl_flexcan2_en: flexcan2engrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 + >; + }; + + pinctrl_s25fl064_hold: s25fl064_holdgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 + >; + }; + + pinctrl_usbotg1pwr: usbotg1pwrgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_user_leds: user_ledsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 + >; + }; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH RESEND 2/4] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL @ 2022-01-31 8:05 ` Andrej Picej 0 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw) To: devicetree, linux-arm-kernel Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas From: Alexander Bauer <a.bauer@phytec.de> Add support for the PHYTEC phyGATE-Tauri-S with i.MX 6ULL with eMMC or NAND. Supported features: * eMMC/NAND * i2c RTC * i2c TEMP * PMIC * PWM * debug UART * CAN * SD card * 2x 1Gbit Ethernet * RS232/RS485 * USB 2.0 Host * TPM * SPI-NOR Signed-off-by: Alexander Bauer <a.bauer@phytec.de> Signed-off-by: Jens Lang <j.lang@phytec.de> Signed-off-by: Andrej Picej <andrej.picej@norik.com> --- arch/arm/boot/dts/Makefile | 2 + .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 605 ++++++++++++++++++ 4 files changed, 647 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 235ad559acb2..f50270b9965a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -704,6 +704,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-phytec-segin-ff-rdk-nand.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-phytec-segin-lc-rdk-nand.dtb \ + imx6ull-phytec-tauri-nand.dtb \ + imx6ull-phytec-tauri-emmc.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts new file mode 100644 index 000000000000..14adb87da911 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer <a.bauer@phytec.de> + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-emmc", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* EMMC-Version */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts new file mode 100644 index 000000000000..ae396ac63443 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer <a.bauer@phytec.de> + */ + +/dts-v1/; +#include "imx6ull-phytec-tauri.dtsi" + +/ { + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-phygate-tauri-nand", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; +}; + +/* NAND-Version */ +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi new file mode 100644 index 000000000000..62a70d80c009 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi @@ -0,0 +1,605 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 PHYTEC Messtechnik GmbH + * Author: Alexander Bauer <a.bauer@phytec.de> + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-phytec-phycore-som.dtsi" + +/ { + + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; + compatible = "phytec,imx6ull-phygate-tauri", + "phytec,imx6ull-pcl063", "fsl,imx6ull"; + + aliases { + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-key"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key { + label = "KEY-A"; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + linux,code = <30>; + wakeup-source; + }; + }; + + reg_adc1_vref_3v3: regulator-vref-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_s25fl064_hold: regulator-s25fl064-hold { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_s25fl064_hold>; + compatible = "regulator-fixed"; + regulator-name = "s25fl064_hold"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_hub_vbus: regulator-hub-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhubpwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_hub_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwr>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + user_leds: user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>, + <&pinctrl_user_leds_snvs>; + + user-led1 { + label = "yellow"; + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + + user-led2 { + label = "red"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "off"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>, + <&pinctrl_ecspi1_cs>; + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, + <&gpio3 10 GPIO_ACTIVE_LOW>, + <&gpio3 11 GPIO_ACTIVE_LOW>; + status = "okay"; + + spi_dev0: spi@0 { + compatible = "linux,spidev"; + spi-max-frequency = <57600000>; + reg = <0>; + }; + + tpm_tis: tpm@1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + compatible = "tcg,tpm_tis-spi"; + reg = <1>; + spi-max-frequency = <20000000>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + }; + +/* S25FL064P */ + s25fl064: flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = " jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <40000000>; + m25p,fast-read; + status = "disabled"; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + dmas = <&sdma 7 8 0>, + <&sdma 8 8 0>; + dma-names = "rx", "tx"; + status = "okay"; + + spi_dev1: spi@0 { + compatible = "linux,spidev"; + spi-max-frequency = <57600000>; + reg = <0>; + }; +}; + +ðphy1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy2>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + i2c_rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_int>; + compatible = "microcrystal,rv4162"; + reg = <0x68>; + interrupt-parent = <&gpio5>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + }; + + tmp102: tmp@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&mdio { + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + status = "okay"; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* UART4 * RS485 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* UART5 * RS232 */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_hub_vbus>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; + +&iomuxc_snvs { + + pinctrl_rtc_int: rtcintgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 + >; + }; + + pinctrl_stmpe: stmpegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 + >; + }; + + pinctrl_usbhubpwr: usbhubpwrgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 + >; + }; + + pinctrl_user_leds_snvs: user_ledsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; +}; + +&iomuxc { + + pinctrl_gpio: gpio_gpiogrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 + >; + }; + + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 + >; + }; + + princtrl_flexcan2_en: flexcan2engrp { + fsl,pins = < + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm6: pwm6grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 + >; + }; + + pinctrl_s25fl064_hold: s25fl064_holdgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 + >; + }; + + pinctrl_usbotg1pwr: usbotg1pwrgrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_user_leds: user_ledsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 + >; + }; +}; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 2/4] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL 2022-01-31 8:05 ` Andrej Picej @ 2022-02-12 5:43 ` Shawn Guo -1 siblings, 0 replies; 20+ messages in thread From: Shawn Guo @ 2022-02-12 5:43 UTC (permalink / raw) To: Andrej Picej Cc: devicetree, linux-arm-kernel, robh+dt, kernel, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas On Mon, Jan 31, 2022 at 09:05:24AM +0100, Andrej Picej wrote: > From: Alexander Bauer <a.bauer@phytec.de> > > Add support for the PHYTEC phyGATE-Tauri-S with i.MX 6ULL with eMMC or > NAND. > > Supported features: > * eMMC/NAND > * i2c RTC > * i2c TEMP > * PMIC > * PWM > * debug UART > * CAN > * SD card > * 2x 1Gbit Ethernet > * RS232/RS485 > * USB 2.0 Host > * TPM > * SPI-NOR > > Signed-off-by: Alexander Bauer <a.bauer@phytec.de> > Signed-off-by: Jens Lang <j.lang@phytec.de> > Signed-off-by: Andrej Picej <andrej.picej@norik.com> > --- > arch/arm/boot/dts/Makefile | 2 + > .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + > .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + > arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 605 ++++++++++++++++++ > 4 files changed, 647 insertions(+) > create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts > create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts > create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 235ad559acb2..f50270b9965a 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -704,6 +704,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ > imx6ull-phytec-segin-ff-rdk-nand.dtb \ > imx6ull-phytec-segin-ff-rdk-emmc.dtb \ > imx6ull-phytec-segin-lc-rdk-nand.dtb \ > + imx6ull-phytec-tauri-nand.dtb \ > + imx6ull-phytec-tauri-emmc.dtb \ Keep them sort alphabetically. > imx6ulz-14x14-evk.dtb \ > imx6ulz-bsh-smm-m2.dtb > dtb-$(CONFIG_SOC_IMX7D) += \ > diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts > new file mode 100644 > index 000000000000..14adb87da911 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts > @@ -0,0 +1,20 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2021 PHYTEC Messtechnik GmbH > + * Author: Alexander Bauer <a.bauer@phytec.de> > + */ > + > +/dts-v1/; > +#include "imx6ull-phytec-tauri.dtsi" > + > +/ { > + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; > + compatible = "phytec,imx6ull-phygate-tauri", > + "phytec,imx6ull-phygate-tauri-emmc", > + "phytec,imx6ull-pcl063", "fsl,imx6ull"; > +}; > + > +/* EMMC-Version */ > +&usdhc2 { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts > new file mode 100644 > index 000000000000..ae396ac63443 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts > @@ -0,0 +1,20 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2021 PHYTEC Messtechnik GmbH > + * Author: Alexander Bauer <a.bauer@phytec.de> > + */ > + > +/dts-v1/; > +#include "imx6ull-phytec-tauri.dtsi" > + > +/ { > + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; > + compatible = "phytec,imx6ull-phygate-tauri", > + "phytec,imx6ull-phygate-tauri-nand", > + "phytec,imx6ull-pcl063", "fsl,imx6ull"; > +}; > + > +/* NAND-Version */ > +&gpmi { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi > new file mode 100644 > index 000000000000..62a70d80c009 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi > @@ -0,0 +1,605 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2021 PHYTEC Messtechnik GmbH > + * Author: Alexander Bauer <a.bauer@phytec.de> > + */ > + > +/dts-v1/; > +#include "imx6ull.dtsi" > +#include "imx6ull-phytec-phycore-som.dtsi" > + > +/ { > + > + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; > + compatible = "phytec,imx6ull-phygate-tauri", > + "phytec,imx6ull-pcl063", "fsl,imx6ull"; > + > + aliases { > + rtc0 = &i2c_rtc; > + rtc1 = &snvs_rtc; > + }; > + > + gpio_keys: gpio-keys { > + compatible = "gpio-key"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpio_keys>; > + > + key { > + label = "KEY-A"; > + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; > + linux,code = <30>; Use define in include/dt-bindings/input/linux-event-codes.h > + wakeup-source; > + }; > + }; > + > + reg_adc1_vref_3v3: regulator-vref-3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vref-3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > + > + reg_s25fl064_hold: regulator-s25fl064-hold { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_s25fl064_hold>; > + compatible = "regulator-fixed"; > + regulator-name = "s25fl064_hold"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + }; > + > + reg_usb_hub_vbus: regulator-hub-otg1-vbus { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usbhubpwr>; > + compatible = "regulator-fixed"; > + regulator-name = "usb_hub_vbus"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + }; > + > + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usbotg1pwr>; > + compatible = "regulator-fixed"; > + regulator-name = "usb_otg1_vbus"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + }; > + > + user_leds: user-leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_user_leds>, > + <&pinctrl_user_leds_snvs>; > + > + user-led1 { > + label = "yellow"; > + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "off"; > + }; > + > + user-led2 { > + label = "red"; > + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "off"; > + }; > + }; > +}; > + > +&can1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + status = "okay"; > +}; > + > +&can2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan2>; > + status = "okay"; > +}; > + > +&ecspi1 { > + #address-cells = <1>; > + #size-cells = <0>; > + fsl,spi-num-chipselects = <3>; The property is no longer supported. > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi1>, > + <&pinctrl_ecspi1_cs>; > + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, > + <&gpio3 10 GPIO_ACTIVE_LOW>, > + <&gpio3 11 GPIO_ACTIVE_LOW>; > + status = "okay"; > + > + spi_dev0: spi@0 { > + compatible = "linux,spidev"; Not supported. > + spi-max-frequency = <57600000>; > + reg = <0>; > + }; > + > + tpm_tis: tpm@1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_tpm>; > + compatible = "tcg,tpm_tis-spi"; > + reg = <1>; > + spi-max-frequency = <20000000>; > + interrupt-parent = <&gpio5>; > + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > + status = "okay"; We generally use okay status to flip a disabled device. You can save it if that's not the case. > + }; > + > +/* S25FL064P */ Not sure this comment is so useful. If you need a comment, as least indent it properly. > + s25fl064: flash@2 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = " jedec,spi-nor"; > + reg = <2>; > + spi-max-frequency = <40000000>; > + m25p,fast-read; > + status = "disabled"; > + }; > +}; > + > +&ecspi3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi3>; > + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; > + dmas = <&sdma 7 8 0>, > + <&sdma 8 8 0>; > + dma-names = "rx", "tx"; > + status = "okay"; > + > + spi_dev1: spi@0 { > + compatible = "linux,spidev"; > + spi-max-frequency = <57600000>; > + reg = <0>; > + }; > +}; > + > +ðphy1 { > + status = "okay"; > +}; > + > +&fec1 { > + status = "okay"; > +}; > + > +&fec2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet2>; > + phy-mode = "rmii"; > + phy-handle = <ðphy2>; > + status = "okay"; > +}; > + > +&i2c1 { > + status = "okay"; > + > + i2c_rtc: rtc@68 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rtc_int>; > + compatible = "microcrystal,rv4162"; > + reg = <0x68>; > + interrupt-parent = <&gpio5>; > + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + tmp102: tmp@49 { Sort the nodes in order of unit-address. > + compatible = "ti,tmp102"; > + reg = <0x49>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_tempsense>; > + interrupt-parent = <&gpio5>; > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > + #thermal-sensor-cells = <1>; > + }; > +}; > + > +&i2c2 { > + pinctrl-names = "default", "gpio"; > + pinctrl-0 = <&pinctrl_i2c2>; > + pinctrl-1 = <&pinctrl_i2c2_gpio>; > + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > +}; > + > +&i2c3 { > + pinctrl-names = "default", "gpio"; > + pinctrl-0 = <&pinctrl_i2c3>; > + pinctrl-1 = <&pinctrl_i2c3_gpio>; > + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > +}; > + > +&i2c4 { > + pinctrl-names = "default", "gpio"; > + pinctrl-0 = <&pinctrl_i2c4>; > + pinctrl-1 = <&pinctrl_i2c4_gpio>; > + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > +}; > + > +&mdio { > + ethphy2: ethernet-phy@2 { > + reg = <2>; > + micrel,led-mode = <1>; > + clocks = <&clks IMX6UL_CLK_ENET2_REF>; > + clock-names = "rmii-ref"; > + status = "okay"; > + }; > +}; > + > +&pwm3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm3>; > + status = "okay"; > +}; > + > +&pwm6 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm6>; > + status = "okay"; > +}; > + > +&pwm7 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm7>; > + status = "okay"; > +}; > + > +&pwm8 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm8>; > + status = "okay"; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + status = "okay"; > +}; > + > +/* UART4 * RS485 */ > +&uart4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart4>; > + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; > + rs485-rts-active-high; > + linux,rs485-enabled-at-boot-time; > + status = "okay"; > +}; > + > +/* UART5 * RS232 */ > +&uart5 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart5>; > + uart-has-rtscts; > + status = "okay"; > +}; > + > +&uart7 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart7>; > + status = "okay"; > +}; > + > +/* USB */ > +&usbotg1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb_otg1>; > + vbus-supply = <®_usb_otg1_vbus>; > + dr_mode = "host"; > + disable-over-current; > + status = "okay"; > +}; > + > +&usbotg2 { > + vbus-supply = <®_usb_hub_vbus>; > + disable-over-current; > + dr_mode = "host"; > + status = "okay"; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; > + no-1-8-v; > + keep-power-in-suspend; > + wakeup-source; > + status = "okay"; > +}; > + > +&usdhc2 { > + status = "disabled"; > +}; > + > +&iomuxc_snvs { > + Drop this newline. > + pinctrl_rtc_int: rtcintgrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 > + >; > + }; > + > + pinctrl_stmpe: stmpegrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 > + >; > + }; > + > + pinctrl_tempsense: tempsensegrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 > + >; > + }; > + > + pinctrl_tpm: tpmgrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 > + >; > + }; > + > + pinctrl_usbhubpwr: usbhubpwrgrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 > + >; > + }; > + > + pinctrl_user_leds_snvs: user_ledsgrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 > + >; > + }; > +}; > + > +&iomuxc { > + Drop this newline. > + pinctrl_gpio: gpio_gpiogrp { Could you name these pinctrl nodes more consistently. If you really need some delimiter in node name, hyphen rather than underscore is recommended. Shawn > + fsl,pins = < > + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ > + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ > + >; > + }; > + > + pinctrl_gpio_keys: gpio_keysgrp { > + fsl,pins = < > + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 > + >; > + }; > + > + pinctrl_ecspi3: ecspi3grp { > + fsl,pins = < > + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 > + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 > + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 > + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 > + >; > + }; > + > + pinctrl_ecspi1: ecspi1grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 > + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 > + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 > + >; > + }; > + > + pinctrl_ecspi1_cs: ecspi1csgrp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 > + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 > + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 > + >; > + }; > + > + > + pinctrl_enet2: enet2grp { > + fsl,pins = < > + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 > + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 > + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 > + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 > + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 > + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 > + >; > + }; > + > + pinctrl_flexcan1: flexcan1grp { > + fsl,pins = < > + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 > + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 > + >; > + }; > + > + pinctrl_flexcan2: flexcan2grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 > + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 > + >; > + }; > + > + princtrl_flexcan2_en: flexcan2engrp { > + fsl,pins = < > + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 > + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 > + >; > + }; > + > + pinctrl_i2c2_gpio: i2c2gpiogrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 > + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 > + >; > + }; > + > + pinctrl_i2c3: i2c3grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 > + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 > + >; > + }; > + > + pinctrl_i2c3_gpio: i2c3gpiogrp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 > + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 > + >; > + }; > + > + pinctrl_i2c4: i2c4grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 > + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 > + >; > + }; > + > + pinctrl_i2c4_gpio: i2c4gpiogrp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 > + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 > + >; > + }; > + > + pinctrl_pwm3: pwm3grp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 > + >; > + }; > + > + pinctrl_pwm6: pwm6grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 > + >; > + }; > + > + pinctrl_pwm7: pwm7grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 > + >; > + }; > + > + pinctrl_pwm8: pwm8grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 > + >; > + }; > + > + pinctrl_s25fl064_hold: s25fl064_holdgrp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 > + >; > + }; > + > + pinctrl_sai2: sai2grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 > + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 > + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 > + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 > + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_uart4: uart4grp { > + fsl,pins = < > + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 > + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 > + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 > + >; > + }; > + > + pinctrl_uart5: uart5grp { > + fsl,pins = < > + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_uart7: uart7grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 > + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_usb_otg1: usbotg1grp { > + fsl,pins = < > + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 > + >; > + }; > + > + pinctrl_usbotg1pwr: usbotg1pwrgrp { > + fsl,pins = < > + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 > + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 > + >; > + }; > + > + pinctrl_user_leds: user_ledsgrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 > + >; > + }; > +}; > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 2/4] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL @ 2022-02-12 5:43 ` Shawn Guo 0 siblings, 0 replies; 20+ messages in thread From: Shawn Guo @ 2022-02-12 5:43 UTC (permalink / raw) To: Andrej Picej Cc: devicetree, linux-arm-kernel, robh+dt, kernel, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas On Mon, Jan 31, 2022 at 09:05:24AM +0100, Andrej Picej wrote: > From: Alexander Bauer <a.bauer@phytec.de> > > Add support for the PHYTEC phyGATE-Tauri-S with i.MX 6ULL with eMMC or > NAND. > > Supported features: > * eMMC/NAND > * i2c RTC > * i2c TEMP > * PMIC > * PWM > * debug UART > * CAN > * SD card > * 2x 1Gbit Ethernet > * RS232/RS485 > * USB 2.0 Host > * TPM > * SPI-NOR > > Signed-off-by: Alexander Bauer <a.bauer@phytec.de> > Signed-off-by: Jens Lang <j.lang@phytec.de> > Signed-off-by: Andrej Picej <andrej.picej@norik.com> > --- > arch/arm/boot/dts/Makefile | 2 + > .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + > .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + > arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 605 ++++++++++++++++++ > 4 files changed, 647 insertions(+) > create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts > create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts > create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 235ad559acb2..f50270b9965a 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -704,6 +704,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ > imx6ull-phytec-segin-ff-rdk-nand.dtb \ > imx6ull-phytec-segin-ff-rdk-emmc.dtb \ > imx6ull-phytec-segin-lc-rdk-nand.dtb \ > + imx6ull-phytec-tauri-nand.dtb \ > + imx6ull-phytec-tauri-emmc.dtb \ Keep them sort alphabetically. > imx6ulz-14x14-evk.dtb \ > imx6ulz-bsh-smm-m2.dtb > dtb-$(CONFIG_SOC_IMX7D) += \ > diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts > new file mode 100644 > index 000000000000..14adb87da911 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts > @@ -0,0 +1,20 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2021 PHYTEC Messtechnik GmbH > + * Author: Alexander Bauer <a.bauer@phytec.de> > + */ > + > +/dts-v1/; > +#include "imx6ull-phytec-tauri.dtsi" > + > +/ { > + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; > + compatible = "phytec,imx6ull-phygate-tauri", > + "phytec,imx6ull-phygate-tauri-emmc", > + "phytec,imx6ull-pcl063", "fsl,imx6ull"; > +}; > + > +/* EMMC-Version */ > +&usdhc2 { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts > new file mode 100644 > index 000000000000..ae396ac63443 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts > @@ -0,0 +1,20 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2021 PHYTEC Messtechnik GmbH > + * Author: Alexander Bauer <a.bauer@phytec.de> > + */ > + > +/dts-v1/; > +#include "imx6ull-phytec-tauri.dtsi" > + > +/ { > + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; > + compatible = "phytec,imx6ull-phygate-tauri", > + "phytec,imx6ull-phygate-tauri-nand", > + "phytec,imx6ull-pcl063", "fsl,imx6ull"; > +}; > + > +/* NAND-Version */ > +&gpmi { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi > new file mode 100644 > index 000000000000..62a70d80c009 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi > @@ -0,0 +1,605 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2021 PHYTEC Messtechnik GmbH > + * Author: Alexander Bauer <a.bauer@phytec.de> > + */ > + > +/dts-v1/; > +#include "imx6ull.dtsi" > +#include "imx6ull-phytec-phycore-som.dtsi" > + > +/ { > + > + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; > + compatible = "phytec,imx6ull-phygate-tauri", > + "phytec,imx6ull-pcl063", "fsl,imx6ull"; > + > + aliases { > + rtc0 = &i2c_rtc; > + rtc1 = &snvs_rtc; > + }; > + > + gpio_keys: gpio-keys { > + compatible = "gpio-key"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpio_keys>; > + > + key { > + label = "KEY-A"; > + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; > + linux,code = <30>; Use define in include/dt-bindings/input/linux-event-codes.h > + wakeup-source; > + }; > + }; > + > + reg_adc1_vref_3v3: regulator-vref-3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vref-3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > + > + reg_s25fl064_hold: regulator-s25fl064-hold { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_s25fl064_hold>; > + compatible = "regulator-fixed"; > + regulator-name = "s25fl064_hold"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + }; > + > + reg_usb_hub_vbus: regulator-hub-otg1-vbus { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usbhubpwr>; > + compatible = "regulator-fixed"; > + regulator-name = "usb_hub_vbus"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + }; > + > + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usbotg1pwr>; > + compatible = "regulator-fixed"; > + regulator-name = "usb_otg1_vbus"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-always-on; > + }; > + > + user_leds: user-leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_user_leds>, > + <&pinctrl_user_leds_snvs>; > + > + user-led1 { > + label = "yellow"; > + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "off"; > + }; > + > + user-led2 { > + label = "red"; > + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "off"; > + }; > + }; > +}; > + > +&can1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan1>; > + status = "okay"; > +}; > + > +&can2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_flexcan2>; > + status = "okay"; > +}; > + > +&ecspi1 { > + #address-cells = <1>; > + #size-cells = <0>; > + fsl,spi-num-chipselects = <3>; The property is no longer supported. > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi1>, > + <&pinctrl_ecspi1_cs>; > + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, > + <&gpio3 10 GPIO_ACTIVE_LOW>, > + <&gpio3 11 GPIO_ACTIVE_LOW>; > + status = "okay"; > + > + spi_dev0: spi@0 { > + compatible = "linux,spidev"; Not supported. > + spi-max-frequency = <57600000>; > + reg = <0>; > + }; > + > + tpm_tis: tpm@1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_tpm>; > + compatible = "tcg,tpm_tis-spi"; > + reg = <1>; > + spi-max-frequency = <20000000>; > + interrupt-parent = <&gpio5>; > + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > + status = "okay"; We generally use okay status to flip a disabled device. You can save it if that's not the case. > + }; > + > +/* S25FL064P */ Not sure this comment is so useful. If you need a comment, as least indent it properly. > + s25fl064: flash@2 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = " jedec,spi-nor"; > + reg = <2>; > + spi-max-frequency = <40000000>; > + m25p,fast-read; > + status = "disabled"; > + }; > +}; > + > +&ecspi3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi3>; > + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; > + dmas = <&sdma 7 8 0>, > + <&sdma 8 8 0>; > + dma-names = "rx", "tx"; > + status = "okay"; > + > + spi_dev1: spi@0 { > + compatible = "linux,spidev"; > + spi-max-frequency = <57600000>; > + reg = <0>; > + }; > +}; > + > +ðphy1 { > + status = "okay"; > +}; > + > +&fec1 { > + status = "okay"; > +}; > + > +&fec2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet2>; > + phy-mode = "rmii"; > + phy-handle = <ðphy2>; > + status = "okay"; > +}; > + > +&i2c1 { > + status = "okay"; > + > + i2c_rtc: rtc@68 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rtc_int>; > + compatible = "microcrystal,rv4162"; > + reg = <0x68>; > + interrupt-parent = <&gpio5>; > + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + tmp102: tmp@49 { Sort the nodes in order of unit-address. > + compatible = "ti,tmp102"; > + reg = <0x49>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_tempsense>; > + interrupt-parent = <&gpio5>; > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > + #thermal-sensor-cells = <1>; > + }; > +}; > + > +&i2c2 { > + pinctrl-names = "default", "gpio"; > + pinctrl-0 = <&pinctrl_i2c2>; > + pinctrl-1 = <&pinctrl_i2c2_gpio>; > + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > +}; > + > +&i2c3 { > + pinctrl-names = "default", "gpio"; > + pinctrl-0 = <&pinctrl_i2c3>; > + pinctrl-1 = <&pinctrl_i2c3_gpio>; > + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > +}; > + > +&i2c4 { > + pinctrl-names = "default", "gpio"; > + pinctrl-0 = <&pinctrl_i2c4>; > + pinctrl-1 = <&pinctrl_i2c4_gpio>; > + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > + status = "okay"; > +}; > + > +&mdio { > + ethphy2: ethernet-phy@2 { > + reg = <2>; > + micrel,led-mode = <1>; > + clocks = <&clks IMX6UL_CLK_ENET2_REF>; > + clock-names = "rmii-ref"; > + status = "okay"; > + }; > +}; > + > +&pwm3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm3>; > + status = "okay"; > +}; > + > +&pwm6 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm6>; > + status = "okay"; > +}; > + > +&pwm7 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm7>; > + status = "okay"; > +}; > + > +&pwm8 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pwm8>; > + status = "okay"; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + status = "okay"; > +}; > + > +/* UART4 * RS485 */ > +&uart4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart4>; > + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; > + rs485-rts-active-high; > + linux,rs485-enabled-at-boot-time; > + status = "okay"; > +}; > + > +/* UART5 * RS232 */ > +&uart5 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart5>; > + uart-has-rtscts; > + status = "okay"; > +}; > + > +&uart7 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart7>; > + status = "okay"; > +}; > + > +/* USB */ > +&usbotg1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb_otg1>; > + vbus-supply = <®_usb_otg1_vbus>; > + dr_mode = "host"; > + disable-over-current; > + status = "okay"; > +}; > + > +&usbotg2 { > + vbus-supply = <®_usb_hub_vbus>; > + disable-over-current; > + dr_mode = "host"; > + status = "okay"; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; > + no-1-8-v; > + keep-power-in-suspend; > + wakeup-source; > + status = "okay"; > +}; > + > +&usdhc2 { > + status = "disabled"; > +}; > + > +&iomuxc_snvs { > + Drop this newline. > + pinctrl_rtc_int: rtcintgrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 > + >; > + }; > + > + pinctrl_stmpe: stmpegrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 > + >; > + }; > + > + pinctrl_tempsense: tempsensegrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 > + >; > + }; > + > + pinctrl_tpm: tpmgrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 > + >; > + }; > + > + pinctrl_usbhubpwr: usbhubpwrgrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 > + >; > + }; > + > + pinctrl_user_leds_snvs: user_ledsgrp { > + fsl,pins = < > + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 > + >; > + }; > +}; > + > +&iomuxc { > + Drop this newline. > + pinctrl_gpio: gpio_gpiogrp { Could you name these pinctrl nodes more consistently. If you really need some delimiter in node name, hyphen rather than underscore is recommended. Shawn > + fsl,pins = < > + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ > + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ > + >; > + }; > + > + pinctrl_gpio_keys: gpio_keysgrp { > + fsl,pins = < > + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 > + >; > + }; > + > + pinctrl_ecspi3: ecspi3grp { > + fsl,pins = < > + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 > + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 > + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 > + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 > + >; > + }; > + > + pinctrl_ecspi1: ecspi1grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 > + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 > + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 > + >; > + }; > + > + pinctrl_ecspi1_cs: ecspi1csgrp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 > + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 > + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 > + >; > + }; > + > + > + pinctrl_enet2: enet2grp { > + fsl,pins = < > + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 > + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 > + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 > + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 > + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 > + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 > + >; > + }; > + > + pinctrl_flexcan1: flexcan1grp { > + fsl,pins = < > + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 > + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 > + >; > + }; > + > + pinctrl_flexcan2: flexcan2grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 > + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 > + >; > + }; > + > + princtrl_flexcan2_en: flexcan2engrp { > + fsl,pins = < > + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 > + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 > + >; > + }; > + > + pinctrl_i2c2_gpio: i2c2gpiogrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 > + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 > + >; > + }; > + > + pinctrl_i2c3: i2c3grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 > + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 > + >; > + }; > + > + pinctrl_i2c3_gpio: i2c3gpiogrp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 > + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 > + >; > + }; > + > + pinctrl_i2c4: i2c4grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 > + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 > + >; > + }; > + > + pinctrl_i2c4_gpio: i2c4gpiogrp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 > + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 > + >; > + }; > + > + pinctrl_pwm3: pwm3grp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 > + >; > + }; > + > + pinctrl_pwm6: pwm6grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 > + >; > + }; > + > + pinctrl_pwm7: pwm7grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 > + >; > + }; > + > + pinctrl_pwm8: pwm8grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 > + >; > + }; > + > + pinctrl_s25fl064_hold: s25fl064_holdgrp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 > + >; > + }; > + > + pinctrl_sai2: sai2grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 > + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 > + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 > + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 > + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_uart4: uart4grp { > + fsl,pins = < > + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 > + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 > + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 > + >; > + }; > + > + pinctrl_uart5: uart5grp { > + fsl,pins = < > + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_uart7: uart7grp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 > + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_usb_otg1: usbotg1grp { > + fsl,pins = < > + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 > + >; > + }; > + > + pinctrl_usbotg1pwr: usbotg1pwrgrp { > + fsl,pins = < > + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 > + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 > + >; > + }; > + > + pinctrl_user_leds: user_ledsgrp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 > + >; > + }; > +}; > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 2/4] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL 2022-02-12 5:43 ` Shawn Guo @ 2022-02-17 6:47 ` Andrej Picej -1 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-02-17 6:47 UTC (permalink / raw) To: Shawn Guo Cc: devicetree, linux-arm-kernel, robh+dt, kernel, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas Hi Shawn, I will fix what you pointed out and send a v2. Thanks for your review. On 12. 02. 22 06:43, Shawn Guo wrote: > On Mon, Jan 31, 2022 at 09:05:24AM +0100, Andrej Picej wrote: >> From: Alexander Bauer <a.bauer@phytec.de> >> >> Add support for the PHYTEC phyGATE-Tauri-S with i.MX 6ULL with eMMC or >> NAND. >> >> Supported features: >> * eMMC/NAND >> * i2c RTC >> * i2c TEMP >> * PMIC >> * PWM >> * debug UART >> * CAN >> * SD card >> * 2x 1Gbit Ethernet >> * RS232/RS485 >> * USB 2.0 Host >> * TPM >> * SPI-NOR >> >> Signed-off-by: Alexander Bauer <a.bauer@phytec.de> >> Signed-off-by: Jens Lang <j.lang@phytec.de> >> Signed-off-by: Andrej Picej <andrej.picej@norik.com> >> --- >> arch/arm/boot/dts/Makefile | 2 + >> .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + >> .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + >> arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 605 ++++++++++++++++++ >> 4 files changed, 647 insertions(+) >> create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts >> create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts >> create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi >> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index 235ad559acb2..f50270b9965a 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -704,6 +704,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ >> imx6ull-phytec-segin-ff-rdk-nand.dtb \ >> imx6ull-phytec-segin-ff-rdk-emmc.dtb \ >> imx6ull-phytec-segin-lc-rdk-nand.dtb \ >> + imx6ull-phytec-tauri-nand.dtb \ >> + imx6ull-phytec-tauri-emmc.dtb \ > > Keep them sort alphabetically. > >> imx6ulz-14x14-evk.dtb \ >> imx6ulz-bsh-smm-m2.dtb >> dtb-$(CONFIG_SOC_IMX7D) += \ >> diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts >> new file mode 100644 >> index 000000000000..14adb87da911 >> --- /dev/null >> +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts >> @@ -0,0 +1,20 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH >> + * Author: Alexander Bauer <a.bauer@phytec.de> >> + */ >> + >> +/dts-v1/; >> +#include "imx6ull-phytec-tauri.dtsi" >> + >> +/ { >> + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; >> + compatible = "phytec,imx6ull-phygate-tauri", >> + "phytec,imx6ull-phygate-tauri-emmc", >> + "phytec,imx6ull-pcl063", "fsl,imx6ull"; >> +}; >> + >> +/* EMMC-Version */ >> +&usdhc2 { >> + status = "okay"; >> +}; >> diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts >> new file mode 100644 >> index 000000000000..ae396ac63443 >> --- /dev/null >> +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts >> @@ -0,0 +1,20 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH >> + * Author: Alexander Bauer <a.bauer@phytec.de> >> + */ >> + >> +/dts-v1/; >> +#include "imx6ull-phytec-tauri.dtsi" >> + >> +/ { >> + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; >> + compatible = "phytec,imx6ull-phygate-tauri", >> + "phytec,imx6ull-phygate-tauri-nand", >> + "phytec,imx6ull-pcl063", "fsl,imx6ull"; >> +}; >> + >> +/* NAND-Version */ >> +&gpmi { >> + status = "okay"; >> +}; >> diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi >> new file mode 100644 >> index 000000000000..62a70d80c009 >> --- /dev/null >> +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi >> @@ -0,0 +1,605 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH >> + * Author: Alexander Bauer <a.bauer@phytec.de> >> + */ >> + >> +/dts-v1/; >> +#include "imx6ull.dtsi" >> +#include "imx6ull-phytec-phycore-som.dtsi" >> + >> +/ { >> + >> + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; >> + compatible = "phytec,imx6ull-phygate-tauri", >> + "phytec,imx6ull-pcl063", "fsl,imx6ull"; >> + >> + aliases { >> + rtc0 = &i2c_rtc; >> + rtc1 = &snvs_rtc; >> + }; >> + >> + gpio_keys: gpio-keys { >> + compatible = "gpio-key"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_gpio_keys>; >> + >> + key { >> + label = "KEY-A"; >> + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; >> + linux,code = <30>; > > Use define in include/dt-bindings/input/linux-event-codes.h > >> + wakeup-source; >> + }; >> + }; >> + >> + reg_adc1_vref_3v3: regulator-vref-3v3 { >> + compatible = "regulator-fixed"; >> + regulator-name = "vref-3v3"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + }; >> + >> + reg_s25fl064_hold: regulator-s25fl064-hold { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_s25fl064_hold>; >> + compatible = "regulator-fixed"; >> + regulator-name = "s25fl064_hold"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + regulator-always-on; >> + }; >> + >> + reg_usb_hub_vbus: regulator-hub-otg1-vbus { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_usbhubpwr>; >> + compatible = "regulator-fixed"; >> + regulator-name = "usb_hub_vbus"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + regulator-always-on; >> + }; >> + >> + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_usbotg1pwr>; >> + compatible = "regulator-fixed"; >> + regulator-name = "usb_otg1_vbus"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + regulator-always-on; >> + }; >> + >> + user_leds: user-leds { >> + compatible = "gpio-leds"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_user_leds>, >> + <&pinctrl_user_leds_snvs>; >> + >> + user-led1 { >> + label = "yellow"; >> + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; >> + linux,default-trigger = "off"; >> + }; >> + >> + user-led2 { >> + label = "red"; >> + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; >> + linux,default-trigger = "off"; >> + }; >> + }; >> +}; >> + >> +&can1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_flexcan1>; >> + status = "okay"; >> +}; >> + >> +&can2 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_flexcan2>; >> + status = "okay"; >> +}; >> + >> +&ecspi1 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + fsl,spi-num-chipselects = <3>; > > The property is no longer supported. > >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_ecspi1>, >> + <&pinctrl_ecspi1_cs>; >> + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, >> + <&gpio3 10 GPIO_ACTIVE_LOW>, >> + <&gpio3 11 GPIO_ACTIVE_LOW>; >> + status = "okay"; >> + >> + spi_dev0: spi@0 { >> + compatible = "linux,spidev"; > > Not supported. > >> + spi-max-frequency = <57600000>; >> + reg = <0>; >> + }; >> + >> + tpm_tis: tpm@1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_tpm>; >> + compatible = "tcg,tpm_tis-spi"; >> + reg = <1>; >> + spi-max-frequency = <20000000>; >> + interrupt-parent = <&gpio5>; >> + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; >> + status = "okay"; > > We generally use okay status to flip a disabled device. You can save it > if that's not the case. > >> + }; >> + >> +/* S25FL064P */ > > Not sure this comment is so useful. If you need a comment, as least > indent it properly. > >> + s25fl064: flash@2 { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = " jedec,spi-nor"; >> + reg = <2>; >> + spi-max-frequency = <40000000>; >> + m25p,fast-read; >> + status = "disabled"; >> + }; >> +}; >> + >> +&ecspi3 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_ecspi3>; >> + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; >> + dmas = <&sdma 7 8 0>, >> + <&sdma 8 8 0>; >> + dma-names = "rx", "tx"; >> + status = "okay"; >> + >> + spi_dev1: spi@0 { >> + compatible = "linux,spidev"; >> + spi-max-frequency = <57600000>; >> + reg = <0>; >> + }; >> +}; >> + >> +ðphy1 { >> + status = "okay"; >> +}; >> + >> +&fec1 { >> + status = "okay"; >> +}; >> + >> +&fec2 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_enet2>; >> + phy-mode = "rmii"; >> + phy-handle = <ðphy2>; >> + status = "okay"; >> +}; >> + >> +&i2c1 { >> + status = "okay"; >> + >> + i2c_rtc: rtc@68 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_rtc_int>; >> + compatible = "microcrystal,rv4162"; >> + reg = <0x68>; >> + interrupt-parent = <&gpio5>; >> + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; >> + }; >> + >> + tmp102: tmp@49 { > > Sort the nodes in order of unit-address. > >> + compatible = "ti,tmp102"; >> + reg = <0x49>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_tempsense>; >> + interrupt-parent = <&gpio5>; >> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; >> + #thermal-sensor-cells = <1>; >> + }; >> +}; >> + >> +&i2c2 { >> + pinctrl-names = "default", "gpio"; >> + pinctrl-0 = <&pinctrl_i2c2>; >> + pinctrl-1 = <&pinctrl_i2c2_gpio>; >> + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + status = "okay"; >> +}; >> + >> +&i2c3 { >> + pinctrl-names = "default", "gpio"; >> + pinctrl-0 = <&pinctrl_i2c3>; >> + pinctrl-1 = <&pinctrl_i2c3_gpio>; >> + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + status = "okay"; >> +}; >> + >> +&i2c4 { >> + pinctrl-names = "default", "gpio"; >> + pinctrl-0 = <&pinctrl_i2c4>; >> + pinctrl-1 = <&pinctrl_i2c4_gpio>; >> + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + status = "okay"; >> +}; >> + >> +&mdio { >> + ethphy2: ethernet-phy@2 { >> + reg = <2>; >> + micrel,led-mode = <1>; >> + clocks = <&clks IMX6UL_CLK_ENET2_REF>; >> + clock-names = "rmii-ref"; >> + status = "okay"; >> + }; >> +}; >> + >> +&pwm3 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pwm3>; >> + status = "okay"; >> +}; >> + >> +&pwm6 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pwm6>; >> + status = "okay"; >> +}; >> + >> +&pwm7 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pwm7>; >> + status = "okay"; >> +}; >> + >> +&pwm8 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pwm8>; >> + status = "okay"; >> +}; >> + >> +&uart3 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart3>; >> + status = "okay"; >> +}; >> + >> +/* UART4 * RS485 */ >> +&uart4 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart4>; >> + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; >> + rs485-rts-active-high; >> + linux,rs485-enabled-at-boot-time; >> + status = "okay"; >> +}; >> + >> +/* UART5 * RS232 */ >> +&uart5 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart5>; >> + uart-has-rtscts; >> + status = "okay"; >> +}; >> + >> +&uart7 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart7>; >> + status = "okay"; >> +}; >> + >> +/* USB */ >> +&usbotg1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_usb_otg1>; >> + vbus-supply = <®_usb_otg1_vbus>; >> + dr_mode = "host"; >> + disable-over-current; >> + status = "okay"; >> +}; >> + >> +&usbotg2 { >> + vbus-supply = <®_usb_hub_vbus>; >> + disable-over-current; >> + dr_mode = "host"; >> + status = "okay"; >> +}; >> + >> +&usdhc1 { >> + pinctrl-names = "default", "state_100mhz", "state_200mhz"; >> + pinctrl-0 = <&pinctrl_usdhc1>; >> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; >> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; >> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; >> + no-1-8-v; >> + keep-power-in-suspend; >> + wakeup-source; >> + status = "okay"; >> +}; >> + >> +&usdhc2 { >> + status = "disabled"; >> +}; >> + >> +&iomuxc_snvs { >> + > > Drop this newline. > >> + pinctrl_rtc_int: rtcintgrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 >> + >; >> + }; >> + >> + pinctrl_stmpe: stmpegrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 >> + >; >> + }; >> + >> + pinctrl_tempsense: tempsensegrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 >> + >; >> + }; >> + >> + pinctrl_tpm: tpmgrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 >> + >; >> + }; >> + >> + pinctrl_usbhubpwr: usbhubpwrgrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 >> + >; >> + }; >> + >> + pinctrl_user_leds_snvs: user_ledsgrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 >> + >; >> + }; >> +}; >> + >> +&iomuxc { >> + > > Drop this newline. > >> + pinctrl_gpio: gpio_gpiogrp { > > Could you name these pinctrl nodes more consistently. If you really > need some delimiter in node name, hyphen rather than underscore is > recommended. > > Shawn > >> + fsl,pins = < >> + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ >> + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ >> + >; >> + }; >> + >> + pinctrl_gpio_keys: gpio_keysgrp { >> + fsl,pins = < >> + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 >> + >; >> + }; >> + >> + pinctrl_ecspi3: ecspi3grp { >> + fsl,pins = < >> + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 >> + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 >> + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 >> + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 >> + >; >> + }; >> + >> + pinctrl_ecspi1: ecspi1grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 >> + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 >> + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 >> + >; >> + }; >> + >> + pinctrl_ecspi1_cs: ecspi1csgrp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 >> + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 >> + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 >> + >; >> + }; >> + >> + >> + pinctrl_enet2: enet2grp { >> + fsl,pins = < >> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 >> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 >> + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 >> + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 >> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 >> + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 >> + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 >> + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 >> + >; >> + }; >> + >> + pinctrl_flexcan1: flexcan1grp { >> + fsl,pins = < >> + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 >> + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_flexcan2: flexcan2grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 >> + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 >> + >; >> + }; >> + >> + princtrl_flexcan2_en: flexcan2engrp { >> + fsl,pins = < >> + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 >> + >; >> + }; >> + >> + pinctrl_i2c2: i2c2grp { >> + fsl,pins = < >> + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 >> + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c2_gpio: i2c2gpiogrp { >> + fsl,pins = < >> + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 >> + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c3: i2c3grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 >> + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c3_gpio: i2c3gpiogrp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 >> + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c4: i2c4grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 >> + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c4_gpio: i2c4gpiogrp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 >> + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 >> + >; >> + }; >> + >> + pinctrl_pwm3: pwm3grp { >> + fsl,pins = < >> + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_pwm6: pwm6grp { >> + fsl,pins = < >> + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_pwm7: pwm7grp { >> + fsl,pins = < >> + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_pwm8: pwm8grp { >> + fsl,pins = < >> + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_s25fl064_hold: s25fl064_holdgrp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 >> + >; >> + }; >> + >> + pinctrl_sai2: sai2grp { >> + fsl,pins = < >> + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 >> + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 >> + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 >> + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 >> + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 >> + >; >> + }; >> + >> + pinctrl_uart3: uart3grp { >> + fsl,pins = < >> + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 >> + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 >> + >; >> + }; >> + >> + pinctrl_uart4: uart4grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 >> + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 >> + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 >> + >; >> + }; >> + >> + pinctrl_uart5: uart5grp { >> + fsl,pins = < >> + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 >> + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 >> + >; >> + }; >> + >> + pinctrl_uart7: uart7grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 >> + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 >> + >; >> + }; >> + >> + pinctrl_usb_otg1: usbotg1grp { >> + fsl,pins = < >> + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 >> + >; >> + }; >> + >> + pinctrl_usbotg1pwr: usbotg1pwrgrp { >> + fsl,pins = < >> + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 >> + >; >> + }; >> + >> + pinctrl_usdhc1: usdhc1grp { >> + fsl,pins = < >> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 >> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 >> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 >> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 >> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 >> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 >> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 >> + >; >> + }; >> + >> + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { >> + fsl,pins = < >> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 >> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 >> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 >> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 >> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 >> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >> + >; >> + }; >> + >> + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { >> + fsl,pins = < >> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 >> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 >> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 >> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 >> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 >> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >> + >; >> + }; >> + >> + pinctrl_user_leds: user_ledsgrp { >> + fsl,pins = < >> + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 >> + >; >> + }; >> +}; >> -- >> 2.25.1 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 2/4] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL @ 2022-02-17 6:47 ` Andrej Picej 0 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-02-17 6:47 UTC (permalink / raw) To: Shawn Guo Cc: devicetree, linux-arm-kernel, robh+dt, kernel, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas Hi Shawn, I will fix what you pointed out and send a v2. Thanks for your review. On 12. 02. 22 06:43, Shawn Guo wrote: > On Mon, Jan 31, 2022 at 09:05:24AM +0100, Andrej Picej wrote: >> From: Alexander Bauer <a.bauer@phytec.de> >> >> Add support for the PHYTEC phyGATE-Tauri-S with i.MX 6ULL with eMMC or >> NAND. >> >> Supported features: >> * eMMC/NAND >> * i2c RTC >> * i2c TEMP >> * PMIC >> * PWM >> * debug UART >> * CAN >> * SD card >> * 2x 1Gbit Ethernet >> * RS232/RS485 >> * USB 2.0 Host >> * TPM >> * SPI-NOR >> >> Signed-off-by: Alexander Bauer <a.bauer@phytec.de> >> Signed-off-by: Jens Lang <j.lang@phytec.de> >> Signed-off-by: Andrej Picej <andrej.picej@norik.com> >> --- >> arch/arm/boot/dts/Makefile | 2 + >> .../boot/dts/imx6ull-phytec-tauri-emmc.dts | 20 + >> .../boot/dts/imx6ull-phytec-tauri-nand.dts | 20 + >> arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi | 605 ++++++++++++++++++ >> 4 files changed, 647 insertions(+) >> create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts >> create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts >> create mode 100644 arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi >> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index 235ad559acb2..f50270b9965a 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -704,6 +704,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ >> imx6ull-phytec-segin-ff-rdk-nand.dtb \ >> imx6ull-phytec-segin-ff-rdk-emmc.dtb \ >> imx6ull-phytec-segin-lc-rdk-nand.dtb \ >> + imx6ull-phytec-tauri-nand.dtb \ >> + imx6ull-phytec-tauri-emmc.dtb \ > > Keep them sort alphabetically. > >> imx6ulz-14x14-evk.dtb \ >> imx6ulz-bsh-smm-m2.dtb >> dtb-$(CONFIG_SOC_IMX7D) += \ >> diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts >> new file mode 100644 >> index 000000000000..14adb87da911 >> --- /dev/null >> +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-emmc.dts >> @@ -0,0 +1,20 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH >> + * Author: Alexander Bauer <a.bauer@phytec.de> >> + */ >> + >> +/dts-v1/; >> +#include "imx6ull-phytec-tauri.dtsi" >> + >> +/ { >> + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; >> + compatible = "phytec,imx6ull-phygate-tauri", >> + "phytec,imx6ull-phygate-tauri-emmc", >> + "phytec,imx6ull-pcl063", "fsl,imx6ull"; >> +}; >> + >> +/* EMMC-Version */ >> +&usdhc2 { >> + status = "okay"; >> +}; >> diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts >> new file mode 100644 >> index 000000000000..ae396ac63443 >> --- /dev/null >> +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri-nand.dts >> @@ -0,0 +1,20 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH >> + * Author: Alexander Bauer <a.bauer@phytec.de> >> + */ >> + >> +/dts-v1/; >> +#include "imx6ull-phytec-tauri.dtsi" >> + >> +/ { >> + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; >> + compatible = "phytec,imx6ull-phygate-tauri", >> + "phytec,imx6ull-phygate-tauri-nand", >> + "phytec,imx6ull-pcl063", "fsl,imx6ull"; >> +}; >> + >> +/* NAND-Version */ >> +&gpmi { >> + status = "okay"; >> +}; >> diff --git a/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi >> new file mode 100644 >> index 000000000000..62a70d80c009 >> --- /dev/null >> +++ b/arch/arm/boot/dts/imx6ull-phytec-tauri.dtsi >> @@ -0,0 +1,605 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2021 PHYTEC Messtechnik GmbH >> + * Author: Alexander Bauer <a.bauer@phytec.de> >> + */ >> + >> +/dts-v1/; >> +#include "imx6ull.dtsi" >> +#include "imx6ull-phytec-phycore-som.dtsi" >> + >> +/ { >> + >> + model = "PHYTEC phyGate-Tauri i.MX6 UltraLite"; >> + compatible = "phytec,imx6ull-phygate-tauri", >> + "phytec,imx6ull-pcl063", "fsl,imx6ull"; >> + >> + aliases { >> + rtc0 = &i2c_rtc; >> + rtc1 = &snvs_rtc; >> + }; >> + >> + gpio_keys: gpio-keys { >> + compatible = "gpio-key"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_gpio_keys>; >> + >> + key { >> + label = "KEY-A"; >> + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; >> + linux,code = <30>; > > Use define in include/dt-bindings/input/linux-event-codes.h > >> + wakeup-source; >> + }; >> + }; >> + >> + reg_adc1_vref_3v3: regulator-vref-3v3 { >> + compatible = "regulator-fixed"; >> + regulator-name = "vref-3v3"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + }; >> + >> + reg_s25fl064_hold: regulator-s25fl064-hold { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_s25fl064_hold>; >> + compatible = "regulator-fixed"; >> + regulator-name = "s25fl064_hold"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + regulator-always-on; >> + }; >> + >> + reg_usb_hub_vbus: regulator-hub-otg1-vbus { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_usbhubpwr>; >> + compatible = "regulator-fixed"; >> + regulator-name = "usb_hub_vbus"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + regulator-always-on; >> + }; >> + >> + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_usbotg1pwr>; >> + compatible = "regulator-fixed"; >> + regulator-name = "usb_otg1_vbus"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + regulator-always-on; >> + }; >> + >> + user_leds: user-leds { >> + compatible = "gpio-leds"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_user_leds>, >> + <&pinctrl_user_leds_snvs>; >> + >> + user-led1 { >> + label = "yellow"; >> + gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; >> + linux,default-trigger = "off"; >> + }; >> + >> + user-led2 { >> + label = "red"; >> + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; >> + linux,default-trigger = "off"; >> + }; >> + }; >> +}; >> + >> +&can1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_flexcan1>; >> + status = "okay"; >> +}; >> + >> +&can2 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_flexcan2>; >> + status = "okay"; >> +}; >> + >> +&ecspi1 { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + fsl,spi-num-chipselects = <3>; > > The property is no longer supported. > >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_ecspi1>, >> + <&pinctrl_ecspi1_cs>; >> + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>, >> + <&gpio3 10 GPIO_ACTIVE_LOW>, >> + <&gpio3 11 GPIO_ACTIVE_LOW>; >> + status = "okay"; >> + >> + spi_dev0: spi@0 { >> + compatible = "linux,spidev"; > > Not supported. > >> + spi-max-frequency = <57600000>; >> + reg = <0>; >> + }; >> + >> + tpm_tis: tpm@1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_tpm>; >> + compatible = "tcg,tpm_tis-spi"; >> + reg = <1>; >> + spi-max-frequency = <20000000>; >> + interrupt-parent = <&gpio5>; >> + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; >> + status = "okay"; > > We generally use okay status to flip a disabled device. You can save it > if that's not the case. > >> + }; >> + >> +/* S25FL064P */ > > Not sure this comment is so useful. If you need a comment, as least > indent it properly. > >> + s25fl064: flash@2 { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = " jedec,spi-nor"; >> + reg = <2>; >> + spi-max-frequency = <40000000>; >> + m25p,fast-read; >> + status = "disabled"; >> + }; >> +}; >> + >> +&ecspi3 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_ecspi3>; >> + cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; >> + dmas = <&sdma 7 8 0>, >> + <&sdma 8 8 0>; >> + dma-names = "rx", "tx"; >> + status = "okay"; >> + >> + spi_dev1: spi@0 { >> + compatible = "linux,spidev"; >> + spi-max-frequency = <57600000>; >> + reg = <0>; >> + }; >> +}; >> + >> +ðphy1 { >> + status = "okay"; >> +}; >> + >> +&fec1 { >> + status = "okay"; >> +}; >> + >> +&fec2 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_enet2>; >> + phy-mode = "rmii"; >> + phy-handle = <ðphy2>; >> + status = "okay"; >> +}; >> + >> +&i2c1 { >> + status = "okay"; >> + >> + i2c_rtc: rtc@68 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_rtc_int>; >> + compatible = "microcrystal,rv4162"; >> + reg = <0x68>; >> + interrupt-parent = <&gpio5>; >> + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; >> + }; >> + >> + tmp102: tmp@49 { > > Sort the nodes in order of unit-address. > >> + compatible = "ti,tmp102"; >> + reg = <0x49>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_tempsense>; >> + interrupt-parent = <&gpio5>; >> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; >> + #thermal-sensor-cells = <1>; >> + }; >> +}; >> + >> +&i2c2 { >> + pinctrl-names = "default", "gpio"; >> + pinctrl-0 = <&pinctrl_i2c2>; >> + pinctrl-1 = <&pinctrl_i2c2_gpio>; >> + sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + status = "okay"; >> +}; >> + >> +&i2c3 { >> + pinctrl-names = "default", "gpio"; >> + pinctrl-0 = <&pinctrl_i2c3>; >> + pinctrl-1 = <&pinctrl_i2c3_gpio>; >> + sda-gpios = <&gpio3 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + scl-gpios = <&gpio3 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + status = "okay"; >> +}; >> + >> +&i2c4 { >> + pinctrl-names = "default", "gpio"; >> + pinctrl-0 = <&pinctrl_i2c4>; >> + pinctrl-1 = <&pinctrl_i2c4_gpio>; >> + sda-gpios = <&gpio3 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + scl-gpios = <&gpio3 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; >> + status = "okay"; >> +}; >> + >> +&mdio { >> + ethphy2: ethernet-phy@2 { >> + reg = <2>; >> + micrel,led-mode = <1>; >> + clocks = <&clks IMX6UL_CLK_ENET2_REF>; >> + clock-names = "rmii-ref"; >> + status = "okay"; >> + }; >> +}; >> + >> +&pwm3 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pwm3>; >> + status = "okay"; >> +}; >> + >> +&pwm6 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pwm6>; >> + status = "okay"; >> +}; >> + >> +&pwm7 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pwm7>; >> + status = "okay"; >> +}; >> + >> +&pwm8 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_pwm8>; >> + status = "okay"; >> +}; >> + >> +&uart3 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart3>; >> + status = "okay"; >> +}; >> + >> +/* UART4 * RS485 */ >> +&uart4 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart4>; >> + rts-gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>; >> + rs485-rts-active-high; >> + linux,rs485-enabled-at-boot-time; >> + status = "okay"; >> +}; >> + >> +/* UART5 * RS232 */ >> +&uart5 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart5>; >> + uart-has-rtscts; >> + status = "okay"; >> +}; >> + >> +&uart7 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_uart7>; >> + status = "okay"; >> +}; >> + >> +/* USB */ >> +&usbotg1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_usb_otg1>; >> + vbus-supply = <®_usb_otg1_vbus>; >> + dr_mode = "host"; >> + disable-over-current; >> + status = "okay"; >> +}; >> + >> +&usbotg2 { >> + vbus-supply = <®_usb_hub_vbus>; >> + disable-over-current; >> + dr_mode = "host"; >> + status = "okay"; >> +}; >> + >> +&usdhc1 { >> + pinctrl-names = "default", "state_100mhz", "state_200mhz"; >> + pinctrl-0 = <&pinctrl_usdhc1>; >> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; >> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; >> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; >> + no-1-8-v; >> + keep-power-in-suspend; >> + wakeup-source; >> + status = "okay"; >> +}; >> + >> +&usdhc2 { >> + status = "disabled"; >> +}; >> + >> +&iomuxc_snvs { >> + > > Drop this newline. > >> + pinctrl_rtc_int: rtcintgrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 >> + >; >> + }; >> + >> + pinctrl_stmpe: stmpegrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059 >> + >; >> + }; >> + >> + pinctrl_tempsense: tempsensegrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 >> + >; >> + }; >> + >> + pinctrl_tpm: tpmgrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x17059 >> + >; >> + }; >> + >> + pinctrl_usbhubpwr: usbhubpwrgrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x17059 >> + >; >> + }; >> + >> + pinctrl_user_leds_snvs: user_ledsgrp { >> + fsl,pins = < >> + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 >> + >; >> + }; >> +}; >> + >> +&iomuxc { >> + > > Drop this newline. > >> + pinctrl_gpio: gpio_gpiogrp { > > Could you name these pinctrl nodes more consistently. If you really > need some delimiter in node name, hyphen rather than underscore is > recommended. > > Shawn > >> + fsl,pins = < >> + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* nUART_MUX_RS232 */ >> + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* nUART_MUX_DUAL_RX_TX */ >> + >; >> + }; >> + >> + pinctrl_gpio_keys: gpio_keysgrp { >> + fsl,pins = < >> + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x79 >> + >; >> + }; >> + >> + pinctrl_ecspi3: ecspi3grp { >> + fsl,pins = < >> + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x100b1 >> + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x100b1 >> + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x100b1 >> + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 >> + >; >> + }; >> + >> + pinctrl_ecspi1: ecspi1grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 >> + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 >> + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 >> + >; >> + }; >> + >> + pinctrl_ecspi1_cs: ecspi1csgrp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x10b0 >> + MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x10b0 >> + MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x10b0 >> + >; >> + }; >> + >> + >> + pinctrl_enet2: enet2grp { >> + fsl,pins = < >> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 >> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 >> + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 >> + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 >> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 >> + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 >> + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 >> + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 >> + >; >> + }; >> + >> + pinctrl_flexcan1: flexcan1grp { >> + fsl,pins = < >> + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 >> + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_flexcan2: flexcan2grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0b0b0 >> + MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0b0b0 >> + >; >> + }; >> + >> + princtrl_flexcan2_en: flexcan2engrp { >> + fsl,pins = < >> + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 >> + >; >> + }; >> + >> + pinctrl_i2c2: i2c2grp { >> + fsl,pins = < >> + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0xb0 >> + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c2_gpio: i2c2gpiogrp { >> + fsl,pins = < >> + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 >> + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c3: i2c3grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA01__I2C3_SCL 0xb0 >> + MX6UL_PAD_LCD_DATA00__I2C3_SDA 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c3_gpio: i2c3gpiogrp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0xb0 >> + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c4: i2c4grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA03__I2C4_SCL 0xb0 >> + MX6UL_PAD_LCD_DATA02__I2C4_SDA 0xb0 >> + >; >> + }; >> + >> + pinctrl_i2c4_gpio: i2c4gpiogrp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0xb0 >> + MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0xb0 >> + >; >> + }; >> + >> + pinctrl_pwm3: pwm3grp { >> + fsl,pins = < >> + MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_pwm6: pwm6grp { >> + fsl,pins = < >> + MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_pwm7: pwm7grp { >> + fsl,pins = < >> + MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_pwm8: pwm8grp { >> + fsl,pins = < >> + MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0b0b0 >> + >; >> + }; >> + >> + pinctrl_s25fl064_hold: s25fl064_holdgrp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x100b1 >> + >; >> + }; >> + >> + pinctrl_sai2: sai2grp { >> + fsl,pins = < >> + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 >> + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 >> + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 >> + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 >> + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 >> + >; >> + }; >> + >> + pinctrl_uart3: uart3grp { >> + fsl,pins = < >> + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 >> + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 >> + >; >> + }; >> + >> + pinctrl_uart4: uart4grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1 >> + MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1 >> + MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x1b0b1 >> + >; >> + }; >> + >> + pinctrl_uart5: uart5grp { >> + fsl,pins = < >> + MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 >> + MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 >> + >; >> + }; >> + >> + pinctrl_uart7: uart7grp { >> + fsl,pins = < >> + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x1b0b1 >> + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x1b0b1 >> + >; >> + }; >> + >> + pinctrl_usb_otg1: usbotg1grp { >> + fsl,pins = < >> + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x80 >> + >; >> + }; >> + >> + pinctrl_usbotg1pwr: usbotg1pwrgrp { >> + fsl,pins = < >> + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x17059 >> + >; >> + }; >> + >> + pinctrl_usdhc1: usdhc1grp { >> + fsl,pins = < >> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 >> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 >> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 >> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 >> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 >> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 >> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 >> + >; >> + }; >> + >> + pinctrl_usdhc1_100mhz: usdhc1100mhzgrp { >> + fsl,pins = < >> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 >> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 >> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 >> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 >> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 >> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 >> + >; >> + }; >> + >> + pinctrl_usdhc1_200mhz: usdhc1200mhzgrp { >> + fsl,pins = < >> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 >> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 >> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 >> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 >> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 >> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 >> + >; >> + }; >> + >> + pinctrl_user_leds: user_ledsgrp { >> + fsl,pins = < >> + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x79 >> + >; >> + }; >> +}; >> -- >> 2.25.1 >> ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH RESEND 3/4] ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance 2022-01-31 8:05 ` Andrej Picej @ 2022-01-31 8:05 ` Andrej Picej -1 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw) To: devicetree, linux-arm-kernel Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas From: Yunus Bas <y.bas@phytec.de> According to the NXP usb compliance reference, the USB data lines for Full/Low speed are connected to the ARM USB LDO, which is set to minimum-voltage = 2.6V and maximum-voltage = 3.4 V. When the regulator is deactivated, the data lines are defaulty driven with 2.6V, which is not USB Full-Speed compliant. To be compliant, we need to activate the USB LDO regulator and set it to the value of 3V, which is the specified value in the USB specification. Signed-off-by: Yunus Bas <y.bas@phytec.de> Signed-off-by: Andrej Picej <andrej.picej@norik.com> --- arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi index 3cddc68917a0..2e03be3d43ec 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi @@ -83,6 +83,11 @@ eeprom@52 { }; }; +®_3p0 { + regulator-min-microvolt = <3000000>; + regulator-always-on; +}; + &snvs_poweroff { status = "okay"; }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH RESEND 3/4] ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance @ 2022-01-31 8:05 ` Andrej Picej 0 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw) To: devicetree, linux-arm-kernel Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas From: Yunus Bas <y.bas@phytec.de> According to the NXP usb compliance reference, the USB data lines for Full/Low speed are connected to the ARM USB LDO, which is set to minimum-voltage = 2.6V and maximum-voltage = 3.4 V. When the regulator is deactivated, the data lines are defaulty driven with 2.6V, which is not USB Full-Speed compliant. To be compliant, we need to activate the USB LDO regulator and set it to the value of 3V, which is the specified value in the USB specification. Signed-off-by: Yunus Bas <y.bas@phytec.de> Signed-off-by: Andrej Picej <andrej.picej@norik.com> --- arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi index 3cddc68917a0..2e03be3d43ec 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi @@ -83,6 +83,11 @@ eeprom@52 { }; }; +®_3p0 { + regulator-min-microvolt = <3000000>; + regulator-always-on; +}; + &snvs_poweroff { status = "okay"; }; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 3/4] ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance 2022-01-31 8:05 ` Andrej Picej @ 2022-02-12 5:46 ` Shawn Guo -1 siblings, 0 replies; 20+ messages in thread From: Shawn Guo @ 2022-02-12 5:46 UTC (permalink / raw) To: Andrej Picej Cc: devicetree, linux-arm-kernel, robh+dt, kernel, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas On Mon, Jan 31, 2022 at 09:05:25AM +0100, Andrej Picej wrote: > From: Yunus Bas <y.bas@phytec.de> > > According to the NXP usb compliance reference, the USB data lines for > Full/Low speed are connected to the ARM USB LDO, which is set to > minimum-voltage = 2.6V and maximum-voltage = 3.4 V. When the regulator > is deactivated, the data lines are defaulty driven with 2.6V, which is > not USB Full-Speed compliant. To be compliant, we need to activate the > USB LDO regulator and set it to the value of 3V, which is the specified > value in the USB specification. > > Signed-off-by: Yunus Bas <y.bas@phytec.de> > Signed-off-by: Andrej Picej <andrej.picej@norik.com> > --- > arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi > index 3cddc68917a0..2e03be3d43ec 100644 > --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi > +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi > @@ -83,6 +83,11 @@ eeprom@52 { > }; > }; > > +®_3p0 { > + regulator-min-microvolt = <3000000>; > + regulator-always-on; Rather than setting it always-on, shouldn't the consumer of the regulator turn it on/off as needed? Shawn > +}; > + > &snvs_poweroff { > status = "okay"; > }; > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 3/4] ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance @ 2022-02-12 5:46 ` Shawn Guo 0 siblings, 0 replies; 20+ messages in thread From: Shawn Guo @ 2022-02-12 5:46 UTC (permalink / raw) To: Andrej Picej Cc: devicetree, linux-arm-kernel, robh+dt, kernel, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas On Mon, Jan 31, 2022 at 09:05:25AM +0100, Andrej Picej wrote: > From: Yunus Bas <y.bas@phytec.de> > > According to the NXP usb compliance reference, the USB data lines for > Full/Low speed are connected to the ARM USB LDO, which is set to > minimum-voltage = 2.6V and maximum-voltage = 3.4 V. When the regulator > is deactivated, the data lines are defaulty driven with 2.6V, which is > not USB Full-Speed compliant. To be compliant, we need to activate the > USB LDO regulator and set it to the value of 3V, which is the specified > value in the USB specification. > > Signed-off-by: Yunus Bas <y.bas@phytec.de> > Signed-off-by: Andrej Picej <andrej.picej@norik.com> > --- > arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi > index 3cddc68917a0..2e03be3d43ec 100644 > --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi > +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi > @@ -83,6 +83,11 @@ eeprom@52 { > }; > }; > > +®_3p0 { > + regulator-min-microvolt = <3000000>; > + regulator-always-on; Rather than setting it always-on, shouldn't the consumer of the regulator turn it on/off as needed? Shawn > +}; > + > &snvs_poweroff { > status = "okay"; > }; > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 3/4] ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance 2022-02-12 5:46 ` Shawn Guo @ 2022-02-18 9:16 ` Andrej Picej -1 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-02-18 9:16 UTC (permalink / raw) To: Shawn Guo Cc: devicetree, linux-arm-kernel, robh+dt, kernel, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas On 12. 02. 22 06:46, Shawn Guo wrote: > On Mon, Jan 31, 2022 at 09:05:25AM +0100, Andrej Picej wrote: >> From: Yunus Bas <y.bas@phytec.de> >> >> According to the NXP usb compliance reference, the USB data lines for >> Full/Low speed are connected to the ARM USB LDO, which is set to >> minimum-voltage = 2.6V and maximum-voltage = 3.4 V. When the regulator >> is deactivated, the data lines are defaulty driven with 2.6V, which is >> not USB Full-Speed compliant. To be compliant, we need to activate the >> USB LDO regulator and set it to the value of 3V, which is the specified >> value in the USB specification. >> >> Signed-off-by: Yunus Bas <y.bas@phytec.de> >> Signed-off-by: Andrej Picej <andrej.picej@norik.com> >> --- >> arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi >> index 3cddc68917a0..2e03be3d43ec 100644 >> --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi >> +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi >> @@ -83,6 +83,11 @@ eeprom@52 { >> }; >> }; >> >> +®_3p0 { >> + regulator-min-microvolt = <3000000>; >> + regulator-always-on; > > Rather than setting it always-on, shouldn't the consumer of the > regulator turn it on/off as needed? Sorry for late response, but I had to look into this a bit to see the reason for using always-on. The consumer should turn the regulator on/off, but the consumer doesn't do that. If regulator is not specified as always-on the regulator stays in disabled state, even when usb device is used. That's why this was added here. This should probably be fixed on consumer side. If you want I can drop the patch from this series and submit the fixed version when the stuff gets resolved. BR, Andrej ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH RESEND 3/4] ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance @ 2022-02-18 9:16 ` Andrej Picej 0 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-02-18 9:16 UTC (permalink / raw) To: Shawn Guo Cc: devicetree, linux-arm-kernel, robh+dt, kernel, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas On 12. 02. 22 06:46, Shawn Guo wrote: > On Mon, Jan 31, 2022 at 09:05:25AM +0100, Andrej Picej wrote: >> From: Yunus Bas <y.bas@phytec.de> >> >> According to the NXP usb compliance reference, the USB data lines for >> Full/Low speed are connected to the ARM USB LDO, which is set to >> minimum-voltage = 2.6V and maximum-voltage = 3.4 V. When the regulator >> is deactivated, the data lines are defaulty driven with 2.6V, which is >> not USB Full-Speed compliant. To be compliant, we need to activate the >> USB LDO regulator and set it to the value of 3V, which is the specified >> value in the USB specification. >> >> Signed-off-by: Yunus Bas <y.bas@phytec.de> >> Signed-off-by: Andrej Picej <andrej.picej@norik.com> >> --- >> arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi >> index 3cddc68917a0..2e03be3d43ec 100644 >> --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi >> +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi >> @@ -83,6 +83,11 @@ eeprom@52 { >> }; >> }; >> >> +®_3p0 { >> + regulator-min-microvolt = <3000000>; >> + regulator-always-on; > > Rather than setting it always-on, shouldn't the consumer of the > regulator turn it on/off as needed? Sorry for late response, but I had to look into this a bit to see the reason for using always-on. The consumer should turn the regulator on/off, but the consumer doesn't do that. If regulator is not specified as always-on the regulator stays in disabled state, even when usb device is used. That's why this was added here. This should probably be fixed on consumer side. If you want I can drop the patch from this series and submit the fixed version when the stuff gets resolved. BR, Andrej _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH RESEND 4/4] ARM: dts: imx6ul: peb-av-02: move to 3 cell pwm 2022-01-31 8:05 ` Andrej Picej @ 2022-01-31 8:05 ` Andrej Picej -1 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw) To: devicetree, linux-arm-kernel Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas Instead of changing default pwm-cells property, use the default "#pwm-cells = <3>" and add the third option. Signed-off-by: Andrej Picej <andrej.picej@norik.com> --- arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi index 7cda6944501d..6ce534a896ef 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -11,7 +11,7 @@ backlight_lcd: backlight-lcd { brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <5>; power-supply = <®_backlight_en>; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; status = "disabled"; }; @@ -91,7 +91,6 @@ lcdif_parallel_out: endpoint { }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; -- 2.25.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH RESEND 4/4] ARM: dts: imx6ul: peb-av-02: move to 3 cell pwm @ 2022-01-31 8:05 ` Andrej Picej 0 siblings, 0 replies; 20+ messages in thread From: Andrej Picej @ 2022-01-31 8:05 UTC (permalink / raw) To: devicetree, linux-arm-kernel Cc: robh+dt, kernel, shawnguo, leoyang.li, krzysztof.kozlowski, festevam, linux, arnd, linux-imx, y.bas Instead of changing default pwm-cells property, use the default "#pwm-cells = <3>" and add the third option. Signed-off-by: Andrej Picej <andrej.picej@norik.com> --- arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi index 7cda6944501d..6ce534a896ef 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-peb-av-02.dtsi @@ -11,7 +11,7 @@ backlight_lcd: backlight-lcd { brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <5>; power-supply = <®_backlight_en>; - pwms = <&pwm3 0 5000000>; + pwms = <&pwm3 0 5000000 0>; status = "disabled"; }; @@ -91,7 +91,6 @@ lcdif_parallel_out: endpoint { }; &pwm3 { - #pwm-cells = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm3>; status = "disabled"; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-02-18 9:17 UTC | newest] Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-01-31 8:05 [PATCH RESEND 0/4] PHYTEC i.MX 6UL/ULL devicetree patches Andrej Picej 2022-01-31 8:05 ` Andrej Picej 2022-01-31 8:05 ` [PATCH RESEND 1/4] dt-bindings: arm: fsl: add PHYTEC phyGATE Tauri i.MX6 ULL Andrej Picej 2022-01-31 8:05 ` Andrej Picej 2022-02-11 13:26 ` Rob Herring 2022-02-11 13:26 ` Rob Herring 2022-01-31 8:05 ` [PATCH RESEND 2/4] ARM: dts: imx6ull: Add support for PHYTEC phyGATE-Tauri-S with i.MX 6ULL Andrej Picej 2022-01-31 8:05 ` Andrej Picej 2022-02-12 5:43 ` Shawn Guo 2022-02-12 5:43 ` Shawn Guo 2022-02-17 6:47 ` Andrej Picej 2022-02-17 6:47 ` Andrej Picej 2022-01-31 8:05 ` [PATCH RESEND 3/4] ARM: dts: imx6ul: phycore: Change USB LDO voltage for usb compliance Andrej Picej 2022-01-31 8:05 ` Andrej Picej 2022-02-12 5:46 ` Shawn Guo 2022-02-12 5:46 ` Shawn Guo 2022-02-18 9:16 ` Andrej Picej 2022-02-18 9:16 ` Andrej Picej 2022-01-31 8:05 ` [PATCH RESEND 4/4] ARM: dts: imx6ul: peb-av-02: move to 3 cell pwm Andrej Picej 2022-01-31 8:05 ` Andrej Picej
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