* [Intel-gfx] [RFC 01/14] drm/i915/pxp: Define PXP component interface
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-08 11:29 ` Rodrigo Vivi
2021-02-06 2:09 ` [Intel-gfx] [RFC 02/14] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio
` (18 subsequent siblings)
19 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx
This will be used for communication between the i915 driver and the mei
one. Defining it in a stand-alone patch to avoid circualr dependedencies
between the patches modifying the 2 drivers.
Split out from an original patch from Huang, Sean Z
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
include/drm/i915_component.h | 1 +
include/drm/i915_pxp_tee_interface.h | 45 ++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 include/drm/i915_pxp_tee_interface.h
diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
index 55c3b123581b..c1e2a43d2d1e 100644
--- a/include/drm/i915_component.h
+++ b/include/drm/i915_component.h
@@ -29,6 +29,7 @@
enum i915_component_type {
I915_COMPONENT_AUDIO = 1,
I915_COMPONENT_HDCP,
+ I915_COMPONENT_PXP
};
/* MAX_PORT is the number of port
diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
new file mode 100644
index 000000000000..0efd14702b4b
--- /dev/null
+++ b/include/drm/i915_pxp_tee_interface.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef _I915_PXP_TEE_INTERFACE_H_
+#define _I915_PXP_TEE_INTERFACE_H_
+
+#include <linux/mutex.h>
+#include <linux/device.h>
+
+/**
+ * struct i915_pxp_component_ops - ops for PXP services.
+ * @owner: Module providing the ops
+ * @send: sends data to PXP
+ * @receive: receives data from PXP
+ */
+struct i915_pxp_component_ops {
+ /**
+ * @owner: owner of the module provding the ops
+ */
+ struct module *owner;
+
+ int (*send)(struct device *dev, const void *message, size_t size);
+ int (*recv)(struct device *dev, void *buffer, size_t size);
+};
+
+/**
+ * struct i915_pxp_component_master - Used for communication between i915
+ * and TEE drivers for the PXP services
+ * @tee_dev: device that provide the PXP service from TEE Bus.
+ * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
+ */
+struct i915_pxp_comp_master {
+ struct device *tee_dev;
+ const struct i915_pxp_component_ops *ops;
+
+ /* To protect the above members. */
+ struct mutex mutex;
+};
+
+#endif /* _I915_TEE_PXP_INTERFACE_H_ */
--
2.29.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 01/14] drm/i915/pxp: Define PXP component interface
2021-02-06 2:09 ` [Intel-gfx] [RFC 01/14] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio
@ 2021-02-08 11:29 ` Rodrigo Vivi
0 siblings, 0 replies; 41+ messages in thread
From: Rodrigo Vivi @ 2021-02-08 11:29 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
On Fri, Feb 05, 2021 at 06:09:12PM -0800, Daniele Ceraolo Spurio wrote:
> This will be used for communication between the i915 driver and the mei
> one. Defining it in a stand-alone patch to avoid circualr dependedencies
> between the patches modifying the 2 drivers.
>
> Split out from an original patch from Huang, Sean Z
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 ++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+)
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
> diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h
> index 55c3b123581b..c1e2a43d2d1e 100644
> --- a/include/drm/i915_component.h
> +++ b/include/drm/i915_component.h
> @@ -29,6 +29,7 @@
> enum i915_component_type {
> I915_COMPONENT_AUDIO = 1,
> I915_COMPONENT_HDCP,
> + I915_COMPONENT_PXP
> };
>
> /* MAX_PORT is the number of port
> diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h
> new file mode 100644
> index 000000000000..0efd14702b4b
> --- /dev/null
> +++ b/include/drm/i915_pxp_tee_interface.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Authors:
> + * Vitaly Lubart <vitaly.lubart@intel.com>
> + */
> +
> +#ifndef _I915_PXP_TEE_INTERFACE_H_
> +#define _I915_PXP_TEE_INTERFACE_H_
> +
> +#include <linux/mutex.h>
> +#include <linux/device.h>
> +
> +/**
> + * struct i915_pxp_component_ops - ops for PXP services.
> + * @owner: Module providing the ops
> + * @send: sends data to PXP
> + * @receive: receives data from PXP
> + */
> +struct i915_pxp_component_ops {
> + /**
> + * @owner: owner of the module provding the ops
> + */
> + struct module *owner;
> +
> + int (*send)(struct device *dev, const void *message, size_t size);
> + int (*recv)(struct device *dev, void *buffer, size_t size);
> +};
> +
> +/**
> + * struct i915_pxp_component_master - Used for communication between i915
Could we have a better name than "master" here?
main? controller?
> + * and TEE drivers for the PXP services
> + * @tee_dev: device that provide the PXP service from TEE Bus.
> + * @pxp_ops: Ops implemented by TEE driver, used by i915 driver.
> + */
> +struct i915_pxp_comp_master {
also use a consistency here:
or we go fully with component or fully with comp...
> + struct device *tee_dev;
> + const struct i915_pxp_component_ops *ops;
> +
> + /* To protect the above members. */
> + struct mutex mutex;
> +};
> +
> +#endif /* _I915_TEE_PXP_INTERFACE_H_ */
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 02/14] mei: pxp: export pavp client to me client bus
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
2021-02-06 2:09 ` [Intel-gfx] [RFC 01/14] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-08 13:13 ` Rodrigo Vivi
2021-02-06 2:09 ` [Intel-gfx] [RFC 03/14] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio
` (17 subsequent siblings)
19 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Tomas Winkler, Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 13 ++
drivers/misc/mei/pxp/Makefile | 7 +
drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++++++++++++++++++++
drivers/misc/mei/pxp/mei_pxp.h | 18 +++
6 files changed, 271 insertions(+)
create mode 100644 drivers/misc/mei/pxp/Kconfig
create mode 100644 drivers/misc/mei/pxp/Makefile
create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index f5fd5b786607..0e0bcd0da852 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -47,3 +47,5 @@ config INTEL_MEI_TXE
Intel Bay Trail
source "drivers/misc/mei/hdcp/Kconfig"
+source "drivers/misc/mei/pxp/Kconfig"
+
diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
index f1c76f7ee804..d8e5165917f2 100644
--- a/drivers/misc/mei/Makefile
+++ b/drivers/misc/mei/Makefile
@@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
CFLAGS_mei-trace.o = -I$(src)
obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
+obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
new file mode 100644
index 000000000000..4029b96afc04
--- /dev/null
+++ b/drivers/misc/mei/pxp/Kconfig
@@ -0,0 +1,13 @@
+
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+config INTEL_MEI_PXP
+ tristate "Intel PXP services of ME Interface"
+ select INTEL_MEI_ME
+ depends on DRM_I915
+ help
+ MEI Support for PXP Services on Intel platforms.
+
+ Enables the ME FW services required for PXP support through
+ I915 display driver of Intel.
diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
new file mode 100644
index 000000000000..0329950d5794
--- /dev/null
+++ b/drivers/misc/mei/pxp/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.
+#
+# Makefile - PXP client driver for Intel MEI Bus Driver.
+
+obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
new file mode 100644
index 000000000000..bd31fce1e6ba
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+/**
+ * DOC: MEI_PXP Client Driver
+ *
+ * The mei_pxp driver acts as a translation layer between PXP
+ * protocol implementer (I915) and ME FW by translating PXP
+ * negotiation messages to ME FW command payloads and vice versa.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/uuid.h>
+#include <linux/mei_cl_bus.h>
+#include <linux/component.h>
+#include <drm/drm_connector.h>
+#include <drm/i915_component.h>
+#include <drm/i915_pxp_tee_interface.h>
+
+#include "mei_pxp.h"
+
+/**
+ * mei_pxp_send_message() - Sends a PXP message to ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @message: a message buffer to send
+ * @size: size of the message
+ * Return: 0 on Success, <0 on Failure
+ */
+static int
+mei_pxp_send_message(struct device *dev, const void *message, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !message)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ /* temporary drop const qualifier till the API is fixed */
+ byte = mei_cldev_send(cldev, (u8 *)message, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
+ return byte;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_pxp_receive_message() - Receives a PXP message from ME FW.
+ * @dev: device corresponding to the mei_cl_device
+ * @buffer: a message buffer to contain the received message
+ * @size: size of the buffer
+ * Return: bytes sent on Success, <0 on Failure
+ */
+static int
+mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
+{
+ struct mei_cl_device *cldev;
+ ssize_t byte;
+
+ if (!dev || !buffer)
+ return -EINVAL;
+
+ cldev = to_mei_cl_device(dev);
+
+ byte = mei_cldev_recv(cldev, buffer, size);
+ if (byte < 0) {
+ dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
+ return byte;
+ }
+
+ return byte;
+}
+
+static const struct i915_pxp_component_ops mei_pxp_ops = {
+ .owner = THIS_MODULE,
+ .send = mei_pxp_send_message,
+ .recv = mei_pxp_receive_message,
+};
+
+static int mei_component_master_bind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+ int ret;
+
+ dev_dbg(dev, "%s\n", __func__);
+ comp_master->ops = &mei_pxp_ops;
+ comp_master->tee_dev = dev;
+ ret = component_bind_all(dev, comp_master);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void mei_component_master_unbind(struct device *dev)
+{
+ struct mei_cl_device *cldev = to_mei_cl_device(dev);
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ dev_dbg(dev, "%s\n", __func__);
+ component_unbind_all(dev, comp_master);
+}
+
+static const struct component_master_ops mei_component_master_ops = {
+ .bind = mei_component_master_bind,
+ .unbind = mei_component_master_unbind,
+};
+
+/**
+ * mei_pxp_component_match - compare function for matching mei pxp.
+ *
+ * The function checks if the driver is i915, the subcomponent is PXP
+ * and the grand parent of pxp and the parent of i915 are the same
+ * PCH device.
+ *
+ * @dev: master device
+ * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
+ * @data: compare data (mei pxp device)
+ *
+ * Return:
+ * * 1 - if components match
+ * * 0 - otherwise
+ */
+static int mei_pxp_component_match(struct device *dev, int subcomponent,
+ void *data)
+{
+ struct device *base = data;
+
+ if (subcomponent != I915_COMPONENT_PXP)
+ return 0;
+
+ if (strcmp(dev->driver->name, "i915") == 0) {
+ base = base->parent;
+ if (!base)
+ return 0;
+
+ base = base->parent;
+ dev = dev->parent;
+ return (base && dev && dev == base);
+ }
+
+ return 0;
+}
+
+static int mei_pxp_probe(struct mei_cl_device *cldev,
+ const struct mei_cl_device_id *id)
+{
+ struct i915_pxp_comp_master *comp_master;
+ struct component_match *master_match;
+ int ret;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
+ goto enable_err_exit;
+ }
+
+ comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
+ if (!comp_master) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ master_match = NULL;
+ component_match_add_typed(&cldev->dev, &master_match,
+ mei_pxp_component_match, &cldev->dev);
+ if (IS_ERR_OR_NULL(master_match)) {
+ ret = -ENOMEM;
+ goto err_exit;
+ }
+
+ mei_cldev_set_drvdata(cldev, comp_master);
+ ret = component_master_add_with_match(&cldev->dev,
+ &mei_component_master_ops,
+ master_match);
+ if (ret < 0) {
+ dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
+ goto err_exit;
+ }
+
+ return 0;
+
+err_exit:
+ mei_cldev_set_drvdata(cldev, NULL);
+ kfree(comp_master);
+ mei_cldev_disable(cldev);
+enable_err_exit:
+ return ret;
+}
+
+static int mei_pxp_remove(struct mei_cl_device *cldev)
+{
+ struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
+
+ component_master_del(&cldev->dev, &mei_component_master_ops);
+ kfree(comp_master);
+ mei_cldev_set_drvdata(cldev, NULL);
+
+ return mei_cldev_disable(cldev);
+}
+
+/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
+#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
+ 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
+
+static struct mei_cl_device_id mei_pxp_tbl[] = {
+ { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
+ { }
+};
+MODULE_DEVICE_TABLE(mei, mei_pxp_tbl);
+
+static struct mei_cl_driver mei_pxp_driver = {
+ .id_table = mei_pxp_tbl,
+ .name = KBUILD_MODNAME,
+ .probe = mei_pxp_probe,
+ .remove = mei_pxp_remove,
+};
+
+module_mei_cl_driver(mei_pxp_driver);
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MEI PXP");
diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h
new file mode 100644
index 000000000000..e7b15373fefd
--- /dev/null
+++ b/drivers/misc/mei/pxp/mei_pxp.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright © 2020 Intel Corporation
+ *
+ * Authors:
+ * Vitaly Lubart <vitaly.lubart@intel.com>
+ */
+
+#ifndef __MEI_PXP_H__
+#define __MEI_PXP_H__
+
+/* me_pxp_status: Enumeration of all PXP Status Codes */
+enum me_pxp_status {
+ ME_PXP_STATUS_SUCCESS = 0x0000,
+
+};
+
+#endif /* __MEI_PXP_H__ */
--
2.29.2
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 02/14] mei: pxp: export pavp client to me client bus
2021-02-06 2:09 ` [Intel-gfx] [RFC 02/14] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio
@ 2021-02-08 13:13 ` Rodrigo Vivi
0 siblings, 0 replies; 41+ messages in thread
From: Rodrigo Vivi @ 2021-02-08 13:13 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, Tomas Winkler, Vitaly Lubart
On Fri, Feb 05, 2021 at 06:09:13PM -0800, Daniele Ceraolo Spurio wrote:
> From: Vitaly Lubart <vitaly.lubart@intel.com>
>
> Export PAVP client to work with i915_cp driver,
s/i915_cp driver/i915's pxp
iirc i915_cp was an experiment to have the pxp as a
separated MFD driver.
> for binding it uses kernel component framework.
>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> ---
> drivers/misc/mei/Kconfig | 2 +
> drivers/misc/mei/Makefile | 1 +
> drivers/misc/mei/pxp/Kconfig | 13 ++
> drivers/misc/mei/pxp/Makefile | 7 +
> drivers/misc/mei/pxp/mei_pxp.c | 230 +++++++++++++++++++++++++++++++++
> drivers/misc/mei/pxp/mei_pxp.h | 18 +++
> 6 files changed, 271 insertions(+)
> create mode 100644 drivers/misc/mei/pxp/Kconfig
> create mode 100644 drivers/misc/mei/pxp/Makefile
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
>
> diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
> index f5fd5b786607..0e0bcd0da852 100644
> --- a/drivers/misc/mei/Kconfig
> +++ b/drivers/misc/mei/Kconfig
> @@ -47,3 +47,5 @@ config INTEL_MEI_TXE
> Intel Bay Trail
>
> source "drivers/misc/mei/hdcp/Kconfig"
> +source "drivers/misc/mei/pxp/Kconfig"
> +
> diff --git a/drivers/misc/mei/Makefile b/drivers/misc/mei/Makefile
> index f1c76f7ee804..d8e5165917f2 100644
> --- a/drivers/misc/mei/Makefile
> +++ b/drivers/misc/mei/Makefile
> @@ -26,3 +26,4 @@ mei-$(CONFIG_EVENT_TRACING) += mei-trace.o
> CFLAGS_mei-trace.o = -I$(src)
>
> obj-$(CONFIG_INTEL_MEI_HDCP) += hdcp/
> +obj-$(CONFIG_INTEL_MEI_PXP) += pxp/
> diff --git a/drivers/misc/mei/pxp/Kconfig b/drivers/misc/mei/pxp/Kconfig
> new file mode 100644
> index 000000000000..4029b96afc04
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/Kconfig
> @@ -0,0 +1,13 @@
> +
> +# SPDX-License-Identifier: GPL-2.0
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +#
> +config INTEL_MEI_PXP
> + tristate "Intel PXP services of ME Interface"
> + select INTEL_MEI_ME
> + depends on DRM_I915
> + help
> + MEI Support for PXP Services on Intel platforms.
> +
> + Enables the ME FW services required for PXP support through
> + I915 display driver of Intel.
> diff --git a/drivers/misc/mei/pxp/Makefile b/drivers/misc/mei/pxp/Makefile
> new file mode 100644
> index 000000000000..0329950d5794
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/Makefile
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.
> +#
> +# Makefile - PXP client driver for Intel MEI Bus Driver.
> +
> +obj-$(CONFIG_INTEL_MEI_PXP) += mei_pxp.o
> diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
> new file mode 100644
> index 000000000000..bd31fce1e6ba
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/mei_pxp.c
> @@ -0,0 +1,230 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +/**
> + * DOC: MEI_PXP Client Driver
> + *
> + * The mei_pxp driver acts as a translation layer between PXP
> + * protocol implementer (I915) and ME FW by translating PXP
> + * negotiation messages to ME FW command payloads and vice versa.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/uuid.h>
> +#include <linux/mei_cl_bus.h>
> +#include <linux/component.h>
> +#include <drm/drm_connector.h>
> +#include <drm/i915_component.h>
> +#include <drm/i915_pxp_tee_interface.h>
> +
> +#include "mei_pxp.h"
> +
> +/**
> + * mei_pxp_send_message() - Sends a PXP message to ME FW.
> + * @dev: device corresponding to the mei_cl_device
> + * @message: a message buffer to send
> + * @size: size of the message
> + * Return: 0 on Success, <0 on Failure
> + */
> +static int
> +mei_pxp_send_message(struct device *dev, const void *message, size_t size)
> +{
> + struct mei_cl_device *cldev;
> + ssize_t byte;
> +
> + if (!dev || !message)
> + return -EINVAL;
> +
> + cldev = to_mei_cl_device(dev);
> +
> + /* temporary drop const qualifier till the API is fixed */
> + byte = mei_cldev_send(cldev, (u8 *)message, size);
> + if (byte < 0) {
> + dev_dbg(dev, "mei_cldev_send failed. %zd\n", byte);
> + return byte;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * mei_pxp_receive_message() - Receives a PXP message from ME FW.
> + * @dev: device corresponding to the mei_cl_device
> + * @buffer: a message buffer to contain the received message
> + * @size: size of the buffer
> + * Return: bytes sent on Success, <0 on Failure
> + */
> +static int
> +mei_pxp_receive_message(struct device *dev, void *buffer, size_t size)
> +{
> + struct mei_cl_device *cldev;
> + ssize_t byte;
> +
> + if (!dev || !buffer)
> + return -EINVAL;
> +
> + cldev = to_mei_cl_device(dev);
> +
> + byte = mei_cldev_recv(cldev, buffer, size);
> + if (byte < 0) {
> + dev_dbg(dev, "mei_cldev_recv failed. %zd\n", byte);
> + return byte;
> + }
> +
> + return byte;
> +}
> +
> +static const struct i915_pxp_component_ops mei_pxp_ops = {
> + .owner = THIS_MODULE,
> + .send = mei_pxp_send_message,
> + .recv = mei_pxp_receive_message,
> +};
> +
> +static int mei_component_master_bind(struct device *dev)
> +{
> + struct mei_cl_device *cldev = to_mei_cl_device(dev);
> + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
> + int ret;
> +
> + dev_dbg(dev, "%s\n", __func__);
> + comp_master->ops = &mei_pxp_ops;
> + comp_master->tee_dev = dev;
> + ret = component_bind_all(dev, comp_master);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static void mei_component_master_unbind(struct device *dev)
> +{
> + struct mei_cl_device *cldev = to_mei_cl_device(dev);
> + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
> +
> + dev_dbg(dev, "%s\n", __func__);
> + component_unbind_all(dev, comp_master);
> +}
> +
> +static const struct component_master_ops mei_component_master_ops = {
> + .bind = mei_component_master_bind,
> + .unbind = mei_component_master_unbind,
> +};
> +
> +/**
> + * mei_pxp_component_match - compare function for matching mei pxp.
> + *
> + * The function checks if the driver is i915, the subcomponent is PXP
> + * and the grand parent of pxp and the parent of i915 are the same
> + * PCH device.
> + *
> + * @dev: master device
> + * @subcomponent: subcomponent to match (I915_COMPONENT_PXP)
> + * @data: compare data (mei pxp device)
> + *
> + * Return:
> + * * 1 - if components match
> + * * 0 - otherwise
> + */
> +static int mei_pxp_component_match(struct device *dev, int subcomponent,
> + void *data)
> +{
> + struct device *base = data;
> +
> + if (subcomponent != I915_COMPONENT_PXP)
> + return 0;
> +
> + if (strcmp(dev->driver->name, "i915") == 0) {
> + base = base->parent;
> + if (!base)
> + return 0;
> +
> + base = base->parent;
> + dev = dev->parent;
> + return (base && dev && dev == base);
> + }
> +
> + return 0;
> +}
> +
> +static int mei_pxp_probe(struct mei_cl_device *cldev,
> + const struct mei_cl_device_id *id)
> +{
> + struct i915_pxp_comp_master *comp_master;
> + struct component_match *master_match;
> + int ret;
> +
> + ret = mei_cldev_enable(cldev);
> + if (ret < 0) {
> + dev_err(&cldev->dev, "mei_cldev_enable Failed. %d\n", ret);
> + goto enable_err_exit;
> + }
> +
> + comp_master = kzalloc(sizeof(*comp_master), GFP_KERNEL);
> + if (!comp_master) {
> + ret = -ENOMEM;
> + goto err_exit;
> + }
> +
> + master_match = NULL;
> + component_match_add_typed(&cldev->dev, &master_match,
> + mei_pxp_component_match, &cldev->dev);
> + if (IS_ERR_OR_NULL(master_match)) {
> + ret = -ENOMEM;
> + goto err_exit;
> + }
> +
> + mei_cldev_set_drvdata(cldev, comp_master);
> + ret = component_master_add_with_match(&cldev->dev,
> + &mei_component_master_ops,
> + master_match);
> + if (ret < 0) {
> + dev_err(&cldev->dev, "Master comp add failed %d\n", ret);
> + goto err_exit;
> + }
> +
> + return 0;
> +
> +err_exit:
> + mei_cldev_set_drvdata(cldev, NULL);
> + kfree(comp_master);
> + mei_cldev_disable(cldev);
> +enable_err_exit:
> + return ret;
> +}
> +
> +static int mei_pxp_remove(struct mei_cl_device *cldev)
> +{
> + struct i915_pxp_comp_master *comp_master = mei_cldev_get_drvdata(cldev);
> +
> + component_master_del(&cldev->dev, &mei_component_master_ops);
> + kfree(comp_master);
> + mei_cldev_set_drvdata(cldev, NULL);
> +
> + return mei_cldev_disable(cldev);
> +}
> +
> +/* fbf6fcf1-96cf-4e2e-a6a6-1bab8cbe36b1 : PAVP GUID*/
> +#define MEI_GUID_PXP GUID_INIT(0xfbf6fcf1, 0x96cf, 0x4e2e, 0xA6, \
> + 0xa6, 0x1b, 0xab, 0x8c, 0xbe, 0x36, 0xb1)
> +
> +static struct mei_cl_device_id mei_pxp_tbl[] = {
> + { .uuid = MEI_GUID_PXP, .version = MEI_CL_VERSION_ANY },
> + { }
> +};
> +MODULE_DEVICE_TABLE(mei, mei_pxp_tbl);
> +
> +static struct mei_cl_driver mei_pxp_driver = {
> + .id_table = mei_pxp_tbl,
> + .name = KBUILD_MODNAME,
> + .probe = mei_pxp_probe,
> + .remove = mei_pxp_remove,
> +};
> +
> +module_mei_cl_driver(mei_pxp_driver);
> +
> +MODULE_AUTHOR("Intel Corporation");
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("MEI PXP");
> diff --git a/drivers/misc/mei/pxp/mei_pxp.h b/drivers/misc/mei/pxp/mei_pxp.h
> new file mode 100644
> index 000000000000..e7b15373fefd
> --- /dev/null
> +++ b/drivers/misc/mei/pxp/mei_pxp.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright © 2020 Intel Corporation
> + *
> + * Authors:
> + * Vitaly Lubart <vitaly.lubart@intel.com>
> + */
> +
> +#ifndef __MEI_PXP_H__
> +#define __MEI_PXP_H__
> +
> +/* me_pxp_status: Enumeration of all PXP Status Codes */
> +enum me_pxp_status {
> + ME_PXP_STATUS_SUCCESS = 0x0000,
> +
> +};
> +
> +#endif /* __MEI_PXP_H__ */
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 03/14] drm/i915/pxp: define PXP device flag and kconfig
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
2021-02-06 2:09 ` [Intel-gfx] [RFC 01/14] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio
2021-02-06 2:09 ` [Intel-gfx] [RFC 02/14] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-08 13:14 ` Rodrigo Vivi
2021-02-06 2:09 ` [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
` (16 subsequent siblings)
19 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx
Ahead of the PXP implementation, define the relevant define flag and
kconfig option.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/Kconfig | 11 +++++++++++
drivers/gpu/drm/i915/i915_drv.h | 4 ++++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 1e1cb245fca7..c55e58bdbe0b 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -130,6 +130,17 @@ config DRM_I915_GVT_KVMGT
Choose this option if you want to enable KVMGT support for
Intel GVT-g.
+config DRM_I915_PXP
+ bool "Enable Intel PXP support for Intel Gen12+ platform"
+ depends on DRM_I915
+ depends on INTEL_MEI && INTEL_MEI_PXP
+ default y
+ help
+ PXP (Protected Xe Path) is an i915 component, available on GEN12+
+ GPUs, that helps to establish the hardware protected session and
+ manage the status of the alive software session, as well as its life
+ cycle.
+
menu "drm/i915 Debugging"
depends on DRM_I915
depends on EXPERT
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2fd7e5039b3..fe1ff025f961 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1779,6 +1779,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
#define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
+#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+ INTEL_INFO(dev_priv)->has_pxp) && \
+ VDBOX_MASK(&dev_priv->gt)
+
/* Only valid when HAS_DISPLAY() is true */
#define INTEL_DISPLAY_ENABLED(dev_priv) \
(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index e6ca1023ffcf..54891f7655e4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -127,6 +127,7 @@ enum intel_ppgtt_type {
func(has_logical_ring_elsq); \
func(has_master_unit_irq); \
func(has_pooled_eu); \
+ func(has_pxp); \
func(has_rc6); \
func(has_rc6p); \
func(has_rps); \
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 03/14] drm/i915/pxp: define PXP device flag and kconfig
2021-02-06 2:09 ` [Intel-gfx] [RFC 03/14] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio
@ 2021-02-08 13:14 ` Rodrigo Vivi
0 siblings, 0 replies; 41+ messages in thread
From: Rodrigo Vivi @ 2021-02-08 13:14 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
On Fri, Feb 05, 2021 at 06:09:14PM -0800, Daniele Ceraolo Spurio wrote:
> Ahead of the PXP implementation, define the relevant define flag and
> kconfig option.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/Kconfig | 11 +++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 4 ++++
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> 3 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
> index 1e1cb245fca7..c55e58bdbe0b 100644
> --- a/drivers/gpu/drm/i915/Kconfig
> +++ b/drivers/gpu/drm/i915/Kconfig
> @@ -130,6 +130,17 @@ config DRM_I915_GVT_KVMGT
> Choose this option if you want to enable KVMGT support for
> Intel GVT-g.
>
> +config DRM_I915_PXP
> + bool "Enable Intel PXP support for Intel Gen12+ platform"
> + depends on DRM_I915
> + depends on INTEL_MEI && INTEL_MEI_PXP
> + default y
> + help
> + PXP (Protected Xe Path) is an i915 component, available on GEN12+
> + GPUs, that helps to establish the hardware protected session and
> + manage the status of the alive software session, as well as its life
> + cycle.
> +
> menu "drm/i915 Debugging"
> depends on DRM_I915
> depends on EXPERT
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a2fd7e5039b3..fe1ff025f961 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1779,6 +1779,10 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
>
> #define HAS_VRR(i915) (INTEL_GEN(i915) >= 12)
>
> +#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
> + INTEL_INFO(dev_priv)->has_pxp) && \
> + VDBOX_MASK(&dev_priv->gt)
> +
> /* Only valid when HAS_DISPLAY() is true */
> #define INTEL_DISPLAY_ENABLED(dev_priv) \
> (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)), !(dev_priv)->params.disable_display)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index e6ca1023ffcf..54891f7655e4 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -127,6 +127,7 @@ enum intel_ppgtt_type {
> func(has_logical_ring_elsq); \
> func(has_master_unit_irq); \
> func(has_pooled_eu); \
> + func(has_pxp); \
> func(has_rc6); \
> func(has_rc6p); \
> func(has_rps); \
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 03/14] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 12:49 ` Chris Wilson
2021-02-06 13:01 ` Chris Wilson
2021-02-06 2:09 ` [Intel-gfx] [RFC 05/14] drm/i915/pxp: set KCR reg init during the boot time Daniele Ceraolo Spurio
` (15 subsequent siblings)
19 siblings, 2 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx
The context is required to send the session termination commands to the
VCS, which will be implemented in a follow-up patch. We can also use the
presence of the context as a check of pxp initialization completion.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/Makefile | 4 ++
drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 61 ++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 35 +++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 ++++++
6 files changed, 123 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index ce01634d4ea7..e2677e8c03e8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -268,6 +268,10 @@ i915-y += \
i915-y += i915_perf.o
+# Protected execution platform (PXP) support
+i915-$(CONFIG_DRM_I915_PXP) += \
+ pxp/intel_pxp.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ca76f93bc03d..daf61db620d6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -20,6 +20,7 @@
#include "intel_uncore.h"
#include "intel_pm.h"
#include "shmem_utils.h"
+#include "pxp/intel_pxp.h"
void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
{
@@ -624,6 +625,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_pxp_init(>->pxp);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -658,6 +661,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
intel_rps_driver_unregister(>->rps);
+ intel_pxp_fini(>->pxp);
+
/*
* Upon unregistering the device to prevent any new users, cancel
* all in-flight requests so that we can quickly unbind the active
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 626af37c7790..324d267eee15 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_types.h"
struct drm_i915_private;
struct i915_ggtt;
@@ -145,6 +146,8 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
} info;
+
+ struct intel_pxp pxp;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
new file mode 100644
index 000000000000..4ddc8a71a3e7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include "intel_pxp.h"
+#include "gt/intel_context.h"
+#include "i915_drv.h"
+
+static int create_vcs_context(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct intel_context *ce = NULL;
+ int i;
+
+ /*
+ * Find the first VCS engine present. We're guaranteed there is one
+ * if we're in this function due to the check in has_pxp
+ */
+ for (i = 0; i < I915_MAX_VCS && !ce; i++)
+ if (HAS_ENGINE(gt, _VCS(i)))
+ ce = intel_context_create(gt->engine[_VCS(i)]);
+
+ if (IS_ERR(ce)) {
+ drm_err(>->i915->drm, "failed to create VCS ctx for PXP\n");
+ return PTR_ERR(ce);
+ }
+
+ pxp->ce = ce;
+
+ return 0;
+}
+
+static void destroy_vcs_context(struct intel_pxp *pxp)
+{
+ intel_context_put(fetch_and_zero(&pxp->ce));
+}
+
+void intel_pxp_init(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ int ret;
+
+ if (!HAS_PXP(gt->i915))
+ return;
+
+ ret = create_vcs_context(pxp);
+ if (ret)
+ return;
+
+ drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
+
+ return;
+}
+
+void intel_pxp_fini(struct intel_pxp *pxp)
+{
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ destroy_vcs_context(pxp);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
new file mode 100644
index 000000000000..e2acd06402cd
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_H__
+#define __INTEL_PXP_H__
+
+#include "gt/intel_gt_types.h"
+#include "intel_pxp_types.h"
+
+static inline struct intel_gt *pxp_to_gt(struct intel_pxp *pxp)
+{
+ return container_of(pxp, struct intel_gt, pxp);
+}
+
+static inline bool intel_pxp_is_enabled(struct intel_pxp *pxp)
+{
+ return pxp->ce;
+}
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_init(struct intel_pxp *pxp);
+void intel_pxp_fini(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_init(struct intel_pxp *pxp)
+{
+}
+
+static inline void intel_pxp_fini(struct intel_pxp *pxp)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
new file mode 100644
index 000000000000..bd12c520e60a
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TYPES_H__
+#define __INTEL_PXP_TYPES_H__
+
+struct intel_context;
+
+struct intel_pxp {
+ struct intel_context *ce;
+};
+
+#endif /* __INTEL_PXP_TYPES_H__ */
--
2.29.2
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^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage
2021-02-06 2:09 ` [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
@ 2021-02-06 12:49 ` Chris Wilson
2021-02-08 18:27 ` Daniele Ceraolo Spurio
2021-02-06 13:01 ` Chris Wilson
1 sibling, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2021-02-06 12:49 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:15)
> The context is required to send the session termination commands to the
> VCS, which will be implemented in a follow-up patch. We can also use the
> presence of the context as a check of pxp initialization completion.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 4 ++
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 61 ++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 35 +++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 ++++++
> 6 files changed, 123 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index ce01634d4ea7..e2677e8c03e8 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -268,6 +268,10 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ca76f93bc03d..daf61db620d6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -20,6 +20,7 @@
> #include "intel_uncore.h"
> #include "intel_pm.h"
> #include "shmem_utils.h"
> +#include "pxp/intel_pxp.h"
>
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> {
> @@ -624,6 +625,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + intel_pxp_init(>->pxp);
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -658,6 +661,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
>
> intel_rps_driver_unregister(>->rps);
>
> + intel_pxp_fini(>->pxp);
> +
> /*
> * Upon unregistering the device to prevent any new users, cancel
> * all in-flight requests so that we can quickly unbind the active
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 626af37c7790..324d267eee15 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_types.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -145,6 +146,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index 000000000000..4ddc8a71a3e7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "intel_pxp.h"
> +#include "gt/intel_context.h"
> +#include "i915_drv.h"
> +
> +static int create_vcs_context(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + struct intel_context *ce = NULL;
> + int i;
> +
> + /*
> + * Find the first VCS engine present. We're guaranteed there is one
> + * if we're in this function due to the check in has_pxp
> + */
> + for (i = 0; i < I915_MAX_VCS && !ce; i++)
> + if (HAS_ENGINE(gt, _VCS(i)))
> + ce = intel_context_create(gt->engine[_VCS(i)]);
Just wondering if
struct intel_engine_cs **vcs_engines = gt->engine_class[CLASS_VIDEO_DECODE];
for (i = 0; i < ARRAY_SIZE(gt->engine_class[CLASS_VIDEO_DECODE]); i++) {
if (!vcs_engines[i])
continue;
ce = intel_context_create(vcs_engines[i]);
break;
}
is a better iterator as it only checks one place of truth about whether
or not the engine exists.
for_each_engine_class(engine, gt, class, i)
A couple of places could use that.
> + if (IS_ERR(ce)) {
> + drm_err(>->i915->drm, "failed to create VCS ctx for PXP\n");
> + return PTR_ERR(ce);
Is the lack of this feature enough to prevent module loading? Surely
userspace will notice and report the lack of the feature?
> + }
> +
> + pxp->ce = ce;
Is protected context then implicitly tried to one engine? i.e.
userspace has to use the same engine as we control invalidation?
Otherwise, everytime we use pxp->ce we must impose barriers across all
gt->vcs.
> +
> + return 0;
> +}
> +
> +static void destroy_vcs_context(struct intel_pxp *pxp)
> +{
> + intel_context_put(fetch_and_zero(&pxp->ce));
> +}
> +
> +void intel_pxp_init(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + int ret;
> +
> + if (!HAS_PXP(gt->i915))
> + return;
> +
> + ret = create_vcs_context(pxp);
> + if (ret)
> + return;
> +
> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
> +
> + return;
> +}
> +
> +void intel_pxp_fini(struct intel_pxp *pxp)
> +{
> + if (!intel_pxp_is_enabled(pxp))
> + return;
> +
> + destroy_vcs_context(pxp);
> +}
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> new file mode 100644
> index 000000000000..e2acd06402cd
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#ifndef __INTEL_PXP_H__
> +#define __INTEL_PXP_H__
> +
> +#include "gt/intel_gt_types.h"
> +#include "intel_pxp_types.h"
> +
> +static inline struct intel_gt *pxp_to_gt(struct intel_pxp *pxp)
> +{
> + return container_of(pxp, struct intel_gt, pxp);
> +}
> +
> +static inline bool intel_pxp_is_enabled(struct intel_pxp *pxp)
const struct intel_pxp *pxp
-Chris
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage
2021-02-06 12:49 ` Chris Wilson
@ 2021-02-08 18:27 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-08 18:27 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 2/6/2021 4:49 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:15)
>> The context is required to send the session termination commands to the
>> VCS, which will be implemented in a follow-up patch. We can also use the
>> presence of the context as a check of pxp initialization completion.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> ---
>> drivers/gpu/drm/i915/Makefile | 4 ++
>> drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp.c | 61 ++++++++++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp.h | 35 +++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 ++++++
>> 6 files changed, 123 insertions(+)
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index ce01634d4ea7..e2677e8c03e8 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -268,6 +268,10 @@ i915-y += \
>>
>> i915-y += i915_perf.o
>>
>> +# Protected execution platform (PXP) support
>> +i915-$(CONFIG_DRM_I915_PXP) += \
>> + pxp/intel_pxp.o
>> +
>> # Post-mortem debug and GPU hang state capture
>> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
>> i915-$(CONFIG_DRM_I915_SELFTEST) += \
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index ca76f93bc03d..daf61db620d6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -20,6 +20,7 @@
>> #include "intel_uncore.h"
>> #include "intel_pm.h"
>> #include "shmem_utils.h"
>> +#include "pxp/intel_pxp.h"
>>
>> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
>> {
>> @@ -624,6 +625,8 @@ int intel_gt_init(struct intel_gt *gt)
>> if (err)
>> goto err_gt;
>>
>> + intel_pxp_init(>->pxp);
>> +
>> goto out_fw;
>> err_gt:
>> __intel_gt_disable(gt);
>> @@ -658,6 +661,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
>>
>> intel_rps_driver_unregister(>->rps);
>>
>> + intel_pxp_fini(>->pxp);
>> +
>> /*
>> * Upon unregistering the device to prevent any new users, cancel
>> * all in-flight requests so that we can quickly unbind the active
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> index 626af37c7790..324d267eee15 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> @@ -23,6 +23,7 @@
>> #include "intel_rc6_types.h"
>> #include "intel_rps_types.h"
>> #include "intel_wakeref.h"
>> +#include "pxp/intel_pxp_types.h"
>>
>> struct drm_i915_private;
>> struct i915_ggtt;
>> @@ -145,6 +146,8 @@ struct intel_gt {
>> /* Slice/subslice/EU info */
>> struct sseu_dev_info sseu;
>> } info;
>> +
>> + struct intel_pxp pxp;
>> };
>>
>> enum intel_gt_scratch_field {
>> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> new file mode 100644
>> index 000000000000..4ddc8a71a3e7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
>> @@ -0,0 +1,61 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright(c) 2020 Intel Corporation.
>> + */
>> +#include "intel_pxp.h"
>> +#include "gt/intel_context.h"
>> +#include "i915_drv.h"
>> +
>> +static int create_vcs_context(struct intel_pxp *pxp)
>> +{
>> + struct intel_gt *gt = pxp_to_gt(pxp);
>> + struct intel_context *ce = NULL;
>> + int i;
>> +
>> + /*
>> + * Find the first VCS engine present. We're guaranteed there is one
>> + * if we're in this function due to the check in has_pxp
>> + */
>> + for (i = 0; i < I915_MAX_VCS && !ce; i++)
>> + if (HAS_ENGINE(gt, _VCS(i)))
>> + ce = intel_context_create(gt->engine[_VCS(i)]);
> Just wondering if
>
> struct intel_engine_cs **vcs_engines = gt->engine_class[CLASS_VIDEO_DECODE];
>
> for (i = 0; i < ARRAY_SIZE(gt->engine_class[CLASS_VIDEO_DECODE]); i++) {
> if (!vcs_engines[i])
> continue;
>
> ce = intel_context_create(vcs_engines[i]);
> break;
> }
>
> is a better iterator as it only checks one place of truth about whether
> or not the engine exists.
>
> for_each_engine_class(engine, gt, class, i)
>
> A couple of places could use that.
>
>> + if (IS_ERR(ce)) {
>> + drm_err(>->i915->drm, "failed to create VCS ctx for PXP\n");
>> + return PTR_ERR(ce);
> Is the lack of this feature enough to prevent module loading? Surely
> userspace will notice and report the lack of the feature?
It's not, and we don't fail the load on this error, it's just used by
intel_pxp_init() to abort PXP enabling.
>
>> + }
>> +
>> + pxp->ce = ce;
> Is protected context then implicitly tried to one engine? i.e.
> userspace has to use the same engine as we control invalidation?
> Otherwise, everytime we use pxp->ce we must impose barriers across all
> gt->vcs.
It's not tied. I considered using a virtual engine, but that needs some
proper testing so better as a follow up step after we have the tests in
place.
Regarding the barriers, I don't think they'd be very helpful. The
teardown process includes an MMIO write after this context completes,
followed by waiting for the irq and then re-creating the session. We
could halt submission of all contexts marked as protected while the
teardown is in progress, but any buffer that was written to using the
old keys is now garbage. The spec says that userspace can detect a
session being re-created but I'm not sure how, let me check with
architecture (I was told that the behavior in the original patch series
was agreed on by all parties so I just stuck to that).
Daniele
>
>> +
>> + return 0;
>> +}
>> +
>> +static void destroy_vcs_context(struct intel_pxp *pxp)
>> +{
>> + intel_context_put(fetch_and_zero(&pxp->ce));
>> +}
>> +
>> +void intel_pxp_init(struct intel_pxp *pxp)
>> +{
>> + struct intel_gt *gt = pxp_to_gt(pxp);
>> + int ret;
>> +
>> + if (!HAS_PXP(gt->i915))
>> + return;
>> +
>> + ret = create_vcs_context(pxp);
>> + if (ret)
>> + return;
>> +
>> + drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
>> +
>> + return;
>> +}
>> +
>> +void intel_pxp_fini(struct intel_pxp *pxp)
>> +{
>> + if (!intel_pxp_is_enabled(pxp))
>> + return;
>> +
>> + destroy_vcs_context(pxp);
>> +}
>> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
>> new file mode 100644
>> index 000000000000..e2acd06402cd
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
>> @@ -0,0 +1,35 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
>> + */
>> +
>> +#ifndef __INTEL_PXP_H__
>> +#define __INTEL_PXP_H__
>> +
>> +#include "gt/intel_gt_types.h"
>> +#include "intel_pxp_types.h"
>> +
>> +static inline struct intel_gt *pxp_to_gt(struct intel_pxp *pxp)
>> +{
>> + return container_of(pxp, struct intel_gt, pxp);
>> +}
>> +
>> +static inline bool intel_pxp_is_enabled(struct intel_pxp *pxp)
> const struct intel_pxp *pxp
> -Chris
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage
2021-02-06 2:09 ` [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
2021-02-06 12:49 ` Chris Wilson
@ 2021-02-06 13:01 ` Chris Wilson
1 sibling, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2021-02-06 13:01 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:15)
> The context is required to send the session termination commands to the
> VCS, which will be implemented in a follow-up patch. We can also use the
> presence of the context as a check of pxp initialization completion.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 4 ++
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 ++
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 61 ++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 35 +++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 15 ++++++
> 6 files changed, 123 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index ce01634d4ea7..e2677e8c03e8 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -268,6 +268,10 @@ i915-y += \
>
> i915-y += i915_perf.o
>
> +# Protected execution platform (PXP) support
> +i915-$(CONFIG_DRM_I915_PXP) += \
> + pxp/intel_pxp.o
> +
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> i915-$(CONFIG_DRM_I915_SELFTEST) += \
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ca76f93bc03d..daf61db620d6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -20,6 +20,7 @@
> #include "intel_uncore.h"
> #include "intel_pm.h"
> #include "shmem_utils.h"
> +#include "pxp/intel_pxp.h"
>
> void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> {
> @@ -624,6 +625,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + intel_pxp_init(>->pxp);
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -658,6 +661,8 @@ void intel_gt_driver_unregister(struct intel_gt *gt)
>
> intel_rps_driver_unregister(>->rps);
>
> + intel_pxp_fini(>->pxp);
> +
> /*
> * Upon unregistering the device to prevent any new users, cancel
> * all in-flight requests so that we can quickly unbind the active
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 626af37c7790..324d267eee15 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> #include "intel_wakeref.h"
> +#include "pxp/intel_pxp_types.h"
>
> struct drm_i915_private;
> struct i915_ggtt;
> @@ -145,6 +146,8 @@ struct intel_gt {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
> } info;
> +
> + struct intel_pxp pxp;
> };
>
> enum intel_gt_scratch_field {
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> new file mode 100644
> index 000000000000..4ddc8a71a3e7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +#include "intel_pxp.h"
> +#include "gt/intel_context.h"
> +#include "i915_drv.h"
> +
> +static int create_vcs_context(struct intel_pxp *pxp)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + struct intel_context *ce = NULL;
> + int i;
> +
> + /*
> + * Find the first VCS engine present. We're guaranteed there is one
> + * if we're in this function due to the check in has_pxp
> + */
> + for (i = 0; i < I915_MAX_VCS && !ce; i++)
> + if (HAS_ENGINE(gt, _VCS(i)))
> + ce = intel_context_create(gt->engine[_VCS(i)]);
This needs to be a pinned context, for failure to execute the invalidation
is not an option.
-Chris
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 05/14] drm/i915/pxp: set KCR reg init during the boot time
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (3 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 04/14] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-08 17:35 ` Rodrigo Vivi
2021-02-06 2:09 ` [Intel-gfx] [RFC 06/14] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio
` (14 subsequent siblings)
19 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Sean Z, Huang
Set the KCR init during the boot time, which is required by hardware,
to allow us doing further protection operation such as sending commands
to GPU or TEE.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 +++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 4ddc8a71a3e7..950daee5b907 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -6,6 +6,24 @@
#include "gt/intel_context.h"
#include "i915_drv.h"
+/* KCR register definitions */
+#define KCR_INIT _MMIO(0x320f0)
+
+/* Setting KCR Init bit is required after system boot */
+#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
+
+static void kcr_pxp_enable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+ _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
+}
+
+static void kcr_pxp_disable(struct intel_gt *gt)
+{
+ intel_uncore_write(gt->uncore, KCR_INIT,
+ _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
+}
+
static int create_vcs_context(struct intel_pxp *pxp)
{
struct intel_gt *gt = pxp_to_gt(pxp);
@@ -43,19 +61,28 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (!HAS_PXP(gt->i915))
return;
+ kcr_pxp_enable(gt);
+
ret = create_vcs_context(pxp);
if (ret)
- return;
+ goto out_kcr;
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
return;
+
+out_kcr:
+ kcr_pxp_disable(gt);
}
void intel_pxp_fini(struct intel_pxp *pxp)
{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
if (!intel_pxp_is_enabled(pxp))
return;
destroy_vcs_context(pxp);
+
+ kcr_pxp_disable(gt);
}
--
2.29.2
_______________________________________________
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^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 05/14] drm/i915/pxp: set KCR reg init during the boot time
2021-02-06 2:09 ` [Intel-gfx] [RFC 05/14] drm/i915/pxp: set KCR reg init during the boot time Daniele Ceraolo Spurio
@ 2021-02-08 17:35 ` Rodrigo Vivi
0 siblings, 0 replies; 41+ messages in thread
From: Rodrigo Vivi @ 2021-02-08 17:35 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: Huang, intel-gfx, Sean Z
On Fri, Feb 05, 2021 at 06:09:16PM -0800, Daniele Ceraolo Spurio wrote:
> Set the KCR init during the boot time, which is required by hardware,
> to allow us doing further protection operation such as sending commands
> to GPU or TEE.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 29 +++++++++++++++++++++++++++-
> 1 file changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 4ddc8a71a3e7..950daee5b907 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -6,6 +6,24 @@
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> +/* KCR register definitions */
> +#define KCR_INIT _MMIO(0x320f0)
> +
> +/* Setting KCR Init bit is required after system boot */
> +#define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
I still don't like the spread register defines... we will soon have some weird duplications...
but seems a new trend...
rant aside:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> +
> +static void kcr_pxp_enable(struct intel_gt *gt)
> +{
> + intel_uncore_write(gt->uncore, KCR_INIT,
> + _MASKED_BIT_ENABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
> +}
> +
> +static void kcr_pxp_disable(struct intel_gt *gt)
> +{
> + intel_uncore_write(gt->uncore, KCR_INIT,
> + _MASKED_BIT_DISABLE(KCR_INIT_ALLOW_DISPLAY_ME_WRITES));
> +}
> +
> static int create_vcs_context(struct intel_pxp *pxp)
> {
> struct intel_gt *gt = pxp_to_gt(pxp);
> @@ -43,19 +61,28 @@ void intel_pxp_init(struct intel_pxp *pxp)
> if (!HAS_PXP(gt->i915))
> return;
>
> + kcr_pxp_enable(gt);
> +
> ret = create_vcs_context(pxp);
> if (ret)
> - return;
> + goto out_kcr;
>
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
>
> return;
> +
> +out_kcr:
> + kcr_pxp_disable(gt);
> }
>
> void intel_pxp_fini(struct intel_pxp *pxp)
> {
> + struct intel_gt *gt = pxp_to_gt(pxp);
> +
> if (!intel_pxp_is_enabled(pxp))
> return;
>
> destroy_vcs_context(pxp);
> +
> + kcr_pxp_disable(gt);
> }
> --
> 2.29.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 06/14] drm/i915/pxp: Implement funcs to create the TEE channel
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (4 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 05/14] drm/i915/pxp: set KCR reg init during the boot time Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 12:52 ` Chris Wilson
2021-02-06 2:09 ` [Intel-gfx] [RFC 07/14] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio
` (13 subsequent siblings)
19 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang
From: "Huang, Sean Z" <sean.z.huang@intel.com>
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(default) session.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 6 ++
drivers/gpu/drm/i915/pxp/intel_pxp.c | 10 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 86 ++++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 ++++
6 files changed, 119 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e2677e8c03e8..f0ba95a2e4fc 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -270,7 +270,8 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
- pxp/intel_pxp.o
+ pxp/intel_pxp.o \
+ pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 41eea02a9285..d1344eb6c849 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -325,6 +325,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->pxp_tee_comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fe1ff025f961..779eb38add40 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1205,6 +1205,12 @@ struct drm_i915_private {
/* Mutex to protect the above hdcp component related values. */
struct mutex hdcp_comp_mutex;
+ struct i915_pxp_comp_master *pxp_tee_master;
+ bool pxp_tee_comp_added;
+
+ /* Mutex to protect the above pxp_tee component related values. */
+ struct mutex pxp_tee_comp_mutex;
+
I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
/*
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 950daee5b907..3f3eeadb7931 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -3,6 +3,7 @@
* Copyright(c) 2020 Intel Corporation.
*/
#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -67,10 +68,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (ret)
goto out_kcr;
+ ret = intel_pxp_tee_component_init(pxp);
+ if (ret)
+ goto out_context;
+
drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
return;
+out_context:
+ destroy_vcs_context(pxp);
out_kcr:
kcr_pxp_disable(gt);
}
@@ -82,7 +89,10 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ intel_pxp_tee_component_fini(pxp);
+
destroy_vcs_context(pxp);
kcr_pxp_disable(gt);
+
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
new file mode 100644
index 000000000000..1d2b8c346161
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include <linux/component.h>
+#include "drm/i915_pxp_tee_interface.h"
+#include "drm/i915_component.h"
+#include "i915_drv.h"
+#include "intel_pxp.h"
+#include "intel_pxp_tee.h"
+
+/**
+ * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee
+ * @i915_kdev: pointer to i915 kernel device
+ * @tee_kdev: pointer to tee kernel device
+ * @data: pointer to pxp_tee_master containing the function pointers
+ *
+ * This bind function is called during the system boot or resume from system sleep.
+ *
+ * Return: return 0 if successful.
+ */
+static int i915_pxp_tee_component_bind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
+ i915->pxp_tee_master->tee_dev = tee_kdev;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ return 0;
+}
+
+static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
+ struct device *tee_kdev, void *data)
+{
+ struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_master = NULL;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+}
+
+static const struct component_ops i915_pxp_tee_component_ops = {
+ .bind = i915_pxp_tee_component_bind,
+ .unbind = i915_pxp_tee_component_unbind,
+};
+
+int intel_pxp_tee_component_init(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
+ I915_COMPONENT_PXP);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret);
+ return ret;
+ }
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ i915->pxp_tee_comp_added = true;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ return 0;
+}
+
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ struct drm_i915_private *i915 = gt->i915;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+ if (!i915->pxp_tee_comp_added) {
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+ return;
+ }
+
+ i915->pxp_tee_comp_added = false;
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
new file mode 100644
index 000000000000..23d050a5d3e7
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_TEE_H__
+#define __INTEL_PXP_TEE_H__
+
+#include "intel_pxp.h"
+
+int intel_pxp_tee_component_init(struct intel_pxp *pxp);
+void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_TEE_H__ */
--
2.29.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 06/14] drm/i915/pxp: Implement funcs to create the TEE channel
2021-02-06 2:09 ` [Intel-gfx] [RFC 06/14] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio
@ 2021-02-06 12:52 ` Chris Wilson
0 siblings, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2021-02-06 12:52 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Huang, Huang, Sean Z
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:17)
> From: "Huang, Sean Z" <sean.z.huang@intel.com>
>
> Implement the funcs to create the TEE channel, so kernel can
> send the TEE commands directly to TEE for creating the arbitrary
> (default) session.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 3 +-
> drivers/gpu/drm/i915/i915_drv.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 6 ++
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 10 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 86 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 14 ++++
> 6 files changed, 119 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e2677e8c03e8..f0ba95a2e4fc 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -270,7 +270,8 @@ i915-y += i915_perf.o
>
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> - pxp/intel_pxp.o
> + pxp/intel_pxp.o \
> + pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 41eea02a9285..d1344eb6c849 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -325,6 +325,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> mutex_init(&dev_priv->wm.wm_mutex);
> mutex_init(&dev_priv->pps_mutex);
> mutex_init(&dev_priv->hdcp_comp_mutex);
> + mutex_init(&dev_priv->pxp_tee_comp_mutex);
>
> i915_memcpy_init_early(dev_priv);
> intel_runtime_pm_init_early(&dev_priv->runtime_pm);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fe1ff025f961..779eb38add40 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1205,6 +1205,12 @@ struct drm_i915_private {
> /* Mutex to protect the above hdcp component related values. */
> struct mutex hdcp_comp_mutex;
>
> + struct i915_pxp_comp_master *pxp_tee_master;
> + bool pxp_tee_comp_added;
> +
> + /* Mutex to protect the above pxp_tee component related values. */
> + struct mutex pxp_tee_comp_mutex;
> +
> I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
>
> /*
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 950daee5b907..3f3eeadb7931 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -3,6 +3,7 @@
> * Copyright(c) 2020 Intel Corporation.
> */
> #include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> #include "gt/intel_context.h"
> #include "i915_drv.h"
>
> @@ -67,10 +68,16 @@ void intel_pxp_init(struct intel_pxp *pxp)
> if (ret)
> goto out_kcr;
>
> + ret = intel_pxp_tee_component_init(pxp);
> + if (ret)
> + goto out_context;
> +
> drm_info(>->i915->drm, "Protected Xe Path (PXP) protected content support initialized\n");
>
> return;
>
> +out_context:
> + destroy_vcs_context(pxp);
> out_kcr:
> kcr_pxp_disable(gt);
> }
> @@ -82,7 +89,10 @@ void intel_pxp_fini(struct intel_pxp *pxp)
> if (!intel_pxp_is_enabled(pxp))
> return;
>
> + intel_pxp_tee_component_fini(pxp);
> +
> destroy_vcs_context(pxp);
>
> kcr_pxp_disable(gt);
> +
> }
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> new file mode 100644
> index 000000000000..1d2b8c346161
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020 Intel Corporation.
> + */
> +
> +#include <linux/component.h>
> +#include "drm/i915_pxp_tee_interface.h"
> +#include "drm/i915_component.h"
> +#include "i915_drv.h"
> +#include "intel_pxp.h"
> +#include "intel_pxp_tee.h"
> +
> +/**
> + * i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee
> + * @i915_kdev: pointer to i915 kernel device
> + * @tee_kdev: pointer to tee kernel device
> + * @data: pointer to pxp_tee_master containing the function pointers
> + *
> + * This bind function is called during the system boot or resume from system sleep.
> + *
> + * Return: return 0 if successful.
> + */
> +static int i915_pxp_tee_component_bind(struct device *i915_kdev,
> + struct device *tee_kdev, void *data)
> +{
> + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
> + i915->pxp_tee_master->tee_dev = tee_kdev;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +
> + return 0;
> +}
> +
> +static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> + struct device *tee_kdev, void *data)
> +{
> + struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_master = NULL;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
> +}
> +
> +static const struct component_ops i915_pxp_tee_component_ops = {
> + .bind = i915_pxp_tee_component_bind,
> + .unbind = i915_pxp_tee_component_unbind,
> +};
> +
> +int intel_pxp_tee_component_init(struct intel_pxp *pxp)
> +{
> + int ret;
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + struct drm_i915_private *i915 = gt->i915;
> +
> + ret = component_add_typed(i915->drm.dev, &i915_pxp_tee_component_ops,
> + I915_COMPONENT_PXP);
> + if (ret < 0) {
> + drm_err(&i915->drm, "Failed to add PXP component (%d)\n", ret);
> + return ret;
> + }
> +
> + mutex_lock(&i915->pxp_tee_comp_mutex);
> + i915->pxp_tee_comp_added = true;
> + mutex_unlock(&i915->pxp_tee_comp_mutex);
i915->pxp_tee_comp_added is used for no other reason than for
uncertainty in the init/fini flow. There is no uncertainty.
There is no reason to pollute drm_i915_private, for if there was a
second pxp device within one i915, it would not work as is.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 07/14] drm/i915/pxp: Create the arbitrary session after boot
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (5 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 06/14] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 12:55 ` Chris Wilson
2021-02-06 2:09 ` [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
` (12 subsequent siblings)
19 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang
From: "Huang, Sean Z" <sean.z.huang@intel.com>
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session will need to be re-created after
teardown or power event because hardware encryption key won't be
valid after such cases.
The session ID is exposed as part of the uapi so it can be used as part
of userspace commands.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 2 +
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 82 +++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 16 +++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 104 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
include/uapi/drm/i915_drm.h | 4 +
8 files changed, 218 insertions(+)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f0ba95a2e4fc..8519abcf6515 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -271,6 +271,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
# Post-mortem debug and GPU hang state capture
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 3f3eeadb7931..916187a0e566 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -62,6 +62,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (!HAS_PXP(gt->i915))
return;
+ mutex_init(&pxp->mutex);
+
kcr_pxp_enable(gt);
ret = create_vcs_context(pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
new file mode 100644
index 000000000000..1ee608341b7a
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "drm/i915_drm.h"
+#include "i915_drv.h"
+
+#include "intel_pxp.h"
+#include "intel_pxp_session.h"
+#include "intel_pxp_tee.h"
+#include "intel_pxp_types.h"
+
+#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
+
+#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+
+static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ intel_wakeref_t wakeref;
+ u32 sip = 0;
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
+ sip = intel_uncore_read(gt->uncore, GEN12_KCR_SIP);
+
+ return sip & BIT(id);
+}
+
+bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp)
+{
+ return intel_pxp_session_is_in_play(pxp, ARB_SESSION);
+}
+
+static int pxp_wait_for_session_state(struct intel_pxp *pxp, u32 id, bool in_play)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ intel_wakeref_t wakeref;
+ u32 mask = BIT(id);
+ int ret;
+
+ with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
+ ret = intel_wait_for_register(gt->uncore,
+ GEN12_KCR_SIP,
+ mask,
+ in_play ? mask : 0,
+ 100);
+
+ return ret;
+}
+
+int intel_pxp_create_arb_session(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ int ret;
+
+ lockdep_assert_held(&pxp->mutex);
+
+ pxp->arb_is_in_play = false;
+
+ if (intel_pxp_session_is_in_play(pxp, ARB_SESSION)) {
+ drm_err(>->i915->drm, "arb session already in play at creation time\n");
+ pxp->arb_is_in_play = true;
+ return -EEXIST;
+ }
+
+ ret = intel_pxp_tee_cmd_create_arb_session(pxp, ARB_SESSION);
+ if (ret) {
+ drm_err(>->i915->drm, "tee cmd for arb session creation failed\n");
+ return ret;
+ }
+
+ ret = pxp_wait_for_session_state(pxp, ARB_SESSION, true);
+ if (ret) {
+ drm_err(>->i915->drm, "arb session failed to go in play\n");
+ return ret;
+ }
+
+ pxp->arb_is_in_play = true;
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
new file mode 100644
index 000000000000..6fc4a2370c44
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_SESSION_H__
+#define __INTEL_PXP_SESSION_H__
+
+#include <linux/types.h>
+
+struct intel_pxp;
+
+bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
+int intel_pxp_create_arb_session(struct intel_pxp *pxp);
+
+#endif /* __INTEL_PXP_SESSION_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 1d2b8c346161..700709f323f7 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -8,8 +8,68 @@
#include "drm/i915_component.h"
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
+#define PXP_TEE_APIVER 0x40002
+#define PXP_TEE_ARB_CMDID 0x1e
+#define PXP_TEE_ARB_PROTECTION_MODE 0x2
+
+/* PXP TEE message header */
+struct pxp_tee_cmd_header {
+ u32 api_version;
+ u32 command_id;
+ u32 status;
+ /* Length of the message (excluding the header) */
+ u32 buffer_len;
+} __packed;
+
+/* PXP TEE message input to create a arbitrary session */
+struct pxp_tee_create_arb_in {
+ struct pxp_tee_cmd_header header;
+ u32 protection_mode;
+ u32 session_id;
+} __packed;
+
+/* PXP TEE message output to create a arbitrary session */
+struct pxp_tee_create_arb_out {
+ struct pxp_tee_cmd_header header;
+} __packed;
+
+static int intel_pxp_tee_io_message(struct intel_pxp *pxp,
+ void *msg_in, u32 msg_in_size,
+ void *msg_out, u32 msg_out_max_size,
+ u32 *msg_out_rcv_size)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct i915_pxp_comp_master *pxp_tee_master = i915->pxp_tee_master;
+ int ret;
+
+ lockdep_assert_held(&i915->pxp_tee_comp_mutex);
+
+ ret = pxp_tee_master->ops->send(pxp_tee_master->tee_dev, msg_in, msg_in_size);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to send TEE message\n");
+ return ret;
+ }
+
+ ret = pxp_tee_master->ops->recv(pxp_tee_master->tee_dev, msg_out, msg_out_max_size);
+ if (ret < 0) {
+ drm_err(&i915->drm, "Failed to receive TEE message\n");
+ return ret;
+ }
+
+ if (ret > msg_out_max_size) {
+ drm_err(&i915->drm, "Failed to receive TEE message due to unexpected output size\n");
+ return -ENOSPC;
+ }
+
+ if (msg_out_rcv_size)
+ *msg_out_rcv_size = ret;
+
+ return 0;
+}
+
/**
* i915_pxp_tee_component_bind - bind funciton to pass the function pointers to pxp_tee
* @i915_kdev: pointer to i915 kernel device
@@ -23,13 +83,28 @@
static int i915_pxp_tee_component_bind(struct device *i915_kdev,
struct device *tee_kdev, void *data)
{
+ int ret = 0;
struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
+ struct intel_pxp *pxp = &i915->gt.pxp;
mutex_lock(&i915->pxp_tee_comp_mutex);
i915->pxp_tee_master = (struct i915_pxp_comp_master *)data;
i915->pxp_tee_master->tee_dev = tee_kdev;
mutex_unlock(&i915->pxp_tee_comp_mutex);
+ mutex_lock(&pxp->mutex);
+
+ /* Create arb session only if tee is ready, during system boot or sleep/resume */
+ if (!intel_pxp_arb_session_is_in_play(pxp))
+ ret = intel_pxp_create_arb_session(pxp);
+
+ mutex_unlock(&pxp->mutex);
+
+ if (ret) {
+ drm_err(&i915->drm, "Failed to create arb session ret=[%d]\n", ret);
+ return ret;
+ }
+
return 0;
}
@@ -84,3 +159,32 @@ void intel_pxp_tee_component_fini(struct intel_pxp *pxp)
component_del(i915->drm.dev, &i915_pxp_tee_component_ops);
}
+
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id)
+{
+ struct drm_i915_private *i915 = pxp_to_gt(pxp)->i915;
+ struct pxp_tee_create_arb_in msg_in = {0};
+ struct pxp_tee_create_arb_out msg_out = {0};
+ int ret;
+
+ msg_in.header.api_version = PXP_TEE_APIVER;
+ msg_in.header.command_id = PXP_TEE_ARB_CMDID;
+ msg_in.header.buffer_len = sizeof(msg_in) - sizeof(msg_in.header);
+ msg_in.protection_mode = PXP_TEE_ARB_PROTECTION_MODE;
+ msg_in.session_id = arb_session_id;
+
+ mutex_lock(&i915->pxp_tee_comp_mutex);
+
+ ret = intel_pxp_tee_io_message(pxp,
+ &msg_in, sizeof(msg_in),
+ &msg_out, sizeof(msg_out),
+ NULL);
+
+ mutex_unlock(&i915->pxp_tee_comp_mutex);
+
+ if (ret)
+ drm_err(&i915->drm, "Failed to send tee msg ret=[%d]\n", ret);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
index 23d050a5d3e7..c136053ce340 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
@@ -11,4 +11,7 @@
int intel_pxp_tee_component_init(struct intel_pxp *pxp);
void intel_pxp_tee_component_fini(struct intel_pxp *pxp);
+int intel_pxp_tee_cmd_create_arb_session(struct intel_pxp *pxp,
+ int arb_session_id);
+
#endif /* __INTEL_PXP_TEE_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index bd12c520e60a..30a6013b5d95 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -6,10 +6,16 @@
#ifndef __INTEL_PXP_TYPES_H__
#define __INTEL_PXP_TYPES_H__
+#include <linux/types.h>
+#include <linux/mutex.h>
+
struct intel_context;
struct intel_pxp {
struct intel_context *ce;
+
+ struct mutex mutex;
+ bool arb_is_in_play;
};
#endif /* __INTEL_PXP_TYPES_H__ */
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 1987e2ea79a3..56c6bfe6c2d0 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -2376,6 +2376,10 @@ struct drm_i915_query_perf_config {
__u8 data[];
};
+
+/* ID of the protected content session managed by i915 when PXP is active */
+#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
+
#if defined(__cplusplus)
}
#endif
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 07/14] drm/i915/pxp: Create the arbitrary session after boot
2021-02-06 2:09 ` [Intel-gfx] [RFC 07/14] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio
@ 2021-02-06 12:55 ` Chris Wilson
0 siblings, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2021-02-06 12:55 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Huang, Huang, Sean Z
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:18)
> From: "Huang, Sean Z" <sean.z.huang@intel.com>
>
> Create the arbitrary session, with the fixed session id 0xf, after
> system boot, for the case that application allocates the protected
> buffer without establishing any protection session. Because the
> hardware requires at least one alive session for protected buffer
> creation. This arbitrary session will need to be re-created after
> teardown or power event because hardware encryption key won't be
> valid after such cases.
>
> The session ID is exposed as part of the uapi so it can be used as part
> of userspace commands.
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 2 +
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 82 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 16 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 104 +++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 3 +
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 6 ++
> include/uapi/drm/i915_drm.h | 4 +
> 8 files changed, 218 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index f0ba95a2e4fc..8519abcf6515 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -271,6 +271,7 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> + pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> # Post-mortem debug and GPU hang state capture
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> index 3f3eeadb7931..916187a0e566 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
> @@ -62,6 +62,8 @@ void intel_pxp_init(struct intel_pxp *pxp)
> if (!HAS_PXP(gt->i915))
> return;
>
> + mutex_init(&pxp->mutex);
> +
> kcr_pxp_enable(gt);
>
> ret = create_vcs_context(pxp);
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> new file mode 100644
> index 000000000000..1ee608341b7a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "drm/i915_drm.h"
> +#include "i915_drv.h"
> +
> +#include "intel_pxp.h"
> +#include "intel_pxp_session.h"
> +#include "intel_pxp_tee.h"
> +#include "intel_pxp_types.h"
> +
> +#define ARB_SESSION I915_PROTECTED_CONTENT_DEFAULT_SESSION /* shorter define */
> +
> +#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
> +
> +static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
> +{
> + struct intel_gt *gt = pxp_to_gt(pxp);
> + intel_wakeref_t wakeref;
> + u32 sip = 0;
> +
> + with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
gt->uncore->rpm
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (6 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 07/14] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 4:08 ` kernel test robot
2021-02-06 12:59 ` Chris Wilson
2021-02-06 2:09 ` [Intel-gfx] [RFC 09/14] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio
` (11 subsequent siblings)
19 siblings, 2 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang
From: "Huang, Sean Z" <sean.z.huang@intel.com>
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. Additionally, we want to emit a
teardown operation to make sure we're clean on boot and resume
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 227 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 40 ++++
drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +-
6 files changed, 288 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8519abcf6515..9698fec810ae 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -271,6 +271,7 @@ i915-y += i915_perf.o
# Protected execution platform (PXP) support
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
+ pxp/intel_pxp_cmd.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
new file mode 100644
index 000000000000..3e2c3580cb1b
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#include "intel_pxp.h"
+#include "intel_pxp_session.h"
+#include "gt/intel_context.h"
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt_buffer_pool.h"
+
+/* PXP GPU command definitions */
+
+/* MI_SET_APPID */
+#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
+
+/* MI_FLUSH_DW */
+#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
+
+/* MI_WAIT */
+#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
+#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
+
+/* CRYPTO_KEY_EXCHANGE */
+#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
+
+static struct i915_vma *intel_pxp_get_batch(struct intel_context *ce,
+ struct i915_gem_ww_ctx *ww,
+ u32 size)
+{
+ struct intel_gt_buffer_pool_node *pool;
+ struct i915_vma *batch;
+ int err;
+
+ intel_engine_pm_get(ce->engine);
+
+retry:
+ err = intel_context_pin_ww(ce, ww);
+ if (err)
+ goto out;
+
+ pool = intel_gt_get_buffer_pool(ce->engine->gt, size, I915_MAP_WC);
+ if (IS_ERR(pool)) {
+ err = PTR_ERR(pool);
+ goto out_ctx;
+ }
+
+ batch = i915_vma_instance(pool->obj, ce->vm, NULL);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_put;
+ }
+
+ err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER);
+ if (unlikely(err))
+ goto out_put;
+
+ err = i915_gem_object_lock(pool->obj, ww);
+ if (err)
+ goto out_unpin;
+
+ batch->private = pool;
+
+ return batch;
+
+out_unpin:
+ i915_vma_unpin(batch);
+out_put:
+ intel_gt_buffer_pool_put(pool);
+out_ctx:
+ intel_context_unpin(ce);
+out:
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(ww);
+ if (!err)
+ goto retry;
+ }
+ intel_engine_pm_put(ce->engine);
+ return ERR_PTR(err);
+}
+
+static void intel_pxp_put_batch(struct intel_context *ce,
+ struct i915_vma *batch)
+{
+ i915_vma_unpin(batch);
+ intel_gt_buffer_pool_put(batch->private);
+ intel_context_unpin(ce);
+ intel_engine_pm_put(ce->engine);
+}
+
+static int intel_pxp_submit_batch(struct intel_context *ce,
+ struct i915_vma *batch)
+{
+ struct i915_request *rq;
+ int err;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ err = i915_request_await_object(rq, batch->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(batch, rq, 0);
+ if (err)
+ goto out_rq;
+
+ err = intel_gt_buffer_pool_mark_active(batch->private, rq);
+ if (err)
+ goto out_rq;
+
+ if (ce->engine->emit_init_breadcrumb) {
+ err = ce->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_rq;
+ }
+
+ err = ce->engine->emit_bb_start(rq, batch->node.start,
+ batch->node.size, 0);
+ if (err)
+ goto out_rq;
+
+out_rq:
+ i915_request_get(rq);
+
+ if (unlikely(err))
+ i915_request_set_error_once(rq, err);
+
+ i915_request_add(rq);
+
+ if (!err && i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+
+ i915_request_put(rq);
+
+ return err;
+}
+
+/* stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
+#define MFX_WAIT_PXP \
+ MFX_WAIT | \
+ MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG;
+
+static u32 *pxp_emit_session_selection(u32 *cmd, u32 idx)
+{
+ *cmd++ = MFX_WAIT_PXP;
+
+ /* pxp off */
+ *cmd++ = MI_FLUSH_DW;
+ *cmd++ = 0;
+ *cmd++ = 0;
+
+ /* select session */
+ *cmd++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx);
+
+ *cmd++ = MFX_WAIT_PXP;
+
+ /* pxp on */
+ *cmd++ = MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE;
+ *cmd++ = 0;
+ *cmd++ = 0;
+
+ *cmd++ = MFX_WAIT_PXP;
+
+ return cmd;
+}
+
+static u32 *pxp_emit_inline_termination(u32 *cmd)
+{
+ /* session inline termination */
+ *cmd++ = CRYPTO_KEY_EXCHANGE;
+ *cmd++ = 0;
+
+ return cmd;
+}
+
+static u32 *pxp_emit_batch_end(u32 *cmd)
+{
+ /* wait for cmds to go through */
+ *cmd++ = MFX_WAIT_PXP;
+
+ *cmd++ = MI_BATCH_BUFFER_END;
+
+ return cmd;
+}
+
+int intel_pxp_submit_session_termination(struct intel_pxp *pxp, u32 id)
+{
+ struct i915_vma *batch;
+ struct i915_gem_ww_ctx ww;
+ u32 *cmd;
+ int err;
+
+ if (!intel_pxp_is_enabled(pxp))
+ return 0;
+
+ i915_gem_ww_ctx_init(&ww, false);
+
+ batch = intel_pxp_get_batch(pxp->ce, &ww, PAGE_SIZE);
+ if (IS_ERR(batch)) {
+ err = PTR_ERR(batch);
+ goto out_ww;
+ }
+
+ cmd = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cmd)) {
+ err = PTR_ERR(cmd);
+ goto out_batch;
+ }
+
+ cmd = pxp_emit_session_selection(cmd, id);
+ cmd = pxp_emit_inline_termination(cmd);
+ cmd = pxp_emit_batch_end(cmd);
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ err = intel_pxp_submit_batch(pxp->ce, batch);
+
+out_batch:
+ intel_pxp_put_batch(pxp->ce, batch);
+out_ww:
+ i915_gem_ww_ctx_fini(&ww);
+ return err;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
new file mode 100644
index 000000000000..7c33b66f0812
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_CMD_H__
+#define __INTEL_PXP_CMD_H__
+
+#include <linux/types.h>
+
+struct intel_pxp;
+
+int intel_pxp_submit_session_termination(struct intel_pxp *pxp, u32 idx);
+
+#endif /* __INTEL_PXP_CMD_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index 1ee608341b7a..fe733cc69f27 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "intel_pxp.h"
+#include "intel_pxp_cmd.h"
#include "intel_pxp_session.h"
#include "intel_pxp_tee.h"
#include "intel_pxp_types.h"
@@ -15,6 +16,9 @@
#define GEN12_KCR_SIP _MMIO(0x32260) /* KCR hwdrm session in play 0-31 */
+/* PXP global terminate register for session termination */
+#define PXP_GLOBAL_TERMINATE _MMIO(0x320f8)
+
static bool intel_pxp_session_is_in_play(struct intel_pxp *pxp, u32 id)
{
struct intel_gt *gt = pxp_to_gt(pxp);
@@ -80,3 +84,39 @@ int intel_pxp_create_arb_session(struct intel_pxp *pxp)
return 0;
}
+
+/**
+ * intel_pxp_arb_terminate_session_with_global_terminate - Terminate the arb hw session.
+ * @pxp: pointer to pxp struct.
+ *
+ * This function is NOT intended to be called from the ioctl, and need to be protected by
+ * mutex to ensure no SIP change during the call.
+ *
+ * Return: status. 0 means terminate is successful.
+ */
+int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp)
+{
+ int ret;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ lockdep_assert_held(&pxp->mutex);
+
+ /* terminate the hw sessions */
+ ret = intel_pxp_submit_session_termination(pxp, ARB_SESSION);
+ if (ret) {
+ drm_err(>->i915->drm, "Failed to submit session termination\n");
+ return ret;
+ }
+
+ pxp->arb_is_in_play = false;
+
+ ret = pxp_wait_for_session_state(pxp, ARB_SESSION, false);
+ if (ret) {
+ drm_err(>->i915->drm, "Session state did not clear\n");
+ return ret;
+ }
+
+ intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
index 6fc4a2370c44..07c97df7a509 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.h
@@ -12,5 +12,6 @@ struct intel_pxp;
bool intel_pxp_arb_session_is_in_play(struct intel_pxp *pxp);
int intel_pxp_create_arb_session(struct intel_pxp *pxp);
+int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp);
#endif /* __INTEL_PXP_SESSION_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 700709f323f7..dd7161f176f1 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -95,7 +95,10 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
mutex_lock(&pxp->mutex);
/* Create arb session only if tee is ready, during system boot or sleep/resume */
- if (!intel_pxp_arb_session_is_in_play(pxp))
+ if (intel_pxp_arb_session_is_in_play(pxp))
+ ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp);
+
+ if (!ret)
ret = intel_pxp_create_arb_session(pxp);
mutex_unlock(&pxp->mutex);
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown
2021-02-06 2:09 ` [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
@ 2021-02-06 4:08 ` kernel test robot
2021-02-06 12:59 ` Chris Wilson
1 sibling, 0 replies; 41+ messages in thread
From: kernel test robot @ 2021-02-06 4:08 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2962 bytes --]
Hi Daniele,
[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next char-misc/char-misc-testing v5.11-rc6 next-20210125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/Introduce-Intel-PXP/20210206-101234
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-allyesconfig (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/775bac398c87dd79c7ba1a9083b98e8b17a678db
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Daniele-Ceraolo-Spurio/Introduce-Intel-PXP/20210206-101234
git checkout 775bac398c87dd79c7ba1a9083b98e8b17a678db
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c:188:5: error: no previous prototype for 'intel_pxp_submit_session_termination' [-Werror=missing-prototypes]
188 | int intel_pxp_submit_session_termination(struct intel_pxp *pxp, u32 id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/intel_pxp_submit_session_termination +188 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
187
> 188 int intel_pxp_submit_session_termination(struct intel_pxp *pxp, u32 id)
189 {
190 struct i915_vma *batch;
191 struct i915_gem_ww_ctx ww;
192 u32 *cmd;
193 int err;
194
195 if (!intel_pxp_is_enabled(pxp))
196 return 0;
197
198 i915_gem_ww_ctx_init(&ww, false);
199
200 batch = intel_pxp_get_batch(pxp->ce, &ww, PAGE_SIZE);
201 if (IS_ERR(batch)) {
202 err = PTR_ERR(batch);
203 goto out_ww;
204 }
205
206 cmd = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
207 if (IS_ERR(cmd)) {
208 err = PTR_ERR(cmd);
209 goto out_batch;
210 }
211
212 cmd = pxp_emit_session_selection(cmd, id);
213 cmd = pxp_emit_inline_termination(cmd);
214 cmd = pxp_emit_batch_end(cmd);
215
216 i915_gem_object_flush_map(batch->obj);
217 i915_gem_object_unpin_map(batch->obj);
218
219 err = intel_pxp_submit_batch(pxp->ce, batch);
220
221 out_batch:
222 intel_pxp_put_batch(pxp->ce, batch);
223 out_ww:
224 i915_gem_ww_ctx_fini(&ww);
225 return err;
226 }
227
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 64242 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown
2021-02-06 2:09 ` [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
2021-02-06 4:08 ` kernel test robot
@ 2021-02-06 12:59 ` Chris Wilson
2021-02-08 19:43 ` Daniele Ceraolo Spurio
1 sibling, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2021-02-06 12:59 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Huang, Huang, Sean Z
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:19)
> From: "Huang, Sean Z" <sean.z.huang@intel.com>
>
> Teardown is triggered when the display topology changes and no
> long meets the secure playback requirement, and hardware trashes
> all the encryption keys for display. Additionally, we want to emit a
> teardown operation to make sure we're clean on boot and resume
>
> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 227 +++++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 40 ++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +-
> 6 files changed, 288 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 8519abcf6515..9698fec810ae 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -271,6 +271,7 @@ i915-y += i915_perf.o
> # Protected execution platform (PXP) support
> i915-$(CONFIG_DRM_I915_PXP) += \
> pxp/intel_pxp.o \
> + pxp/intel_pxp_cmd.o \
> pxp/intel_pxp_session.o \
> pxp/intel_pxp_tee.o
>
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> new file mode 100644
> index 000000000000..3e2c3580cb1b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> @@ -0,0 +1,227 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
> + */
> +
> +#include "intel_pxp.h"
> +#include "intel_pxp_session.h"
> +#include "gt/intel_context.h"
> +#include "gt/intel_engine_pm.h"
> +#include "gt/intel_gpu_commands.h"
> +#include "gt/intel_gt_buffer_pool.h"
> +
> +/* PXP GPU command definitions */
> +
> +/* MI_SET_APPID */
> +#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
> +
> +/* MI_FLUSH_DW */
> +#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
> +
> +/* MI_WAIT */
> +#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
> +#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
> +
> +/* CRYPTO_KEY_EXCHANGE */
> +#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
> +
> +static struct i915_vma *intel_pxp_get_batch(struct intel_context *ce,
> + struct i915_gem_ww_ctx *ww,
> + u32 size)
> +{
> + struct intel_gt_buffer_pool_node *pool;
> + struct i915_vma *batch;
> + int err;
> +
> + intel_engine_pm_get(ce->engine);
> +
> +retry:
> + err = intel_context_pin_ww(ce, ww);
> + if (err)
> + goto out;
> +
> + pool = intel_gt_get_buffer_pool(ce->engine->gt, size, I915_MAP_WC);
> + if (IS_ERR(pool)) {
> + err = PTR_ERR(pool);
> + goto out_ctx;
> + }
> +
> + batch = i915_vma_instance(pool->obj, ce->vm, NULL);
> + if (IS_ERR(batch)) {
> + err = PTR_ERR(batch);
> + goto out_put;
> + }
> +
> + err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER);
> + if (unlikely(err))
> + goto out_put;
> +
> + err = i915_gem_object_lock(pool->obj, ww);
> + if (err)
> + goto out_unpin;
> +
> + batch->private = pool;
> +
> + return batch;
> +
> +out_unpin:
> + i915_vma_unpin(batch);
> +out_put:
> + intel_gt_buffer_pool_put(pool);
> +out_ctx:
> + intel_context_unpin(ce);
> +out:
> + if (err == -EDEADLK) {
> + err = i915_gem_ww_ctx_backoff(ww);
> + if (!err)
> + goto retry;
> + }
> + intel_engine_pm_put(ce->engine);
> + return ERR_PTR(err);
> +}
> +
> +static void intel_pxp_put_batch(struct intel_context *ce,
> + struct i915_vma *batch)
> +{
> + i915_vma_unpin(batch);
> + intel_gt_buffer_pool_put(batch->private);
> + intel_context_unpin(ce);
> + intel_engine_pm_put(ce->engine);
> +}
> +
> +static int intel_pxp_submit_batch(struct intel_context *ce,
> + struct i915_vma *batch)
> +{
> + struct i915_request *rq;
> + int err;
> +
> + rq = i915_request_create(ce);
> + if (IS_ERR(rq))
> + return PTR_ERR(rq);
> +
> + err = i915_request_await_object(rq, batch->obj, false);
> + if (!err)
> + err = i915_vma_move_to_active(batch, rq, 0);
> + if (err)
> + goto out_rq;
> +
> + err = intel_gt_buffer_pool_mark_active(batch->private, rq);
> + if (err)
> + goto out_rq;
> +
> + if (ce->engine->emit_init_breadcrumb) {
> + err = ce->engine->emit_init_breadcrumb(rq);
> + if (err)
> + goto out_rq;
> + }
> +
> + err = ce->engine->emit_bb_start(rq, batch->node.start,
> + batch->node.size, 0);
> + if (err)
> + goto out_rq;
> +
> +out_rq:
> + i915_request_get(rq);
> +
> + if (unlikely(err))
> + i915_request_set_error_once(rq, err);
> +
> + i915_request_add(rq);
> +
> + if (!err && i915_request_wait(rq, 0, HZ / 5) < 0)
> + err = -ETIME;
> +
> + i915_request_put(rq);
> +
> + return err;
> +}
> +
> +/* stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
> +#define MFX_WAIT_PXP \
> + MFX_WAIT | \
> + MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
> + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG;
> +
> +static u32 *pxp_emit_session_selection(u32 *cmd, u32 idx)
> +{
> + *cmd++ = MFX_WAIT_PXP;
> +
> + /* pxp off */
> + *cmd++ = MI_FLUSH_DW;
> + *cmd++ = 0;
> + *cmd++ = 0;
> +
> + /* select session */
> + *cmd++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx);
> +
> + *cmd++ = MFX_WAIT_PXP;
> +
> + /* pxp on */
> + *cmd++ = MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE;
> + *cmd++ = 0;
> + *cmd++ = 0;
> +
> + *cmd++ = MFX_WAIT_PXP;
> +
> + return cmd;
> +}
> +
> +static u32 *pxp_emit_inline_termination(u32 *cmd)
> +{
> + /* session inline termination */
> + *cmd++ = CRYPTO_KEY_EXCHANGE;
> + *cmd++ = 0;
> +
> + return cmd;
> +}
> +
> +static u32 *pxp_emit_batch_end(u32 *cmd)
> +{
> + /* wait for cmds to go through */
> + *cmd++ = MFX_WAIT_PXP;
> +
> + *cmd++ = MI_BATCH_BUFFER_END;
> +
> + return cmd;
> +}
> +
> +int intel_pxp_submit_session_termination(struct intel_pxp *pxp, u32 id)
> +{
> + struct i915_vma *batch;
> + struct i915_gem_ww_ctx ww;
> + u32 *cmd;
> + int err;
> +
> + if (!intel_pxp_is_enabled(pxp))
> + return 0;
> +
> + i915_gem_ww_ctx_init(&ww, false);
> +
> + batch = intel_pxp_get_batch(pxp->ce, &ww, PAGE_SIZE);
Is there any reason at all to use the batch and not just emit directly
into the ring? The command sequence is short. And you probably want to
disable arbitration.
Does this invalidation need priority for immediate execution?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown
2021-02-06 12:59 ` Chris Wilson
@ 2021-02-08 19:43 ` Daniele Ceraolo Spurio
2021-02-08 20:41 ` Chris Wilson
0 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-08 19:43 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Huang, Sean Z
On 2/6/2021 4:59 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:19)
>> From: "Huang, Sean Z" <sean.z.huang@intel.com>
>>
>> Teardown is triggered when the display topology changes and no
>> long meets the secure playback requirement, and hardware trashes
>> all the encryption keys for display. Additionally, we want to emit a
>> teardown operation to make sure we're clean on boot and resume
>>
>> Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> ---
>> drivers/gpu/drm/i915/Makefile | 1 +
>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 227 +++++++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 40 ++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 1 +
>> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 5 +-
>> 6 files changed, 288 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>>
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index 8519abcf6515..9698fec810ae 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -271,6 +271,7 @@ i915-y += i915_perf.o
>> # Protected execution platform (PXP) support
>> i915-$(CONFIG_DRM_I915_PXP) += \
>> pxp/intel_pxp.o \
>> + pxp/intel_pxp_cmd.o \
>> pxp/intel_pxp_session.o \
>> pxp/intel_pxp_tee.o
>>
>> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
>> new file mode 100644
>> index 000000000000..3e2c3580cb1b
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
>> @@ -0,0 +1,227 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright(c) 2020, Intel Corporation. All rights reserved.
>> + */
>> +
>> +#include "intel_pxp.h"
>> +#include "intel_pxp_session.h"
>> +#include "gt/intel_context.h"
>> +#include "gt/intel_engine_pm.h"
>> +#include "gt/intel_gpu_commands.h"
>> +#include "gt/intel_gt_buffer_pool.h"
>> +
>> +/* PXP GPU command definitions */
>> +
>> +/* MI_SET_APPID */
>> +#define MI_SET_APPID_SESSION_ID(x) ((x) << 0)
>> +
>> +/* MI_FLUSH_DW */
>> +#define MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE BIT(22)
>> +
>> +/* MI_WAIT */
>> +#define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG BIT(9)
>> +#define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG BIT(8)
>> +
>> +/* CRYPTO_KEY_EXCHANGE */
>> +#define CRYPTO_KEY_EXCHANGE ((0x3 << 29) | (0x01609 << 16))
>> +
>> +static struct i915_vma *intel_pxp_get_batch(struct intel_context *ce,
>> + struct i915_gem_ww_ctx *ww,
>> + u32 size)
>> +{
>> + struct intel_gt_buffer_pool_node *pool;
>> + struct i915_vma *batch;
>> + int err;
>> +
>> + intel_engine_pm_get(ce->engine);
>> +
>> +retry:
>> + err = intel_context_pin_ww(ce, ww);
>> + if (err)
>> + goto out;
>> +
>> + pool = intel_gt_get_buffer_pool(ce->engine->gt, size, I915_MAP_WC);
>> + if (IS_ERR(pool)) {
>> + err = PTR_ERR(pool);
>> + goto out_ctx;
>> + }
>> +
>> + batch = i915_vma_instance(pool->obj, ce->vm, NULL);
>> + if (IS_ERR(batch)) {
>> + err = PTR_ERR(batch);
>> + goto out_put;
>> + }
>> +
>> + err = i915_vma_pin_ww(batch, ww, 0, 0, PIN_USER);
>> + if (unlikely(err))
>> + goto out_put;
>> +
>> + err = i915_gem_object_lock(pool->obj, ww);
>> + if (err)
>> + goto out_unpin;
>> +
>> + batch->private = pool;
>> +
>> + return batch;
>> +
>> +out_unpin:
>> + i915_vma_unpin(batch);
>> +out_put:
>> + intel_gt_buffer_pool_put(pool);
>> +out_ctx:
>> + intel_context_unpin(ce);
>> +out:
>> + if (err == -EDEADLK) {
>> + err = i915_gem_ww_ctx_backoff(ww);
>> + if (!err)
>> + goto retry;
>> + }
>> + intel_engine_pm_put(ce->engine);
>> + return ERR_PTR(err);
>> +}
>> +
>> +static void intel_pxp_put_batch(struct intel_context *ce,
>> + struct i915_vma *batch)
>> +{
>> + i915_vma_unpin(batch);
>> + intel_gt_buffer_pool_put(batch->private);
>> + intel_context_unpin(ce);
>> + intel_engine_pm_put(ce->engine);
>> +}
>> +
>> +static int intel_pxp_submit_batch(struct intel_context *ce,
>> + struct i915_vma *batch)
>> +{
>> + struct i915_request *rq;
>> + int err;
>> +
>> + rq = i915_request_create(ce);
>> + if (IS_ERR(rq))
>> + return PTR_ERR(rq);
>> +
>> + err = i915_request_await_object(rq, batch->obj, false);
>> + if (!err)
>> + err = i915_vma_move_to_active(batch, rq, 0);
>> + if (err)
>> + goto out_rq;
>> +
>> + err = intel_gt_buffer_pool_mark_active(batch->private, rq);
>> + if (err)
>> + goto out_rq;
>> +
>> + if (ce->engine->emit_init_breadcrumb) {
>> + err = ce->engine->emit_init_breadcrumb(rq);
>> + if (err)
>> + goto out_rq;
>> + }
>> +
>> + err = ce->engine->emit_bb_start(rq, batch->node.start,
>> + batch->node.size, 0);
>> + if (err)
>> + goto out_rq;
>> +
>> +out_rq:
>> + i915_request_get(rq);
>> +
>> + if (unlikely(err))
>> + i915_request_set_error_once(rq, err);
>> +
>> + i915_request_add(rq);
>> +
>> + if (!err && i915_request_wait(rq, 0, HZ / 5) < 0)
>> + err = -ETIME;
>> +
>> + i915_request_put(rq);
>> +
>> + return err;
>> +}
>> +
>> +/* stall until prior PXP and MFX/HCP/HUC objects are cmopleted */
>> +#define MFX_WAIT_PXP \
>> + MFX_WAIT | \
>> + MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
>> + MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG;
>> +
>> +static u32 *pxp_emit_session_selection(u32 *cmd, u32 idx)
>> +{
>> + *cmd++ = MFX_WAIT_PXP;
>> +
>> + /* pxp off */
>> + *cmd++ = MI_FLUSH_DW;
>> + *cmd++ = 0;
>> + *cmd++ = 0;
>> +
>> + /* select session */
>> + *cmd++ = MI_SET_APPID | MI_SET_APPID_SESSION_ID(idx);
>> +
>> + *cmd++ = MFX_WAIT_PXP;
>> +
>> + /* pxp on */
>> + *cmd++ = MI_FLUSH_DW | MI_FLUSH_DW_DW0_PROTECTED_MEMORY_ENABLE;
>> + *cmd++ = 0;
>> + *cmd++ = 0;
>> +
>> + *cmd++ = MFX_WAIT_PXP;
>> +
>> + return cmd;
>> +}
>> +
>> +static u32 *pxp_emit_inline_termination(u32 *cmd)
>> +{
>> + /* session inline termination */
>> + *cmd++ = CRYPTO_KEY_EXCHANGE;
>> + *cmd++ = 0;
>> +
>> + return cmd;
>> +}
>> +
>> +static u32 *pxp_emit_batch_end(u32 *cmd)
>> +{
>> + /* wait for cmds to go through */
>> + *cmd++ = MFX_WAIT_PXP;
>> +
>> + *cmd++ = MI_BATCH_BUFFER_END;
>> +
>> + return cmd;
>> +}
>> +
>> +int intel_pxp_submit_session_termination(struct intel_pxp *pxp, u32 id)
>> +{
>> + struct i915_vma *batch;
>> + struct i915_gem_ww_ctx ww;
>> + u32 *cmd;
>> + int err;
>> +
>> + if (!intel_pxp_is_enabled(pxp))
>> + return 0;
>> +
>> + i915_gem_ww_ctx_init(&ww, false);
>> +
>> + batch = intel_pxp_get_batch(pxp->ce, &ww, PAGE_SIZE);
> Is there any reason at all to use the batch and not just emit directly
> into the ring? The command sequence is short. And you probably want to
> disable arbitration.
Future proofing - with multiple sessions in place we'd need to emit a
termination for each of them (pxp_emit_session_selection +
pxp_emit_inline_termination), so the sequence would be longer. It'd
still be below a page, so it should still be possible to fit it in the
ring if you believe that works better.
>
> Does this invalidation need priority for immediate execution?
Not spec-wise, but probably better to still do it to get the session
back-up ASAP.
Daniele
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown
2021-02-08 19:43 ` Daniele Ceraolo Spurio
@ 2021-02-08 20:41 ` Chris Wilson
0 siblings, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2021-02-08 20:41 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Huang, Sean Z
Quoting Daniele Ceraolo Spurio (2021-02-08 19:43:23)
>
>
> On 2/6/2021 4:59 AM, Chris Wilson wrote:
> > Is there any reason at all to use the batch and not just emit directly
> > into the ring? The command sequence is short. And you probably want to
> > disable arbitration.
>
> Future proofing - with multiple sessions in place we'd need to emit a
> termination for each of them (pxp_emit_session_selection +
> pxp_emit_inline_termination), so the sequence would be longer. It'd
> still be below a page, so it should still be possible to fit it in the
> ring if you believe that works better.
In terms of complexity and assurance (pre-allocated space), emitting from
the ring buffer is far simpler. You can make the ring upto 512KiB, but
if a single page is all that is needed for the most complicated
invalidate command, 8/16KiB should be plenty. (Number of pages then
equals number of invalidates that can in flight at any time, which
realistically is going to be a small number.)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 09/14] drm/i915/pxp: Implement PXP irq handler
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (7 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 08/14] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 2:09 ` [Intel-gfx] [RFC 10/14] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio
` (10 subsequent siblings)
19 siblings, 0 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang
From: "Huang, Sean Z" <sean.z.huang@intel.com>
The HW will generate a teardown interrupt when session termination is
required, which requires i915 to submit a terminating batch. Once the HW
is done with the termination it will generate another interrupt, at
which point it is safe to re-create the session.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c | 7 +
drivers/gpu/drm/i915/pxp/intel_pxp.h | 9 ++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 145 +++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 33 +++++
drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 9 +-
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 7 +
10 files changed, 219 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 9698fec810ae..f45275c0034e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -272,6 +272,7 @@ i915-y += i915_perf.o
i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
+ pxp/intel_pxp_irq.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index d29126c458ba..0d3585efe2b8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -13,6 +13,7 @@
#include "intel_lrc_reg.h"
#include "intel_uncore.h"
#include "intel_rps.h"
+#include "pxp/intel_pxp_irq.h"
static void guc_irq_handler(struct intel_guc *guc, u16 iir)
{
@@ -64,6 +65,9 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance,
if (instance == OTHER_GTPM_INSTANCE)
return gen11_rps_irq_handler(>->rps, iir);
+ if (instance == OTHER_KCR_INSTANCE)
+ return intel_pxp_irq_handler(>->pxp, iir);
+
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
instance, iir);
}
@@ -190,6 +194,9 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
intel_uncore_write(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
intel_uncore_write(uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, 0);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~0);
}
void gen11_gt_irq_postinstall(struct intel_gt *gt)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 224ad897af34..0dcc04c7d2d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7958,6 +7958,7 @@ enum {
/* irq instances for OTHER_CLASS */
#define OTHER_GUC_INSTANCE 0
#define OTHER_GTPM_INSTANCE 1
+#define OTHER_KCR_INSTANCE 4
#define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.c b/drivers/gpu/drm/i915/pxp/intel_pxp.c
index 916187a0e566..f6317ce645c7 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.c
@@ -2,7 +2,9 @@
/*
* Copyright(c) 2020 Intel Corporation.
*/
+#include <linux/workqueue.h>
#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
#include "intel_pxp_tee.h"
#include "gt/intel_context.h"
#include "i915_drv.h"
@@ -70,6 +72,9 @@ void intel_pxp_init(struct intel_pxp *pxp)
if (ret)
goto out_kcr;
+ intel_pxp_irq_init(pxp);
+ intel_pxp_irq_enable(pxp);
+
ret = intel_pxp_tee_component_init(pxp);
if (ret)
goto out_context;
@@ -91,6 +96,8 @@ void intel_pxp_fini(struct intel_pxp *pxp)
if (!intel_pxp_is_enabled(pxp))
return;
+ intel_pxp_irq_disable(pxp);
+
intel_pxp_tee_component_fini(pxp);
destroy_vcs_context(pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index e2acd06402cd..dce7b1a23850 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -9,6 +9,15 @@
#include "gt/intel_gt_types.h"
#include "intel_pxp_types.h"
+#define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1)
+#define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2)
+#define GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT BIT(3)
+
+#define GEN12_PXP_INTERRUPTS \
+ (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT | \
+ GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT | \
+ GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
+
static inline struct intel_gt *pxp_to_gt(struct intel_pxp *pxp)
{
return container_of(pxp, struct intel_gt, pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
new file mode 100644
index 000000000000..5ca0218a27d8
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+#include <linux/workqueue.h>
+#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
+#include "intel_pxp_session.h"
+#include "gt/intel_gt_irq.h"
+#include "i915_irq.h"
+#include "i915_reg.h"
+
+static int pxp_terminate(struct intel_pxp *pxp)
+{
+ int ret = 0;
+
+ mutex_lock(&pxp->mutex);
+
+ pxp->global_state_attacked = true;
+
+ ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp);
+
+ mutex_unlock(&pxp->mutex);
+
+ return ret;
+}
+
+static int pxp_terminate_complete(struct intel_pxp *pxp)
+{
+ int ret = 0;
+
+ mutex_lock(&pxp->mutex);
+
+ pxp->termination_in_progress = false;
+
+ if (pxp->global_state_attacked) {
+ pxp->global_state_attacked = false;
+
+ /* Re-create the arb session after teardown handle complete */
+ ret = intel_pxp_create_arb_session(pxp);
+ }
+
+ mutex_unlock(&pxp->mutex);
+ return ret;
+}
+
+static void intel_pxp_irq_work(struct work_struct *work)
+{
+ struct intel_pxp *pxp = container_of(work, typeof(*pxp), irq_work);
+ struct intel_gt *gt = pxp_to_gt(pxp);
+ u32 events = 0;
+
+ spin_lock_irq(>->irq_lock);
+ events = fetch_and_zero(&pxp->current_events);
+ spin_unlock_irq(>->irq_lock);
+
+ if (!events)
+ return;
+
+ if (events & (GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT |
+ GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT))
+ pxp_terminate(pxp);
+
+ if (events & GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
+ pxp_terminate_complete(pxp);
+
+ /*
+ * we expect the terminate complete to arrive quickly after emitting
+ * the terminate, so check back on it
+ */
+ if (pxp->irq_enabled)
+ queue_work(system_unbound_wq, &pxp->irq_work);
+}
+
+/**
+ * intel_pxp_irq_handler - Handles PXP interrupts.
+ * @pxp: pointer to pxp struct
+ * @iir: interrupt vector
+ */
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ if (GEM_WARN_ON(!intel_pxp_is_enabled(pxp)))
+ return;
+
+ lockdep_assert_held(>->irq_lock);
+
+ if (unlikely(!iir))
+ return;
+
+ pxp->current_events |= iir;
+ queue_work(system_unbound_wq, &pxp->irq_work);
+}
+
+static inline void __pxp_set_interrupts(struct intel_gt *gt, u32 interrupts)
+{
+ struct intel_uncore *uncore = gt->uncore;
+ const u32 mask = interrupts << 16;
+
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_ENABLE, mask);
+ intel_uncore_write(uncore, GEN11_CRYPTO_RSVD_INTR_MASK, ~mask);
+}
+
+static inline void pxp_irq_reset(struct intel_gt *gt)
+{
+ spin_lock_irq(>->irq_lock);
+ gen11_gt_reset_one_iir(gt, 0, GEN11_KCR);
+ spin_unlock_irq(>->irq_lock);
+}
+
+void intel_pxp_irq_init(struct intel_pxp *pxp)
+{
+ INIT_WORK(&pxp->irq_work, intel_pxp_irq_work);
+}
+
+void intel_pxp_irq_enable(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ spin_lock_irq(>->irq_lock);
+ if (!pxp->irq_enabled) {
+ WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
+ __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
+ pxp->irq_enabled = true;
+ }
+ spin_unlock_irq(>->irq_lock);
+}
+
+void intel_pxp_irq_disable(struct intel_pxp *pxp)
+{
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ spin_lock_irq(>->irq_lock);
+
+ pxp->irq_enabled = false;
+ __pxp_set_interrupts(gt, 0);
+
+ spin_unlock_irq(>->irq_lock);
+ intel_synchronize_irq(gt->i915);
+
+ pxp_irq_reset(gt);
+
+ flush_work(&pxp->irq_work);
+}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
new file mode 100644
index 000000000000..7a875831636d
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_IRQ_H__
+#define __INTEL_PXP_IRQ_H__
+
+#include <linux/types.h>
+
+struct intel_pxp;
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_irq_init(struct intel_pxp *pxp);
+void intel_pxp_irq_enable(struct intel_pxp *pxp);
+void intel_pxp_irq_disable(struct intel_pxp *pxp);
+void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
+#else
+void intel_pxp_irq_init(struct intel_pxp *pxp)
+{
+}
+void intel_pxp_irq_enable(struct intel_pxp *pxp)
+{
+}
+void intel_pxp_irq_disable(struct intel_pxp *pxp)
+{
+}
+static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_IRQ_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
index fe733cc69f27..d0cb35a8b991 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_session.c
@@ -117,6 +117,7 @@ int intel_pxp_arb_terminate_session_with_global_terminate(struct intel_pxp *pxp)
}
intel_uncore_write(gt->uncore, PXP_GLOBAL_TERMINATE, 1);
+ pxp->termination_in_progress = true;
return ret;
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index dd7161f176f1..f52150aca02b 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -95,9 +95,16 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
mutex_lock(&pxp->mutex);
/* Create arb session only if tee is ready, during system boot or sleep/resume */
- if (intel_pxp_arb_session_is_in_play(pxp))
+ if (intel_pxp_arb_session_is_in_play(pxp)) {
ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp);
+ if (!ret) {
+ mutex_unlock(&pxp->mutex);
+ ret = wait_for(!pxp->termination_in_progress, 10);
+ mutex_lock(&pxp->mutex);
+ }
+ }
+
if (!ret)
ret = intel_pxp_create_arb_session(pxp);
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index 30a6013b5d95..51915f7b1521 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
#include <linux/mutex.h>
+#include <linux/workqueue.h>
struct intel_context;
@@ -16,6 +17,12 @@ struct intel_pxp {
struct mutex mutex;
bool arb_is_in_play;
+ bool termination_in_progress;
+ bool global_state_attacked;
+
+ struct work_struct irq_work;
+ bool irq_enabled;
+ u32 current_events; /* protected with gt->irq_lock */
};
#endif /* __INTEL_PXP_TYPES_H__ */
--
2.29.2
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^ permalink raw reply related [flat|nested] 41+ messages in thread* [Intel-gfx] [RFC 10/14] drm/i915/pxp: Enable PXP power management
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (8 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 09/14] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 13:06 ` Chris Wilson
2021-02-06 2:09 ` [Intel-gfx] [RFC 11/14] drm/i915/uapi: introduce drm_i915_gem_create_ext Daniele Ceraolo Spurio
` (9 subsequent siblings)
19 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang, Sean Z, Huang
From: "Huang, Sean Z" <sean.z.huang@intel.com>
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should unconditionally terminate the hardware
sessions and cleanup all the software states after the power cycle.
Signed-off-by: Huang, Sean Z <sean.z.huang@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 ++
drivers/gpu/drm/i915/i915_drv.c | 4 +
drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 10 ++-
drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 94 ++++++++++++++++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 36 +++++++++
drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 1 +
7 files changed, 148 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f45275c0034e..51c56889cfeb 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -273,6 +273,7 @@ i915-$(CONFIG_DRM_I915_PXP) += \
pxp/intel_pxp.o \
pxp/intel_pxp_cmd.o \
pxp/intel_pxp_irq.o \
+ pxp/intel_pxp_pm.o \
pxp/intel_pxp_session.o \
pxp/intel_pxp_tee.o
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index 0bd303d2823e..160a60e701dc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -19,6 +19,7 @@
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
+#include "pxp/intel_pxp_pm.h"
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
@@ -260,6 +261,8 @@ int intel_gt_resume(struct intel_gt *gt)
intel_uc_resume(>->uc);
+ intel_pxp_pm_resume(>->pxp);
+
user_forcewake(gt, false);
out_fw:
@@ -294,6 +297,7 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
user_forcewake(gt, true);
wait_for_suspend(gt);
+ intel_pxp_pm_prepare_suspend(>->pxp);
intel_uc_suspend(>->uc);
}
@@ -355,6 +359,8 @@ int intel_gt_runtime_resume(struct intel_gt *gt)
intel_gt_init_swizzling(gt);
intel_ggtt_restore_fences(gt->ggtt);
+ intel_pxp_runtime_resume(>->pxp);
+
return intel_uc_runtime_resume(>->uc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d1344eb6c849..172fd97de5eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -70,6 +70,8 @@
#include "gt/intel_gt_pm.h"
#include "gt/intel_rc6.h"
+#include "pxp/intel_pxp_pm.h"
+
#include "i915_debugfs.h"
#include "i915_drm_client.h"
#include "i915_drv.h"
@@ -1364,6 +1366,8 @@ static int i915_drm_resume_early(struct drm_device *dev)
intel_power_domains_resume(dev_priv);
+ intel_pxp_pm_resume_early(&dev_priv->gt.pxp);
+
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
return ret;
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
index 5ca0218a27d8..c20990f8943c 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
@@ -119,11 +119,13 @@ void intel_pxp_irq_enable(struct intel_pxp *pxp)
struct intel_gt *gt = pxp_to_gt(pxp);
spin_lock_irq(>->irq_lock);
- if (!pxp->irq_enabled) {
+
+ if (!pxp->irq_enabled)
WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_KCR));
- __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
- pxp->irq_enabled = true;
- }
+
+ __pxp_set_interrupts(gt, GEN12_PXP_INTERRUPTS);
+ pxp->irq_enabled = true;
+
spin_unlock_irq(>->irq_lock);
}
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
new file mode 100644
index 000000000000..f227634c2956
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright(c) 2020 Intel Corporation.
+ */
+
+#include "intel_pxp.h"
+#include "intel_pxp_irq.h"
+#include "intel_pxp_pm.h"
+#include "intel_pxp_session.h"
+
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ mutex_lock(&pxp->mutex);
+
+ /* Mark PXP ops as disabled */
+ pxp->global_state_in_suspend = true;
+
+ mutex_unlock(&pxp->mutex);
+
+ intel_pxp_irq_disable(pxp);
+}
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ mutex_lock(&pxp->mutex);
+
+ /* reset the attacked flag even if there was a pending */
+ if (pxp->global_state_in_suspend)
+ pxp->global_state_attacked = false;
+
+ mutex_unlock(&pxp->mutex);
+}
+
+int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ int ret = 0;
+ struct intel_gt *gt = pxp_to_gt(pxp);
+
+ if (!intel_pxp_is_enabled(pxp))
+ return 0;
+
+ intel_pxp_irq_enable(pxp);
+
+ mutex_lock(&pxp->mutex);
+
+ /* Re-enable PXP ops */
+ if (pxp->global_state_in_suspend) {
+ /*
+ * Note: we won't re-create the session as part of the irq
+ * generated by this termination because
+ * pxp->global_state_attacked is not set. The session
+ * will be recreated as part of the mei component re-binding.
+ */
+ ret = intel_pxp_arb_terminate_session_with_global_terminate(pxp);
+ if (ret) {
+ drm_err(>->i915->drm,
+ "Failed to terminate the arb session on resume\n");
+ goto end;
+ }
+
+ pxp->global_state_in_suspend = false;
+ }
+
+end:
+ mutex_unlock(&pxp->mutex);
+
+ if (!ret) {
+ ret = wait_for(!pxp->termination_in_progress, 10);
+ if (ret) {
+ drm_err(>->i915->drm,
+ "Didn't recevive the PXP termination irq\n");
+ }
+ }
+
+ return ret;
+}
+
+void intel_pxp_runtime_resume(struct intel_pxp *pxp)
+{
+ if (!intel_pxp_is_enabled(pxp))
+ return;
+
+ /* interrupts are reset in the rpm resume path, so turn them back on */
+ intel_pxp_irq_enable(pxp);
+
+ return;
+}
+
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
new file mode 100644
index 000000000000..0150f28c0940
--- /dev/null
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright(c) 2020, Intel Corporation. All rights reserved.
+ */
+
+#ifndef __INTEL_PXP_PM_H__
+#define __INTEL_PXP_PM_H__
+
+#include "i915_drv.h"
+
+#ifdef CONFIG_DRM_I915_PXP
+void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp);
+
+void intel_pxp_pm_resume_early(struct intel_pxp *pxp);
+int intel_pxp_pm_resume(struct intel_pxp *pxp);
+void intel_pxp_runtime_resume(struct intel_pxp *pxp);
+#else
+static inline void intel_pxp_pm_prepare_suspend(struct intel_pxp *pxp)
+{
+}
+
+static inline void intel_pxp_pm_resume_early(struct intel_pxp *pxp)
+{
+}
+
+static inline int intel_pxp_pm_resume(struct intel_pxp *pxp)
+{
+ return 0;
+}
+
+static inline void intel_pxp_runtime_resume(struct intel_pxp *pxp)
+{
+}
+#endif
+
+#endif /* __INTEL_PXP_PM_H__ */
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
index 51915f7b1521..5e400fb3cd15 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_types.h
@@ -19,6 +19,7 @@ struct intel_pxp {
bool arb_is_in_play;
bool termination_in_progress;
bool global_state_attacked;
+ bool global_state_in_suspend;
struct work_struct irq_work;
bool irq_enabled;
--
2.29.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 10/14] drm/i915/pxp: Enable PXP power management
2021-02-06 2:09 ` [Intel-gfx] [RFC 10/14] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio
@ 2021-02-06 13:06 ` Chris Wilson
2021-02-06 13:08 ` Chris Wilson
0 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2021-02-06 13:06 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Huang, Huang, Sean Z
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:21)
> + if (!ret) {
> + ret = wait_for(!pxp->termination_in_progress, 10);
This only works by chance. The compiler doesn't even have to reload the
variable. See struct completion.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 10/14] drm/i915/pxp: Enable PXP power management
2021-02-06 13:06 ` Chris Wilson
@ 2021-02-06 13:08 ` Chris Wilson
2021-02-08 18:33 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2021-02-06 13:08 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Huang, Huang, Sean Z
Quoting Chris Wilson (2021-02-06 13:06:05)
> Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:21)
> > + if (!ret) {
> > + ret = wait_for(!pxp->termination_in_progress, 10);
>
> This only works by chance. The compiler doesn't even have to reload the
> variable. See struct completion.
It appears we already have a ready made one with the termination
i915_request. But that will require RCU pointer management...
-Chris
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 10/14] drm/i915/pxp: Enable PXP power management
2021-02-06 13:08 ` Chris Wilson
@ 2021-02-08 18:33 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-08 18:33 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Huang, Sean Z
On 2/6/2021 5:08 AM, Chris Wilson wrote:
> Quoting Chris Wilson (2021-02-06 13:06:05)
>> Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:21)
>>> + if (!ret) {
>>> + ret = wait_for(!pxp->termination_in_progress, 10);
>> This only works by chance. The compiler doesn't even have to reload the
>> variable. See struct completion.
This was a last minute addition when I was told that waiting on the
in_play state change was not enough to guarantee full invalidation and I
admit I didn't fully think it through because I want to get the RFC out.
> It appears we already have a ready made one with the termination
> i915_request. But that will require RCU pointer management...
> -Chris
I've tried to keep this decoupled from the request because after the
request completion there is an MMIO write and only after that we start
waiting for the interrupt. I'll go with a struct completion.
Daniele
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 11/14] drm/i915/uapi: introduce drm_i915_gem_create_ext
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (9 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 10/14] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 2:09 ` [Intel-gfx] [RFC 12/14] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio
` (8 subsequent siblings)
19 siblings, 0 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Bommu Krishnaiah, Matthew Auld
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 41 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_drv.c | 2 +-
include/uapi/drm/i915_drm.h | 47 ++++++++++++++++++++++
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 45d60e3d98e3..3ad3413c459f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -7,6 +7,7 @@
#include "gem/i915_gem_region.h"
#include "i915_drv.h"
+#include "i915_user_extensions.h"
static int
i915_gem_create(struct drm_file *file,
@@ -91,6 +92,35 @@ i915_gem_dumb_create(struct drm_file *file,
&args->size, &args->handle);
}
+struct create_ext {
+ struct drm_i915_private *i915;
+};
+
+static int __create_setparam(struct drm_i915_gem_object_param *args,
+ struct create_ext *ext_data)
+{
+ if (!(args->param & I915_OBJECT_PARAM)) {
+ DRM_DEBUG("Missing I915_OBJECT_PARAM namespace\n");
+ return -EINVAL;
+ }
+
+ return -EINVAL;
+}
+
+static int create_setparam(struct i915_user_extension __user *base, void *data)
+{
+ struct drm_i915_gem_create_ext_setparam ext;
+
+ if (copy_from_user(&ext, base, sizeof(ext)))
+ return -EFAULT;
+
+ return __create_setparam(&ext.param, data);
+}
+
+static const i915_user_extension_fn create_extensions[] = {
+ [I915_GEM_CREATE_EXT_SETPARAM] = create_setparam,
+};
+
/**
* Creates a new mm object and returns a handle to it.
* @dev: drm device pointer
@@ -102,10 +132,19 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file)
{
struct drm_i915_private *i915 = to_i915(dev);
- struct drm_i915_gem_create *args = data;
+ struct create_ext ext_data = { .i915 = i915 };
+ struct drm_i915_gem_create_ext *args = data;
+ int ret;
i915_gem_flush_free_objects(i915);
+ ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
+ create_extensions,
+ ARRAY_SIZE(create_extensions),
+ &ext_data);
+ if (ret)
+ return ret;
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 172fd97de5eb..d69fce617e8b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1753,7 +1753,7 @@ static const struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
- DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 56c6bfe6c2d0..c5ed7680c252 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -392,6 +392,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
@@ -729,6 +730,27 @@ struct drm_i915_gem_create {
__u32 pad;
};
+struct drm_i915_gem_create_ext {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+#define I915_GEM_CREATE_EXT_SETPARAM (1u << 0)
+#define I915_GEM_CREATE_EXT_FLAGS_UNKNOWN \
+ (-(I915_GEM_CREATE_EXT_SETPARAM << 1))
+ __u64 extensions;
+
+};
+
struct drm_i915_gem_pread {
/** Handle for the object being read. */
__u32 handle;
@@ -1699,6 +1721,31 @@ struct drm_i915_gem_context_param {
__u64 value;
};
+struct drm_i915_gem_object_param {
+ /* Object handle (0 for I915_GEM_CREATE_EXT_SETPARAM) */
+ __u32 handle;
+
+ /* Data pointer size */
+ __u32 size;
+
+/*
+ * I915_OBJECT_PARAM:
+ *
+ * Select object namespace for the param.
+ */
+#define I915_OBJECT_PARAM (1ull << 32)
+
+ __u64 param;
+
+ /* Data value or pointer */
+ __u64 data;
+};
+
+struct drm_i915_gem_create_ext_setparam {
+ struct i915_user_extension base;
+ struct drm_i915_gem_object_param param;
+};
+
/**
* Context SSEU programming
*
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* [Intel-gfx] [RFC 12/14] drm/i915/pxp: User interface for Protected buffer
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (10 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 11/14] drm/i915/uapi: introduce drm_i915_gem_create_ext Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 12:25 ` Chris Wilson
2021-02-06 2:09 ` [Intel-gfx] [RFC 13/14] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio
` (7 subsequent siblings)
19 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang Sean Z, Kondapally Kalyan, Bommu Krishnaiah
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
This api allow user mode to create Protected buffer and context creation.
Only contexts created with the flag set are allowed to operate on
protected buffers.
We only allow setting the flags at creation time; the context flag also
requires the context to be marked as unrecoverable.
This is a rework + squash of the original code by Bommu Krishnaiah. I've
authorship unchanged since significant chunks have not been modified.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 34 +++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 ++++
.../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 +++++++++++++--
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +++++
.../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +++
drivers/gpu/drm/i915/pxp/intel_pxp.h | 10 ++++++
include/uapi/drm/i915_drm.h | 19 +++++++++++
8 files changed, 108 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index ecacfae8412d..d3d9b4578ba8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -76,6 +76,8 @@
#include "gt/intel_gpu_commands.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
+
#include "i915_drm_client.h"
#include "i915_gem_context.h"
#include "i915_globals.h"
@@ -2006,6 +2008,27 @@ static int set_priority(struct i915_gem_context *ctx,
return 0;
}
+static int set_protected(struct i915_gem_context *ctx,
+ const struct drm_i915_gem_context_param *args)
+{
+ int ret = 0;
+
+ if (ctx->client) /* can't change this after creation! */
+ ret = -EEXIST;
+ else if (args->size)
+ ret = -EINVAL;
+ else if (i915_gem_context_is_recoverable(ctx))
+ ret = -EPERM;
+ else if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
+ ret = -ENODEV;
+ else if (args->value)
+ set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+ else
+ clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+
+ return ret;
+}
+
static int ctx_setparam(struct drm_i915_file_private *fpriv,
struct i915_gem_context *ctx,
struct drm_i915_gem_context_param *args)
@@ -2045,6 +2068,8 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
case I915_CONTEXT_PARAM_RECOVERABLE:
if (args->size)
ret = -EINVAL;
+ else if (i915_gem_context_can_use_protected_content(ctx))
+ ret = -EPERM;
else if (args->value)
i915_gem_context_set_recoverable(ctx);
else
@@ -2075,6 +2100,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
ret = set_ringsize(ctx, args);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ ret = set_protected(ctx, args);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
@@ -2532,6 +2561,11 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
ret = get_ringsize(ctx, args);
break;
+ case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ args->size = 0;
+ args->value = i915_gem_context_can_use_protected_content(ctx);
+ break;
+
case I915_CONTEXT_PARAM_BAN_PERIOD:
default:
ret = -EINVAL;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index b5c908f3f4f2..473bce972bb2 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -108,6 +108,12 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
clear_bit(CONTEXT_USER_ENGINES, &ctx->flags);
}
+static inline bool
+i915_gem_context_can_use_protected_content(const struct i915_gem_context *ctx)
+{
+ return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
+}
+
/* i915_gem_context.c */
void i915_gem_init__contexts(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 085f6a3735e8..1cab741983c9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -130,6 +130,7 @@ struct i915_gem_context {
#define UCONTEXT_BANNABLE 2
#define UCONTEXT_RECOVERABLE 3
#define UCONTEXT_PERSISTENCE 4
+#define UCONTEXT_PROTECTED 5
/**
* @flags: small set of booleans
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index 3ad3413c459f..ac246b814a3a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -5,6 +5,7 @@
#include "gem/i915_gem_ioctls.h"
#include "gem/i915_gem_region.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_user_extensions.h"
@@ -13,7 +14,8 @@ static int
i915_gem_create(struct drm_file *file,
struct intel_memory_region *mr,
u64 *size_p,
- u32 *handle_p)
+ u32 *handle_p,
+ u64 user_flags)
{
struct drm_i915_gem_object *obj;
u32 handle;
@@ -35,6 +37,8 @@ i915_gem_create(struct drm_file *file,
GEM_BUG_ON(size != obj->base.size);
+ obj->user_flags = user_flags;
+
ret = drm_gem_handle_create(file, &obj->base, &handle);
/* drop reference from allocate - handle holds it now */
i915_gem_object_put(obj);
@@ -89,11 +93,12 @@ i915_gem_dumb_create(struct drm_file *file,
return i915_gem_create(file,
intel_memory_region_by_type(to_i915(dev),
mem_type),
- &args->size, &args->handle);
+ &args->size, &args->handle, 0);
}
struct create_ext {
struct drm_i915_private *i915;
+ unsigned long user_flags;
};
static int __create_setparam(struct drm_i915_gem_object_param *args,
@@ -104,6 +109,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
return -EINVAL;
}
+ switch (lower_32_bits(args->param)) {
+ case I915_PARAM_PROTECTED_CONTENT:
+ if (args->size) {
+ return -EINVAL;
+ } else if (args->data) {
+ ext_data->user_flags = args->data;
+ return 0;
+ }
+ break;
+ }
+
return -EINVAL;
}
@@ -145,8 +161,13 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
if (ret)
return ret;
+ if (ext_data.user_flags & I915_BO_PROTECTED) {
+ if (!intel_pxp_is_enabled(&i915->gt.pxp))
+ return -EINVAL;
+ }
+
return i915_gem_create(file,
intel_memory_region_by_type(i915,
INTEL_MEMORY_SYSTEM),
- &args->size, &args->handle);
+ &args->size, &args->handle, ext_data.user_flags);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index fe170186dd42..42e75d21f4d0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -20,6 +20,7 @@
#include "gt/intel_gt_buffer_pool.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_ring.h"
+#include "pxp/intel_pxp.h"
#include "i915_drv.h"
#include "i915_gem_clflush.h"
@@ -498,6 +499,14 @@ eb_validate_vma(struct i915_execbuffer *eb,
entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
return -EINVAL;
+
+ if (vma->obj->user_flags & I915_BO_PROTECTED) {
+ if (!intel_pxp_is_active(&vma->vm->gt->pxp))
+ return -ENODEV;
+ if (!i915_gem_context_can_use_protected_content(eb->gem_context))
+ return -EINVAL;
+ }
+
/* pad_to_size was once a reserved field, so sanitize it */
if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
if (unlikely(offset_in_page(entry->pad_to_size)))
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 0a1fdbac882e..9629b6b2e3d6 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -167,6 +167,11 @@ struct drm_i915_gem_object {
} mmo;
I915_SELFTEST_DECLARE(struct list_head st_link);
+ /**
+ * @user_flags: small set of booleans set by the user
+ */
+ unsigned long user_flags;
+#define I915_BO_PROTECTED BIT(0)
unsigned long flags;
#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
index dce7b1a23850..e5b5ae16b068 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
@@ -28,6 +28,16 @@ static inline bool intel_pxp_is_enabled(struct intel_pxp *pxp)
return pxp->ce;
}
+/*
+ * Note: the HW state can change at any point due to user actions, so keep that
+ * in mind when using the below check.
+ */
+static inline bool intel_pxp_is_active(struct intel_pxp *pxp)
+{
+ return intel_pxp_is_enabled(pxp) && pxp->arb_is_in_play &&
+ !pxp->global_state_in_suspend;
+}
+
#ifdef CONFIG_DRM_I915_PXP
void intel_pxp_init(struct intel_pxp *pxp);
void intel_pxp_fini(struct intel_pxp *pxp);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index c5ed7680c252..982b7ec6da48 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1716,6 +1716,15 @@ struct drm_i915_gem_context_param {
* Default is 16 KiB.
*/
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
+
+/*
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * Enable usage of protected context with the context. This flag can only be
+ * set at context creation time and, when set to true, must be preceded by
+ * an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE to false.
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
/* Must be kept compact -- no holes and well documented */
__u64 value;
@@ -1735,6 +1744,16 @@ struct drm_i915_gem_object_param {
*/
#define I915_OBJECT_PARAM (1ull << 32)
+/*
+ * I915_PARAM_PROTECTED_CONTENT:
+ *
+ * If set to true (1) buffer contents is expected to be protected by
+ * PAVP encryption and requires decryption for scan out and processing.
+ * Protected buffers can only be used in PAVP protected contexts.
+ * A protected buffer may become invalid as a result of PAVP teardown.
+ */
+#define I915_PARAM_PROTECTED_CONTENT 0x1
+
__u64 param;
/* Data value or pointer */
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 12/14] drm/i915/pxp: User interface for Protected buffer
2021-02-06 2:09 ` [Intel-gfx] [RFC 12/14] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio
@ 2021-02-06 12:25 ` Chris Wilson
2021-02-08 18:10 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2021-02-06 12:25 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Cc: Kondapally Kalyan, Huang Sean Z, Bommu Krishnaiah
Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:23)
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> This api allow user mode to create Protected buffer and context creation.
> Only contexts created with the flag set are allowed to operate on
> protected buffers.
>
> We only allow setting the flags at creation time; the context flag also
> requires the context to be marked as unrecoverable.
>
> This is a rework + squash of the original code by Bommu Krishnaiah. I've
> authorship unchanged since significant chunks have not been modified.
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
> Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
> Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
> Cc: Huang Sean Z <sean.z.huang@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 34 +++++++++++++++++++
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 ++++
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 +++++++++++++--
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +++++
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 10 ++++++
> include/uapi/drm/i915_drm.h | 19 +++++++++++
> 8 files changed, 108 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index ecacfae8412d..d3d9b4578ba8 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -76,6 +76,8 @@
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_ring.h"
>
> +#include "pxp/intel_pxp.h"
> +
> #include "i915_drm_client.h"
> #include "i915_gem_context.h"
> #include "i915_globals.h"
> @@ -2006,6 +2008,27 @@ static int set_priority(struct i915_gem_context *ctx,
> return 0;
> }
>
> +static int set_protected(struct i915_gem_context *ctx,
> + const struct drm_i915_gem_context_param *args)
> +{
> + int ret = 0;
> +
> + if (ctx->client) /* can't change this after creation! */
> + ret = -EEXIST;
> + else if (args->size)
> + ret = -EINVAL;
> + else if (i915_gem_context_is_recoverable(ctx))
> + ret = -EPERM;
> + else if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> + ret = -ENODEV;
I like HW validity checks early. I think that gives a more consistent
response.
> + else if (args->value)
> + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> + else
> + clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +
> + return ret;
> +}
> +
> static int ctx_setparam(struct drm_i915_file_private *fpriv,
> struct i915_gem_context *ctx,
> struct drm_i915_gem_context_param *args)
> @@ -2045,6 +2068,8 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> case I915_CONTEXT_PARAM_RECOVERABLE:
> if (args->size)
> ret = -EINVAL;
> + else if (i915_gem_context_can_use_protected_content(ctx))
> + ret = -EPERM;
> else if (args->value)
> i915_gem_context_set_recoverable(ctx);
> else
> @@ -2075,6 +2100,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
> ret = set_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + ret = set_protected(ctx, args);
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> @@ -2532,6 +2561,11 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
> ret = get_ringsize(ctx, args);
> break;
>
> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + args->size = 0;
> + args->value = i915_gem_context_can_use_protected_content(ctx);
The getter should also report feature availability, i.e.
if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
ret = -ENODEV;
else
args->value = i915_gem_context_can_use_protected_content(ctx);
Stick it in a get_protected_content() so it can sit next to the setter.
This allows userspace to do a feature query on an existing context (i.e.
the default context) without having to create anything [else]. For
example, that's useful for probing features sets once during screen setup.
> + break;
> +
> case I915_CONTEXT_PARAM_BAN_PERIOD:
> default:
> ret = -EINVAL;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index b5c908f3f4f2..473bce972bb2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -108,6 +108,12 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
> clear_bit(CONTEXT_USER_ENGINES, &ctx->flags);
> }
>
> +static inline bool
> +i915_gem_context_can_use_protected_content(const struct i915_gem_context *ctx)
> +{
> + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
> +}
> +
> /* i915_gem_context.c */
> void i915_gem_init__contexts(struct drm_i915_private *i915);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 085f6a3735e8..1cab741983c9 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -130,6 +130,7 @@ struct i915_gem_context {
> #define UCONTEXT_BANNABLE 2
> #define UCONTEXT_RECOVERABLE 3
> #define UCONTEXT_PERSISTENCE 4
> +#define UCONTEXT_PROTECTED 5
>
> /**
> * @flags: small set of booleans
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index 3ad3413c459f..ac246b814a3a 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -5,6 +5,7 @@
>
> #include "gem/i915_gem_ioctls.h"
> #include "gem/i915_gem_region.h"
> +#include "pxp/intel_pxp.h"
>
> #include "i915_drv.h"
> #include "i915_user_extensions.h"
> @@ -13,7 +14,8 @@ static int
> i915_gem_create(struct drm_file *file,
> struct intel_memory_region *mr,
> u64 *size_p,
> - u32 *handle_p)
> + u32 *handle_p,
> + u64 user_flags)
> {
> struct drm_i915_gem_object *obj;
> u32 handle;
> @@ -35,6 +37,8 @@ i915_gem_create(struct drm_file *file,
>
> GEM_BUG_ON(size != obj->base.size);
>
> + obj->user_flags = user_flags;
> +
> ret = drm_gem_handle_create(file, &obj->base, &handle);
> /* drop reference from allocate - handle holds it now */
> i915_gem_object_put(obj);
> @@ -89,11 +93,12 @@ i915_gem_dumb_create(struct drm_file *file,
> return i915_gem_create(file,
> intel_memory_region_by_type(to_i915(dev),
> mem_type),
> - &args->size, &args->handle);
> + &args->size, &args->handle, 0);
> }
>
> struct create_ext {
> struct drm_i915_private *i915;
> + unsigned long user_flags;
> };
>
> static int __create_setparam(struct drm_i915_gem_object_param *args,
> @@ -104,6 +109,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
> return -EINVAL;
> }
>
> + switch (lower_32_bits(args->param)) {
> + case I915_PARAM_PROTECTED_CONTENT:
> + if (args->size) {
> + return -EINVAL;
> + } else if (args->data) {
> + ext_data->user_flags = args->data;
> + return 0;
> + }
> + break;
> + }
> +
> return -EINVAL;
> }
>
> @@ -145,8 +161,13 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
> if (ret)
> return ret;
>
> + if (ext_data.user_flags & I915_BO_PROTECTED) {
> + if (!intel_pxp_is_enabled(&i915->gt.pxp))
> + return -EINVAL;
> + }
> +
> return i915_gem_create(file,
> intel_memory_region_by_type(i915,
> INTEL_MEMORY_SYSTEM),
> - &args->size, &args->handle);
> + &args->size, &args->handle, ext_data.user_flags);
> }
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index fe170186dd42..42e75d21f4d0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -20,6 +20,7 @@
> #include "gt/intel_gt_buffer_pool.h"
> #include "gt/intel_gt_pm.h"
> #include "gt/intel_ring.h"
> +#include "pxp/intel_pxp.h"
>
> #include "i915_drv.h"
> #include "i915_gem_clflush.h"
> @@ -498,6 +499,14 @@ eb_validate_vma(struct i915_execbuffer *eb,
> entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
> return -EINVAL;
>
> +
> + if (vma->obj->user_flags & I915_BO_PROTECTED) {
> + if (!intel_pxp_is_active(&vma->vm->gt->pxp))
> + return -ENODEV;
TOCTOU?
> + if (!i915_gem_context_can_use_protected_content(eb->gem_context))
> + return -EINVAL;
There's no encryption keying to each context? Is more than one GEM
context allowed to enable protected content on itself and so snoop?
> + }
> +
> /* pad_to_size was once a reserved field, so sanitize it */
> if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
> if (unlikely(offset_in_page(entry->pad_to_size)))
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 0a1fdbac882e..9629b6b2e3d6 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -167,6 +167,11 @@ struct drm_i915_gem_object {
> } mmo;
>
> I915_SELFTEST_DECLARE(struct list_head st_link);
> + /**
> + * @user_flags: small set of booleans set by the user
> + */
> + unsigned long user_flags;
> +#define I915_BO_PROTECTED BIT(0)
>
> unsigned long flags;
> #define I915_BO_ALLOC_CONTIGUOUS BIT(0)
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> index dce7b1a23850..e5b5ae16b068 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
> @@ -28,6 +28,16 @@ static inline bool intel_pxp_is_enabled(struct intel_pxp *pxp)
> return pxp->ce;
> }
>
> +/*
> + * Note: the HW state can change at any point due to user actions, so keep that
> + * in mind when using the below check.
> + */
> +static inline bool intel_pxp_is_active(struct intel_pxp *pxp)
> +{
> + return intel_pxp_is_enabled(pxp) && pxp->arb_is_in_play &&
> + !pxp->global_state_in_suspend;
How about pxp makes it easy for us and sets pxp->active when all the
conditions are true.
> +}
> +
> #ifdef CONFIG_DRM_I915_PXP
> void intel_pxp_init(struct intel_pxp *pxp);
> void intel_pxp_fini(struct intel_pxp *pxp);
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index c5ed7680c252..982b7ec6da48 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -1716,6 +1716,15 @@ struct drm_i915_gem_context_param {
> * Default is 16 KiB.
> */
> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
> +
> +/*
> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
> + *
> + * Enable usage of protected context with the context. This flag can only be
First context here is content.
> + * set at context creation time and, when set to true, must be preceded by
> + * an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE to false.
For the errors we have that are unique to setting up the protected
context, please list them.
> + */
> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
> /* Must be kept compact -- no holes and well documented */
>
> __u64 value;
> @@ -1735,6 +1744,16 @@ struct drm_i915_gem_object_param {
> */
> #define I915_OBJECT_PARAM (1ull << 32)
>
> +/*
> + * I915_PARAM_PROTECTED_CONTENT:
> + *
> + * If set to true (1) buffer contents is expected to be protected by
> + * PAVP encryption and requires decryption for scan out and processing.
> + * Protected buffers can only be used in PAVP protected contexts.
> + * A protected buffer may become invalid as a result of PAVP teardown.
> + */
> +#define I915_PARAM_PROTECTED_CONTENT 0x1
Missing the OBJECT_PARAM namespace and bias. Missing the comment about
not leaving gaps for internal abuse, and missing parameter 0.
What happens if a protected object is used outside of a protected
enclave, either by mistake or by buffer passing? Do we class that as an
error, or leave it up to the HW? Details on protected buffer usage and
if it changes the flow at all.
For example you have added a couple of EINVAL, ENODEV checks. Those
errors should be discussed as potential outcomes of enabling protected
context.
I think this is at least two patches, for the 2 new bits of uAPI that
look like they can be introduced separately.
-Chris
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^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 12/14] drm/i915/pxp: User interface for Protected buffer
2021-02-06 12:25 ` Chris Wilson
@ 2021-02-08 18:10 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-08 18:10 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Bommu Krishnaiah, Huang Sean Z
On 2/6/2021 4:25 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2021-02-06 02:09:23)
>> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>
>> This api allow user mode to create Protected buffer and context creation.
>> Only contexts created with the flag set are allowed to operate on
>> protected buffers.
>>
>> We only allow setting the flags at creation time; the context flag also
>> requires the context to be marked as unrecoverable.
>>
>> This is a rework + squash of the original code by Bommu Krishnaiah. I've
>> authorship unchanged since significant chunks have not been modified.
>>
>> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Telukuntla Sreedhar <sreedhar.telukuntla@intel.com>
>> Cc: Kondapally Kalyan <kalyan.kondapally@intel.com>
>> Cc: Gupta Anshuman <Anshuman.Gupta@intel.com>
>> Cc: Huang Sean Z <sean.z.huang@intel.com>
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 34 +++++++++++++++++++
>> drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 ++++
>> .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 27 +++++++++++++--
>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +++++
>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +++
>> drivers/gpu/drm/i915/pxp/intel_pxp.h | 10 ++++++
>> include/uapi/drm/i915_drm.h | 19 +++++++++++
>> 8 files changed, 108 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> index ecacfae8412d..d3d9b4578ba8 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> @@ -76,6 +76,8 @@
>> #include "gt/intel_gpu_commands.h"
>> #include "gt/intel_ring.h"
>>
>> +#include "pxp/intel_pxp.h"
>> +
>> #include "i915_drm_client.h"
>> #include "i915_gem_context.h"
>> #include "i915_globals.h"
>> @@ -2006,6 +2008,27 @@ static int set_priority(struct i915_gem_context *ctx,
>> return 0;
>> }
>>
>> +static int set_protected(struct i915_gem_context *ctx,
>> + const struct drm_i915_gem_context_param *args)
>> +{
>> + int ret = 0;
>> +
>> + if (ctx->client) /* can't change this after creation! */
>> + ret = -EEXIST;
>> + else if (args->size)
>> + ret = -EINVAL;
>> + else if (i915_gem_context_is_recoverable(ctx))
>> + ret = -EPERM;
>> + else if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
>> + ret = -ENODEV;
> I like HW validity checks early. I think that gives a more consistent
> response.
Ok, will do it first.
>
>> + else if (args->value)
>> + set_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
>> + else
>> + clear_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
>> +
>> + return ret;
>> +}
>> +
>> static int ctx_setparam(struct drm_i915_file_private *fpriv,
>> struct i915_gem_context *ctx,
>> struct drm_i915_gem_context_param *args)
>> @@ -2045,6 +2068,8 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
>> case I915_CONTEXT_PARAM_RECOVERABLE:
>> if (args->size)
>> ret = -EINVAL;
>> + else if (i915_gem_context_can_use_protected_content(ctx))
>> + ret = -EPERM;
>> else if (args->value)
>> i915_gem_context_set_recoverable(ctx);
>> else
>> @@ -2075,6 +2100,10 @@ static int ctx_setparam(struct drm_i915_file_private *fpriv,
>> ret = set_ringsize(ctx, args);
>> break;
>>
>> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
>> + ret = set_protected(ctx, args);
>> + break;
>> +
>> case I915_CONTEXT_PARAM_BAN_PERIOD:
>> default:
>> ret = -EINVAL;
>> @@ -2532,6 +2561,11 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
>> ret = get_ringsize(ctx, args);
>> break;
>>
>> + case I915_CONTEXT_PARAM_PROTECTED_CONTENT:
>> + args->size = 0;
>> + args->value = i915_gem_context_can_use_protected_content(ctx);
> The getter should also report feature availability, i.e.
>
> if (!intel_pxp_is_enabled(&ctx->i915->gt.pxp))
> ret = -ENODEV;
> else
> args->value = i915_gem_context_can_use_protected_content(ctx);
>
> Stick it in a get_protected_content() so it can sit next to the setter.
>
> This allows userspace to do a feature query on an existing context (i.e.
> the default context) without having to create anything [else]. For
> example, that's useful for probing features sets once during screen setup.
ok
>> + break;
>> +
>> case I915_CONTEXT_PARAM_BAN_PERIOD:
>> default:
>> ret = -EINVAL;
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
>> index b5c908f3f4f2..473bce972bb2 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
>> @@ -108,6 +108,12 @@ i915_gem_context_clear_user_engines(struct i915_gem_context *ctx)
>> clear_bit(CONTEXT_USER_ENGINES, &ctx->flags);
>> }
>>
>> +static inline bool
>> +i915_gem_context_can_use_protected_content(const struct i915_gem_context *ctx)
>> +{
>> + return test_bit(UCONTEXT_PROTECTED, &ctx->user_flags);
>> +}
>> +
>> /* i915_gem_context.c */
>> void i915_gem_init__contexts(struct drm_i915_private *i915);
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
>> index 085f6a3735e8..1cab741983c9 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
>> @@ -130,6 +130,7 @@ struct i915_gem_context {
>> #define UCONTEXT_BANNABLE 2
>> #define UCONTEXT_RECOVERABLE 3
>> #define UCONTEXT_PERSISTENCE 4
>> +#define UCONTEXT_PROTECTED 5
>>
>> /**
>> * @flags: small set of booleans
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> index 3ad3413c459f..ac246b814a3a 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>> @@ -5,6 +5,7 @@
>>
>> #include "gem/i915_gem_ioctls.h"
>> #include "gem/i915_gem_region.h"
>> +#include "pxp/intel_pxp.h"
>>
>> #include "i915_drv.h"
>> #include "i915_user_extensions.h"
>> @@ -13,7 +14,8 @@ static int
>> i915_gem_create(struct drm_file *file,
>> struct intel_memory_region *mr,
>> u64 *size_p,
>> - u32 *handle_p)
>> + u32 *handle_p,
>> + u64 user_flags)
>> {
>> struct drm_i915_gem_object *obj;
>> u32 handle;
>> @@ -35,6 +37,8 @@ i915_gem_create(struct drm_file *file,
>>
>> GEM_BUG_ON(size != obj->base.size);
>>
>> + obj->user_flags = user_flags;
>> +
>> ret = drm_gem_handle_create(file, &obj->base, &handle);
>> /* drop reference from allocate - handle holds it now */
>> i915_gem_object_put(obj);
>> @@ -89,11 +93,12 @@ i915_gem_dumb_create(struct drm_file *file,
>> return i915_gem_create(file,
>> intel_memory_region_by_type(to_i915(dev),
>> mem_type),
>> - &args->size, &args->handle);
>> + &args->size, &args->handle, 0);
>> }
>>
>> struct create_ext {
>> struct drm_i915_private *i915;
>> + unsigned long user_flags;
>> };
>>
>> static int __create_setparam(struct drm_i915_gem_object_param *args,
>> @@ -104,6 +109,17 @@ static int __create_setparam(struct drm_i915_gem_object_param *args,
>> return -EINVAL;
>> }
>>
>> + switch (lower_32_bits(args->param)) {
>> + case I915_PARAM_PROTECTED_CONTENT:
>> + if (args->size) {
>> + return -EINVAL;
>> + } else if (args->data) {
>> + ext_data->user_flags = args->data;
>> + return 0;
>> + }
>> + break;
>> + }
>> +
>> return -EINVAL;
>> }
>>
>> @@ -145,8 +161,13 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
>> if (ret)
>> return ret;
>>
>> + if (ext_data.user_flags & I915_BO_PROTECTED) {
>> + if (!intel_pxp_is_enabled(&i915->gt.pxp))
>> + return -EINVAL;
>> + }
>> +
>> return i915_gem_create(file,
>> intel_memory_region_by_type(i915,
>> INTEL_MEMORY_SYSTEM),
>> - &args->size, &args->handle);
>> + &args->size, &args->handle, ext_data.user_flags);
>> }
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> index fe170186dd42..42e75d21f4d0 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> @@ -20,6 +20,7 @@
>> #include "gt/intel_gt_buffer_pool.h"
>> #include "gt/intel_gt_pm.h"
>> #include "gt/intel_ring.h"
>> +#include "pxp/intel_pxp.h"
>>
>> #include "i915_drv.h"
>> #include "i915_gem_clflush.h"
>> @@ -498,6 +499,14 @@ eb_validate_vma(struct i915_execbuffer *eb,
>> entry->offset != gen8_canonical_addr(entry->offset & I915_GTT_PAGE_MASK)))
>> return -EINVAL;
>>
>> +
>> + if (vma->obj->user_flags & I915_BO_PROTECTED) {
>> + if (!intel_pxp_is_active(&vma->vm->gt->pxp))
>> + return -ENODEV;
> TOCTOU?
You mean PXP going inactive after this check? There is no way to prevent
PXP going inactive at "inconvenient" times since the user can cause a
termination action at any time (e.g. via display hotplug), this is just
best effort for a properly behaved system. The HW ensures that the
security is maintained, but there could be some corruption. I have a
comment above intel_pxp_is_active to reflect this, I'll try to be a bit
more eloquent with it.
>
>> + if (!i915_gem_context_can_use_protected_content(eb->gem_context))
>> + return -EINVAL;
> There's no encryption keying to each context? Is more than one GEM
> context allowed to enable protected content on itself and so snoop?
No keying to context, PXP is a batch-level thing.
>
>> + }
>> +
>> /* pad_to_size was once a reserved field, so sanitize it */
>> if (entry->flags & EXEC_OBJECT_PAD_TO_SIZE) {
>> if (unlikely(offset_in_page(entry->pad_to_size)))
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> index 0a1fdbac882e..9629b6b2e3d6 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> @@ -167,6 +167,11 @@ struct drm_i915_gem_object {
>> } mmo;
>>
>> I915_SELFTEST_DECLARE(struct list_head st_link);
>> + /**
>> + * @user_flags: small set of booleans set by the user
>> + */
>> + unsigned long user_flags;
>> +#define I915_BO_PROTECTED BIT(0)
>>
>> unsigned long flags;
>> #define I915_BO_ALLOC_CONTIGUOUS BIT(0)
>> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp.h b/drivers/gpu/drm/i915/pxp/intel_pxp.h
>> index dce7b1a23850..e5b5ae16b068 100644
>> --- a/drivers/gpu/drm/i915/pxp/intel_pxp.h
>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp.h
>> @@ -28,6 +28,16 @@ static inline bool intel_pxp_is_enabled(struct intel_pxp *pxp)
>> return pxp->ce;
>> }
>>
>> +/*
>> + * Note: the HW state can change at any point due to user actions, so keep that
>> + * in mind when using the below check.
>> + */
>> +static inline bool intel_pxp_is_active(struct intel_pxp *pxp)
>> +{
>> + return intel_pxp_is_enabled(pxp) && pxp->arb_is_in_play &&
>> + !pxp->global_state_in_suspend;
> How about pxp makes it easy for us and sets pxp->active when all the
> conditions are true.
>
>> +}
>> +
>> #ifdef CONFIG_DRM_I915_PXP
>> void intel_pxp_init(struct intel_pxp *pxp);
>> void intel_pxp_fini(struct intel_pxp *pxp);
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index c5ed7680c252..982b7ec6da48 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -1716,6 +1716,15 @@ struct drm_i915_gem_context_param {
>> * Default is 16 KiB.
>> */
>> #define I915_CONTEXT_PARAM_RINGSIZE 0xc
>> +
>> +/*
>> + * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
>> + *
>> + * Enable usage of protected context with the context. This flag can only be
> First context here is content.
>
>> + * set at context creation time and, when set to true, must be preceded by
>> + * an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE to false.
> For the errors we have that are unique to setting up the protected
> context, please list them.
>
>> + */
>> +#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
>> /* Must be kept compact -- no holes and well documented */
>>
>> __u64 value;
>> @@ -1735,6 +1744,16 @@ struct drm_i915_gem_object_param {
>> */
>> #define I915_OBJECT_PARAM (1ull << 32)
>>
>> +/*
>> + * I915_PARAM_PROTECTED_CONTENT:
>> + *
>> + * If set to true (1) buffer contents is expected to be protected by
>> + * PAVP encryption and requires decryption for scan out and processing.
>> + * Protected buffers can only be used in PAVP protected contexts.
>> + * A protected buffer may become invalid as a result of PAVP teardown.
>> + */
>> +#define I915_PARAM_PROTECTED_CONTENT 0x1
> Missing the OBJECT_PARAM namespace and bias. Missing the comment about
> not leaving gaps for internal abuse, and missing parameter 0.
>
> What happens if a protected object is used outside of a protected
> enclave, either by mistake or by buffer passing? Do we class that as an
> error, or leave it up to the HW? Details on protected buffer usage and
> if it changes the flow at all.
There is no way for i915 to detect buffer usage outside of an enclave
given that the HW allows the same context to be used for both protected
an non-protected work with batch-level selection. The check in the
execbuf is to reduce the chance of that happening, but full security is
enforced by the HW.
>
> For example you have added a couple of EINVAL, ENODEV checks. Those
> errors should be discussed as potential outcomes of enabling protected
> context.
>
> I think this is at least two patches, for the 2 new bits of uAPI that
> look like they can be introduced separately.
ok, will split into separate BO and context patches.
Daniele
> -Chris
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^ permalink raw reply [flat|nested] 41+ messages in thread
* [Intel-gfx] [RFC 13/14] drm/i915/pxp: Add plane decryption support
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (11 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 12/14] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 2:09 ` [Intel-gfx] [RFC 14/14] drm/i915/pxp: enable PXP for integrated Gen12 Daniele Ceraolo Spurio
` (6 subsequent siblings)
19 siblings, 0 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang Sean Z, Gaurav Kumar, Bommu Krishnaiah
From: Anshuman Gupta <anshuman.gupta@intel.com>
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PXP session is enabled.
2. Buffer object is protected.
v2:
- Used gen fb obj user_flags instead gem_object_metadata. [Krishna]
v3:
- intel_pxp_gem_object_status() API changes.
v4: use intel_pxp_is_active (Daniele)
Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Huang Sean Z <sean.z.huang@intel.com>
Cc: Gaurav Kumar <kumar.gaurav@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 21 ++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 402030251c64..77156d38c7e3 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -39,6 +39,8 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_rect.h>
+#include "pxp/intel_pxp.h"
+
#include "i915_drv.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
@@ -738,6 +740,11 @@ icl_program_input_csc(struct intel_plane *plane,
PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
}
+static bool intel_fb_obj_protected(const struct drm_i915_gem_object *obj)
+{
+ return obj->user_flags & I915_BO_PROTECTED ? true : false;
+}
+
static void
skl_plane_async_flip(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -778,6 +785,7 @@ skl_program_plane(struct intel_plane *plane,
u32 surf_addr = plane_state->color_plane[color_plane].offset;
u32 stride = skl_plane_stride(plane_state, color_plane);
const struct drm_framebuffer *fb = plane_state->hw.fb;
+ const struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int aux_plane = intel_main_to_aux_plane(fb, color_plane);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -788,7 +796,7 @@ skl_program_plane(struct intel_plane *plane,
u8 alpha = plane_state->hw.alpha >> 8;
u32 plane_color_ctl = 0, aux_dist = 0;
unsigned long irqflags;
- u32 keymsk, keymax;
+ u32 keymsk, keymax, plane_surf;
u32 plane_ctl = plane_state->ctl;
plane_ctl |= skl_plane_ctl_crtc(crtc_state);
@@ -868,8 +876,15 @@ skl_program_plane(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
- intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
- intel_plane_ggtt_offset(plane_state) + surf_addr);
+ plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr;
+
+ if (intel_pxp_is_active(&dev_priv->gt.pxp) &&
+ intel_fb_obj_protected(obj))
+ plane_surf |= PLANE_SURF_DECRYPTION_ENABLED;
+ else
+ plane_surf &= ~PLANE_SURF_DECRYPTION_ENABLED;
+
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf);
if (plane_state->scaler_id >= 0)
skl_program_scaler(plane, crtc_state, plane_state);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0dcc04c7d2d8..6cb1283b4eed 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7223,6 +7223,7 @@ enum {
#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
#define PLANE_SURF(pipe, plane) \
_MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
+#define PLANE_SURF_DECRYPTION_ENABLED REG_BIT(2)
#define _PLANE_OFFSET_1_B 0x711a4
#define _PLANE_OFFSET_2_B 0x712a4
--
2.29.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* [Intel-gfx] [RFC 14/14] drm/i915/pxp: enable PXP for integrated Gen12
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (12 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 13/14] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio
@ 2021-02-06 2:09 ` Daniele Ceraolo Spurio
2021-02-06 2:15 ` [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (5 subsequent siblings)
19 siblings, 0 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:09 UTC (permalink / raw)
To: intel-gfx
Note that discrete cards can support PXP as well, but we haven't tested
on those yet so keeping it disabled for now.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 6cff7cf0f17b..aa5644206e38 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -880,6 +880,7 @@ static const struct intel_device_info jsl_info = {
}, \
TGL_CURSOR_OFFSETS, \
.has_global_mocs = 1, \
+ .has_pxp = 1, \
.display.has_dsb = 1
static const struct intel_device_info tgl_info = {
@@ -909,6 +910,7 @@ static const struct intel_device_info rkl_info = {
.memory_regions = REGION_SMEM | REGION_LMEM, \
.has_master_unit_irq = 1, \
.has_llc = 0, \
+ .has_pxp = 0, \
.has_snoop = 1, \
.is_dgfx = 1
--
2.29.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 00/14] Introduce Intel PXP
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (13 preceding siblings ...)
2021-02-06 2:09 ` [Intel-gfx] [RFC 14/14] drm/i915/pxp: enable PXP for integrated Gen12 Daniele Ceraolo Spurio
@ 2021-02-06 2:15 ` Daniele Ceraolo Spurio
2021-02-06 3:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (4 subsequent siblings)
19 siblings, 0 replies; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-06 2:15 UTC (permalink / raw)
To: intel-gfx; +Cc: Huang Sean Z, Gaurav Kumar, Huang, Ryan T, Chris Wilson
On 2/5/2021 6:09 PM, Daniele Ceraolo Spurio wrote:
> PXP (Protected Xe Path) is an i915 component, available on
> GEN12+, that helps to establish the hardware protected session
> and manage the status of the alive software session, as well
> as its life cycle.
>
> I'm taking over this series from Sean. I've significantly reworked the
> code since his last revisioni [1], including a different patch split, so
> I've reset the series revision count. I believe I've addressed most of
> the pending comments, but please point out aything I've missed.
>
> Still RFC for 2 reasons:
> - mutex usage needs a bit more reworking
> - very lightly tested
>
> [1] https://patchwork.freedesktop.org/series/84620/
>
> Cc: Huang Sean Z <sean.z.huang@intel.com>
> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Adding a couple more people:
Cc: Juston Li <juston.li@intel.com>
Cc: Ryan T Huang <ryan.t.huang@intel.com>
Daniele
>
> Anshuman Gupta (1):
> drm/i915/pxp: Add plane decryption support
>
> Bommu Krishnaiah (2):
> drm/i915/uapi: introduce drm_i915_gem_create_ext
> drm/i915/pxp: User interface for Protected buffer
>
> Daniele Ceraolo Spurio (5):
> drm/i915/pxp: Define PXP component interface
> drm/i915/pxp: define PXP device flag and kconfig
> drm/i915/pxp: allocate a vcs context for pxp usage
> drm/i915/pxp: set KCR reg init during the boot time
> drm/i915/pxp: enable PXP for integrated Gen12
>
> Huang, Sean Z (5):
> drm/i915/pxp: Implement funcs to create the TEE channel
> drm/i915/pxp: Create the arbitrary session after boot
> drm/i915/pxp: Implement arb session teardown
> drm/i915/pxp: Implement PXP irq handler
> drm/i915/pxp: Enable PXP power management
>
> Vitaly Lubart (1):
> mei: pxp: export pavp client to me client bus
>
> drivers/gpu/drm/i915/Kconfig | 11 +
> drivers/gpu/drm/i915/Makefile | 9 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 34 +++
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 +
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 +++++-
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/i915_drv.c | 7 +-
> drivers/gpu/drm/i915/i915_drv.h | 10 +
> drivers/gpu/drm/i915/i915_pci.c | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 107 ++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 54 ++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 227 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 147 +++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 33 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 94 +++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 36 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 123 ++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 200 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 29 +++
> drivers/misc/mei/Kconfig | 2 +
> drivers/misc/mei/Makefile | 1 +
> drivers/misc/mei/pxp/Kconfig | 13 +
> drivers/misc/mei/pxp/Makefile | 7 +
> drivers/misc/mei/pxp/mei_pxp.c | 230 ++++++++++++++++++
> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 ++++
> include/uapi/drm/i915_drm.h | 70 ++++++
> 40 files changed, 1685 insertions(+), 8 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> create mode 100644 drivers/misc/mei/pxp/Kconfig
> create mode 100644 drivers/misc/mei/pxp/Makefile
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
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^ permalink raw reply [flat|nested] 41+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (14 preceding siblings ...)
2021-02-06 2:15 ` [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
@ 2021-02-06 3:14 ` Patchwork
2021-02-06 3:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2021-02-06 3:14 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP
URL : https://patchwork.freedesktop.org/series/86798/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7aa9cb10d6b7 drm/i915/pxp: Define PXP component interface
-:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#27:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 52 lines checked
4f3333b243ad mei: pxp: export pavp client to me client bus
-:32: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#32:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 277 lines checked
32f694bec37d drm/i915/pxp: define PXP device flag and kconfig
-:41: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#41: FILE: drivers/gpu/drm/i915/i915_drv.h:1746:
+#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+ INTEL_INFO(dev_priv)->has_pxp) && \
+ VDBOX_MASK(&dev_priv->gt)
-:41: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#41: FILE: drivers/gpu/drm/i915/i915_drv.h:1746:
+#define HAS_PXP(dev_priv) (IS_ENABLED(CONFIG_DRM_I915_PXP) && \
+ INTEL_INFO(dev_priv)->has_pxp) && \
+ VDBOX_MASK(&dev_priv->gt)
total: 1 errors, 0 warnings, 1 checks, 34 lines checked
bd3c9d86e3d9 drm/i915/pxp: allocate a vcs context for pxp usage
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#79:
new file mode 100644
-:136: WARNING:RETURN_VOID: void function return statements are not generally useful
#136: FILE: drivers/gpu/drm/i915/pxp/intel_pxp.c:53:
+ return;
+}
total: 0 errors, 2 warnings, 0 checks, 159 lines checked
fba284057979 drm/i915/pxp: set KCR reg init during the boot time
4536d239a998 drm/i915/pxp: Implement funcs to create the TEE channel
-:97: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#97:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 161 lines checked
e2c06ca6e948 drm/i915/pxp: Create the arbitrary session after boot
-:46: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#46:
new file mode 100644
-:318: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#318: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_types.h:17:
+ struct mutex mutex;
-:331: CHECK:LINE_SPACING: Please don't use multiple blank lines
#331: FILE: include/uapi/drm/i915_drm.h:2379:
+
total: 0 errors, 1 warnings, 2 checks, 274 lines checked
708df2ee4706 drm/i915/pxp: Implement arb session teardown
-:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#27:
new file mode 100644
-:171: ERROR:MULTISTATEMENT_MACRO_USE_DO_WHILE: Macros with multiple statements should be enclosed in a do - while loop
#171: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c:140:
+#define MFX_WAIT_PXP \
+ MFX_WAIT | \
+ MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG;
-:171: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#171: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c:140:
+#define MFX_WAIT_PXP \
+ MFX_WAIT | \
+ MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG | \
+ MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG;
total: 1 errors, 2 warnings, 0 checks, 321 lines checked
1114f3b829b2 drm/i915/pxp: Implement PXP irq handler
-:124: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#124:
new file mode 100644
-:301: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#301: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:22:
+}
+void intel_pxp_irq_enable(struct intel_pxp *pxp)
-:304: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#304: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:25:
+}
+void intel_pxp_irq_disable(struct intel_pxp *pxp)
-:307: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#307: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:28:
+}
+static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
total: 0 errors, 1 warnings, 3 checks, 301 lines checked
f02841c95381 drm/i915/pxp: Enable PXP power management
-:110: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#110:
new file mode 100644
-:207: WARNING:RETURN_VOID: void function return statements are not generally useful
#207: FILE: drivers/gpu/drm/i915/pxp/intel_pxp_pm.c:93:
+ return;
+}
total: 0 errors, 2 warnings, 0 checks, 207 lines checked
3aa79d7b4bbd drm/i915/uapi: introduce drm_i915_gem_create_ext
-:106: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#106: FILE: include/uapi/drm/i915_drm.h:395:
+#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create_ext)
total: 0 errors, 1 warnings, 0 checks, 135 lines checked
998839e51267 drm/i915/pxp: User interface for Protected buffer
-:219: CHECK:LINE_SPACING: Please don't use multiple blank lines
#219: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:502:
+
total: 0 errors, 0 warnings, 1 checks, 230 lines checked
506139f99362 drm/i915/pxp: Add plane decryption support
fdf64b2df325 drm/i915/pxp: enable PXP for integrated Gen12
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Intel PXP
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (15 preceding siblings ...)
2021-02-06 3:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2021-02-06 3:16 ` Patchwork
2021-02-06 3:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2021-02-06 3:16 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Introduce Intel PXP
URL : https://patchwork.freedesktop.org/series/86798/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_reset.c:1323:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1450:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1504:15: warning: memset with byte count of 16777216
+./drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:19:6: warning: symbol 'intel_pxp_irq_init' was not declared. Should it be static?
+./drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:22:6: warning: symbol 'intel_pxp_irq_enable' was not declared. Should it be static?
+./drivers/gpu/drm/i915/pxp/intel_pxp_irq.h:25:6: warning: symbol 'intel_pxp_irq_disable' was not declared. Should it be static?
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Intel PXP
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (16 preceding siblings ...)
2021-02-06 3:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-02-06 3:45 ` Patchwork
2021-02-06 16:51 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-02-12 13:23 ` [Intel-gfx] [RFC 00/14] " Lionel Landwerlin
19 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2021-02-06 3:45 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3266 bytes --]
== Series Details ==
Series: Introduce Intel PXP
URL : https://patchwork.freedesktop.org/series/86798/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9741 -> Patchwork_19617
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/index.html
Known issues
------------
Here are the changes found in Patchwork_19617 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-7500u: [PASS][1] -> [DMESG-WARN][2] ([i915#2605])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/fi-kbl-7500u/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/fi-kbl-7500u/igt@i915_pm_rpm@module-reload.html
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [PASS][3] -> [DMESG-WARN][4] ([i915#402]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
#### Possible fixes ####
* igt@debugfs_test@read_all_entries:
- fi-tgl-y: [DMESG-WARN][5] ([i915#402]) -> [PASS][6] +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/fi-tgl-y/igt@debugfs_test@read_all_entries.html
[i915#2605]: https://gitlab.freedesktop.org/drm/intel/issues/2605
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (44 -> 38)
------------------------------
Missing (6): fi-jsl-1 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9741 -> Patchwork_19617
CI-20190529: 20190529
CI_DRM_9741: 439ad4a70b3d6663de543ee56478d64b16cca1cf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5994: 53268fc5e5dde45a16e7185023a42296e3599e6e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19617: fdf64b2df325397c9f8e9878427ffaf1068808e9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fdf64b2df325 drm/i915/pxp: enable PXP for integrated Gen12
506139f99362 drm/i915/pxp: Add plane decryption support
998839e51267 drm/i915/pxp: User interface for Protected buffer
3aa79d7b4bbd drm/i915/uapi: introduce drm_i915_gem_create_ext
f02841c95381 drm/i915/pxp: Enable PXP power management
1114f3b829b2 drm/i915/pxp: Implement PXP irq handler
708df2ee4706 drm/i915/pxp: Implement arb session teardown
e2c06ca6e948 drm/i915/pxp: Create the arbitrary session after boot
4536d239a998 drm/i915/pxp: Implement funcs to create the TEE channel
fba284057979 drm/i915/pxp: set KCR reg init during the boot time
bd3c9d86e3d9 drm/i915/pxp: allocate a vcs context for pxp usage
32f694bec37d drm/i915/pxp: define PXP device flag and kconfig
4f3333b243ad mei: pxp: export pavp client to me client bus
7aa9cb10d6b7 drm/i915/pxp: Define PXP component interface
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/index.html
[-- Attachment #1.2: Type: text/html, Size: 4068 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Intel PXP
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (17 preceding siblings ...)
2021-02-06 3:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-02-06 16:51 ` Patchwork
2021-02-12 13:23 ` [Intel-gfx] [RFC 00/14] " Lionel Landwerlin
19 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2021-02-06 16:51 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30242 bytes --]
== Series Details ==
Series: Introduce Intel PXP
URL : https://patchwork.freedesktop.org/series/86798/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9741_full -> Patchwork_19617_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_19617_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_19617_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19617_full:
### Piglit changes ###
#### Possible regressions ####
* spec@glsl-1.30@execution@texelfetch fs sampler2d 71x1-71x281:
- pig-glk-j5005: NOTRUN -> [INCOMPLETE][1] +3 similar issues
[1]: None
New tests
---------
New tests have been introduced between CI_DRM_9741_full and Patchwork_19617_full:
### New Piglit tests (1) ###
* spec@arb_depth_buffer_float@depthstencil-render-miplevels 292 d=s=z32f_s8:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_19617_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][2] -> [FAIL][3] ([i915#2842]) +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-wide-active@vcs1:
- shard-iclb: NOTRUN -> [FAIL][4] ([i915#2389]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb1/igt@gem_exec_reloc@basic-wide-active@vcs1.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-iclb: [PASS][5] -> [DMESG-WARN][6] ([i915#2803])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb2/igt@gem_exec_schedule@u-fairslice@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb1/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- shard-kbl: NOTRUN -> [SKIP][7] ([fdo#109271]) +133 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@gem_render_copy@x-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@process-exit-mmap-busy@uc:
- shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1699]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl1/igt@gem_userptr_blits@process-exit-mmap-busy@uc.html
* igt@gem_userptr_blits@process-exit-mmap@gtt:
- shard-kbl: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1699]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@gem_userptr_blits@process-exit-mmap@gtt.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-apl: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#658])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl3/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-b:
- shard-kbl: [PASS][11] -> [DMESG-WARN][12] ([i915#62]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-b.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@dp-1-pipe-b.html
* igt@kms_ccs@pipe-c-bad-aux-stride:
- shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111304])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl3/igt@kms_ccs@pipe-c-bad-aux-stride.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl3/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +6 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl1/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [fdo#111827]) +12 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl1/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color@pipe-d-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271]) +80 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl1/igt@kms_color@pipe-d-ctm-0-5.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][18] ([i915#1319])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl2/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#54]) +5 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl4/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl8/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen:
- shard-skl: NOTRUN -> [FAIL][23] ([i915#54]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-tglb: [PASS][24] -> [FAIL][25] ([i915#2346]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-tglb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-tglb3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][26] -> [FAIL][27] ([i915#79])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
- shard-apl: [PASS][28] -> [FAIL][29] ([i915#79])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl6/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl3/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: [PASS][30] -> [INCOMPLETE][31] ([i915#146] / [i915#198])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl7/igt@kms_flip@flip-vs-suspend@b-edp1.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl10/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][32] ([i915#180]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-kbl: NOTRUN -> [FAIL][33] ([i915#2641])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#2642])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#2672])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271]) +28 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][37] -> [DMESG-WARN][38] ([i915#180]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl2/igt@kms_hdr@bpc-switch-suspend.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#533])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][40] ([fdo#108145] / [i915#265])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][41] ([i915#265])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#658]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][43] -> [SKIP][44] ([fdo#109441]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb2/igt@kms_psr@psr2_suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb7/igt@kms_psr@psr2_suspend.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][45] ([IGT#2])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl3/igt@kms_sysfs_edid_timing.html
* igt@kms_writeback@writeback-fb-id:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#2437])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl3/igt@kms_writeback@writeback-fb-id.html
* igt@perf@polling:
- shard-skl: [PASS][47] -> [FAIL][48] ([i915#1542])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl5/igt@perf@polling.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl9/igt@perf@polling.html
* igt@perf@polling-parameterized:
- shard-apl: [PASS][49] -> [FAIL][50] ([i915#1542])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl7/igt@perf@polling-parameterized.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl8/igt@perf@polling-parameterized.html
* igt@sysfs_clients@recycle:
- shard-kbl: [PASS][51] -> [FAIL][52] ([i915#3028])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl6/igt@sysfs_clients@recycle.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl2/igt@sysfs_clients@recycle.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][53] ([i915#658]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb7/igt@feature_discovery@psr2.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-skl: [INCOMPLETE][55] ([i915#198]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl2/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-iclb: [FAIL][57] ([i915#2842]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb1/igt@gem_exec_fair@basic-none-vip@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb8/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][59] ([i915#2842]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [FAIL][61] ([i915#2842]) -> [PASS][62] +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-tglb6/igt@gem_exec_fair@basic-pace@bcs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-tglb3/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][63] ([i915#2842]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl2/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl: [DMESG-WARN][65] ([i915#1610] / [i915#2803]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl6/igt@gem_exec_schedule@u-fairslice@rcs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl10/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs1:
- shard-iclb: [DMESG-WARN][67] ([i915#2803]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb2/igt@gem_exec_schedule@u-fairslice@vcs1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb1/igt@gem_exec_schedule@u-fairslice@vcs1.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [INCOMPLETE][69] ([i915#180] / [i915#2405]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl4/igt@gem_softpin@noreloc-s3.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][71] ([i915#454]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [DMESG-WARN][73] ([i915#180]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl1/igt@i915_suspend@debugfs-reader.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl2/igt@i915_suspend@debugfs-reader.html
* igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
- shard-skl: [FAIL][75] ([i915#54]) -> [PASS][76] +7 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy:
- shard-skl: [FAIL][77] ([i915#2346]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][79] ([i915#2122]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [FAIL][81] ([i915#1188]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl6/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [DMESG-WARN][83] ([i915#180] / [i915#533]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-kbl: [DMESG-WARN][85] ([i915#180]) -> [PASS][86] +3 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][87] ([fdo#108145] / [i915#265]) -> [PASS][88] +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][89] ([fdo#109441]) -> [PASS][90] +3 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@sysfs_clients@recycle:
- shard-iclb: [FAIL][91] ([i915#3028]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb4/igt@sysfs_clients@recycle.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb2/igt@sysfs_clients@recycle.html
- shard-glk: [FAIL][93] ([i915#3028]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-glk1/igt@sysfs_clients@recycle.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-glk4/igt@sysfs_clients@recycle.html
* {igt@sysfs_clients@recycle-many}:
- shard-apl: [FAIL][95] ([i915#3028]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl7/igt@sysfs_clients@recycle-many.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl6/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-10@vcs0:
- shard-apl: [SKIP][97] ([fdo#109271] / [i915#3026]) -> [PASS][98] +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl8/igt@sysfs_clients@sema-10@vcs0.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl8/igt@sysfs_clients@sema-10@vcs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][99] ([fdo#109271]) -> [FAIL][100] ([i915#2842])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl2/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][101] ([i915#2849]) -> [FAIL][102] ([i915#2842])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][103] ([i915#1804] / [i915#2684]) -> [WARN][104] ([i915#2681] / [i915#2684])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][105] ([i915#2681] / [i915#2684]) -> [WARN][106] ([i915#1804] / [i915#2684])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-iclb: [SKIP][107] ([i915#658]) -> [SKIP][108] ([i915#2920]) +2 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb1/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][109] ([i915#2920]) -> [SKIP][110] ([i915#658])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122]) ([i915#1436] / [i915#1814] / [i915#2283] / [i915#2295] / [i915#2505] / [i915#3002]) -> ([FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131]) ([i915#1436] / [i915#1814] / [i915#2283] / [i915#2295] / [i915#3002])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl7/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl4/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl6/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl7/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl4/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl4/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl4/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl7/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl4/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl2/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl2/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-kbl1/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl7/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl2/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl2/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl2/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl4/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-kbl3/igt@runner@aborted.html
- shard-apl: ([FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#2283] / [i915#2295] / [i915#3002]) -> ([FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([fdo#109271] / [i915#1814] / [i915#2283] / [i915#2295] / [i915#3002])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl1/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl6/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl6/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl2/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl6/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl6/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-apl1/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl6/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl3/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl2/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl3/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl7/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-apl3/igt@runner@aborted.html
- shard-skl: ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148]) ([i915#2295] / [i915#2426] / [i915#3002]) -> ([FAIL][149], [FAIL][150], [FAIL][151]) ([i915#2295] / [i915#3002])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl8/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl9/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl6/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9741/shard-skl2/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl1/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl7/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/shard-skl9/igt@runner@aborted.html
### Piglit changes ###
#### Issues hit ####
* spec@glsl-1.30@execution@texelfetch fs sampler2d 1x281-501x281:
- pig-glk-j5005: NOTRUN -> [INCOMPLETE][152] ([i915#2981])
[152]: None
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1699]: https://gitlab.freedesktop.org/drm/intel/issues/1699
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2405]: https://gitlab.freedesktop.org/drm/intel/issues/2405
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2641]: https://gitlab.freedesktop.org/drm/intel/issues/2641
[i915#2642]: h
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19617/index.html
[-- Attachment #1.2: Type: text/html, Size: 35870 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 00/14] Introduce Intel PXP
2021-02-06 2:09 [Intel-gfx] [RFC 00/14] Introduce Intel PXP Daniele Ceraolo Spurio
` (18 preceding siblings ...)
2021-02-06 16:51 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-02-12 13:23 ` Lionel Landwerlin
2021-02-12 15:10 ` Daniele Ceraolo Spurio
19 siblings, 1 reply; 41+ messages in thread
From: Lionel Landwerlin @ 2021-02-12 13:23 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Cc: Gaurav Kumar, Huang Sean Z, Chris Wilson
I just gave a try to this new iteration and it's apparently failing to
enable PXP on a machine with this pciID : 0x9a68.
-Lionel
On 06/02/2021 04:09, Daniele Ceraolo Spurio wrote:
> PXP (Protected Xe Path) is an i915 component, available on
> GEN12+, that helps to establish the hardware protected session
> and manage the status of the alive software session, as well
> as its life cycle.
>
> I'm taking over this series from Sean. I've significantly reworked the
> code since his last revisioni [1], including a different patch split, so
> I've reset the series revision count. I believe I've addressed most of
> the pending comments, but please point out aything I've missed.
>
> Still RFC for 2 reasons:
> - mutex usage needs a bit more reworking
> - very lightly tested
>
> [1] https://patchwork.freedesktop.org/series/84620/
>
> Cc: Huang Sean Z <sean.z.huang@intel.com>
> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>
> Anshuman Gupta (1):
> drm/i915/pxp: Add plane decryption support
>
> Bommu Krishnaiah (2):
> drm/i915/uapi: introduce drm_i915_gem_create_ext
> drm/i915/pxp: User interface for Protected buffer
>
> Daniele Ceraolo Spurio (5):
> drm/i915/pxp: Define PXP component interface
> drm/i915/pxp: define PXP device flag and kconfig
> drm/i915/pxp: allocate a vcs context for pxp usage
> drm/i915/pxp: set KCR reg init during the boot time
> drm/i915/pxp: enable PXP for integrated Gen12
>
> Huang, Sean Z (5):
> drm/i915/pxp: Implement funcs to create the TEE channel
> drm/i915/pxp: Create the arbitrary session after boot
> drm/i915/pxp: Implement arb session teardown
> drm/i915/pxp: Implement PXP irq handler
> drm/i915/pxp: Enable PXP power management
>
> Vitaly Lubart (1):
> mei: pxp: export pavp client to me client bus
>
> drivers/gpu/drm/i915/Kconfig | 11 +
> drivers/gpu/drm/i915/Makefile | 9 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 34 +++
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 +
> .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 +++++-
> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +
> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/i915_drv.c | 7 +-
> drivers/gpu/drm/i915/i915_drv.h | 10 +
> drivers/gpu/drm/i915/i915_pci.c | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 2 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/pxp/intel_pxp.c | 107 ++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp.h | 54 ++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 227 +++++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 147 +++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 33 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 94 +++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 36 +++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 123 ++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 200 +++++++++++++++
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 29 +++
> drivers/misc/mei/Kconfig | 2 +
> drivers/misc/mei/Makefile | 1 +
> drivers/misc/mei/pxp/Kconfig | 13 +
> drivers/misc/mei/pxp/Makefile | 7 +
> drivers/misc/mei/pxp/mei_pxp.c | 230 ++++++++++++++++++
> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
> include/drm/i915_component.h | 1 +
> include/drm/i915_pxp_tee_interface.h | 45 ++++
> include/uapi/drm/i915_drm.h | 70 ++++++
> 40 files changed, 1685 insertions(+), 8 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
> create mode 100644 drivers/misc/mei/pxp/Kconfig
> create mode 100644 drivers/misc/mei/pxp/Makefile
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
> create mode 100644 include/drm/i915_pxp_tee_interface.h
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread* Re: [Intel-gfx] [RFC 00/14] Introduce Intel PXP
2021-02-12 13:23 ` [Intel-gfx] [RFC 00/14] " Lionel Landwerlin
@ 2021-02-12 15:10 ` Daniele Ceraolo Spurio
2021-02-12 15:13 ` Lionel Landwerlin
0 siblings, 1 reply; 41+ messages in thread
From: Daniele Ceraolo Spurio @ 2021-02-12 15:10 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx; +Cc: Gaurav Kumar, Huang Sean Z, Chris Wilson
On 2/12/2021 5:23 AM, Lionel Landwerlin wrote:
> I just gave a try to this new iteration and it's apparently failing to
> enable PXP on a machine with this pciID : 0x9a68.
>
What error are you seeing?
Daniele
> -Lionel
>
> On 06/02/2021 04:09, Daniele Ceraolo Spurio wrote:
>> PXP (Protected Xe Path) is an i915 component, available on
>> GEN12+, that helps to establish the hardware protected session
>> and manage the status of the alive software session, as well
>> as its life cycle.
>>
>> I'm taking over this series from Sean. I've significantly reworked the
>> code since his last revisioni [1], including a different patch split, so
>> I've reset the series revision count. I believe I've addressed most of
>> the pending comments, but please point out aything I've missed.
>>
>> Still RFC for 2 reasons:
>> - mutex usage needs a bit more reworking
>> - very lightly tested
>>
>> [1] https://patchwork.freedesktop.org/series/84620/
>>
>> Cc: Huang Sean Z <sean.z.huang@intel.com>
>> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>
>> Anshuman Gupta (1):
>> drm/i915/pxp: Add plane decryption support
>>
>> Bommu Krishnaiah (2):
>> drm/i915/uapi: introduce drm_i915_gem_create_ext
>> drm/i915/pxp: User interface for Protected buffer
>>
>> Daniele Ceraolo Spurio (5):
>> drm/i915/pxp: Define PXP component interface
>> drm/i915/pxp: define PXP device flag and kconfig
>> drm/i915/pxp: allocate a vcs context for pxp usage
>> drm/i915/pxp: set KCR reg init during the boot time
>> drm/i915/pxp: enable PXP for integrated Gen12
>>
>> Huang, Sean Z (5):
>> drm/i915/pxp: Implement funcs to create the TEE channel
>> drm/i915/pxp: Create the arbitrary session after boot
>> drm/i915/pxp: Implement arb session teardown
>> drm/i915/pxp: Implement PXP irq handler
>> drm/i915/pxp: Enable PXP power management
>>
>> Vitaly Lubart (1):
>> mei: pxp: export pavp client to me client bus
>>
>> drivers/gpu/drm/i915/Kconfig | 11 +
>> drivers/gpu/drm/i915/Makefile | 9 +
>> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 34 +++
>> drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 +
>> .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 +++++-
>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +
>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
>> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
>> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>> drivers/gpu/drm/i915/i915_drv.c | 7 +-
>> drivers/gpu/drm/i915/i915_drv.h | 10 +
>> drivers/gpu/drm/i915/i915_pci.c | 2 +
>> drivers/gpu/drm/i915/i915_reg.h | 2 +
>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>> drivers/gpu/drm/i915/pxp/intel_pxp.c | 107 ++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp.h | 54 ++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 227 +++++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 147 +++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 33 +++
>> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 94 +++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 36 +++
>> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 123 ++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 17 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 200 +++++++++++++++
>> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
>> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 29 +++
>> drivers/misc/mei/Kconfig | 2 +
>> drivers/misc/mei/Makefile | 1 +
>> drivers/misc/mei/pxp/Kconfig | 13 +
>> drivers/misc/mei/pxp/Makefile | 7 +
>> drivers/misc/mei/pxp/mei_pxp.c | 230 ++++++++++++++++++
>> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
>> include/drm/i915_component.h | 1 +
>> include/drm/i915_pxp_tee_interface.h | 45 ++++
>> include/uapi/drm/i915_drm.h | 70 ++++++
>> 40 files changed, 1685 insertions(+), 8 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>> create mode 100644 drivers/misc/mei/pxp/Kconfig
>> create mode 100644 drivers/misc/mei/pxp/Makefile
>> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
>> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
>> create mode 100644 include/drm/i915_pxp_tee_interface.h
>>
>
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [Intel-gfx] [RFC 00/14] Introduce Intel PXP
2021-02-12 15:10 ` Daniele Ceraolo Spurio
@ 2021-02-12 15:13 ` Lionel Landwerlin
0 siblings, 0 replies; 41+ messages in thread
From: Lionel Landwerlin @ 2021-02-12 15:13 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Cc: Gaurav Kumar, Huang Sean Z, Chris Wilson
On 12/02/2021 17:10, Daniele Ceraolo Spurio wrote:
>
> On 2/12/2021 5:23 AM, Lionel Landwerlin wrote:
>> I just gave a try to this new iteration and it's apparently failing
>> to enable PXP on a machine with this pciID : 0x9a68.
>>
>
> What error are you seeing?
>
> Daniele
Failure to create a protected GEM object, checking the HW register
(GEN12_KCR_SIP), the session seems to not be enabled.
-Lionel
>
>> -Lionel
>>
>> On 06/02/2021 04:09, Daniele Ceraolo Spurio wrote:
>>> PXP (Protected Xe Path) is an i915 component, available on
>>> GEN12+, that helps to establish the hardware protected session
>>> and manage the status of the alive software session, as well
>>> as its life cycle.
>>>
>>> I'm taking over this series from Sean. I've significantly reworked the
>>> code since his last revisioni [1], including a different patch
>>> split, so
>>> I've reset the series revision count. I believe I've addressed most of
>>> the pending comments, but please point out aything I've missed.
>>>
>>> Still RFC for 2 reasons:
>>> - mutex usage needs a bit more reworking
>>> - very lightly tested
>>>
>>> [1] https://patchwork.freedesktop.org/series/84620/
>>>
>>> Cc: Huang Sean Z <sean.z.huang@intel.com>
>>> Cc: Gaurav Kumar <kumar.gaurav@intel.com>
>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>>>
>>> Anshuman Gupta (1):
>>> drm/i915/pxp: Add plane decryption support
>>>
>>> Bommu Krishnaiah (2):
>>> drm/i915/uapi: introduce drm_i915_gem_create_ext
>>> drm/i915/pxp: User interface for Protected buffer
>>>
>>> Daniele Ceraolo Spurio (5):
>>> drm/i915/pxp: Define PXP component interface
>>> drm/i915/pxp: define PXP device flag and kconfig
>>> drm/i915/pxp: allocate a vcs context for pxp usage
>>> drm/i915/pxp: set KCR reg init during the boot time
>>> drm/i915/pxp: enable PXP for integrated Gen12
>>>
>>> Huang, Sean Z (5):
>>> drm/i915/pxp: Implement funcs to create the TEE channel
>>> drm/i915/pxp: Create the arbitrary session after boot
>>> drm/i915/pxp: Implement arb session teardown
>>> drm/i915/pxp: Implement PXP irq handler
>>> drm/i915/pxp: Enable PXP power management
>>>
>>> Vitaly Lubart (1):
>>> mei: pxp: export pavp client to me client bus
>>>
>>> drivers/gpu/drm/i915/Kconfig | 11 +
>>> drivers/gpu/drm/i915/Makefile | 9 +
>>> drivers/gpu/drm/i915/display/intel_sprite.c | 21 +-
>>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 34 +++
>>> drivers/gpu/drm/i915/gem/i915_gem_context.h | 6 +
>>> .../gpu/drm/i915/gem/i915_gem_context_types.h | 1 +
>>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 68 +++++-
>>> .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 9 +
>>> .../gpu/drm/i915/gem/i915_gem_object_types.h | 5 +
>>> drivers/gpu/drm/i915/gt/intel_gt.c | 5 +
>>> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 7 +
>>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 6 +
>>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>>> drivers/gpu/drm/i915/i915_drv.c | 7 +-
>>> drivers/gpu/drm/i915/i915_drv.h | 10 +
>>> drivers/gpu/drm/i915/i915_pci.c | 2 +
>>> drivers/gpu/drm/i915/i915_reg.h | 2 +
>>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>>> drivers/gpu/drm/i915/pxp/intel_pxp.c | 107 ++++++++
>>> drivers/gpu/drm/i915/pxp/intel_pxp.h | 54 ++++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 227 +++++++++++++++++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h | 15 ++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_irq.c | 147 +++++++++++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_irq.h | 33 +++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_pm.c | 94 +++++++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_pm.h | 36 +++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_session.c | 123 ++++++++++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_session.h | 17 ++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 200 +++++++++++++++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_tee.h | 17 ++
>>> drivers/gpu/drm/i915/pxp/intel_pxp_types.h | 29 +++
>>> drivers/misc/mei/Kconfig | 2 +
>>> drivers/misc/mei/Makefile | 1 +
>>> drivers/misc/mei/pxp/Kconfig | 13 +
>>> drivers/misc/mei/pxp/Makefile | 7 +
>>> drivers/misc/mei/pxp/mei_pxp.c | 230
>>> ++++++++++++++++++
>>> drivers/misc/mei/pxp/mei_pxp.h | 18 ++
>>> include/drm/i915_component.h | 1 +
>>> include/drm/i915_pxp_tee_interface.h | 45 ++++
>>> include/uapi/drm/i915_drm.h | 70 ++++++
>>> 40 files changed, 1685 insertions(+), 8 deletions(-)
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.c
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp.h
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.c
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_irq.h
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.c
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_pm.h
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.c
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_session.h
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_tee.h
>>> create mode 100644 drivers/gpu/drm/i915/pxp/intel_pxp_types.h
>>> create mode 100644 drivers/misc/mei/pxp/Kconfig
>>> create mode 100644 drivers/misc/mei/pxp/Makefile
>>> create mode 100644 drivers/misc/mei/pxp/mei_pxp.c
>>> create mode 100644 drivers/misc/mei/pxp/mei_pxp.h
>>> create mode 100644 include/drm/i915_pxp_tee_interface.h
>>>
>>
>
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