* [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines
@ 2020-05-07 13:41 Mika Kuoppala
2020-05-07 13:44 ` Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Mika Kuoppala @ 2020-05-07 13:41 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
All engines, exception being blitter as it does not
care about the form, can access compressed surfaces.
So we need to add forced aux table invalidates
for those engines.
v2: virtual instance masking (Chris)
References: d248b371f747 ("drm/i915/gen12: Invalidate aux table entries forcibly")
References bspec#43904, hsdes#1809175790
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chuansheng Liu <chuansheng.liu@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 84 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 6 +++
2 files changed, 85 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index bbdb0e2a4571..2fffedc99806 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4539,11 +4539,34 @@ static u32 preparser_disable(bool state)
return MI_ARB_CHECK | 1 << 8 | state;
}
+static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
+{
+ static const i915_reg_t vd[] = {
+ GEN12_VD0_AUX_NV,
+ GEN12_VD1_AUX_NV,
+ GEN12_VD2_AUX_NV,
+ GEN12_VD3_AUX_NV,
+ };
+
+ static const i915_reg_t ve[] = {
+ GEN12_VE0_AUX_NV,
+ GEN12_VE1_AUX_NV,
+ };
+
+ if (engine->class == VIDEO_DECODE_CLASS)
+ return vd[engine->instance];
+
+ if (engine->class == VIDEO_ENHANCEMENT_CLASS)
+ return ve[engine->instance];
+
+ return INVALID_MMIO_REG;
+}
+
static u32 *
-gen12_emit_aux_table_inv(struct i915_request *rq, u32 *cs)
+gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
{
*cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(GEN12_GFX_CCS_AUX_NV);
+ *cs++ = i915_mmio_reg_offset(inv_reg);
*cs++ = AUX_INV;
*cs++ = MI_NOOP;
@@ -4612,7 +4635,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
/* hsdes: 1809175790 */
- cs = gen12_emit_aux_table_inv(request, cs);
+ cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs);
*cs++ = preparser_disable(false);
intel_ring_advance(request, cs);
@@ -4621,6 +4644,56 @@ static int gen12_emit_flush_render(struct i915_request *request,
return 0;
}
+static int gen12_emit_flush(struct i915_request *request, u32 mode)
+{
+ intel_engine_mask_t aux_inv = 0;
+ u32 cmd, *cs;
+
+ if (mode & EMIT_INVALIDATE)
+ aux_inv = request->engine->mask & ~BIT(BCS0);
+
+ cs = intel_ring_begin(request,
+ 4 + (aux_inv ? 2 * hweight8(aux_inv) + 2 : 0));
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cmd = MI_FLUSH_DW + 1;
+
+ /* We always require a command barrier so that subsequent
+ * commands, such as breadcrumb interrupts, are strictly ordered
+ * wrt the contents of the write cache being flushed to memory
+ * (and thus being coherent from the CPU).
+ */
+ cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
+
+ if (mode & EMIT_INVALIDATE) {
+ cmd |= MI_INVALIDATE_TLB;
+ if (request->engine->class == VIDEO_DECODE_CLASS)
+ cmd |= MI_INVALIDATE_BSD;
+ }
+
+ *cs++ = cmd;
+ *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
+ *cs++ = 0; /* upper addr */
+ *cs++ = 0; /* value */
+
+ if (aux_inv) { /* hsdes: 1809175790 */
+ struct intel_engine_cs *engine;
+ unsigned int tmp;
+
+ *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
+ for_each_engine_masked(engine, request->engine->gt,
+ aux_inv, tmp) {
+ *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
+ *cs++ = AUX_INV;
+ }
+ *cs++ = MI_NOOP;
+ }
+ intel_ring_advance(request, cs);
+
+ return 0;
+}
+
/*
* Reserve space for 2 NOOPs at the end of each request to be
* used as a workaround for not being allowed to do lite
@@ -4854,9 +4927,10 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_flush = gen8_emit_flush;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb;
- if (INTEL_GEN(engine->i915) >= 12)
+ if (INTEL_GEN(engine->i915) >= 12) {
engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb;
-
+ engine->emit_flush = gen12_emit_flush;
+ }
engine->set_default_submission = intel_execlists_set_default_submission;
if (INTEL_GEN(engine->i915) < 11) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc5952200a07..6c076a24eb82 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2558,6 +2558,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
+#define GEN12_VD0_AUX_NV _MMIO(0x4218)
+#define GEN12_VD1_AUX_NV _MMIO(0x4228)
+#define GEN12_VD2_AUX_NV _MMIO(0x4298)
+#define GEN12_VD3_AUX_NV _MMIO(0x42A8)
+#define GEN12_VE0_AUX_NV _MMIO(0x4238)
+#define GEN12_VE1_AUX_NV _MMIO(0x42B8)
#define AUX_INV REG_BIT(0)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines
2020-05-07 13:41 [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines Mika Kuoppala
@ 2020-05-07 13:44 ` Chris Wilson
2020-05-07 14:20 ` Mika Kuoppala
2020-05-07 14:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen12: Add aux table invalidate for all engines (rev2) Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Chris Wilson @ 2020-05-07 13:44 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-05-07 14:41:22)
> All engines, exception being blitter as it does not
> care about the form, can access compressed surfaces.
>
> So we need to add forced aux table invalidates
> for those engines.
>
> v2: virtual instance masking (Chris)
>
> References: d248b371f747 ("drm/i915/gen12: Invalidate aux table entries forcibly")
> References bspec#43904, hsdes#1809175790
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Chuansheng Liu <chuansheng.liu@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 84 +++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 6 +++
> 2 files changed, 85 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index bbdb0e2a4571..2fffedc99806 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -4539,11 +4539,34 @@ static u32 preparser_disable(bool state)
> return MI_ARB_CHECK | 1 << 8 | state;
> }
>
> +static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
> +{
> + static const i915_reg_t vd[] = {
> + GEN12_VD0_AUX_NV,
> + GEN12_VD1_AUX_NV,
> + GEN12_VD2_AUX_NV,
> + GEN12_VD3_AUX_NV,
> + };
> +
> + static const i915_reg_t ve[] = {
> + GEN12_VE0_AUX_NV,
> + GEN12_VE1_AUX_NV,
> + };
> +
> + if (engine->class == VIDEO_DECODE_CLASS)
> + return vd[engine->instance];
> +
> + if (engine->class == VIDEO_ENHANCEMENT_CLASS)
> + return ve[engine->instance];
> +
GEM_BUG_ON("unknown aux_inv_reg");
> + return INVALID_MMIO_REG;
> +}
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines
2020-05-07 13:44 ` Chris Wilson
@ 2020-05-07 14:20 ` Mika Kuoppala
2020-05-07 16:22 ` Chris Wilson
2020-05-07 21:32 ` Daniele Ceraolo Spurio
0 siblings, 2 replies; 9+ messages in thread
From: Mika Kuoppala @ 2020-05-07 14:20 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
All engines, exception being blitter as it does not
care about the form, can access compressed surfaces.
So we need to add forced aux table invalidates
for those engines.
v2: virtual instance masking (Chris)
v3: bug on if not found (Chris)
References: d248b371f747 ("drm/i915/gen12: Invalidate aux table entries forcibly")
References bspec#43904, hsdes#1809175790
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chuansheng Liu <chuansheng.liu@intel.com>
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 86 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 6 ++
2 files changed, 87 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index bbdb0e2a4571..e12916e2799b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4539,11 +4539,36 @@ static u32 preparser_disable(bool state)
return MI_ARB_CHECK | 1 << 8 | state;
}
+static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
+{
+ static const i915_reg_t vd[] = {
+ GEN12_VD0_AUX_NV,
+ GEN12_VD1_AUX_NV,
+ GEN12_VD2_AUX_NV,
+ GEN12_VD3_AUX_NV,
+ };
+
+ static const i915_reg_t ve[] = {
+ GEN12_VE0_AUX_NV,
+ GEN12_VE1_AUX_NV,
+ };
+
+ if (engine->class == VIDEO_DECODE_CLASS)
+ return vd[engine->instance];
+
+ if (engine->class == VIDEO_ENHANCEMENT_CLASS)
+ return ve[engine->instance];
+
+ GEM_BUG_ON("unknown aux_inv_reg\n");
+
+ return INVALID_MMIO_REG;
+}
+
static u32 *
-gen12_emit_aux_table_inv(struct i915_request *rq, u32 *cs)
+gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
{
*cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(GEN12_GFX_CCS_AUX_NV);
+ *cs++ = i915_mmio_reg_offset(inv_reg);
*cs++ = AUX_INV;
*cs++ = MI_NOOP;
@@ -4612,7 +4637,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
/* hsdes: 1809175790 */
- cs = gen12_emit_aux_table_inv(request, cs);
+ cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs);
*cs++ = preparser_disable(false);
intel_ring_advance(request, cs);
@@ -4621,6 +4646,56 @@ static int gen12_emit_flush_render(struct i915_request *request,
return 0;
}
+static int gen12_emit_flush(struct i915_request *request, u32 mode)
+{
+ intel_engine_mask_t aux_inv = 0;
+ u32 cmd, *cs;
+
+ if (mode & EMIT_INVALIDATE)
+ aux_inv = request->engine->mask & ~BIT(BCS0);
+
+ cs = intel_ring_begin(request,
+ 4 + (aux_inv ? 2 * hweight8(aux_inv) + 2 : 0));
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cmd = MI_FLUSH_DW + 1;
+
+ /* We always require a command barrier so that subsequent
+ * commands, such as breadcrumb interrupts, are strictly ordered
+ * wrt the contents of the write cache being flushed to memory
+ * (and thus being coherent from the CPU).
+ */
+ cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
+
+ if (mode & EMIT_INVALIDATE) {
+ cmd |= MI_INVALIDATE_TLB;
+ if (request->engine->class == VIDEO_DECODE_CLASS)
+ cmd |= MI_INVALIDATE_BSD;
+ }
+
+ *cs++ = cmd;
+ *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
+ *cs++ = 0; /* upper addr */
+ *cs++ = 0; /* value */
+
+ if (aux_inv) { /* hsdes: 1809175790 */
+ struct intel_engine_cs *engine;
+ unsigned int tmp;
+
+ *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
+ for_each_engine_masked(engine, request->engine->gt,
+ aux_inv, tmp) {
+ *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
+ *cs++ = AUX_INV;
+ }
+ *cs++ = MI_NOOP;
+ }
+ intel_ring_advance(request, cs);
+
+ return 0;
+}
+
/*
* Reserve space for 2 NOOPs at the end of each request to be
* used as a workaround for not being allowed to do lite
@@ -4854,9 +4929,10 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_flush = gen8_emit_flush;
engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb;
- if (INTEL_GEN(engine->i915) >= 12)
+ if (INTEL_GEN(engine->i915) >= 12) {
engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb;
-
+ engine->emit_flush = gen12_emit_flush;
+ }
engine->set_default_submission = intel_execlists_set_default_submission;
if (INTEL_GEN(engine->i915) < 11) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dc5952200a07..6c076a24eb82 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2558,6 +2558,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
#define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
#define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
+#define GEN12_VD0_AUX_NV _MMIO(0x4218)
+#define GEN12_VD1_AUX_NV _MMIO(0x4228)
+#define GEN12_VD2_AUX_NV _MMIO(0x4298)
+#define GEN12_VD3_AUX_NV _MMIO(0x42A8)
+#define GEN12_VE0_AUX_NV _MMIO(0x4238)
+#define GEN12_VE1_AUX_NV _MMIO(0x42B8)
#define AUX_INV REG_BIT(0)
#define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
#define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen12: Add aux table invalidate for all engines (rev2)
2020-05-07 13:41 [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines Mika Kuoppala
2020-05-07 13:44 ` Chris Wilson
@ 2020-05-07 14:44 ` Patchwork
2020-05-07 15:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-07 18:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-05-07 14:44 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen12: Add aux table invalidate for all engines (rev2)
URL : https://patchwork.freedesktop.org/series/77038/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e20a34365bd6 drm/i915/gen12: Add aux table invalidate for all engines
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#15:
References: d248b371f747 ("drm/i915/gen12: Invalidate aux table entries forcibly")
-:15: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit d248b371f747 ("drm/i915/gen12: Invalidate aux table entries forcibly")'
#15:
References: d248b371f747 ("drm/i915/gen12: Invalidate aux table entries forcibly")
-:50: WARNING:EMBEDDED_FUNCTION_NAME: Prefer using '"%s...", __func__' to using 'aux_inv_reg', this function's name, in a string
#50: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:4562:
+ GEM_BUG_ON("unknown aux_inv_reg\n");
total: 1 errors, 2 warnings, 0 checks, 126 lines checked
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gen12: Add aux table invalidate for all engines (rev2)
2020-05-07 13:41 [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines Mika Kuoppala
2020-05-07 13:44 ` Chris Wilson
2020-05-07 14:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen12: Add aux table invalidate for all engines (rev2) Patchwork
@ 2020-05-07 15:08 ` Patchwork
2020-05-07 18:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-05-07 15:08 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen12: Add aux table invalidate for all engines (rev2)
URL : https://patchwork.freedesktop.org/series/77038/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8444 -> Patchwork_17601
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/index.html
Known issues
------------
Here are the changes found in Patchwork_17601 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_pm_rpm@basic-rte:
- fi-hsw-4770: [SKIP][1] ([fdo#109271]) -> [PASS][2] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/fi-hsw-4770/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6700k2: [INCOMPLETE][3] ([i915#151]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/fi-skl-6700k2/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@reset:
- fi-bwr-2160: [INCOMPLETE][5] ([i915#489]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/fi-bwr-2160/igt@i915_selftest@live@reset.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/fi-bwr-2160/igt@i915_selftest@live@reset.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
Participating hosts (49 -> 42)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8444 -> Patchwork_17601
CI-20190529: 20190529
CI_DRM_8444: 39544482386ac801dc4140df00a7e7e5bbea4d8a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5638: 50868ab3c532a86aa147fb555b69a1078c572b13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17601: e20a34365bd65217187425abcc1fbba0528a8003 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e20a34365bd6 drm/i915/gen12: Add aux table invalidate for all engines
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines
2020-05-07 14:20 ` Mika Kuoppala
@ 2020-05-07 16:22 ` Chris Wilson
2020-05-07 21:32 ` Daniele Ceraolo Spurio
1 sibling, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2020-05-07 16:22 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-05-07 15:20:45)
> All engines, exception being blitter as it does not
> care about the form, can access compressed surfaces.
>
> So we need to add forced aux table invalidates
> for those engines.
>
> v2: virtual instance masking (Chris)
> v3: bug on if not found (Chris)
>
> References: d248b371f747 ("drm/i915/gen12: Invalidate aux table entries forcibly")
> References bspec#43904, hsdes#1809175790
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Chuansheng Liu <chuansheng.liu@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
The code handles the more complicated vengs without exploding, so looks
good. But I still think is a w/a and only deserves an ack as something
that empirically works [although we have a lack of evidence situation
here :],
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gen12: Add aux table invalidate for all engines (rev2)
2020-05-07 13:41 [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines Mika Kuoppala
` (2 preceding siblings ...)
2020-05-07 15:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-05-07 18:15 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-05-07 18:15 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen12: Add aux table invalidate for all engines (rev2)
URL : https://patchwork.freedesktop.org/series/77038/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8444_full -> Patchwork_17601_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17601_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17601_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17601_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ctx_persistence@engines-queued@vcs1:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-tglb6/igt@gem_ctx_persistence@engines-queued@vcs1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-tglb2/igt@gem_ctx_persistence@engines-queued@vcs1.html
* igt@gem_exec_balancer@bonded-slice:
- shard-kbl: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl7/igt@gem_exec_balancer@bonded-slice.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-kbl1/igt@gem_exec_balancer@bonded-slice.html
* igt@runner@aborted:
- shard-kbl: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-kbl1/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_flip@dpms-vs-vblank-race@c-hdmi-a1}:
- shard-glk: [PASS][6] -> [FAIL][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-glk8/igt@kms_flip@dpms-vs-vblank-race@c-hdmi-a1.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-glk5/igt@kms_flip@dpms-vs-vblank-race@c-hdmi-a1.html
Known issues
------------
Here are the changes found in Patchwork_17601_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#180]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl3/igt@gem_workarounds@suspend-resume-fd.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_color@pipe-a-ctm-green-to-red:
- shard-skl: [PASS][10] -> [FAIL][11] ([i915#129])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-skl5/igt@kms_color@pipe-a-ctm-green-to-red.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-skl7/igt@kms_color@pipe-a-ctm-green-to-red.html
* igt@kms_cursor_legacy@all-pipes-torture-bo:
- shard-tglb: [PASS][12] -> [DMESG-WARN][13] ([i915#128])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-tglb7/igt@kms_cursor_legacy@all-pipes-torture-bo.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-tglb8/igt@kms_cursor_legacy@all-pipes-torture-bo.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#49])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-glk1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-glk6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][16] -> [FAIL][17] ([i915#1188])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][18] -> [FAIL][19] ([fdo#108145] / [i915#265])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109441]) +4 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-iclb6/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][22] -> [FAIL][23] ([i915#31])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-apl7/igt@kms_setmode@basic.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-apl1/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][24] ([i915#180]) -> [PASS][25] +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][26] ([i915#72]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-glk6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@pipe-c-torture-bo:
- shard-hsw: [DMESG-WARN][28] ([i915#128]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-hsw5/igt@kms_cursor_legacy@pipe-c-torture-bo.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-hsw6/igt@kms_cursor_legacy@pipe-c-torture-bo.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][30] ([fdo#109349]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb3/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled:
- shard-kbl: [FAIL][32] ([i915#177] / [i915#52] / [i915#54] / [i915#93] / [i915#95]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl7/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-kbl7/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-untiled.html
* {igt@kms_flip@flip-vs-rmfb-interruptible@c-vga1}:
- shard-hsw: [INCOMPLETE][34] ([i915#61]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-hsw4/igt@kms_flip@flip-vs-rmfb-interruptible@c-vga1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-hsw1/igt@kms_flip@flip-vs-rmfb-interruptible@c-vga1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][36] ([i915#1188]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-skl1/igt@kms_hdr@bpc-switch.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-skl3/igt@kms_hdr@bpc-switch.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][38] ([fdo#109642] / [fdo#111068]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb3/igt@kms_psr2_su@frontbuffer.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][40] ([fdo#109441]) -> [PASS][41] +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb3/igt@kms_psr@psr2_cursor_blt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_setmode@basic:
- shard-hsw: [FAIL][42] ([i915#31]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-hsw1/igt@kms_setmode@basic.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-hsw7/igt@kms_setmode@basic.html
- shard-kbl: [FAIL][44] ([i915#31]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl4/igt@kms_setmode@basic.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-kbl2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][46] ([i915#180]) -> [PASS][47] +4 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
- shard-skl: [INCOMPLETE][48] ([i915#69]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-skl4/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-skl5/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
* {igt@perf@blocking-parameterized}:
- shard-hsw: [FAIL][50] ([i915#1542]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-hsw6/igt@perf@blocking-parameterized.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-hsw4/igt@perf@blocking-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][52] ([i915#658]) -> [SKIP][53] ([i915#588])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-snb: [SKIP][54] ([fdo#109271]) -> [INCOMPLETE][55] ([i915#82])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-snb6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-snb2/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@kms_content_protection@atomic:
- shard-apl: [FAIL][56] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][57] ([i915#1319])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-apl4/igt@kms_content_protection@atomic.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-apl8/igt@kms_content_protection@atomic.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][58] ([i915#180]) -> [INCOMPLETE][59] ([i915#155] / [i915#794])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8444/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/shard-kbl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
[i915#129]: https://gitlab.freedesktop.org/drm/intel/issues/129
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8444 -> Patchwork_17601
CI-20190529: 20190529
CI_DRM_8444: 39544482386ac801dc4140df00a7e7e5bbea4d8a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5638: 50868ab3c532a86aa147fb555b69a1078c572b13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17601: e20a34365bd65217187425abcc1fbba0528a8003 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17601/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines
2020-05-07 14:20 ` Mika Kuoppala
2020-05-07 16:22 ` Chris Wilson
@ 2020-05-07 21:32 ` Daniele Ceraolo Spurio
2020-05-12 14:22 ` Mika Kuoppala
1 sibling, 1 reply; 9+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-05-07 21:32 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx; +Cc: Chris Wilson
On 5/7/20 7:20 AM, Mika Kuoppala wrote:
> All engines, exception being blitter as it does not
> care about the form, can access compressed surfaces.
>
> So we need to add forced aux table invalidates
> for those engines.
>
> v2: virtual instance masking (Chris)
> v3: bug on if not found (Chris)
>
> References: d248b371f747 ("drm/i915/gen12: Invalidate aux table entries forcibly")
> References bspec#43904, hsdes#1809175790
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Chuansheng Liu <chuansheng.liu@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 86 +++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 6 ++
> 2 files changed, 87 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index bbdb0e2a4571..e12916e2799b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -4539,11 +4539,36 @@ static u32 preparser_disable(bool state)
> return MI_ARB_CHECK | 1 << 8 | state;
> }
>
> +static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
> +{
> + static const i915_reg_t vd[] = {
> + GEN12_VD0_AUX_NV,
> + GEN12_VD1_AUX_NV,
> + GEN12_VD2_AUX_NV,
> + GEN12_VD3_AUX_NV,
> + };
> +
> + static const i915_reg_t ve[] = {
> + GEN12_VE0_AUX_NV,
> + GEN12_VE1_AUX_NV,
> + };
> +
> + if (engine->class == VIDEO_DECODE_CLASS)
> + return vd[engine->instance];
> +
> + if (engine->class == VIDEO_ENHANCEMENT_CLASS)
> + return ve[engine->instance];
> +
> + GEM_BUG_ON("unknown aux_inv_reg\n");
> +
> + return INVALID_MMIO_REG;
> +}
> +
> static u32 *
> -gen12_emit_aux_table_inv(struct i915_request *rq, u32 *cs)
> +gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
> {
> *cs++ = MI_LOAD_REGISTER_IMM(1);
> - *cs++ = i915_mmio_reg_offset(GEN12_GFX_CCS_AUX_NV);
> + *cs++ = i915_mmio_reg_offset(inv_reg);
> *cs++ = AUX_INV;
> *cs++ = MI_NOOP;
>
> @@ -4612,7 +4637,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
> cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
>
> /* hsdes: 1809175790 */
> - cs = gen12_emit_aux_table_inv(request, cs);
> + cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs);
>
> *cs++ = preparser_disable(false);
> intel_ring_advance(request, cs);
> @@ -4621,6 +4646,56 @@ static int gen12_emit_flush_render(struct i915_request *request,
> return 0;
> }
>
> +static int gen12_emit_flush(struct i915_request *request, u32 mode)
> +{
> + intel_engine_mask_t aux_inv = 0;
> + u32 cmd, *cs;
> +
> + if (mode & EMIT_INVALIDATE)
> + aux_inv = request->engine->mask & ~BIT(BCS0);
> +
> + cs = intel_ring_begin(request,
> + 4 + (aux_inv ? 2 * hweight8(aux_inv) + 2 : 0));
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + cmd = MI_FLUSH_DW + 1;
> +
> + /* We always require a command barrier so that subsequent
> + * commands, such as breadcrumb interrupts, are strictly ordered
> + * wrt the contents of the write cache being flushed to memory
> + * (and thus being coherent from the CPU).
> + */
> + cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
> +
> + if (mode & EMIT_INVALIDATE) {
> + cmd |= MI_INVALIDATE_TLB;
> + if (request->engine->class == VIDEO_DECODE_CLASS)
> + cmd |= MI_INVALIDATE_BSD;
> + }
> +
> + *cs++ = cmd;
> + *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
> + *cs++ = 0; /* upper addr */
> + *cs++ = 0; /* value */
> +
> + if (aux_inv) { /* hsdes: 1809175790 */
> + struct intel_engine_cs *engine;
> + unsigned int tmp;
> +
> + *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
> + for_each_engine_masked(engine, request->engine->gt,
> + aux_inv, tmp) {
> + *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
> + *cs++ = AUX_INV;
Why do we loop through all engines? AFAICS the WA just says to
invalidate the current one. If it is because we don't know what we're
running on, can't we just use the automatic mmio remap on the CS? That
was added on purpose for per-engine registers that are not relative to
the mmio base (see bspec 45606)
Daniele
> + }
> + *cs++ = MI_NOOP;
> + }
> + intel_ring_advance(request, cs);
> +
> + return 0;
> +}
> +
> /*
> * Reserve space for 2 NOOPs at the end of each request to be
> * used as a workaround for not being allowed to do lite
> @@ -4854,9 +4929,10 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
> engine->emit_flush = gen8_emit_flush;
> engine->emit_init_breadcrumb = gen8_emit_init_breadcrumb;
> engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb;
> - if (INTEL_GEN(engine->i915) >= 12)
> + if (INTEL_GEN(engine->i915) >= 12) {
> engine->emit_fini_breadcrumb = gen12_emit_fini_breadcrumb;
> -
> + engine->emit_flush = gen12_emit_flush;
> + }
> engine->set_default_submission = intel_execlists_set_default_submission;
>
> if (INTEL_GEN(engine->i915) < 11) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dc5952200a07..6c076a24eb82 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2558,6 +2558,12 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
> #define BSD_HWS_PGA_GEN7 _MMIO(0x04180)
> #define GEN12_GFX_CCS_AUX_NV _MMIO(0x4208)
> +#define GEN12_VD0_AUX_NV _MMIO(0x4218)
> +#define GEN12_VD1_AUX_NV _MMIO(0x4228)
> +#define GEN12_VD2_AUX_NV _MMIO(0x4298)
> +#define GEN12_VD3_AUX_NV _MMIO(0x42A8)
> +#define GEN12_VE0_AUX_NV _MMIO(0x4238)
> +#define GEN12_VE1_AUX_NV _MMIO(0x42B8)
> #define AUX_INV REG_BIT(0)
> #define BLT_HWS_PGA_GEN7 _MMIO(0x04280)
> #define VEBOX_HWS_PGA_GEN7 _MMIO(0x04380)
>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines
2020-05-07 21:32 ` Daniele Ceraolo Spurio
@ 2020-05-12 14:22 ` Mika Kuoppala
0 siblings, 0 replies; 9+ messages in thread
From: Mika Kuoppala @ 2020-05-12 14:22 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx; +Cc: Chris Wilson
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> writes:
> On 5/7/20 7:20 AM, Mika Kuoppala wrote:
>> All engines, exception being blitter as it does not
>> care about the form, can access compressed surfaces.
>>
>> So we need to add forced aux table invalidates
>> for those engines.
>>
>> v2: virtual instance masking (Chris)
>> v3: bug on if not found (Chris)
>>
>> References: d248b371f747 ("drm/i915/gen12: Invalidate aux table entries forcibly")
>> References bspec#43904, hsdes#1809175790
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Chuansheng Liu <chuansheng.liu@intel.com>
>> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_lrc.c | 86 +++++++++++++++++++++++++++--
>> drivers/gpu/drm/i915/i915_reg.h | 6 ++
>> 2 files changed, 87 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index bbdb0e2a4571..e12916e2799b 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -4539,11 +4539,36 @@ static u32 preparser_disable(bool state)
>> return MI_ARB_CHECK | 1 << 8 | state;
>> }
>>
>> +static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
>> +{
>> + static const i915_reg_t vd[] = {
>> + GEN12_VD0_AUX_NV,
>> + GEN12_VD1_AUX_NV,
>> + GEN12_VD2_AUX_NV,
>> + GEN12_VD3_AUX_NV,
>> + };
>> +
>> + static const i915_reg_t ve[] = {
>> + GEN12_VE0_AUX_NV,
>> + GEN12_VE1_AUX_NV,
>> + };
>> +
>> + if (engine->class == VIDEO_DECODE_CLASS)
>> + return vd[engine->instance];
>> +
>> + if (engine->class == VIDEO_ENHANCEMENT_CLASS)
>> + return ve[engine->instance];
>> +
>> + GEM_BUG_ON("unknown aux_inv_reg\n");
>> +
>> + return INVALID_MMIO_REG;
>> +}
>> +
>> static u32 *
>> -gen12_emit_aux_table_inv(struct i915_request *rq, u32 *cs)
>> +gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs)
>> {
>> *cs++ = MI_LOAD_REGISTER_IMM(1);
>> - *cs++ = i915_mmio_reg_offset(GEN12_GFX_CCS_AUX_NV);
>> + *cs++ = i915_mmio_reg_offset(inv_reg);
>> *cs++ = AUX_INV;
>> *cs++ = MI_NOOP;
>>
>> @@ -4612,7 +4637,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
>> cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
>>
>> /* hsdes: 1809175790 */
>> - cs = gen12_emit_aux_table_inv(request, cs);
>> + cs = gen12_emit_aux_table_inv(GEN12_GFX_CCS_AUX_NV, cs);
>>
>> *cs++ = preparser_disable(false);
>> intel_ring_advance(request, cs);
>> @@ -4621,6 +4646,56 @@ static int gen12_emit_flush_render(struct i915_request *request,
>> return 0;
>> }
>>
>> +static int gen12_emit_flush(struct i915_request *request, u32 mode)
>> +{
>> + intel_engine_mask_t aux_inv = 0;
>> + u32 cmd, *cs;
>> +
>> + if (mode & EMIT_INVALIDATE)
>> + aux_inv = request->engine->mask & ~BIT(BCS0);
>> +
>> + cs = intel_ring_begin(request,
>> + 4 + (aux_inv ? 2 * hweight8(aux_inv) + 2 : 0));
>> + if (IS_ERR(cs))
>> + return PTR_ERR(cs);
>> +
>> + cmd = MI_FLUSH_DW + 1;
>> +
>> + /* We always require a command barrier so that subsequent
>> + * commands, such as breadcrumb interrupts, are strictly ordered
>> + * wrt the contents of the write cache being flushed to memory
>> + * (and thus being coherent from the CPU).
>> + */
>> + cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
>> +
>> + if (mode & EMIT_INVALIDATE) {
>> + cmd |= MI_INVALIDATE_TLB;
>> + if (request->engine->class == VIDEO_DECODE_CLASS)
>> + cmd |= MI_INVALIDATE_BSD;
>> + }
>> +
>> + *cs++ = cmd;
>> + *cs++ = LRC_PPHWSP_SCRATCH_ADDR;
>> + *cs++ = 0; /* upper addr */
>> + *cs++ = 0; /* value */
>> +
>> + if (aux_inv) { /* hsdes: 1809175790 */
>> + struct intel_engine_cs *engine;
>> + unsigned int tmp;
>> +
>> + *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv));
>> + for_each_engine_masked(engine, request->engine->gt,
>> + aux_inv, tmp) {
>> + *cs++ = i915_mmio_reg_offset(aux_inv_reg(engine));
>> + *cs++ = AUX_INV;
>
> Why do we loop through all engines? AFAICS the WA just says to
> invalidate the current one. If it is because we don't know what we're
> running on, can't we just use the automatic mmio remap on the CS? That
> was added on purpose for per-engine registers that are not relative to
> the mmio base (see bspec 45606)
>
> Daniele
I looked at the auto remap feature and it should be doable
with that feature.
Now it will inv with all engine backing up a virtual one.
So there is a difference. But we do not have a bug on other
engines to require inv. So we play it safe.
We would need a media pipeline expert to ack/nack actually.
Thanks for the remap io pointer,
-Mika
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-05-12 14:24 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-07 13:41 [Intel-gfx] [PATCH] drm/i915/gen12: Add aux table invalidate for all engines Mika Kuoppala
2020-05-07 13:44 ` Chris Wilson
2020-05-07 14:20 ` Mika Kuoppala
2020-05-07 16:22 ` Chris Wilson
2020-05-07 21:32 ` Daniele Ceraolo Spurio
2020-05-12 14:22 ` Mika Kuoppala
2020-05-07 14:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/gen12: Add aux table invalidate for all engines (rev2) Patchwork
2020-05-07 15:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-07 18:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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