* [PATCH] pinctrl: Add mux options 3 and 4 for rockchip pinctrl
@ 2014-08-08 22:29 ` Doug Anderson
0 siblings, 0 replies; 7+ messages in thread
From: Doug Anderson @ 2014-08-08 22:29 UTC (permalink / raw)
To: Linus Walleij, Heiko Stuebner
Cc: linux-arm-kernel, Sonny Rao, eddie.cai, Doug Anderson, robh+dt,
pawel.moll, mark.rutland, ijc+devicetree, galak, devicetree,
linux-kernel
Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since
the rk3288 table goes all the way up to 4.
Signed-off-by: Doug Anderson <dianders@chromium.org>
---
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 6 +++---
include/dt-bindings/pinctrl/rockchip.h | 2 ++
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 4658b69..388b213 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -2,8 +2,8 @@
The Rockchip Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
-multiplexing the PAD input/output signals. For each PAD there are up to
-4 muxing options with option 0 being the use as a GPIO.
+multiplexing the PAD input/output signals. For each PAD there are several
+muxing options with option 0 being the use as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
@@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes:
Required properties for pin configuration node:
- rockchip,pins: 3 integers array, represents a group of pins mux and config
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
- The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
+ The MUX 0 means gpio and MUX 1 to N mean the specific device function.
The phandle of a node containing the generic pinconfig options
to use, as described in pinctrl-bindings.txt in this directory.
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
index cd5788b..743e66a 100644
--- a/include/dt-bindings/pinctrl/rockchip.h
+++ b/include/dt-bindings/pinctrl/rockchip.h
@@ -28,5 +28,7 @@
#define RK_FUNC_GPIO 0
#define RK_FUNC_1 1
#define RK_FUNC_2 2
+#define RK_FUNC_3 3
+#define RK_FUNC_4 4
#endif
--
2.0.0.526.g5318336
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH] pinctrl: Add mux options 3 and 4 for rockchip pinctrl
@ 2014-08-08 22:29 ` Doug Anderson
0 siblings, 0 replies; 7+ messages in thread
From: Doug Anderson @ 2014-08-08 22:29 UTC (permalink / raw)
To: linux-arm-kernel
Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since
the rk3288 table goes all the way up to 4.
Signed-off-by: Doug Anderson <dianders@chromium.org>
---
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 6 +++---
include/dt-bindings/pinctrl/rockchip.h | 2 ++
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 4658b69..388b213 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -2,8 +2,8 @@
The Rockchip Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
-multiplexing the PAD input/output signals. For each PAD there are up to
-4 muxing options with option 0 being the use as a GPIO.
+multiplexing the PAD input/output signals. For each PAD there are several
+muxing options with option 0 being the use as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
@@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes:
Required properties for pin configuration node:
- rockchip,pins: 3 integers array, represents a group of pins mux and config
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
- The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
+ The MUX 0 means gpio and MUX 1 to N mean the specific device function.
The phandle of a node containing the generic pinconfig options
to use, as described in pinctrl-bindings.txt in this directory.
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
index cd5788b..743e66a 100644
--- a/include/dt-bindings/pinctrl/rockchip.h
+++ b/include/dt-bindings/pinctrl/rockchip.h
@@ -28,5 +28,7 @@
#define RK_FUNC_GPIO 0
#define RK_FUNC_1 1
#define RK_FUNC_2 2
+#define RK_FUNC_3 3
+#define RK_FUNC_4 4
#endif
--
2.0.0.526.g5318336
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] pinctrl: Add mux options 3 and 4 for rockchip pinctrl
2014-08-08 22:29 ` Doug Anderson
@ 2014-08-09 15:34 ` Heiko Stübner
-1 siblings, 0 replies; 7+ messages in thread
From: Heiko Stübner @ 2014-08-09 15:34 UTC (permalink / raw)
To: Doug Anderson, Linus Walleij
Cc: linux-arm-kernel, Sonny Rao, eddie.cai, robh+dt, pawel.moll,
mark.rutland, ijc+devicetree, galak, devicetree, linux-kernel
Am Freitag, 8. August 2014, 15:29:09 schrieb Doug Anderson:
> Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since
> the rk3288 table goes all the way up to 4.
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
> Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 6 +++---
> include/dt-bindings/pinctrl/rockchip.h | 2 ++
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index
> 4658b69..388b213 100644
> --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
> @@ -2,8 +2,8 @@
>
> The Rockchip Pinmux Controller, enables the IC
> to share one PAD to several functional blocks. The sharing is done by
> -multiplexing the PAD input/output signals. For each PAD there are up to
> -4 muxing options with option 0 being the use as a GPIO.
> +multiplexing the PAD input/output signals. For each PAD there are several
> +muxing options with option 0 being the use as a GPIO.
>
> Please refer to pinctrl-bindings.txt in this directory for details of the
> common pinctrl bindings used by client devices, including the meaning of
> the @@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes:
> Required properties for pin configuration node:
> - rockchip,pins: 3 integers array, represents a group of pins mux and
> config setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX
> &phandle>. - The MUX 0 means gpio and MUX 1 to 3 mean the specific
> device function. + The MUX 0 means gpio and MUX 1 to N mean the specific
> device function. The phandle of a node containing the generic pinconfig
> options to use, as described in pinctrl-bindings.txt in this directory.
>
> diff --git a/include/dt-bindings/pinctrl/rockchip.h
> b/include/dt-bindings/pinctrl/rockchip.h index cd5788b..743e66a 100644
> --- a/include/dt-bindings/pinctrl/rockchip.h
> +++ b/include/dt-bindings/pinctrl/rockchip.h
> @@ -28,5 +28,7 @@
> #define RK_FUNC_GPIO 0
> #define RK_FUNC_1 1
> #define RK_FUNC_2 2
> +#define RK_FUNC_3 3
> +#define RK_FUNC_4 4
>
> #endif
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] pinctrl: Add mux options 3 and 4 for rockchip pinctrl
@ 2014-08-09 15:34 ` Heiko Stübner
0 siblings, 0 replies; 7+ messages in thread
From: Heiko Stübner @ 2014-08-09 15:34 UTC (permalink / raw)
To: linux-arm-kernel
Am Freitag, 8. August 2014, 15:29:09 schrieb Doug Anderson:
> Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since
> the rk3288 table goes all the way up to 4.
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> ---
> Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 6 +++---
> include/dt-bindings/pinctrl/rockchip.h | 2 ++
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
> b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index
> 4658b69..388b213 100644
> --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
> @@ -2,8 +2,8 @@
>
> The Rockchip Pinmux Controller, enables the IC
> to share one PAD to several functional blocks. The sharing is done by
> -multiplexing the PAD input/output signals. For each PAD there are up to
> -4 muxing options with option 0 being the use as a GPIO.
> +multiplexing the PAD input/output signals. For each PAD there are several
> +muxing options with option 0 being the use as a GPIO.
>
> Please refer to pinctrl-bindings.txt in this directory for details of the
> common pinctrl bindings used by client devices, including the meaning of
> the @@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes:
> Required properties for pin configuration node:
> - rockchip,pins: 3 integers array, represents a group of pins mux and
> config setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX
> &phandle>. - The MUX 0 means gpio and MUX 1 to 3 mean the specific
> device function. + The MUX 0 means gpio and MUX 1 to N mean the specific
> device function. The phandle of a node containing the generic pinconfig
> options to use, as described in pinctrl-bindings.txt in this directory.
>
> diff --git a/include/dt-bindings/pinctrl/rockchip.h
> b/include/dt-bindings/pinctrl/rockchip.h index cd5788b..743e66a 100644
> --- a/include/dt-bindings/pinctrl/rockchip.h
> +++ b/include/dt-bindings/pinctrl/rockchip.h
> @@ -28,5 +28,7 @@
> #define RK_FUNC_GPIO 0
> #define RK_FUNC_1 1
> #define RK_FUNC_2 2
> +#define RK_FUNC_3 3
> +#define RK_FUNC_4 4
>
> #endif
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] pinctrl: Add mux options 3 and 4 for rockchip pinctrl
@ 2014-08-28 13:19 ` Linus Walleij
0 siblings, 0 replies; 7+ messages in thread
From: Linus Walleij @ 2014-08-28 13:19 UTC (permalink / raw)
To: Doug Anderson
Cc: Heiko Stuebner, linux-arm-kernel, Sonny Rao, eddie.cai,
Rob Herring, Pawel Moll, Mark Rutland, ijc+devicetree,
Kumar Gala, devicetree, linux-kernel
On Sat, Aug 9, 2014 at 12:29 AM, Doug Anderson <dianders@chromium.org> wrote:
> Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since
> the rk3288 table goes all the way up to 4.
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
Patch applied with Heiko's review tag.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] pinctrl: Add mux options 3 and 4 for rockchip pinctrl
@ 2014-08-28 13:19 ` Linus Walleij
0 siblings, 0 replies; 7+ messages in thread
From: Linus Walleij @ 2014-08-28 13:19 UTC (permalink / raw)
To: Doug Anderson
Cc: Heiko Stuebner,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sonny Rao,
eddie.cai-TNX95d0MmH7DzftRWevZcw, Rob Herring, Pawel Moll,
Mark Rutland, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Sat, Aug 9, 2014 at 12:29 AM, Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> wrote:
> Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since
> the rk3288 table goes all the way up to 4.
>
> Signed-off-by: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Patch applied with Heiko's review tag.
Yours,
Linus Walleij
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH] pinctrl: Add mux options 3 and 4 for rockchip pinctrl
@ 2014-08-28 13:19 ` Linus Walleij
0 siblings, 0 replies; 7+ messages in thread
From: Linus Walleij @ 2014-08-28 13:19 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Aug 9, 2014 at 12:29 AM, Doug Anderson <dianders@chromium.org> wrote:
> Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since
> the rk3288 table goes all the way up to 4.
>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
Patch applied with Heiko's review tag.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2014-08-28 13:19 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2014-08-08 22:29 [PATCH] pinctrl: Add mux options 3 and 4 for rockchip pinctrl Doug Anderson
2014-08-08 22:29 ` Doug Anderson
2014-08-09 15:34 ` Heiko Stübner
2014-08-09 15:34 ` Heiko Stübner
2014-08-28 13:19 ` Linus Walleij
2014-08-28 13:19 ` Linus Walleij
2014-08-28 13:19 ` Linus Walleij
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