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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-riscv] [Qemu-devel] [PULL] target/riscv: Convert to decodetree
Date: Wed, 13 Mar 2019 10:31:03 +0100	[thread overview]
Message-ID: <108e3974-e305-4a0b-69cf-92809ddc117c@mail.uni-paderborn.de> (raw)
In-Reply-To: <CAFEAcA_hZLO032+gPuoy6enJvssjiZBUtBaC_pG4BGUPR3F0kQ@mail.gmail.com>


On 3/12/19 7:31 PM, Peter Maydell wrote:
> On Tue, 12 Mar 2019 at 13:15, Palmer Dabbelt <palmer@sifive.com> wrote:
>> The following changes since commit 377b155bde451d5ac545fbdcdfbf6ca17a4228f5:
>>
>>    Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-03-11 18:26:37 +0000)
>>
>> are available in the Git repository at:
>>
>>    git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf3
>>
>> for you to fetch changes up to a971f8ae0e8ab6fab1eee199961b1ea2f4d876f7:
>>
>>    target/riscv: Remove decode_RV32_64G() (2019-03-12 03:08:34 -0700)
>>
>> ----------------------------------------------------------------
>> target/riscv: Convert to decodetree
>
> I'm still seeing some errors about redefining typedefs, I'm afraid:
>
> target/riscv/decode_insn16.inc.c:102:28: error: redefinition of
> typedef 'arg_c_addi16sp_lui' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:122:17: error: redefinition of
> typedef 'arg_c_j' is a C11 feature [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:134:26: error: redefinition of
> typedef 'arg_c_flwsp_ldsp' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:144:26: error: redefinition of
> typedef 'arg_c_fswsp_sdsp' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:102:28: error: redefinition of
> typedef 'arg_c_addi16sp_lui' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:122:17: error: redefinition of
> typedef 'arg_c_j' is a C11 feature [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:134:26: error: redefinition of
> typedef 'arg_c_flwsp_ldsp' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:144:26: error: redefinition of
> typedef 'arg_c_fswsp_sdsp' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
>
> thanks
> -- PMM
>

Hi Peter,

this should fix it:

diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 0829e3bc59..1a461616aa 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -50,15 +50,15 @@
  &cs_dw     uimm   rs1 rs2
  &cb        imm    rs1
  &cr               rd  rs2
-&c_j       imm
+&cj       imm
  &c_shift   shamt      rd

  &c_ld      uimm  rd
  &c_sd      uimm  rs2

-&c_addi16sp_lui  imm_lui imm_addi16sp rd
-&c_flwsp_ldsp    uimm_flwsp uimm_ldsp rd
-&c_fswsp_sdsp    uimm_fswsp uimm_sdsp rs2
+&caddi16sp_lui  imm_lui imm_addi16sp rd
+&cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
+&cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2

  # Formats 16:
  @cr        ....  ..... .....  .. &cr rs2=%rs2_5  %rd
@@ -72,17 +72,17 @@
  @cs_d      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d rs1=%rs1_3  
rs2=%rs2_3
  @cs_w      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w rs1=%rs1_3  
rs2=%rs2_3
  @cb        ... ... ... .. ... .. &cb     imm=%imm_cb rs1=%rs1_3
-@cj        ...    ........... .. &c_j    imm=%imm_cj
+@cj        ...    ........... .. &cj    imm=%imm_cj

  @c_ld      ... . .....  ..... .. &c_ld uimm=%uimm_6bit_ld  %rd
  @c_lw      ... . .....  ..... .. &c_ld uimm=%uimm_6bit_lw  %rd
  @c_sd      ... . .....  ..... .. &c_sd uimm=%uimm_6bit_sd  rs2=%rs2_5
  @c_sw      ... . .....  ..... .. &c_sd uimm=%uimm_6bit_sw  rs2=%rs2_5

-@c_addi16sp_lui ... .  ..... ..... .. &c_addi16sp_lui %imm_lui 
%imm_addi16sp %rd
-@c_flwsp_ldsp   ... .  ..... ..... .. &c_flwsp_ldsp 
uimm_flwsp=%uimm_6bit_lw \
+@c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui 
%imm_addi16sp %rd
+@c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp 
uimm_flwsp=%uimm_6bit_lw \
      uimm_ldsp=%uimm_6bit_ld %rd
-@c_fswsp_sdsp   ... .  ..... ..... .. &c_fswsp_sdsp 
uimm_fswsp=%uimm_6bit_sw \
+@c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp 
uimm_fswsp=%uimm_6bit_sw \
      uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5

  @c_shift        ... . .. ... ..... .. &c_shift rd=%rs1_3 
shamt=%nzuimm_6bit


@Palmer: I send a fixed version of the offending patch.

Cheers,

Bastian





  reply	other threads:[~2019-03-13  9:44 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-12 13:14 [Qemu-riscv] [PULL] target/riscv: Convert to decodetree Palmer Dabbelt
2019-03-12 13:14 ` [Qemu-riscv] [PULL 01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC Palmer Dabbelt
2019-03-12 13:14 ` [Qemu-riscv] [PULL 02/29] target/riscv: Convert RVXI branch insns to decodetree Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 03/29] target/riscv: Convert RV32I load/store " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 04/29] target/riscv: Convert RV64I " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 05/29] target/riscv: Convert RVXI arithmetic " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 06/29] target/riscv: Convert RVXI fence " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 07/29] target/riscv: Convert RVXI csr " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 08/29] target/riscv: Convert RVXM " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 09/29] target/riscv: Convert RV32A " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 10/29] target/riscv: Convert RV64A " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 11/29] target/riscv: Convert RV32F " Palmer Dabbelt
2023-03-06 14:11   ` [Qemu-devel] " Philippe Mathieu-Daudé
2023-03-06 20:22     ` Richard Henderson
2019-03-12 13:15 ` [Qemu-riscv] [PULL 12/29] target/riscv: Convert RV64F " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 13/29] target/riscv: Convert RV32D " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 14/29] target/riscv: Convert RV64D " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 15/29] target/riscv: Convert RV priv " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 16/29] target/riscv: Convert quadrant 0 of RVXC " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 17/29] target/riscv: Convert quadrant 1 " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 18/29] target/riscv: Convert quadrant 2 " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 19/29] target/riscv: Remove gen_jalr() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 20/29] target/riscv: Remove manual decoding from gen_branch() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 21/29] target/riscv: Remove manual decoding from gen_load() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 22/29] target/riscv: Remove manual decoding from gen_store() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 25/29] target/riscv: Remove shift and slt insn manual decoding Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 26/29] target/riscv: Remove manual decoding of RV32/64M insn Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 27/29] target/riscv: Rename trans_arith to gen_arith Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 28/29] target/riscv: Remove gen_system() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 29/29] target/riscv: Remove decode_RV32_64G() Palmer Dabbelt
2019-03-12 18:31 ` [Qemu-riscv] [PULL] target/riscv: Convert to decodetree Peter Maydell
2019-03-13  9:31   ` Bastian Koppelmann [this message]
  -- strict thread matches above, loose matches on Subject: below --
2019-03-01 21:49 [Qemu-devel] " Palmer Dabbelt
2019-03-04 11:02 ` Peter Maydell
2019-03-04 12:52   ` [Qemu-riscv] " Bastian Koppelmann
2019-03-04 15:25     ` Bastian Koppelmann
2019-03-04 19:30     ` Richard Henderson
2019-03-04 21:46       ` Palmer Dabbelt

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