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From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org,       qemu-riscv@nongnu.org,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Peer Adelt <peer.adelt@hni.uni-paderborn.de>,
	 Palmer Dabbelt <palmer@sifive.com>
Subject: [Qemu-riscv] [PULL 15/29] target/riscv: Convert RV priv insns to decodetree
Date: Tue, 12 Mar 2019 06:15:12 -0700	[thread overview]
Message-ID: <20190312131526.14710-16-palmer@sifive.com> (raw)
In-Reply-To: <20190312131526.14710-1-palmer@sifive.com>

From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/insn32.decode                    |  15 +++
 .../riscv/insn_trans/trans_privileged.inc.c   | 110 ++++++++++++++++++
 target/riscv/translate.c                      |  57 +--------
 3 files changed, 126 insertions(+), 56 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e64b2b5e3458..ecc46a50cc27 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -57,6 +57,21 @@
 @r2_rm   .......   ..... ..... ... ..... ....... %rs1 %rm %rd
 @r2      .......   ..... ..... ... ..... ....... %rs1 %rd
 
+@sfence_vma ....... ..... .....   ... ..... ....... %rs2 %rs1
+@sfence_vm  ....... ..... .....   ... ..... ....... %rs1
+
+
+# *** Privileged Instructions ***
+ecall      000000000000     00000 000 00000 1110011
+ebreak     000000000001     00000 000 00000 1110011
+uret       0000000    00010 00000 000 00000 1110011
+sret       0001000    00010 00000 000 00000 1110011
+hret       0010000    00010 00000 000 00000 1110011
+mret       0011000    00010 00000 000 00000 1110011
+wfi        0001000    00101 00000 000 00000 1110011
+sfence_vma 0001001    ..... ..... 000 00000 1110011 @sfence_vma
+sfence_vm  0001000    00100 ..... 000 00000 1110011 @sfence_vm
+
 # *** RV32I Base Instruction Set ***
 lui      ....................       ..... 0110111 @u
 auipc    ....................       ..... 0010111 @u
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
new file mode 100644
index 000000000000..acb605923e68
--- /dev/null
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -0,0 +1,110 @@
+/*
+ * RISC-V translation routines for the RISC-V privileged instructions.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
+ *                    Bastian Koppelmann, kbastian@mail.uni-paderborn.de
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
+{
+    /* always generates U-level ECALL, fixed in do_interrupt handler */
+    generate_exception(ctx, RISCV_EXCP_U_ECALL);
+    tcg_gen_exit_tb(NULL, 0); /* no chaining */
+    ctx->base.is_jmp = DISAS_NORETURN;
+    return true;
+}
+
+static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
+{
+    generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
+    tcg_gen_exit_tb(NULL, 0); /* no chaining */
+    ctx->base.is_jmp = DISAS_NORETURN;
+    return true;
+}
+
+static bool trans_uret(DisasContext *ctx, arg_uret *a)
+{
+    return false;
+}
+
+static bool trans_sret(DisasContext *ctx, arg_sret *a)
+{
+#ifndef CONFIG_USER_ONLY
+    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+
+    if (has_ext(ctx, RVS)) {
+        gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
+        tcg_gen_exit_tb(NULL, 0); /* no chaining */
+        ctx->base.is_jmp = DISAS_NORETURN;
+    } else {
+        return false;
+    }
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_hret(DisasContext *ctx, arg_hret *a)
+{
+    return false;
+}
+
+static bool trans_mret(DisasContext *ctx, arg_mret *a)
+{
+#ifndef CONFIG_USER_ONLY
+    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
+    tcg_gen_exit_tb(NULL, 0); /* no chaining */
+    ctx->base.is_jmp = DISAS_NORETURN;
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
+{
+#ifndef CONFIG_USER_ONLY
+    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+    gen_helper_wfi(cpu_env);
+    return true;
+#else
+    return false;
+#endif
+}
+
+static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
+{
+#ifndef CONFIG_USER_ONLY
+    if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
+        gen_helper_tlb_flush(cpu_env);
+        return true;
+    }
+#endif
+    return false;
+}
+
+static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
+{
+#ifndef CONFIG_USER_ONLY
+    if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
+        gen_helper_tlb_flush(cpu_env);
+        return true;
+    }
+#endif
+    return false;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2e36deee82f4..02f64ed8a734 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -772,26 +772,8 @@ static void gen_set_rm(DisasContext *ctx, int rm)
 static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
                        int csr)
 {
-    TCGv source1, dest;
-    source1 = tcg_temp_new();
-    dest = tcg_temp_new();
-    gen_get_gpr(source1, rs1);
     tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
 
-#ifndef CONFIG_USER_ONLY
-    /* Extract funct7 value and check whether it matches SFENCE.VMA */
-    if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
-        if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
-            /* sfence.vma */
-            /* TODO: handle ASID specific fences */
-            gen_helper_tlb_flush(cpu_env);
-            return;
-        } else {
-            gen_exception_illegal(ctx);
-        }
-    }
-#endif
-
     switch (opc) {
     case OPC_RISC_ECALL:
         switch (csr) {
@@ -806,50 +788,12 @@ static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
             tcg_gen_exit_tb(NULL, 0); /* no chaining */
             ctx->base.is_jmp = DISAS_NORETURN;
             break;
-#ifndef CONFIG_USER_ONLY
-        case 0x002: /* URET */
-            gen_exception_illegal(ctx);
-            break;
-        case 0x102: /* SRET */
-            if (has_ext(ctx, RVS)) {
-                gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
-                tcg_gen_exit_tb(NULL, 0); /* no chaining */
-                ctx->base.is_jmp = DISAS_NORETURN;
-            } else {
-                gen_exception_illegal(ctx);
-            }
-            break;
-        case 0x202: /* HRET */
-            gen_exception_illegal(ctx);
-            break;
-        case 0x302: /* MRET */
-            gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
-            tcg_gen_exit_tb(NULL, 0); /* no chaining */
-            ctx->base.is_jmp = DISAS_NORETURN;
-            break;
-        case 0x7b2: /* DRET */
-            gen_exception_illegal(ctx);
-            break;
-        case 0x105: /* WFI */
-            tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
-            gen_helper_wfi(cpu_env);
-            break;
-        case 0x104: /* SFENCE.VM */
-            if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
-                gen_helper_tlb_flush(cpu_env);
-            } else {
-                gen_exception_illegal(ctx);
-            }
-            break;
-#endif
         default:
             gen_exception_illegal(ctx);
             break;
         }
         break;
     }
-    tcg_temp_free(source1);
-    tcg_temp_free(dest);
 }
 
 static void decode_RV32_64C0(DisasContext *ctx)
@@ -1152,6 +1096,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
 #include "insn_trans/trans_rva.inc.c"
 #include "insn_trans/trans_rvf.inc.c"
 #include "insn_trans/trans_rvd.inc.c"
+#include "insn_trans/trans_privileged.inc.c"
 
 static void decode_RV32_64G(DisasContext *ctx)
 {
-- 
2.19.2



  parent reply	other threads:[~2019-03-12 13:30 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-12 13:14 [Qemu-riscv] [PULL] target/riscv: Convert to decodetree Palmer Dabbelt
2019-03-12 13:14 ` [Qemu-riscv] [PULL 01/29] target/riscv: Activate decodetree and implemnt LUI & AUIPC Palmer Dabbelt
2019-03-12 13:14 ` [Qemu-riscv] [PULL 02/29] target/riscv: Convert RVXI branch insns to decodetree Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 03/29] target/riscv: Convert RV32I load/store " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 04/29] target/riscv: Convert RV64I " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 05/29] target/riscv: Convert RVXI arithmetic " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 06/29] target/riscv: Convert RVXI fence " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 07/29] target/riscv: Convert RVXI csr " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 08/29] target/riscv: Convert RVXM " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 09/29] target/riscv: Convert RV32A " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 10/29] target/riscv: Convert RV64A " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 11/29] target/riscv: Convert RV32F " Palmer Dabbelt
2023-03-06 14:11   ` [Qemu-devel] " Philippe Mathieu-Daudé
2023-03-06 20:22     ` Richard Henderson
2019-03-12 13:15 ` [Qemu-riscv] [PULL 12/29] target/riscv: Convert RV64F " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 13/29] target/riscv: Convert RV32D " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 14/29] target/riscv: Convert RV64D " Palmer Dabbelt
2019-03-12 13:15 ` Palmer Dabbelt [this message]
2019-03-12 13:15 ` [Qemu-riscv] [PULL 16/29] target/riscv: Convert quadrant 0 of RVXC " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 17/29] target/riscv: Convert quadrant 1 " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 18/29] target/riscv: Convert quadrant 2 " Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 19/29] target/riscv: Remove gen_jalr() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 20/29] target/riscv: Remove manual decoding from gen_branch() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 21/29] target/riscv: Remove manual decoding from gen_load() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 22/29] target/riscv: Remove manual decoding from gen_store() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 25/29] target/riscv: Remove shift and slt insn manual decoding Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 26/29] target/riscv: Remove manual decoding of RV32/64M insn Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 27/29] target/riscv: Rename trans_arith to gen_arith Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 28/29] target/riscv: Remove gen_system() Palmer Dabbelt
2019-03-12 13:15 ` [Qemu-riscv] [PULL 29/29] target/riscv: Remove decode_RV32_64G() Palmer Dabbelt
2019-03-12 18:31 ` [Qemu-riscv] [PULL] target/riscv: Convert to decodetree Peter Maydell
2019-03-13  9:31   ` [Qemu-riscv] [Qemu-devel] " Bastian Koppelmann
2019-03-13 14:36 [Qemu-riscv] " Palmer Dabbelt
2019-03-13 14:36 ` [Qemu-riscv] [PULL 15/29] target/riscv: Convert RV priv insns " Palmer Dabbelt

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