From: Vignesh Raghavendra <vigneshr@ti.com> To: <Tudor.Ambarus@microchip.com>, <boris.brezillon@collabora.com> Cc: <miquel.raynal@bootlin.com>, <richard@nod.at>, <linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org> Subject: Re: [PATCH v4 18/20] mtd: spi-nor: Rename macronix_quad_enable to spi_nor_sr1_bit6_quad_enable Date: Wed, 6 Nov 2019 11:30:10 +0530 [thread overview] Message-ID: <10b14e43-0f06-88fa-20b5-05f99cd93b6f@ti.com> (raw) In-Reply-To: <20191102112316.20715-19-tudor.ambarus@microchip.com> On 02/11/19 4:53 PM, Tudor.Ambarus@microchip.com wrote: > From: Tudor Ambarus <tudor.ambarus@microchip.com> > > Rename method to a generic name: spi_nor_sr1_bit6_quad_enable(). > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Regards Vignesh > --- > drivers/mtd/spi-nor/spi-nor.c | 19 +++++++++---------- > include/linux/mtd/spi-nor.h | 2 +- > 2 files changed, 10 insertions(+), 11 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 8bc29cc073a0..85e5a56fb2d7 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -2078,16 +2078,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) > } > > /** > - * macronix_quad_enable() - set QE bit in Status Register. > + * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status > + * Register 1. > * @nor: pointer to a 'struct spi_nor' > * > - * Set the Quad Enable (QE) bit in the Status Register. > - * > - * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. > + * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. > * > * Return: 0 on success, -errno otherwise. > */ > -static int macronix_quad_enable(struct spi_nor *nor) > +static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) > { > int ret; > > @@ -2095,10 +2094,10 @@ static int macronix_quad_enable(struct spi_nor *nor) > if (ret) > return ret; > > - if (nor->bouncebuf[0] & SR_QUAD_EN_MX) > + if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) > return 0; > > - nor->bouncebuf[0] |= SR_QUAD_EN_MX; > + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; > > return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); > } > @@ -2349,7 +2348,7 @@ static void gd25q256_default_init(struct spi_nor *nor) > * indicate the quad_enable method for this case, we need > * to set it in the default_init fixup hook. > */ > - nor->params.quad_enable = macronix_quad_enable; > + nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; > } > > static struct spi_nor_fixups gd25q256_fixups = { > @@ -3729,7 +3728,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, > > case BFPT_DWORD15_QER_SR1_BIT6: > nor->flags &= ~SNOR_F_HAS_16BIT_SR; > - params->quad_enable = macronix_quad_enable; > + params->quad_enable = spi_nor_sr1_bit6_quad_enable; > break; > > case BFPT_DWORD15_QER_SR2_BIT7: > @@ -4627,7 +4626,7 @@ static int spi_nor_setup(struct spi_nor *nor, > > static void macronix_set_default_init(struct spi_nor *nor) > { > - nor->params.quad_enable = macronix_quad_enable; > + nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; > nor->params.set_4byte = macronix_set_4byte; > } > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index f626e0e52909..6d703df97f13 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -133,7 +133,7 @@ > #define SR_E_ERR BIT(5) > #define SR_P_ERR BIT(6) > > -#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ > +#define SR1_QUAD_EN_BIT6 BIT(6) > > /* Enhanced Volatile Configuration Register bits */ > #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ > -- Regards Vignesh
WARNING: multiple messages have this Message-ID (diff)
From: Vignesh Raghavendra <vigneshr@ti.com> To: <Tudor.Ambarus@microchip.com>, <boris.brezillon@collabora.com> Cc: richard@nod.at, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, miquel.raynal@bootlin.com Subject: Re: [PATCH v4 18/20] mtd: spi-nor: Rename macronix_quad_enable to spi_nor_sr1_bit6_quad_enable Date: Wed, 6 Nov 2019 11:30:10 +0530 [thread overview] Message-ID: <10b14e43-0f06-88fa-20b5-05f99cd93b6f@ti.com> (raw) In-Reply-To: <20191102112316.20715-19-tudor.ambarus@microchip.com> On 02/11/19 4:53 PM, Tudor.Ambarus@microchip.com wrote: > From: Tudor Ambarus <tudor.ambarus@microchip.com> > > Rename method to a generic name: spi_nor_sr1_bit6_quad_enable(). > > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Regards Vignesh > --- > drivers/mtd/spi-nor/spi-nor.c | 19 +++++++++---------- > include/linux/mtd/spi-nor.h | 2 +- > 2 files changed, 10 insertions(+), 11 deletions(-) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index 8bc29cc073a0..85e5a56fb2d7 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -2078,16 +2078,15 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len) > } > > /** > - * macronix_quad_enable() - set QE bit in Status Register. > + * spi_nor_sr1_bit6_quad_enable() - Set the Quad Enable BIT(6) in the Status > + * Register 1. > * @nor: pointer to a 'struct spi_nor' > * > - * Set the Quad Enable (QE) bit in the Status Register. > - * > - * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. > + * Bit 6 of the Status Register 1 is the QE bit for Macronix like QSPI memories. > * > * Return: 0 on success, -errno otherwise. > */ > -static int macronix_quad_enable(struct spi_nor *nor) > +static int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor) > { > int ret; > > @@ -2095,10 +2094,10 @@ static int macronix_quad_enable(struct spi_nor *nor) > if (ret) > return ret; > > - if (nor->bouncebuf[0] & SR_QUAD_EN_MX) > + if (nor->bouncebuf[0] & SR1_QUAD_EN_BIT6) > return 0; > > - nor->bouncebuf[0] |= SR_QUAD_EN_MX; > + nor->bouncebuf[0] |= SR1_QUAD_EN_BIT6; > > return spi_nor_write_sr1_and_check(nor, nor->bouncebuf[0]); > } > @@ -2349,7 +2348,7 @@ static void gd25q256_default_init(struct spi_nor *nor) > * indicate the quad_enable method for this case, we need > * to set it in the default_init fixup hook. > */ > - nor->params.quad_enable = macronix_quad_enable; > + nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; > } > > static struct spi_nor_fixups gd25q256_fixups = { > @@ -3729,7 +3728,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, > > case BFPT_DWORD15_QER_SR1_BIT6: > nor->flags &= ~SNOR_F_HAS_16BIT_SR; > - params->quad_enable = macronix_quad_enable; > + params->quad_enable = spi_nor_sr1_bit6_quad_enable; > break; > > case BFPT_DWORD15_QER_SR2_BIT7: > @@ -4627,7 +4626,7 @@ static int spi_nor_setup(struct spi_nor *nor, > > static void macronix_set_default_init(struct spi_nor *nor) > { > - nor->params.quad_enable = macronix_quad_enable; > + nor->params.quad_enable = spi_nor_sr1_bit6_quad_enable; > nor->params.set_4byte = macronix_set_4byte; > } > > diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h > index f626e0e52909..6d703df97f13 100644 > --- a/include/linux/mtd/spi-nor.h > +++ b/include/linux/mtd/spi-nor.h > @@ -133,7 +133,7 @@ > #define SR_E_ERR BIT(5) > #define SR_P_ERR BIT(6) > > -#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */ > +#define SR1_QUAD_EN_BIT6 BIT(6) > > /* Enhanced Volatile Configuration Register bits */ > #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */ > -- Regards Vignesh ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2019-11-06 5:59 UTC|newest] Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-02 11:23 [PATCH v4 00/20] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-02 11:23 ` [PATCH v4 01/20] mtd: spi-nor: Use dev_dbg insted of dev_err for low level info Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-05 12:12 ` Vignesh Raghavendra 2019-11-05 12:12 ` Vignesh Raghavendra 2019-11-06 7:07 ` Tudor.Ambarus 2019-11-06 7:07 ` Tudor.Ambarus 2019-11-02 11:23 ` [PATCH v4 02/20] mtd: spi-nor: Print debug info inside Reg Ops methods Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-05 12:13 ` Vignesh Raghavendra 2019-11-05 12:13 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 03/20] mtd: spi-nor: Check for errors after each Register Operation Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-06 9:19 ` Vignesh Raghavendra 2019-11-06 9:19 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 04/20] mtd: spi-nor: Rename label as it is no longer generic Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-02 11:23 ` [PATCH v4 05/20] mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr() Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-02 11:23 ` [PATCH v4 06/20] mtd: spi-nor: Move the WE and wait calls inside Write SR methods Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-02 11:23 ` [PATCH v4 07/20] mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr() Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-02 11:23 ` [PATCH v4 08/20] mtd: spi-nor: Describe all the Reg Ops Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-05 12:21 ` Vignesh Raghavendra 2019-11-05 12:21 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 09/20] mtd: spi-nor: Drop spansion_quad_enable() Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-05 12:35 ` Vignesh Raghavendra 2019-11-05 12:35 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 10/20] mtd: spi-nor: Fix errno on Quad Enable methods Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-05 12:36 ` Vignesh Raghavendra 2019-11-05 12:36 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 11/20] mtd: spi-nor: Check all the bits written, not just the BP ones Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-05 12:21 ` Vignesh Raghavendra 2019-11-05 12:21 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 12/20] mtd: spi-nor: Print debug message when the read back test fails Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-05 12:37 ` Vignesh Raghavendra 2019-11-05 12:37 ` Vignesh Raghavendra 2019-11-06 7:24 ` Tudor.Ambarus 2019-11-06 7:24 ` Tudor.Ambarus 2019-11-06 7:39 ` Vignesh Raghavendra 2019-11-06 7:39 ` Vignesh Raghavendra 2019-11-07 5:58 ` Vignesh Raghavendra 2019-11-07 5:58 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 13/20] mtd: spi-nor: Fix clearing of QE bit on lock()/unlock() Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-05 17:07 ` Vignesh Raghavendra 2019-11-05 17:07 ` Vignesh Raghavendra 2019-11-06 8:33 ` Tudor.Ambarus 2019-11-06 8:33 ` Tudor.Ambarus 2019-11-06 16:26 ` Vignesh Raghavendra 2019-11-06 16:26 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 14/20] mtd: spi-nor: Extend the QE Read Back test to the entire SR byte Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-02 11:23 ` [PATCH v4 15/20] mtd: spi-nor: Extend the QE Read Back test to both SR1 and SR2 Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-05 16:06 ` Vignesh Raghavendra 2019-11-05 16:06 ` Vignesh Raghavendra 2019-11-06 8:41 ` Tudor.Ambarus 2019-11-06 8:41 ` Tudor.Ambarus 2019-11-02 11:23 ` [PATCH v4 16/20] mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1 Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-06 5:45 ` Vignesh Raghavendra 2019-11-06 5:45 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 17/20] mtd: spi-nor: Merge spansion Quad Enable methods Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-06 5:46 ` Vignesh Raghavendra 2019-11-06 5:46 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 18/20] mtd: spi-nor: Rename macronix_quad_enable to spi_nor_sr1_bit6_quad_enable Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-06 6:00 ` Vignesh Raghavendra [this message] 2019-11-06 6:00 ` Vignesh Raghavendra 2019-11-02 11:23 ` [PATCH v4 19/20] mtd: spi-nor: Prepend "spi_nor_" to "sr2_bit7_quad_enable" Tudor.Ambarus 2019-11-02 11:23 ` Tudor.Ambarus 2019-11-02 11:24 ` [PATCH v4 20/20] mtd: spi-nor: Rework the disabling of block write protection Tudor.Ambarus 2019-11-02 11:24 ` Tudor.Ambarus 2019-11-07 6:27 ` [PATCH v4 00/20] mtd: spi-nor: Quad Enable and (un)lock methods Tudor.Ambarus 2019-11-07 6:27 ` Tudor.Ambarus
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