* [PATCH v3] drm/i915: BXT DDI PHY sequence BUN
@ 2016-03-31 17:45 Vandana Kannan
2016-04-01 7:26 ` Jani Nikula
2016-04-01 8:33 ` ✗ Fi.CI.BAT: failure for drm/i915: BXT DDI PHY sequence BUN (rev3) Patchwork
0 siblings, 2 replies; 6+ messages in thread
From: Vandana Kannan @ 2016-03-31 17:45 UTC (permalink / raw)
To: intel-gfx; +Cc: Nikula, Jani
According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
checked to ensure that the register is in accessible state.
Also, based on a BSpec update, changing the timeout value to
check iphypwrgood, from 10ms to wait for up to 100us.
v2: [Ville] use wait_for_us instead of the atomic call.
v3: [Jani/Imre] read register only once
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com>
Cc: Deak, Imre <imre.deak@intel.com>
Cc: Nikula, Jani <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ddi.c | 13 +++++++++++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7dfc400..9a02bfc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1318,6 +1318,7 @@ enum skl_disp_power_wells {
#define _PORT_CL1CM_DW0_A 0x162000
#define _PORT_CL1CM_DW0_BC 0x6C000
#define PHY_POWER_GOOD (1 << 16)
+#define PHY_RESERVED (1 << 7)
#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
_PORT_CL1CM_DW0_A)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 62de9f4..4a8f504 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2669,9 +2669,18 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
val |= GT_DISPLAY_POWER_ON(phy);
I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
- /* Considering 10ms timeout until BSpec is updated */
- if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
+ /*
+ * The PHY registers start out inaccessible and respond to reads with
+ * all 1s. Eventually they become accessible as they power up, then
+ * the reserved bit will give the default 0. Poll on the reserved bit
+ * becoming 0 to find when the PHY is accessible.
+ * HW team confirmed that the time to reach phypowergood status is
+ * anywhere between 50 us and 100us.
+ */
+ if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
+ (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
DRM_ERROR("timeout during PHY%d power on\n", phy);
+ }
for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3] drm/i915: BXT DDI PHY sequence BUN
2016-03-31 17:45 [PATCH v3] drm/i915: BXT DDI PHY sequence BUN Vandana Kannan
@ 2016-04-01 7:26 ` Jani Nikula
2016-04-01 10:03 ` Imre Deak
2016-04-01 8:33 ` ✗ Fi.CI.BAT: failure for drm/i915: BXT DDI PHY sequence BUN (rev3) Patchwork
1 sibling, 1 reply; 6+ messages in thread
From: Jani Nikula @ 2016-04-01 7:26 UTC (permalink / raw)
To: Vandana Kannan, intel-gfx
On Thu, 31 Mar 2016, Vandana Kannan <vandana.kannan@intel.com> wrote:
> According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
> checked to ensure that the register is in accessible state.
> Also, based on a BSpec update, changing the timeout value to
> check iphypwrgood, from 10ms to wait for up to 100us.
>
> v2: [Ville] use wait_for_us instead of the atomic call.
> v3: [Jani/Imre] read register only once
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com>
> Cc: Deak, Imre <imre.deak@intel.com>
> Cc: Nikula, Jani <jani.nikula@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ddi.c | 13 +++++++++++--
> 2 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7dfc400..9a02bfc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells {
> #define _PORT_CL1CM_DW0_A 0x162000
> #define _PORT_CL1CM_DW0_BC 0x6C000
> #define PHY_POWER_GOOD (1 << 16)
> +#define PHY_RESERVED (1 << 7)
> #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
> _PORT_CL1CM_DW0_A)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 62de9f4..4a8f504 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2669,9 +2669,18 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
> val |= GT_DISPLAY_POWER_ON(phy);
> I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
>
> - /* Considering 10ms timeout until BSpec is updated */
> - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
> + /*
> + * The PHY registers start out inaccessible and respond to reads with
> + * all 1s. Eventually they become accessible as they power up, then
> + * the reserved bit will give the default 0. Poll on the reserved bit
> + * becoming 0 to find when the PHY is accessible.
> + * HW team confirmed that the time to reach phypowergood status is
> + * anywhere between 50 us and 100us.
> + */
> + if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> + (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
> DRM_ERROR("timeout during PHY%d power on\n", phy);
> + }
>
> for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
> port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: BXT DDI PHY sequence BUN (rev3)
2016-03-31 17:45 [PATCH v3] drm/i915: BXT DDI PHY sequence BUN Vandana Kannan
2016-04-01 7:26 ` Jani Nikula
@ 2016-04-01 8:33 ` Patchwork
2016-04-01 10:12 ` Imre Deak
1 sibling, 1 reply; 6+ messages in thread
From: Patchwork @ 2016-04-01 8:33 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: BXT DDI PHY sequence BUN (rev3)
URL : https://patchwork.freedesktop.org/series/4687/
State : failure
== Summary ==
Series 4687v3 drm/i915: BXT DDI PHY sequence BUN
http://patchwork.freedesktop.org/api/1.0/series/4687/revisions/3/mbox/
Test drv_module_reload_basic:
skip -> PASS (skl-nuci5)
bdw-nuci7 total:196 pass:184 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:196 pass:175 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:196 pass:159 dwarn:0 dfail:0 fail:0 skip:37
byt-nuc total:196 pass:161 dwarn:0 dfail:0 fail:0 skip:35
hsw-brixbox total:196 pass:174 dwarn:0 dfail:0 fail:0 skip:22
skl-i7k-2 total:196 pass:173 dwarn:0 dfail:0 fail:0 skip:23
skl-nuci5 total:196 pass:185 dwarn:0 dfail:0 fail:0 skip:11
BOOT FAILED for snb-dellxps
Results at /archive/results/CI_IGT_test/Patchwork_1769/
e8d1e8123ef907fc23b53554af9cb99c7f380fb9 drm-intel-nightly: 2016y-04m-01d-07h-26m-00s UTC integration manifest
25dc2984df5282161927d641a225b3a2f70a2f1d drm/i915: BXT DDI PHY sequence BUN
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] drm/i915: BXT DDI PHY sequence BUN
2016-04-01 7:26 ` Jani Nikula
@ 2016-04-01 10:03 ` Imre Deak
0 siblings, 0 replies; 6+ messages in thread
From: Imre Deak @ 2016-04-01 10:03 UTC (permalink / raw)
To: Jani Nikula, Vandana Kannan, intel-gfx
On pe, 2016-04-01 at 10:26 +0300, Jani Nikula wrote:
> On Thu, 31 Mar 2016, Vandana Kannan <vandana.kannan@intel.com> wrote:
> > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
> > checked to ensure that the register is in accessible state.
> > Also, based on a BSpec update, changing the timeout value to
> > check iphypwrgood, from 10ms to wait for up to 100us.
> >
> > v2: [Ville] use wait_for_us instead of the atomic call.
> > v3: [Jani/Imre] read register only once
> >
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> > Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com>
> > Cc: Deak, Imre <imre.deak@intel.com>
> > Cc: Nikula, Jani <jani.nikula@intel.com>
>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Vandana, for next time: please use git format-patch --in-reply-to when
sending a new version of individual patches to maintain proper email
threading.
--Imre
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_ddi.c | 13 +++++++++++--
> > 2 files changed, 12 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7dfc400..9a02bfc 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells {
> > #define _PORT_CL1CM_DW0_A 0x162000
> > #define _PORT_CL1CM_DW0_BC 0x6C000
> > #define PHY_POWER_GOOD (1 << 16)
> > +#define PHY_RESERVED (1 << 7)
> > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
> > _PORT_CL1CM_DW0_A)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 62de9f4..4a8f504 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2669,9 +2669,18 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
> > val |= GT_DISPLAY_POWER_ON(phy);
> > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
> >
> > - /* Considering 10ms timeout until BSpec is updated */
> > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
> > + /*
> > + * The PHY registers start out inaccessible and respond to reads with
> > + * all 1s. Eventually they become accessible as they power up, then
> > + * the reserved bit will give the default 0. Poll on the reserved bit
> > + * becoming 0 to find when the PHY is accessible.
> > + * HW team confirmed that the time to reach phypowergood status is
> > + * anywhere between 50 us and 100us.
> > + */
> > + if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> > + (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
> > DRM_ERROR("timeout during PHY%d power on\n", phy);
> > + }
> >
> > for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
> > port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: BXT DDI PHY sequence BUN (rev3)
2016-04-01 8:33 ` ✗ Fi.CI.BAT: failure for drm/i915: BXT DDI PHY sequence BUN (rev3) Patchwork
@ 2016-04-01 10:12 ` Imre Deak
2016-04-01 10:18 ` Tomi Sarvela
0 siblings, 1 reply; 6+ messages in thread
From: Imre Deak @ 2016-04-01 10:12 UTC (permalink / raw)
To: intel-gfx, Vandana Kannan, Jani Nikula; +Cc: Sarvela, Tomi P
On pe, 2016-04-01 at 08:33 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: BXT DDI PHY sequence BUN (rev3)
> URL : https://patchwork.freedesktop.org/series/4687/
> State : failure
>
> == Summary ==
>
> Series 4687v3 drm/i915: BXT DDI PHY sequence BUN
> http://patchwork.freedesktop.org/api/1.0/series/4687/revisions/3/mbox
> /
>
> Test drv_module_reload_basic:
> skip -> PASS (skl-nuci5)
>
> bdw-
> nuci7 total:196 pass:184 dwarn:0 dfail:0 fail:0 skip:1
> 2
> bdw-
> ultra total:196 pass:175 dwarn:0 dfail:0 fail:0 skip:2
> 1
> bsw-nuc-
> 2 total:196 pass:159 dwarn:0 dfail:0 fail:0 skip:37
> byt-
> nuc total:196 pass:161 dwarn:0 dfail:0 fail:0 skip:3
> 5
> hsw-
> brixbox total:196 pass:174 dwarn:0 dfail:0 fail:0 skip:2
> 2
> skl-i7k-
> 2 total:196 pass:173 dwarn:0 dfail:0 fail:0 skip:23
> skl-
> nuci5 total:196 pass:185 dwarn:0 dfail:0 fail:0 skip:1
> 1
> BOOT FAILED for snb-dellxps
>
> Results at /archive/results/CI_IGT_test/Patchwork_1769/
Hrm, something went wrong with CI, I see no results behind the above
link. But since there is no BXT atm in the CI farm I went ahead and
pushed this one to -dinq.
Thanks for the patch and review.
>
> e8d1e8123ef907fc23b53554af9cb99c7f380fb9 drm-intel-nightly: 2016y-
> 04m-01d-07h-26m-00s UTC integration manifest
> 25dc2984df5282161927d641a225b3a2f70a2f1d drm/i915: BXT DDI PHY
> sequence BUN
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915: BXT DDI PHY sequence BUN (rev3)
2016-04-01 10:12 ` Imre Deak
@ 2016-04-01 10:18 ` Tomi Sarvela
0 siblings, 0 replies; 6+ messages in thread
From: Tomi Sarvela @ 2016-04-01 10:18 UTC (permalink / raw)
To: imre.deak; +Cc: Jani Nikula, intel-gfx
Temporary fluke, they are there now. Nothing special, just dellxps not deciding
which suspend-read-crc-pipe it hangs this time.
Tomi
On Friday 01 April 2016 13:12:41 Imre Deak wrote:
> On pe, 2016-04-01 at 08:33 +0000, Patchwork wrote:
> > BOOT FAILED for snb-dellxps
> >
> > Results at /archive/results/CI_IGT_test/Patchwork_1769/
>
> Hrm, something went wrong with CI, I see no results behind the above
> link. But since there is no BXT atm in the CI farm I went ahead and
> pushed this one to -dinq.
>
> Thanks for the patch and review.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-04-01 10:18 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-31 17:45 [PATCH v3] drm/i915: BXT DDI PHY sequence BUN Vandana Kannan
2016-04-01 7:26 ` Jani Nikula
2016-04-01 10:03 ` Imre Deak
2016-04-01 8:33 ` ✗ Fi.CI.BAT: failure for drm/i915: BXT DDI PHY sequence BUN (rev3) Patchwork
2016-04-01 10:12 ` Imre Deak
2016-04-01 10:18 ` Tomi Sarvela
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