From: Vignesh Raghavendra <vigneshr@ti.com> To: Pratyush Yadav <p.yadav@ti.com>, Rob Herring <robh@kernel.org> Cc: Mark Brown <broonie@kernel.org>, Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>, <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH 4/4] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Date: Thu, 1 Apr 2021 13:57:49 +0530 [thread overview] Message-ID: <1161dc3b-c889-c5d7-f7c8-baf5b7b79505@ti.com> (raw) In-Reply-To: <20210329182256.q4zhss6lezj3s44a@ti.com> On 3/29/21 11:52 PM, Pratyush Yadav wrote: >>> + cdns,fifo-depth: >>> + description: >>> + Size of the data FIFO in words. >>> + $ref: "/schemas/types.yaml#/definitions/uint32" >>> + enum: [ 128, 256 ] >>> + default: 128 >>> + >>> + cdns,fifo-width: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + description: >>> + Bus width of the data FIFO in bytes. >>> + default: 4 >> I assume there's some constraints on this? > IIUC this is a matter of how the peripheral is implemented and there are > no clear constraints. Different implementations can use different bus > widths for the SRAM bus but I don't see any mention of minimum or > maximum values. FWIW, all users in the kernel use a 4 byte bus. > IMO a safe constraint would be to set a range of 1 to 4 (8/16/24/32 bit wide) given this represents SRAM bus width. Binding can always be updated if there exists an implementation with higher SRAM bus width/fifo-width (although that's highly unlikely given there are no such examples today). But leaving it open ended with range of 0 to UINT_MAX sounds incorrect to me. >> With that, >> >> Reviewed-by: Rob Herring <robh@kernel.org> > Thanks. >
WARNING: multiple messages have this Message-ID (diff)
From: Vignesh Raghavendra <vigneshr@ti.com> To: Pratyush Yadav <p.yadav@ti.com>, Rob Herring <robh@kernel.org> Cc: Mark Brown <broonie@kernel.org>, Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>, <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org> Subject: Re: [PATCH 4/4] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Date: Thu, 1 Apr 2021 13:57:49 +0530 [thread overview] Message-ID: <1161dc3b-c889-c5d7-f7c8-baf5b7b79505@ti.com> (raw) In-Reply-To: <20210329182256.q4zhss6lezj3s44a@ti.com> On 3/29/21 11:52 PM, Pratyush Yadav wrote: >>> + cdns,fifo-depth: >>> + description: >>> + Size of the data FIFO in words. >>> + $ref: "/schemas/types.yaml#/definitions/uint32" >>> + enum: [ 128, 256 ] >>> + default: 128 >>> + >>> + cdns,fifo-width: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + description: >>> + Bus width of the data FIFO in bytes. >>> + default: 4 >> I assume there's some constraints on this? > IIUC this is a matter of how the peripheral is implemented and there are > no clear constraints. Different implementations can use different bus > widths for the SRAM bus but I don't see any mention of minimum or > maximum values. FWIW, all users in the kernel use a 4 byte bus. > IMO a safe constraint would be to set a range of 1 to 4 (8/16/24/32 bit wide) given this represents SRAM bus width. Binding can always be updated if there exists an implementation with higher SRAM bus width/fifo-width (although that's highly unlikely given there are no such examples today). But leaving it open ended with range of 0 to UINT_MAX sounds incorrect to me. >> With that, >> >> Reviewed-by: Rob Herring <robh@kernel.org> > Thanks. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-04-01 8:29 UTC|newest] Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-26 13:00 [PATCH 0/4] Convert Cadence QSPI bindings to yaml Pratyush Yadav 2021-03-26 13:00 ` Pratyush Yadav 2021-03-26 13:00 ` [PATCH 1/4] arm64: dts: ti: k3-j721e-mcu: Fix ospi compatible Pratyush Yadav 2021-03-26 13:00 ` Pratyush Yadav 2021-04-01 6:28 ` Vignesh Raghavendra 2021-04-01 6:28 ` Vignesh Raghavendra 2021-03-26 13:00 ` [PATCH 2/4] arm64: dts: ti: k3-j7200-mcu: " Pratyush Yadav 2021-03-26 13:00 ` Pratyush Yadav 2021-04-01 6:28 ` Vignesh Raghavendra 2021-04-01 6:28 ` Vignesh Raghavendra 2021-03-26 13:00 ` [PATCH 3/4] arm64: dts: ti: k3-am64-main: " Pratyush Yadav 2021-03-26 13:00 ` Pratyush Yadav 2021-04-01 6:29 ` Vignesh Raghavendra 2021-04-01 6:29 ` Vignesh Raghavendra 2021-03-26 13:00 ` [PATCH 4/4] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml Pratyush Yadav 2021-03-26 13:00 ` Pratyush Yadav 2021-03-27 18:36 ` Rob Herring 2021-03-27 18:36 ` Rob Herring 2021-03-29 18:22 ` Pratyush Yadav 2021-03-29 18:22 ` Pratyush Yadav 2021-04-01 8:27 ` Vignesh Raghavendra [this message] 2021-04-01 8:27 ` Vignesh Raghavendra 2021-04-01 8:56 ` Pratyush Yadav 2021-04-01 8:56 ` Pratyush Yadav 2021-03-31 19:11 ` Mark Brown 2021-03-31 19:11 ` Mark Brown 2021-03-31 19:39 ` Pratyush Yadav 2021-03-31 19:39 ` Pratyush Yadav 2021-04-01 14:13 ` Mark Brown 2021-04-01 14:13 ` Mark Brown 2021-04-05 8:34 ` Pratyush Yadav 2021-04-05 8:34 ` Pratyush Yadav 2021-04-01 10:16 ` (subset) [PATCH 0/4] Convert Cadence QSPI bindings to yaml Mark Brown 2021-04-01 10:16 ` Mark Brown 2021-04-01 13:52 ` Nishanth Menon 2021-04-01 13:52 ` Nishanth Menon 2021-03-29 1:14 [PATCH 4/4] dt-bindings: spi: Convert cadence-quadspi.txt to cadence-quadspi.yaml kernel test robot
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