[U-Boot-Users] [PATCH 1/3]Add the cpu and board specific code for MPC8349E rev3.1 MDS

[U-Boot-Users] [PATCH 1/3]Add the cpu and board specific code for MPC8349E rev3.1 MDS

[Xie Xiaobo]

MPC8349E rev3.1 have new spridr,and PVR value,
The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM.

Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>

---
This patch applies to the mpc83xx branch of the opensource.freescale.com u-boot-83xx.git tree

 cpu/mpc83xx/cpu.c             |   17 +++++++++++++--
 include/configs/MPC8349EMDS.h |   44 +++++++++++++++++++++++++++++++++-------
 include/mpc83xx.h             |   13 ++++++++++-
 3 files changed, 61 insertions(+), 13 deletions(-)

diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index c24a20f..9f55f18 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -56,30 +56,38 @@ int checkcpu(void)
 	switch(spridr) {
 	case SPR_8349E_REV10:
 	case SPR_8349E_REV11:
+	case SPR_8349E_REV31:
 		puts("MPC8349E, ");
 		break;
 	case SPR_8349_REV10:
 	case SPR_8349_REV11:
+	case SPR_8349_REV31:
 		puts("MPC8349, ");
 		break;
 	case SPR_8347E_REV10_TBGA:
 	case SPR_8347E_REV11_TBGA:
+	case SPR_8347E_REV31_TBGA:
 	case SPR_8347E_REV10_PBGA:
 	case SPR_8347E_REV11_PBGA:
+	case SPR_8347E_REV31_PBGA:
 		puts("MPC8347E, ");
 		break;
 	case SPR_8347_REV10_TBGA:
 	case SPR_8347_REV11_TBGA:
+	case SPR_8347_REV31_TBGA:
 	case SPR_8347_REV10_PBGA:
 	case SPR_8347_REV11_PBGA:
+	case SPR_8347_REV31_PBGA:
 		puts("MPC8347, ");
 		break;
 	case SPR_8343E_REV10:
 	case SPR_8343E_REV11:
+	case SPR_8343E_REV31:
 		puts("MPC8343E, ");
 		break;
 	case SPR_8343_REV10:
 	case SPR_8343_REV11:
+	case SPR_8343_REV31:
 		puts("MPC8343, ");
 		break;
 	case SPR_8360E_REV10:
@@ -109,12 +117,15 @@ int checkcpu(void)
 		puts("MPC8321, ");
 		break;
 	default:
-		puts("Rev: Unknown\n");
-		return -1;	/* Not sure what this is */
+		puts("Rev: Unknown revision number.\nWarning: Unsupported cpu revision!\n");
+		return 0;
 	}
 
 #if defined(CONFIG_MPC834X)
-	printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock));
+	/* Multiple revisons of 834x processors may have the same SPRIDR value.
+	 * So use PVR to identify the revision number.
+	 */
+	printf("Rev: %02x at %s MHz\n", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
 #else
 	printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
 #endif
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index e7a961e..757ed4c 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -82,7 +82,7 @@
 /*
  * DDR Setup
  */
-#undef CONFIG_DDR_ECC			/* only for ECC DDR module */
+#define CONFIG_DDR_ECC			/* support DDR ECC function */
 #define CONFIG_DDR_ECC_CMD		/* use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 
@@ -101,8 +101,15 @@
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_BASE
 #define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#define CFG_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
+				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING
 
+/*
+ * DDRCDR - DDR Control Driver Register
+ */
+#define CFG_DDRCDR_VALUE	0x80080001
+
 #if defined(CONFIG_SPD_EEPROM)
 /*
  * Determine DDR configuration from I2C interface.
@@ -113,6 +120,21 @@
  * Manually set up DDR parameters
  */
 #define CFG_DDR_SIZE		256		/* MB */
+#if defined(CONFIG_DDR_II)
+#define CFG_DDRCDR		0x80080001
+#define CFG_DDR_CS2_BNDS	0x0000000f
+#define CFG_DDR_CS2_CONFIG	0x80330102
+#define CFG_DDR_TIMING_0	0x00220802
+#define CFG_DDR_TIMING_1	0x38357322
+#define CFG_DDR_TIMING_2	0x2f9048c8
+#define CFG_DDR_TIMING_3	0x00000000
+#define CFG_DDR_CLK_CNTL	0x02000000
+#define CFG_DDR_MODE		0x47d00432
+#define CFG_DDR_MODE2		0x8000c000
+#define CFG_DDR_INTERVAL	0x03cf0080
+#define CFG_DDR_SDRAM_CFG	0x43000000
+#define CFG_DDR_SDRAM_CFG2	0x00401000
+#else
 #define CFG_DDR_CONFIG		(CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
 #define CFG_DDR_TIMING_1	0x36332321
 #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
@@ -127,6 +149,7 @@
 #define CFG_DDR_MODE		0x00000022	/* DLL,normal,seq,4/2.5, 4 burst len */
 #endif
 #endif
+#endif
 
 /*
  * SDRAM on the Local Bus
@@ -140,19 +163,20 @@
 #define CFG_FLASH_CFI				/* use the Common Flash Interface */
 #define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
 #define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
-#define CFG_FLASH_SIZE		8		/* flash size in MB */
+#define CFG_FLASH_SIZE		32		/* max flash size in MB */
 /* #define CFG_FLASH_USE_BUFFER_WRITE */
 
 #define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
-				(2 << BR_PS_SHIFT) |	/* 32 bit port size */	 \
+				(2 << BR_PS_SHIFT) |	/* 16 bit port size */	 \
 				BR_V)			/* valid */
-
-#define CFG_OR0_PRELIM		0xFF806FF7	/* 8 MB flash size */
+#define CFG_OR0_PRELIM		((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
+				OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
+				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 #define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base@flash base */
-#define CFG_LBLAWAR0_PRELIM	0x80000016	/* 8 MB window size */
+#define CFG_LBLAWAR0_PRELIM	0x80000018	/* 32 MB window size */
 
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
+#define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
 
 #undef CFG_FLASH_CHECKSUM
 #define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
@@ -197,7 +221,11 @@
 #define CFG_LCRR	(LCRR_DBYP | LCRR_CLKDIV_4)
 #define CFG_LBC_LBCR	0x00000000
 
-#define CFG_LB_SDRAM	/* if board has SRDAM on local bus */
+/*
+ * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
+ * if board has SRDAM on local bus, you can define CFG_LB_SDRAM
+ */
+#undef CFG_LB_SDRAM
 
 #ifdef CFG_LB_SDRAM
 /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 1b62f81..73f2721 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -68,6 +68,15 @@
 #define SPR_8343E_REV11			0x80360101
 #define SPR_8343_REV11			0x80370101
 
+#define SPR_8349E_REV31			0x80300300
+#define SPR_8349_REV31			0x80310300
+#define SPR_8347E_REV31_TBGA		0x80320300
+#define SPR_8347_REV31_TBGA		0x80330300
+#define SPR_8347E_REV31_PBGA		0x80340300
+#define SPR_8347_REV31_PBGA		0x80350300
+#define SPR_8343E_REV31			0x80360300
+#define SPR_8343_REV31			0x80370300
+
 #define SPR_8360E_REV10			0x80480010
 #define SPR_8360_REV10			0x80490010
 #define SPR_8360E_REV11			0x80480011
@@ -573,8 +582,8 @@
 
 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
  */
-#define TIMING_CFG2_CPO			0x0F000000
-#define TIMING_CFG2_CPO_SHIFT		24
+#define TIMING_CFG2_CPO			0x0F800000
+#define TIMING_CFG2_CPO_SHIFT		23
 #define TIMING_CFG2_ACSM		0x00080000
 #define TIMING_CFG2_WR_DATA_DELAY	0x00001C00
 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT	10
-- 
1.4.4.1