* [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3
@ 2018-06-27 18:16 Dan Murphy
2018-06-27 18:16 ` [PATCH 2/2] net: phy: DP83TC811: Fix SGMII enable/disable Dan Murphy
2018-06-28 8:16 ` [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3 Andrew Lunn
0 siblings, 2 replies; 7+ messages in thread
From: Dan Murphy @ 2018-06-27 18:16 UTC (permalink / raw)
To: andrew, f.fainelli; +Cc: netdev, Dan Murphy
Add INT_STAT3 interrupt setting and clearing.
Also fixed writing to INT_STAT2 when disabling
the interrupts as there was a double write to
INT_STAT1.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
drivers/net/phy/dp83tc811.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/dp83tc811.c b/drivers/net/phy/dp83tc811.c
index 081d99aa3985..f8653f5d8789 100644
--- a/drivers/net/phy/dp83tc811.c
+++ b/drivers/net/phy/dp83tc811.c
@@ -21,6 +21,7 @@
#define MII_DP83811_SGMII_CTRL 0x09
#define MII_DP83811_INT_STAT1 0x12
#define MII_DP83811_INT_STAT2 0x13
+#define MII_DP83811_INT_STAT3 0x18
#define MII_DP83811_RESET_CTRL 0x1f
#define DP83811_HW_RESET BIT(15)
@@ -44,6 +45,11 @@
#define DP83811_OVERVOLTAGE_INT_EN BIT(6)
#define DP83811_UNDERVOLTAGE_INT_EN BIT(7)
+/* INT_STAT3 bits */
+#define DP83811_LPS_INT_EN BIT(0)
+#define DP83811_NO_FRAME_INT_EN BIT(3)
+#define DP83811_POR_DONE_INT_EN BIT(4)
+
#define MII_DP83811_RXSOP1 0x04a5
#define MII_DP83811_RXSOP2 0x04a6
#define MII_DP83811_RXSOP3 0x04a7
@@ -81,6 +87,10 @@ static int dp83811_ack_interrupt(struct phy_device *phydev)
if (err < 0)
return err;
+ err = phy_read(phydev, MII_DP83811_INT_STAT3);
+ if (err < 0)
+ return err;
+
return 0;
}
@@ -216,13 +226,29 @@ static int dp83811_config_intr(struct phy_device *phydev)
DP83811_UNDERVOLTAGE_INT_EN);
err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
+ if (err < 0)
+ return err;
+
+ misr_status = phy_read(phydev, MII_DP83811_INT_STAT3);
+ if (misr_status < 0)
+ return misr_status;
+
+ misr_status |= (DP83811_LPS_INT_EN |
+ DP83811_NO_FRAME_INT_EN |
+ DP83811_POR_DONE_INT_EN);
+
+ err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status);
} else {
err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
if (err < 0)
return err;
- err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
+ err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
+ if (err < 0)
+ return err;
+
+ err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
}
return err;
--
2.17.0.582.gccdcbd54c
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/2] net: phy: DP83TC811: Fix SGMII enable/disable
2018-06-27 18:16 [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3 Dan Murphy
@ 2018-06-27 18:16 ` Dan Murphy
2018-06-28 8:20 ` Andrew Lunn
2018-06-28 8:16 ` [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3 Andrew Lunn
1 sibling, 1 reply; 7+ messages in thread
From: Dan Murphy @ 2018-06-27 18:16 UTC (permalink / raw)
To: andrew, f.fainelli; +Cc: netdev, Dan Murphy
If SGMII was selected in the DT then the device should
write the SGMII enable bit.
If SGMII is not selected in the DT then the SGMII bit
should be disabled.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
arch/arm/configs/omap2plus_defconfig | 1 +
drivers/net/phy/dp83tc811.c | 20 +++++++++-----------
2 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 06fb948ecfb3..30857d5b7a6c 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -182,6 +182,7 @@ CONFIG_TI_CPTS=y
CONFIG_AT803X_PHY=y
CONFIG_DP83848_PHY=y
CONFIG_DP83867_PHY=y
+CONFIG_DP83TC811_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_PPP=m
diff --git a/drivers/net/phy/dp83tc811.c b/drivers/net/phy/dp83tc811.c
index f8653f5d8789..78cad134a79e 100644
--- a/drivers/net/phy/dp83tc811.c
+++ b/drivers/net/phy/dp83tc811.c
@@ -284,21 +284,19 @@ static int dp83811_config_init(struct phy_device *phydev)
if (err < 0)
return err;
+ value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
- value = phy_read(phydev, MII_DP83811_SGMII_CTRL);
- if (!(value & DP83811_SGMII_EN)) {
- err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
+ err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
(DP83811_SGMII_EN | value));
- if (err < 0)
- return err;
- } else {
- err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
- (~DP83811_SGMII_EN & value));
- if (err < 0)
- return err;
- }
+ } else {
+ err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
+ (~DP83811_SGMII_EN & value));
}
+ if (err < 0)
+
+ return err;
+
value = DP83811_WOL_MAGIC_EN | DP83811_WOL_SECURE_ON | DP83811_WOL_EN;
return phy_write_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG,
--
2.17.0.582.gccdcbd54c
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 2/2] net: phy: DP83TC811: Fix SGMII enable/disable
2018-06-27 18:16 ` [PATCH 2/2] net: phy: DP83TC811: Fix SGMII enable/disable Dan Murphy
@ 2018-06-28 8:20 ` Andrew Lunn
2018-06-28 11:53 ` Dan Murphy
0 siblings, 1 reply; 7+ messages in thread
From: Andrew Lunn @ 2018-06-28 8:20 UTC (permalink / raw)
To: Dan Murphy; +Cc: f.fainelli, netdev
On Wed, Jun 27, 2018 at 01:16:18PM -0500, Dan Murphy wrote:
> If SGMII was selected in the DT then the device should
> write the SGMII enable bit.
>
> If SGMII is not selected in the DT then the SGMII bit
> should be disabled.
>
> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> ---
> arch/arm/configs/omap2plus_defconfig | 1 +
> drivers/net/phy/dp83tc811.c | 20 +++++++++-----------
> 2 files changed, 10 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
> index 06fb948ecfb3..30857d5b7a6c 100644
> --- a/arch/arm/configs/omap2plus_defconfig
> +++ b/arch/arm/configs/omap2plus_defconfig
> @@ -182,6 +182,7 @@ CONFIG_TI_CPTS=y
> CONFIG_AT803X_PHY=y
> CONFIG_DP83848_PHY=y
> CONFIG_DP83867_PHY=y
> +CONFIG_DP83TC811_PHY=y
> CONFIG_MICREL_PHY=y
> CONFIG_SMSC_PHY=y
> CONFIG_PPP=m
Hi Dan
This change does not belong here.
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 2/2] net: phy: DP83TC811: Fix SGMII enable/disable
2018-06-28 8:20 ` Andrew Lunn
@ 2018-06-28 11:53 ` Dan Murphy
0 siblings, 0 replies; 7+ messages in thread
From: Dan Murphy @ 2018-06-28 11:53 UTC (permalink / raw)
To: Andrew Lunn; +Cc: f.fainelli, netdev
Andrew
On 06/28/2018 03:20 AM, Andrew Lunn wrote:
> On Wed, Jun 27, 2018 at 01:16:18PM -0500, Dan Murphy wrote:
>> If SGMII was selected in the DT then the device should
>> write the SGMII enable bit.
>>
>> If SGMII is not selected in the DT then the SGMII bit
>> should be disabled.
>>
>> Signed-off-by: Dan Murphy <dmurphy@ti.com>
>> ---
>> arch/arm/configs/omap2plus_defconfig | 1 +
>> drivers/net/phy/dp83tc811.c | 20 +++++++++-----------
>> 2 files changed, 10 insertions(+), 11 deletions(-)
>>
>> diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
>> index 06fb948ecfb3..30857d5b7a6c 100644
>> --- a/arch/arm/configs/omap2plus_defconfig
>> +++ b/arch/arm/configs/omap2plus_defconfig
>> @@ -182,6 +182,7 @@ CONFIG_TI_CPTS=y
>> CONFIG_AT803X_PHY=y
>> CONFIG_DP83848_PHY=y
>> CONFIG_DP83867_PHY=y
>> +CONFIG_DP83TC811_PHY=y
>> CONFIG_MICREL_PHY=y
>> CONFIG_SMSC_PHY=y
>> CONFIG_PPP=m
>
> Hi Dan
>
> This change does not belong here.
>
Correct I will remove it.
> Andrew
>
--
------------------
Dan Murphy
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3
2018-06-27 18:16 [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3 Dan Murphy
2018-06-27 18:16 ` [PATCH 2/2] net: phy: DP83TC811: Fix SGMII enable/disable Dan Murphy
@ 2018-06-28 8:16 ` Andrew Lunn
2018-06-28 11:54 ` Dan Murphy
1 sibling, 1 reply; 7+ messages in thread
From: Andrew Lunn @ 2018-06-28 8:16 UTC (permalink / raw)
To: Dan Murphy; +Cc: f.fainelli, netdev
> err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
> if (err < 0)
> return err;
>
> - err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
> + err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
> + if (err < 0)
> + return err;
> +
> + err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
> }
>
Hi Dan
This seems like a bug fix, and so should be in a patch of its own, for
net, not net-next.
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3
2018-06-28 8:16 ` [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3 Andrew Lunn
@ 2018-06-28 11:54 ` Dan Murphy
2018-06-28 12:04 ` Andrew Lunn
0 siblings, 1 reply; 7+ messages in thread
From: Dan Murphy @ 2018-06-28 11:54 UTC (permalink / raw)
To: Andrew Lunn; +Cc: f.fainelli, netdev
Andrew
On 06/28/2018 03:16 AM, Andrew Lunn wrote:
>> err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
>> if (err < 0)
>> return err;
>>
>> - err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
>> + err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
>> + if (err < 0)
>> + return err;
>> +
>> + err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
>> }
>>
>
> Hi Dan
>
> This seems like a bug fix, and so should be in a patch of its own, for
> net, not net-next.
>
Yes I was debating whether to include this change in the patch or have it
stand alone for stable back port.
I will pull it out and cc stable
> Andrew
>
--
------------------
Dan Murphy
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3
2018-06-28 11:54 ` Dan Murphy
@ 2018-06-28 12:04 ` Andrew Lunn
0 siblings, 0 replies; 7+ messages in thread
From: Andrew Lunn @ 2018-06-28 12:04 UTC (permalink / raw)
To: Dan Murphy; +Cc: f.fainelli, netdev
> Yes I was debating whether to include this change in the patch or have it
> stand alone for stable back port.
>
> I will pull it out and cc stable
No need to CC stable. Base the patch on daveM net branch, and David
will do the rest.
You probably want to wait a week or two before sending the other
patches for net-next. You want net to be merged into net-next, in
order to avoid conflicts.
Andrew
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-06-28 12:04 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-27 18:16 [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3 Dan Murphy
2018-06-27 18:16 ` [PATCH 2/2] net: phy: DP83TC811: Fix SGMII enable/disable Dan Murphy
2018-06-28 8:20 ` Andrew Lunn
2018-06-28 11:53 ` Dan Murphy
2018-06-28 8:16 ` [PATCH 1/2] net: phy: DP83TC811: Add INT_STAT3 Andrew Lunn
2018-06-28 11:54 ` Dan Murphy
2018-06-28 12:04 ` Andrew Lunn
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