[PATCH 1/2] Alchemy: MIPS hazard workarounds are not required.

[PATCH 1/2] Alchemy: MIPS hazard workarounds are not required.

[Manuel Lauss]

Quoting the Au1xxx manuals:
"All pipeline hazards and dependencies are enforced by hardware interlocks
 so that any sequence of instructions is guaranteed to execute correctly.
 Therefore, it is not necessary to pad legacy MIPS hazards (such as
 load delay slots and coprocessor accesses) with NOPs."

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
---
 arch/mips/include/asm/hazards.h |    5 +++--
 arch/mips/mm/tlbex.c            |   14 +++++++-------
 2 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 43baed1..0a0f241 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -87,7 +87,7 @@ do {									\
 	: "=r" (tmp));							\
 } while (0)
 
-#elif defined(CONFIG_CPU_MIPSR1)
+#elif defined(CONFIG_CPU_MIPSR1) && !defined(CONFIG_MACH_ALCHEMY)
 
 /*
  * These are slightly complicated by the fact that we guarantee R1 kernels to
@@ -138,7 +138,8 @@ do {									\
 		__instruction_hazard();					\
 } while (0)
 
-#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
+#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)	\
+   || defined(CONFIG_MACH_ALCHEMY)
 
 /*
  * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 4294203..c36e8c2 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -292,13 +292,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 	case CPU_R4300:
 	case CPU_5KC:
 	case CPU_TX49XX:
-	case CPU_AU1000:
-	case CPU_AU1100:
-	case CPU_AU1500:
-	case CPU_AU1550:
-	case CPU_AU1200:
-	case CPU_AU1210:
-	case CPU_AU1250:
 	case CPU_PR4450:
 		uasm_i_nop(p);
 		tlbw(p);
@@ -318,6 +311,13 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
 	case CPU_BCM4710:
 	case CPU_LOONGSON2:
 	case CPU_CAVIUM_OCTEON:
+	case CPU_AU1000:
+	case CPU_AU1100:
+	case CPU_AU1500:
+	case CPU_AU1550:
+	case CPU_AU1200:
+	case CPU_AU1210:
+	case CPU_AU1250:
 		if (m4kc_tlbp_war())
 			uasm_i_nop(p);
 		tlbw(p);
-- 
1.6.0.4

[PATCH 2/2] Alchemy: provide cpu feature overrides.

[Manuel Lauss]

Add cpu feature override constants for Alchemy.

Code generated for Alchemy does not use all MIPS32r1 features.  Add cpu
feature overrides tailored for Alchemy chips and help GCC create better
code.  As a nice sideeffect the size of the resulting kernel is reduced
by a few kilobytes (~200kB for a non-modular db1200 devboard build).

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
---
 .../asm/mach-au1x00/cpu-feature-overrides.h        |   51 ++++++++++++++++++++
 1 files changed, 51 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h

diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
new file mode 100644
index 0000000..725e575
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -0,0 +1,51 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
+
+#define cpu_has_tlb			1
+#define cpu_has_4kex			1
+#define cpu_has_3k_cache		0
+#define cpu_has_4k_cache		1
+#define cpu_has_tx39_cache		0
+#define cpu_has_fpu			0
+#define cpu_has_32fpr			0
+#define cpu_has_counter			1
+#define cpu_has_watch			1
+#define cpu_has_divec			1
+#define cpu_has_vce			0
+#define cpu_has_cache_cdex_p		0
+#define cpu_has_cache_cdex_s		0
+#define cpu_has_mcheck			1
+#define cpu_has_ejtag			1
+#define cpu_has_llsc			1
+#define cpu_has_mips16			0
+#define cpu_has_mdmx			0
+#define cpu_has_mips3d			0
+#define cpu_has_smartmips		0
+#define cpu_has_vtag_icache		0
+#define cpu_has_dc_aliases		0
+#define cpu_has_ic_fills_f_dc		1
+#define cpu_has_pindexed_cache		0
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_has_dsp			0
+#define cpu_has_mipsmt			0
+#define cpu_has_userlocal		0
+#define cpu_has_nofpuex			0
+#define cpu_has_64bits			0
+#define cpu_has_64bit_zero_reg		0
+#define cpu_has_vint			0
+#define cpu_has_veic			0
+#define cpu_has_inclusive_pcaches	0
+
+#define cpu_dcache_line_size()		32
+#define cpu_icache_line_size()		32
+
+#endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */
-- 
1.6.0.4

Re: [PATCH 2/2] Alchemy: provide cpu feature overrides.

[Ralf Baechle]

On Mon, Dec 22, 2008 at 08:21:08PM +0100, Manuel Lauss wrote:

> Add cpu feature override constants for Alchemy.
> 
> Code generated for Alchemy does not use all MIPS32r1 features.  Add cpu
> feature overrides tailored for Alchemy chips and help GCC create better
> code.  As a nice sideeffect the size of the resulting kernel is reduced
> by a few kilobytes (~200kB for a non-modular db1200 devboard build).

The enormous size difference is probably 99% due to atomic and bitops
which exist in LL/SC and non-LL/SC versions and without the header gcc
will expand the inline function each time.  That will hurt, also
performance.  Also the big size difference suggests that we may want to
outline some or all of these functions.

  Ralf

Re: [PATCH 2/2] Alchemy: provide cpu feature overrides.

[Manuel Lauss]

On Tue, 23 Dec 2008 15:39:09 +0100
Ralf Baechle <ralf@linux-mips.org> wrote:

> On Mon, Dec 22, 2008 at 08:21:08PM +0100, Manuel Lauss wrote:
> 
> > Add cpu feature override constants for Alchemy.
> > 
> > Code generated for Alchemy does not use all MIPS32r1 features.  Add cpu
> > feature overrides tailored for Alchemy chips and help GCC create better
> > code.  As a nice sideeffect the size of the resulting kernel is reduced
> > by a few kilobytes (~200kB for a non-modular db1200 devboard build).
> 
> The enormous size difference is probably 99% due to atomic and bitops
> which exist in LL/SC and non-LL/SC versions and without the header gcc
> will expand the inline function each time.  That will hurt, also
> performance.  Also the big size difference suggests that we may want to
> outline some or all of these functions.

You are of course correct:

   text    data     bss     dec     hex filename                                                                                                                
3890074  124400  436528 4451002  43eaba vmlinux                                                                                                                 
3890070  124400  436528 4450998  43eab6 vmlinux+mips32r1
3690742  124396  436528 4251666  40e012 vmlinux++llsc
3666386  124332  436528 4227246  4080ae vmlinux+++all

-- ml.

Re: [PATCH 2/2] Alchemy: provide cpu feature overrides.

[Ralf Baechle]

On Tue, Dec 23, 2008 at 05:29:54PM +0100, Manuel Lauss wrote:

> > > Code generated for Alchemy does not use all MIPS32r1 features.  Add cpu
> > > feature overrides tailored for Alchemy chips and help GCC create better
> > > code.  As a nice sideeffect the size of the resulting kernel is reduced
> > > by a few kilobytes (~200kB for a non-modular db1200 devboard build).
> > 
> > The enormous size difference is probably 99% due to atomic and bitops
> > which exist in LL/SC and non-LL/SC versions and without the header gcc
> > will expand the inline function each time.  That will hurt, also
> > performance.  Also the big size difference suggests that we may want to
> > outline some or all of these functions.
> 
> You are of course correct:
> 
>    text    data     bss     dec     hex filename                                                                                                                
> 3890074  124400  436528 4451002  43eaba vmlinux
> 3890070  124400  436528 4450998  43eab6 vmlinux+mips32r1
> 3690742  124396  436528 4251666  40e012 vmlinux++llsc
> 3666386  124332  436528 4227246  4080ae vmlinux+++all

Thanks for the numbers.  I'm a little surprised that there are only
4 byte difference between the first two variants?

  Ralf

Re: [PATCH 2/2] Alchemy: provide cpu feature overrides.

[Manuel Lauss]

On Tue, 23 Dec 2008 17:37:03 +0100
Ralf Baechle <ralf@linux-mips.org> wrote:

> On Tue, Dec 23, 2008 at 05:29:54PM +0100, Manuel Lauss wrote:
> 
> > > > Code generated for Alchemy does not use all MIPS32r1 features.  Add cpu
> > > > feature overrides tailored for Alchemy chips and help GCC create better
> > > > code.  As a nice sideeffect the size of the resulting kernel is reduced
> > > > by a few kilobytes (~200kB for a non-modular db1200 devboard build).
> > > 
> > > The enormous size difference is probably 99% due to atomic and bitops
> > > which exist in LL/SC and non-LL/SC versions and without the header gcc
> > > will expand the inline function each time.  That will hurt, also
> > > performance.  Also the big size difference suggests that we may want to
> > > outline some or all of these functions.
> > 
> > You are of course correct:
> > 
> >    text    data     bss     dec     hex filename                                                                                                                
> > 3890074  124400  436528 4451002  43eaba vmlinux
> > 3890070  124400  436528 4450998  43eab6 vmlinux+mips32r1
> > 3690742  124396  436528 4251666  40e012 vmlinux++llsc
> > 3666386  124332  436528 4227246  4080ae vmlinux+++all
> 
> Thanks for the numbers.  I'm a little surprised that there are only
> 4 byte difference between the first two variants?
> 
>   Ralf

Sorry, error on my side: one has to define constants for all
mipsXXrY variants to get a good result:

3890074  124400  436528 4451002  43eaba vmlinux
3880034  124400  436528 4440962  43c382 vmlinux+mips_r
3690742  124396  436528 4251666  40e012 vmlinux++llsc
3666386  124332  436528 4227246  4080ae vmlinux+++all

Happy holidays,
	Manuel Lauss.