* [PATCH] DSPBRIDGE: Remove SEEK_* redefinitions
@ 2009-03-04 18:11 Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Removes wrappers funtions of readl and writel Fernando Guzman Lugo
0 siblings, 1 reply; 8+ messages in thread
From: Fernando Guzman Lugo @ 2009-03-04 18:11 UTC (permalink / raw)
To: leed.aguilar, vikram.pandita, h-kanigeri2, linux-omap
Cc: Fernando Guzman Lugo
This patch removes the SEEK_* redefinitions in host_os.h
Signed-off-by: Guzman Lugo Fernando <x0095840@ti.com>
---
arch/arm/plat-omap/include/dspbridge/host_os.h | 6 ------
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/host_os.h b/arch/arm/plat-omap/include/dspbridge/host_os.h
index ff49e0d..9245eea
--- a/arch/arm/plat-omap/include/dspbridge/host_os.h
+++ b/arch/arm/plat-omap/include/dspbridge/host_os.h
@@ -60,12 +60,6 @@
#include <asm/cacheflush.h>
#include <linux/dma-mapping.h>
-/* ----------------------------------- Macros */
-
-#define SEEK_SET 0 /* Seek from beginning of file. */
-#define SEEK_CUR 1 /* Seek from current position. */
-#define SEEK_END 2 /* Seek from end of file. */
-
/* TODO -- Remove, once BP defines them */
#define INT_MAIL_MPU_IRQ 26
#define INT_DSP_MMU_IRQ 28
--
1.5.6.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] DSPBRIDGE: Removes wrappers funtions of readl and writel
2009-03-04 18:11 [PATCH] DSPBRIDGE: Remove SEEK_* redefinitions Fernando Guzman Lugo
@ 2009-03-04 18:11 ` Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Change address resources to void __iomem * Fernando Guzman Lugo
0 siblings, 1 reply; 8+ messages in thread
From: Fernando Guzman Lugo @ 2009-03-04 18:11 UTC (permalink / raw)
To: leed.aguilar, vikram.pandita, h-kanigeri2, linux-omap
Cc: Fernando Guzman Lugo
This patch change the call to RD_MEM_32_VOLATILE and
WR_MEM_32_VOLATILE with __raw_readl and __raw_writel
Signed-off-by: Guzman Lugo Fernando <x0095840@ti.com>
---
drivers/dsp/bridge/hw/MLBRegAcM.h | 41 ++++----
drivers/dsp/bridge/hw/MMURegAcM.h | 66 ++++++------
drivers/dsp/bridge/hw/PRCMRegAcM.h | 181 +++++++++++++++++-----------------
drivers/dsp/bridge/hw/hw_dspssC64P.c | 5 +-
4 files changed, 148 insertions(+), 145 deletions(-)
diff --git a/drivers/dsp/bridge/hw/MLBRegAcM.h b/drivers/dsp/bridge/hw/MLBRegAcM.h
index 747a2e1..d215ec5
--- a/drivers/dsp/bridge/hw/MLBRegAcM.h
+++ b/drivers/dsp/bridge/hw/MLBRegAcM.h
@@ -18,6 +18,7 @@
#define _MLB_REG_ACM_H
#include <GlobalTypes.h>
+#include <linux/io.h>
#include <EasiGlobal.h>
#include "MLBAccInt.h"
@@ -25,7 +26,7 @@
#define MLBMAILBOX_SYSCONFIGReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+ \
+ __raw_readl(((baseAddress))+ \
MLB_MAILBOX_SYSCONFIG_OFFSET))
@@ -34,13 +35,13 @@
const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32);\
- WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
+ __raw_writel(newValue, ((baseAddress))+offset);\
}
#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32),\
- (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
+ (((__raw_readl((((u32)(baseAddress))+\
(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))
@@ -49,7 +50,7 @@
#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(baseAddress, value)\
{\
const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress)) +\
+ register u32 data = __raw_readl(((u32)(baseAddress)) +\
offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32);\
@@ -57,7 +58,7 @@
newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -65,20 +66,20 @@
{\
const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
register u32 data =\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32);\
data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\
newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\
newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32),\
- (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
+ (((__raw_readl((((u32)(baseAddress))+\
(MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))
@@ -88,20 +89,20 @@
{\
const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
register u32 data =\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32);\
data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\
newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\
newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
#define MLBMAILBOX_SYSSTATUSResetDoneRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32),\
- (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
+ (((__raw_readl((((u32)(baseAddress))+\
(MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\
MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))
@@ -109,7 +110,7 @@
#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(baseAddress, bank)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
+ __raw_readl(((baseAddress))+\
(MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
MLB_MAILBOX_MESSAGE___0_15_OFFSET+(\
(bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP))))
@@ -122,14 +123,14 @@
((bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32);\
- WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
+ __raw_writel(newValue, ((baseAddress))+offset);\
}
#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(baseAddress, bank)\
(_DEBUG_LEVEL_1_EASI(\
EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
+ __raw_readl(((u32)(baseAddress))+\
(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP))))
@@ -138,7 +139,7 @@
#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress, bank)\
(_DEBUG_LEVEL_1_EASI(\
EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32),\
- (((RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
+ (((__raw_readl(((baseAddress))+\
(MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\
@@ -149,7 +150,7 @@
#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(baseAddress, bank)\
(_DEBUG_LEVEL_1_EASI(\
EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32),\
- (((RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
+ (((__raw_readl(((baseAddress))+\
(MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\
MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+\
((bank)*MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\
@@ -159,7 +160,7 @@
#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(baseAddress, bank)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
+ __raw_readl(((baseAddress))+\
(MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\
((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP))))
@@ -172,13 +173,13 @@
((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32);\
- WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
+ __raw_writel(newValue, ((baseAddress))+offset);\
}
#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(baseAddress, bank)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
+ __raw_readl(((baseAddress))+\
(MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\
((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP))))
@@ -191,7 +192,7 @@
((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32);\
- WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
+ __raw_writel(newValue, ((baseAddress))+offset);\
}
diff --git a/drivers/dsp/bridge/hw/MMURegAcM.h b/drivers/dsp/bridge/hw/MMURegAcM.h
index a130b1a..34b0c49
--- a/drivers/dsp/bridge/hw/MMURegAcM.h
+++ b/drivers/dsp/bridge/hw/MMURegAcM.h
@@ -19,7 +19,7 @@
#define _MMU_REG_ACM_H
#include <GlobalTypes.h>
-
+#include <linux/io.h>
#include <EasiGlobal.h>
#include "MMUAccInt.h"
@@ -29,40 +29,40 @@
#define MMUMMU_SYSCONFIGReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGReadRegister32),\
- RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_SYSCONFIG_OFFSET))
+ __raw_readl((baseAddress)+MMU_MMU_SYSCONFIG_OFFSET))
#define MMUMMU_SYSCONFIGIdleModeWrite32(baseAddress, value)\
{\
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGIdleModeWrite32);\
data &= ~(MMU_MMU_SYSCONFIG_IdleMode_MASK);\
newValue <<= MMU_MMU_SYSCONFIG_IdleMode_OFFSET;\
newValue &= MMU_MMU_SYSCONFIG_IdleMode_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
+ __raw_writel(newValue, baseAddress+offset);\
}
#define MMUMMU_SYSCONFIGAutoIdleWrite32(baseAddress, value)\
{\
const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGAutoIdleWrite32);\
data &= ~(MMU_MMU_SYSCONFIG_AutoIdle_MASK);\
newValue <<= MMU_MMU_SYSCONFIG_AutoIdle_OFFSET;\
newValue &= MMU_MMU_SYSCONFIG_AutoIdle_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
+ __raw_writel(newValue, baseAddress+offset);\
}
#define MMUMMU_IRQSTATUSReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSReadRegister32),\
- RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_IRQSTATUS_OFFSET))
+ __raw_readl((baseAddress)+MMU_MMU_IRQSTATUS_OFFSET))
#define MMUMMU_IRQSTATUSWriteRegister32(baseAddress, value)\
@@ -70,13 +70,13 @@
const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSWriteRegister32);\
- WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
#define MMUMMU_IRQENABLEReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEReadRegister32),\
- RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_IRQENABLE_OFFSET))
+ __raw_readl((baseAddress)+MMU_MMU_IRQENABLE_OFFSET))
#define MMUMMU_IRQENABLEWriteRegister32(baseAddress, value)\
@@ -84,20 +84,20 @@
const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEWriteRegister32);\
- WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
#define MMUMMU_WALKING_STTWLRunningRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_WALKING_STTWLRunningRead32),\
- (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_WALKING_ST_OFFSET))))\
+ (((__raw_readl(((baseAddress)+(MMU_MMU_WALKING_ST_OFFSET))))\
& MMU_MMU_WALKING_ST_TWLRunning_MASK) >>\
MMU_MMU_WALKING_ST_TWLRunning_OFFSET))
#define MMUMMU_CNTLTWLEnableRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableRead32),\
- (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_CNTL_OFFSET)))) &\
+ (((__raw_readl(((baseAddress)+(MMU_MMU_CNTL_OFFSET)))) &\
MMU_MMU_CNTL_TWLEnable_MASK) >>\
MMU_MMU_CNTL_TWLEnable_OFFSET))
@@ -105,34 +105,34 @@
#define MMUMMU_CNTLTWLEnableWrite32(baseAddress, value)\
{\
const u32 offset = MMU_MMU_CNTL_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableWrite32);\
data &= ~(MMU_MMU_CNTL_TWLEnable_MASK);\
newValue <<= MMU_MMU_CNTL_TWLEnable_OFFSET;\
newValue &= MMU_MMU_CNTL_TWLEnable_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
+ __raw_writel(newValue, baseAddress+offset);\
}
#define MMUMMU_CNTLMMUEnableWrite32(baseAddress, value)\
{\
const u32 offset = MMU_MMU_CNTL_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLMMUEnableWrite32);\
data &= ~(MMU_MMU_CNTL_MMUEnable_MASK);\
newValue <<= MMU_MMU_CNTL_MMUEnable_OFFSET;\
newValue &= MMU_MMU_CNTL_MMUEnable_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
+ __raw_writel(newValue, baseAddress+offset);\
}
#define MMUMMU_FAULT_ADReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FAULT_ADReadRegister32),\
- RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_FAULT_AD_OFFSET))
+ __raw_readl((baseAddress)+MMU_MMU_FAULT_AD_OFFSET))
#define MMUMMU_TTBWriteRegister32(baseAddress, value)\
@@ -140,13 +140,13 @@
const u32 offset = MMU_MMU_TTB_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_TTBWriteRegister32);\
- WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
#define MMUMMU_LOCKReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKReadRegister32),\
- RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_LOCK_OFFSET))
+ __raw_readl((baseAddress)+MMU_MMU_LOCK_OFFSET))
#define MMUMMU_LOCKWriteRegister32(baseAddress, value)\
@@ -154,13 +154,13 @@
const u32 offset = MMU_MMU_LOCK_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKWriteRegister32);\
- WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
#define MMUMMU_LOCKBaseValueRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueRead32),\
- (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
+ (((__raw_readl(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
MMU_MMU_LOCK_BaseValue_MASK) >>\
MMU_MMU_LOCK_BaseValue_OFFSET))
@@ -168,20 +168,20 @@
#define MMUMMU_LOCKBaseValueWrite32(baseAddress, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueWrite32);\
data &= ~(MMU_MMU_LOCK_BaseValue_MASK);\
newValue <<= MMU_MMU_LOCK_BaseValue_OFFSET;\
newValue &= MMU_MMU_LOCK_BaseValue_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
+ __raw_writel(newValue, baseAddress+offset);\
}
#define MMUMMU_LOCKCurrentVictimRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimRead32),\
- (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
+ (((__raw_readl(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
MMU_MMU_LOCK_CurrentVictim_MASK) >>\
MMU_MMU_LOCK_CurrentVictim_OFFSET))
@@ -189,14 +189,14 @@
#define MMUMMU_LOCKCurrentVictimWrite32(baseAddress, value)\
{\
const u32 offset = MMU_MMU_LOCK_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimWrite32);\
data &= ~(MMU_MMU_LOCK_CurrentVictim_MASK);\
newValue <<= MMU_MMU_LOCK_CurrentVictim_OFFSET;\
newValue &= MMU_MMU_LOCK_CurrentVictim_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
+ __raw_writel(newValue, baseAddress+offset);\
}
@@ -209,7 +209,7 @@
#define MMUMMU_LD_TLBReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBReadRegister32),\
- RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_LD_TLB_OFFSET))
+ __raw_readl((baseAddress)+MMU_MMU_LD_TLB_OFFSET))
#define MMUMMU_LD_TLBWriteRegister32(baseAddress, value)\
@@ -217,7 +217,7 @@
const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBWriteRegister32);\
- WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
@@ -226,7 +226,7 @@
const u32 offset = MMU_MMU_CAM_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CAMWriteRegister32);\
- WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
@@ -235,21 +235,21 @@
const u32 offset = MMU_MMU_RAM_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_RAMWriteRegister32);\
- WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
#define MMUMMU_GFLUSHGlobalFlushWrite32(baseAddress, value)\
{\
const u32 offset = MMU_MMU_GFLUSH_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_GFLUSHGlobalFlushWrite32);\
data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\
newValue <<= MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\
newValue &= MMU_MMU_GFLUSH_GlobalFlush_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
+ __raw_writel(newValue, baseAddress+offset);\
}
@@ -258,7 +258,7 @@
const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
register u32 newValue = (value);\
_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FLUSH_ENTRYWriteRegister32);\
- WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
diff --git a/drivers/dsp/bridge/hw/PRCMRegAcM.h b/drivers/dsp/bridge/hw/PRCMRegAcM.h
index 91cb33c..c0db1fe
--- a/drivers/dsp/bridge/hw/PRCMRegAcM.h
+++ b/drivers/dsp/bridge/hw/PRCMRegAcM.h
@@ -18,6 +18,7 @@
#define _PRCM_REG_ACM_H
#include <GlobalTypes.h>
+#include <linux/io.h>
#include <EasiGlobal.h>
@@ -31,37 +32,37 @@
const u32 newValue = \
(u32)PRCMPRCM_CLKCFG_CTRLValid_configClk_valid <<\
PRCM_PRCM_CLKCFG_CTRL_Valid_config_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(\
EASIL1_PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32);\
data &= ~(PRCM_PRCM_CLKCFG_CTRL_Valid_config_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
#define CM_FCLKEN_PERReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_FCLKEN_PER_OFFSET))
+ __raw_readl(((u32)(baseAddress))+CM_FCLKEN_PER_OFFSET))
#define CM_ICLKEN_PERReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_ICLKEN_PER_OFFSET))
+ __raw_readl(((u32)(baseAddress))+CM_ICLKEN_PER_OFFSET))
#define CM_FCLKEN_PER_GPT5WriteRegister32(baseAddress,value)\
{\
const u32 offset = CM_FCLKEN_PER_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32);\
data &= ~(CM_FCLKEN_PER_GPT5_MASK);\
newValue <<= CM_FCLKEN_PER_GPT5_OFFSET;\
newValue &= CM_FCLKEN_PER_GPT5_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
+ __raw_writel(newValue, ((u32)(baseAddress))+offset);\
}
@@ -69,14 +70,14 @@
{\
const u32 offset = CM_FCLKEN_PER_OFFSET;\
register u32 data =\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32);\
data &= ~(CM_FCLKEN_PER_GPT6_MASK);\
newValue <<= CM_FCLKEN_PER_GPT6_OFFSET;\
newValue &= CM_FCLKEN_PER_GPT6_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
+ __raw_writel(newValue, ((u32)(baseAddress))+offset);\
}
@@ -84,14 +85,14 @@
{\
const u32 offset = CM_ICLKEN_PER_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32);\
data &= ~(CM_ICLKEN_PER_GPT5_MASK);\
newValue <<= CM_ICLKEN_PER_GPT5_OFFSET;\
newValue &= CM_ICLKEN_PER_GPT5_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
+ __raw_writel(newValue, ((u32)(baseAddress))+offset);\
}
@@ -99,34 +100,34 @@
{\
const u32 offset = CM_ICLKEN_PER_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32);\
data &= ~(CM_ICLKEN_PER_GPT6_MASK);\
newValue <<= CM_ICLKEN_PER_GPT6_OFFSET;\
newValue &= CM_ICLKEN_PER_GPT6_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
+ __raw_writel(newValue, ((u32)(baseAddress))+offset);\
}
#define CM_FCLKEN1_COREReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_FCLKEN1_CORE_OFFSET))
+ __raw_readl(((u32)(baseAddress))+CM_FCLKEN1_CORE_OFFSET))
#define PRCMCM_FCLKEN1_COREEN_GPT8Write32(baseAddress,value)\
{\
const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT8Write32);\
data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK);\
newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT8_OFFSET;\
newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -134,34 +135,34 @@
{\
const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT7Write32);\
data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK);\
newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT7_OFFSET;\
newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
#define CM_ICLKEN1_COREReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_ICLKEN1_CORE_OFFSET))
+ __raw_readl(((u32)(baseAddress))+CM_ICLKEN1_CORE_OFFSET))
#define CM_ICLKEN1_COREEN_MAILBOXESWrite32(baseAddress, value)\
{\
const u32 offset = CM_ICLKEN1_CORE_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_MAILBOXESWrite32);\
data &= ~(CM_ICLKEN1_CORE_EN_MAILBOXES_MASK);\
newValue <<= CM_ICLKEN1_CORE_EN_MAILBOXES_OFFSET;\
newValue &= CM_ICLKEN1_CORE_EN_MAILBOXES_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -169,14 +170,14 @@
{\
const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT8Write32);\
data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK);\
newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT8_OFFSET;\
newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -184,14 +185,14 @@
{\
const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET;\
register u32 data =\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT7Write32);\
data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK);\
newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT7_OFFSET;\
newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -200,11 +201,11 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT832k <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -213,11 +214,11 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Sys <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -226,11 +227,11 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Ext <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -239,11 +240,11 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT732k <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -252,11 +253,11 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Sys <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -265,11 +266,11 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Ext <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -278,11 +279,11 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Sys <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -291,11 +292,11 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Ext <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -304,11 +305,11 @@
const u32 offset = CM_CLKSEL_PER_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k <<\
CM_CLKSEL_PER_GPT5_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT5Write32k32);\
data &= ~(CM_CLKSEL_PER_GPT5_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -317,11 +318,11 @@
const u32 offset = CM_CLKSEL_PER_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k <<\
CM_CLKSEL_PER_GPT6_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT6Write32k32);\
data &= ~(CM_CLKSEL_PER_GPT6_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -330,11 +331,11 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Sys <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
@@ -343,17 +344,17 @@
const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Ext <<\
PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((u32)(baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32);\
data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (u32)(baseAddress)+offset);\
}
#define PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32),\
- (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
+ (((__raw_readl((((u32)(baseAddress))+\
(PRCM_CM_CLKSEL1_PLL_OFFSET)))) &\
PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_MASK) >>\
PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_OFFSET))
@@ -363,14 +364,14 @@
{\
const u32 offset = CM_FCLKEN_IVA2_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN_DSPEN_DSPWrite32);\
data &= ~(CM_FCLKEN_IVA2_EN_MASK);\
newValue <<= CM_FCLKEN_IVA2_EN_OFFSET;\
newValue &= CM_FCLKEN_IVA2_EN_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -378,25 +379,25 @@
{\
const u32 offset = PRCM_CM_ICLKEN_DSP_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32);\
data &= ~(PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK);\
newValue <<= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_OFFSET;\
newValue &= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
#define PRCMCM_IDLEST_DSPReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_CM_IDLEST_DSP_OFFSET))
+ __raw_readl(((u32)(baseAddress))+PRCM_CM_IDLEST_DSP_OFFSET))
#define PRCMCM_IDLEST_DSPST_IPIRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_IPIRead32),\
- (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
+ (((__raw_readl((((u32)(baseAddress))+\
(PRCM_CM_IDLEST_DSP_OFFSET)))) &\
PRCM_CM_IDLEST_DSP_ST_IPI_MASK) >>\
PRCM_CM_IDLEST_DSP_ST_IPI_OFFSET))
@@ -404,7 +405,7 @@
#define PRM_IDLEST_IVA2ST_IVA2Read32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_DSPRead32),\
- (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
+ (((__raw_readl((((u32)(baseAddress))+\
(CM_IDLEST_IVA2_OFFSET)))) &\
CM_IDLEST_IVA2_ST_IVA2_MASK) >>\
CM_IDLEST_IVA2_ST_IVA2_OFFSET))
@@ -414,14 +415,14 @@
{\
const u32 offset = PRCM_CM_AUTOIDLE_DSP_OFFSET;\
register u32 data =\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32);\
data &= ~(PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK);\
newValue <<= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_OFFSET;\
newValue &= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -429,14 +430,14 @@
{\
const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPSYNC_DSPWrite32);\
data &= ~(PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK);\
newValue <<= PRCM_CM_CLKSEL_DSP_SYNC_DSP_OFFSET;\
newValue &= PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -444,14 +445,14 @@
{\
const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32);\
data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK);\
newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_OFFSET;\
newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -459,14 +460,14 @@
{\
const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32);\
data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK);\
newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_OFFSET;\
newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -474,20 +475,20 @@
{\
const u32 offset = PRCM_CM_CLKSTCTRL_IVA2_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_IVA2WriteRegister32);\
data &= ~(CM_CLKSTCTRL_IVA2_MASK);\
newValue <<= CM_CLKSTCTRL_IVA2_OFFSET;\
newValue &= CM_CLKSTCTRL_IVA2_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
#define PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32),\
- (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
+ (((__raw_readl((((u32)(baseAddress))+\
(PRCM_CM_CLKSTCTRL_DSP_OFFSET)))) &\
PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK) >>\
PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET))
@@ -497,34 +498,34 @@
{\
const u32 offset = PRCM_CM_CLKSTCTRL_DSP_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32);\
data &= ~(PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK);\
newValue <<= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET;\
newValue &= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
#define PRCMRM_RSTCTRL_DSPReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_RM_RSTCTRL_DSP_OFFSET))
+ __raw_readl(((baseAddress))+PRCM_RM_RSTCTRL_DSP_OFFSET))
#define PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress,value)\
{\
const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\
register u32 data =\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\
data &= ~(PRM_RSTCTRL_IVA2_RST1_MASK);\
newValue <<= PRM_RSTCTRL_IVA2_RST1_OFFSET;\
newValue &= PRM_RSTCTRL_IVA2_RST1_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
@@ -532,14 +533,14 @@
{\
const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\
register u32 data =\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\
data &= ~(PRM_RSTCTRL_IVA2_RST2_MASK);\
newValue <<= PRM_RSTCTRL_IVA2_RST2_OFFSET;\
newValue &= PRM_RSTCTRL_IVA2_RST2_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
@@ -547,20 +548,20 @@
{\
const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\
register u32 data =\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\
data &= ~(PRM_RSTCTRL_IVA2_RST3_MASK);\
newValue <<= PRM_RSTCTRL_IVA2_RST3_OFFSET;\
newValue &= PRM_RSTCTRL_IVA2_RST3_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (baseAddress)+offset);\
}
#define PRCMRM_RSTST_DSPReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_RM_RSTST_DSP_OFFSET))
+ __raw_readl(((baseAddress))+PRCM_RM_RSTST_DSP_OFFSET))
#define PRCMRM_RSTST_DSPWriteRegister32(baseAddress,value)\
@@ -568,7 +569,7 @@
const u32 offset = PRCM_RM_RSTST_DSP_OFFSET;\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPWriteRegister32);\
- WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
+ __raw_writel(newValue, ((u32)(baseAddress))+offset);\
}
@@ -576,14 +577,14 @@
{\
const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET;\
register u32 data = \
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
+ __raw_readl(((u32)(baseAddress))+offset);\
register u32 newValue = ((u32)(value));\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPForceStateWrite32);\
data &= ~(PRCM_PM_PWSTCTRL_DSP_ForceState_MASK);\
newValue <<= PRCM_PM_PWSTCTRL_DSP_ForceState_OFFSET;\
newValue &= PRCM_PM_PWSTCTRL_DSP_ForceState_MASK;\
newValue |= data;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
+ __raw_writel(newValue, (u32)(baseAddress)+offset);\
}
@@ -592,11 +593,11 @@
const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET;\
const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateON <<\
PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32);\
data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (baseAddress)+offset);\
}
@@ -605,11 +606,11 @@
const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET;\
const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateOFF <<\
PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32);\
data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (baseAddress)+offset);\
}
@@ -618,27 +619,27 @@
const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET;\
const u32 newValue = (u32)PRCMPM_PWSTCTRL_DSPPowerStateRET <<\
PRCM_PM_PWSTCTRL_DSP_PowerState_OFFSET;\
- register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
+ register u32 data = __raw_readl((baseAddress)+offset);\
_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32);\
data &= ~(PRCM_PM_PWSTCTRL_DSP_PowerState_MASK);\
data |= newValue;\
- WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
+ __raw_writel(data, (baseAddress)+offset);\
}
#define PRCMPM_PWSTST_DSPReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_PM_PWSTST_DSP_OFFSET))
+ __raw_readl(((u32)(baseAddress))+PRCM_PM_PWSTST_DSP_OFFSET))
#define PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2ReadRegister32),\
- RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_PM_PWSTST_IVA2_OFFSET))
+ __raw_readl((baseAddress) + PRCM_PM_PWSTST_IVA2_OFFSET))
#define PRCMPM_PWSTST_DSPInTransitionRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPInTransitionRead32),\
- (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
+ (((__raw_readl((((u32)(baseAddress))+\
(PRCM_PM_PWSTST_DSP_OFFSET)))) &\
PRCM_PM_PWSTST_DSP_InTransition_MASK) >>\
PRCM_PM_PWSTST_DSP_InTransition_OFFSET))
@@ -646,7 +647,7 @@
#define PRCMPM_PWSTST_IVA2InTransitionRead32(baseAddress)\
(_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2InTransitionRead32),\
- (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
+ (((__raw_readl((((baseAddress))+\
(PRCM_PM_PWSTST_IVA2_OFFSET)))) &\
PRCM_PM_PWSTST_IVA2_InTransition_MASK) >>\
PRCM_PM_PWSTST_IVA2_InTransition_OFFSET))
diff --git a/drivers/dsp/bridge/hw/hw_dspssC64P.c b/drivers/dsp/bridge/hw/hw_dspssC64P.c
index 029aff5..0d0d45c
--- a/drivers/dsp/bridge/hw/hw_dspssC64P.c
+++ b/drivers/dsp/bridge/hw/hw_dspssC64P.c
@@ -27,6 +27,7 @@
/* PROJECT SPECIFIC INCLUDE FILES */
#include <GlobalTypes.h>
+#include <linux/io.h>
#include <hw_defs.h>
#include <hw_dspssC64P.h>
#include <IVA2RegAcM.h>
@@ -43,13 +44,13 @@ HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
/* if Boot mode it DIRECT BOOT, check that the bootAddress is
* aligned to atleast 1K :: TODO */
- WR_MEM_32_VOLATILE((baseAddress) + offset, bootMode);
+ __raw_writel(bootMode, (baseAddress) + offset);
offset = SYSC_IVA2BOOTADDR_OFFSET;
alignedBootAddr = bootAddress & SYSC_IVA2BOOTADDR_MASK;
- WR_MEM_32_VOLATILE((baseAddress) + offset, alignedBootAddr);
+ __raw_writel(alignedBootAddr, (baseAddress) + offset);
return status;
}
--
1.5.6.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] DSPBRIDGE: Change address resources to void __iomem *
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Removes wrappers funtions of readl and writel Fernando Guzman Lugo
@ 2009-03-04 18:11 ` Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h Fernando Guzman Lugo
2009-03-05 10:22 ` [PATCH] DSPBRIDGE: Change address resources to void __iomem * Ameya Palande
0 siblings, 2 replies; 8+ messages in thread
From: Fernando Guzman Lugo @ 2009-03-04 18:11 UTC (permalink / raw)
To: leed.aguilar, vikram.pandita, h-kanigeri2, linux-omap
Cc: Fernando Guzman Lugo
This patch changes address resources to void __iomem *
Signed-off-by: Guzman Lugo Fernando <x0095840@ti.com>
---
arch/arm/plat-omap/include/dspbridge/cfgdefs.h | 16 ++++----
drivers/dsp/bridge/hw/hw_dspssC64P.c | 2 +-
drivers/dsp/bridge/hw/hw_dspssC64P.h | 2 +-
drivers/dsp/bridge/hw/hw_mbox.c | 30 +++++++------
drivers/dsp/bridge/hw/hw_mbox.h | 18 ++++----
drivers/dsp/bridge/hw/hw_mmu.c | 43 ++++++++++----------
drivers/dsp/bridge/hw/hw_mmu.h | 30 +++++++-------
drivers/dsp/bridge/hw/hw_prcm.c | 26 ++++++------
drivers/dsp/bridge/hw/hw_prcm.h | 17 ++++----
drivers/dsp/bridge/rmgr/drv.c | 52 ++++++++++++------------
drivers/dsp/bridge/rmgr/node.c | 2 +-
drivers/dsp/bridge/wmd/_tiomap.h | 2 +-
drivers/dsp/bridge/wmd/tiomap3430.c | 47 ++++++++++-----------
13 files changed, 145 insertions(+), 142 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
index ca96b3c..e7633b5
--- a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
+++ b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
@@ -96,14 +96,14 @@
u32 dwChnlOffset;
u32 dwChnlBufSize;
u32 dwNumChnls;
- u32 dwPrmBase;
- u32 dwCmBase;
- u32 dwPerBase;
- u32 dwWdTimerDspBase;
- u32 dwMboxBase;
- u32 dwDmmuBase;
- u32 dwDipiBase;
- u32 dwSysCtrlBase;
+ void __iomem *dwPrmBase;
+ void __iomem *dwCmBase;
+ void __iomem *dwPerBase;
+ void __iomem *dwWdTimerDspBase;
+ void __iomem *dwMboxBase;
+ void __iomem *dwDmmuBase;
+ u32 *dwDipiBase;
+ void __iomem *dwSysCtrlBase;
} ;
struct CFG_DSPMEMDESC {
diff --git a/drivers/dsp/bridge/hw/hw_dspssC64P.c b/drivers/dsp/bridge/hw/hw_dspssC64P.c
index 0d0d45c..6aac57d
--- a/drivers/dsp/bridge/hw/hw_dspssC64P.c
+++ b/drivers/dsp/bridge/hw/hw_dspssC64P.c
@@ -34,7 +34,7 @@
#include <IPIAccInt.h>
/* HW FUNCTIONS */
-HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
+HW_STATUS HW_DSPSS_BootModeSet(const void __iomem *baseAddress,
enum HW_DSPSYSC_BootMode_t bootMode,
const u32 bootAddress)
{
diff --git a/drivers/dsp/bridge/hw/hw_dspssC64P.h b/drivers/dsp/bridge/hw/hw_dspssC64P.h
index 493effd..50f9af4
--- a/drivers/dsp/bridge/hw/hw_dspssC64P.h
+++ b/drivers/dsp/bridge/hw/hw_dspssC64P.h
@@ -41,7 +41,7 @@
#define HW_DSP_IDLEBOOT_ADDR 0x007E0000
- extern HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
+ extern HW_STATUS HW_DSPSS_BootModeSet(const void __iomem *baseAddress,
enum HW_DSPSYSC_BootMode_t bootMode,
const u32 bootAddress);
diff --git a/drivers/dsp/bridge/hw/hw_mbox.c b/drivers/dsp/bridge/hw/hw_mbox.c
index bc61d64..93fa51e
--- a/drivers/dsp/bridge/hw/hw_mbox.c
+++ b/drivers/dsp/bridge/hw/hw_mbox.c
@@ -36,7 +37,7 @@
struct MAILBOX_CONTEXT mboxsetting = {0x4, 0x1, 0x1};
/* Saves the mailbox context */
-HW_STATUS HW_MBOX_saveSettings(u32 baseAddress)
+HW_STATUS HW_MBOX_saveSettings(void __iomem *baseAddress)
{
HW_STATUS status = RET_OK;
@@ -50,7 +51,7 @@ HW_STATUS HW_MBOX_saveSettings(u32 baseAddress)
}
/* Restores the mailbox context */
-HW_STATUS HW_MBOX_restoreSettings(u32 baseAddress)
+HW_STATUS HW_MBOX_restoreSettings(void __iomem *baseAddress)
{
HW_STATUS status = RET_OK;
/* Restor IRQ enable status */
@@ -65,8 +66,8 @@ HW_STATUS HW_MBOX_restoreSettings(u32 baseAddress)
/* Reads a u32 from the sub module message box Specified. if there are no
* messages in the mailbox then and error is returned. */
-HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
- u32 *const pReadValue)
+HW_STATUS HW_MBOX_MsgRead(const void __iomem *baseAddress,
+ const HW_MBOX_Id_t mailBoxId, u32 *const pReadValue)
{
HW_STATUS status = RET_OK;
@@ -86,8 +87,8 @@ HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
}
/* Writes a u32 from the sub module message box Specified. */
-HW_STATUS HW_MBOX_MsgWrite(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
- const u32 writeValue)
+HW_STATUS HW_MBOX_MsgWrite(const void __iomem *baseAddress,
+ const HW_MBOX_Id_t mailBoxId, const u32 writeValue)
{
HW_STATUS status = RET_OK;
@@ -105,8 +106,8 @@ HW_STATUS HW_MBOX_MsgWrite(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
}
/* Reads the full status register for mailbox. */
-HW_STATUS HW_MBOX_IsFull(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
- u32 *const pIsFull)
+HW_STATUS HW_MBOX_IsFull(const void __iomem *baseAddress,
+ const HW_MBOX_Id_t mailBoxId, u32 *const pIsFull)
{
HW_STATUS status = RET_OK;
u32 fullStatus;
@@ -130,8 +131,8 @@ HW_STATUS HW_MBOX_IsFull(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
}
/* Gets number of messages in a specified mailbox. */
-HW_STATUS HW_MBOX_NumMsgGet(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
- u32 *const pNumMsg)
+HW_STATUS HW_MBOX_NumMsgGet(const void __iomem *baseAddress,
+ const HW_MBOX_Id_t mailBoxId, u32 *const pNumMsg)
{
HW_STATUS status = RET_OK;
@@ -152,7 +153,7 @@ HW_STATUS HW_MBOX_NumMsgGet(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
}
/* Enables the specified IRQ. */
-HW_STATUS HW_MBOX_EventEnable(const u32 baseAddress,
+HW_STATUS HW_MBOX_EventEnable(const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId,
const HW_MBOX_UserId_t userId,
const u32 events)
@@ -192,7 +193,7 @@ HW_STATUS HW_MBOX_EventEnable(const u32 baseAddress,
}
/* Disables the specified IRQ. */
-HW_STATUS HW_MBOX_EventDisable(const u32 baseAddress,
+HW_STATUS HW_MBOX_EventDisable(const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId,
const HW_MBOX_UserId_t userId,
const u32 events)
@@ -226,8 +227,9 @@ HW_STATUS HW_MBOX_EventDisable(const u32 baseAddress,
}
/* Sets the status of the specified IRQ. */
-HW_STATUS HW_MBOX_EventAck(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
- const HW_MBOX_UserId_t userId, const u32 event)
+HW_STATUS HW_MBOX_EventAck(const void __iomem *baseAddress,
+ const HW_MBOX_Id_t mailBoxId, const HW_MBOX_UserId_t userId,
+ const u32 event)
{
HW_STATUS status = RET_OK;
u32 irqStatusReg;
diff --git a/drivers/dsp/bridge/hw/hw_mbox.h b/drivers/dsp/bridge/hw/hw_mbox.h
index 225fb40..5d3d18f
--- a/drivers/dsp/bridge/hw/hw_mbox.h
+++ b/drivers/dsp/bridge/hw/hw_mbox.h
@@ -92,7 +92,7 @@ struct MAILBOX_CONTEXT {
* box Specified. if there are no messages in the mailbox
* then and error is returned.
*/
-extern HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress,
+extern HW_STATUS HW_MBOX_MsgRead(const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId,
u32 *const pReadValue);
@@ -124,7 +124,7 @@ extern HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress,
* box Specified.
*/
extern HW_STATUS HW_MBOX_MsgWrite(
- const u32 baseAddress,
+ const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId,
const u32 writeValue
);
@@ -159,7 +159,7 @@ extern HW_STATUS HW_MBOX_MsgWrite(
* PURPOSE: : this function reads the full status register for mailbox.
*/
extern HW_STATUS HW_MBOX_IsFull(
- const u32 baseAddress,
+ const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId,
u32 *const pIsFull
);
@@ -193,7 +193,7 @@ extern HW_STATUS HW_MBOX_IsFull(
* PURPOSE: : this function gets number of messages in a specified mailbox.
*/
extern HW_STATUS HW_MBOX_NumMsgGet(
- const u32 baseAddress,
+ const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId,
u32 *const pNumMsg
);
@@ -229,7 +229,7 @@ extern HW_STATUS HW_MBOX_NumMsgGet(
* PURPOSE: : this function enables the specified IRQ.
*/
extern HW_STATUS HW_MBOX_EventEnable(
- const u32 baseAddress,
+ const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId,
const HW_MBOX_UserId_t userId,
const u32 events
@@ -266,7 +266,7 @@ extern HW_STATUS HW_MBOX_EventEnable(
* PURPOSE: : this function disables the specified IRQ.
*/
extern HW_STATUS HW_MBOX_EventDisable(
- const u32 baseAddress,
+ const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId,
const HW_MBOX_UserId_t userId,
const u32 events
@@ -305,7 +305,7 @@ extern HW_STATUS HW_MBOX_EventDisable(
* PURPOSE: : this function sets the status of the specified IRQ.
*/
extern HW_STATUS HW_MBOX_EventAck(
- const u32 baseAddress,
+ const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId,
const HW_MBOX_UserId_t userId,
const u32 event
@@ -331,7 +331,7 @@ extern HW_STATUS HW_MBOX_EventAck(
*
* PURPOSE: : this function saves the context of mailbox
*/
-extern HW_STATUS HW_MBOX_saveSettings(u32 baseAddres);
+extern HW_STATUS HW_MBOX_saveSettings(void __iomem *baseAddres);
/*
* FUNCTION : HW_MBOX_restoreSettings
@@ -353,6 +353,6 @@ extern HW_STATUS HW_MBOX_saveSettings(u32 baseAddres);
*
* PURPOSE: : this function restores the context of mailbox
*/
-extern HW_STATUS HW_MBOX_restoreSettings(u32 baseAddres);
+extern HW_STATUS HW_MBOX_restoreSettings(void __iomem *baseAddres);
#endif /* __MBOX_H */
diff --git a/drivers/dsp/bridge/hw/hw_mmu.c b/drivers/dsp/bridge/hw/hw_mmu.c
index da7e092..3f2b75c
--- a/drivers/dsp/bridge/hw/hw_mmu.c
+++ b/drivers/dsp/bridge/hw/hw_mmu.c
@@ -30,6 +30,7 @@
*/
#include <GlobalTypes.h>
+#include <linux/io.h>
#include "MMURegAcM.h"
#include <hw_defs.h>
#include <hw_mmu.h>
@@ -79,7 +80,7 @@ enum HW_MMUPageSize_t {
* METHOD: : Check the Input parameter and Flush a
* single entry in the TLB.
*/
-static HW_STATUS MMU_FlushEntry(const u32 baseAddress);
+static HW_STATUS MMU_FlushEntry(const void __iomem *baseAddress);
/*
* FUNCTION : MMU_SetCAMEntry
@@ -121,7 +122,7 @@ static HW_STATUS MMU_FlushEntry(const u32 baseAddress);
*
* METHOD: : Check the Input parameters and set the CAM entry.
*/
-static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
+static HW_STATUS MMU_SetCAMEntry(const void __iomem *baseAddress,
const u32 pageSize,
const u32 preservedBit,
const u32 validBit,
@@ -166,7 +167,7 @@ static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
*
* METHOD: : Check the Input parameters and set the RAM entry.
*/
-static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
+static HW_STATUS MMU_SetRAMEntry(const void __iomem *baseAddress,
const u32 physicalAddr,
enum HW_Endianism_t endianism,
enum HW_ElementSize_t elementSize,
@@ -174,7 +175,7 @@ static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
/* HW FUNCTIONS */
-HW_STATUS HW_MMU_Enable(const u32 baseAddress)
+HW_STATUS HW_MMU_Enable(const void __iomem *baseAddress)
{
HW_STATUS status = RET_OK;
@@ -183,7 +184,7 @@ HW_STATUS HW_MMU_Enable(const u32 baseAddress)
return status;
}
-HW_STATUS HW_MMU_Disable(const u32 baseAddress)
+HW_STATUS HW_MMU_Disable(const void __iomem *baseAddress)
{
HW_STATUS status = RET_OK;
@@ -192,7 +193,7 @@ HW_STATUS HW_MMU_Disable(const u32 baseAddress)
return status;
}
-HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
+HW_STATUS HW_MMU_NumLockedSet(const void __iomem *baseAddress,
u32 numLockedEntries)
{
HW_STATUS status = RET_OK;
@@ -202,7 +203,7 @@ HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
return status;
}
-HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
+HW_STATUS HW_MMU_VictimNumSet(const void __iomem *baseAddress,
u32 victimEntryNum)
{
HW_STATUS status = RET_OK;
@@ -212,7 +213,7 @@ HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
return status;
}
-HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress)
+HW_STATUS HW_MMU_TLBFlushAll(const void __iomem *baseAddress)
{
HW_STATUS status = RET_OK;
@@ -221,7 +222,7 @@ HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress)
return status;
}
-HW_STATUS HW_MMU_EventAck(const u32 baseAddress, u32 irqMask)
+HW_STATUS HW_MMU_EventAck(const void __iomem *baseAddress, u32 irqMask)
{
HW_STATUS status = RET_OK;
@@ -230,7 +231,7 @@ HW_STATUS HW_MMU_EventAck(const u32 baseAddress, u32 irqMask)
return status;
}
-HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
+HW_STATUS HW_MMU_EventDisable(const void __iomem *baseAddress,
u32 irqMask)
{
HW_STATUS status = RET_OK;
@@ -243,7 +244,7 @@ HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
return status;
}
-HW_STATUS HW_MMU_EventEnable(const u32 baseAddress, u32 irqMask)
+HW_STATUS HW_MMU_EventEnable(const void __iomem *baseAddress, u32 irqMask)
{
HW_STATUS status = RET_OK;
u32 irqReg;
@@ -256,7 +257,7 @@ HW_STATUS HW_MMU_EventEnable(const u32 baseAddress, u32 irqMask)
}
-HW_STATUS HW_MMU_EventStatus(const u32 baseAddress, u32 *irqMask)
+HW_STATUS HW_MMU_EventStatus(const void __iomem *baseAddress, u32 *irqMask)
{
HW_STATUS status = RET_OK;
@@ -266,7 +267,7 @@ HW_STATUS HW_MMU_EventStatus(const u32 baseAddress, u32 *irqMask)
}
-HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress, u32 *addr)
+HW_STATUS HW_MMU_FaultAddrRead(const void __iomem *baseAddress, u32 *addr)
{
HW_STATUS status = RET_OK;
@@ -280,7 +281,7 @@ HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress, u32 *addr)
return status;
}
-HW_STATUS HW_MMU_TTBSet(const u32 baseAddress, u32 TTBPhysAddr)
+HW_STATUS HW_MMU_TTBSet(const void __iomem *baseAddress, u32 TTBPhysAddr)
{
HW_STATUS status = RET_OK;
u32 loadTTB;
@@ -296,7 +297,7 @@ HW_STATUS HW_MMU_TTBSet(const u32 baseAddress, u32 TTBPhysAddr)
return status;
}
-HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress)
+HW_STATUS HW_MMU_TWLEnable(const void __iomem *baseAddress)
{
HW_STATUS status = RET_OK;
@@ -305,7 +306,7 @@ HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress)
return status;
}
-HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress)
+HW_STATUS HW_MMU_TWLDisable(const void __iomem *baseAddress)
{
HW_STATUS status = RET_OK;
@@ -314,7 +315,7 @@ HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress)
return status;
}
-HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress, u32 virtualAddr,
+HW_STATUS HW_MMU_TLBFlush(const void __iomem *baseAddress, u32 virtualAddr,
u32 pageSize)
{
HW_STATUS status = RET_OK;
@@ -352,7 +353,7 @@ HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress, u32 virtualAddr,
return status;
}
-HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
+HW_STATUS HW_MMU_TLBAdd(const void __iomem *baseAddress,
u32 physicalAddr,
u32 virtualAddr,
u32 pageSize,
@@ -538,7 +539,7 @@ HW_STATUS HW_MMU_PteClear(const u32 pgTblVa,
}
/* MMU_FlushEntry */
-static HW_STATUS MMU_FlushEntry(const u32 baseAddress)
+static HW_STATUS MMU_FlushEntry(const void __iomem *baseAddress)
{
HW_STATUS status = RET_OK;
u32 flushEntryData = 0x1;
@@ -554,7 +555,7 @@ static HW_STATUS MMU_FlushEntry(const u32 baseAddress)
}
/* MMU_SetCAMEntry */
-static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
+static HW_STATUS MMU_SetCAMEntry(const void __iomem *baseAddress,
const u32 pageSize,
const u32 preservedBit,
const u32 validBit,
@@ -578,7 +579,7 @@ static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
}
/* MMU_SetRAMEntry */
-static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
+static HW_STATUS MMU_SetRAMEntry(const void __iomem *baseAddress,
const u32 physicalAddr,
enum HW_Endianism_t endianism,
enum HW_ElementSize_t elementSize,
diff --git a/drivers/dsp/bridge/hw/hw_mmu.h b/drivers/dsp/bridge/hw/hw_mmu.h
index 924f32b..dc1aec1
--- a/drivers/dsp/bridge/hw/hw_mmu.h
+++ b/drivers/dsp/bridge/hw/hw_mmu.h
@@ -53,47 +53,47 @@ struct HW_MMUMapAttrs_t {
enum HW_MMUMixedSize_t mixedSize;
} ;
-extern HW_STATUS HW_MMU_Enable(const u32 baseAddress);
+extern HW_STATUS HW_MMU_Enable(const void __iomem *baseAddress);
-extern HW_STATUS HW_MMU_Disable(const u32 baseAddress);
+extern HW_STATUS HW_MMU_Disable(const void __iomem *baseAddress);
-extern HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
+extern HW_STATUS HW_MMU_NumLockedSet(const void __iomem *baseAddress,
u32 numLockedEntries);
-extern HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
+extern HW_STATUS HW_MMU_VictimNumSet(const void __iomem *baseAddress,
u32 victimEntryNum);
/* For MMU faults */
-extern HW_STATUS HW_MMU_EventAck(const u32 baseAddress,
+extern HW_STATUS HW_MMU_EventAck(const void __iomem *baseAddress,
u32 irqMask);
-extern HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
+extern HW_STATUS HW_MMU_EventDisable(const void __iomem *baseAddress,
u32 irqMask);
-extern HW_STATUS HW_MMU_EventEnable(const u32 baseAddress,
+extern HW_STATUS HW_MMU_EventEnable(const void __iomem *baseAddress,
u32 irqMask);
-extern HW_STATUS HW_MMU_EventStatus(const u32 baseAddress,
+extern HW_STATUS HW_MMU_EventStatus(const void __iomem *baseAddress,
u32 *irqMask);
-extern HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress,
+extern HW_STATUS HW_MMU_FaultAddrRead(const void __iomem *baseAddress,
u32 *addr);
/* Set the TT base address */
-extern HW_STATUS HW_MMU_TTBSet(const u32 baseAddress,
+extern HW_STATUS HW_MMU_TTBSet(const void __iomem *baseAddress,
u32 TTBPhysAddr);
-extern HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress);
+extern HW_STATUS HW_MMU_TWLEnable(const void __iomem *baseAddress);
-extern HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress);
+extern HW_STATUS HW_MMU_TWLDisable(const void __iomem *baseAddress);
-extern HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress,
+extern HW_STATUS HW_MMU_TLBFlush(const void __iomem *baseAddress,
u32 virtualAddr,
u32 pageSize);
-extern HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress);
+extern HW_STATUS HW_MMU_TLBFlushAll(const void __iomem *baseAddress);
-extern HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
+extern HW_STATUS HW_MMU_TLBAdd(const void __iomem *baseAddress,
u32 physicalAddr,
u32 virtualAddr,
u32 pageSize,
diff --git a/drivers/dsp/bridge/hw/hw_prcm.c b/drivers/dsp/bridge/hw/hw_prcm.c
index 61ff08f..8f04a70
--- a/drivers/dsp/bridge/hw/hw_prcm.c
+++ b/drivers/dsp/bridge/hw/hw_prcm.c
@@ -29,21 +29,21 @@
#include <hw_defs.h>
#include <hw_prcm.h>
-static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
+static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
enum HW_RstModule_t r,
enum HW_SetClear_t val);
-HW_STATUS HW_RST_Reset(const u32 baseAddress, enum HW_RstModule_t r)
+HW_STATUS HW_RST_Reset(const void __iomem *baseAddress, enum HW_RstModule_t r)
{
return HW_RST_WriteVal(baseAddress, r, HW_SET);
}
-HW_STATUS HW_RST_UnReset(const u32 baseAddress, enum HW_RstModule_t r)
+HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress, enum HW_RstModule_t r)
{
return HW_RST_WriteVal(baseAddress, r, HW_CLEAR);
}
-static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
+static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
enum HW_RstModule_t r,
enum HW_SetClear_t val)
{
@@ -66,8 +66,8 @@ static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
return status;
}
-HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress, enum HW_PwrModule_t p,
- enum HW_PwrState_t *value)
+HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
+ enum HW_PwrModule_t p, enum HW_PwrState_t *value)
{
HW_STATUS status = RET_OK;
u32 temp;
@@ -93,7 +93,7 @@ HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress, enum HW_PwrModule_t p,
return status;
}
-HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value)
+HW_STATUS HW_PWRST_IVA2RegGet(const void __iomem *baseAddress, u32 *value)
{
HW_STATUS status = RET_OK;
@@ -103,7 +103,7 @@ HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value)
}
-HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
+HW_STATUS HW_PWR_IVA2PowerStateSet(const void __iomem *baseAddress,
enum HW_PwrModule_t p,
enum HW_PwrState_t value)
{
@@ -135,7 +135,7 @@ HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
return status;
}
-HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
+HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
enum HW_TransitionState_t val)
{
HW_STATUS status = RET_OK;
@@ -146,8 +146,8 @@ HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
}
-HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
- u32 *value)
+HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
+ enum HW_RstModule_t m, u32 *value)
{
HW_STATUS status = RET_OK;
@@ -156,8 +156,8 @@ HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
return status;
}
-HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
- u32 *value)
+HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
+ enum HW_RstModule_t m, u32 *value)
{
HW_STATUS status = RET_OK;
diff --git a/drivers/dsp/bridge/hw/hw_prcm.h b/drivers/dsp/bridge/hw/hw_prcm.h
index 928486c..65c8bd1
--- a/drivers/dsp/bridge/hw/hw_prcm.h
+++ b/drivers/dsp/bridge/hw/hw_prcm.h
@@ -132,16 +132,16 @@ enum HW_TransitionState_t {
} ;
-extern HW_STATUS HW_RST_Reset(const u32 baseAddress,
+extern HW_STATUS HW_RST_Reset(const void __iomem *baseAddress,
enum HW_RstModule_t r);
-extern HW_STATUS HW_RST_UnReset(const u32 baseAddress,
+extern HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress,
enum HW_RstModule_t r);
-extern HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress,
+extern HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
enum HW_RstModule_t p,
u32 *value);
-extern HW_STATUS HW_RSTST_RegGet(const u32 baseAddress,
+extern HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
enum HW_RstModule_t p, u32 *value);
extern HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
@@ -152,17 +152,18 @@ extern HW_STATUS HW_CLK_SetInputClock(const u32 baseAddress,
enum HW_GPtimer_t gpt,
enum HW_Clocktype_t c);
-extern HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress,
+extern HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
enum HW_PwrModule_t p,
enum HW_PwrState_t *value);
-extern HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value);
+extern HW_STATUS HW_PWRST_IVA2RegGet(const void __iomem *baseAddress,
+ u32 *value);
-extern HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
+extern HW_STATUS HW_PWR_IVA2PowerStateSet(const void __iomem *baseAddress,
enum HW_PwrModule_t p,
enum HW_PwrState_t value);
-extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
+extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
enum HW_TransitionState_t val);
#endif /* __HW_PRCM_H */
diff --git a/drivers/dsp/bridge/rmgr/drv.c b/drivers/dsp/bridge/rmgr/drv.c
index 22faf49..07fde81
--- a/drivers/dsp/bridge/rmgr/drv.c
+++ b/drivers/dsp/bridge/rmgr/drv.c
@@ -1649,15 +1649,15 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
"%x. Not calling MEM_FreePhysMem\n",
status);
}
pResources->dwMemBase[1] = 0;
pResources->dwMemPhys[1] = 0;
if (pResources->dwPrmBase)
- iounmap((void *)pResources->dwPrmBase);
+ iounmap(pResources->dwPrmBase);
if (pResources->dwCmBase)
- iounmap((void *)pResources->dwCmBase);
+ iounmap(pResources->dwCmBase);
if (pResources->dwMboxBase)
- iounmap((void *)pResources->dwMboxBase);
+ iounmap(pResources->dwMboxBase);
if (pResources->dwMemBase[0])
iounmap((void *)pResources->dwMemBase[0]);
if (pResources->dwMemBase[2])
@@ -1667,26 +1667,26 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
if (pResources->dwMemBase[4])
iounmap((void *)pResources->dwMemBase[4]);
if (pResources->dwWdTimerDspBase)
- iounmap((void *)pResources->dwWdTimerDspBase);
+ iounmap(pResources->dwWdTimerDspBase);
if (pResources->dwDmmuBase)
- iounmap((void *)pResources->dwDmmuBase);
+ iounmap(pResources->dwDmmuBase);
if (pResources->dwPerBase)
- iounmap((void *)pResources->dwPerBase);
+ iounmap(pResources->dwPerBase);
if (pResources->dwSysCtrlBase) {
- iounmap((void *)pResources->dwSysCtrlBase);
+ iounmap(pResources->dwSysCtrlBase);
/* don't set pResources->dwSysCtrlBase to null
* as it is used in BOARD_Stop */
}
- pResources->dwPrmBase = (u32) NULL;
- pResources->dwCmBase = (u32) NULL;
- pResources->dwMboxBase = (u32) NULL;
- pResources->dwMemBase[0] = (u32) NULL;
- pResources->dwMemBase[2] = (u32) NULL;
- pResources->dwMemBase[3] = (u32) NULL;
- pResources->dwMemBase[4] = (u32) NULL;
- pResources->dwWdTimerDspBase = (u32) NULL;
- pResources->dwDmmuBase = (u32) NULL;
+ pResources->dwPrmBase = NULL;
+ pResources->dwCmBase = NULL;
+ pResources->dwMboxBase = NULL;
+ pResources->dwMemBase[0] = (u32)NULL;
+ pResources->dwMemBase[2] = (u32)NULL;
+ pResources->dwMemBase[3] = (u32)NULL;
+ pResources->dwMemBase[4] = (u32)NULL;
+ pResources->dwWdTimerDspBase = NULL;
+ pResources->dwDmmuBase = NULL;
dwBuffSize = sizeof(struct CFG_HOSTRES);
status = REG_SetValue(NULL, (char *)driverExt->szString,
@@ -1705,13 +1705,13 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
pResources->wNumMemWindows = 2;
/* First window is for DSP internal memory */
- pResources->dwPrmBase = (u32)ioremap(OMAP_IVA2_PRM_BASE,
+ pResources->dwPrmBase = ioremap(OMAP_IVA2_PRM_BASE,
OMAP_IVA2_PRM_SIZE);
- pResources->dwCmBase = (u32)ioremap(OMAP_IVA2_CM_BASE,
+ pResources->dwCmBase = ioremap(OMAP_IVA2_CM_BASE,
OMAP_IVA2_CM_SIZE);
- pResources->dwMboxBase = (u32)ioremap(OMAP_MBOX_BASE,
+ pResources->dwMboxBase = ioremap(OMAP_MBOX_BASE,
OMAP_MBOX_SIZE);
- pResources->dwSysCtrlBase = (u32)ioremap(OMAP_SYSC_BASE,
+ pResources->dwSysCtrlBase = ioremap(OMAP_SYSC_BASE,
OMAP_SYSC_SIZE);
GT_1trace(curTrace, GT_2CLASS, "dwMemBase[0] 0x%x\n",
pResources->dwMemBase[0]);
@@ -1797,18 +1797,18 @@ static DSP_STATUS RequestBridgeResourcesDSP(u32 dwContext, s32 bRequest)
/* wNumMemWindows must not be more than CFG_MAXMEMREGISTERS */
pResources->wNumMemWindows = 4;
pResources->dwMemBase[0] = 0;
pResources->dwMemBase[2] = (u32)ioremap(OMAP_DSP_MEM1_BASE,
OMAP_DSP_MEM1_SIZE);
pResources->dwMemBase[3] = (u32)ioremap(OMAP_DSP_MEM2_BASE,
OMAP_DSP_MEM2_SIZE);
pResources->dwMemBase[4] = (u32)ioremap(OMAP_DSP_MEM3_BASE,
OMAP_DSP_MEM3_SIZE);
- pResources->dwPerBase = (u32)ioremap(OMAP_PER_CM_BASE,
+ pResources->dwPerBase = ioremap(OMAP_PER_CM_BASE,
OMAP_PER_CM_SIZE);
- pResources->dwDmmuBase = (u32)ioremap(OMAP_DMMU_BASE,
+ pResources->dwDmmuBase = ioremap(OMAP_DMMU_BASE,
OMAP_DMMU_SIZE);
- pResources->dwWdTimerDspBase = 0;
+ pResources->dwWdTimerDspBase = NULL;
GT_1trace(curTrace, GT_2CLASS, "dwMemBase[0] 0x%x\n",
pResources->dwMemBase[0]);
diff --git a/drivers/dsp/bridge/rmgr/node.c b/drivers/dsp/bridge/rmgr/node.c
index 1db32e9..2b029c7
--- a/drivers/dsp/bridge/rmgr/node.c
+++ b/drivers/dsp/bridge/rmgr/node.c
@@ -717,7 +717,7 @@ func_cont2:
"0x%x\n", status);
}
- ulGppMemBase = hostRes.dwMemBase[1];
+ ulGppMemBase = (u32)hostRes.dwMemBase[1];
offSet = pulValue - dynextBase;
ulStackSegAddr = ulGppMemBase + offSet;
ulStackSegVal = (u32)*((REG_UWORD32 *)
diff --git a/drivers/dsp/bridge/wmd/_tiomap.h b/drivers/dsp/bridge/wmd/_tiomap.h
index 5267eb2..3cd2237
--- a/drivers/dsp/bridge/wmd/_tiomap.h
+++ b/drivers/dsp/bridge/wmd/_tiomap.h
@@ -362,7 +362,7 @@ struct WMD_DEV_CONTEXT {
*/
u32 dwDspExtBaseAddr; /* See the comment above */
u32 dwAPIRegBase; /* API memory mapped registers */
- u32 dwDSPMmuBase; /* DSP MMU Mapped registers */
+ void __iomem *dwDSPMmuBase; /* DSP MMU Mapped registers */
u32 dwMailBoxBase; /* Mail box mapped registers */
u32 dwAPIClkBase; /* CLK Registers */
u32 dwDSPClkM2Base; /* DSP Clock Module m2 */
diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c
index 730f9b5..ad813e4
--- a/drivers/dsp/bridge/wmd/tiomap3430.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430.c
@@ -131,9 +131,9 @@ static DSP_STATUS PteSet(struct PgTableAttrs *pt, u32 pa, u32 va,
static DSP_STATUS MemMapVmalloc(struct WMD_DEV_CONTEXT *hDevContext,
u32 ulMpuAddr, u32 ulVirtAddr,
u32 ulNumBytes, u32 ulMapAttr);
-static DSP_STATUS run_IdleBoot(u32 prcm_base, u32 cm_base,
- u32 sysctrl_base);
-void GetHWRegs(u32 prcm_base, u32 cm_base);
+static DSP_STATUS run_IdleBoot(void __iomem *prcm_base, void __iomem *cm_base,
+ void __iomem *sysctrl_base);
+static void GetHWRegs(void __iomem *prcm_base, void __iomem *cm_base);
/* ----------------------------------- Globals */
@@ -505,11 +505,10 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
HW_MMU_TWLEnable(resources.dwDmmuBase);
/* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
- temp = (u32) *((REG_UWORD32 *)
- ((u32) (resources.dwDmmuBase) + 0x10));
+
+ temp = __raw_readl((resources.dwDmmuBase) + 0x10);
temp = (temp & 0xFFFFFFEF) | 0x11;
- *((REG_UWORD32 *) ((u32) (resources.dwDmmuBase) + 0x10)) =
- (u32) temp;
+ __raw_writel(temp, (resources.dwDmmuBase) + 0x10);
/* Let the DSP MMU run */
HW_MMU_Enable(resources.dwDmmuBase);
@@ -2069,8 +2068,8 @@ func_cont:
return status;
}
-static DSP_STATUS run_IdleBoot(u32 prm_base, u32 cm_base,
- u32 sysctrl_base)
+static DSP_STATUS run_IdleBoot(void __iomem *prm_base, void __iomem *cm_base,
+ void __iomem *sysctrl_base)
{
u32 temp;
DSP_STATUS status = DSP_SOK;
@@ -2096,10 +2095,10 @@ static DSP_STATUS run_IdleBoot(u32 prm_base, u32 cm_base,
}
udelay(10);
/* Assert IVA2-RST1 and IVA2-RST2 */
- *((REG_UWORD32 *)((u32)(prm_base) + 0x50)) = (u32)0x07;
+ __raw_writel((u32)0x07, (prm_base) + 0x50);
udelay(30);
/* set the SYSC for Idle Boot */
- *((REG_UWORD32 *)((u32)(sysctrl_base) + 0x404)) = (u32)0x01;
+ __raw_writel((u32)0x01, (sysctrl_base) + 0x404);
clk_status = CLK_Enable(SERVICESCLK_iva2_ck);
if (DSP_FAILED(clk_status)) {
DBG_Trace(DBG_LEVEL6, "CLK_Enable failed for clk = 0x%x \n",
@@ -2108,36 +2107,36 @@ static DSP_STATUS run_IdleBoot(u32 prm_base, u32 cm_base,
udelay(20);
GetHWRegs(prm_base, cm_base);
/* Release Reset1 and Reset2 */
- *((REG_UWORD32 *)((u32)(prm_base) + 0x50)) = (u32)0x05;
+ __raw_writel((u32)0x05, (prm_base) + 0x50);
udelay(20);
- *((REG_UWORD32 *)((u32)(prm_base) + 0x50)) = (u32)0x04;
+ __raw_writel((u32)0x04, (prm_base) + 0x50);
udelay(30);
return status;
}
-void GetHWRegs(u32 prm_base, u32 cm_base)
+static void GetHWRegs(void __iomem *prm_base, void __iomem *cm_base)
{
u32 temp;
- temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x00));
+ temp = __raw_readl((cm_base) + 0x00);
DBG_Trace(DBG_LEVEL6, "CM_FCLKEN_IVA2 = 0x%x \n", temp);
- temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x10));
+ temp = __raw_readl((cm_base) + 0x10);
DBG_Trace(DBG_LEVEL6, "CM_ICLKEN1_IVA2 = 0x%x \n", temp);
- temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x20));
+ temp = __raw_readl((cm_base) + 0x20);
DBG_Trace(DBG_LEVEL6, "CM_IDLEST_IVA2 = 0x%x \n", temp);
- temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x48));
+ temp = __raw_readl((cm_base) + 0x48);
DBG_Trace(DBG_LEVEL6, "CM_CLKSTCTRL_IVA2 = 0x%x \n", temp);
- temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x4c));
+ temp = __raw_readl((cm_base) + 0x4c);
DBG_Trace(DBG_LEVEL6, "CM_CLKSTST_IVA2 = 0x%x \n", temp);
- temp = (u32)*((REG_UWORD32 *)((u32)(prm_base) + 0x50));
+ temp = __raw_readl((prm_base) + 0x50);
DBG_Trace(DBG_LEVEL6, "RM_RSTCTRL_IVA2 = 0x%x \n", temp);
- temp = (u32)*((REG_UWORD32 *)((u32)(prm_base) + 0x58));
+ temp = __raw_readl((prm_base) + 0x58);
DBG_Trace(DBG_LEVEL6, "RM_RSTST_IVA2 = 0x%x \n", temp);
- temp = (u32)*((REG_UWORD32 *)((u32)(prm_base) + 0xE0));
+ temp = __raw_readl((prm_base) + 0xE0);
DBG_Trace(DBG_LEVEL6, "PM_PWSTCTRL_IVA2 = 0x%x \n", temp);
- temp = (u32)*((REG_UWORD32 *)((u32)(prm_base) + 0xE4));
+ temp = __raw_readl((prm_base) + 0xE4);
DBG_Trace(DBG_LEVEL6, "PM_PWSTST_IVA2 = 0x%x \n", temp);
- temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0xA10));
+ temp = __raw_readl((cm_base) + 0xA10);
DBG_Trace(DBG_LEVEL6, "CM_ICLKEN1_CORE = 0x%x \n", temp);
}
--
1.5.6.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Change address resources to void __iomem * Fernando Guzman Lugo
@ 2009-03-04 18:11 ` Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: cleanup of HW_MBOX_IsFull function Fernando Guzman Lugo
2009-03-05 10:14 ` [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h Ameya Palande
2009-03-05 10:22 ` [PATCH] DSPBRIDGE: Change address resources to void __iomem * Ameya Palande
1 sibling, 2 replies; 8+ messages in thread
From: Fernando Guzman Lugo @ 2009-03-04 18:11 UTC (permalink / raw)
To: leed.aguilar, vikram.pandita, h-kanigeri2, linux-omap
Cc: Fernando Guzman Lugo
This patch removes some variable that are not used.
Signed-off-by: Guzman Lugo Fernando <x0095840@ti.com>
---
arch/arm/plat-omap/include/dspbridge/cfgdefs.h | 10 ----------
drivers/dsp/bridge/rmgr/drv.c | 2 --
2 files changed, 0 insertions(+), 12 deletions(-)
diff --git a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
index e7633b5..34a28f8
--- a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
+++ b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
@@ -77,15 +77,6 @@
u8 bIRQAttrib; /* IRQ Attribute */
u32 dwOffsetForMonitor; /* The Shared memory starts from
* dwMemBase + this offset */
- u32 dwBusType; /* Bus type for this device */
- u32 dwProgBase; /* DSP ProgBase */
- u32 dwProgLength; /* DSP ProgBase Length */
- u32 dwRegBase; /* DSP memory mapped register base */
- u32 dwRegLength; /* DSP Register Base Length */
- u32 ClientHandle; /* Client Handle */
- u32 SocketHandle; /* Socket and Function Pair */
- u32 CardInfo; /* This will be used as a context data in
- * in the CardRequestIRQ */
/*
* Info needed by NODE for allocating channels to communicate with RMS:
* dwChnlOffset: Offset of RMS channels. Lower channels are
@@ -102,7 +93,6 @@
void __iomem *dwWdTimerDspBase;
void __iomem *dwMboxBase;
void __iomem *dwDmmuBase;
- u32 *dwDipiBase;
void __iomem *dwSysCtrlBase;
} ;
diff --git a/drivers/dsp/bridge/rmgr/drv.c b/drivers/dsp/bridge/rmgr/drv.c
index 2241f48..160d730
--- a/drivers/dsp/bridge/rmgr/drv.c
+++ b/drivers/dsp/bridge/rmgr/drv.c
@@ -1733,7 +1733,6 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
/* Second window is for DSP external memory shared with MPU */
if (DSP_SUCCEEDED(status)) {
/* for Linux, these are hard-coded values */
- pResources->dwBusType = 0;
pResources->bIRQRegisters = 0;
pResources->bIRQAttrib = 0;
pResources->dwOffsetForMonitor = 0;
@@ -1856,7 +1855,6 @@ static DSP_STATUS RequestBridgeResourcesDSP(u32 dwContext, s32 bRequest)
}
if (DSP_SUCCEEDED(status)) {
/* for Linux, these are hard-coded values */
- pResources->dwBusType = 0;
pResources->bIRQRegisters = 0;
pResources->bIRQAttrib = 0;
pResources->dwOffsetForMonitor = 0;
--
1.5.6.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] DSPBRIDGE: cleanup of HW_MBOX_IsFull function
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h Fernando Guzman Lugo
@ 2009-03-04 18:11 ` Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: wait less and check the mailbox more Fernando Guzman Lugo
2009-03-05 10:14 ` [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h Ameya Palande
1 sibling, 1 reply; 8+ messages in thread
From: Fernando Guzman Lugo @ 2009-03-04 18:11 UTC (permalink / raw)
To: leed.aguilar, vikram.pandita, h-kanigeri2, linux-omap
Cc: Fernando Guzman Lugo
This patch does a cleanup of the HW_MBOX_IsFull function; removing some
unnecessary checks and changing the returned value to bool because the status
value is not needed.
Signed-off-by: Fernando Guzman Lugo <x0095840@ti.com>
Reviewed-by: Felipe Contreras <felipe.contreras@gmail.com>
---
drivers/dsp/bridge/hw/hw_mbox.c | 25 -------------------------
drivers/dsp/bridge/hw/hw_mbox.h | 14 ++++++++------
drivers/dsp/bridge/wmd/tiomap_sm.c | 12 +++---------
3 files changed, 11 insertions(+), 40 deletions(-)
diff --git a/drivers/dsp/bridge/hw/hw_mbox.c b/drivers/dsp/bridge/hw/hw_mbox.c
index 0c0f721..ee79032
--- a/drivers/dsp/bridge/hw/hw_mbox.c
+++ b/drivers/dsp/bridge/hw/hw_mbox.c
@@ -104,31 +104,6 @@ HW_STATUS HW_MBOX_MsgWrite(const void __iomem *baseAddress,
return status;
}
-/* Reads the full status register for mailbox. */
-HW_STATUS HW_MBOX_IsFull(const void __iomem *baseAddress,
- const HW_MBOX_Id_t mailBoxId, u32 *const pIsFull)
-{
- HW_STATUS status = RET_OK;
- u32 fullStatus;
-
- /* Check input parameters */
- CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
- RES_INVALID_INPUT_PARAM);
- CHECK_INPUT_PARAM(pIsFull, NULL, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
- RES_INVALID_INPUT_PARAM);
- CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
- RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
-
- /* read the is full status parameter for Mailbox */
- fullStatus = MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress,
- (u32)mailBoxId);
-
- /* fill in return parameter */
- *pIsFull = (fullStatus & 0xFF);
-
- return status;
-}
-
/* Gets number of messages in a specified mailbox. */
HW_STATUS HW_MBOX_NumMsgGet(const void __iomem *baseAddress,
const HW_MBOX_Id_t mailBoxId, u32 *const pNumMsg)
diff --git a/drivers/dsp/bridge/hw/hw_mbox.h b/drivers/dsp/bridge/hw/hw_mbox.h
index 5d3d18f..341b58a
--- a/drivers/dsp/bridge/hw/hw_mbox.h
+++ b/drivers/dsp/bridge/hw/hw_mbox.h
@@ -26,6 +26,8 @@
#ifndef __MBOX_H
#define __MBOX_H
+#include "MLBRegAcM.h"
+
/* Bitmasks for Mailbox interrupt sources */
#define HW_MBOX_INT_NEW_MSG 0x1
#define HW_MBOX_INT_NOT_FULL 0x2
@@ -158,12 +160,12 @@ extern HW_STATUS HW_MBOX_MsgWrite(
*
* PURPOSE: : this function reads the full status register for mailbox.
*/
-extern HW_STATUS HW_MBOX_IsFull(
- const void __iomem *baseAddress,
- const HW_MBOX_Id_t mailBoxId,
- u32 *const pIsFull
- );
-
+static inline bool HW_MBOX_IsFull(const void __iomem *baseAddress,
+ const HW_MBOX_Id_t mailBoxId)
+{
+ return MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress,
+ (u32)mailBoxId);
+}
/*
* FUNCTION : HW_MBOX_NumMsgGet
*
diff --git a/drivers/dsp/bridge/wmd/tiomap_sm.c b/drivers/dsp/bridge/wmd/tiomap_sm.c
index edc3bcf..f8496cf
--- a/drivers/dsp/bridge/wmd/tiomap_sm.c
+++ b/drivers/dsp/bridge/wmd/tiomap_sm.c
@@ -178,7 +178,6 @@ DSP_STATUS CHNLSM_InterruptDSP(struct WMD_DEV_CONTEXT *hDevContext)
#endif
#endif
HW_STATUS hwStatus;
- u32 mbxFull;
struct CFG_HOSTRES resources;
u16 cnt = 10;
u32 temp;
@@ -241,14 +240,9 @@ DSP_STATUS CHNLSM_InterruptDSP(struct WMD_DEV_CONTEXT *hDevContext)
pDevContext->dwBrdState = BRD_RUNNING;
}
- while (--cnt) {
- hwStatus = HW_MBOX_IsFull(resources.dwMboxBase,
- MBOX_ARM2DSP, &mbxFull);
- if (mbxFull)
- UTIL_Wait(1000); /* wait for 1 ms) */
- else
- break;
- }
+ while (--cnt && HW_MBOX_IsFull(resources.dwMboxBase, MBOX_ARM2DSP))
+ mdelay(1);
+
if (!cnt) {
DBG_Trace(DBG_LEVEL7, "Timed out waiting for DSP mailbox \n");
status = WMD_E_TIMEOUT;
--
1.5.6.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH] DSPBRIDGE: wait less and check the mailbox more.
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: cleanup of HW_MBOX_IsFull function Fernando Guzman Lugo
@ 2009-03-04 18:11 ` Fernando Guzman Lugo
0 siblings, 0 replies; 8+ messages in thread
From: Fernando Guzman Lugo @ 2009-03-04 18:11 UTC (permalink / raw)
To: leed.aguilar, vikram.pandita, h-kanigeri2, linux-omap
Cc: Fernando Guzman Lugo, Felipe Contreras
Performance is increased if we wait less and check the mailbox more when it's
full.
Signed-off-by: Felipe Contreras <felipe.contreras@nokia.com>
Signed-off-by: Fernando Guzman Lugo <x0095840@ti.com>
---
drivers/dsp/bridge/wmd/tiomap_sm.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dsp/bridge/wmd/tiomap_sm.c b/drivers/dsp/bridge/wmd/tiomap_sm.c
index f8496cf..2843788
--- a/drivers/dsp/bridge/wmd/tiomap_sm.c
+++ b/drivers/dsp/bridge/wmd/tiomap_sm.c
@@ -179,7 +179,7 @@ DSP_STATUS CHNLSM_InterruptDSP(struct WMD_DEV_CONTEXT *hDevContext)
#endif
HW_STATUS hwStatus;
struct CFG_HOSTRES resources;
- u16 cnt = 10;
+ u16 cnt = 1000;
u32 temp;
/* We are waiting indefinitely here. This needs to be fixed in the
* second phase */
@@ -241,7 +241,7 @@ DSP_STATUS CHNLSM_InterruptDSP(struct WMD_DEV_CONTEXT *hDevContext)
pDevContext->dwBrdState = BRD_RUNNING;
}
while (--cnt && HW_MBOX_IsFull(resources.dwMboxBase, MBOX_ARM2DSP))
- mdelay(1);
+ udelay(1);
if (!cnt) {
DBG_Trace(DBG_LEVEL7, "Timed out waiting for DSP mailbox \n");
--
1.5.6.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: cleanup of HW_MBOX_IsFull function Fernando Guzman Lugo
@ 2009-03-05 10:14 ` Ameya Palande
1 sibling, 0 replies; 8+ messages in thread
From: Ameya Palande @ 2009-03-05 10:14 UTC (permalink / raw)
To: Fernando Guzman Lugo
Cc: leed.aguilar, vikram.pandita, h-kanigeri2, linux-omap
On Wed, Mar 4, 2009 at 8:11 PM, Fernando Guzman Lugo <x0095840@ti.com> wrote:
> This patch removes some variable that are not used.
> Signed-off-by: Guzman Lugo Fernando <x0095840@ti.com>
> ---
> arch/arm/plat-omap/include/dspbridge/cfgdefs.h | 10 ----------
> drivers/dsp/bridge/rmgr/drv.c | 2 --
> 2 files changed, 0 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> index e7633b5..34a28f8
> --- a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> +++ b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> @@ -77,15 +77,6 @@
> u8 bIRQAttrib; /* IRQ Attribute */
> u32 dwOffsetForMonitor; /* The Shared memory starts from
> * dwMemBase + this offset */
> - u32 dwBusType; /* Bus type for this device */
> - u32 dwProgBase; /* DSP ProgBase */
> - u32 dwProgLength; /* DSP ProgBase Length */
> - u32 dwRegBase; /* DSP memory mapped register base */
> - u32 dwRegLength; /* DSP Register Base Length */
> - u32 ClientHandle; /* Client Handle */
> - u32 SocketHandle; /* Socket and Function Pair */
> - u32 CardInfo; /* This will be used as a context data in
> - * in the CardRequestIRQ */
> /*
> * Info needed by NODE for allocating channels to communicate with RMS:
> * dwChnlOffset: Offset of RMS channels. Lower channels are
> @@ -102,7 +93,6 @@
> void __iomem *dwWdTimerDspBase;
> void __iomem *dwMboxBase;
> void __iomem *dwDmmuBase;
> - u32 *dwDipiBase;
> void __iomem *dwSysCtrlBase;
> } ;
>
> diff --git a/drivers/dsp/bridge/rmgr/drv.c b/drivers/dsp/bridge/rmgr/drv.c
> index 2241f48..160d730
> --- a/drivers/dsp/bridge/rmgr/drv.c
> +++ b/drivers/dsp/bridge/rmgr/drv.c
> @@ -1733,7 +1733,6 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
> /* Second window is for DSP external memory shared with MPU */
> if (DSP_SUCCEEDED(status)) {
> /* for Linux, these are hard-coded values */
> - pResources->dwBusType = 0;
> pResources->bIRQRegisters = 0;
> pResources->bIRQAttrib = 0;
> pResources->dwOffsetForMonitor = 0;
> @@ -1856,7 +1855,6 @@ static DSP_STATUS RequestBridgeResourcesDSP(u32 dwContext, s32 bRequest)
> }
> if (DSP_SUCCEEDED(status)) {
> /* for Linux, these are hard-coded values */
> - pResources->dwBusType = 0;
> pResources->bIRQRegisters = 0;
> pResources->bIRQAttrib = 0;
> pResources->dwOffsetForMonitor = 0;
> --
> 1.5.6.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
Couldn't apply :(
I guess you missed the following commit.
commit 3b313ff3e50d3c46c506e8939f92c406aa5b0bc6
Author: Ramesh Gupta G <grgupta@ti.com>
Date: Fri Feb 13 14:51:19 2009 +0530
patching file arch/arm/plat-omap/include/dspbridge/cfgdefs.h
Hunk #2 FAILED at 93.
1 out of 2 hunks FAILED -- saving rejects to file
arch/arm/plat-omap/include/dspbridge/cfgdefs.h.rej
patching file drivers/dsp/bridge/rmgr/drv.c
Hunk #1 succeeded at 1736 (offset 3 lines).
Hunk #2 succeeded at 1862 (offset 7 lines).
Cheers,
Ameya.
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] DSPBRIDGE: Change address resources to void __iomem *
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Change address resources to void __iomem * Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h Fernando Guzman Lugo
@ 2009-03-05 10:22 ` Ameya Palande
1 sibling, 0 replies; 8+ messages in thread
From: Ameya Palande @ 2009-03-05 10:22 UTC (permalink / raw)
To: Fernando Guzman Lugo
Cc: leed.aguilar, vikram.pandita, h-kanigeri2, linux-omap
On Wed, Mar 4, 2009 at 8:11 PM, Fernando Guzman Lugo <x0095840@ti.com> wrote:
> This patch changes address resources to void __iomem *
> Signed-off-by: Guzman Lugo Fernando <x0095840@ti.com>
> ---
> arch/arm/plat-omap/include/dspbridge/cfgdefs.h | 16 ++++----
> drivers/dsp/bridge/hw/hw_dspssC64P.c | 2 +-
> drivers/dsp/bridge/hw/hw_dspssC64P.h | 2 +-
> drivers/dsp/bridge/hw/hw_mbox.c | 30 +++++++------
> drivers/dsp/bridge/hw/hw_mbox.h | 18 ++++----
> drivers/dsp/bridge/hw/hw_mmu.c | 43 ++++++++++----------
> drivers/dsp/bridge/hw/hw_mmu.h | 30 +++++++-------
> drivers/dsp/bridge/hw/hw_prcm.c | 26 ++++++------
> drivers/dsp/bridge/hw/hw_prcm.h | 17 ++++----
> drivers/dsp/bridge/rmgr/drv.c | 52 ++++++++++++------------
> drivers/dsp/bridge/rmgr/node.c | 2 +-
> drivers/dsp/bridge/wmd/_tiomap.h | 2 +-
> drivers/dsp/bridge/wmd/tiomap3430.c | 47 ++++++++++-----------
> 13 files changed, 145 insertions(+), 142 deletions(-)
>
> diff --git a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> index ca96b3c..e7633b5
> --- a/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> +++ b/arch/arm/plat-omap/include/dspbridge/cfgdefs.h
> @@ -96,14 +96,14 @@
> u32 dwChnlOffset;
> u32 dwChnlBufSize;
> u32 dwNumChnls;
> - u32 dwPrmBase;
> - u32 dwCmBase;
> - u32 dwPerBase;
> - u32 dwWdTimerDspBase;
> - u32 dwMboxBase;
> - u32 dwDmmuBase;
> - u32 dwDipiBase;
> - u32 dwSysCtrlBase;
> + void __iomem *dwPrmBase;
> + void __iomem *dwCmBase;
> + void __iomem *dwPerBase;
> + void __iomem *dwWdTimerDspBase;
> + void __iomem *dwMboxBase;
> + void __iomem *dwDmmuBase;
> + u32 *dwDipiBase;
> + void __iomem *dwSysCtrlBase;
> } ;
>
> struct CFG_DSPMEMDESC {
> diff --git a/drivers/dsp/bridge/hw/hw_dspssC64P.c b/drivers/dsp/bridge/hw/hw_dspssC64P.c
> index 0d0d45c..6aac57d
> --- a/drivers/dsp/bridge/hw/hw_dspssC64P.c
> +++ b/drivers/dsp/bridge/hw/hw_dspssC64P.c
> @@ -34,7 +34,7 @@
> #include <IPIAccInt.h>
>
> /* HW FUNCTIONS */
> -HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
> +HW_STATUS HW_DSPSS_BootModeSet(const void __iomem *baseAddress,
> enum HW_DSPSYSC_BootMode_t bootMode,
> const u32 bootAddress)
> {
> diff --git a/drivers/dsp/bridge/hw/hw_dspssC64P.h b/drivers/dsp/bridge/hw/hw_dspssC64P.h
> index 493effd..50f9af4
> --- a/drivers/dsp/bridge/hw/hw_dspssC64P.h
> +++ b/drivers/dsp/bridge/hw/hw_dspssC64P.h
> @@ -41,7 +41,7 @@
>
> #define HW_DSP_IDLEBOOT_ADDR 0x007E0000
>
> - extern HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
> + extern HW_STATUS HW_DSPSS_BootModeSet(const void __iomem *baseAddress,
> enum HW_DSPSYSC_BootMode_t bootMode,
> const u32 bootAddress);
>
> diff --git a/drivers/dsp/bridge/hw/hw_mbox.c b/drivers/dsp/bridge/hw/hw_mbox.c
> index bc61d64..93fa51e
> --- a/drivers/dsp/bridge/hw/hw_mbox.c
> +++ b/drivers/dsp/bridge/hw/hw_mbox.c
> @@ -36,7 +37,7 @@
> struct MAILBOX_CONTEXT mboxsetting = {0x4, 0x1, 0x1};
>
> /* Saves the mailbox context */
> -HW_STATUS HW_MBOX_saveSettings(u32 baseAddress)
> +HW_STATUS HW_MBOX_saveSettings(void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -50,7 +51,7 @@ HW_STATUS HW_MBOX_saveSettings(u32 baseAddress)
> }
>
> /* Restores the mailbox context */
> -HW_STATUS HW_MBOX_restoreSettings(u32 baseAddress)
> +HW_STATUS HW_MBOX_restoreSettings(void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
> /* Restor IRQ enable status */
> @@ -65,8 +66,8 @@ HW_STATUS HW_MBOX_restoreSettings(u32 baseAddress)
>
> /* Reads a u32 from the sub module message box Specified. if there are no
> * messages in the mailbox then and error is returned. */
> -HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> - u32 *const pReadValue)
> +HW_STATUS HW_MBOX_MsgRead(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, u32 *const pReadValue)
> {
> HW_STATUS status = RET_OK;
>
> @@ -86,8 +87,8 @@ HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> }
>
> /* Writes a u32 from the sub module message box Specified. */
> -HW_STATUS HW_MBOX_MsgWrite(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> - const u32 writeValue)
> +HW_STATUS HW_MBOX_MsgWrite(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, const u32 writeValue)
> {
> HW_STATUS status = RET_OK;
>
> @@ -105,8 +106,8 @@ HW_STATUS HW_MBOX_MsgWrite(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> }
>
> /* Reads the full status register for mailbox. */
> -HW_STATUS HW_MBOX_IsFull(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> - u32 *const pIsFull)
> +HW_STATUS HW_MBOX_IsFull(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, u32 *const pIsFull)
> {
> HW_STATUS status = RET_OK;
> u32 fullStatus;
> @@ -130,8 +131,8 @@ HW_STATUS HW_MBOX_IsFull(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> }
>
> /* Gets number of messages in a specified mailbox. */
> -HW_STATUS HW_MBOX_NumMsgGet(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> - u32 *const pNumMsg)
> +HW_STATUS HW_MBOX_NumMsgGet(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, u32 *const pNumMsg)
> {
> HW_STATUS status = RET_OK;
>
> @@ -152,7 +153,7 @@ HW_STATUS HW_MBOX_NumMsgGet(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> }
>
> /* Enables the specified IRQ. */
> -HW_STATUS HW_MBOX_EventEnable(const u32 baseAddress,
> +HW_STATUS HW_MBOX_EventEnable(const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 events)
> @@ -192,7 +193,7 @@ HW_STATUS HW_MBOX_EventEnable(const u32 baseAddress,
> }
>
> /* Disables the specified IRQ. */
> -HW_STATUS HW_MBOX_EventDisable(const u32 baseAddress,
> +HW_STATUS HW_MBOX_EventDisable(const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 events)
> @@ -226,8 +227,9 @@ HW_STATUS HW_MBOX_EventDisable(const u32 baseAddress,
> }
>
> /* Sets the status of the specified IRQ. */
> -HW_STATUS HW_MBOX_EventAck(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
> - const HW_MBOX_UserId_t userId, const u32 event)
> +HW_STATUS HW_MBOX_EventAck(const void __iomem *baseAddress,
> + const HW_MBOX_Id_t mailBoxId, const HW_MBOX_UserId_t userId,
> + const u32 event)
> {
> HW_STATUS status = RET_OK;
> u32 irqStatusReg;
> diff --git a/drivers/dsp/bridge/hw/hw_mbox.h b/drivers/dsp/bridge/hw/hw_mbox.h
> index 225fb40..5d3d18f
> --- a/drivers/dsp/bridge/hw/hw_mbox.h
> +++ b/drivers/dsp/bridge/hw/hw_mbox.h
> @@ -92,7 +92,7 @@ struct MAILBOX_CONTEXT {
> * box Specified. if there are no messages in the mailbox
> * then and error is returned.
> */
> -extern HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress,
> +extern HW_STATUS HW_MBOX_MsgRead(const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> u32 *const pReadValue);
>
> @@ -124,7 +124,7 @@ extern HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress,
> * box Specified.
> */
> extern HW_STATUS HW_MBOX_MsgWrite(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const u32 writeValue
> );
> @@ -159,7 +159,7 @@ extern HW_STATUS HW_MBOX_MsgWrite(
> * PURPOSE: : this function reads the full status register for mailbox.
> */
> extern HW_STATUS HW_MBOX_IsFull(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> u32 *const pIsFull
> );
> @@ -193,7 +193,7 @@ extern HW_STATUS HW_MBOX_IsFull(
> * PURPOSE: : this function gets number of messages in a specified mailbox.
> */
> extern HW_STATUS HW_MBOX_NumMsgGet(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> u32 *const pNumMsg
> );
> @@ -229,7 +229,7 @@ extern HW_STATUS HW_MBOX_NumMsgGet(
> * PURPOSE: : this function enables the specified IRQ.
> */
> extern HW_STATUS HW_MBOX_EventEnable(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 events
> @@ -266,7 +266,7 @@ extern HW_STATUS HW_MBOX_EventEnable(
> * PURPOSE: : this function disables the specified IRQ.
> */
> extern HW_STATUS HW_MBOX_EventDisable(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 events
> @@ -305,7 +305,7 @@ extern HW_STATUS HW_MBOX_EventDisable(
> * PURPOSE: : this function sets the status of the specified IRQ.
> */
> extern HW_STATUS HW_MBOX_EventAck(
> - const u32 baseAddress,
> + const void __iomem *baseAddress,
> const HW_MBOX_Id_t mailBoxId,
> const HW_MBOX_UserId_t userId,
> const u32 event
> @@ -331,7 +331,7 @@ extern HW_STATUS HW_MBOX_EventAck(
> *
> * PURPOSE: : this function saves the context of mailbox
> */
> -extern HW_STATUS HW_MBOX_saveSettings(u32 baseAddres);
> +extern HW_STATUS HW_MBOX_saveSettings(void __iomem *baseAddres);
>
> /*
> * FUNCTION : HW_MBOX_restoreSettings
> @@ -353,6 +353,6 @@ extern HW_STATUS HW_MBOX_saveSettings(u32 baseAddres);
> *
> * PURPOSE: : this function restores the context of mailbox
> */
> -extern HW_STATUS HW_MBOX_restoreSettings(u32 baseAddres);
> +extern HW_STATUS HW_MBOX_restoreSettings(void __iomem *baseAddres);
>
> #endif /* __MBOX_H */
> diff --git a/drivers/dsp/bridge/hw/hw_mmu.c b/drivers/dsp/bridge/hw/hw_mmu.c
> index da7e092..3f2b75c
> --- a/drivers/dsp/bridge/hw/hw_mmu.c
> +++ b/drivers/dsp/bridge/hw/hw_mmu.c
> @@ -30,6 +30,7 @@
> */
>
> #include <GlobalTypes.h>
> +#include <linux/io.h>
> #include "MMURegAcM.h"
> #include <hw_defs.h>
> #include <hw_mmu.h>
> @@ -79,7 +80,7 @@ enum HW_MMUPageSize_t {
> * METHOD: : Check the Input parameter and Flush a
> * single entry in the TLB.
> */
> -static HW_STATUS MMU_FlushEntry(const u32 baseAddress);
> +static HW_STATUS MMU_FlushEntry(const void __iomem *baseAddress);
>
> /*
> * FUNCTION : MMU_SetCAMEntry
> @@ -121,7 +122,7 @@ static HW_STATUS MMU_FlushEntry(const u32 baseAddress);
> *
> * METHOD: : Check the Input parameters and set the CAM entry.
> */
> -static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
> +static HW_STATUS MMU_SetCAMEntry(const void __iomem *baseAddress,
> const u32 pageSize,
> const u32 preservedBit,
> const u32 validBit,
> @@ -166,7 +167,7 @@ static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
> *
> * METHOD: : Check the Input parameters and set the RAM entry.
> */
> -static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
> +static HW_STATUS MMU_SetRAMEntry(const void __iomem *baseAddress,
> const u32 physicalAddr,
> enum HW_Endianism_t endianism,
> enum HW_ElementSize_t elementSize,
> @@ -174,7 +175,7 @@ static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
>
> /* HW FUNCTIONS */
>
> -HW_STATUS HW_MMU_Enable(const u32 baseAddress)
> +HW_STATUS HW_MMU_Enable(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -183,7 +184,7 @@ HW_STATUS HW_MMU_Enable(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_Disable(const u32 baseAddress)
> +HW_STATUS HW_MMU_Disable(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -192,7 +193,7 @@ HW_STATUS HW_MMU_Disable(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
> +HW_STATUS HW_MMU_NumLockedSet(const void __iomem *baseAddress,
> u32 numLockedEntries)
> {
> HW_STATUS status = RET_OK;
> @@ -202,7 +203,7 @@ HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
> +HW_STATUS HW_MMU_VictimNumSet(const void __iomem *baseAddress,
> u32 victimEntryNum)
> {
> HW_STATUS status = RET_OK;
> @@ -212,7 +213,7 @@ HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress)
> +HW_STATUS HW_MMU_TLBFlushAll(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -221,7 +222,7 @@ HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_EventAck(const u32 baseAddress, u32 irqMask)
> +HW_STATUS HW_MMU_EventAck(const void __iomem *baseAddress, u32 irqMask)
> {
> HW_STATUS status = RET_OK;
>
> @@ -230,7 +231,7 @@ HW_STATUS HW_MMU_EventAck(const u32 baseAddress, u32 irqMask)
> return status;
> }
>
> -HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
> +HW_STATUS HW_MMU_EventDisable(const void __iomem *baseAddress,
> u32 irqMask)
> {
> HW_STATUS status = RET_OK;
> @@ -243,7 +244,7 @@ HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_MMU_EventEnable(const u32 baseAddress, u32 irqMask)
> +HW_STATUS HW_MMU_EventEnable(const void __iomem *baseAddress, u32 irqMask)
> {
> HW_STATUS status = RET_OK;
> u32 irqReg;
> @@ -256,7 +257,7 @@ HW_STATUS HW_MMU_EventEnable(const u32 baseAddress, u32 irqMask)
> }
>
>
> -HW_STATUS HW_MMU_EventStatus(const u32 baseAddress, u32 *irqMask)
> +HW_STATUS HW_MMU_EventStatus(const void __iomem *baseAddress, u32 *irqMask)
> {
> HW_STATUS status = RET_OK;
>
> @@ -266,7 +267,7 @@ HW_STATUS HW_MMU_EventStatus(const u32 baseAddress, u32 *irqMask)
> }
>
>
> -HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress, u32 *addr)
> +HW_STATUS HW_MMU_FaultAddrRead(const void __iomem *baseAddress, u32 *addr)
> {
> HW_STATUS status = RET_OK;
>
> @@ -280,7 +281,7 @@ HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress, u32 *addr)
> return status;
> }
>
> -HW_STATUS HW_MMU_TTBSet(const u32 baseAddress, u32 TTBPhysAddr)
> +HW_STATUS HW_MMU_TTBSet(const void __iomem *baseAddress, u32 TTBPhysAddr)
> {
> HW_STATUS status = RET_OK;
> u32 loadTTB;
> @@ -296,7 +297,7 @@ HW_STATUS HW_MMU_TTBSet(const u32 baseAddress, u32 TTBPhysAddr)
> return status;
> }
>
> -HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress)
> +HW_STATUS HW_MMU_TWLEnable(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -305,7 +306,7 @@ HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress)
> +HW_STATUS HW_MMU_TWLDisable(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
>
> @@ -314,7 +315,7 @@ HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress)
> return status;
> }
>
> -HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress, u32 virtualAddr,
> +HW_STATUS HW_MMU_TLBFlush(const void __iomem *baseAddress, u32 virtualAddr,
> u32 pageSize)
> {
> HW_STATUS status = RET_OK;
> @@ -352,7 +353,7 @@ HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress, u32 virtualAddr,
> return status;
> }
>
> -HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
> +HW_STATUS HW_MMU_TLBAdd(const void __iomem *baseAddress,
> u32 physicalAddr,
> u32 virtualAddr,
> u32 pageSize,
> @@ -538,7 +539,7 @@ HW_STATUS HW_MMU_PteClear(const u32 pgTblVa,
> }
>
> /* MMU_FlushEntry */
> -static HW_STATUS MMU_FlushEntry(const u32 baseAddress)
> +static HW_STATUS MMU_FlushEntry(const void __iomem *baseAddress)
> {
> HW_STATUS status = RET_OK;
> u32 flushEntryData = 0x1;
> @@ -554,7 +555,7 @@ static HW_STATUS MMU_FlushEntry(const u32 baseAddress)
> }
>
> /* MMU_SetCAMEntry */
> -static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
> +static HW_STATUS MMU_SetCAMEntry(const void __iomem *baseAddress,
> const u32 pageSize,
> const u32 preservedBit,
> const u32 validBit,
> @@ -578,7 +579,7 @@ static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
> }
>
> /* MMU_SetRAMEntry */
> -static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
> +static HW_STATUS MMU_SetRAMEntry(const void __iomem *baseAddress,
> const u32 physicalAddr,
> enum HW_Endianism_t endianism,
> enum HW_ElementSize_t elementSize,
> diff --git a/drivers/dsp/bridge/hw/hw_mmu.h b/drivers/dsp/bridge/hw/hw_mmu.h
> index 924f32b..dc1aec1
> --- a/drivers/dsp/bridge/hw/hw_mmu.h
> +++ b/drivers/dsp/bridge/hw/hw_mmu.h
> @@ -53,47 +53,47 @@ struct HW_MMUMapAttrs_t {
> enum HW_MMUMixedSize_t mixedSize;
> } ;
>
> -extern HW_STATUS HW_MMU_Enable(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_Enable(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_Disable(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_Disable(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_NumLockedSet(const void __iomem *baseAddress,
> u32 numLockedEntries);
>
> -extern HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_VictimNumSet(const void __iomem *baseAddress,
> u32 victimEntryNum);
>
> /* For MMU faults */
> -extern HW_STATUS HW_MMU_EventAck(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_EventAck(const void __iomem *baseAddress,
> u32 irqMask);
>
> -extern HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_EventDisable(const void __iomem *baseAddress,
> u32 irqMask);
>
> -extern HW_STATUS HW_MMU_EventEnable(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_EventEnable(const void __iomem *baseAddress,
> u32 irqMask);
>
> -extern HW_STATUS HW_MMU_EventStatus(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_EventStatus(const void __iomem *baseAddress,
> u32 *irqMask);
>
> -extern HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_FaultAddrRead(const void __iomem *baseAddress,
> u32 *addr);
>
> /* Set the TT base address */
> -extern HW_STATUS HW_MMU_TTBSet(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_TTBSet(const void __iomem *baseAddress,
> u32 TTBPhysAddr);
>
> -extern HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_TWLEnable(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_TWLDisable(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_TLBFlush(const void __iomem *baseAddress,
> u32 virtualAddr,
> u32 pageSize);
>
> -extern HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress);
> +extern HW_STATUS HW_MMU_TLBFlushAll(const void __iomem *baseAddress);
>
> -extern HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
> +extern HW_STATUS HW_MMU_TLBAdd(const void __iomem *baseAddress,
> u32 physicalAddr,
> u32 virtualAddr,
> u32 pageSize,
> diff --git a/drivers/dsp/bridge/hw/hw_prcm.c b/drivers/dsp/bridge/hw/hw_prcm.c
> index 61ff08f..8f04a70
> --- a/drivers/dsp/bridge/hw/hw_prcm.c
> +++ b/drivers/dsp/bridge/hw/hw_prcm.c
> @@ -29,21 +29,21 @@
> #include <hw_defs.h>
> #include <hw_prcm.h>
>
> -static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
> +static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
> enum HW_RstModule_t r,
> enum HW_SetClear_t val);
>
> -HW_STATUS HW_RST_Reset(const u32 baseAddress, enum HW_RstModule_t r)
> +HW_STATUS HW_RST_Reset(const void __iomem *baseAddress, enum HW_RstModule_t r)
> {
> return HW_RST_WriteVal(baseAddress, r, HW_SET);
> }
>
> -HW_STATUS HW_RST_UnReset(const u32 baseAddress, enum HW_RstModule_t r)
> +HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress, enum HW_RstModule_t r)
> {
> return HW_RST_WriteVal(baseAddress, r, HW_CLEAR);
> }
>
> -static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
> +static HW_STATUS HW_RST_WriteVal(const void __iomem *baseAddress,
> enum HW_RstModule_t r,
> enum HW_SetClear_t val)
> {
> @@ -66,8 +66,8 @@ static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress, enum HW_PwrModule_t p,
> - enum HW_PwrState_t *value)
> +HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
> + enum HW_PwrModule_t p, enum HW_PwrState_t *value)
> {
> HW_STATUS status = RET_OK;
> u32 temp;
> @@ -93,7 +93,7 @@ HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress, enum HW_PwrModule_t p,
> return status;
> }
>
> -HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value)
> +HW_STATUS HW_PWRST_IVA2RegGet(const void __iomem *baseAddress, u32 *value)
> {
> HW_STATUS status = RET_OK;
>
> @@ -103,7 +103,7 @@ HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value)
> }
>
>
> -HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
> +HW_STATUS HW_PWR_IVA2PowerStateSet(const void __iomem *baseAddress,
> enum HW_PwrModule_t p,
> enum HW_PwrState_t value)
> {
> @@ -135,7 +135,7 @@ HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
> return status;
> }
>
> -HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
> +HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
> enum HW_TransitionState_t val)
> {
> HW_STATUS status = RET_OK;
> @@ -146,8 +146,8 @@ HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
>
> }
>
> -HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
> - u32 *value)
> +HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
> + enum HW_RstModule_t m, u32 *value)
> {
> HW_STATUS status = RET_OK;
>
> @@ -156,8 +156,8 @@ HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
> return status;
> }
>
> -HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
> - u32 *value)
> +HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
> + enum HW_RstModule_t m, u32 *value)
> {
> HW_STATUS status = RET_OK;
>
> diff --git a/drivers/dsp/bridge/hw/hw_prcm.h b/drivers/dsp/bridge/hw/hw_prcm.h
> index 928486c..65c8bd1
> --- a/drivers/dsp/bridge/hw/hw_prcm.h
> +++ b/drivers/dsp/bridge/hw/hw_prcm.h
> @@ -132,16 +132,16 @@ enum HW_TransitionState_t {
> } ;
>
>
> -extern HW_STATUS HW_RST_Reset(const u32 baseAddress,
> +extern HW_STATUS HW_RST_Reset(const void __iomem *baseAddress,
> enum HW_RstModule_t r);
>
> -extern HW_STATUS HW_RST_UnReset(const u32 baseAddress,
> +extern HW_STATUS HW_RST_UnReset(const void __iomem *baseAddress,
> enum HW_RstModule_t r);
>
> -extern HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress,
> +extern HW_STATUS HW_RSTCTRL_RegGet(const void __iomem *baseAddress,
> enum HW_RstModule_t p,
> u32 *value);
> -extern HW_STATUS HW_RSTST_RegGet(const u32 baseAddress,
> +extern HW_STATUS HW_RSTST_RegGet(const void __iomem *baseAddress,
> enum HW_RstModule_t p, u32 *value);
>
> extern HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
> @@ -152,17 +152,18 @@ extern HW_STATUS HW_CLK_SetInputClock(const u32 baseAddress,
> enum HW_GPtimer_t gpt,
> enum HW_Clocktype_t c);
>
> -extern HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress,
> +extern HW_STATUS HW_PWR_IVA2StateGet(const void __iomem *baseAddress,
> enum HW_PwrModule_t p,
> enum HW_PwrState_t *value);
>
> -extern HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value);
> +extern HW_STATUS HW_PWRST_IVA2RegGet(const void __iomem *baseAddress,
> + u32 *value);
>
> -extern HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
> +extern HW_STATUS HW_PWR_IVA2PowerStateSet(const void __iomem *baseAddress,
> enum HW_PwrModule_t p,
> enum HW_PwrState_t value);
>
> -extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
> +extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const void __iomem *baseAddress,
> enum HW_TransitionState_t val);
>
> #endif /* __HW_PRCM_H */
> diff --git a/drivers/dsp/bridge/rmgr/drv.c b/drivers/dsp/bridge/rmgr/drv.c
> index 22faf49..07fde81
> --- a/drivers/dsp/bridge/rmgr/drv.c
> +++ b/drivers/dsp/bridge/rmgr/drv.c
> @@ -1649,15 +1649,15 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
> "%x. Not calling MEM_FreePhysMem\n",
> status);
> }
> pResources->dwMemBase[1] = 0;
> pResources->dwMemPhys[1] = 0;
>
> if (pResources->dwPrmBase)
> - iounmap((void *)pResources->dwPrmBase);
> + iounmap(pResources->dwPrmBase);
> if (pResources->dwCmBase)
> - iounmap((void *)pResources->dwCmBase);
> + iounmap(pResources->dwCmBase);
> if (pResources->dwMboxBase)
> - iounmap((void *)pResources->dwMboxBase);
> + iounmap(pResources->dwMboxBase);
> if (pResources->dwMemBase[0])
> iounmap((void *)pResources->dwMemBase[0]);
> if (pResources->dwMemBase[2])
> @@ -1667,26 +1667,26 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
> if (pResources->dwMemBase[4])
> iounmap((void *)pResources->dwMemBase[4]);
> if (pResources->dwWdTimerDspBase)
> - iounmap((void *)pResources->dwWdTimerDspBase);
> + iounmap(pResources->dwWdTimerDspBase);
> if (pResources->dwDmmuBase)
> - iounmap((void *)pResources->dwDmmuBase);
> + iounmap(pResources->dwDmmuBase);
> if (pResources->dwPerBase)
> - iounmap((void *)pResources->dwPerBase);
> + iounmap(pResources->dwPerBase);
>
> if (pResources->dwSysCtrlBase) {
> - iounmap((void *)pResources->dwSysCtrlBase);
> + iounmap(pResources->dwSysCtrlBase);
> /* don't set pResources->dwSysCtrlBase to null
> * as it is used in BOARD_Stop */
> }
> - pResources->dwPrmBase = (u32) NULL;
> - pResources->dwCmBase = (u32) NULL;
> - pResources->dwMboxBase = (u32) NULL;
> - pResources->dwMemBase[0] = (u32) NULL;
> - pResources->dwMemBase[2] = (u32) NULL;
> - pResources->dwMemBase[3] = (u32) NULL;
> - pResources->dwMemBase[4] = (u32) NULL;
> - pResources->dwWdTimerDspBase = (u32) NULL;
> - pResources->dwDmmuBase = (u32) NULL;
> + pResources->dwPrmBase = NULL;
> + pResources->dwCmBase = NULL;
> + pResources->dwMboxBase = NULL;
> + pResources->dwMemBase[0] = (u32)NULL;
> + pResources->dwMemBase[2] = (u32)NULL;
> + pResources->dwMemBase[3] = (u32)NULL;
> + pResources->dwMemBase[4] = (u32)NULL;
> + pResources->dwWdTimerDspBase = NULL;
> + pResources->dwDmmuBase = NULL;
>
> dwBuffSize = sizeof(struct CFG_HOSTRES);
> status = REG_SetValue(NULL, (char *)driverExt->szString,
> @@ -1705,13 +1705,13 @@ static DSP_STATUS RequestBridgeResources(u32 dwContext, s32 bRequest)
> pResources->wNumMemWindows = 2;
> /* First window is for DSP internal memory */
>
> - pResources->dwPrmBase = (u32)ioremap(OMAP_IVA2_PRM_BASE,
> + pResources->dwPrmBase = ioremap(OMAP_IVA2_PRM_BASE,
> OMAP_IVA2_PRM_SIZE);
> - pResources->dwCmBase = (u32)ioremap(OMAP_IVA2_CM_BASE,
> + pResources->dwCmBase = ioremap(OMAP_IVA2_CM_BASE,
> OMAP_IVA2_CM_SIZE);
> - pResources->dwMboxBase = (u32)ioremap(OMAP_MBOX_BASE,
> + pResources->dwMboxBase = ioremap(OMAP_MBOX_BASE,
> OMAP_MBOX_SIZE);
> - pResources->dwSysCtrlBase = (u32)ioremap(OMAP_SYSC_BASE,
> + pResources->dwSysCtrlBase = ioremap(OMAP_SYSC_BASE,
> OMAP_SYSC_SIZE);
> GT_1trace(curTrace, GT_2CLASS, "dwMemBase[0] 0x%x\n",
> pResources->dwMemBase[0]);
> @@ -1797,18 +1797,18 @@ static DSP_STATUS RequestBridgeResourcesDSP(u32 dwContext, s32 bRequest)
> /* wNumMemWindows must not be more than CFG_MAXMEMREGISTERS */
> pResources->wNumMemWindows = 4;
>
> pResources->dwMemBase[0] = 0;
> pResources->dwMemBase[2] = (u32)ioremap(OMAP_DSP_MEM1_BASE,
> OMAP_DSP_MEM1_SIZE);
> pResources->dwMemBase[3] = (u32)ioremap(OMAP_DSP_MEM2_BASE,
> OMAP_DSP_MEM2_SIZE);
> pResources->dwMemBase[4] = (u32)ioremap(OMAP_DSP_MEM3_BASE,
> OMAP_DSP_MEM3_SIZE);
> - pResources->dwPerBase = (u32)ioremap(OMAP_PER_CM_BASE,
> + pResources->dwPerBase = ioremap(OMAP_PER_CM_BASE,
> OMAP_PER_CM_SIZE);
> - pResources->dwDmmuBase = (u32)ioremap(OMAP_DMMU_BASE,
> + pResources->dwDmmuBase = ioremap(OMAP_DMMU_BASE,
> OMAP_DMMU_SIZE);
> - pResources->dwWdTimerDspBase = 0;
> + pResources->dwWdTimerDspBase = NULL;
>
> GT_1trace(curTrace, GT_2CLASS, "dwMemBase[0] 0x%x\n",
> pResources->dwMemBase[0]);
> diff --git a/drivers/dsp/bridge/rmgr/node.c b/drivers/dsp/bridge/rmgr/node.c
> index 1db32e9..2b029c7
> --- a/drivers/dsp/bridge/rmgr/node.c
> +++ b/drivers/dsp/bridge/rmgr/node.c
> @@ -717,7 +717,7 @@ func_cont2:
> "0x%x\n", status);
> }
>
> - ulGppMemBase = hostRes.dwMemBase[1];
> + ulGppMemBase = (u32)hostRes.dwMemBase[1];
> offSet = pulValue - dynextBase;
> ulStackSegAddr = ulGppMemBase + offSet;
> ulStackSegVal = (u32)*((REG_UWORD32 *)
> diff --git a/drivers/dsp/bridge/wmd/_tiomap.h b/drivers/dsp/bridge/wmd/_tiomap.h
> index 5267eb2..3cd2237
> --- a/drivers/dsp/bridge/wmd/_tiomap.h
> +++ b/drivers/dsp/bridge/wmd/_tiomap.h
> @@ -362,7 +362,7 @@ struct WMD_DEV_CONTEXT {
> */
> u32 dwDspExtBaseAddr; /* See the comment above */
> u32 dwAPIRegBase; /* API memory mapped registers */
> - u32 dwDSPMmuBase; /* DSP MMU Mapped registers */
> + void __iomem *dwDSPMmuBase; /* DSP MMU Mapped registers */
> u32 dwMailBoxBase; /* Mail box mapped registers */
> u32 dwAPIClkBase; /* CLK Registers */
> u32 dwDSPClkM2Base; /* DSP Clock Module m2 */
> diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c
> index 730f9b5..ad813e4
> --- a/drivers/dsp/bridge/wmd/tiomap3430.c
> +++ b/drivers/dsp/bridge/wmd/tiomap3430.c
> @@ -131,9 +131,9 @@ static DSP_STATUS PteSet(struct PgTableAttrs *pt, u32 pa, u32 va,
> static DSP_STATUS MemMapVmalloc(struct WMD_DEV_CONTEXT *hDevContext,
> u32 ulMpuAddr, u32 ulVirtAddr,
> u32 ulNumBytes, u32 ulMapAttr);
> -static DSP_STATUS run_IdleBoot(u32 prcm_base, u32 cm_base,
> - u32 sysctrl_base);
> -void GetHWRegs(u32 prcm_base, u32 cm_base);
> +static DSP_STATUS run_IdleBoot(void __iomem *prcm_base, void __iomem *cm_base,
> + void __iomem *sysctrl_base);
> +static void GetHWRegs(void __iomem *prcm_base, void __iomem *cm_base);
>
> /* ----------------------------------- Globals */
>
> @@ -505,11 +505,10 @@ static DSP_STATUS WMD_BRD_Start(struct WMD_DEV_CONTEXT *hDevContext,
> HW_MMU_TWLEnable(resources.dwDmmuBase);
> /* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
>
> - temp = (u32) *((REG_UWORD32 *)
> - ((u32) (resources.dwDmmuBase) + 0x10));
> +
> + temp = __raw_readl((resources.dwDmmuBase) + 0x10);
> temp = (temp & 0xFFFFFFEF) | 0x11;
> - *((REG_UWORD32 *) ((u32) (resources.dwDmmuBase) + 0x10)) =
> - (u32) temp;
> + __raw_writel(temp, (resources.dwDmmuBase) + 0x10);
>
> /* Let the DSP MMU run */
> HW_MMU_Enable(resources.dwDmmuBase);
> @@ -2069,8 +2068,8 @@ func_cont:
> return status;
> }
>
> -static DSP_STATUS run_IdleBoot(u32 prm_base, u32 cm_base,
> - u32 sysctrl_base)
> +static DSP_STATUS run_IdleBoot(void __iomem *prm_base, void __iomem *cm_base,
> + void __iomem *sysctrl_base)
> {
> u32 temp;
> DSP_STATUS status = DSP_SOK;
> @@ -2096,10 +2095,10 @@ static DSP_STATUS run_IdleBoot(u32 prm_base, u32 cm_base,
> }
> udelay(10);
> /* Assert IVA2-RST1 and IVA2-RST2 */
> - *((REG_UWORD32 *)((u32)(prm_base) + 0x50)) = (u32)0x07;
> + __raw_writel((u32)0x07, (prm_base) + 0x50);
> udelay(30);
> /* set the SYSC for Idle Boot */
> - *((REG_UWORD32 *)((u32)(sysctrl_base) + 0x404)) = (u32)0x01;
> + __raw_writel((u32)0x01, (sysctrl_base) + 0x404);
> clk_status = CLK_Enable(SERVICESCLK_iva2_ck);
> if (DSP_FAILED(clk_status)) {
> DBG_Trace(DBG_LEVEL6, "CLK_Enable failed for clk = 0x%x \n",
> @@ -2108,36 +2107,36 @@ static DSP_STATUS run_IdleBoot(u32 prm_base, u32 cm_base,
> udelay(20);
> GetHWRegs(prm_base, cm_base);
> /* Release Reset1 and Reset2 */
> - *((REG_UWORD32 *)((u32)(prm_base) + 0x50)) = (u32)0x05;
> + __raw_writel((u32)0x05, (prm_base) + 0x50);
> udelay(20);
> - *((REG_UWORD32 *)((u32)(prm_base) + 0x50)) = (u32)0x04;
> + __raw_writel((u32)0x04, (prm_base) + 0x50);
> udelay(30);
> return status;
> }
>
>
> -void GetHWRegs(u32 prm_base, u32 cm_base)
> +static void GetHWRegs(void __iomem *prm_base, void __iomem *cm_base)
> {
> u32 temp;
> - temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x00));
> + temp = __raw_readl((cm_base) + 0x00);
> DBG_Trace(DBG_LEVEL6, "CM_FCLKEN_IVA2 = 0x%x \n", temp);
> - temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x10));
> + temp = __raw_readl((cm_base) + 0x10);
> DBG_Trace(DBG_LEVEL6, "CM_ICLKEN1_IVA2 = 0x%x \n", temp);
> - temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x20));
> + temp = __raw_readl((cm_base) + 0x20);
> DBG_Trace(DBG_LEVEL6, "CM_IDLEST_IVA2 = 0x%x \n", temp);
> - temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x48));
> + temp = __raw_readl((cm_base) + 0x48);
> DBG_Trace(DBG_LEVEL6, "CM_CLKSTCTRL_IVA2 = 0x%x \n", temp);
> - temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0x4c));
> + temp = __raw_readl((cm_base) + 0x4c);
> DBG_Trace(DBG_LEVEL6, "CM_CLKSTST_IVA2 = 0x%x \n", temp);
> - temp = (u32)*((REG_UWORD32 *)((u32)(prm_base) + 0x50));
> + temp = __raw_readl((prm_base) + 0x50);
> DBG_Trace(DBG_LEVEL6, "RM_RSTCTRL_IVA2 = 0x%x \n", temp);
> - temp = (u32)*((REG_UWORD32 *)((u32)(prm_base) + 0x58));
> + temp = __raw_readl((prm_base) + 0x58);
> DBG_Trace(DBG_LEVEL6, "RM_RSTST_IVA2 = 0x%x \n", temp);
> - temp = (u32)*((REG_UWORD32 *)((u32)(prm_base) + 0xE0));
> + temp = __raw_readl((prm_base) + 0xE0);
> DBG_Trace(DBG_LEVEL6, "PM_PWSTCTRL_IVA2 = 0x%x \n", temp);
> - temp = (u32)*((REG_UWORD32 *)((u32)(prm_base) + 0xE4));
> + temp = __raw_readl((prm_base) + 0xE4);
> DBG_Trace(DBG_LEVEL6, "PM_PWSTST_IVA2 = 0x%x \n", temp);
> - temp = (u32)*((REG_UWORD32 *)((u32)(cm_base) + 0xA10));
> + temp = __raw_readl((cm_base) + 0xA10);
> DBG_Trace(DBG_LEVEL6, "CM_ICLKEN1_CORE = 0x%x \n", temp);
> }
>
> --
> 1.5.6.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
This also failed because of following missing commit:
commit 3b313ff3e50d3c46c506e8939f92c406aa5b0bc6
Author: Ramesh Gupta G <grgupta@ti.com>
Date: Fri Feb 13 14:51:19 2009 +0530
DSPBRIDGE DVFS and offmode support
Here are the error messages:
patching file arch/arm/plat-omap/include/dspbridge/cfgdefs.h
Hunk #1 FAILED at 96.
1 out of 1 hunk FAILED -- saving rejects to file
arch/arm/plat-omap/include/dspbridge/cfgdefs.h.rej
patching file drivers/dsp/bridge/hw/hw_dspssC64P.c
patching file drivers/dsp/bridge/hw/hw_dspssC64P.h
patching file drivers/dsp/bridge/hw/hw_mbox.c
Hunk #5 FAILED at 106.
Hunk #6 succeeded at 106 (offset -25 lines).
Hunk #7 succeeded at 128 (offset -25 lines).
Hunk #8 succeeded at 168 (offset -25 lines).
Hunk #9 succeeded at 202 (offset -25 lines).
1 out of 9 hunks FAILED -- saving rejects to file
drivers/dsp/bridge/hw/hw_mbox.c.rej
patching file drivers/dsp/bridge/hw/hw_mbox.h
Hunk #3 FAILED at 159.
Hunk #4 succeeded at 158 (offset -35 lines).
Hunk #5 succeeded at 194 (offset -35 lines).
Hunk #6 succeeded at 231 (offset -35 lines).
Hunk #7 succeeded at 270 (offset -35 lines).
Hunk #8 succeeded at 296 (offset -35 lines).
Hunk #9 succeeded at 318 (offset -35 lines).
1 out of 9 hunks FAILED -- saving rejects to file
drivers/dsp/bridge/hw/hw_mbox.h.rej
patching file drivers/dsp/bridge/hw/hw_mmu.c
patching file drivers/dsp/bridge/hw/hw_mmu.h
patching file drivers/dsp/bridge/hw/hw_prcm.c
patching file drivers/dsp/bridge/hw/hw_prcm.h
patching file drivers/dsp/bridge/rmgr/drv.c
Hunk #1 FAILED at 1649.
Hunk #2 FAILED at 1667.
Hunk #3 succeeded at 1708 (offset 3 lines).
Hunk #4 FAILED at 1800.
3 out of 4 hunks FAILED -- saving rejects to file
drivers/dsp/bridge/rmgr/drv.c.rej
patching file drivers/dsp/bridge/rmgr/node.c
Hunk #1 succeeded at 701 (offset -16 lines).
patching file drivers/dsp/bridge/wmd/_tiomap.h
patching file drivers/dsp/bridge/wmd/tiomap3430.c
Hunk #1 succeeded at 138 (offset 7 lines).
Hunk #2 succeeded at 512 (offset 7 lines).
Hunk #3 succeeded at 2104 (offset 36 lines).
Hunk #4 FAILED at 2131.
Hunk #5 succeeded at 2153 (offset 46 lines).
1 out of 5 hunks FAILED -- saving rejects to file
drivers/dsp/bridge/wmd/tiomap3430.c.rej
Cheers,
Ameya.
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2009-03-05 10:22 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-03-04 18:11 [PATCH] DSPBRIDGE: Remove SEEK_* redefinitions Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Removes wrappers funtions of readl and writel Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Change address resources to void __iomem * Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: cleanup of HW_MBOX_IsFull function Fernando Guzman Lugo
2009-03-04 18:11 ` [PATCH] DSPBRIDGE: wait less and check the mailbox more Fernando Guzman Lugo
2009-03-05 10:14 ` [PATCH] DSPBRIDGE: Remove variables not used in cfgdefs.h Ameya Palande
2009-03-05 10:22 ` [PATCH] DSPBRIDGE: Change address resources to void __iomem * Ameya Palande
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