* [U-Boot] [PATCH] mpc512x: Add esd gmbh mecp5123 board support
@ 2009-06-08 7:54 Stefan Roese
2009-06-08 10:38 ` Wolfgang Denk
0 siblings, 1 reply; 5+ messages in thread
From: Stefan Roese @ 2009-06-08 7:54 UTC (permalink / raw)
To: u-boot
MECP5123 is a MPC5121E based module by esd gmbh.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +
board/esd/mecp5123/Makefile | 50 +++++
board/esd/mecp5123/config.mk | 23 ++
board/esd/mecp5123/mecp5123.c | 360 ++++++++++++++++++++++++++++++++
include/configs/mecp5123.h | 455 +++++++++++++++++++++++++++++++++++++++++
7 files changed, 893 insertions(+), 0 deletions(-)
create mode 100644 board/esd/mecp5123/Makefile
create mode 100644 board/esd/mecp5123/config.mk
create mode 100644 board/esd/mecp5123/mecp5123.c
create mode 100644 include/configs/mecp5123.h
diff --git a/MAINTAINERS b/MAINTAINERS
index bba6ce9..942e9de 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -28,6 +28,7 @@ Pantelis Antoniou <panto@intracom.gr>
Reinhard Arlt <reinhard.arlt@esd-electronics.com>
cpci5200 MPC5200
+ mecp5123 MPC5121
mecp5200 MPC5200
pf5200 MPC5200
diff --git a/MAKEALL b/MAKEALL
index fd31252..f48a08e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -78,6 +78,7 @@ LIST_5xxx=" \
LIST_512x=" \
aria \
+ mecp5123 \
mpc5121ads \
"
diff --git a/Makefile b/Makefile
index 034441c..2540f74 100644
--- a/Makefile
+++ b/Makefile
@@ -815,6 +815,9 @@ v38b_config: unconfig
aria_config: unconfig
@$(MKCONFIG) -a aria ppc mpc512x aria davedenx
+mecp5123_config: unconfig
+ @$(MKCONFIG) -a mecp5123 ppc mpc512x mecp5123 esd
+
mpc5121ads_config \
mpc5121ads_rev2_config \
: unconfig
diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile
new file mode 100644
index 0000000..2e3d73a
--- /dev/null
+++ b/board/esd/mecp5123/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+
+COBJS := $(COBJS-y)
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/mecp5123/config.mk b/board/esd/mecp5123/config.mk
new file mode 100644
index 0000000..838a018
--- /dev/null
+++ b/board/esd/mecp5123/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFF00000
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
new file mode 100644
index 0000000..29f9960
--- /dev/null
+++ b/board/esd/mecp5123/mecp5123.c
@@ -0,0 +1,360 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
+ CLOCK_SCCR1_LPC_EN | \
+ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
+ CLOCK_SCCR1_PSCFIFO_EN | \
+ CLOCK_SCCR1_DDR_EN | \
+ CLOCK_SCCR1_FEC_EN | \
+ CLOCK_SCCR1_NFC_EN | \
+ CLOCK_SCCR1_PCI_EN | \
+ CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
+ CLOCK_SCCR2_I2C_EN)
+
+#define CSAW_START(start) ((start) & 0xFFFF0000)
+#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
+
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+ if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
+ return -1;
+
+ if (state == 0)
+ setbits_be32(&im->gpio.gpdat, 0x00100000);
+ else
+ clrbits_be32(&im->gpio.gpdat, 0x00100000);
+
+ return 0;
+}
+
+/*
+ * According to MPC5121e RM, configuring local access windows should
+ * be followed by a dummy read of the config register that was
+ * modified last and an isync.
+ */
+static inline void sync_law(volatile void *addr)
+{
+ in_be32(addr);
+ __asm__ __volatile__ ("isync");
+}
+
+int board_early_init_f(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 spridr;
+
+ /*
+ * Initialize Local Window for NOR FLASH access
+ */
+ out_be32(&im->sysconf.lpcs0aw,
+ CSAW_START(CONFIG_SYS_FLASH_BASE) |
+ CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
+ sync_law(&im->sysconf.lpcs0aw);
+
+ /*
+ * Initialize Local Window for boot access
+ */
+ out_be32(&im->sysconf.lpbaw,
+ CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
+ sync_law(&im->sysconf.lpbaw);
+
+ /*
+ * Initialize Local Window for VPC3 access
+ */
+ out_be32(&im->sysconf.lpcs1aw,
+ CSAW_START(CONFIG_SYS_VPC3_BASE) |
+ CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE));
+ sync_law(&im->sysconf.lpcs1aw);
+
+ /*
+ * Configure Flash Speed
+ */
+ out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+
+ /*
+ * Configure VPC3 Speed
+ */
+ out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
+
+ spridr = in_be32(&im->sysconf.spridr);
+ if (SVR_MJREV(spridr) >= 2)
+ out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+ /*
+ * Enable clocks
+ */
+ out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+ out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+ setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+ /*
+ * Configure MSCAN clocks
+ */
+ out_be32(&im->clk.m1ccr, 0x00300000);
+ out_be32(&im->clk.m2ccr, 0x00300000);
+ out_be32(&im->clk.m3ccr, 0x00300000);
+ out_be32(&im->clk.m4ccr, 0x00300000);
+ out_be32(&im->clk.m1ccr, 0x00310000);
+ out_be32(&im->clk.m2ccr, 0x00310000);
+ out_be32(&im->clk.m3ccr, 0x00310000);
+ out_be32(&im->clk.m4ccr, 0x00310000);
+
+ /*
+ * Configure GPIO's
+ */
+ clrbits_be32(&im->gpio.gpodr, 0x000000e0);
+ clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
+ setbits_be32(&im->gpio.gpdir, 0x001000e0);
+ setbits_be32(&im->gpio.gpdat, 0x00100000);
+
+ return 0;
+}
+
+/*
+ * fixed sdram init:
+ * The board doesn't use memory modules that have serial presence
+ * detect or similar mechanism for discovery of the DRAM settings
+ */
+long int fixed_sdram(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+ u32 msize_log2 = __ilog2(msize);
+ u32 i;
+
+ /* Initialize IO Control */
+ out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+
+ /* Initialize DDR Local Window */
+ out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
+ out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
+ sync_law(&im->sysconf.ddrlaw.ar);
+
+ /* Enable DDR */
+ out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
+
+ /* Initialize DDR Priority Manager */
+ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
+ out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
+ out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
+ out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
+ out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
+ out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
+ out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
+ out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
+ out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
+ out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
+ out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
+ out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
+ out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
+ out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
+ out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
+ out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
+ out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
+ out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
+ out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
+ out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
+ out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
+ out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
+ out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
+
+ /* Initialize MDDRC */
+ out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
+ out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
+ out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
+ out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
+
+ /* Initialize DDR */
+ for (i = 0; i < 10; i++)
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+ out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+ /* Start MDDRC */
+ out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
+ out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
+
+ return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+ return fixed_sdram();
+}
+
+int misc_init_r(void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+
+ clrbits_be32(&im->clk.scfr[0], 0x00003800);
+ setbits_be32(&im->clk.scfr[0], 0x01 << 11);
+ clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
+ setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
+ clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
+ setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
+
+ return 0;
+}
+
+static iopin_t ioregs_init[] = {
+ /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+ {
+ offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+ {
+ offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+ IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC1=SELECT LPC_CS1 */
+ {
+ offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC5_2 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
+ IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC5_3 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC7_3 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC9_0 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC10_0 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC10_3 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC3=SELECT PSC11_0 */
+ {
+ offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
+ IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ },
+ /* FUNC0=SELECT IRQ0 */
+ {
+ offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+ IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+ }
+};
+
+static iopin_t rev2_silicon_pci_ioregs_init[] = {
+ /* FUNC0=PCI Sets next 54 to PCI pads */
+ {
+ offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+ IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+ }
+};
+
+int checkboard(void)
+{
+ volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+ u32 spridr;
+
+ puts("Board: MECP_5123\n");
+
+ /*
+ * Initialize function mux & slew rate IO inter alia on IO
+ * Pins
+ */
+ iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+ spridr = in_be32(&im->sysconf.spridr);
+ if (SVR_MJREV(spridr) >= 2)
+ iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+ fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
new file mode 100644
index 0000000..4c3428e
--- /dev/null
+++ b/include/configs/mecp5123.h
@@ -0,0 +1,455 @@
+/*
+ * (C) Copyright 2007, 2008 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the MECP5123 by reinhard.arlt at esd-electronics.com
+ *
+ */
+
+/*
+ * MECP5123 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MECP5123 1
+/*
+ * Memory map for the MECP5123 board:
+ *
+ * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
+ * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_FFFF VPC-3 (64 KB)
+ * 0xFFC0_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC512X 1 /* MPC512X family */
+
+#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR 0x80000000
+#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
+
+#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END 0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CONFIG_SYS_DDR_SIZE 512 /* MB */
+
+#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ * [31:31] MDDRC Soft Reset: Diabled
+ * [30:30] DRAM CKE pin: Enabled
+ * [29:29] DRAM CLK: Enabled
+ * [28:28] Command Mode: Enabled (For initialization only)
+ * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
+ * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
+ * [20:19] Read Test: DON'T USE
+ * [18:18] Self Refresh: Enabled
+ * [17:17] 16bit Mode: Disabled
+ * [16:13] Ready Delay: 2
+ * [12:12] Half DQS Delay: Disabled
+ * [11:11] Quarter DQS Delay: Disabled
+ * [10:08] Write Delay: 2
+ * [07:07] Early ODT: Disabled
+ * [06:06] On DIE Termination: Disabled
+ * [05:05] FIFO Overflow Clear: DON'T USE here
+ * [04:04] FIFO Underflow Clear: DON'T USE here
+ * [03:03] FIFO Overflow Pending: DON'T USE here
+ * [02:02] FIFO Underlfow Pending: DON'T USE here
+ * [01:01] FIFO Overlfow Enabled: Enabled
+ * [00:00] FIFO Underflow Enabled: Enabled
+ * TIME_CFG0
+ * [31:16] DRAM Refresh Time: 0 CSB clocks
+ * [15:8] DRAM Command Time: 0 CSB clocks
+ * [07:00] DRAM Precharge Time: 0 CSB clocks
+ * TIME_CFG1
+ * [31:26] DRAM tRFC:
+ * [25:21] DRAM tWR1:
+ * [20:17] DRAM tWRT1:
+ * [16:11] DRAM tDRR:
+ * [10:05] DRAM tRC:
+ * [04:00] DRAM tRAS:
+ * TIME_CFG2
+ * [31:28] DRAM tRCD:
+ * [27:23] DRAM tFAW:
+ * [22:19] DRAM tRTW1:
+ * [18:15] DRAM tCCD:
+ * [14:10] DRAM tRTP:
+ * [09:05] DRAM tRP:
+ * [04:00] DRAM tRPA
+ */
+#ifdef CONFIG_ADS5121_REV2
+#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
+#else
+#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
+#endif
+#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
+#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E
+
+#define CONFIG_SYS_MICRON_NOP 0x01380000
+#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
+#define CONFIG_SYS_MICRON_EM2 0x01020000
+#define CONFIG_SYS_MICRON_EM3 0x01030000
+#define CONFIG_SYS_MICRON_EN_DLL 0x01010000
+#define CONFIG_SYS_MICRON_RFSH 0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
+#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
+
+#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size in bytes */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * NAND FLASH
+ * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon only)
+ */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_MPC5121_NFC
+#define CONFIG_SYS_NAND_BASE 0x40000000
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH 1
+#define CONFIG_FSL_NFC_WRITE_SIZE 2048
+#define CONFIG_FSL_NFC_SPARE_SIZE 64
+#define CONFIG_FSL_NFC_CHIPS 1
+
+#define CONFIG_SYS_SRAM_BASE 0x30000000
+#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
+
+#define CONFIG_SYS_CS0_CFG 0x05051150 /* ALE active low, data size 4bytes */
+
+#define CONFIG_SYS_CS_ALETIMING 0x00000000 /* Use not alternative CS timing */
+
+#define CONFIG_SYS_CS1_CFG 0x1f1f3090 /* ALE active low, data size 4bytes */
+#define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */
+#define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size in bytes */
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_IIM
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */
+#define CONFIG_SYS_EEPROM_WREN 1 /* Use EEPROM write protect */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC 1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR 0x1
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_FEC_AN_TIMEOUT 1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_SYS_RTC_BUS_NUM 0x01
+#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#define CONFIG_RTC_RX8025
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_EEPROM /* Store env in I2C EEPROM */
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */
+
+#define CONFIG_LOADS_ECHO /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#undef CONFIG_CMD_FUSE
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_ELF
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5121e Reference Manual.
+ */
+/* #define CONFIG_WATCHDOG */ /* enable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 32
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE 32768
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_HIGH_BATS 1 /* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME mecp512x
+#define CONFIG_BOOTFILE /tftpboot/mecp512x/uImage
+#define CONFIG_ROOTPATH /tftpboot/mecp512x/target_root
+
+#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Welcome to MECP5123" \
+ "echo"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "u-boot_addr_r=200000\0" \
+ "kernel_addr_r=600000\0" \
+ "fdt_addr_r=880000\0" \
+ "ramdisk_addr_r=900000\0" \
+ "u-boot_addr=FFF00000\0" \
+ "kernel_addr=FFC40000\0" \
+ "fdt_addr=FFEC0000\0" \
+ "ramdisk_addr=FC040000\0" \
+ "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \
+ "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \
+ "bootfile=/tftpboot/mecp512x/uImage\0" \
+ "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \
+ "rootpath=/tftpboot/mecp512x/target_root\n" \
+ "netdev=eth0\0" \
+ "consdev=ttyPSC0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} - ${fdt_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${fdt_addr_r} ${fdtfile};" \
+ "run nfsargs addip addtty;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "net_self=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
+ "tftp ${fdt_addr_r} ${fdtfile};" \
+ "run ramargs addip addtty;" \
+ "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+ "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
+ "update=protect off ${u-boot_addr} +${filesize};" \
+ "era ${u-boot_addr} +${filesize};" \
+ "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
+ "upd=run load update\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
+
+#define OF_CPU "PowerPC,5121@0"
+#define OF_SOC_COMPAT "fsl,mpc5121-immr"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc at 80000000/serial at 11300"
+
+#endif /* __CONFIG_H */
--
1.6.3.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] mpc512x: Add esd gmbh mecp5123 board support
2009-06-08 7:54 [U-Boot] [PATCH] mpc512x: Add esd gmbh mecp5123 board support Stefan Roese
@ 2009-06-08 10:38 ` Wolfgang Denk
2009-06-08 17:37 ` Stefan Roese
0 siblings, 1 reply; 5+ messages in thread
From: Wolfgang Denk @ 2009-06-08 10:38 UTC (permalink / raw)
To: u-boot
Dear Stefan Roese,
In message <1244447665-14264-1-git-send-email-sr@denx.de> you wrote:
> MECP5123 is a MPC5121E based module by esd gmbh.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
...
> +int eeprom_write_enable(unsigned dev_addr, int state)
> +{
> + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> +
> + if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
> + return -1;
> +
> + if (state == 0)
> + setbits_be32(&im->gpio.gpdat, 0x00100000);
> + else
> + clrbits_be32(&im->gpio.gpdat, 0x00100000);
> +
> + return 0;
> +}
Please fix indentation - indentation by TAB only, please.
...
> +int board_early_init_f(void)
> +{
...
> + /* Initialize DDR Priority Manager */
> + out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
> + out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
> + out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
> + out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
> + out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
> + out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
> + out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
> + out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
> + out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
> + out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
> + out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
> + out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
> + out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
> + out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
> + out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
> + out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
> + out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
> + out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
> + out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
> + out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
> + out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
> + out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
> + out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
Lines too long.
> +phys_size_t initdram(int board_type)
> +{
> + return fixed_sdram();
> +}
Use auto-sizing?
> +int misc_init_r(void)
> +{
> + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> +
> + clrbits_be32(&im->clk.scfr[0], 0x00003800);
> + setbits_be32(&im->clk.scfr[0], 0x01 << 11);
> + clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
> + setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
> + clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
> + setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
Please add some comments what you are doing here, and eventually
#define the magic constants used.
...
> --- /dev/null
> +++ b/include/configs/mecp5123.h
> @@ -0,0 +1,455 @@
> +/*
> + * (C) Copyright 2007, 2008 DENX Software Engineering
2009?
...
> +/*
> + * NOR FLASH on the Local Bus
> + */
> +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
> +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
> +
> +#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */
> +#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size in bytes */
Lines too long (check everywhere!)
...
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "u-boot_addr_r=200000\0" \
> + "kernel_addr_r=600000\0" \
> + "fdt_addr_r=880000\0" \
> + "ramdisk_addr_r=900000\0" \
> + "u-boot_addr=FFF00000\0" \
> + "kernel_addr=FFC40000\0" \
> + "fdt_addr=FFEC0000\0" \
> + "ramdisk_addr=FC040000\0" \
> + "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \
> + "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \
> + "bootfile=/tftpboot/mecp512x/uImage\0" \
> + "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \
> + "rootpath=/tftpboot/mecp512x/target_root\n" \
> + "netdev=eth0\0" \
> + "consdev=ttyPSC0\0" \
> + "nfsargs=setenv bootargs root=/dev/nfs rw " \
> + "nfsroot=${serverip}:${rootpath}\0" \
> + "ramargs=setenv bootargs root=/dev/ram rw\0" \
> + "addip=setenv bootargs ${bootargs} " \
> + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> + ":${hostname}:${netdev}:off panic=1\0" \
> + "addtty=setenv bootargs ${bootargs} " \
> + "console=${consdev},${baudrate}\0" \
> + "flash_nfs=run nfsargs addip addtty;" \
> + "bootm ${kernel_addr} - ${fdt_addr}\0" \
> + "flash_self=run ramargs addip addtty;" \
> + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
> + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
> + "tftp ${fdt_addr_r} ${fdtfile};" \
> + "run nfsargs addip addtty;" \
> + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
> + "net_self=tftp ${kernel_addr_r} ${bootfile};" \
> + "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
> + "tftp ${fdt_addr_r} ${fdtfile};" \
> + "run ramargs addip addtty;" \
> + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
> + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
> + "update=protect off ${u-boot_addr} +${filesize};" \
> + "era ${u-boot_addr} +${filesize};" \
> + "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
> + "upd=run load update\0" \
> + ""
How long does it to boot with such an environment in EEPROM?
> +#define CONFIG_OF_LIBFDT 1
> +#define CONFIG_OF_BOARD_SETUP 1
> +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
Do you really need this on a new board?
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"I'm growing older, but not up." - Jimmy Buffett
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] mpc512x: Add esd gmbh mecp5123 board support
2009-06-08 10:38 ` Wolfgang Denk
@ 2009-06-08 17:37 ` Stefan Roese
2009-06-08 18:14 ` Wolfgang Denk
0 siblings, 1 reply; 5+ messages in thread
From: Stefan Roese @ 2009-06-08 17:37 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
On Monday 08 June 2009 12:38:18 Wolfgang Denk wrote:
> > +int eeprom_write_enable(unsigned dev_addr, int state)
> > +{
> > + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
> > +
> > + if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
> > + return -1;
> > +
> > + if (state == 0)
> > + setbits_be32(&im->gpio.gpdat, 0x00100000);
> > + else
> > + clrbits_be32(&im->gpio.gpdat, 0x00100000);
> > +
> > + return 0;
> > +}
>
> Please fix indentation - indentation by TAB only, please.
OK.
> ...
>
> > +int board_early_init_f(void)
> > +{
>
> ...
>
> > + /* Initialize DDR Priority Manager */
> > + out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
> > + out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
> > + out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
> > + out_be32(&im->mddrc.lut_table0_main_upper,
> > CONFIG_SYS_MDDRCGRP_LUT0_MU);
> > + out_be32(&im->mddrc.lut_table0_main_lower,
> > CONFIG_SYS_MDDRCGRP_LUT0_ML);
> > + out_be32(&im->mddrc.lut_table1_main_upper,
> > CONFIG_SYS_MDDRCGRP_LUT1_MU);
> > + out_be32(&im->mddrc.lut_table1_main_lower,
> > CONFIG_SYS_MDDRCGRP_LUT1_ML);
> > + out_be32(&im->mddrc.lut_table2_main_upper,
> > CONFIG_SYS_MDDRCGRP_LUT2_MU);
> > + out_be32(&im->mddrc.lut_table2_main_lower,
> > CONFIG_SYS_MDDRCGRP_LUT2_ML);
> > + out_be32(&im->mddrc.lut_table3_main_upper,
> > CONFIG_SYS_MDDRCGRP_LUT3_MU);
> > + out_be32(&im->mddrc.lut_table3_main_lower,
> > CONFIG_SYS_MDDRCGRP_LUT3_ML);
> > + out_be32(&im->mddrc.lut_table4_main_upper,
> > CONFIG_SYS_MDDRCGRP_LUT4_MU);
> > + out_be32(&im->mddrc.lut_table4_main_lower,
> > CONFIG_SYS_MDDRCGRP_LUT4_ML);
> > + out_be32(&im->mddrc.lut_table0_alternate_upper,
> > CONFIG_SYS_MDDRCGRP_LUT0_AU);
> > + out_be32(&im->mddrc.lut_table0_alternate_lower,
> > CONFIG_SYS_MDDRCGRP_LUT0_AL);
> > + out_be32(&im->mddrc.lut_table1_alternate_upper,
> > CONFIG_SYS_MDDRCGRP_LUT1_AU);
> > + out_be32(&im->mddrc.lut_table1_alternate_lower,
> > CONFIG_SYS_MDDRCGRP_LUT1_AL);
> > + out_be32(&im->mddrc.lut_table2_alternate_upper,
> > CONFIG_SYS_MDDRCGRP_LUT2_AU);
> > + out_be32(&im->mddrc.lut_table2_alternate_lower,
> > CONFIG_SYS_MDDRCGRP_LUT2_AL);
> > + out_be32(&im->mddrc.lut_table3_alternate_upper,
> > CONFIG_SYS_MDDRCGRP_LUT3_AU);
> > + out_be32(&im->mddrc.lut_table3_alternate_lower,
> > CONFIG_SYS_MDDRCGRP_LUT3_AL);
> > + out_be32(&im->mddrc.lut_table4_alternate_upper,
> > CONFIG_SYS_MDDRCGRP_LUT4_AU);
> > + out_be32(&im->mddrc.lut_table4_alternate_lower,
> > CONFIG_SYS_MDDRCGRP_LUT4_AL);
>
> Lines too long.
OK. Some is true for aria and mcp5121ads btw. But I'll change it in the next
patch version.
> > +phys_size_t initdram(int board_type)
> > +{
> > + return fixed_sdram();
> > +}
>
> Use auto-sizing?
You refer to using get_ram_size()? I'm no big fan of using this routine in a
fixed environment (only one soldering possibility). But ok, I can change this
too.
BTW, again this is the same code as in aria.
> > +int misc_init_r(void)
> > +{
> > + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
> > +
> > + clrbits_be32(&im->clk.scfr[0], 0x00003800);
> > + setbits_be32(&im->clk.scfr[0], 0x01 << 11);
> > + clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
> > + setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
> > + clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
> > + setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
>
> Please add some comments what you are doing here, and eventually
> #define the magic constants used.
OK.
> > --- /dev/null
> > +++ b/include/configs/mecp5123.h
> > @@ -0,0 +1,455 @@
> > +/*
> > + * (C) Copyright 2007, 2008 DENX Software Engineering
>
> 2009?
OK.
> > +/*
> > + * NOR FLASH on the Local Bus
> > + */
> > +#define CONFIG_SYS_FLASH_CFI /* use the Common
Flash Interface */
> > +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI
driver */
> > +
> > +#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH
*/
> > +#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size
in bytes */
>
> Lines too long (check everywhere!)
OK.
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > + "u-boot_addr_r=200000\0" \
> > + "kernel_addr_r=600000\0" \
> > + "fdt_addr_r=880000\0" \
> > + "ramdisk_addr_r=900000\0" \
> > + "u-boot_addr=FFF00000\0" \
> > + "kernel_addr=FFC40000\0" \
> > + "fdt_addr=FFEC0000\0" \
> > + "ramdisk_addr=FC040000\0" \
> > + "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \
> > + "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \
> > + "bootfile=/tftpboot/mecp512x/uImage\0" \
> > + "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \
> > + "rootpath=/tftpboot/mecp512x/target_root\n" \
> > + "netdev=eth0\0" \
> > + "consdev=ttyPSC0\0" \
> > + "nfsargs=setenv bootargs root=/dev/nfs rw " \
> > + "nfsroot=${serverip}:${rootpath}\0" \
> > + "ramargs=setenv bootargs root=/dev/ram rw\0" \
> > + "addip=setenv bootargs ${bootargs} " \
> > + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
> > + ":${hostname}:${netdev}:off panic=1\0" \
> > + "addtty=setenv bootargs ${bootargs} " \
> > + "console=${consdev},${baudrate}\0" \
> > + "flash_nfs=run nfsargs addip addtty;" \
> > + "bootm ${kernel_addr} - ${fdt_addr}\0" \
> > + "flash_self=run ramargs addip addtty;" \
> > + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
> > + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
> > + "tftp ${fdt_addr_r} ${fdtfile};" \
> > + "run nfsargs addip addtty;" \
> > + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
> > + "net_self=tftp ${kernel_addr_r} ${bootfile};" \
> > + "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
> > + "tftp ${fdt_addr_r} ${fdtfile};" \
> > + "run ramargs addip addtty;" \
> > + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
> > + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
> > + "update=protect off ${u-boot_addr} +${filesize};" \
> > + "era ${u-boot_addr} +${filesize};" \
> > + "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
> > + "upd=run load update\0" \
> > + ""
>
> How long does it to boot with such an environment in EEPROM?
Quite long. About 10 seconds to the U-Boot prompt.
> > +#define CONFIG_OF_LIBFDT 1
> > +#define CONFIG_OF_BOARD_SETUP 1
> > +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
>
> Do you really need this on a new board?
Probably not. Again this is just a copy from aria. I'll remove it in the next
patch version.
Thanks.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] mpc512x: Add esd gmbh mecp5123 board support
2009-06-08 17:37 ` Stefan Roese
@ 2009-06-08 18:14 ` Wolfgang Denk
2009-06-09 7:24 ` Stefan Roese
0 siblings, 1 reply; 5+ messages in thread
From: Wolfgang Denk @ 2009-06-08 18:14 UTC (permalink / raw)
To: u-boot
Dear Stefan,
In message <200906081937.02354.sr@denx.de> you wrote:
>
> > > + out_be32(&im->mddrc.lut_table4_alternate_upper,
> > > CONFIG_SYS_MDDRCGRP_LUT4_AU);
> > > + out_be32(&im->mddrc.lut_table4_alternate_lower,
> > > CONFIG_SYS_MDDRCGRP_LUT4_AL);
> >
> > Lines too long.
>
> OK. Some is true for aria and mcp5121ads btw. But I'll change it in the next
> patch version.
If you argument that the too long lines are easier to read then the
wrapped ones, I will not fight about this :-)
> > > +phys_size_t initdram(int board_type)
> > > +{
> > > + return fixed_sdram();
> > > +}
> >
> > Use auto-sizing?
>
> You refer to using get_ram_size()? I'm no big fan of using this routine in a
> fixed environment (only one soldering possibility). But ok, I can change this
> too.
Yes, I stronlgy recommend to use this even on fixed configurations.
Keep in mind that it includes a very fast yet pretty efficient memory
test that will catch 95% of all RAM issues. It's a great help not
only for the board bringup, but also for diabnosing problems in the
field. If I could, I would like to make the use of get_ram_size()
mandatory :-)
> BTW, again this is the same code as in aria.
I know. It's on my list of things to iron out in this port.
> > How long does it to boot with such an environment in EEPROM?
>
> Quite long. About 10 seconds to the U-Boot prompt.
He. And then try "setenv baudrate 115200 ; saveenv" and measure again.
Does your customer really want to release such a product to his
customers? Other boards boot in a fraction of that time.
> > > +#define CONFIG_OF_LIBFDT 1
> > > +#define CONFIG_OF_BOARD_SETUP 1
> > > +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
> >
> > Do you really need this on a new board?
>
> Probably not. Again this is just a copy from aria. I'll remove it in the next
> patch version.
Thanks for pointing out. I put it on my cleanup list, too.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Include the success of others in your dreams for your own success.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] mpc512x: Add esd gmbh mecp5123 board support
2009-06-08 18:14 ` Wolfgang Denk
@ 2009-06-09 7:24 ` Stefan Roese
0 siblings, 0 replies; 5+ messages in thread
From: Stefan Roese @ 2009-06-09 7:24 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
On Monday 08 June 2009 20:14:33 Wolfgang Denk wrote:
> Dear Stefan,
>
> In message <200906081937.02354.sr@denx.de> you wrote:
> > > > + out_be32(&im->mddrc.lut_table4_alternate_upper,
> > > > CONFIG_SYS_MDDRCGRP_LUT4_AU);
> > > > + out_be32(&im->mddrc.lut_table4_alternate_lower,
> > > > CONFIG_SYS_MDDRCGRP_LUT4_AL);
> > >
> > > Lines too long.
> >
> > OK. Some is true for aria and mcp5121ads btw. But I'll change it in the
> > next patch version.
>
> If you argument that the too long lines are easier to read then the
> wrapped ones, I will not fight about this :-)
Yes, sometimes I really prefer these "too long lines" because it's just better
readable. I'll keep this code part as is then. :)
> > > How long does it to boot with such an environment in EEPROM?
> >
> > Quite long. About 10 seconds to the U-Boot prompt.
>
> He. And then try "setenv baudrate 115200 ; saveenv" and measure again.
About 6 seconds.
> Does your customer really want to release such a product to his
> customers? Other boards boot in a fraction of that time.
I know. I asked again. Please accept the EEPROM decision for now.
Best regards,
Stefan
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2009-06-09 7:24 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-06-08 7:54 [U-Boot] [PATCH] mpc512x: Add esd gmbh mecp5123 board support Stefan Roese
2009-06-08 10:38 ` Wolfgang Denk
2009-06-08 17:37 ` Stefan Roese
2009-06-08 18:14 ` Wolfgang Denk
2009-06-09 7:24 ` Stefan Roese
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