[U-Boot] [PATCH v2 0/5] Add boot from NAND/eSDHC/eSPI support

[U-Boot] [PATCH v2 0/5] Add boot from NAND/eSDHC/eSPI support

[Mingkai Hu]

These patches implement boot from NAND/eSDHC/eSPI in a unified way - all of
these use the general file cpu/mpc85xx/start.S and load the image into L2SRAM.

Modification over v1:
 - Align to the latest tree: http://git.denx.de/u-boot-mpc85xx.git
 - Align the NAND board make config to the latest mkconfig mofication 
 - Split the "save env variables to SDCard" patches to another patchset,
   so patch 4 doesn't depend on that patchset.
 - Some cleanup work

The general modification for 85xx platform:
[PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

Add support for boot from NAND:
[PATCH v2 2/5] NAND boot: change NAND loader's relocate SP to CONFIG param
[PATCH v2 3/5] NAND boot: MPC8536DS support

Add support for boot from eSDHC and eSPI:
[PATCH v2 4/5] On-chip ROM boot: MPC8536DS support

[PATCH v2 5/5] Add README.mpc8536ds

[U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

[Mingkai Hu]

The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.

For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.

When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NADN loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.

When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.

The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
---
 cpu/mpc85xx/cpu_init.c |   19 +++++++++++++++++++
 cpu/mpc85xx/start.S    |   23 ++++++++++++++++++++++-
 cpu/mpc85xx/tlb.c      |    6 ++++++
 drivers/misc/fsl_law.c |    2 ++
 4 files changed, 49 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a54cf5d..5f66511 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -291,6 +291,25 @@ int cpu_init_r(void)
 
 	asm("msync;isync");
 	cache_ctl = l2cache->l2ctl;
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	if (cache_ctl & MPC85xx_L2CTL_L2E) {
+		/* Clear L2 SRAM memory-mapped base address */
+		out_be32(&l2cache->l2srbar0, 0x0);
+		out_be32(&l2cache->l2srbar1, 0x0);
+
+		/* set MBECCDIS=0, SBECCDIS=0 */
+		clrbits_be32(&l2cache->l2errdis,
+				(MPC85xx_L2ERRDIS_MBECC |
+				 MPC85xx_L2ERRDIS_SBECC));
+
+		/* set L2E=0, L2SRAM=0 */
+		clrbits_be32(&l2cache->l2ctl,
+				(MPC85xx_L2CTL_L2E |
+				 MPC85xx_L2CTL_L2SRAM_ENTIRE));
+	}
+#endif
+
 	l2siz_field = (cache_ctl >> 28) & 0x3;
 
 	switch (l2siz_field) {
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index e21a4eb..c5b6bd9 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -57,10 +57,12 @@
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
 
+#ifndef CONFIG_NAND_SPL
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
 	GOT_ENTRY(_end_of_vectors)
 	GOT_ENTRY(transfer_to_handler)
+#endif
 
 	GOT_ENTRY(__init_end)
 	GOT_ENTRY(_end)
@@ -235,10 +237,11 @@ _start_e500:
 
 #endif /* CONFIG_MPC8569 */
 
-	/* create a temp mapping in AS=1 to the 4M boot window */
 	lis     r6,FSL_BOOKE_MAS0(1, 15, 0)@h
 	ori     r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
 
+#ifndef CONFIG_SYS_RAMBOOT
+	/* create a temp mapping in AS=1 to the 4M boot window */
 	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
 	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
 
@@ -248,6 +251,20 @@ _start_e500:
 	/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
 	lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
 	ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#else
+	/*
+	 * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
+	 * image has been relocated to TEXT_BASE on the second stage.
+	 */
+	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
+	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
+
+	lis     r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
+	ori     r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+
+	lis     r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+	ori     r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#endif
 
 	mtspr   MAS0,r6
 	mtspr   MAS1,r7
@@ -359,6 +376,7 @@ _start_cont:
 	bl	board_init_f
 	isync
 
+#ifndef CONFIG_NAND_SPL
 	. = EXC_OFF_SYS_RESET
 	.globl	_start_of_vectors
 _start_of_vectors:
@@ -813,6 +831,7 @@ in32:
 in32r:
 	lwbrx	r3,r0,r3
 	blr
+#endif  /* !CONFIG_NAND_SPL */
 
 /*------------------------------------------------------------------------------*/
 
@@ -975,6 +994,7 @@ clear_bss:
 	mr	r4,r10		/* Destination Address		*/
 	bl	board_init_r
 
+#ifndef CONFIG_NAND_SPL
 	/*
 	 * Copy exception vector code to low memory
 	 *
@@ -1128,3 +1148,4 @@ setup_ivors:
 
 #include "fixed_ivor.S"
 	blr
+#endif /* !CONFIG_NAND_SPL */
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 0497a29..9c7c928 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -59,6 +59,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
 #endif
 }
 
+#ifndef CONFIG_NAND_SPL
 void disable_tlb(u8 esel)
 {
 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
@@ -83,6 +84,7 @@ void disable_tlb(u8 esel)
 		addrmap_set_entry(0, 0, 0, esel);
 #endif
 }
+#endif
 
 void invalidate_tlb(u8 tlb)
 {
@@ -106,6 +108,7 @@ void init_tlbs(void)
 	return ;
 }
 
+#ifdef CONFIG_ADDR_MAP
 static void tlbsx (const volatile unsigned *addr)
 {
 	__asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
@@ -132,6 +135,7 @@ int find_tlb_idx(void *addr, u8 tlbsel)
 
 	return -1;
 }
+#endif
 
 #ifdef CONFIG_ADDR_MAP
 void init_addr_map(void)
@@ -168,6 +172,7 @@ void init_addr_map(void)
 }
 #endif
 
+#ifndef CONFIG_NAND_SPL
 #ifndef CONFIG_SYS_DDR_TLB_START
 #define CONFIG_SYS_DDR_TLB_START 8
 #endif
@@ -215,3 +220,4 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 	 */
 	return memsize_in_meg;
 }
+#endif /* !CONFIG_NAND_SPL */
diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c
index 7bdd355..aa877c6 100644
--- a/drivers/misc/fsl_law.c
+++ b/drivers/misc/fsl_law.c
@@ -74,6 +74,7 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 	return idx;
 }
 
+#ifndef CONFIG_NAND_SPL
 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {
 	u32 idx;
@@ -166,6 +167,7 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 
 	return 0;
 }
+#endif
 
 void init_laws(void)
 {
-- 
1.6.4

[U-Boot] [PATCH v2 2/5] NAND boot: change NAND loader's relocate SP to CONFIG param

[Mingkai Hu]

So that we can set the NAND loader's relocate stack pointer
to the value other than the relocate address + 0x10000.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
---
 board/freescale/mpc8313erdb/mpc8313erdb.c |    2 +-
 board/sheldon/simpc8313/simpc8313.c       |    2 +-
 include/configs/MPC8313ERDB.h             |    1 +
 include/configs/SIMPC8313.h               |    1 +
 4 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index 9ffd4bf..e5f62ae 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -140,7 +140,7 @@ void board_init_f(ulong bootflag)
 	puts("NAND boot... ");
 	init_timebase();
 	initdram(0);
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
 	              CONFIG_SYS_NAND_U_BOOT_RELOC);
 }
 
diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c
index 25e5c24..1044de2 100644
--- a/board/sheldon/simpc8313/simpc8313.c
+++ b/board/sheldon/simpc8313/simpc8313.c
@@ -112,7 +112,7 @@ void board_init_f(ulong bootflag)
 	puts("NAND boot... ");
 	init_timebase();
 	initdram(0);
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
 				  CONFIG_SYS_NAND_U_BOOT_RELOC);
 }
 
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 4bf05d2..76b7894 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -242,6 +242,7 @@
 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 
 #define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
 				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index b847ce8..866ff17 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -136,6 +136,7 @@
 #define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
 #define CONFIG_SYS_NAND_U_BOOT_START	0x00100100
 #define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
 
 #define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
 					| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
-- 
1.6.4

[U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support

[Mingkai Hu]

MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.

When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.

This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.

Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
---
 Makefile                                       |    1 +
 board/freescale/mpc8536ds/config.mk            |    7 +
 board/freescale/mpc8536ds/tlb.c                |   11 ++
 board/freescale/mpc8536ds/u-boot-nand.lds      |  140 ++++++++++++++++++++++++
 cpu/mpc85xx/nand_init.c                        |  109 ++++++++++++++++++
 include/configs/MPC8536DS.h                    |   96 +++++++++++++----
 nand_spl/board/freescale/mpc8536ds/Makefile    |  119 ++++++++++++++++++++
 nand_spl/board/freescale/mpc8536ds/nand_boot.c |   99 +++++++++++++++++
 nand_spl/board/freescale/mpc8536ds/u-boot.lds  |   67 +++++++++++
 9 files changed, 629 insertions(+), 20 deletions(-)
 create mode 100644 board/freescale/mpc8536ds/u-boot-nand.lds
 create mode 100644 cpu/mpc85xx/nand_init.c
 create mode 100644 nand_spl/board/freescale/mpc8536ds/Makefile
 create mode 100644 nand_spl/board/freescale/mpc8536ds/nand_boot.c
 create mode 100644 nand_spl/board/freescale/mpc8536ds/u-boot.lds

diff --git a/Makefile b/Makefile
index 8fd9979..681242e 100644
--- a/Makefile
+++ b/Makefile
@@ -2442,6 +2442,7 @@ vme8349_config:		unconfig
 ATUM8548_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
 
+MPC8536DS_NAND_config \
 MPC8536DS_36BIT_config \
 MPC8536DS_config:       unconfig
 	@$(MKCONFIG) -n $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk
index f030876..b4bc33c 100644
--- a/board/freescale/mpc8536ds/config.mk
+++ b/board/freescale/mpc8536ds/config.mk
@@ -23,6 +23,13 @@
 #
 # mpc8536ds board
 #
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_MPC8536DS_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
+endif
+
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff80000
 endif
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index 35a13d4..dc52d7f 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -71,6 +71,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256K, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
+		      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8536ds/u-boot-nand.lds b/board/freescale/mpc8536ds/u-boot-nand.lds
new file mode 100644
index 0000000..c14e946
--- /dev/null
+++ b/board/freescale/mpc8536ds/u-boot-nand.lds
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  } :text
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg ADDR(.text) - 0x1000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  . = ADDR(.text) + 0x80000;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/cpu/mpc85xx/nand_init.c b/cpu/mpc85xx/nand_init.c
new file mode 100644
index 0000000..c29b22d
--- /dev/null
+++ b/cpu/mpc85xx/nand_init.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cpu_init_early_f(void)
+{
+	int i;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+	/* Clear initial global data */
+	for (i = 0; i < sizeof(gd_t); i++)
+		((char *)gd)[i] = 0;
+
+	set_tlb(0, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		1, 0, BOOKE_PAGESZ_4K, 0);
+
+	/* set up CCSR if we want it moved */
+#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS)
+	{
+		volatile u32 *ccsr_virt =
+			(volatile u32 *)(CONFIG_SYS_CCSRBAR + 0x1000);
+
+		set_tlb(0, (u32)ccsr_virt, CONFIG_SYS_CCSRBAR_DEFAULT,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			1, 1, BOOKE_PAGESZ_4K, 0);
+
+		in_be32(ccsr_virt);
+		out_be32(ccsr_virt, CONFIG_SYS_CCSRBAR_PHYS >> 12);
+		in_be32((volatile u32 *)CONFIG_SYS_CCSRBAR);
+	}
+#endif
+
+	init_laws();
+	invalidate_tlb(0);
+	init_tlbs();
+}
+
+void cpu_init_f(void)
+{
+	ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+
+	/*
+	 * LCRR - Clock Ratio Register - set up local bus timing
+	 * when needed
+	 */
+	out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
+
+#if defined(CONFIG_NAND_BR_PRELIM)  \
+	&& defined(CONFIG_NAND_OR_PRELIM)
+	out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
+	out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
+	/* for FPGA */
+	out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
+	out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
+#else
+#error  CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+	uint l2srbar;
+	int i;
+
+	l2srbar = CONFIG_SYS_INIT_L2_ADDR;
+	out_be32(&l2cache->l2srbar0, l2srbar);
+
+	/* set MBECCDIS=1, SBECCDIS=1 */
+	out_be32(&l2cache->l2errdis,
+			(MPC85xx_L2ERRDIS_MBECC |
+			 MPC85xx_L2ERRDIS_SBECC));
+
+	/* set L2E=1 & L2SRAM=001 */
+	out_be32(&l2cache->l2ctl,
+			(MPC85xx_L2CTL_L2E |
+			 MPC85xx_L2CTL_L2SRAM_ENTIRE));
+
+	/* Initialize L2 SRAM to zero */
+	for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
+		((char *)l2srbar)[i] = 0;
+#endif
+}
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 6018858..9b43e97 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -31,6 +31,12 @@
 #define CONFIG_PHYS_64BIT	1
 #endif
 
+#ifdef CONFIG_MK_MPC8536DS_NAND
+#define CONFIG_NAND_U_BOOT		1
+#define CONFIG_RAMBOOT_NAND		1
+#define CONFIG_RAMBOOT_TEXT_BASE	0xf8f82000
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
@@ -91,10 +97,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
 
 /*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8f80000ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE		(512 << 10)
+#define CONFIG_SYS_INIT_L2_END		(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+/*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_CCSRBAR_PHYS		0xfffe00000ull	/* physical addr of CCSRBAR */
@@ -103,6 +120,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
 
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT	CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#endif
+
 #define CONFIG_SYS_PCI1_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
 #define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
@@ -190,8 +213,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
-#define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
+#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
 
 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
@@ -208,6 +231,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
@@ -276,12 +305,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
+#ifndef CONFIG_NAND_SPL
 #define CONFIG_SYS_NAND_BASE		0xffa00000
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
 #else
 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
 #endif
+#else
+#define CONFIG_SYS_NAND_BASE		0xfff00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xffff00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#endif
 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
 				CONFIG_SYS_NAND_BASE + 0x40000, \
 				CONFIG_SYS_NAND_BASE + 0x80000, \
@@ -292,6 +330,15 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_NAND_FSL_ELBC	1
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 
+/* NAND boot: 4K NAND loader config */
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
+#define CONFIG_SYS_NAND_U_BOOT_START	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+
 /* NAND flash config */
 #define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
@@ -307,8 +354,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 				| OR_FCM_TRLX \
 				| OR_FCM_EHTR)
 
-#define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
-#define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+#ifdef CONFIG_RAMBOOT_NAND
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_NAND_BR_PRELIM	/* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_NAND_OR_PRELIM	/* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM	/* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM	/* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM	/* NAND Options */
+#endif
 
 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
 				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
@@ -526,15 +582,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_EXT2
 #endif
 
-/*
- * USB
- */
-#define CONFIG_CMD_USB
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_FSL
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
@@ -569,14 +616,23 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 /*
  * Environment
  */
-#define CONFIG_ENV_IS_IN_FLASH	1
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR		0xfff80000
+
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_NAND)
+	#define CONFIG_ENV_IS_IN_NAND	1
+	#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+	#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
 #else
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#define CONFIG_ENV_IS_IN_FLASH	1
+	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+	#define CONFIG_ENV_ADDR		0xfff80000
+	#else
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+	#endif
+	#define CONFIG_ENV_SIZE		0x2000
+	#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 #endif
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile
new file mode 100644
index 0000000..c9104d3
--- /dev/null
+++ b/nand_spl/board/freescale/mpc8536ds/Makefile
@@ -0,0 +1,119 @@
+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr at denx.de.
+#
+# Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+TEXT_BASE := 0xfff00000
+PAD_TO := 0xfff01000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL
+
+SOBJS	= start.o resetvec.o
+COBJS	= nand_boot_fsl_elbc.o ns16550.o nand_init.o nand_boot.o cache.o \
+	  tlb.o tlb_table.o law.o law_table.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:	$(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+$(obj)start.S:
+	@rm -f $(obj)start.S
+	ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
+
+$(obj)resetvec.S:
+	@rm -f $(obj)resetvec.S
+	ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+
+$(obj)nand_boot_fsl_elbc.c:
+	@rm -f $(obj)nand_boot_fsl_elbc.c
+	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+	       $(obj)nand_boot_fsl_elbc.c
+
+$(obj)ns16550.c:
+	@rm -f $(obj)ns16550.c
+	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)nand_init.c:
+	@rm -f $(obj)nand_init.c
+	ln -sf $(SRCTREE)/cpu/mpc85xx/nand_init.c $(obj)nand_init.c
+
+$(obj)cache.c:
+	@rm -f $(obj)cache.c
+	ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
+
+$(obj)tlb.c:
+	@rm -f $(obj)tlb.c
+	ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+	@rm -f $(obj)tlb_table.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+$(obj)law.c:
+	@rm -f $(obj)law.c
+	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)law.c
+
+$(obj)law_table.c:
+	@rm -f $(obj)law_table.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law_table.c
+
+#########################################################################
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/mpc8536ds/nand_boot.c b/nand_spl/board/freescale/mpc8536ds/nand_boot.c
new file mode 100644
index 0000000..77973d1
--- /dev/null
+++ b/nand_spl/board/freescale/mpc8536ds/nand_boot.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <nand.h>
+
+void board_init_f(ulong bootflag)
+{
+	u8 sysclk_ratio;
+	uint plat_ratio, bus_clk, sys_clk;
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* initialize selected port with appropriate baud rate */
+	sysclk_ratio = *((volatile unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+	sysclk_ratio &= 0x7;
+	switch (sysclk_ratio) {
+	case 0:
+		sys_clk = 33333000;
+		break;
+	case 1:
+		sys_clk = 39999600;
+		break;
+	case 2:
+		sys_clk = 49999500;
+		break;
+	case 3:
+		sys_clk = 66666000;
+		break;
+	case 4:
+		sys_clk = 83332500;
+		break;
+	case 5:
+		sys_clk = 99999000;
+		break;
+	case 6:
+		sys_clk = 133332000;
+		break;
+	case 7:
+		sys_clk = 166665000;
+		break;
+	default:
+		sys_clk = 0;
+		break;
+	}
+
+	plat_ratio = (gur->porpllsr) & 0x0000003e;
+	plat_ratio >>= 1;
+	bus_clk = plat_ratio * sys_clk;
+	NS16550_init((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500),
+			bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+
+	/* copy code to RAM and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+			CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), '\r');
+
+	NS16550_putc((NS16550_t)(CONFIG_SYS_CCSRBAR + 0x4500), c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
+
diff --git a/nand_spl/board/freescale/mpc8536ds/u-boot.lds b/nand_spl/board/freescale/mpc8536ds/u-boot.lds
new file mode 100644
index 0000000..fef3e42
--- /dev/null
+++ b/nand_spl/board/freescale/mpc8536ds/u-boot.lds
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de
+ *
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+	. = 0xfff00000;
+	.text : {
+		*(.text)
+  	}
+	_etext = .;
+
+	.reloc : {
+		_GOT2_TABLE_ = .;
+		*(.got2)
+		_FIXUP_TABLE_ = .;
+		*(.fixup)
+	}
+	__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+	__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+	. = ALIGN(8);
+	.data : {
+		*(.rodata*)
+		*(.data*)
+		*(.sdata*)
+	}
+	_edata  =  .;
+
+	. = ALIGN(8);
+	__init_begin = .;
+	__init_end = .;
+
+	.resetvec ADDR(.text) + 0xffc : {
+		*(.resetvec)
+	} = 0xffff
+
+	__bss_start = .;
+	.bss : {
+		*(.sbss)
+		*(.bss)
+	}
+	_end = .;
+}
+ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");
-- 
1.6.4

[U-Boot] [PATCH v2 4/5] On-chip ROM boot: MPC8536DS support

[Mingkai Hu]

The MPC8536E is capable of booting from the on-chip ROM - boot from
eSDHC and boot from eSPI. When power on, the porcessor excutes the
ROM code to initialize the eSPI/eSDHC controller, and loads the mian
U-Boot image from the memory device that interfaced to the controller,
such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
L2SRAM, then boot from it.

The memory device should contain a specific data structure with control
word and config word at the fixed address. The config word direct the
process how to config the memory device, and the control word direct
the processor where to find the image on the memory device, or where
copy the main image to. The user can use any method to store the data
structure to the memory device, only if store it on the assigned address.

The on-chip ROM code will map the whole 4GB address space by setting
entry0 in the TLB1, so the main image need to switch to Address space 1
to disable this mapping and map the address space again.

This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM. But save
the env variables to NOWHERE.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
---
 Makefile                            |    2 ++
 board/freescale/mpc8536ds/config.mk |    8 ++++++++
 include/configs/MPC8536DS.h         |   17 ++++++++++++++++-
 3 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/Makefile b/Makefile
index 681242e..79d40fa 100644
--- a/Makefile
+++ b/Makefile
@@ -2443,6 +2443,8 @@ ATUM8548_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
 
 MPC8536DS_NAND_config \
+MPC8536DS_SDCARD_config \
+MPC8536DS_SPIFLASH_config \
 MPC8536DS_36BIT_config \
 MPC8536DS_config:       unconfig
 	@$(MKCONFIG) -n $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk
index b4bc33c..7e34751 100644
--- a/board/freescale/mpc8536ds/config.mk
+++ b/board/freescale/mpc8536ds/config.mk
@@ -30,6 +30,14 @@ LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
 endif
 endif
 
+ifeq ($(CONFIG_MK_MPC8536DS_SDCARD), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+endif
+
+ifeq ($(CONFIG_MK_MPC8536DS_SPIFLASH), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+endif
+
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff80000
 endif
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 9b43e97..580d66f 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -37,6 +37,16 @@
 #define CONFIG_RAMBOOT_TEXT_BASE	0xf8f82000
 #endif
 
+#ifdef CONFIG_MK_MPC8536DS_SDCARD
+#define CONFIG_RAMBOOT_SDCARD		1
+#define CONFIG_RAMBOOT_TEXT_BASE	0xf8f80000
+#endif
+
+#ifdef CONFIG_MK_MPC8536DS_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH		1
+#define CONFIG_RAMBOOT_TEXT_BASE	0xf8f80000
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE		1	/* BOOKE */
 #define CONFIG_E500		1	/* BOOKE e500 family */
@@ -231,7 +241,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
+	|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef CONFIG_SYS_RAMBOOT
@@ -622,6 +633,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 	#define CONFIG_ENV_IS_IN_NAND	1
 	#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 	#define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_RAMBOOT_SPIFLASH) || defined(CONFIG_RAMBOOT_SDCARD)
+	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
+	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
+	#define CONFIG_ENV_SIZE		0x2000
 #endif
 #else
 	#define CONFIG_ENV_IS_IN_FLASH	1
-- 
1.6.4

[U-Boot] [PATCH v2 5/5] Add README.mpc8536ds

[Mingkai Hu]

Add boot from NAND/eSDHC/eSPI description

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
---
 doc/README.mpc8536ds |  127 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 127 insertions(+), 0 deletions(-)
 create mode 100644 doc/README.mpc8536ds

diff --git a/doc/README.mpc8536ds b/doc/README.mpc8536ds
new file mode 100644
index 0000000..4d0bee0
--- /dev/null
+++ b/doc/README.mpc8536ds
@@ -0,0 +1,127 @@
+Overview:
+=========
+
+The MPC8536E integrates a PowerPC processor core with system logic
+required for imaging, networking, and communications applications.
+
+Boot from NAND:
+===============
+
+The MPC8536E is capable of booting from NAND flash which uses the image
+u-boot-nand.bin. This image contains two parts: a first stage image(also
+call 4K NAND loader and a second stage image. The former is appended to
+the latter to produce u-boot-nand.bin.
+
+The bootup process can be divided into two stages: the first stage will
+configure the L2SRAM, then copy the second stage image to L2SRAM and jump
+to it. The second stage image is to configure all the hardware and boot up
+to U-Boot command line.
+
+The 4K NAND loader's code comes from the corresponding nand_spl directory,
+along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
+is mainly used to shrink the code size to the 4K size limitation.
+
+The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
+second stage image. It's set in the board config file when boot from NAND
+is selected.
+
+Build and boot steps
+--------------------
+
+1. Building image
+	make MPC8536DS_NAND_config
+	make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+
+2. Change dip-switch
+	SW2[5-8] = 1011
+	SW9[1-3] = 101
+	Note: 1 stands for 'on', 0 stands for 'off'
+
+3. Flash image
+	tftp 1000000 u-boot-nand.bin
+	nand erase 0 a0000
+	nand write 1000000 0 a0000
+
+Boot from On-chip ROM:
+======================
+
+The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
+and boot from eSPI. When power on, the porcessor excutes the ROM code to
+initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
+the memory device that interfaced to the controller, such as the SDCard or
+SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
+
+The memory device should contain a specific data structure with control word
+and config word at the fixed address. The config word direct the process how
+to config the memory device, and the control word direct the processor where
+to find the image on the memory device, or where copy the main image to. The
+user can use any method to store the data structure to the memory device, only
+if store it on the assigned address.
+
+Build and boot steps
+--------------------
+
+For boot from eSDHC:
+1. Build image
+	make MPC8536DS_SDCARD_config
+	make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+
+2. Change dip-switch
+	SW2[5-8] = 0111
+	SW3[1]   = 0
+	SW8[7]   = 0 - The on-board SD/MMC slot is active
+	SW8[7]   = 1 - The externel SD/MMC slot is active
+
+3. Put image to SDCard
+	Put the follwing info at the assigned address on the SDCard:
+
+	   Offset   |   Data     | Description
+	--------------------------------------------------------
+	| 0x40-0x43 | 0x424F4F54 | BOOT signature              |
+	--------------------------------------------------------
+	| 0x48-0x4B | 0x00080000 | u-boot.bin's size           |
+	--------------------------------------------------------
+	| 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
+	--------------------------------------------------------
+	| 0x58-0x5B | 0xF8F80000 | Target Address              |
+	-------------------------------------------------------
+	| 0x60-0x63 | 0xF8FFF000 | Execution Starting Address  |
+	--------------------------------------------------------
+	| 0x68-0x6B | 0x6        | Number of Config Addr/Data  |
+	--------------------------------------------------------
+	| 0x80-0x83 | 0xFF720100 | Config Addr 1               |
+	| 0x84-0x87 | 0xF8F80000 | Config Data 1               |
+	--------------------------------------------------------
+	| 0x88-0x8b | 0xFF720e44 | Config Addr 2               |
+	| 0x8c-0x8f | 0x0000000C | Config Data 2               |
+	--------------------------------------------------------
+	| 0x90-0x93 | 0xFF720000 | Config Addr 3               |
+	| 0x94-0x97 | 0x80010000 | Config Data 3               |
+	--------------------------------------------------------
+	| 0x98-0x9b | 0xFF72e40e | Config Addr 4               |
+	| 0x9c-0x9f | 0x00000040 | Config Data 4               |
+	--------------------------------------------------------
+	| 0xa0-0xa3 | 0x40000001 | Config Addr 5               |
+	| 0xa4-0xa7 | 0x00000100 | Config Data 5               |
+	--------------------------------------------------------
+	| 0xa8-0xab | 0x80000001 | Config Addr 6               |
+	| 0xac-0xaf | 0x80000001 | Config Data 6               |
+	--------------------------------------------------------
+	|              ......                                  |
+	--------------------------------------------------------
+	| 0x???????? | u-boot.bin                              |
+	--------------------------------------------------------
+
+	then insert the SDCard to the active slot to boot up.
+
+For boot from eSPI:
+1. Build image
+	make MPC8536DS_SPIFLASH_config
+	make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
+
+2. Change dip-switch
+	SW2[5-8] = 0110
+
+3. Put image to SPI flash
+	Put the info in the above table onto the SPI flash, then
+	boot up.
-- 
1.6.4

[U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

[Kumar Gala]

On Sep 10, 2009, at 9:53 PM, Mingkai Hu wrote:

> diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
> index 0497a29..9c7c928 100644
> --- a/cpu/mpc85xx/tlb.c
> +++ b/cpu/mpc85xx/tlb.c
> @@ -59,6 +59,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
> #endif
> }
>
> +#ifndef CONFIG_NAND_SPL
> void disable_tlb(u8 esel)
> {
> 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
> @@ -83,6 +84,7 @@ void disable_tlb(u8 esel)
> 		addrmap_set_entry(0, 0, 0, esel);
> #endif
> }
> +#endif
>
> void invalidate_tlb(u8 tlb)
> {
> @@ -106,6 +108,7 @@ void init_tlbs(void)
> 	return ;
> }
>
> +#ifdef CONFIG_ADDR_MAP

why ADDR_MAP?

- k

> static void tlbsx (const volatile unsigned *addr)
> {
> 	__asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
> @@ -132,6 +135,7 @@ int find_tlb_idx(void *addr, u8 tlbsel)
>
> 	return -1;
> }
> +#endif
>
> #ifdef CONFIG_ADDR_MAP
> void init_addr_map(void)
> @@ -168,6 +172,7 @@ void init_addr_map(void)
> }
> #endif
>
> +#ifndef CONFIG_NAND_SPL
> #ifndef CONFIG_SYS_DDR_TLB_START
> #define CONFIG_SYS_DDR_TLB_START 8
> #endif
> @@ -215,3 +220,4 @@ unsigned int setup_ddr_tlbs(unsigned int  
> memsize_in_meg)
> 	 */
> 	return memsize_in_meg;
> }
> +#endif /* !CONFIG_NAND_SPL */

[U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support

[Hu Mingkai-B21284]

 

> -----Original Message-----
> From: Gala Kumar-B11780 
> Sent: Friday, September 11, 2009 11:13 AM
> To: Hu Mingkai-B21284
> Cc: u-boot at lists.denx.de; Wood Scott-B07421
> Subject: Re: [PATCH v2 1/5] 85xx: add boot from 
> NAND/eSDHC/eSPI support
> 
> 
> On Sep 10, 2009, at 9:53 PM, Mingkai Hu wrote:
> 
> > diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 
> > 0497a29..9c7c928 100644
> > --- a/cpu/mpc85xx/tlb.c
> > +++ b/cpu/mpc85xx/tlb.c
> > @@ -59,6 +59,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn, #endif }
> >
> > +#ifndef CONFIG_NAND_SPL
> > void disable_tlb(u8 esel)
> > {
> > 	u32 _mas0, _mas1, _mas2, _mas3, _mas7; @@ -83,6 +84,7 @@ void 
> > disable_tlb(u8 esel)
> > 		addrmap_set_entry(0, 0, 0, esel);
> > #endif
> > }
> > +#endif
> >
> > void invalidate_tlb(u8 tlb)
> > {
> > @@ -106,6 +108,7 @@ void init_tlbs(void)
> > 	return ;
> > }
> >
> > +#ifdef CONFIG_ADDR_MAP
> 
> why ADDR_MAP?
> 

Oh..., sorry, copy error, it should be NAND_SPL. I'll send it again.

Without this, the 4K NAND loader size will over 4K.

Thanks,
Mingkai

[U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support

[Kumar Gala]

On Sep 10, 2009, at 9:53 PM, Mingkai Hu wrote:

> board/freescale/mpc8536ds/u-boot-nand.lds      |  140 +++++++++++++++ 
> +++++++++

Do we really need a specific linker script for this?

- k

[U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support

[Kumar Gala]

On Sep 10, 2009, at 11:11 PM, Kumar Gala wrote:

>
> On Sep 10, 2009, at 9:53 PM, Mingkai Hu wrote:
>
>> board/freescale/mpc8536ds/u-boot-nand.lds      |  140 +++++++++++++++
>> +++++++++
>
> Do we really need a specific linker script for this?

More specifically, can we move it into cpu/mpc85xx/u-boot-nand.lds and  
match cpu/mpc85xx/u-boot.lds.

- k

[U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support

[Hu Mingkai-B21284]

 

> -----Original Message-----
> From: Kumar Gala [mailto:galak at kernel.crashing.org] 
> Sent: Friday, September 11, 2009 12:21 PM
> To: Gala Kumar-B11780
> Cc: Hu Mingkai-B21284; Wood Scott-B07421; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support
> 
> 
> On Sep 10, 2009, at 11:11 PM, Kumar Gala wrote:
> 
> >
> > On Sep 10, 2009, at 9:53 PM, Mingkai Hu wrote:
> >
> >> board/freescale/mpc8536ds/u-boot-nand.lds      |  140 
> +++++++++++++++
> >> +++++++++
> >
> > Do we really need a specific linker script for this?
> 
> More specifically, can we move it into 
> cpu/mpc85xx/u-boot-nand.lds and match cpu/mpc85xx/u-boot.lds.
> 

I think it can be moved to cpu/mpc85xx/*, but it's a little trouble to
match u-boot.lds
when load the boot-from-nand image to L2 SRAM. 

The script u-boot.lds will expand the image to 512K, along with the 4K
NAND loader,
the image size wil over 512K, so we place the boot page on the beginning
of the
boot-from-nand image.

When load the image to DDR, I think it can match u-boot.lds.

Thanks,
Mingkai

[U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support

[Kumar Gala]

On Sep 11, 2009, at 12:43 AM, Hu Mingkai-B21284 wrote:

>
>
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak at kernel.crashing.org]
>> Sent: Friday, September 11, 2009 12:21 PM
>> To: Gala Kumar-B11780
>> Cc: Hu Mingkai-B21284; Wood Scott-B07421; u-boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support
>>
>>
>> On Sep 10, 2009, at 11:11 PM, Kumar Gala wrote:
>>
>>>
>>> On Sep 10, 2009, at 9:53 PM, Mingkai Hu wrote:
>>>
>>>> board/freescale/mpc8536ds/u-boot-nand.lds      |  140
>> +++++++++++++++
>>>> +++++++++
>>>
>>> Do we really need a specific linker script for this?
>>
>> More specifically, can we move it into
>> cpu/mpc85xx/u-boot-nand.lds and match cpu/mpc85xx/u-boot.lds.
>>
>
> I think it can be moved to cpu/mpc85xx/*, but it's a little trouble to
> match u-boot.lds
> when load the boot-from-nand image to L2 SRAM.
>
> The script u-boot.lds will expand the image to 512K, along with the 4K
> NAND loader,
> the image size wil over 512K, so we place the boot page on the  
> beginning
> of the
> boot-from-nand image.
>
> When load the image to DDR, I think it can match u-boot.lds.

When I say match I just meant the differences should only be the one's  
required.

For example I don't believe this difference is necessary:

@@ -69,8 +65,10 @@
      PROVIDE (etext = .);
      .rodata    :
     {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
      *(.eh_frame)
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
    } :text
    .fini      : { *(.fini)    } =0
    .ctors     : { *(.ctors)   }

- k

[U-Boot] [PATCH v2 2/5] NAND boot: change NAND loader's relocate SP to CONFIG param

[Scott Wood]

Mingkai Hu wrote:
> So that we can set the NAND loader's relocate stack pointer
> to the value other than the relocate address + 0x10000.
> 
> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
> ---
>  board/freescale/mpc8313erdb/mpc8313erdb.c |    2 +-
>  board/sheldon/simpc8313/simpc8313.c       |    2 +-
>  include/configs/MPC8313ERDB.h             |    1 +
>  include/configs/SIMPC8313.h               |    1 +
>  4 files changed, 4 insertions(+), 2 deletions(-)

Acked-by: Scott Wood <scottwood@freescale.com>

-Scott

[U-Boot] [PATCH v2 2/5] NAND boot: change NAND loader's relocate SP to CONFIG param

[Kumar Gala]

On Sep 11, 2009, at 2:04 PM, Scott Wood wrote:

> Mingkai Hu wrote:
>> So that we can set the NAND loader's relocate stack pointer
>> to the value other than the relocate address + 0x10000.
>>
>> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
>> ---
>> board/freescale/mpc8313erdb/mpc8313erdb.c |    2 +-
>> board/sheldon/simpc8313/simpc8313.c       |    2 +-
>> include/configs/MPC8313ERDB.h             |    1 +
>> include/configs/SIMPC8313.h               |    1 +
>> 4 files changed, 4 insertions(+), 2 deletions(-)
>
> Acked-by: Scott Wood <scottwood@freescale.com>

applied to 85xx

- k

[U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support

[Hu Mingkai-B21284]

 

> -----Original Message-----
> From: Kumar Gala [mailto:galak at kernel.crashing.org] 
> Sent: Friday, September 11, 2009 10:49 PM
> To: Hu Mingkai-B21284
> Cc: Wood Scott-B07421; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support
> 
> 
> When I say match I just meant the differences should only be 
> the one's required.
> 
> For example I don't believe this difference is necessary:
> 
> @@ -69,8 +65,10 @@
>       PROVIDE (etext = .);
>       .rodata    :
>      {
> +    *(.rodata)
> +    *(.rodata1)
> +    *(.rodata.str1.4)
>       *(.eh_frame)
> -    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
>     } :text
>     .fini      : { *(.fini)    } =0
>     .ctors     : { *(.ctors)   }
> 

Ok, I have matched this difference with u-boot.lds in version 3.

Thanks,
Mingkai