* [U-Boot] [PATCH 1/3] ppc/85xx: Cleanup p1_p2_rdb PCI setup
@ 2009-09-17 15:46 Kumar Gala
2009-09-17 15:46 ` [U-Boot] [PATCH 2/3] ppc/85xx: Clean up p2020ds PCI setup code Kumar Gala
0 siblings, 1 reply; 3+ messages in thread
From: Kumar Gala @ 2009-09-17 15:46 UTC (permalink / raw)
To: u-boot
General code cleanup to use in/out IO accessors as well as making
the code that prints out info sane between board and generic fsl pci
code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
board/freescale/p1_p2_rdb/pci.c | 38 ++++++++++++++++++++------------------
drivers/pci/fsl_pci_init.c | 2 +-
2 files changed, 21 insertions(+), 19 deletions(-)
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index a3617d5..1193362 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -41,58 +41,60 @@ static struct pci_controller pcie2_hose;
void pci_init_board(void)
{
- struct fsl_pci_info pci_info[2];
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint devdisr = in_be32(&gur->devdisr);
- uint io_sel = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
- int num = 0;
+ struct fsl_pci_info pci_info[2];
+ u32 devdisr, pordevsr, io_sel, host_agent;
int first_free_busno = 0;
+ int num = 0;
int pcie_ep, pcie_configured;
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
+
debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf (" eTSEC2 is in sgmii mode.\n");
+ puts("\n");
#ifdef CONFIG_PCIE2
- SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- puts ("\n PCIE2 connected to Slot 1 as ");
- printf ("%s (base address %lx)",
- pcie_ep ? "End Point": "Root Complex", pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num],
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
- num++;
} else {
printf (" PCIE2: disabled\n");
}
+ puts("\n");
#else
set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE1
- SET_STD_PCIE_INFO(pci_info[num], 1);
-
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- puts ("\n PCIE1 connected to Slot 2 as ");
- printf ("%s (base address %lx)",
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num],
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
- num++;
} else {
printf (" PCIE1: disabled\n");
}
+ puts("\n");
#else
set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 885542c..87944bf 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -450,7 +450,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- printf("\n PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
+ printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
hose->first_busno, hose->last_busno);
return(hose->last_busno + 1);
--
1.6.0.6
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH 2/3] ppc/85xx: Clean up p2020ds PCI setup code
2009-09-17 15:46 [U-Boot] [PATCH 1/3] ppc/85xx: Cleanup p1_p2_rdb PCI setup Kumar Gala
@ 2009-09-17 15:46 ` Kumar Gala
2009-09-17 15:46 ` [U-Boot] [PATCH 3/3] ppc/85xx: Clean up mpc8572DS " Kumar Gala
0 siblings, 1 reply; 3+ messages in thread
From: Kumar Gala @ 2009-09-17 15:46 UTC (permalink / raw)
To: u-boot
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
board/freescale/p2020ds/p2020ds.c | 150 ++++++++-----------------------------
1 files changed, 33 insertions(+), 117 deletions(-)
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 7ad9be8..0832fe1 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -192,69 +192,42 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
-int first_free_busno = 0;
-
#ifdef CONFIG_PCI
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+ struct fsl_pci_info pci_info[3];
+ u32 devdisr, pordevsr, io_sel, host_agent;
+ int first_free_busno = 0;
+ int num = 0;
- volatile ccsr_fsl_pci_t *pci;
- struct pci_controller *hose;
int pcie_ep, pcie_configured;
- struct pci_region *r;
-/* u32 temp32; */
+
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf(" eTSEC2 is in sgmii mode.\n");
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
printf(" eTSEC3 is in sgmii mode.\n");
+ puts("\n");
#ifdef CONFIG_PCIE2
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- hose = &pcie2_hose;
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
- r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
- printf("\n PCIE2 connected to ULI as %s (base addr %x)",
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- printf("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno = hose->last_busno+1;
- printf(" PCIE2 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
/*
* The workaround doesn't work on p2020 because the location
@@ -279,104 +252,47 @@ void pci_init_board(void)
} else {
printf(" PCIE2: disabled\n");
}
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+ set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE3
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- hose = &pcie3_hose;
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
- r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
- printf("\n PCIE3 connected to Slot 1 as %s (base addr %x)",
+ SET_STD_PCIE_INFO(pci_info[num], 3);
+ printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- printf("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BUS,
- CONFIG_SYS_PCIE3_MEM_PHYS,
- CONFIG_SYS_PCIE3_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BUS,
- CONFIG_SYS_PCIE3_IO_PHYS,
- CONFIG_SYS_PCIE3_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno = hose->last_busno+1;
- printf(" PCIE3 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
-
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie3_hose, first_free_busno);
} else {
printf(" PCIE3: disabled\n");
}
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+ set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE1
- pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- hose = &pcie1_hose;
pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- r = hose->regions;
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
- printf("\n PCIE1 connected to Slot 2 as %s (base addr %x)",
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug(" with errors. Clearing. Now 0x%08x",
- pci->pme_msg_det);
- }
- printf("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno = first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno = hose->last_busno+1;
- printf(" PCIE1 on bus %02x - %02x\n",
- hose->first_busno, hose->last_busno);
-
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
printf(" PCIE1: disabled\n");
}
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}
#endif
--
1.6.0.6
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH 3/3] ppc/85xx: Clean up mpc8572DS PCI setup code
2009-09-17 15:46 ` [U-Boot] [PATCH 2/3] ppc/85xx: Clean up p2020ds PCI setup code Kumar Gala
@ 2009-09-17 15:46 ` Kumar Gala
0 siblings, 0 replies; 3+ messages in thread
From: Kumar Gala @ 2009-09-17 15:46 UTC (permalink / raw)
To: u-boot
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
board/freescale/mpc8572ds/mpc8572ds.c | 226 ++++++++++----------------------
1 files changed, 71 insertions(+), 155 deletions(-)
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index c69934c..f8d9713 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -160,189 +160,105 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
-int first_free_busno=0;
#ifdef CONFIG_PCI
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+ struct fsl_pci_info pci_info[3];
+ u32 devdisr, pordevsr, io_sel, host_agent, temp32;
+ int first_free_busno = 0;
+ int num = 0;
+
+ int pcie_ep, pcie_configured;
+
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
devdisr, io_sel, host_agent);
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
printf (" eTSEC1 is in sgmii mode.\n");
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
printf (" eTSEC2 is in sgmii mode.\n");
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
printf (" eTSEC3 is in sgmii mode.\n");
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
+ if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
printf (" eTSEC4 is in sgmii mode.\n");
-
+ puts("\n");
#ifdef CONFIG_PCIE3
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- struct pci_controller *hose = &pcie3_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
- struct pci_region *r = hose->regions;
- u32 temp32;
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
- printf ("\n PCIE3 connected to ULI as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BUS,
- CONFIG_SYS_PCIE3_MEM_PHYS,
- CONFIG_SYS_PCIE3_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BUS,
- CONFIG_SYS_PCIE3_IO_PHYS,
- CONFIG_SYS_PCIE3_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf (" PCIE3 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-
- /*
- * Activate ULI1575 legacy chip by performing a fake
- * memory access. Needed to make ULI RTC work.
- * Device 1d has the first on-board memory BAR.
- */
-
- pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
- PCI_BASE_ADDRESS_1, &temp32);
- if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
- void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
- temp32, 4, 0);
- debug(" uli1572 read to %p\n", p);
- in_be32(p);
- }
- } else {
- printf (" PCIE3: disabled\n");
+ pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+ SET_STD_PCIE_INFO(pci_info[num], 3);
+ printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie3_hose, first_free_busno);
+ /*
+ * Activate ULI1575 legacy chip by performing a fake
+ * memory access. Needed to make ULI RTC work.
+ * Device 1d has the first on-board memory BAR.
+ */
+ pci_hose_read_config_dword(&pcie3_hose, PCI_BDF(2, 0x1d, 0),
+ PCI_BASE_ADDRESS_1, &temp32);
+ if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
+ void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
+ temp32, 4, 0);
+ debug(" uli1572 read to %p\n", p);
+ in_be32(p);
}
-
+ } else {
+ printf (" PCIE3: disabled\n");
}
+ puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
#endif
#ifdef CONFIG_PCIE2
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
- struct pci_controller *hose = &pcie2_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
- struct pci_region *r = hose->regions;
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
- printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_MEM_BUS,
- CONFIG_SYS_PCIE2_MEM_PHYS,
- CONFIG_SYS_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE2_IO_BUS,
- CONFIG_SYS_PCIE2_IO_PHYS,
- CONFIG_SYS_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
- first_free_busno=hose->last_busno+1;
- printf (" PCIE2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-
- } else {
- printf (" PCIE2: disabled\n");
- }
-
+ pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+ SET_STD_PCIE_INFO(pci_info[num], 2);
+ printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie2_hose, first_free_busno);
+ } else {
+ printf (" PCIE2: disabled\n");
}
+
+ puts("\n");
#else
gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
#endif
-#ifdef CONFIG_PCIE1
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- struct pci_region *r = hose->regions;
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE1 connected to Slot 2 as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BUS,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BUS,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf(" PCIE1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-
- } else {
- printf (" PCIE1: disabled\n");
- }
+#ifdef CONFIG_PCIE1
+ pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
+ } else {
+ printf (" PCIE1: disabled\n");
}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ set_bits32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}
#endif
--
1.6.0.6
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2009-09-17 15:46 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-09-17 15:46 [U-Boot] [PATCH 1/3] ppc/85xx: Cleanup p1_p2_rdb PCI setup Kumar Gala
2009-09-17 15:46 ` [U-Boot] [PATCH 2/3] ppc/85xx: Clean up p2020ds PCI setup code Kumar Gala
2009-09-17 15:46 ` [U-Boot] [PATCH 3/3] ppc/85xx: Clean up mpc8572DS " Kumar Gala
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