[PATCH 1/9] SMDK6410: Configure GPIO pull up for WM835x IRQ line

[PATCH 1/9] SMDK6410: Configure GPIO pull up for WM835x IRQ line

[Mark Brown]

When used with the WM1190-EV1 board we can use the internal pull up
resistor of the CPU to provide the required pull for the IRQ line.
Without this interrupts from the WM835x don't work in the default
WM1190-EV1 hardwaer configuration.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
 arch/arm/mach-s3c6410/mach-smdk6410.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index ea51dbe..9f1a214 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -320,6 +320,9 @@ static int __init smdk6410_wm8350_init(struct wm8350 *wm8350)
 {
 	int i;
 
+	/* Configure the IRQ line */
+	s3c_gpio_setpull(S3C64XX_GPN(12), S3C_GPIO_PULL_UP);
+
 	/* Instantiate the regulators */
 	for (i = 0; i < ARRAY_SIZE(wm1190_regulators); i++)
 		wm8350_register_regulator(wm8350,
-- 
1.6.5.2

[PATCH 2/9] S3C64XX: Fix S3C64XX_CLKDIV0_ARM_MASK value

[Mark Brown]

From: Kukjin Kim <kgene.kim@samsung.com>

The value of S3C64XX_CLKDIV0_ARM_MASK is wrong. This patch fixes
this values, S3C6400_CLKDIV0_ARM_MASK and S3C6410_CLKDIV0_ARM_MASK.

Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
 arch/arm/plat-s3c64xx/include/plat/regs-clock.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
index a8777a7..ff46e7f 100644
--- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
+++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h
@@ -51,8 +51,8 @@
 #define S3C6400_CLKDIV0_HCLK_SHIFT	(8)
 #define S3C6400_CLKDIV0_MPLL_MASK	(0x1 << 4)
 #define S3C6400_CLKDIV0_MPLL_SHIFT	(4)
-#define S3C6400_CLKDIV0_ARM_MASK	(0x3 << 0)
-#define S3C6410_CLKDIV0_ARM_MASK	(0x7 << 0)
+#define S3C6400_CLKDIV0_ARM_MASK	(0x7 << 0)
+#define S3C6410_CLKDIV0_ARM_MASK	(0xf << 0)
 #define S3C6400_CLKDIV0_ARM_SHIFT	(0)
 
 /* CLKDIV1 */
-- 
1.6.5.2

[PATCH 3/9] SMDK6410: Hook up regulator supplies for WM8580

[Mark Brown]

DVDD is supplied by supplies derived from the PMIC, AVDD and PVDD are
supplied from the main wall supply on the base board which runs at
5V. No option is currently supported for running without a PMIC card,
the assumption is that the regulator API will be built out when no
soft PMIC card is in use.

To ease merge issues since this uses the newly added dev_name supply
configuration from the regulator API (currently in -next only) the
fixed voltage regulator is ifdefed out when the regulator API is not
enabled.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
 arch/arm/mach-s3c6410/mach-smdk6410.c |   52 +++++++++++++++++++++++++++++++++
 1 files changed, 52 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index 9f1a214..480d297 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -25,6 +25,7 @@
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/smsc911x.h>
+#include <linux/regulator/fixed.h>
 
 #ifdef CONFIG_SMDK6410_WM1190_EV1
 #include <linux/mfd/wm8350/core.h>
@@ -184,6 +185,43 @@ static struct platform_device smdk6410_smsc911x = {
 	},
 };
 
+#ifdef CONFIG_REGULATOR
+static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
+	{
+		/* WM8580 */
+		.supply = "PVDD",
+		.dev_name = "0-001b",
+	},
+	{
+		/* WM8580 */
+		.supply = "AVDD",
+		.dev_name = "0-001b",
+	},
+};
+
+static struct regulator_init_data smdk6410_b_pwr_5v_data = {
+	.constraints = {
+		.always_on = 1,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers),
+	.consumer_supplies = smdk6410_b_pwr_5v_consumers,
+};
+
+static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = {
+	.supply_name = "B_PWR_5V",
+	.microvolts = 5000000,
+	.init_data = &smdk6410_b_pwr_5v_data,
+};
+
+static struct platform_device smdk6410_b_pwr_5v = {
+	.name          = "reg-fixed-voltage",
+	.id            = -1,
+	.dev = {
+		.platform_data = &smdk6410_b_pwr_5v_pdata,
+	},
+};
+#endif
+
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
@@ -198,6 +236,10 @@ static struct platform_device *smdk6410_devices[] __initdata = {
 	&s3c_device_fb,
 	&s3c_device_usb,
 	&s3c_device_usb_hsotg,
+
+#ifdef CONFIG_REGULATOR
+	&smdk6410_b_pwr_5v,
+#endif
 	&smdk6410_lcd_powerdev,
 
 	&smdk6410_smsc911x,
@@ -232,6 +274,14 @@ static struct regulator_init_data wm8350_dcdc3_data = {
 };
 
 /* USB, EXT, PCM, ADC/DAC, USB, MMC */
+static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
+	{
+		/* WM8580 */
+		.supply = "DVDD",
+		.dev_name = "0-001b",
+	},
+};
+
 static struct regulator_init_data wm8350_dcdc4_data = {
 	.constraints = {
 		.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
@@ -239,6 +289,8 @@ static struct regulator_init_data wm8350_dcdc4_data = {
 		.max_uV = 3000000,
 		.always_on = 1,
 	},
+	.num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers),
+	.consumer_supplies = wm8350_dcdc4_consumers,
 };
 
 /* ARM core */
-- 
1.6.5.2

[PATCH 4/9] S3C64XX: Provide logging when CPU frequencies are eliminated due to clocks

[Mark Brown]

This provides symmetry with the voltage based checks done for the
regulator.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
 arch/arm/plat-s3c64xx/cpufreq.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c
index e6e0843..bdc3c96 100644
--- a/arch/arm/plat-s3c64xx/cpufreq.c
+++ b/arch/arm/plat-s3c64xx/cpufreq.c
@@ -217,8 +217,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 		/* Check for frequencies we can generate */
 		r = clk_round_rate(armclk, freq->frequency * 1000);
 		r /= 1000;
-		if (r != freq->frequency)
+		if (r != freq->frequency) {
+			pr_debug("cpufreq: %dkHz unsupported by clock\n",
+				 freq->frequency);
 			freq->frequency = CPUFREQ_ENTRY_INVALID;
+		}
 
 		/* If we have no regulator then assume startup
 		 * frequency is the maximum we can support. */
-- 
1.6.5.2

[PATCH 5/9] S3C64XX: Set rate of crystal mux

[Mark Brown]

The current code assumes that the external clock mux will be set to
the crystal. Set this up explicitly within the clock API.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
 arch/arm/plat-s3c64xx/s3c6400-clock.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 9745852..6ffa21e 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -677,6 +677,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
 
 	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 
+	/* For now assume the mux always selects the crystal */
+	clk_ext_xtal_mux.parent = xtal_clk;
+
 	epll = s3c6400_get_epll(xtal);
 	mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
 	apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
-- 
1.6.5.2

[PATCH 6/9] S3C64XX: Provide control of APLL

[Mark Brown]

Set up runtime control of APLL in the clock API. Since both APLL and
MPLL use the same IP a generic PLL6552 clock is provided but at present
only APLL is hooked up.  Since the documentation recommends using only
one of a specific list of configurations we do not attempt to calculate
arbatrary PLL setups but instead choose from that list.

Note that reconfiguration of APLL may not be safe when SYNCMUX is set to
clock HCLKx2 from the APLL mux since it will also change the state of
that tree without notice.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
 arch/arm/plat-s3c64xx/s3c6400-clock.c |   83 +++++++++++++++++++++++++++++++--
 1 files changed, 78 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c
index 6ffa21e..3fa16b7 100644
--- a/arch/arm/plat-s3c64xx/s3c6400-clock.c
+++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c
@@ -63,14 +63,86 @@ struct clksrc_clk {
 	void __iomem		*reg_divider;
 };
 
-static struct clk clk_fout_apll = {
-	.name		= "fout_apll",
-	.id		= -1,
+#define PLL6552_CON(mdiv, pdiv, sdiv) (0x8000000 | (mdiv << 16) | \
+				       (pdiv << 8) | sdiv)
+#define PLL6552_MASK PLL6552_CON(0x1f, 0x3ff, 7)
+
+/* While PLL output can be calculated as MDIV * input / (PDIV *
+ * 2^SDIV) the datasheet recommends using one of the configurations
+ * listed below.
+ */
+static const struct {
+	int input;
+	int output;
+	u32 reg;
+} pll6552_cfg[] = {
+	{ 12000000, 0,         0                      },
+	{ 12000000, 100000000, PLL6552_CON(400, 3, 4) },
+	{ 12000000, 200000000, PLL6552_CON(400, 3, 3) },
+	{ 12000000, 266000000, PLL6552_CON(266, 3, 2) },
+	{ 12000000, 400000000, PLL6552_CON(400, 3, 2) },
+	{ 12000000, 533000000, PLL6552_CON(266, 3, 1) },
+	{ 12000000, 667000000, PLL6552_CON(333, 3, 1) },
+	{ 27000000, 0,         0                      },
+	{ 27000000, 100000000, PLL6552_CON(474, 8, 4) },
+	{ 27000000, 200000000, PLL6552_CON(474, 8, 3) },
+	{ 27000000, 266000000, PLL6552_CON(276, 7, 2) },
+	{ 27000000, 400000000, PLL6552_CON(474, 8, 2) },
+	{ 27000000, 533000000, PLL6552_CON(276, 7, 1) },
+	{ 27000000, 667000000, PLL6552_CON(346, 7, 1) },
+};
+
+struct pll6552_clk {
+	struct clk		clk;
+	void __iomem		*pll_con;
+};
+
+static unsigned long pll6552_get_rate(struct clk *clk)
+{
+	unsigned long parent = clk_get_rate(clk->parent);
+	struct pll6552_clk *pll6552 =
+		container_of(clk, struct pll6552_clk, clk);
+
+	return s3c6400_get_pll(parent, __raw_readl(pll6552->pll_con));
+}
+
+static int pll6552_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long parent = clk_get_rate(clk->parent);
+	struct pll6552_clk *pll6552 =
+		container_of(clk, struct pll6552_clk, clk);
+	int i;
+	u32 val;
+
+	for (i = 0; i < ARRAY_SIZE(pll6552_cfg); i++)
+		if (pll6552_cfg[i].input == parent &&
+		    pll6552_cfg[i].output == rate)
+			break;
+	if (i == ARRAY_SIZE(pll6552_cfg))
+		return -EINVAL;
+
+	val = __raw_readl(pll6552->pll_con);
+	val &= ~PLL6552_MASK;
+	val |= pll6552_cfg[i].reg;
+
+	__raw_writel(val, pll6552->pll_con);
+
+	return 0;
+}
+
+static struct pll6552_clk clk_fout_apll = {
+	.clk = {
+		.name		= "fout_apll",
+		.id		= -1,
+		.get_rate	= pll6552_get_rate,
+		.set_rate	= pll6552_set_rate,
+	},
+	.pll_con = S3C_APLL_CON,
 };
 
 static struct clk *clk_src_apll_list[] = {
 	[0] = &clk_fin_apll,
-	[1] = &clk_fout_apll,
+	[1] = &clk_fout_apll.clk,
 };
 
 static struct clk_sources clk_src_apll = {
@@ -698,7 +770,6 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
 
 	clk_fout_mpll.rate = mpll;
 	clk_fout_epll.rate = epll;
-	clk_fout_apll.rate = apll;
 
 	clk_h2.rate = hclk2;
 	clk_h.rate = hclk;
@@ -729,6 +800,7 @@ static struct clk *clks[] __initdata = {
 	&clk_audio1.clk,
 	&clk_irda.clk,
 	&clk_camif.clk,
+	&clk_fout_apll.clk,
 	&clk_arm,
 };
 
@@ -761,6 +833,7 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit)
 		}
 	}
 
+	clk_fout_apll.clk.parent = &clk_fin_apll;
 	clk_mpll.parent = &clk_mout_mpll.clk;
 	clk_epll.parent = &clk_mout_epll.clk;
 }
-- 
1.6.5.2

[PATCH 7/9] SMDK6410: Allocate more GPIO space for WM1190-EV1

[Mark Brown]

The WM835x has some GPIOs on it, allocate some space so we can use
them with gpiolib.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
 arch/arm/mach-s3c6410/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig
index b8c0332..162f456 100644
--- a/arch/arm/mach-s3c6410/Kconfig
+++ b/arch/arm/mach-s3c6410/Kconfig
@@ -75,6 +75,7 @@ config SMDK6410_WM1190_EV1
 	depends on MACH_SMDK6410
 	select REGULATOR
 	select REGULATOR_WM8350
+	select S3C24XX_GPIO_EXTRA64
 	select MFD_WM8350_I2C
 	select MFD_WM8350_CONFIG_MODE_0
 	select MFD_WM8350_CONFIG_MODE_3
-- 
1.6.5.2

[PATCH 8/9] S3C64XX: Separate out regulator and frequency latencies

[Mark Brown]

Currently the transition latency reported by the S3C64xx cpufreq
driver includes both the time for the CPU to reclock itself and
the time for a regulator to change voltage. This means that if
a regulator is not in use then the transition latency reported
is excessively high.

In future the regulator API will be extended to report latencies
so the driver will be able to query the performance of a given
regulator.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
 arch/arm/plat-s3c64xx/cpufreq.c |   20 +++++++++++++-------
 1 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c
index bdc3c96..61276bf 100644
--- a/arch/arm/plat-s3c64xx/cpufreq.c
+++ b/arch/arm/plat-s3c64xx/cpufreq.c
@@ -19,6 +19,7 @@
 
 static struct clk *armclk;
 static struct regulator *vddarm;
+static unsigned long regulator_latency;
 
 #ifdef CONFIG_CPU_S3C6410
 struct s3c64xx_dvfs {
@@ -141,7 +142,7 @@ err:
 }
 
 #ifdef CONFIG_REGULATOR
-static void __init s3c64xx_cpufreq_constrain_voltages(void)
+static void __init s3c64xx_cpufreq_config_regulator(void)
 {
 	int count, v, i, found;
 	struct cpufreq_frequency_table *freq;
@@ -150,11 +151,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
 	count = regulator_count_voltages(vddarm);
 	if (count < 0) {
 		pr_err("cpufreq: Unable to check supported voltages\n");
-		return;
 	}
 
 	freq = s3c64xx_freq_table;
-	while (freq->frequency != CPUFREQ_TABLE_END) {
+	while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
 		if (freq->frequency == CPUFREQ_ENTRY_INVALID)
 			continue;
 
@@ -175,6 +175,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void)
 
 		freq++;
 	}
+
+	/* Guess based on having to do an I2C/SPI write; in future we
+	 * will be able to query the regulator performance here. */
+	regulator_latency = 1 * 1000 * 1000;
 }
 #endif
 
@@ -206,7 +210,7 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 		pr_err("cpufreq: Only frequency scaling available\n");
 		vddarm = NULL;
 	} else {
-		s3c64xx_cpufreq_constrain_voltages();
+		s3c64xx_cpufreq_config_regulator();
 	}
 #endif
 
@@ -233,9 +237,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
 
 	policy->cur = clk_get_rate(armclk) / 1000;
 
-	/* Pick a conservative guess in ns: we'll need ~1 I2C/SPI
-	 * write plus clock reprogramming. */
-	policy->cpuinfo.transition_latency = 2 * 1000 * 1000;
+	/* Datasheet says PLL stabalisation time (if we were to use
+	 * the PLLs, which we don't currently) is ~300us worst case,
+	 * but add some fudge.
+	 */
+	policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
 
 	ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
 	if (ret != 0) {
-- 
1.6.5.2

[PATCH 9/9] S3C64XX: Redo voltage ranges for cpufreq

[Mark Brown]

The documentation for the S3C6410 CPU voltage scaling is rather
unclear, with omitted values for several speed settings. Originally
the code was using only quoted values, resulting in some fairly odd
settings. The S3C6410 is also unusual in that the both the maximum
and minimum voltages quoted scale as the frequency rises, rather
than just the minimum voltage.

Clean this up a bit by always using the specified typical settings
as the minimum voltage (ignoring any specified minimum voltage) in
order to avoid running near the edge of the processor capabilities.
Also use the next quoted maximum voltages rather than the typical
voltages where no maximum voltage is quoted, allowing operation on
a greater range of systems.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
---
 arch/arm/plat-s3c64xx/cpufreq.c |   15 +++++++--------
 1 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c
index 61276bf..74c0e83 100644
--- a/arch/arm/plat-s3c64xx/cpufreq.c
+++ b/arch/arm/plat-s3c64xx/cpufreq.c
@@ -28,11 +28,10 @@ struct s3c64xx_dvfs {
 };
 
 static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
-	[0] = { 1000000, 1000000 },
-	[1] = { 1000000, 1050000 },
-	[2] = { 1050000, 1100000 },
-	[3] = { 1050000, 1150000 },
-	[4] = { 1250000, 1350000 },
+	[0] = { 1000000, 1150000 },
+	[1] = { 1050000, 1150000 },
+	[2] = { 1100000, 1150000 },
+	[3] = { 1200000, 1350000 },
 };
 
 static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
@@ -42,9 +41,9 @@ static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
 	{ 1, 266000 },
 	{ 2, 333000 },
 	{ 2, 400000 },
-	{ 3, 532000 },
-	{ 3, 533000 },
-	{ 4, 667000 },
+	{ 2, 532000 },
+	{ 2, 533000 },
+	{ 3, 667000 },
 	{ 0, CPUFREQ_TABLE_END },
 };
 #endif
-- 
1.6.5.2

[PATCH 2/9] S3C64XX: Fix S3C64XX_CLKDIV0_ARM_MASK value

[Ben Dooks]

On Tue, Nov 03, 2009 at 02:42:05PM +0000, Mark Brown wrote:
> From: Kukjin Kim <kgene.kim@samsung.com>
> 
> The value of S3C64XX_CLKDIV0_ARM_MASK is wrong. This patch fixes
> this values, S3C6400_CLKDIV0_ARM_MASK and S3C6410_CLKDIV0_ARM_MASK.

this should be merged now.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.

[PATCH 5/9] S3C64XX: Set rate of crystal mux

[Ben Dooks]

On Tue, Nov 03, 2009 at 02:42:08PM +0000, Mark Brown wrote:
> The current code assumes that the external clock mux will be set to
> the crystal. Set this up explicitly within the clock API.

should be merged now.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.