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* [PATCH] drm/radeon/kms: implement reading PCIE lanes on R600+
@ 2010-02-17 22:57 Rafał Miłecki
  2010-02-18  4:57 ` Dave Airlie
  2010-02-18 15:20 ` Alex Deucher
  0 siblings, 2 replies; 6+ messages in thread
From: Rafał Miłecki @ 2010-02-17 22:57 UTC (permalink / raw)
  To: dri-devel, Dave Airlie

Ported from DDX

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
---
 drivers/gpu/drm/radeon/r300.c        |    5 ++++-
 drivers/gpu/drm/radeon/radeon.h      |   14 ++++++++++++++
 drivers/gpu/drm/radeon/radeon_asic.h |    4 ++--
 drivers/gpu/drm/radeon/radeon_pm.c   |    2 ++
 4 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 654aca1..cd92880 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -593,7 +593,10 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev)
 
 	/* FIXME wait for idle */
 
-	link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+	if (rdev->family < CHIP_R600)
+		link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
+	else
+		link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
 
 	switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
 	case RADEON_PCIE_LC_LINK_WIDTH_X0:
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index b533411..db98924 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1009,6 +1009,8 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
+#define RREG32_PCIE_P(reg) r600_pcie_port_rreg(rdev, (reg))
+#define WREG32_PCIE_P(reg, v) r600_pcie_port_wreg(rdev, (reg), (v))
 #define WREG32_P(reg, val, mask)				\
 	do {							\
 		uint32_t tmp_ = RREG32(reg);			\
@@ -1043,6 +1045,18 @@ static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uin
 	WREG32(RADEON_PCIE_DATA, (v));
 }
 
+static inline uint32_t r600_pcie_port_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+	WREG32(R600_PCIE_PORT_INDEX, ((reg) & rdev->pcie_reg_mask));
+	return RREG32(R600_PCIE_PORT_DATA);
+}
+
+static inline void r600_pcie_port_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+	WREG32(R600_PCIE_PORT_INDEX, ((reg) & rdev->pcie_reg_mask));
+	WREG32(R600_PCIE_PORT_DATA, (v));
+}
+
 void r100_pll_errata_after_index(struct radeon_device *rdev);
 
 
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 4b0cb67..735d594 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -547,7 +547,7 @@ static struct radeon_asic r600_asic = {
 	.set_engine_clock = &radeon_atom_set_engine_clock,
 	.get_memory_clock = &radeon_atom_get_memory_clock,
 	.set_memory_clock = &radeon_atom_set_memory_clock,
-	.get_pcie_lanes = NULL,
+	.get_pcie_lanes = &rv370_get_pcie_lanes,
 	.set_pcie_lanes = NULL,
 	.set_clock_gating = NULL,
 	.set_surface_reg = r600_set_surface_reg,
@@ -593,7 +593,7 @@ static struct radeon_asic rv770_asic = {
 	.set_engine_clock = &radeon_atom_set_engine_clock,
 	.get_memory_clock = &radeon_atom_get_memory_clock,
 	.set_memory_clock = &radeon_atom_set_memory_clock,
-	.get_pcie_lanes = NULL,
+	.get_pcie_lanes = &rv370_get_pcie_lanes,
 	.set_pcie_lanes = NULL,
 	.set_clock_gating = &radeon_atom_set_clock_gating,
 	.set_surface_reg = r600_set_surface_reg,
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 8426aff..3b00202 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -441,6 +441,8 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 	seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 	if (rdev->asic->get_memory_clock)
 		seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
+	if (rdev->asic->get_pcie_lanes)
+		seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 
 	return 0;
 }
-- 
1.6.4.2


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^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/radeon/kms: implement reading PCIE lanes on R600+
  2010-02-17 22:57 [PATCH] drm/radeon/kms: implement reading PCIE lanes on R600+ Rafał Miłecki
@ 2010-02-18  4:57 ` Dave Airlie
  2010-02-18 11:40   ` Rafał Miłecki
  2010-02-18 15:19   ` Alex Deucher
  2010-02-18 15:20 ` Alex Deucher
  1 sibling, 2 replies; 6+ messages in thread
From: Dave Airlie @ 2010-02-18  4:57 UTC (permalink / raw)
  To: Rafał Miłecki; +Cc: dri-devel

2010/2/18 Rafał Miłecki <zajec5@gmail.com>:
> Ported from DDX
>

The PCIE regs on r600 are the same offsets at the ones on rv370 from
what I can see
probably don't need to add a new PCIE_P struct at all I think the
rv370 functions should work.

Dave.

------------------------------------------------------------------------------
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proactively, and fine-tune applications for parallel performance. 
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^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/radeon/kms: implement reading PCIE lanes on R600+
  2010-02-18  4:57 ` Dave Airlie
@ 2010-02-18 11:40   ` Rafał Miłecki
  2010-02-18 15:19   ` Alex Deucher
  1 sibling, 0 replies; 6+ messages in thread
From: Rafał Miłecki @ 2010-02-18 11:40 UTC (permalink / raw)
  To: Dave Airlie; +Cc: dri-devel

W dniu 18 lutego 2010 05:57 użytkownik Dave Airlie <airlied@gmail.com> napisał:
> 2010/2/18 Rafał Miłecki <zajec5@gmail.com>:
>> Ported from DDX
>>
>
> The PCIE regs on r600 are the same offsets at the ones on rv370 from
> what I can see
> probably don't need to add a new PCIE_P struct at all I think the
> rv370 functions should work.

Err, not really?

# egrep --color "define.*PCIE_(PORT_)?INDEX" ./*h
./r600_reg.h:#define R600_PCIE_PORT_INDEX                0x0038
./radeon_reg.h:#define RADEON_PCIE_INDEX               0x0030

# egrep --color "define.*PCIE_(PORT_)?DATA" ./*h
./r600_reg.h:#define R600_PCIE_PORT_DATA                 0x003c
./radeon_reg.h:#define RADEON_PCIE_DATA                0x0034

-- 
Rafał

------------------------------------------------------------------------------
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proactively, and fine-tune applications for parallel performance. 
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^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/radeon/kms: implement reading PCIE lanes on R600+
  2010-02-18  4:57 ` Dave Airlie
  2010-02-18 11:40   ` Rafał Miłecki
@ 2010-02-18 15:19   ` Alex Deucher
  1 sibling, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2010-02-18 15:19 UTC (permalink / raw)
  To: Dave Airlie; +Cc: dri-devel

2010/2/17 Dave Airlie <airlied@gmail.com>:
> 2010/2/18 Rafał Miłecki <zajec5@gmail.com>:
>> Ported from DDX
>>
>
> The PCIE regs on r600 are the same offsets at the ones on rv370 from
> what I can see
> probably don't need to add a new PCIE_P struct at all I think the
> rv370 functions should work.
>

There are PCIE index regs at the same offset, but the PCIE lane
controls moved to the PCIE PORT index.

Alex

> Dave.
>
> ------------------------------------------------------------------------------
> Download Intel&reg; Parallel Studio Eval
> Try the new software tools for yourself. Speed compiling, find bugs
> proactively, and fine-tune applications for parallel performance.
> See why Intel Parallel Studio got high marks during beta.
> http://p.sf.net/sfu/intel-sw-dev
> --
> _______________________________________________
> Dri-devel mailing list
> Dri-devel@lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/dri-devel
>

------------------------------------------------------------------------------
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Try the new software tools for yourself. Speed compiling, find bugs 
proactively, and fine-tune applications for parallel performance. 
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
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^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/radeon/kms: implement reading PCIE lanes on R600+
  2010-02-17 22:57 [PATCH] drm/radeon/kms: implement reading PCIE lanes on R600+ Rafał Miłecki
  2010-02-18  4:57 ` Dave Airlie
@ 2010-02-18 15:20 ` Alex Deucher
  2010-02-18 19:10   ` Rafał Miłecki
  1 sibling, 1 reply; 6+ messages in thread
From: Alex Deucher @ 2010-02-18 15:20 UTC (permalink / raw)
  To: Rafał Miłecki; +Cc: dri-devel

2010/2/17 Rafał Miłecki <zajec5@gmail.com>:
> Ported from DDX
>
> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
> ---
>  drivers/gpu/drm/radeon/r300.c        |    5 ++++-
>  drivers/gpu/drm/radeon/radeon.h      |   14 ++++++++++++++
>  drivers/gpu/drm/radeon/radeon_asic.h |    4 ++--
>  drivers/gpu/drm/radeon/radeon_pm.c   |    2 ++
>  4 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
> index 654aca1..cd92880 100644
> --- a/drivers/gpu/drm/radeon/r300.c
> +++ b/drivers/gpu/drm/radeon/r300.c
> @@ -593,7 +593,10 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev)
>
>        /* FIXME wait for idle */
>
> -       link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
> +       if (rdev->family < CHIP_R600)
> +               link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
> +       else
> +               link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
>
>        switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
>        case RADEON_PCIE_LC_LINK_WIDTH_X0:
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index b533411..db98924 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -1009,6 +1009,8 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
>  #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
>  #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
>  #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
> +#define RREG32_PCIE_P(reg) r600_pcie_port_rreg(rdev, (reg))
> +#define WREG32_PCIE_P(reg, v) r600_pcie_port_wreg(rdev, (reg), (v))
>  #define WREG32_P(reg, val, mask)                               \
>        do {                                                    \
>                uint32_t tmp_ = RREG32(reg);                    \
> @@ -1043,6 +1045,18 @@ static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uin
>        WREG32(RADEON_PCIE_DATA, (v));
>  }
>
> +static inline uint32_t r600_pcie_port_rreg(struct radeon_device *rdev, uint32_t reg)
> +{
> +       WREG32(R600_PCIE_PORT_INDEX, ((reg) & rdev->pcie_reg_mask));
> +       return RREG32(R600_PCIE_PORT_DATA);
> +}
> +
> +static inline void r600_pcie_port_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
> +{
> +       WREG32(R600_PCIE_PORT_INDEX, ((reg) & rdev->pcie_reg_mask));
> +       WREG32(R600_PCIE_PORT_DATA, (v));
> +}
> +

These already exist in r600.c:
r600_pciep_rreg
r600_pciep_wreg

Alex

>  void r100_pll_errata_after_index(struct radeon_device *rdev);
>
>
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
> index 4b0cb67..735d594 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.h
> +++ b/drivers/gpu/drm/radeon/radeon_asic.h
> @@ -547,7 +547,7 @@ static struct radeon_asic r600_asic = {
>        .set_engine_clock = &radeon_atom_set_engine_clock,
>        .get_memory_clock = &radeon_atom_get_memory_clock,
>        .set_memory_clock = &radeon_atom_set_memory_clock,
> -       .get_pcie_lanes = NULL,
> +       .get_pcie_lanes = &rv370_get_pcie_lanes,
>        .set_pcie_lanes = NULL,
>        .set_clock_gating = NULL,
>        .set_surface_reg = r600_set_surface_reg,
> @@ -593,7 +593,7 @@ static struct radeon_asic rv770_asic = {
>        .set_engine_clock = &radeon_atom_set_engine_clock,
>        .get_memory_clock = &radeon_atom_get_memory_clock,
>        .set_memory_clock = &radeon_atom_set_memory_clock,
> -       .get_pcie_lanes = NULL,
> +       .get_pcie_lanes = &rv370_get_pcie_lanes,
>        .set_pcie_lanes = NULL,
>        .set_clock_gating = &radeon_atom_set_clock_gating,
>        .set_surface_reg = r600_set_surface_reg,
> diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
> index 8426aff..3b00202 100644
> --- a/drivers/gpu/drm/radeon/radeon_pm.c
> +++ b/drivers/gpu/drm/radeon/radeon_pm.c
> @@ -441,6 +441,8 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
>        seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
>        if (rdev->asic->get_memory_clock)
>                seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
> +       if (rdev->asic->get_pcie_lanes)
> +               seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
>
>        return 0;
>  }
> --
> 1.6.4.2
>
>
> ------------------------------------------------------------------------------
> Download Intel&reg; Parallel Studio Eval
> Try the new software tools for yourself. Speed compiling, find bugs
> proactively, and fine-tune applications for parallel performance.
> See why Intel Parallel Studio got high marks during beta.
> http://p.sf.net/sfu/intel-sw-dev
> --
> _______________________________________________
> Dri-devel mailing list
> Dri-devel@lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/dri-devel
>

------------------------------------------------------------------------------
Download Intel&reg; Parallel Studio Eval
Try the new software tools for yourself. Speed compiling, find bugs 
proactively, and fine-tune applications for parallel performance. 
See why Intel Parallel Studio got high marks during beta.
http://p.sf.net/sfu/intel-sw-dev
--
_______________________________________________
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^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [PATCH] drm/radeon/kms: implement reading PCIE lanes on R600+
  2010-02-18 15:20 ` Alex Deucher
@ 2010-02-18 19:10   ` Rafał Miłecki
  0 siblings, 0 replies; 6+ messages in thread
From: Rafał Miłecki @ 2010-02-18 19:10 UTC (permalink / raw)
  To: Alex Deucher; +Cc: dri-devel

W dniu 18 lutego 2010 16:20 użytkownik Alex Deucher
<alexdeucher@gmail.com> napisał:
> 2010/2/17 Rafał Miłecki <zajec5@gmail.com>:
>> Ported from DDX
>>
>> Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
>> ---
>>  drivers/gpu/drm/radeon/r300.c        |    5 ++++-
>>  drivers/gpu/drm/radeon/radeon.h      |   14 ++++++++++++++
>>  drivers/gpu/drm/radeon/radeon_asic.h |    4 ++--
>>  drivers/gpu/drm/radeon/radeon_pm.c   |    2 ++
>>  4 files changed, 22 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
>> index 654aca1..cd92880 100644
>> --- a/drivers/gpu/drm/radeon/r300.c
>> +++ b/drivers/gpu/drm/radeon/r300.c
>> @@ -593,7 +593,10 @@ int rv370_get_pcie_lanes(struct radeon_device *rdev)
>>
>>        /* FIXME wait for idle */
>>
>> -       link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
>> +       if (rdev->family < CHIP_R600)
>> +               link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
>> +       else
>> +               link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
>>
>>        switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
>>        case RADEON_PCIE_LC_LINK_WIDTH_X0:
>> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
>> index b533411..db98924 100644
>> --- a/drivers/gpu/drm/radeon/radeon.h
>> +++ b/drivers/gpu/drm/radeon/radeon.h
>> @@ -1009,6 +1009,8 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
>>  #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
>>  #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
>>  #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
>> +#define RREG32_PCIE_P(reg) r600_pcie_port_rreg(rdev, (reg))
>> +#define WREG32_PCIE_P(reg, v) r600_pcie_port_wreg(rdev, (reg), (v))
>>  #define WREG32_P(reg, val, mask)                               \
>>        do {                                                    \
>>                uint32_t tmp_ = RREG32(reg);                    \
>> @@ -1043,6 +1045,18 @@ static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uin
>>        WREG32(RADEON_PCIE_DATA, (v));
>>  }
>>
>> +static inline uint32_t r600_pcie_port_rreg(struct radeon_device *rdev, uint32_t reg)
>> +{
>> +       WREG32(R600_PCIE_PORT_INDEX, ((reg) & rdev->pcie_reg_mask));
>> +       return RREG32(R600_PCIE_PORT_DATA);
>> +}
>> +
>> +static inline void r600_pcie_port_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
>> +{
>> +       WREG32(R600_PCIE_PORT_INDEX, ((reg) & rdev->pcie_reg_mask));
>> +       WREG32(R600_PCIE_PORT_DATA, (v));
>> +}
>> +
>
> These already exist in r600.c:
> r600_pciep_rreg
> r600_pciep_wreg

Oh, didn't notice that because it uses duplicated definition:
./r600d.h:#define       PCIE_PORT_INDEX                                 0x0038
./r600_reg.h:#define R600_PCIE_PORT_INDEX                0x0038

-- 
Rafał

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^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2010-02-18 19:10 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2010-02-17 22:57 [PATCH] drm/radeon/kms: implement reading PCIE lanes on R600+ Rafał Miłecki
2010-02-18  4:57 ` Dave Airlie
2010-02-18 11:40   ` Rafał Miłecki
2010-02-18 15:19   ` Alex Deucher
2010-02-18 15:20 ` Alex Deucher
2010-02-18 19:10   ` Rafał Miłecki

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