[PATCH v2] generic clk module removal

[PATCH v2] generic clk module removal

[Omar Ramirez Luna]

This set of patches remove clk module from the services layer.

Now:
- GPT 5-8 are controlled through DM Timer framework.
- MCBSP clocks are enabled by requesting the proper mcbsp device.
- WDT is left for bridge driver to control rather than on request from dsp.
- SSI is controlled by enabling/disabling its sst, ssr and ick clocks.

v2:
- rebased
- keep iva2 handling as it is advised to turn off the clocks for iva reset
  sources.
- release all the clocks (disable & free) if driver is uninstalled.


Omar Ramirez Luna (5):
  DSPBRIDGE: iva2 clock handling
  DSPBRIDGE: dsp interface to enable ssi clocks
  DSPBRIDGE: Balance the number of enable/disable
  DSPBRIDGE: move clk to dsp-clock
  DSPBRIDGE: reorganize the code to handle peripheral clocks
  DSPBRIDGE: remove clk_handle from drv interface
  DSPBRIDGE: fail if clk handle is NULL
  DSPBRIDGE: Now actually fail if a clk handle is wrong
  DSPBRIDGE: Rename services_clk_* to dsp_clk_*
  DSPBRIDGE: remove unused clock sys_ck
  DSPBRIDGE: remove function clk_set32k_hz
  DSPBRIDGE: remove clk_get_use_cnt
  DSPBRIDGE: trivial clock cleanup for unused code
  DSPBRIDGE: function to get the type of clock requested by dsp
  DSPBRIDGE: use dm timer framework for gpt timers
  DSPBRIDGE: use omap mcbsp to enable mcbsp clocks
  DSPBRIDGE: remove wdt3 from dsp control
  DSPBRIDGE: use one call for both ick and fck clocks
  DSPBRIDGE: Move MCBSP_CLOCKS code to a common place

 arch/arm/plat-omap/include/dspbridge/clk.h |  103 ++------
 drivers/dsp/bridge/Makefile                |    4 +-
 drivers/dsp/bridge/rmgr/drv_interface.c    |   12 +-
 drivers/dsp/bridge/services/clk.c          |  323 ------------------------
 drivers/dsp/bridge/services/services.c     |   10 +-
 drivers/dsp/bridge/wmd/_tiomap.h           |   25 +-
 drivers/dsp/bridge/wmd/_tiomap_pwr.h       |   17 --
 drivers/dsp/bridge/wmd/dsp-clock.c         |  377 ++++++++++++++++++++++++++++
 drivers/dsp/bridge/wmd/tiomap3430.c        |   62 +-----
 drivers/dsp/bridge/wmd/tiomap3430_pwr.c    |  147 +----------
 drivers/dsp/bridge/wmd/tiomap_io.c         |    4 +-
 drivers/dsp/bridge/wmd/ue_deh.c            |    2 +-
 12 files changed, 440 insertions(+), 646 deletions(-)
 delete mode 100644 drivers/dsp/bridge/services/clk.c
 create mode 100644 drivers/dsp/bridge/wmd/dsp-clock.c

[PATCH v2] DSPBRIDGE: remove clk_handle from drv interface

[Omar Ramirez Luna]

Since it is not used, remove.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/rmgr/drv_interface.c |    9 ---------
 1 files changed, 0 insertions(+), 9 deletions(-)

diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c b/drivers/dsp/bridge/rmgr/drv_interface.c
index 2f92278..ea2a5f3 100644
--- a/drivers/dsp/bridge/rmgr/drv_interface.c
+++ b/drivers/dsp/bridge/rmgr/drv_interface.c
@@ -149,7 +149,6 @@ static struct file_operations bridge_fops = {
 #ifdef CONFIG_PM
 static u32 time_out = 1000;
 #ifdef CONFIG_BRIDGE_DVFS
-static struct clk *clk_handle;
 s32 dsp_max_opps = VDD1_OPP5;
 #endif
 
@@ -324,10 +323,6 @@ static int __devinit omap34_xx_bridge_probe(struct platform_device *pdev)
 		for (i = 0; i < 6; i++)
 			pdata->mpu_speed[i] = vdd1_rate_table_bridge[i].rate;
 
-		clk_handle = clk_get(NULL, "iva2_ck");
-		if (!clk_handle)
-			pr_err("%s: clk_get failed to get iva2_ck\n", __func__);
-
 		if (!cpufreq_register_notifier(&iva_clk_notifier,
 						CPUFREQ_TRANSITION_NOTIFIER))
 			pr_err("%s: clk_notifier_register failed for iva2_ck\n",
@@ -383,10 +378,6 @@ static int __devexit omap34_xx_bridge_remove(struct platform_device *pdev)
 		driver_context = 0;
 		DBC_ASSERT(ret == true);
 	}
-#ifdef CONFIG_BRIDGE_DVFS
-	clk_put(clk_handle);
-	clk_handle = NULL;
-#endif /* #ifdef CONFIG_BRIDGE_DVFS */
 
 func_cont:
 	mem_ext_phys_pool_release();
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: fail if clk handle is NULL

[Omar Ramirez Luna]

If we fail if a clk handle is NULL during initialization
then there is no need to keep checking every time if the
handle is NULL for enable/disable/set_32k/get_use_cnt.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/services/clk.c |   68 +++++++++++--------------------------
 1 files changed, 20 insertions(+), 48 deletions(-)

diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index fb2ca81..1089e72 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -130,7 +130,7 @@ bool services_clk_init(void)
 			pr_err("%s: failed to get clk handle %s, dev id = %d\n",
 			       __func__, services_clks[i].clk_name,
 			       services_clks[i].id);
-			/* should we fail here?? */
+			return false;
 		}
 		services_clks[i].clk_handle = clk_handle;
 		i++;
@@ -153,17 +153,11 @@ dsp_status services_clk_enable(IN enum services_clk_id clk_id)
 	DBC_REQUIRE(clk_id < SERVICESCLK_NOT_DEFINED);
 
 	clk_handle = services_clks[clk_id].clk_handle;
-	if (clk_handle) {
-		if (clk_enable(clk_handle)) {
-			pr_err("services_clk_enable: failed to Enable CLK %s, "
-			       "CLK dev id = %d\n",
-			       services_clks[clk_id].clk_name,
-			       services_clks[clk_id].id);
-			status = -EPERM;
-		}
-	} else {
-		pr_err("%s: failed to get CLK %s, CLK dev id = %d\n", __func__,
-		     services_clks[clk_id].clk_name, services_clks[clk_id].id);
+	if (clk_enable(clk_handle)) {
+		pr_err("services_clk_enable: failed to Enable CLK %s, "
+		       "CLK dev id = %d\n",
+		       services_clks[clk_id].clk_name,
+		       services_clks[clk_id].id);
 		status = -EPERM;
 	}
 	/* The SSI module need to configured not to have the Forced idle for
@@ -193,13 +187,11 @@ dsp_status clk_set32k_hz(IN enum services_clk_id clk_id)
 	DBC_REQUIRE(clk_id < SERVICESCLK_NOT_DEFINED);
 
 	clk_handle = services_clks[clk_id].clk_handle;
-	if (clk_handle) {
-		if (!(clk_set_parent(clk_handle, clk_parent) == 0x0)) {
-			pr_err("%s: failed for %s, dev id = %d\n", __func__,
-			       services_clks[clk_id].clk_name,
-			       services_clks[clk_id].id);
-			status = -EPERM;
-		}
+	if (!(clk_set_parent(clk_handle, clk_parent) == 0x0)) {
+		pr_err("%s: failed for %s, dev id = %d\n", __func__,
+		       services_clks[clk_id].clk_name,
+		       services_clks[clk_id].id);
+		status = -EPERM;
 	}
 	return status;
 }
@@ -231,15 +223,8 @@ dsp_status services_clk_disable(IN enum services_clk_id clk_id)
 	if (clk_id == SERVICESCLK_SSI_ICK)
 		ssi_clk_prepare(false);
 
-	if (clk_handle) {
-		clk_disable(clk_handle);
-	} else {
-		pr_err("services_clk_disable: failed to get CLK %s,"
-		       "CLK dev id = %d\n",
-		       services_clks[clk_id].clk_name,
-		       services_clks[clk_id].id);
-		status = -EPERM;
-	}
+	clk_disable(clk_handle);
+
 	return status;
 }
 
@@ -260,38 +245,25 @@ dsp_status services_clk_get_rate(IN enum services_clk_id clk_id, u32 *speedKhz)
 	*speedKhz = 0x0;
 
 	clk_handle = services_clks[clk_id].clk_handle;
-	if (clk_handle) {
-		clk_speed_hz = clk_get_rate(clk_handle);
-		*speedKhz = clk_speed_hz / 1000;
-		dev_dbg(bridge, "%s: clk_speed_hz = %d, speedinKhz = %d\n",
+	clk_speed_hz = clk_get_rate(clk_handle);
+	*speedKhz = clk_speed_hz / 1000;
+	dev_dbg(bridge, "%s: clk_speed_hz = %d, speedinKhz = %d\n",
 			__func__, clk_speed_hz, *speedKhz);
-	} else {
-		pr_err("%s: failed to get %s, dev Id = %d\n", __func__,
-		       services_clks[clk_id].clk_name,
-		       services_clks[clk_id].id);
-		status = -EPERM;
-	}
+
 	return status;
 }
 
 s32 clk_get_use_cnt(IN enum services_clk_id clk_id)
 {
-	dsp_status status = DSP_SOK;
 	struct clk *clk_handle;
 	s32 use_count = -1;
 	DBC_REQUIRE(clk_id < SERVICESCLK_NOT_DEFINED);
 
 	clk_handle = services_clks[clk_id].clk_handle;
 
-	if (clk_handle) {
-		/* FIXME: usecount shouldn't be used */
-		use_count = clk_handle->usecount;
-	} else {
-		pr_err("%s: failed to get %s, dev Id = %d\n", __func__,
-		       services_clks[clk_id].clk_name,
-		       services_clks[clk_id].id);
-		status = -EPERM;
-	}
+	/* FIXME: usecount shouldn't be used */
+	use_count = clk_handle->usecount;
+
 	return use_count;
 }
 
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: Now actually fail if a clk handle is wrong

[Omar Ramirez Luna]

The value returned by clk_get on error is not NULL.

This checks if the value returned is an error or not.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/services/clk.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index 1089e72..b9fb9ef 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -126,7 +126,7 @@ bool services_clk_init(void)
 		clk_handle = clk_get(&dspbridge_device.dev,
 				     services_clks[i].clk_name);
 
-		if (!clk_handle) {
+		if (IS_ERR(clk_handle)) {
 			pr_err("%s: failed to get clk handle %s, dev id = %d\n",
 			       __func__, services_clks[i].clk_name,
 			       services_clks[i].id);
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: Rename services_clk_* to dsp_clk_*

[Omar Ramirez Luna]

Rename services_clk_* to dsp_clk_*

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 arch/arm/plat-omap/include/dspbridge/clk.h |   78 ++++++++++++------------
 drivers/dsp/bridge/services/clk.c          |   88 ++++++++++++++--------------
 drivers/dsp/bridge/services/services.c     |    6 +-
 drivers/dsp/bridge/wmd/_tiomap.h           |   26 ++++----
 drivers/dsp/bridge/wmd/tiomap3430.c        |   10 ++--
 drivers/dsp/bridge/wmd/tiomap3430_pwr.c    |   16 +++---
 6 files changed, 112 insertions(+), 112 deletions(-)

diff --git a/arch/arm/plat-omap/include/dspbridge/clk.h b/arch/arm/plat-omap/include/dspbridge/clk.h
index c36b634..a547225 100644
--- a/arch/arm/plat-omap/include/dspbridge/clk.h
+++ b/arch/arm/plat-omap/include/dspbridge/clk.h
@@ -21,37 +21,37 @@
 
 	/* Generic TIMER object: */
 struct timer_object;
-enum services_clk_id {
-	SERVICESCLK_IVA2_CK = 0,
-	SERVICESCLK_GPT5_FCK,
-	SERVICESCLK_GPT5_ICK,
-	SERVICESCLK_GPT6_FCK,
-	SERVICESCLK_GPT6_ICK,
-	SERVICESCLK_GPT7_FCK,
-	SERVICESCLK_GPT7_ICK,
-	SERVICESCLK_GPT8_FCK,
-	SERVICESCLK_GPT8_ICK,
-	SERVICESCLK_WDT3_FCK,
-	SERVICESCLK_WDT3_ICK,
-	SERVICESCLK_MCBSP1_FCK,
-	SERVICESCLK_MCBSP1_ICK,
-	SERVICESCLK_MCBSP2_FCK,
-	SERVICESCLK_MCBSP2_ICK,
-	SERVICESCLK_MCBSP3_FCK,
-	SERVICESCLK_MCBSP3_ICK,
-	SERVICESCLK_MCBSP4_FCK,
-	SERVICESCLK_MCBSP4_ICK,
-	SERVICESCLK_MCBSP5_FCK,
-	SERVICESCLK_MCBSP5_ICK,
-	SERVICESCLK_SSI_FCK,
-	SERVICESCLK_SSI_ICK,
-	SERVICESCLK_SYS32K_CK,
-	SERVICESCLK_SYS_CK,
-	SERVICESCLK_NOT_DEFINED
+enum dsp_clk_id {
+	DSP_CLK_IVA2_CK = 0,
+	DSP_CLK_GPT5_FCK,
+	DSP_CLK_GPT5_ICK,
+	DSP_CLK_GPT6_FCK,
+	DSP_CLK_GPT6_ICK,
+	DSP_CLK_GPT7_FCK,
+	DSP_CLK_GPT7_ICK,
+	DSP_CLK_GPT8_FCK,
+	DSP_CLK_GPT8_ICK,
+	DSP_CLK_WDT3_FCK,
+	DSP_CLK_WDT3_ICK,
+	DSP_CLK_MCBSP1_FCK,
+	DSP_CLK_MCBSP1_ICK,
+	DSP_CLK_MCBSP2_FCK,
+	DSP_CLK_MCBSP2_ICK,
+	DSP_CLK_MCBSP3_FCK,
+	DSP_CLK_MCBSP3_ICK,
+	DSP_CLK_MCBSP4_FCK,
+	DSP_CLK_MCBSP4_ICK,
+	DSP_CLK_MCBSP5_FCK,
+	DSP_CLK_MCBSP5_ICK,
+	DSP_CLK_SSI_FCK,
+	DSP_CLK_SSI_ICK,
+	DSP_CLK_SYS32K_CK,
+	DSP_CLK_SYS_CK,
+	DSP_CLK_NOT_DEFINED
 };
 
 /*
- *  ======== clk_exit ========
+ *  ======== dsp_clk_exit ========
  *  Purpose:
  *      Discontinue usage of module; free resources when reference count
  *      reaches 0.
@@ -62,10 +62,10 @@ enum services_clk_id {
  *  Ensures:
  *      Resources used by module are freed when cRef reaches zero.
  */
-extern void clk_exit(void);
+extern void dsp_clk_exit(void);
 
 /*
- *  ======== services_clk_init ========
+ *  ======== dsp_clk_init ========
  *  Purpose:
  *      Initializes private state of CLK module.
  *  Parameters:
@@ -75,10 +75,10 @@ extern void clk_exit(void);
  *  Ensures:
  *      CLK initialized.
  */
-extern bool services_clk_init(void);
+extern bool dsp_clk_init(void);
 
 /*
- *  ======== services_clk_enable ========
+ *  ======== dsp_clk_enable ========
  *  Purpose:
  *      Enables the clock requested.
  *  Parameters:
@@ -88,10 +88,10 @@ extern bool services_clk_init(void);
  *  Requires:
  *  Ensures:
  */
-extern dsp_status services_clk_enable(IN enum services_clk_id clk_id);
+extern dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id);
 
 /*
- *  ======== services_clk_disable ========
+ *  ======== dsp_clk_disable ========
  *  Purpose:
  *      Disables the clock requested.
  *  Parameters:
@@ -101,10 +101,10 @@ extern dsp_status services_clk_enable(IN enum services_clk_id clk_id);
  *  Requires:
  *  Ensures:
  */
-extern dsp_status services_clk_disable(IN enum services_clk_id clk_id);
+extern dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id);
 
 /*
- *  ======== services_clk_get_rate ========
+ *  ======== dsp_clk_get_rate ========
  *  Purpose:
  *      Get the clock rate of requested clock.
  *  Parameters:
@@ -114,7 +114,7 @@ extern dsp_status services_clk_disable(IN enum services_clk_id clk_id);
  *  Requires:
  *  Ensures:
  */
-extern dsp_status services_clk_get_rate(IN enum services_clk_id clk_id,
+extern dsp_status dsp_clk_get_rate(IN enum dsp_clk_id clk_id,
 					u32 *speedMhz);
 /*
  *  ======== clk_set32k_hz ========
@@ -127,7 +127,7 @@ extern dsp_status services_clk_get_rate(IN enum services_clk_id clk_id,
  *  Requires:
  *  Ensures:
  */
-extern dsp_status clk_set32k_hz(IN enum services_clk_id clk_id);
+extern dsp_status clk_set32k_hz(IN enum dsp_clk_id clk_id);
 extern void ssi_clk_prepare(bool FLAG);
 
 /*
@@ -141,6 +141,6 @@ extern void ssi_clk_prepare(bool FLAG);
  *  Requires:
  *  Ensures:
  */
-extern s32 clk_get_use_cnt(IN enum services_clk_id clk_id);
+extern s32 clk_get_use_cnt(IN enum dsp_clk_id clk_id);
 
 #endif /* _SYNC_H */
diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index b9fb9ef..4101c38 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -42,16 +42,16 @@ typedef volatile unsigned long reg_uword32;
 #define SSI_SIDLE_SMARTIDLE		(2 << 3)
 #define SSI_MIDLE_NOIDLE		(1 << 12)
 
-struct services_clk_t {
+struct dsp_clk_t {
 	struct clk *clk_handle;
 	const char *clk_name;
 	int id;
 };
 
 /* The row order of the below array needs to match with the clock enumerations
- * 'services_clk_id' provided in the header file.. any changes in the
+ * 'dsp_clk_id' provided in the header file.. any changes in the
  * enumerations needs to be fixed in the array as well */
-static struct services_clk_t services_clks[] = {
+static struct dsp_clk_t dsp_clks[] = {
 	{NULL, "iva2_ck", -1},
 	{NULL, "gpt5_fck", -1},
 	{NULL, "gpt5_ick", -1},
@@ -86,31 +86,31 @@ struct timer_object {
 };
 
 /*
- *  ======== clk_exit ========
+ *  ======== dsp_clk_exit ========
  *  Purpose:
  *      Cleanup CLK module.
  */
-void clk_exit(void)
+void dsp_clk_exit(void)
 {
 	int i = 0;
 
 	/* Relinquish the clock handles */
-	while (i < SERVICESCLK_NOT_DEFINED) {
-		if (services_clks[i].clk_handle)
-			clk_put(services_clks[i].clk_handle);
+	while (i < DSP_CLK_NOT_DEFINED) {
+		if (dsp_clks[i].clk_handle)
+			clk_put(dsp_clks[i].clk_handle);
 
-		services_clks[i].clk_handle = NULL;
+		dsp_clks[i].clk_handle = NULL;
 		i++;
 	}
 
 }
 
 /*
- *  ======== services_clk_init ========
+ *  ======== dsp_clk_init ========
  *  Purpose:
  *      Initialize CLK module.
  */
-bool services_clk_init(void)
+bool dsp_clk_init(void)
 {
 	static struct platform_device dspbridge_device;
 	struct clk *clk_handle;
@@ -119,20 +119,20 @@ bool services_clk_init(void)
 	dspbridge_device.dev.bus = &platform_bus_type;
 
 	/* Get the clock handles from base port and store locally */
-	while (i < SERVICESCLK_NOT_DEFINED) {
+	while (i < DSP_CLK_NOT_DEFINED) {
 		/* get the handle from BP */
-		dspbridge_device.id = services_clks[i].id;
+		dspbridge_device.id = dsp_clks[i].id;
 
 		clk_handle = clk_get(&dspbridge_device.dev,
-				     services_clks[i].clk_name);
+				     dsp_clks[i].clk_name);
 
 		if (IS_ERR(clk_handle)) {
 			pr_err("%s: failed to get clk handle %s, dev id = %d\n",
-			       __func__, services_clks[i].clk_name,
-			       services_clks[i].id);
+			       __func__, dsp_clks[i].clk_name,
+			       dsp_clks[i].id);
 			return false;
 		}
-		services_clks[i].clk_handle = clk_handle;
+		dsp_clks[i].clk_handle = clk_handle;
 		i++;
 	}
 
@@ -140,24 +140,24 @@ bool services_clk_init(void)
 }
 
 /*
- *  ======== services_clk_enable ========
+ *  ======== dsp_clk_enable ========
  *  Purpose:
  *      Enable Clock .
  *
  */
-dsp_status services_clk_enable(IN enum services_clk_id clk_id)
+dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 {
 	dsp_status status = DSP_SOK;
 	struct clk *clk_handle;
 
-	DBC_REQUIRE(clk_id < SERVICESCLK_NOT_DEFINED);
+	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
 
-	clk_handle = services_clks[clk_id].clk_handle;
+	clk_handle = dsp_clks[clk_id].clk_handle;
 	if (clk_enable(clk_handle)) {
-		pr_err("services_clk_enable: failed to Enable CLK %s, "
+		pr_err("dsp_clk_enable: failed to Enable CLK %s, "
 		       "CLK dev id = %d\n",
-		       services_clks[clk_id].clk_name,
-		       services_clks[clk_id].id);
+		       dsp_clks[clk_id].clk_name,
+		       dsp_clks[clk_id].id);
 		status = -EPERM;
 	}
 	/* The SSI module need to configured not to have the Forced idle for
@@ -165,7 +165,7 @@ dsp_status services_clk_enable(IN enum services_clk_id clk_id)
 	 * transitioning to standby thereby causing the client in the DSP hang
 	 * waiting for the SSI module to be active after enabling the clocks
 	 */
-	if (clk_id == SERVICESCLK_SSI_FCK)
+	if (clk_id == DSP_CLK_SSI_FCK)
 		ssi_clk_prepare(true);
 
 	return status;
@@ -177,50 +177,50 @@ dsp_status services_clk_enable(IN enum services_clk_id clk_id)
  *      To Set parent of a clock to 32KHz.
  */
 
-dsp_status clk_set32k_hz(IN enum services_clk_id clk_id)
+dsp_status clk_set32k_hz(IN enum dsp_clk_id clk_id)
 {
 	dsp_status status = DSP_SOK;
 	struct clk *clk_handle;
 	struct clk *clk_parent;
-	clk_parent = services_clks[SERVICESCLK_SYS32K_CK].clk_handle;
+	clk_parent = dsp_clks[DSP_CLK_SYS32K_CK].clk_handle;
 
-	DBC_REQUIRE(clk_id < SERVICESCLK_NOT_DEFINED);
+	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
 
-	clk_handle = services_clks[clk_id].clk_handle;
+	clk_handle = dsp_clks[clk_id].clk_handle;
 	if (!(clk_set_parent(clk_handle, clk_parent) == 0x0)) {
 		pr_err("%s: failed for %s, dev id = %d\n", __func__,
-		       services_clks[clk_id].clk_name,
-		       services_clks[clk_id].id);
+		       dsp_clks[clk_id].clk_name,
+		       dsp_clks[clk_id].id);
 		status = -EPERM;
 	}
 	return status;
 }
 
 /*
- *  ======== services_clk_disable ========
+ *  ======== dsp_clk_disable ========
  *  Purpose:
  *      Disable the clock.
  *
  */
-dsp_status services_clk_disable(IN enum services_clk_id clk_id)
+dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 {
 	dsp_status status = DSP_SOK;
 	struct clk *clk_handle;
 	s32 clk_use_cnt;
 
-	DBC_REQUIRE(clk_id < SERVICESCLK_NOT_DEFINED);
+	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
 
-	clk_handle = services_clks[clk_id].clk_handle;
+	clk_handle = dsp_clks[clk_id].clk_handle;
 
 	clk_use_cnt = clk_get_use_cnt(clk_id);
 	if (clk_use_cnt == -1) {
 		pr_err("%s: failed to get CLK Use count for CLK %s, CLK dev id"
-		       " = %d\n", __func__, services_clks[clk_id].clk_name,
-		       services_clks[clk_id].id);
+		       " = %d\n", __func__, dsp_clks[clk_id].clk_name,
+		       dsp_clks[clk_id].id);
 	} else if (clk_use_cnt == 0) {
 		return status;
 	}
-	if (clk_id == SERVICESCLK_SSI_ICK)
+	if (clk_id == DSP_CLK_SSI_ICK)
 		ssi_clk_prepare(false);
 
 	clk_disable(clk_handle);
@@ -229,13 +229,13 @@ dsp_status services_clk_disable(IN enum services_clk_id clk_id)
 }
 
 /*
- *  ======== services_clk_get_rate ========
+ *  ======== dsp_clk_get_rate ========
  *  Purpose:
  *      GetClock Speed.
  *
  */
 
-dsp_status services_clk_get_rate(IN enum services_clk_id clk_id, u32 *speedKhz)
+dsp_status dsp_clk_get_rate(IN enum dsp_clk_id clk_id, u32 *speedKhz)
 {
 	dsp_status status = DSP_SOK;
 	struct clk *clk_handle;
@@ -244,7 +244,7 @@ dsp_status services_clk_get_rate(IN enum services_clk_id clk_id, u32 *speedKhz)
 	DBC_REQUIRE(clk_id < SERVICESCLK_NOT_DEFINED);
 	*speedKhz = 0x0;
 
-	clk_handle = services_clks[clk_id].clk_handle;
+	clk_handle = dsp_clks[clk_id].clk_handle;
 	clk_speed_hz = clk_get_rate(clk_handle);
 	*speedKhz = clk_speed_hz / 1000;
 	dev_dbg(bridge, "%s: clk_speed_hz = %d, speedinKhz = %d\n",
@@ -253,13 +253,13 @@ dsp_status services_clk_get_rate(IN enum services_clk_id clk_id, u32 *speedKhz)
 	return status;
 }
 
-s32 clk_get_use_cnt(IN enum services_clk_id clk_id)
+s32 clk_get_use_cnt(IN enum dsp_clk_id clk_id)
 {
 	struct clk *clk_handle;
 	s32 use_count = -1;
-	DBC_REQUIRE(clk_id < SERVICESCLK_NOT_DEFINED);
+	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
 
-	clk_handle = services_clks[clk_id].clk_handle;
+	clk_handle = dsp_clks[clk_id].clk_handle;
 
 	/* FIXME: usecount shouldn't be used */
 	use_count = clk_handle->usecount;
diff --git a/drivers/dsp/bridge/services/services.c b/drivers/dsp/bridge/services/services.c
index 19ab4d0..afb01be 100644
--- a/drivers/dsp/bridge/services/services.c
+++ b/drivers/dsp/bridge/services/services.c
@@ -43,7 +43,7 @@
 void services_exit(void)
 {
 	/* Uninitialize all SERVICES modules here */
-	clk_exit();
+	dsp_clk_exit();
 	cfg_exit();
 }
 
@@ -60,14 +60,14 @@ bool services_init(void)
 
 	/* Perform required initialization of SERVICES modules. */
 	fcfg = cfg_init();
-	fclk = services_clk_init();
+	fclk = dsp_clk_init();
 
 	ret = fcfg && fclk;
 
 	if (!ret) {
 
 		if (fclk)
-			clk_exit();
+			dsp_clk_exit();
 
 		if (fcfg)
 			cfg_exit();
diff --git a/drivers/dsp/bridge/wmd/_tiomap.h b/drivers/dsp/bridge/wmd/_tiomap.h
index bf3b849..887232b 100644
--- a/drivers/dsp/bridge/wmd/_tiomap.h
+++ b/drivers/dsp/bridge/wmd/_tiomap.h
@@ -246,22 +246,22 @@ static const u32 bpwr_clkid[] = {
 
 struct bpwr_clk_t {
 	u32 clk_id;
-	enum services_clk_id fun_clk;
-	enum services_clk_id int_clk;
+	enum dsp_clk_id fun_clk;
+	enum dsp_clk_id int_clk;
 };
 
 static const struct bpwr_clk_t bpwr_clks[] = {
-	{(u32) BPWR_GP_TIMER5, SERVICESCLK_GPT5_FCK, SERVICESCLK_GPT5_ICK},
-	{(u32) BPWR_GP_TIMER6, SERVICESCLK_GPT6_FCK, SERVICESCLK_GPT6_ICK},
-	{(u32) BPWR_GP_TIMER7, SERVICESCLK_GPT7_FCK, SERVICESCLK_GPT7_ICK},
-	{(u32) BPWR_GP_TIMER8, SERVICESCLK_GPT8_FCK, SERVICESCLK_GPT8_ICK},
-	{(u32) BPWR_WD_TIMER3, SERVICESCLK_WDT3_FCK, SERVICESCLK_WDT3_ICK},
-	{(u32) BPWR_MCBSP1, SERVICESCLK_MCBSP1_FCK, SERVICESCLK_MCBSP1_ICK},
-	{(u32) BPWR_MCBSP2, SERVICESCLK_MCBSP2_FCK, SERVICESCLK_MCBSP2_ICK},
-	{(u32) BPWR_MCBSP3, SERVICESCLK_MCBSP3_FCK, SERVICESCLK_MCBSP3_ICK},
-	{(u32) BPWR_MCBSP4, SERVICESCLK_MCBSP4_FCK, SERVICESCLK_MCBSP4_ICK},
-	{(u32) BPWR_MCBSP5, SERVICESCLK_MCBSP5_FCK, SERVICESCLK_MCBSP5_ICK},
-	{(u32) BPWR_SSI, SERVICESCLK_SSI_FCK, SERVICESCLK_SSI_ICK}
+	{(u32) BPWR_GP_TIMER5, DSP_CLK_GPT5_FCK, DSP_CLK_GPT5_ICK},
+	{(u32) BPWR_GP_TIMER6, DSP_CLK_GPT6_FCK, DSP_CLK_GPT6_ICK},
+	{(u32) BPWR_GP_TIMER7, DSP_CLK_GPT7_FCK, DSP_CLK_GPT7_ICK},
+	{(u32) BPWR_GP_TIMER8, DSP_CLK_GPT8_FCK, DSP_CLK_GPT8_ICK},
+	{(u32) BPWR_WD_TIMER3, DSP_CLK_WDT3_FCK, DSP_CLK_WDT3_ICK},
+	{(u32) BPWR_MCBSP1, DSP_CLK_MCBSP1_FCK, DSP_CLK_MCBSP1_ICK},
+	{(u32) BPWR_MCBSP2, DSP_CLK_MCBSP2_FCK, DSP_CLK_MCBSP2_ICK},
+	{(u32) BPWR_MCBSP3, DSP_CLK_MCBSP3_FCK, DSP_CLK_MCBSP3_ICK},
+	{(u32) BPWR_MCBSP4, DSP_CLK_MCBSP4_FCK, DSP_CLK_MCBSP4_ICK},
+	{(u32) BPWR_MCBSP5, DSP_CLK_MCBSP5_FCK, DSP_CLK_MCBSP5_ICK},
+	{(u32) BPWR_SSI, DSP_CLK_SSI_FCK, DSP_CLK_SSI_ICK}
 };
 
 /* Interrupt Register Offsets */
diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c
index a69f663..896941c 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430.c
@@ -305,7 +305,7 @@ static dsp_status bridge_brd_monitor(struct wmd_dev_context *hDevContext)
 	}
 	(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2, 0,
 					OMAP3430_IVA2_MOD, RM_RSTCTRL);
-	services_clk_enable(SERVICESCLK_IVA2_CK);
+	dsp_clk_enable(DSP_CLK_IVA2_CK);
 
 	if (DSP_SUCCEEDED(status)) {
 		/* set the device state to IDLE */
@@ -607,7 +607,7 @@ static dsp_status bridge_brd_start(struct wmd_dev_context *hDevContext,
 
 		if ((unsigned int *)ul_dsp_clk_addr != NULL) {
 			/* Get the clock rate */
-			status = services_clk_get_rate(SERVICESCLK_IVA2_CK,
+			status = dsp_clk_get_rate(DSP_CLK_IVA2_CK,
 						       &ul_dsp_clk_rate);
 			dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
 				__func__, ul_dsp_clk_rate);
@@ -727,7 +727,7 @@ static dsp_status bridge_brd_stop(struct wmd_dev_context *hDevContext)
 		sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
 		mdelay(10);
 
-		clk_status = services_clk_disable(SERVICESCLK_IVA2_CK);
+		clk_status = dsp_clk_disable(DSP_CLK_IVA2_CK);
 
 		/* IVA2 is not in OFF state */
 		/* Set PM_PWSTCTRL_IVA2  to OFF */
@@ -737,7 +737,7 @@ static dsp_status bridge_brd_stop(struct wmd_dev_context *hDevContext)
 		(*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
 					OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
 	} else {
-		clk_status = services_clk_disable(SERVICESCLK_IVA2_CK);
+		clk_status = dsp_clk_disable(DSP_CLK_IVA2_CK);
 	}
 	udelay(10);
 	/* Release the Ext Base virtual Address as the next DSP Program
@@ -795,7 +795,7 @@ static dsp_status wmd_brd_delete(struct wmd_dev_context *hDevContext)
 	 * to ensure that there are no pending L3 or other transactons from
 	 * IVA2 */
 	status = sleep_dsp(dev_context, PWR_EMERGENCYDEEPSLEEP, NULL);
-	clk_status = services_clk_disable(SERVICESCLK_IVA2_CK);
+	clk_status = dsp_clk_disable(DSP_CLK_IVA2_CK);
 
 	/* Release the Ext Base virtual Address as the next DSP Program
 	 * may have a different load address */
diff --git a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
index 87ec8d2..2e08746 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
@@ -319,8 +319,8 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 	switch (ext_clk_cmd) {
 	case BPWR_DISABLE_CLOCK:
 		/* Call BP to disable the needed clock */
-		status1 = services_clk_disable(bpwr_clks[clk_id_index].int_clk);
-		status = services_clk_disable(bpwr_clks[clk_id_index].fun_clk);
+		status1 = dsp_clk_disable(bpwr_clks[clk_id_index].int_clk);
+		status = dsp_clk_disable(bpwr_clks[clk_id_index].fun_clk);
 		if (bpwr_clkid[clk_id_index] == BPWR_MCBSP1) {
 			/* clear MCBSP1_CLKS, on McBSP1 OFF */
 			value = __raw_readl(
@@ -344,8 +344,8 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 		}
 		break;
 	case BPWR_ENABLE_CLOCK:
-		status1 = services_clk_enable(bpwr_clks[clk_id_index].int_clk);
-		status = services_clk_enable(bpwr_clks[clk_id_index].fun_clk);
+		status1 = dsp_clk_enable(bpwr_clks[clk_id_index].int_clk);
+		status = dsp_clk_enable(bpwr_clks[clk_id_index].fun_clk);
 		if (bpwr_clkid[clk_id_index] == BPWR_MCBSP1) {
 			/* set MCBSP1_CLKS, on McBSP1 ON */
 			value = __raw_readl(
@@ -469,7 +469,7 @@ dsp_status dsp_peripheral_clocks_disable(struct wmd_dev_context *dev_context,
 		if (((dev_context->dsp_per_clks) >> clk_idx) & 0x01) {
 			/* Disables the interface clock of the peripheral */
 			status =
-			    services_clk_disable(bpwr_clks[clk_idx].int_clk);
+			    dsp_clk_disable(bpwr_clks[clk_idx].int_clk);
 			if (bpwr_clkid[clk_idx] == BPWR_MCBSP1) {
 				/* clear MCBSP1_CLKS, on McBSP1 OFF */
 				value = __raw_readl(resources->dw_sys_ctrl_base
@@ -488,7 +488,7 @@ dsp_status dsp_peripheral_clocks_disable(struct wmd_dev_context *dev_context,
 
 			/* Disables the functional clock of the periphearl */
 			status =
-			    services_clk_disable(bpwr_clks[clk_idx].fun_clk);
+			    dsp_clk_disable(bpwr_clks[clk_idx].fun_clk);
 		}
 	}
 	return status;
@@ -513,7 +513,7 @@ dsp_status dsp_peripheral_clocks_enable(struct wmd_dev_context *dev_context,
 		if (((dev_context->dsp_per_clks) >> clk_idx) & 0x01) {
 			/* Enable the interface clock of the peripheral */
 			int_clk_status =
-			    services_clk_enable(bpwr_clks[clk_idx].int_clk);
+			    dsp_clk_enable(bpwr_clks[clk_idx].int_clk);
 			if (bpwr_clkid[clk_idx] == BPWR_MCBSP1) {
 				/* set MCBSP1_CLKS, on McBSP1 ON */
 				value = __raw_readl(resources->dw_sys_ctrl_base
@@ -531,7 +531,7 @@ dsp_status dsp_peripheral_clocks_enable(struct wmd_dev_context *dev_context,
 			}
 			/* Enable the functional clock of the periphearl */
 			fun_clk_status =
-			    services_clk_enable(bpwr_clks[clk_idx].fun_clk);
+			    dsp_clk_enable(bpwr_clks[clk_idx].fun_clk);
 		}
 	}
 	if ((int_clk_status | fun_clk_status) != DSP_SOK)
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: remove unused clock sys_ck

[Omar Ramirez Luna]

Remove unused clock sys_ck

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 arch/arm/plat-omap/include/dspbridge/clk.h |    1 -
 drivers/dsp/bridge/services/clk.c          |    1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-omap/include/dspbridge/clk.h b/arch/arm/plat-omap/include/dspbridge/clk.h
index a547225..2a43aab 100644
--- a/arch/arm/plat-omap/include/dspbridge/clk.h
+++ b/arch/arm/plat-omap/include/dspbridge/clk.h
@@ -46,7 +46,6 @@ enum dsp_clk_id {
 	DSP_CLK_SSI_FCK,
 	DSP_CLK_SSI_ICK,
 	DSP_CLK_SYS32K_CK,
-	DSP_CLK_SYS_CK,
 	DSP_CLK_NOT_DEFINED
 };
 
diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index 4101c38..23d4346 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -76,7 +76,6 @@ static struct dsp_clk_t dsp_clks[] = {
 	{NULL, "ssi_ssr_sst_fck", -1},
 	{NULL, "ssi_ick", -1},
 	{NULL, "omap_32k_fck", -1},
-	{NULL, "sys_ck", -1},
 	{NULL, ""}
 };
 
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: remove function clk_set32k_hz

[Omar Ramirez Luna]

This is only used for GPTs and should be addressed once
those clocks are requested using DM timer framework.

This patch might break functionality.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 arch/arm/plat-omap/include/dspbridge/clk.h |   14 +-------------
 drivers/dsp/bridge/services/clk.c          |   26 --------------------------
 drivers/dsp/bridge/wmd/tiomap3430.c        |   15 ---------------
 3 files changed, 1 insertions(+), 54 deletions(-)

diff --git a/arch/arm/plat-omap/include/dspbridge/clk.h b/arch/arm/plat-omap/include/dspbridge/clk.h
index 2a43aab..5f7a925 100644
--- a/arch/arm/plat-omap/include/dspbridge/clk.h
+++ b/arch/arm/plat-omap/include/dspbridge/clk.h
@@ -45,7 +45,6 @@ enum dsp_clk_id {
 	DSP_CLK_MCBSP5_ICK,
 	DSP_CLK_SSI_FCK,
 	DSP_CLK_SSI_ICK,
-	DSP_CLK_SYS32K_CK,
 	DSP_CLK_NOT_DEFINED
 };
 
@@ -115,18 +114,7 @@ extern dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id);
  */
 extern dsp_status dsp_clk_get_rate(IN enum dsp_clk_id clk_id,
 					u32 *speedMhz);
-/*
- *  ======== clk_set32k_hz ========
- *  Purpose:
- *      Set the requested clock to 32KHz.
- *  Parameters:
- *  Returns:
- *      DSP_SOK:        Success.
- *      -EPERM:      Error occured while setting the clock parent to 32KHz.
- *  Requires:
- *  Ensures:
- */
-extern dsp_status clk_set32k_hz(IN enum dsp_clk_id clk_id);
+
 extern void ssi_clk_prepare(bool FLAG);
 
 /*
diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index 23d4346..b4f5709 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -75,7 +75,6 @@ static struct dsp_clk_t dsp_clks[] = {
 	{NULL, "mcbsp_ick", 5},
 	{NULL, "ssi_ssr_sst_fck", -1},
 	{NULL, "ssi_ick", -1},
-	{NULL, "omap_32k_fck", -1},
 	{NULL, ""}
 };
 
@@ -171,31 +170,6 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 }
 
 /*
- *  ======== clk_set32k_hz ========
- *  Purpose:
- *      To Set parent of a clock to 32KHz.
- */
-
-dsp_status clk_set32k_hz(IN enum dsp_clk_id clk_id)
-{
-	dsp_status status = DSP_SOK;
-	struct clk *clk_handle;
-	struct clk *clk_parent;
-	clk_parent = dsp_clks[DSP_CLK_SYS32K_CK].clk_handle;
-
-	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
-
-	clk_handle = dsp_clks[clk_id].clk_handle;
-	if (!(clk_set_parent(clk_handle, clk_parent) == 0x0)) {
-		pr_err("%s: failed for %s, dev id = %d\n", __func__,
-		       dsp_clks[clk_id].clk_name,
-		       dsp_clks[clk_id].id);
-		status = -EPERM;
-	}
-	return status;
-}
-
-/*
  *  ======== dsp_clk_disable ========
  *  Purpose:
  *      Disable the clock.
diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c
index 896941c..52ec3bc 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430.c
@@ -543,13 +543,6 @@ static dsp_status bridge_brd_start(struct wmd_dev_context *hDevContext,
 				}
 			}
 
-			if (clk_id_index < MBX_PM_MAX_RESOURCES) {
-				status =
-				    clk_set32k_hz(bpwr_clks
-						  [clk_id_index].fun_clk);
-			} else {
-				status = -EPERM;
-			}
 			clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 			    ul_load_monitor_timer;
 
@@ -578,14 +571,6 @@ static dsp_status bridge_brd_start(struct wmd_dev_context *hDevContext,
 				}
 			}
 
-			if (clk_id_index < MBX_PM_MAX_RESOURCES) {
-				status =
-				    clk_set32k_hz(bpwr_clks
-						  [clk_id_index].fun_clk);
-			} else {
-				status = -EPERM;
-			}
-
 			clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 			    ul_bios_gp_timer;
 
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: remove clk_get_use_cnt

[Omar Ramirez Luna]

Instead of querying the use count, balanced number of
enable/disable should be enforced across the system.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 arch/arm/plat-omap/include/dspbridge/clk.h |   13 -------------
 drivers/dsp/bridge/services/clk.c          |   23 -----------------------
 2 files changed, 0 insertions(+), 36 deletions(-)

diff --git a/arch/arm/plat-omap/include/dspbridge/clk.h b/arch/arm/plat-omap/include/dspbridge/clk.h
index 5f7a925..621d08f 100644
--- a/arch/arm/plat-omap/include/dspbridge/clk.h
+++ b/arch/arm/plat-omap/include/dspbridge/clk.h
@@ -117,17 +117,4 @@ extern dsp_status dsp_clk_get_rate(IN enum dsp_clk_id clk_id,
 
 extern void ssi_clk_prepare(bool FLAG);
 
-/*
- *  ======== CLK_Get_RefCnt ========
- *  Purpose:
- *      get the reference count for the clock.
- *  Parameters:
- *  Returns:
- *      s32:        Reference Count for the clock.
- *      -EPERM:  Error occured while getting the reference count of a clock.
- *  Requires:
- *  Ensures:
- */
-extern s32 clk_get_use_cnt(IN enum dsp_clk_id clk_id);
-
 #endif /* _SYNC_H */
diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index b4f5709..e447d54 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -179,20 +179,11 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 {
 	dsp_status status = DSP_SOK;
 	struct clk *clk_handle;
-	s32 clk_use_cnt;
 
 	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
 
 	clk_handle = dsp_clks[clk_id].clk_handle;
 
-	clk_use_cnt = clk_get_use_cnt(clk_id);
-	if (clk_use_cnt == -1) {
-		pr_err("%s: failed to get CLK Use count for CLK %s, CLK dev id"
-		       " = %d\n", __func__, dsp_clks[clk_id].clk_name,
-		       dsp_clks[clk_id].id);
-	} else if (clk_use_cnt == 0) {
-		return status;
-	}
 	if (clk_id == DSP_CLK_SSI_ICK)
 		ssi_clk_prepare(false);
 
@@ -226,20 +217,6 @@ dsp_status dsp_clk_get_rate(IN enum dsp_clk_id clk_id, u32 *speedKhz)
 	return status;
 }
 
-s32 clk_get_use_cnt(IN enum dsp_clk_id clk_id)
-{
-	struct clk *clk_handle;
-	s32 use_count = -1;
-	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
-
-	clk_handle = dsp_clks[clk_id].clk_handle;
-
-	/* FIXME: usecount shouldn't be used */
-	use_count = clk_handle->usecount;
-
-	return use_count;
-}
-
 void ssi_clk_prepare(bool FLAG)
 {
 	void __iomem *ssi_base;
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: trivial clock cleanup for unused code

[Omar Ramirez Luna]

Remove unusued struct and typedef.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 arch/arm/plat-omap/include/dspbridge/clk.h |    2 --
 drivers/dsp/bridge/services/clk.c          |    7 -------
 2 files changed, 0 insertions(+), 9 deletions(-)

diff --git a/arch/arm/plat-omap/include/dspbridge/clk.h b/arch/arm/plat-omap/include/dspbridge/clk.h
index 621d08f..f19d024 100644
--- a/arch/arm/plat-omap/include/dspbridge/clk.h
+++ b/arch/arm/plat-omap/include/dspbridge/clk.h
@@ -19,8 +19,6 @@
 #ifndef _CLK_H
 #define _CLK_H
 
-	/* Generic TIMER object: */
-struct timer_object;
 enum dsp_clk_id {
 	DSP_CLK_IVA2_CK = 0,
 	DSP_CLK_GPT5_FCK,
diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index e447d54..e35b929 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -32,8 +32,6 @@
 
 /*  ----------------------------------- Defines, Data Structures, Typedefs */
 
-typedef volatile unsigned long reg_uword32;
-
 #define OMAP_SSI_OFFSET			0x58000
 #define OMAP_SSI_SIZE			0x1000
 #define OMAP_SSI_SYSCONFIG_OFFSET	0x10
@@ -78,11 +76,6 @@ static struct dsp_clk_t dsp_clks[] = {
 	{NULL, ""}
 };
 
-/* Generic TIMER object: */
-struct timer_object {
-	struct timer_list timer;
-};
-
 /*
  *  ======== dsp_clk_exit ========
  *  Purpose:
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: function to get the type of clock requested by dsp

[Omar Ramirez Luna]

DSP can request between 5 types of clocks: IVA2, GPT (5-8), WDT (3),
MCBSP (1-5) or SSI clock. This function will be useful in case
a specific clock framework is associated with the clock.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/services/clk.c |   89 ++++++++++++++++++++++++++++---------
 1 files changed, 68 insertions(+), 21 deletions(-)

diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index e35b929..d5c3d4e 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -40,6 +40,13 @@
 #define SSI_SIDLE_SMARTIDLE		(2 << 3)
 #define SSI_MIDLE_NOIDLE		(1 << 12)
 
+/* Clk types requested by the dsp */
+#define IVA2_CLK	0
+#define GPT_CLK		1
+#define WDT_CLK		2
+#define MCBSP_CLK	3
+#define SSI_CLK		4
+
 struct dsp_clk_t {
 	struct clk *clk_handle;
 	const char *clk_name;
@@ -76,6 +83,26 @@ static struct dsp_clk_t dsp_clks[] = {
 	{NULL, ""}
 };
 
+static s8 get_clk_type(u8 id)
+{
+	s8 type;
+
+	if (id == DSP_CLK_IVA2_CK)
+		type = IVA2_CLK;
+	else if (id <= DSP_CLK_GPT8_ICK)
+		type = GPT_CLK;
+	else if (id <= DSP_CLK_WDT3_ICK)
+		type = WDT_CLK;
+	else if (id <= DSP_CLK_MCBSP5_ICK)
+		type = MCBSP_CLK;
+	else if (id < DSP_CLK_SSI_ICK)
+		type = SSI_CLK;
+	else
+		type = -1;
+
+	return type;
+}
+
 /*
  *  ======== dsp_clk_exit ========
  *  Purpose:
@@ -141,23 +168,33 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 	dsp_status status = DSP_SOK;
 	struct clk *clk_handle;
 
-	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
+	switch (get_clk_type(clk_id)) {
+	case IVA2_CLK:
+	case GPT_CLK:
+	case MCBSP_CLK:
+	case WDT_CLK:
+	case SSI_CLK:
+		clk_handle = dsp_clks[clk_id].clk_handle;
+		if (clk_enable(clk_handle)) {
+			pr_err("dsp_clk_enable: failed to Enable CLK %s, "
+				"CLK dev id = %d\n", dsp_clks[clk_id].clk_name,
+				dsp_clks[clk_id].id);
+			status = -EPERM;
+		}
 
-	clk_handle = dsp_clks[clk_id].clk_handle;
-	if (clk_enable(clk_handle)) {
-		pr_err("dsp_clk_enable: failed to Enable CLK %s, "
-		       "CLK dev id = %d\n",
-		       dsp_clks[clk_id].clk_name,
-		       dsp_clks[clk_id].id);
-		status = -EPERM;
+		/*
+		 * The SSI module need to configured not to have the Forced
+		 * idle for master interface. If it is set to forced idle,
+		 * the SSI module is transitioning to standby thereby causing
+		 * the client in the DSP hang waiting for the SSI module to
+		 * be active after enabling the clocks
+		 */
+		if (clk_id == DSP_CLK_SSI_ICK)
+			ssi_clk_prepare(true);
+		break;
+	default:
+		dev_err(bridge, "Invalid clock id for enable\n");
 	}
-	/* The SSI module need to configured not to have the Forced idle for
-	 * master interface. If it is set to forced idle, the SSI module is
-	 * transitioning to standby thereby causing the client in the DSP hang
-	 * waiting for the SSI module to be active after enabling the clocks
-	 */
-	if (clk_id == DSP_CLK_SSI_FCK)
-		ssi_clk_prepare(true);
 
 	return status;
 }
@@ -175,12 +212,22 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 
 	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
 
-	clk_handle = dsp_clks[clk_id].clk_handle;
-
-	if (clk_id == DSP_CLK_SSI_ICK)
-		ssi_clk_prepare(false);
-
-	clk_disable(clk_handle);
+	switch (get_clk_type(clk_id)) {
+	case IVA2_CLK:
+	case GPT_CLK:
+	case MCBSP_CLK:
+	case WDT_CLK:
+	case SSI_CLK:
+		clk_handle = dsp_clks[clk_id].clk_handle;
+
+		if (clk_id == DSP_CLK_SSI_ICK)
+			ssi_clk_prepare(false);
+
+		clk_disable(clk_handle);
+		break;
+	default:
+		dev_err(bridge, "Invalid clock id for disable\n");
+	}
 
 	return status;
 }
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: iva2 clock handling

[Omar Ramirez Luna]

Change the way iva2 clock is handled and since the rate is needed
for this clock only, make the function get_rate to be specific for
iva clock.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 arch/arm/plat-omap/include/dspbridge/clk.h |   16 +------
 drivers/dsp/bridge/services/clk.c          |   71 +++++++---------------------
 drivers/dsp/bridge/services/services.c     |    9 +---
 drivers/dsp/bridge/wmd/tiomap3430.c        |    3 +-
 4 files changed, 22 insertions(+), 77 deletions(-)

diff --git a/arch/arm/plat-omap/include/dspbridge/clk.h b/arch/arm/plat-omap/include/dspbridge/clk.h
index f19d024..2602d9f 100644
--- a/arch/arm/plat-omap/include/dspbridge/clk.h
+++ b/arch/arm/plat-omap/include/dspbridge/clk.h
@@ -71,7 +71,7 @@ extern void dsp_clk_exit(void);
  *  Ensures:
  *      CLK initialized.
  */
-extern bool dsp_clk_init(void);
+extern void dsp_clk_init(void);
 
 /*
  *  ======== dsp_clk_enable ========
@@ -99,19 +99,7 @@ extern dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id);
  */
 extern dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id);
 
-/*
- *  ======== dsp_clk_get_rate ========
- *  Purpose:
- *      Get the clock rate of requested clock.
- *  Parameters:
- *  Returns:
- *      DSP_SOK:        Success.
- *      -EPERM:      Error occured while Getting the clock rate.
- *  Requires:
- *  Ensures:
- */
-extern dsp_status dsp_clk_get_rate(IN enum dsp_clk_id clk_id,
-					u32 *speedMhz);
+extern u32 dsp_clk_get_iva2_rate(void);
 
 extern void ssi_clk_prepare(bool FLAG);
 
diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index d5c3d4e..9c994d3 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -57,7 +57,6 @@ struct dsp_clk_t {
  * 'dsp_clk_id' provided in the header file.. any changes in the
  * enumerations needs to be fixed in the array as well */
 static struct dsp_clk_t dsp_clks[] = {
-	{NULL, "iva2_ck", -1},
 	{NULL, "gpt5_fck", -1},
 	{NULL, "gpt5_ick", -1},
 	{NULL, "gpt6_fck", -1},
@@ -83,6 +82,8 @@ static struct dsp_clk_t dsp_clks[] = {
 	{NULL, ""}
 };
 
+struct clk *iva2_clk;
+
 static s8 get_clk_type(u8 id)
 {
 	s8 type;
@@ -110,17 +111,7 @@ static s8 get_clk_type(u8 id)
  */
 void dsp_clk_exit(void)
 {
-	int i = 0;
-
-	/* Relinquish the clock handles */
-	while (i < DSP_CLK_NOT_DEFINED) {
-		if (dsp_clks[i].clk_handle)
-			clk_put(dsp_clks[i].clk_handle);
-
-		dsp_clks[i].clk_handle = NULL;
-		i++;
-	}
-
+	clk_put(iva2_clk);
 }
 
 /*
@@ -128,33 +119,15 @@ void dsp_clk_exit(void)
  *  Purpose:
  *      Initialize CLK module.
  */
-bool dsp_clk_init(void)
+void dsp_clk_init(void)
 {
 	static struct platform_device dspbridge_device;
-	struct clk *clk_handle;
-	int i = 0;
 
 	dspbridge_device.dev.bus = &platform_bus_type;
 
-	/* Get the clock handles from base port and store locally */
-	while (i < DSP_CLK_NOT_DEFINED) {
-		/* get the handle from BP */
-		dspbridge_device.id = dsp_clks[i].id;
-
-		clk_handle = clk_get(&dspbridge_device.dev,
-				     dsp_clks[i].clk_name);
-
-		if (IS_ERR(clk_handle)) {
-			pr_err("%s: failed to get clk handle %s, dev id = %d\n",
-			       __func__, dsp_clks[i].clk_name,
-			       dsp_clks[i].id);
-			return false;
-		}
-		dsp_clks[i].clk_handle = clk_handle;
-		i++;
-	}
-
-	return true;
+	iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
+	if (IS_ERR(iva2_clk))
+		dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
 }
 
 /*
@@ -170,6 +143,8 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 
 	switch (get_clk_type(clk_id)) {
 	case IVA2_CLK:
+		clk_enable(iva2_clk);
+		break;
 	case GPT_CLK:
 	case MCBSP_CLK:
 	case WDT_CLK:
@@ -214,6 +189,8 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 
 	switch (get_clk_type(clk_id)) {
 	case IVA2_CLK:
+		clk_disable(iva2_clk);
+		break;
 	case GPT_CLK:
 	case MCBSP_CLK:
 	case WDT_CLK:
@@ -232,29 +209,15 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 	return status;
 }
 
-/*
- *  ======== dsp_clk_get_rate ========
- *  Purpose:
- *      GetClock Speed.
- *
- */
-
-dsp_status dsp_clk_get_rate(IN enum dsp_clk_id clk_id, u32 *speedKhz)
+u32 dsp_clk_get_iva2_rate(void)
 {
-	dsp_status status = DSP_SOK;
-	struct clk *clk_handle;
-	u32 clk_speed_hz;
+	u32 clk_speed_khz;
 
-	DBC_REQUIRE(clk_id < SERVICESCLK_NOT_DEFINED);
-	*speedKhz = 0x0;
+	clk_speed_khz = clk_get_rate(iva2_clk);
+	clk_speed_khz /= 1000;
+	dev_dbg(bridge, "%s: clk speed Khz = %d\n", __func__, clk_speed_khz);
 
-	clk_handle = dsp_clks[clk_id].clk_handle;
-	clk_speed_hz = clk_get_rate(clk_handle);
-	*speedKhz = clk_speed_hz / 1000;
-	dev_dbg(bridge, "%s: clk_speed_hz = %d, speedinKhz = %d\n",
-			__func__, clk_speed_hz, *speedKhz);
-
-	return status;
+	return clk_speed_khz;
 }
 
 void ssi_clk_prepare(bool FLAG)
diff --git a/drivers/dsp/bridge/services/services.c b/drivers/dsp/bridge/services/services.c
index afb01be..cc2e89d 100644
--- a/drivers/dsp/bridge/services/services.c
+++ b/drivers/dsp/bridge/services/services.c
@@ -56,19 +56,14 @@ bool services_init(void)
 {
 	bool ret = true;
 	bool fcfg;
-	bool fclk;
 
 	/* Perform required initialization of SERVICES modules. */
 	fcfg = cfg_init();
-	fclk = dsp_clk_init();
+	dsp_clk_init();
 
-	ret = fcfg && fclk;
+	ret = fcfg;
 
 	if (!ret) {
-
-		if (fclk)
-			dsp_clk_exit();
-
 		if (fcfg)
 			cfg_exit();
 	}
diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c
index 52ec3bc..bb78df2 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430.c
@@ -592,8 +592,7 @@ static dsp_status bridge_brd_start(struct wmd_dev_context *hDevContext,
 
 		if ((unsigned int *)ul_dsp_clk_addr != NULL) {
 			/* Get the clock rate */
-			status = dsp_clk_get_rate(DSP_CLK_IVA2_CK,
-						       &ul_dsp_clk_rate);
+			ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
 			dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
 				__func__, ul_dsp_clk_rate);
 			(void)bridge_brd_write(dev_context,
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Omar Ramirez Luna]

This patch switches to use DM timer framework instead of
a custom one for GPT timers, currently dsp can make use of
gpt 5, 6, 7 or 8.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@hotmail.com>
---
 drivers/dsp/bridge/services/clk.c   |   25 ++++++++++++-----------
 drivers/dsp/bridge/wmd/tiomap3430.c |   36 -----------------------------------
 2 files changed, 13 insertions(+), 48 deletions(-)

diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index 9c994d3..37739a9 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -18,6 +18,7 @@
 
 /*  ----------------------------------- Host OS */
 #include <dspbridge/host_os.h>
+#include <plat/dmtimer.h>
 
 /*  ----------------------------------- DSP/BIOS Bridge */
 #include <dspbridge/std.h>
@@ -47,24 +48,21 @@
 #define MCBSP_CLK	3
 #define SSI_CLK		4
 
+/*
+ * Bridge specific DM Timer macro.
+ * Bridge GPT id (1 - 4), DM Timer id (5 - 8)
+ */
+#define DMT_ID(id) ((id) + 4)
+
 struct dsp_clk_t {
 	struct clk *clk_handle;
 	const char *clk_name;
 	int id;
 };
 
-/* The row order of the below array needs to match with the clock enumerations
- * 'dsp_clk_id' provided in the header file.. any changes in the
- * enumerations needs to be fixed in the array as well */
+static struct omap_dm_timer *timer[4];
+
 static struct dsp_clk_t dsp_clks[] = {
-	{NULL, "gpt5_fck", -1},
-	{NULL, "gpt5_ick", -1},
-	{NULL, "gpt6_fck", -1},
-	{NULL, "gpt6_ick", -1},
-	{NULL, "gpt7_fck", -1},
-	{NULL, "gpt7_ick", -1},
-	{NULL, "gpt8_fck", -1},
-	{NULL, "gpt8_ick", -1},
 	{NULL, "wdt_fck", 3},
 	{NULL, "wdt_ick", 3},
 	{NULL, "mcbsp_fck", 1},
@@ -79,7 +77,6 @@ static struct dsp_clk_t dsp_clks[] = {
 	{NULL, "mcbsp_ick", 5},
 	{NULL, "ssi_ssr_sst_fck", -1},
 	{NULL, "ssi_ick", -1},
-	{NULL, ""}
 };
 
 struct clk *iva2_clk;
@@ -146,6 +143,8 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 		clk_enable(iva2_clk);
 		break;
 	case GPT_CLK:
+		timer[clk_id] = omap_dm_timer_request_specific(DMT_ID(clk_id));
+		break;
 	case MCBSP_CLK:
 	case WDT_CLK:
 	case SSI_CLK:
@@ -192,6 +191,8 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 		clk_disable(iva2_clk);
 		break;
 	case GPT_CLK:
+		omap_dm_timer_free(timer[clk_id]);
+		break;
 	case MCBSP_CLK:
 	case WDT_CLK:
 	case SSI_CLK:
diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c
index bb78df2..38338d1 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430.c
@@ -392,9 +392,6 @@ static dsp_status bridge_brd_start(struct wmd_dev_context *hDevContext,
 	u32 clk_cmd;
 	struct io_mgr *hio_mgr;
 	u32 ul_load_monitor_timer;
-	u32 ext_clk_id = 0;
-	u32 tmp_index;
-	u32 clk_id_index = MBX_PM_MAX_RESOURCES;
 	struct dspbridge_platform_data *pdata =
 				omap_dspbridge_dev->dev.platform_data;
 
@@ -529,25 +526,9 @@ static dsp_status bridge_brd_start(struct wmd_dev_context *hDevContext,
 
 	if (DSP_SUCCEEDED(status)) {
 		if (ul_load_monitor_timer != 0xFFFF) {
-			clk_cmd = (BPWR_DISABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
-			    ul_load_monitor_timer;
-
-			dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
-
-			ext_clk_id = clk_cmd & MBX_PM_CLK_IDMASK;
-			for (tmp_index = 0; tmp_index < MBX_PM_MAX_RESOURCES;
-			     tmp_index++) {
-				if (ext_clk_id == bpwr_clkid[tmp_index]) {
-					clk_id_index = tmp_index;
-					break;
-				}
-			}
-
 			clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 			    ul_load_monitor_timer;
-
 			dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
-
 		} else {
 			dev_dbg(bridge, "Not able to get the symbol for Load "
 				"Monitor Timer\n");
@@ -556,26 +537,9 @@ static dsp_status bridge_brd_start(struct wmd_dev_context *hDevContext,
 
 	if (DSP_SUCCEEDED(status)) {
 		if (ul_bios_gp_timer != 0xFFFF) {
-			clk_cmd = (BPWR_DISABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
-			    ul_bios_gp_timer;
-
-			dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
-
-			ext_clk_id = clk_cmd & MBX_PM_CLK_IDMASK;
-
-			for (tmp_index = 0; tmp_index < MBX_PM_MAX_RESOURCES;
-			     tmp_index++) {
-				if (ext_clk_id == bpwr_clkid[tmp_index]) {
-					clk_id_index = tmp_index;
-					break;
-				}
-			}
-
 			clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
 			    ul_bios_gp_timer;
-
 			dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
-
 		} else {
 			dev_dbg(bridge,
 				"Not able to get the symbol for BIOS Timer\n");
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: use omap mcbsp to enable mcbsp clocks

[Omar Ramirez Luna]

Use omap mcbsp to enable mcbsp clocks

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/services/clk.c |   24 ++++++++++--------------
 1 files changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index 37739a9..2e3c64d 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -19,6 +19,7 @@
 /*  ----------------------------------- Host OS */
 #include <dspbridge/host_os.h>
 #include <plat/dmtimer.h>
+#include <plat/mcbsp.h>
 
 /*  ----------------------------------- DSP/BIOS Bridge */
 #include <dspbridge/std.h>
@@ -48,12 +49,12 @@
 #define MCBSP_CLK	3
 #define SSI_CLK		4
 
-/*
- * Bridge specific DM Timer macro.
- * Bridge GPT id (1 - 4), DM Timer id (5 - 8)
- */
+/* Bridge GPT id (1 - 4), DM Timer id (5 - 8) */
 #define DMT_ID(id) ((id) + 4)
 
+/* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (1 - 5) */
+#define MCBSP_ID(id) ((id) - 13)
+
 struct dsp_clk_t {
 	struct clk *clk_handle;
 	const char *clk_name;
@@ -65,16 +66,6 @@ static struct omap_dm_timer *timer[4];
 static struct dsp_clk_t dsp_clks[] = {
 	{NULL, "wdt_fck", 3},
 	{NULL, "wdt_ick", 3},
-	{NULL, "mcbsp_fck", 1},
-	{NULL, "mcbsp_ick", 1},
-	{NULL, "mcbsp_fck", 2},
-	{NULL, "mcbsp_ick", 2},
-	{NULL, "mcbsp_fck", 3},
-	{NULL, "mcbsp_ick", 3},
-	{NULL, "mcbsp_fck", 4},
-	{NULL, "mcbsp_ick", 4},
-	{NULL, "mcbsp_fck", 5},
-	{NULL, "mcbsp_ick", 5},
 	{NULL, "ssi_ssr_sst_fck", -1},
 	{NULL, "ssi_ick", -1},
 };
@@ -146,6 +137,9 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 		timer[clk_id] = omap_dm_timer_request_specific(DMT_ID(clk_id));
 		break;
 	case MCBSP_CLK:
+		omap_mcbsp_set_io_type(MCBSP_ID(clk_id), OMAP_MCBSP_POLL_IO);
+		omap_mcbsp_request(MCBSP_ID(clk_id));
+		break;
 	case WDT_CLK:
 	case SSI_CLK:
 		clk_handle = dsp_clks[clk_id].clk_handle;
@@ -194,6 +188,8 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 		omap_dm_timer_free(timer[clk_id]);
 		break;
 	case MCBSP_CLK:
+		omap_mcbsp_free(MCBSP_ID(clk_id));
+		break;
 	case WDT_CLK:
 	case SSI_CLK:
 		clk_handle = dsp_clks[clk_id].clk_handle;
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: remove wdt3 from dsp control

[Omar Ramirez Luna]

WDT3 is used as a way to detect dsp hangs, as of now its
control is left to arm side driver, so, no requests should
be received by the dsp to enable/disable this clock.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/services/clk.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index 2e3c64d..ee85905 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -64,8 +64,6 @@ struct dsp_clk_t {
 static struct omap_dm_timer *timer[4];
 
 static struct dsp_clk_t dsp_clks[] = {
-	{NULL, "wdt_fck", 3},
-	{NULL, "wdt_ick", 3},
 	{NULL, "ssi_ssr_sst_fck", -1},
 	{NULL, "ssi_ick", -1},
 };
@@ -141,6 +139,8 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 		omap_mcbsp_request(MCBSP_ID(clk_id));
 		break;
 	case WDT_CLK:
+		dev_err(bridge, "ERROR: DSP requested to enable WDT3 clk\n");
+		break;
 	case SSI_CLK:
 		clk_handle = dsp_clks[clk_id].clk_handle;
 		if (clk_enable(clk_handle)) {
@@ -191,6 +191,8 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 		omap_mcbsp_free(MCBSP_ID(clk_id));
 		break;
 	case WDT_CLK:
+		dev_err(bridge, "ERROR: DSP requested to disable WDT3 clk\n");
+		break;
 	case SSI_CLK:
 		clk_handle = dsp_clks[clk_id].clk_handle;
 
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: dsp interface to enable ssi clocks

[Omar Ramirez Luna]

This patch fixes the wrong name for ssi clock,
now it has been split into ssr and sst for fck. It
handle ick/ssr_fck/sst_fck clocks with one call to
disable/enable.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/services/clk.c |   56 ++++++++++++++++++-------------------
 1 files changed, 27 insertions(+), 29 deletions(-)

diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index ee85905..c72f574 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -55,20 +55,17 @@
 /* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (1 - 5) */
 #define MCBSP_ID(id) ((id) - 13)
 
-struct dsp_clk_t {
-	struct clk *clk_handle;
-	const char *clk_name;
-	int id;
-};
-
 static struct omap_dm_timer *timer[4];
 
-static struct dsp_clk_t dsp_clks[] = {
-	{NULL, "ssi_ssr_sst_fck", -1},
-	{NULL, "ssi_ick", -1},
+struct clk *iva2_clk;
+
+struct dsp_ssi {
+	struct clk *sst_fck;
+	struct clk *ssr_fck;
+	struct clk *ick;
 };
 
-struct clk *iva2_clk;
+static struct dsp_ssi ssi;
 
 static s8 get_clk_type(u8 id)
 {
@@ -98,6 +95,9 @@ static s8 get_clk_type(u8 id)
 void dsp_clk_exit(void)
 {
 	clk_put(iva2_clk);
+	clk_put(ssi.sst_fck);
+	clk_put(ssi.ssr_fck);
+	clk_put(ssi.ick);
 }
 
 /*
@@ -114,6 +114,14 @@ void dsp_clk_init(void)
 	iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
 	if (IS_ERR(iva2_clk))
 		dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
+
+	ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck");
+	ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck");
+	ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick");
+
+	if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick))
+		dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n",
+					ssi.sst_fck, ssi.ssr_fck, ssi.ick);
 }
 
 /*
@@ -125,7 +133,6 @@ void dsp_clk_init(void)
 dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 {
 	dsp_status status = DSP_SOK;
-	struct clk *clk_handle;
 
 	switch (get_clk_type(clk_id)) {
 	case IVA2_CLK:
@@ -142,13 +149,9 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 		dev_err(bridge, "ERROR: DSP requested to enable WDT3 clk\n");
 		break;
 	case SSI_CLK:
-		clk_handle = dsp_clks[clk_id].clk_handle;
-		if (clk_enable(clk_handle)) {
-			pr_err("dsp_clk_enable: failed to Enable CLK %s, "
-				"CLK dev id = %d\n", dsp_clks[clk_id].clk_name,
-				dsp_clks[clk_id].id);
-			status = -EPERM;
-		}
+		clk_enable(ssi.sst_fck);
+		clk_enable(ssi.ssr_fck);
+		clk_enable(ssi.ick);
 
 		/*
 		 * The SSI module need to configured not to have the Forced
@@ -157,8 +160,7 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 		 * the client in the DSP hang waiting for the SSI module to
 		 * be active after enabling the clocks
 		 */
-		if (clk_id == DSP_CLK_SSI_ICK)
-			ssi_clk_prepare(true);
+		ssi_clk_prepare(true);
 		break;
 	default:
 		dev_err(bridge, "Invalid clock id for enable\n");
@@ -176,9 +178,6 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 {
 	dsp_status status = DSP_SOK;
-	struct clk *clk_handle;
-
-	DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED);
 
 	switch (get_clk_type(clk_id)) {
 	case IVA2_CLK:
@@ -194,12 +193,11 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 		dev_err(bridge, "ERROR: DSP requested to disable WDT3 clk\n");
 		break;
 	case SSI_CLK:
-		clk_handle = dsp_clks[clk_id].clk_handle;
-
-		if (clk_id == DSP_CLK_SSI_ICK)
-			ssi_clk_prepare(false);
-
-		clk_disable(clk_handle);
+		ssi_clk_prepare(false);
+		ssi_clk_prepare(false);
+		clk_disable(ssi.sst_fck);
+		clk_disable(ssi.ssr_fck);
+		clk_disable(ssi.ick);
 		break;
 	default:
 		dev_err(bridge, "Invalid clock id for disable\n");
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: use one call for both ick and fck clocks

[Omar Ramirez Luna]

Instead of two calls to enable/disable for ick and fck use
one call to enable/disable both.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 arch/arm/plat-omap/include/dspbridge/clk.h |   35 +++++++++------------------
 drivers/dsp/bridge/services/clk.c          |   14 +++++-----
 drivers/dsp/bridge/wmd/_tiomap.h           |   25 +++++++++----------
 drivers/dsp/bridge/wmd/tiomap3430.c        |    8 +++---
 drivers/dsp/bridge/wmd/tiomap3430_pwr.c    |   35 ++++++++--------------------
 5 files changed, 45 insertions(+), 72 deletions(-)

diff --git a/arch/arm/plat-omap/include/dspbridge/clk.h b/arch/arm/plat-omap/include/dspbridge/clk.h
index 2602d9f..e6b09c7 100644
--- a/arch/arm/plat-omap/include/dspbridge/clk.h
+++ b/arch/arm/plat-omap/include/dspbridge/clk.h
@@ -20,29 +20,18 @@
 #define _CLK_H
 
 enum dsp_clk_id {
-	DSP_CLK_IVA2_CK = 0,
-	DSP_CLK_GPT5_FCK,
-	DSP_CLK_GPT5_ICK,
-	DSP_CLK_GPT6_FCK,
-	DSP_CLK_GPT6_ICK,
-	DSP_CLK_GPT7_FCK,
-	DSP_CLK_GPT7_ICK,
-	DSP_CLK_GPT8_FCK,
-	DSP_CLK_GPT8_ICK,
-	DSP_CLK_WDT3_FCK,
-	DSP_CLK_WDT3_ICK,
-	DSP_CLK_MCBSP1_FCK,
-	DSP_CLK_MCBSP1_ICK,
-	DSP_CLK_MCBSP2_FCK,
-	DSP_CLK_MCBSP2_ICK,
-	DSP_CLK_MCBSP3_FCK,
-	DSP_CLK_MCBSP3_ICK,
-	DSP_CLK_MCBSP4_FCK,
-	DSP_CLK_MCBSP4_ICK,
-	DSP_CLK_MCBSP5_FCK,
-	DSP_CLK_MCBSP5_ICK,
-	DSP_CLK_SSI_FCK,
-	DSP_CLK_SSI_ICK,
+	DSP_CLK_IVA2 = 0,
+	DSP_CLK_GPT5,
+	DSP_CLK_GPT6,
+	DSP_CLK_GPT7,
+	DSP_CLK_GPT8,
+	DSP_CLK_WDT3,
+	DSP_CLK_MCBSP1,
+	DSP_CLK_MCBSP2,
+	DSP_CLK_MCBSP3,
+	DSP_CLK_MCBSP4,
+	DSP_CLK_MCBSP5,
+	DSP_CLK_SSI,
 	DSP_CLK_NOT_DEFINED
 };
 
diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index c72f574..9a439c7 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -52,8 +52,8 @@
 /* Bridge GPT id (1 - 4), DM Timer id (5 - 8) */
 #define DMT_ID(id) ((id) + 4)
 
-/* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (1 - 5) */
-#define MCBSP_ID(id) ((id) - 13)
+/* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (0 - 4) */
+#define MCBSP_ID(id) ((id) - 6)
 
 static struct omap_dm_timer *timer[4];
 
@@ -71,15 +71,15 @@ static s8 get_clk_type(u8 id)
 {
 	s8 type;
 
-	if (id == DSP_CLK_IVA2_CK)
+	if (id == DSP_CLK_IVA2)
 		type = IVA2_CLK;
-	else if (id <= DSP_CLK_GPT8_ICK)
+	else if (id <= DSP_CLK_GPT8)
 		type = GPT_CLK;
-	else if (id <= DSP_CLK_WDT3_ICK)
+	else if (id == DSP_CLK_WDT3)
 		type = WDT_CLK;
-	else if (id <= DSP_CLK_MCBSP5_ICK)
+	else if (id <= DSP_CLK_MCBSP5)
 		type = MCBSP_CLK;
-	else if (id < DSP_CLK_SSI_ICK)
+	else if (id == DSP_CLK_SSI)
 		type = SSI_CLK;
 	else
 		type = -1;
diff --git a/drivers/dsp/bridge/wmd/_tiomap.h b/drivers/dsp/bridge/wmd/_tiomap.h
index 887232b..56efb84 100644
--- a/drivers/dsp/bridge/wmd/_tiomap.h
+++ b/drivers/dsp/bridge/wmd/_tiomap.h
@@ -246,22 +246,21 @@ static const u32 bpwr_clkid[] = {
 
 struct bpwr_clk_t {
 	u32 clk_id;
-	enum dsp_clk_id fun_clk;
-	enum dsp_clk_id int_clk;
+	enum dsp_clk_id clk;
 };
 
 static const struct bpwr_clk_t bpwr_clks[] = {
-	{(u32) BPWR_GP_TIMER5, DSP_CLK_GPT5_FCK, DSP_CLK_GPT5_ICK},
-	{(u32) BPWR_GP_TIMER6, DSP_CLK_GPT6_FCK, DSP_CLK_GPT6_ICK},
-	{(u32) BPWR_GP_TIMER7, DSP_CLK_GPT7_FCK, DSP_CLK_GPT7_ICK},
-	{(u32) BPWR_GP_TIMER8, DSP_CLK_GPT8_FCK, DSP_CLK_GPT8_ICK},
-	{(u32) BPWR_WD_TIMER3, DSP_CLK_WDT3_FCK, DSP_CLK_WDT3_ICK},
-	{(u32) BPWR_MCBSP1, DSP_CLK_MCBSP1_FCK, DSP_CLK_MCBSP1_ICK},
-	{(u32) BPWR_MCBSP2, DSP_CLK_MCBSP2_FCK, DSP_CLK_MCBSP2_ICK},
-	{(u32) BPWR_MCBSP3, DSP_CLK_MCBSP3_FCK, DSP_CLK_MCBSP3_ICK},
-	{(u32) BPWR_MCBSP4, DSP_CLK_MCBSP4_FCK, DSP_CLK_MCBSP4_ICK},
-	{(u32) BPWR_MCBSP5, DSP_CLK_MCBSP5_FCK, DSP_CLK_MCBSP5_ICK},
-	{(u32) BPWR_SSI, DSP_CLK_SSI_FCK, DSP_CLK_SSI_ICK}
+	{(u32) BPWR_GP_TIMER5, DSP_CLK_GPT5},
+	{(u32) BPWR_GP_TIMER6, DSP_CLK_GPT6},
+	{(u32) BPWR_GP_TIMER7, DSP_CLK_GPT7},
+	{(u32) BPWR_GP_TIMER8, DSP_CLK_GPT8},
+	{(u32) BPWR_WD_TIMER3, DSP_CLK_WDT3},
+	{(u32) BPWR_MCBSP1, DSP_CLK_MCBSP1},
+	{(u32) BPWR_MCBSP2, DSP_CLK_MCBSP2},
+	{(u32) BPWR_MCBSP3, DSP_CLK_MCBSP3},
+	{(u32) BPWR_MCBSP4, DSP_CLK_MCBSP4},
+	{(u32) BPWR_MCBSP5, DSP_CLK_MCBSP5},
+	{(u32) BPWR_SSI, DSP_CLK_SSI}
 };
 
 /* Interrupt Register Offsets */
diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c
index 38338d1..4ac53ea 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430.c
@@ -305,7 +305,7 @@ static dsp_status bridge_brd_monitor(struct wmd_dev_context *hDevContext)
 	}
 	(*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2, 0,
 					OMAP3430_IVA2_MOD, RM_RSTCTRL);
-	dsp_clk_enable(DSP_CLK_IVA2_CK);
+	dsp_clk_enable(DSP_CLK_IVA2);
 
 	if (DSP_SUCCEEDED(status)) {
 		/* set the device state to IDLE */
@@ -675,7 +675,7 @@ static dsp_status bridge_brd_stop(struct wmd_dev_context *hDevContext)
 		sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
 		mdelay(10);
 
-		clk_status = dsp_clk_disable(DSP_CLK_IVA2_CK);
+		clk_status = dsp_clk_disable(DSP_CLK_IVA2);
 
 		/* IVA2 is not in OFF state */
 		/* Set PM_PWSTCTRL_IVA2  to OFF */
@@ -685,7 +685,7 @@ static dsp_status bridge_brd_stop(struct wmd_dev_context *hDevContext)
 		(*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
 					OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
 	} else {
-		clk_status = dsp_clk_disable(DSP_CLK_IVA2_CK);
+		clk_status = dsp_clk_disable(DSP_CLK_IVA2);
 	}
 	udelay(10);
 	/* Release the Ext Base virtual Address as the next DSP Program
@@ -743,7 +743,7 @@ static dsp_status wmd_brd_delete(struct wmd_dev_context *hDevContext)
 	 * to ensure that there are no pending L3 or other transactons from
 	 * IVA2 */
 	status = sleep_dsp(dev_context, PWR_EMERGENCYDEEPSLEEP, NULL);
-	clk_status = dsp_clk_disable(DSP_CLK_IVA2_CK);
+	clk_status = dsp_clk_disable(DSP_CLK_IVA2);
 
 	/* Release the Ext Base virtual Address as the next DSP Program
 	 * may have a different load address */
diff --git a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
index 2e08746..879f99e 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
@@ -288,7 +288,6 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 	u32 tmp_index;
 	u32 dsp_per_clks_before;
 	dsp_status status = DSP_SOK;
-	dsp_status status1 = DSP_SOK;
 	struct cfg_hostres *resources = dev_context->resources;
 	u32 value;
 
@@ -318,9 +317,6 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 	ext_clk_cmd = (ext_clk >> MBX_PM_CLK_CMDSHIFT) & MBX_PM_CLK_CMDMASK;
 	switch (ext_clk_cmd) {
 	case BPWR_DISABLE_CLOCK:
-		/* Call BP to disable the needed clock */
-		status1 = dsp_clk_disable(bpwr_clks[clk_id_index].int_clk);
-		status = dsp_clk_disable(bpwr_clks[clk_id_index].fun_clk);
 		if (bpwr_clkid[clk_id_index] == BPWR_MCBSP1) {
 			/* clear MCBSP1_CLKS, on McBSP1 OFF */
 			value = __raw_readl(
@@ -336,16 +332,16 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 			__raw_writel(value,
 				resources->dw_sys_ctrl_base + 0x274);
 		}
+		status = dsp_clk_disable(bpwr_clks[clk_id_index].clk);
 		dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id,
 					  false);
-		if ((DSP_SUCCEEDED(status)) && (DSP_SUCCEEDED(status1))) {
+		if (DSP_SUCCEEDED(status)) {
 			(dev_context->dsp_per_clks) &=
 			    (~((u32) (1 << clk_id_index)));
 		}
 		break;
 	case BPWR_ENABLE_CLOCK:
-		status1 = dsp_clk_enable(bpwr_clks[clk_id_index].int_clk);
-		status = dsp_clk_enable(bpwr_clks[clk_id_index].fun_clk);
+		status = dsp_clk_enable(bpwr_clks[clk_id_index].clk);
 		if (bpwr_clkid[clk_id_index] == BPWR_MCBSP1) {
 			/* set MCBSP1_CLKS, on McBSP1 ON */
 			value = __raw_readl(
@@ -362,9 +358,8 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 				resources->dw_sys_ctrl_base + 0x274);
 		}
 		dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id, true);
-		if ((DSP_SUCCEEDED(status)) && (DSP_SUCCEEDED(status1))) {
+		if (DSP_SUCCEEDED(status))
 			(dev_context->dsp_per_clks) |= (1 << clk_id_index);
-		}
 		break;
 	default:
 		dev_dbg(bridge, "%s: Unsupported CMD\n", __func__);
@@ -467,9 +462,6 @@ dsp_status dsp_peripheral_clocks_disable(struct wmd_dev_context *dev_context,
 
 	for (clk_idx = 0; clk_idx < MBX_PM_MAX_RESOURCES; clk_idx++) {
 		if (((dev_context->dsp_per_clks) >> clk_idx) & 0x01) {
-			/* Disables the interface clock of the peripheral */
-			status =
-			    dsp_clk_disable(bpwr_clks[clk_idx].int_clk);
 			if (bpwr_clkid[clk_idx] == BPWR_MCBSP1) {
 				/* clear MCBSP1_CLKS, on McBSP1 OFF */
 				value = __raw_readl(resources->dw_sys_ctrl_base
@@ -486,9 +478,8 @@ dsp_status dsp_peripheral_clocks_disable(struct wmd_dev_context *dev_context,
 					     + 0x274);
 			}
 
-			/* Disables the functional clock of the periphearl */
-			status =
-			    dsp_clk_disable(bpwr_clks[clk_idx].fun_clk);
+			/* Disables the clocks of the peripheral */
+			status = dsp_clk_disable(bpwr_clks[clk_idx].clk);
 		}
 	}
 	return status;
@@ -502,7 +493,7 @@ dsp_status dsp_peripheral_clocks_enable(struct wmd_dev_context *dev_context,
 					IN void *pargs)
 {
 	u32 clk_idx;
-	dsp_status int_clk_status = -EPERM, fun_clk_status = -EPERM;
+	dsp_status clk_status = -EPERM;
 	struct cfg_hostres *resources = dev_context->resources;
 	u32 value;
 
@@ -511,9 +502,8 @@ dsp_status dsp_peripheral_clocks_enable(struct wmd_dev_context *dev_context,
 
 	for (clk_idx = 0; clk_idx < MBX_PM_MAX_RESOURCES; clk_idx++) {
 		if (((dev_context->dsp_per_clks) >> clk_idx) & 0x01) {
-			/* Enable the interface clock of the peripheral */
-			int_clk_status =
-			    dsp_clk_enable(bpwr_clks[clk_idx].int_clk);
+			/* Enable the clocks of the peripheral */
+			clk_status = dsp_clk_enable(bpwr_clks[clk_idx].clk);
 			if (bpwr_clkid[clk_idx] == BPWR_MCBSP1) {
 				/* set MCBSP1_CLKS, on McBSP1 ON */
 				value = __raw_readl(resources->dw_sys_ctrl_base
@@ -529,14 +519,9 @@ dsp_status dsp_peripheral_clocks_enable(struct wmd_dev_context *dev_context,
 				__raw_writel(value, resources->dw_sys_ctrl_base
 					     + 0x274);
 			}
-			/* Enable the functional clock of the periphearl */
-			fun_clk_status =
-			    dsp_clk_enable(bpwr_clks[clk_idx].fun_clk);
 		}
 	}
-	if ((int_clk_status | fun_clk_status) != DSP_SOK)
-		return -EPERM;
-	return DSP_SOK;
+	return clk_status;
 }
 
 void dsp_clk_wakeup_event_ctrl(u32 ClkId, bool enable)
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: Move MCBSP_CLOCKS code to a common place

[Omar Ramirez Luna]

Given that:
"Bridge should enable McBSP_CLKS (using T2 clock) so that DPLL4
 can be gated. Once McBSP2 clock is released, it should disable
 McBSP_CLKS as it prevents PER and CORE domain transitions when
 OFF is set to target power state."

It seems this code was duplicated, now it has been moved to be
called only when dsp is requesting a MCBSP clock.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/services/clk.c       |   52 +++++++++++++++++++++
 drivers/dsp/bridge/wmd/tiomap3430_pwr.c |   77 -------------------------------
 2 files changed, 52 insertions(+), 77 deletions(-)

diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index 9a439c7..763a599 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -25,6 +25,10 @@
 #include <dspbridge/std.h>
 #include <dspbridge/dbdefs.h>
 #include <dspbridge/errbase.h>
+#include <dspbridge/cfg.h>
+#include <dspbridge/drv.h>
+#include <dspbridge/dev.h>
+#include "_tiomap.h"
 
 /*  ----------------------------------- Trace & Debug */
 #include <dspbridge/dbc.h>
@@ -124,6 +128,52 @@ void dsp_clk_init(void)
 					ssi.sst_fck, ssi.ssr_fck, ssi.ick);
 }
 
+static void mcbsp_clk_prepare(bool flag, u8 id)
+{
+	struct cfg_hostres *resources;
+	struct dev_object *hdev_object = NULL;
+	struct wmd_dev_context *wmd_context = NULL;
+	u32 val;
+
+	hdev_object = (struct dev_object *)drv_get_first_dev_object();
+	if (!hdev_object)
+		return;
+
+	dev_get_wmd_context(hdev_object, &wmd_context);
+	if (!wmd_context)
+		return;
+
+	resources = wmd_context->resources;
+	if (!resources)
+		return;
+
+	if (flag) {
+		if (id == DSP_CLK_MCBSP1) {
+			/* set MCBSP1_CLKS, on McBSP1 ON */
+			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
+			val |= 1 << 2;
+			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
+		} else if (id == DSP_CLK_MCBSP2) {
+			/* set MCBSP2_CLKS, on McBSP2 ON */
+			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
+			val |= 1 << 6;
+			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
+		}
+	} else {
+		if (id == DSP_CLK_MCBSP1) {
+			/* clear MCBSP1_CLKS, on McBSP1 OFF */
+			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
+			val &= ~(1 << 2);
+			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
+		} else if (id == DSP_CLK_MCBSP2) {
+			/* clear MCBSP2_CLKS, on McBSP2 OFF */
+			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
+			val &= ~(1 << 6);
+			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
+		}
+	}
+}
+
 /*
  *  ======== dsp_clk_enable ========
  *  Purpose:
@@ -142,6 +192,7 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 		timer[clk_id] = omap_dm_timer_request_specific(DMT_ID(clk_id));
 		break;
 	case MCBSP_CLK:
+		mcbsp_clk_prepare(true, clk_id);
 		omap_mcbsp_set_io_type(MCBSP_ID(clk_id), OMAP_MCBSP_POLL_IO);
 		omap_mcbsp_request(MCBSP_ID(clk_id));
 		break;
@@ -187,6 +238,7 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 		omap_dm_timer_free(timer[clk_id]);
 		break;
 	case MCBSP_CLK:
+		mcbsp_clk_prepare(false, clk_id);
 		omap_mcbsp_free(MCBSP_ID(clk_id));
 		break;
 	case WDT_CLK:
diff --git a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
index 879f99e..6d1d557 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
@@ -288,16 +288,10 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 	u32 tmp_index;
 	u32 dsp_per_clks_before;
 	dsp_status status = DSP_SOK;
-	struct cfg_hostres *resources = dev_context->resources;
-	u32 value;
 
 	dsp_per_clks_before = dev_context->dsp_per_clks;
 
 	ext_clk = (u32) *((u32 *) pargs);
-
-	if (!resources)
-		return -EPERM;
-
 	ext_clk_id = ext_clk & MBX_PM_CLK_IDMASK;
 
 	/* process the power message -- TODO, keep it in a separate function */
@@ -317,21 +311,6 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 	ext_clk_cmd = (ext_clk >> MBX_PM_CLK_CMDSHIFT) & MBX_PM_CLK_CMDMASK;
 	switch (ext_clk_cmd) {
 	case BPWR_DISABLE_CLOCK:
-		if (bpwr_clkid[clk_id_index] == BPWR_MCBSP1) {
-			/* clear MCBSP1_CLKS, on McBSP1 OFF */
-			value = __raw_readl(
-				resources->dw_sys_ctrl_base + 0x274);
-			value &= ~(1 << 2);
-			__raw_writel(value,
-				resources->dw_sys_ctrl_base + 0x274);
-		} else if (bpwr_clkid[clk_id_index] == BPWR_MCBSP2) {
-			/* clear MCBSP2_CLKS, on McBSP2 OFF */
-			value = __raw_readl(
-				resources->dw_sys_ctrl_base + 0x274);
-			value &= ~(1 << 6);
-			__raw_writel(value,
-				resources->dw_sys_ctrl_base + 0x274);
-		}
 		status = dsp_clk_disable(bpwr_clks[clk_id_index].clk);
 		dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id,
 					  false);
@@ -342,21 +321,6 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 		break;
 	case BPWR_ENABLE_CLOCK:
 		status = dsp_clk_enable(bpwr_clks[clk_id_index].clk);
-		if (bpwr_clkid[clk_id_index] == BPWR_MCBSP1) {
-			/* set MCBSP1_CLKS, on McBSP1 ON */
-			value = __raw_readl(
-				resources->dw_sys_ctrl_base + 0x274);
-			value |= 1 << 2;
-			__raw_writel(value,
-				resources->dw_sys_ctrl_base + 0x274);
-		} else if (bpwr_clkid[clk_id_index] == BPWR_MCBSP2) {
-			/* set MCBSP2_CLKS, on McBSP2 ON */
-			value = __raw_readl(
-				resources->dw_sys_ctrl_base + 0x274);
-			value |= 1 << 6;
-			__raw_writel(value,
-				resources->dw_sys_ctrl_base + 0x274);
-		}
 		dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id, true);
 		if (DSP_SUCCEEDED(status))
 			(dev_context->dsp_per_clks) |= (1 << clk_id_index);
@@ -454,30 +418,9 @@ dsp_status dsp_peripheral_clocks_disable(struct wmd_dev_context *dev_context,
 {
 	u32 clk_idx;
 	dsp_status status = DSP_SOK;
-	struct cfg_hostres *resources = dev_context->resources;
-	u32 value;
-
-	if (!resources)
-		return -EPERM;
 
 	for (clk_idx = 0; clk_idx < MBX_PM_MAX_RESOURCES; clk_idx++) {
 		if (((dev_context->dsp_per_clks) >> clk_idx) & 0x01) {
-			if (bpwr_clkid[clk_idx] == BPWR_MCBSP1) {
-				/* clear MCBSP1_CLKS, on McBSP1 OFF */
-				value = __raw_readl(resources->dw_sys_ctrl_base
-						    + 0x274);
-				value &= ~(1 << 2);
-				__raw_writel(value, resources->dw_sys_ctrl_base
-					     + 0x274);
-			} else if (bpwr_clkid[clk_idx] == BPWR_MCBSP2) {
-				/* clear MCBSP2_CLKS, on McBSP2 OFF */
-				value = __raw_readl(resources->dw_sys_ctrl_base
-						    + 0x274);
-				value &= ~(1 << 6);
-				__raw_writel(value, resources->dw_sys_ctrl_base
-					     + 0x274);
-			}
-
 			/* Disables the clocks of the peripheral */
 			status = dsp_clk_disable(bpwr_clks[clk_idx].clk);
 		}
@@ -494,31 +437,11 @@ dsp_status dsp_peripheral_clocks_enable(struct wmd_dev_context *dev_context,
 {
 	u32 clk_idx;
 	dsp_status clk_status = -EPERM;
-	struct cfg_hostres *resources = dev_context->resources;
-	u32 value;
-
-	if (!resources)
-		return -EPERM;
 
 	for (clk_idx = 0; clk_idx < MBX_PM_MAX_RESOURCES; clk_idx++) {
 		if (((dev_context->dsp_per_clks) >> clk_idx) & 0x01) {
 			/* Enable the clocks of the peripheral */
 			clk_status = dsp_clk_enable(bpwr_clks[clk_idx].clk);
-			if (bpwr_clkid[clk_idx] == BPWR_MCBSP1) {
-				/* set MCBSP1_CLKS, on McBSP1 ON */
-				value = __raw_readl(resources->dw_sys_ctrl_base
-						    + 0x274);
-				value |= 1 << 2;
-				__raw_writel(value, resources->dw_sys_ctrl_base
-					     + 0x274);
-			} else if (bpwr_clkid[clk_idx] == BPWR_MCBSP2) {
-				/* set MCBSP2_CLKS, on McBSP2 ON */
-				value = __raw_readl(resources->dw_sys_ctrl_base
-						    + 0x274);
-				value |= 1 << 6;
-				__raw_writel(value, resources->dw_sys_ctrl_base
-					     + 0x274);
-			}
 		}
 	}
 	return clk_status;
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: Balance the number of enable/disable

[Omar Ramirez Luna]

This patch ensure a balanced number of enable/disable
calls is made.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/services/clk.c |   37 +++++++++++++++++++++++++++++++++++++
 1 files changed, 37 insertions(+), 0 deletions(-)

diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
index 763a599..c4f0874 100644
--- a/drivers/dsp/bridge/services/clk.c
+++ b/drivers/dsp/bridge/services/clk.c
@@ -71,6 +71,23 @@ struct dsp_ssi {
 
 static struct dsp_ssi ssi;
 
+static u32 dsp_clocks;
+
+static inline u32 is_dsp_clk_active(u32 clk, u8 id)
+{
+	return clk & (1 << id);
+}
+
+static inline void set_dsp_clk_active(u32 *clk, u8 id)
+{
+	*clk |= (1 << id);
+}
+
+static inline void set_dsp_clk_inactive(u32 *clk, u8 id)
+{
+	*clk &= ~(1 << id);
+}
+
 static s8 get_clk_type(u8 id)
 {
 	s8 type;
@@ -184,6 +201,11 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 {
 	dsp_status status = DSP_SOK;
 
+	if (is_dsp_clk_active(dsp_clocks, clk_id)) {
+		dev_err(bridge, "WARN: clock id %d already enabled\n", clk_id);
+		goto out;
+	}
+
 	switch (get_clk_type(clk_id)) {
 	case IVA2_CLK:
 		clk_enable(iva2_clk);
@@ -215,8 +237,13 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
 		break;
 	default:
 		dev_err(bridge, "Invalid clock id for enable\n");
+		status = -EPERM;
 	}
 
+	if (DSP_SUCCEEDED(status))
+		set_dsp_clk_active(&dsp_clocks, clk_id);
+
+out:
 	return status;
 }
 
@@ -230,6 +257,11 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 {
 	dsp_status status = DSP_SOK;
 
+	if (!is_dsp_clk_active(dsp_clocks, clk_id)) {
+		dev_err(bridge, "ERR: clock id %d already disabled\n", clk_id);
+		goto out;
+	}
+
 	switch (get_clk_type(clk_id)) {
 	case IVA2_CLK:
 		clk_disable(iva2_clk);
@@ -253,8 +285,13 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
 		break;
 	default:
 		dev_err(bridge, "Invalid clock id for disable\n");
+		status = -EPERM;
 	}
 
+	if (DSP_SUCCEEDED(status))
+		set_dsp_clk_inactive(&dsp_clocks, clk_id);
+
+out:
 	return status;
 }
 
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: move clk to dsp-clock

[Omar Ramirez Luna]

Rename file and move it outside services layer.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
---
 drivers/dsp/bridge/Makefile             |    4 +-
 drivers/dsp/bridge/rmgr/drv_interface.c |    2 +
 drivers/dsp/bridge/services/clk.c       |  334 -------------------------------
 drivers/dsp/bridge/services/services.c  |    3 -
 drivers/dsp/bridge/wmd/dsp-clock.c      |  334 +++++++++++++++++++++++++++++++
 5 files changed, 338 insertions(+), 339 deletions(-)
 delete mode 100644 drivers/dsp/bridge/services/clk.c
 create mode 100644 drivers/dsp/bridge/wmd/dsp-clock.c

diff --git a/drivers/dsp/bridge/Makefile b/drivers/dsp/bridge/Makefile
index e243670..8b9a681 100644
--- a/drivers/dsp/bridge/Makefile
+++ b/drivers/dsp/bridge/Makefile
@@ -1,11 +1,11 @@
 obj-$(CONFIG_MPU_BRIDGE)	+= bridgedriver.o
 
 libgen = gen/gb.o gen/gs.o gen/gh.o gen/uuidutil.o
-libservices = services/sync.o services/clk.o services/cfg.o \
+libservices = services/sync.o services/cfg.o \
 		services/ntfy.o services/services.o
 libwmd = wmd/chnl_sm.o wmd/msg_sm.o wmd/io_sm.o wmd/tiomap3430.o \
 		wmd/tiomap3430_pwr.o wmd/tiomap_io.o \
-		wmd/mmu_fault.o wmd/ue_deh.o wmd/wdt.o
+		wmd/mmu_fault.o wmd/ue_deh.o wmd/wdt.o wmd/dsp-clock.o
 libpmgr = pmgr/chnl.o pmgr/io.o pmgr/msg.o pmgr/cod.o pmgr/dev.o pmgr/wcd.o \
 		pmgr/dmm.o pmgr/cmm.o pmgr/dbll.o
 librmgr = rmgr/dbdcd.o rmgr/disp.o rmgr/drv.o rmgr/mgr.o rmgr/node.o \
diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c b/drivers/dsp/bridge/rmgr/drv_interface.c
index ea2a5f3..db1c746 100644
--- a/drivers/dsp/bridge/rmgr/drv_interface.c
+++ b/drivers/dsp/bridge/rmgr/drv_interface.c
@@ -285,6 +285,7 @@ static int __devinit omap34_xx_bridge_probe(struct platform_device *pdev)
 	}
 #endif
 
+	dsp_clk_init();
 	services_init();
 
 	/*  Autostart flag.  This should be set to true if the DSP image should
@@ -382,6 +383,7 @@ static int __devexit omap34_xx_bridge_remove(struct platform_device *pdev)
 func_cont:
 	mem_ext_phys_pool_release();
 
+	dsp_clk_exit();
 	services_exit();
 
 	devno = MKDEV(driver_major, 0);
diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c
deleted file mode 100644
index c4f0874..0000000
--- a/drivers/dsp/bridge/services/clk.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * clk.c
- *
- * DSP-BIOS Bridge driver support functions for TI OMAP processors.
- *
- * Clock and Timer services.
- *
- * Copyright (C) 2005-2006 Texas Instruments, Inc.
- *
- * This package is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
- * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- */
-
-/*  ----------------------------------- Host OS */
-#include <dspbridge/host_os.h>
-#include <plat/dmtimer.h>
-#include <plat/mcbsp.h>
-
-/*  ----------------------------------- DSP/BIOS Bridge */
-#include <dspbridge/std.h>
-#include <dspbridge/dbdefs.h>
-#include <dspbridge/errbase.h>
-#include <dspbridge/cfg.h>
-#include <dspbridge/drv.h>
-#include <dspbridge/dev.h>
-#include "_tiomap.h"
-
-/*  ----------------------------------- Trace & Debug */
-#include <dspbridge/dbc.h>
-
-/*  ----------------------------------- This */
-#include <dspbridge/clk.h>
-
-/*  ----------------------------------- Defines, Data Structures, Typedefs */
-
-#define OMAP_SSI_OFFSET			0x58000
-#define OMAP_SSI_SIZE			0x1000
-#define OMAP_SSI_SYSCONFIG_OFFSET	0x10
-
-#define SSI_AUTOIDLE			(1 << 0)
-#define SSI_SIDLE_SMARTIDLE		(2 << 3)
-#define SSI_MIDLE_NOIDLE		(1 << 12)
-
-/* Clk types requested by the dsp */
-#define IVA2_CLK	0
-#define GPT_CLK		1
-#define WDT_CLK		2
-#define MCBSP_CLK	3
-#define SSI_CLK		4
-
-/* Bridge GPT id (1 - 4), DM Timer id (5 - 8) */
-#define DMT_ID(id) ((id) + 4)
-
-/* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (0 - 4) */
-#define MCBSP_ID(id) ((id) - 6)
-
-static struct omap_dm_timer *timer[4];
-
-struct clk *iva2_clk;
-
-struct dsp_ssi {
-	struct clk *sst_fck;
-	struct clk *ssr_fck;
-	struct clk *ick;
-};
-
-static struct dsp_ssi ssi;
-
-static u32 dsp_clocks;
-
-static inline u32 is_dsp_clk_active(u32 clk, u8 id)
-{
-	return clk & (1 << id);
-}
-
-static inline void set_dsp_clk_active(u32 *clk, u8 id)
-{
-	*clk |= (1 << id);
-}
-
-static inline void set_dsp_clk_inactive(u32 *clk, u8 id)
-{
-	*clk &= ~(1 << id);
-}
-
-static s8 get_clk_type(u8 id)
-{
-	s8 type;
-
-	if (id == DSP_CLK_IVA2)
-		type = IVA2_CLK;
-	else if (id <= DSP_CLK_GPT8)
-		type = GPT_CLK;
-	else if (id == DSP_CLK_WDT3)
-		type = WDT_CLK;
-	else if (id <= DSP_CLK_MCBSP5)
-		type = MCBSP_CLK;
-	else if (id == DSP_CLK_SSI)
-		type = SSI_CLK;
-	else
-		type = -1;
-
-	return type;
-}
-
-/*
- *  ======== dsp_clk_exit ========
- *  Purpose:
- *      Cleanup CLK module.
- */
-void dsp_clk_exit(void)
-{
-	clk_put(iva2_clk);
-	clk_put(ssi.sst_fck);
-	clk_put(ssi.ssr_fck);
-	clk_put(ssi.ick);
-}
-
-/*
- *  ======== dsp_clk_init ========
- *  Purpose:
- *      Initialize CLK module.
- */
-void dsp_clk_init(void)
-{
-	static struct platform_device dspbridge_device;
-
-	dspbridge_device.dev.bus = &platform_bus_type;
-
-	iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
-	if (IS_ERR(iva2_clk))
-		dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
-
-	ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck");
-	ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck");
-	ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick");
-
-	if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick))
-		dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n",
-					ssi.sst_fck, ssi.ssr_fck, ssi.ick);
-}
-
-static void mcbsp_clk_prepare(bool flag, u8 id)
-{
-	struct cfg_hostres *resources;
-	struct dev_object *hdev_object = NULL;
-	struct wmd_dev_context *wmd_context = NULL;
-	u32 val;
-
-	hdev_object = (struct dev_object *)drv_get_first_dev_object();
-	if (!hdev_object)
-		return;
-
-	dev_get_wmd_context(hdev_object, &wmd_context);
-	if (!wmd_context)
-		return;
-
-	resources = wmd_context->resources;
-	if (!resources)
-		return;
-
-	if (flag) {
-		if (id == DSP_CLK_MCBSP1) {
-			/* set MCBSP1_CLKS, on McBSP1 ON */
-			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
-			val |= 1 << 2;
-			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
-		} else if (id == DSP_CLK_MCBSP2) {
-			/* set MCBSP2_CLKS, on McBSP2 ON */
-			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
-			val |= 1 << 6;
-			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
-		}
-	} else {
-		if (id == DSP_CLK_MCBSP1) {
-			/* clear MCBSP1_CLKS, on McBSP1 OFF */
-			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
-			val &= ~(1 << 2);
-			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
-		} else if (id == DSP_CLK_MCBSP2) {
-			/* clear MCBSP2_CLKS, on McBSP2 OFF */
-			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
-			val &= ~(1 << 6);
-			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
-		}
-	}
-}
-
-/*
- *  ======== dsp_clk_enable ========
- *  Purpose:
- *      Enable Clock .
- *
- */
-dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
-{
-	dsp_status status = DSP_SOK;
-
-	if (is_dsp_clk_active(dsp_clocks, clk_id)) {
-		dev_err(bridge, "WARN: clock id %d already enabled\n", clk_id);
-		goto out;
-	}
-
-	switch (get_clk_type(clk_id)) {
-	case IVA2_CLK:
-		clk_enable(iva2_clk);
-		break;
-	case GPT_CLK:
-		timer[clk_id] = omap_dm_timer_request_specific(DMT_ID(clk_id));
-		break;
-	case MCBSP_CLK:
-		mcbsp_clk_prepare(true, clk_id);
-		omap_mcbsp_set_io_type(MCBSP_ID(clk_id), OMAP_MCBSP_POLL_IO);
-		omap_mcbsp_request(MCBSP_ID(clk_id));
-		break;
-	case WDT_CLK:
-		dev_err(bridge, "ERROR: DSP requested to enable WDT3 clk\n");
-		break;
-	case SSI_CLK:
-		clk_enable(ssi.sst_fck);
-		clk_enable(ssi.ssr_fck);
-		clk_enable(ssi.ick);
-
-		/*
-		 * The SSI module need to configured not to have the Forced
-		 * idle for master interface. If it is set to forced idle,
-		 * the SSI module is transitioning to standby thereby causing
-		 * the client in the DSP hang waiting for the SSI module to
-		 * be active after enabling the clocks
-		 */
-		ssi_clk_prepare(true);
-		break;
-	default:
-		dev_err(bridge, "Invalid clock id for enable\n");
-		status = -EPERM;
-	}
-
-	if (DSP_SUCCEEDED(status))
-		set_dsp_clk_active(&dsp_clocks, clk_id);
-
-out:
-	return status;
-}
-
-/*
- *  ======== dsp_clk_disable ========
- *  Purpose:
- *      Disable the clock.
- *
- */
-dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
-{
-	dsp_status status = DSP_SOK;
-
-	if (!is_dsp_clk_active(dsp_clocks, clk_id)) {
-		dev_err(bridge, "ERR: clock id %d already disabled\n", clk_id);
-		goto out;
-	}
-
-	switch (get_clk_type(clk_id)) {
-	case IVA2_CLK:
-		clk_disable(iva2_clk);
-		break;
-	case GPT_CLK:
-		omap_dm_timer_free(timer[clk_id]);
-		break;
-	case MCBSP_CLK:
-		mcbsp_clk_prepare(false, clk_id);
-		omap_mcbsp_free(MCBSP_ID(clk_id));
-		break;
-	case WDT_CLK:
-		dev_err(bridge, "ERROR: DSP requested to disable WDT3 clk\n");
-		break;
-	case SSI_CLK:
-		ssi_clk_prepare(false);
-		ssi_clk_prepare(false);
-		clk_disable(ssi.sst_fck);
-		clk_disable(ssi.ssr_fck);
-		clk_disable(ssi.ick);
-		break;
-	default:
-		dev_err(bridge, "Invalid clock id for disable\n");
-		status = -EPERM;
-	}
-
-	if (DSP_SUCCEEDED(status))
-		set_dsp_clk_inactive(&dsp_clocks, clk_id);
-
-out:
-	return status;
-}
-
-u32 dsp_clk_get_iva2_rate(void)
-{
-	u32 clk_speed_khz;
-
-	clk_speed_khz = clk_get_rate(iva2_clk);
-	clk_speed_khz /= 1000;
-	dev_dbg(bridge, "%s: clk speed Khz = %d\n", __func__, clk_speed_khz);
-
-	return clk_speed_khz;
-}
-
-void ssi_clk_prepare(bool FLAG)
-{
-	void __iomem *ssi_base;
-	unsigned int value;
-
-	ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
-	if (!ssi_base) {
-		pr_err("%s: error, SSI not configured\n", __func__);
-		return;
-	}
-
-	if (FLAG) {
-		/* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
-		 * no idle
-		 */
-		value = SSI_AUTOIDLE | SSI_SIDLE_SMARTIDLE | SSI_MIDLE_NOIDLE;
-	} else {
-		/* Set Autoidle, SIDLEMode to forced idle, and MIDLEmode to
-		 * forced idle
-		 */
-		value = SSI_AUTOIDLE;
-	}
-
-	__raw_writel(value, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
-	iounmap(ssi_base);
-}
diff --git a/drivers/dsp/bridge/services/services.c b/drivers/dsp/bridge/services/services.c
index cc2e89d..23be95c 100644
--- a/drivers/dsp/bridge/services/services.c
+++ b/drivers/dsp/bridge/services/services.c
@@ -42,8 +42,6 @@
  */
 void services_exit(void)
 {
-	/* Uninitialize all SERVICES modules here */
-	dsp_clk_exit();
 	cfg_exit();
 }
 
@@ -59,7 +57,6 @@ bool services_init(void)
 
 	/* Perform required initialization of SERVICES modules. */
 	fcfg = cfg_init();
-	dsp_clk_init();
 
 	ret = fcfg;
 
diff --git a/drivers/dsp/bridge/wmd/dsp-clock.c b/drivers/dsp/bridge/wmd/dsp-clock.c
new file mode 100644
index 0000000..c4f0874
--- /dev/null
+++ b/drivers/dsp/bridge/wmd/dsp-clock.c
@@ -0,0 +1,334 @@
+/*
+ * clk.c
+ *
+ * DSP-BIOS Bridge driver support functions for TI OMAP processors.
+ *
+ * Clock and Timer services.
+ *
+ * Copyright (C) 2005-2006 Texas Instruments, Inc.
+ *
+ * This package is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+/*  ----------------------------------- Host OS */
+#include <dspbridge/host_os.h>
+#include <plat/dmtimer.h>
+#include <plat/mcbsp.h>
+
+/*  ----------------------------------- DSP/BIOS Bridge */
+#include <dspbridge/std.h>
+#include <dspbridge/dbdefs.h>
+#include <dspbridge/errbase.h>
+#include <dspbridge/cfg.h>
+#include <dspbridge/drv.h>
+#include <dspbridge/dev.h>
+#include "_tiomap.h"
+
+/*  ----------------------------------- Trace & Debug */
+#include <dspbridge/dbc.h>
+
+/*  ----------------------------------- This */
+#include <dspbridge/clk.h>
+
+/*  ----------------------------------- Defines, Data Structures, Typedefs */
+
+#define OMAP_SSI_OFFSET			0x58000
+#define OMAP_SSI_SIZE			0x1000
+#define OMAP_SSI_SYSCONFIG_OFFSET	0x10
+
+#define SSI_AUTOIDLE			(1 << 0)
+#define SSI_SIDLE_SMARTIDLE		(2 << 3)
+#define SSI_MIDLE_NOIDLE		(1 << 12)
+
+/* Clk types requested by the dsp */
+#define IVA2_CLK	0
+#define GPT_CLK		1
+#define WDT_CLK		2
+#define MCBSP_CLK	3
+#define SSI_CLK		4
+
+/* Bridge GPT id (1 - 4), DM Timer id (5 - 8) */
+#define DMT_ID(id) ((id) + 4)
+
+/* Bridge MCBSP id (6 - 10), OMAP Mcbsp id (0 - 4) */
+#define MCBSP_ID(id) ((id) - 6)
+
+static struct omap_dm_timer *timer[4];
+
+struct clk *iva2_clk;
+
+struct dsp_ssi {
+	struct clk *sst_fck;
+	struct clk *ssr_fck;
+	struct clk *ick;
+};
+
+static struct dsp_ssi ssi;
+
+static u32 dsp_clocks;
+
+static inline u32 is_dsp_clk_active(u32 clk, u8 id)
+{
+	return clk & (1 << id);
+}
+
+static inline void set_dsp_clk_active(u32 *clk, u8 id)
+{
+	*clk |= (1 << id);
+}
+
+static inline void set_dsp_clk_inactive(u32 *clk, u8 id)
+{
+	*clk &= ~(1 << id);
+}
+
+static s8 get_clk_type(u8 id)
+{
+	s8 type;
+
+	if (id == DSP_CLK_IVA2)
+		type = IVA2_CLK;
+	else if (id <= DSP_CLK_GPT8)
+		type = GPT_CLK;
+	else if (id == DSP_CLK_WDT3)
+		type = WDT_CLK;
+	else if (id <= DSP_CLK_MCBSP5)
+		type = MCBSP_CLK;
+	else if (id == DSP_CLK_SSI)
+		type = SSI_CLK;
+	else
+		type = -1;
+
+	return type;
+}
+
+/*
+ *  ======== dsp_clk_exit ========
+ *  Purpose:
+ *      Cleanup CLK module.
+ */
+void dsp_clk_exit(void)
+{
+	clk_put(iva2_clk);
+	clk_put(ssi.sst_fck);
+	clk_put(ssi.ssr_fck);
+	clk_put(ssi.ick);
+}
+
+/*
+ *  ======== dsp_clk_init ========
+ *  Purpose:
+ *      Initialize CLK module.
+ */
+void dsp_clk_init(void)
+{
+	static struct platform_device dspbridge_device;
+
+	dspbridge_device.dev.bus = &platform_bus_type;
+
+	iva2_clk = clk_get(&dspbridge_device.dev, "iva2_ck");
+	if (IS_ERR(iva2_clk))
+		dev_err(bridge, "failed to get iva2 clock %p\n", iva2_clk);
+
+	ssi.sst_fck = clk_get(&dspbridge_device.dev, "ssi_sst_fck");
+	ssi.ssr_fck = clk_get(&dspbridge_device.dev, "ssi_ssr_fck");
+	ssi.ick = clk_get(&dspbridge_device.dev, "ssi_ick");
+
+	if (IS_ERR(ssi.sst_fck) || IS_ERR(ssi.ssr_fck) || IS_ERR(ssi.ick))
+		dev_err(bridge, "failed to get ssi: sst %p, ssr %p, ick %p\n",
+					ssi.sst_fck, ssi.ssr_fck, ssi.ick);
+}
+
+static void mcbsp_clk_prepare(bool flag, u8 id)
+{
+	struct cfg_hostres *resources;
+	struct dev_object *hdev_object = NULL;
+	struct wmd_dev_context *wmd_context = NULL;
+	u32 val;
+
+	hdev_object = (struct dev_object *)drv_get_first_dev_object();
+	if (!hdev_object)
+		return;
+
+	dev_get_wmd_context(hdev_object, &wmd_context);
+	if (!wmd_context)
+		return;
+
+	resources = wmd_context->resources;
+	if (!resources)
+		return;
+
+	if (flag) {
+		if (id == DSP_CLK_MCBSP1) {
+			/* set MCBSP1_CLKS, on McBSP1 ON */
+			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
+			val |= 1 << 2;
+			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
+		} else if (id == DSP_CLK_MCBSP2) {
+			/* set MCBSP2_CLKS, on McBSP2 ON */
+			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
+			val |= 1 << 6;
+			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
+		}
+	} else {
+		if (id == DSP_CLK_MCBSP1) {
+			/* clear MCBSP1_CLKS, on McBSP1 OFF */
+			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
+			val &= ~(1 << 2);
+			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
+		} else if (id == DSP_CLK_MCBSP2) {
+			/* clear MCBSP2_CLKS, on McBSP2 OFF */
+			val = __raw_readl(resources->dw_sys_ctrl_base + 0x274);
+			val &= ~(1 << 6);
+			__raw_writel(val, resources->dw_sys_ctrl_base + 0x274);
+		}
+	}
+}
+
+/*
+ *  ======== dsp_clk_enable ========
+ *  Purpose:
+ *      Enable Clock .
+ *
+ */
+dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id)
+{
+	dsp_status status = DSP_SOK;
+
+	if (is_dsp_clk_active(dsp_clocks, clk_id)) {
+		dev_err(bridge, "WARN: clock id %d already enabled\n", clk_id);
+		goto out;
+	}
+
+	switch (get_clk_type(clk_id)) {
+	case IVA2_CLK:
+		clk_enable(iva2_clk);
+		break;
+	case GPT_CLK:
+		timer[clk_id] = omap_dm_timer_request_specific(DMT_ID(clk_id));
+		break;
+	case MCBSP_CLK:
+		mcbsp_clk_prepare(true, clk_id);
+		omap_mcbsp_set_io_type(MCBSP_ID(clk_id), OMAP_MCBSP_POLL_IO);
+		omap_mcbsp_request(MCBSP_ID(clk_id));
+		break;
+	case WDT_CLK:
+		dev_err(bridge, "ERROR: DSP requested to enable WDT3 clk\n");
+		break;
+	case SSI_CLK:
+		clk_enable(ssi.sst_fck);
+		clk_enable(ssi.ssr_fck);
+		clk_enable(ssi.ick);
+
+		/*
+		 * The SSI module need to configured not to have the Forced
+		 * idle for master interface. If it is set to forced idle,
+		 * the SSI module is transitioning to standby thereby causing
+		 * the client in the DSP hang waiting for the SSI module to
+		 * be active after enabling the clocks
+		 */
+		ssi_clk_prepare(true);
+		break;
+	default:
+		dev_err(bridge, "Invalid clock id for enable\n");
+		status = -EPERM;
+	}
+
+	if (DSP_SUCCEEDED(status))
+		set_dsp_clk_active(&dsp_clocks, clk_id);
+
+out:
+	return status;
+}
+
+/*
+ *  ======== dsp_clk_disable ========
+ *  Purpose:
+ *      Disable the clock.
+ *
+ */
+dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id)
+{
+	dsp_status status = DSP_SOK;
+
+	if (!is_dsp_clk_active(dsp_clocks, clk_id)) {
+		dev_err(bridge, "ERR: clock id %d already disabled\n", clk_id);
+		goto out;
+	}
+
+	switch (get_clk_type(clk_id)) {
+	case IVA2_CLK:
+		clk_disable(iva2_clk);
+		break;
+	case GPT_CLK:
+		omap_dm_timer_free(timer[clk_id]);
+		break;
+	case MCBSP_CLK:
+		mcbsp_clk_prepare(false, clk_id);
+		omap_mcbsp_free(MCBSP_ID(clk_id));
+		break;
+	case WDT_CLK:
+		dev_err(bridge, "ERROR: DSP requested to disable WDT3 clk\n");
+		break;
+	case SSI_CLK:
+		ssi_clk_prepare(false);
+		ssi_clk_prepare(false);
+		clk_disable(ssi.sst_fck);
+		clk_disable(ssi.ssr_fck);
+		clk_disable(ssi.ick);
+		break;
+	default:
+		dev_err(bridge, "Invalid clock id for disable\n");
+		status = -EPERM;
+	}
+
+	if (DSP_SUCCEEDED(status))
+		set_dsp_clk_inactive(&dsp_clocks, clk_id);
+
+out:
+	return status;
+}
+
+u32 dsp_clk_get_iva2_rate(void)
+{
+	u32 clk_speed_khz;
+
+	clk_speed_khz = clk_get_rate(iva2_clk);
+	clk_speed_khz /= 1000;
+	dev_dbg(bridge, "%s: clk speed Khz = %d\n", __func__, clk_speed_khz);
+
+	return clk_speed_khz;
+}
+
+void ssi_clk_prepare(bool FLAG)
+{
+	void __iomem *ssi_base;
+	unsigned int value;
+
+	ssi_base = ioremap(L4_34XX_BASE + OMAP_SSI_OFFSET, OMAP_SSI_SIZE);
+	if (!ssi_base) {
+		pr_err("%s: error, SSI not configured\n", __func__);
+		return;
+	}
+
+	if (FLAG) {
+		/* Set Autoidle, SIDLEMode to smart idle, and MIDLEmode to
+		 * no idle
+		 */
+		value = SSI_AUTOIDLE | SSI_SIDLE_SMARTIDLE | SSI_MIDLE_NOIDLE;
+	} else {
+		/* Set Autoidle, SIDLEMode to forced idle, and MIDLEmode to
+		 * forced idle
+		 */
+		value = SSI_AUTOIDLE;
+	}
+
+	__raw_writel(value, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
+	iounmap(ssi_base);
+}
-- 
1.6.0.4

[PATCH v2] DSPBRIDGE: reorganize the code to handle peripheral clocks

[Omar Ramirez Luna]

This patch moves and simplifies the code used to enable/disable
all the requested peripheral clocks.

Signed-off-by: Omar Ramirez Luna <omar.ramirez@hotmail.com>
---
 arch/arm/plat-omap/include/dspbridge/clk.h |    4 ++
 drivers/dsp/bridge/rmgr/drv_interface.c    |    1 +
 drivers/dsp/bridge/wmd/_tiomap_pwr.h       |   17 ----------
 drivers/dsp/bridge/wmd/dsp-clock.c         |   43 +++++++++++++++++++++++++
 drivers/dsp/bridge/wmd/tiomap3430_pwr.c    |   47 +++-------------------------
 drivers/dsp/bridge/wmd/tiomap_io.c         |    4 +-
 drivers/dsp/bridge/wmd/ue_deh.c            |    2 +-
 7 files changed, 56 insertions(+), 62 deletions(-)

diff --git a/arch/arm/plat-omap/include/dspbridge/clk.h b/arch/arm/plat-omap/include/dspbridge/clk.h
index e6b09c7..439fc2d 100644
--- a/arch/arm/plat-omap/include/dspbridge/clk.h
+++ b/arch/arm/plat-omap/include/dspbridge/clk.h
@@ -75,6 +75,8 @@ extern void dsp_clk_init(void);
  */
 extern dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id);
 
+u32 dsp_clock_enable_all(u32 dsp_per_clocks);
+
 /*
  *  ======== dsp_clk_disable ========
  *  Purpose:
@@ -90,6 +92,8 @@ extern dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id);
 
 extern u32 dsp_clk_get_iva2_rate(void);
 
+u32 dsp_clock_disable_all(u32 dsp_per_clocks);
+
 extern void ssi_clk_prepare(bool FLAG);
 
 #endif /* _SYNC_H */
diff --git a/drivers/dsp/bridge/rmgr/drv_interface.c b/drivers/dsp/bridge/rmgr/drv_interface.c
index db1c746..04b17be 100644
--- a/drivers/dsp/bridge/rmgr/drv_interface.c
+++ b/drivers/dsp/bridge/rmgr/drv_interface.c
@@ -41,6 +41,7 @@
 
 /*  ----------------------------------- OS Adaptation Layer */
 #include <dspbridge/services.h>
+#include <dspbridge/clk.h>
 #include <dspbridge/sync.h>
 
 /*  ----------------------------------- Platform Manager */
diff --git a/drivers/dsp/bridge/wmd/_tiomap_pwr.h b/drivers/dsp/bridge/wmd/_tiomap_pwr.h
index a7a4fc2..1948e83 100644
--- a/drivers/dsp/bridge/wmd/_tiomap_pwr.h
+++ b/drivers/dsp/bridge/wmd/_tiomap_pwr.h
@@ -64,23 +64,6 @@ dsp_status pre_scale_dsp(struct wmd_dev_context *dev_context, IN void *pargs);
  */
 dsp_status handle_constraints_set(struct wmd_dev_context *dev_context,
 				  IN void *pargs);
-/*
- *  ======== dsp_peripheral_clocks_disable ========
- *  	This function disables all the peripheral clocks that
- *	were enabled by DSP. Call this function only when
- *	DSP is entering Hibernation or when DSP is in
- *	Error state
- */
-dsp_status dsp_peripheral_clocks_disable(struct wmd_dev_context *dev_context,
-					 IN void *pargs);
-
-/*
- *  ======== dsp_peripheral_clocks_enable ========
- *  	This function enables all the peripheral clocks that
- *	were requested by DSP.
- */
-dsp_status dsp_peripheral_clocks_enable(struct wmd_dev_context *dev_context,
-					IN void *pargs);
 
 /*
  *  ======== dsp_clk_wakeup_event_ctrl ========
diff --git a/drivers/dsp/bridge/wmd/dsp-clock.c b/drivers/dsp/bridge/wmd/dsp-clock.c
index c4f0874..608ff03 100644
--- a/drivers/dsp/bridge/wmd/dsp-clock.c
+++ b/drivers/dsp/bridge/wmd/dsp-clock.c
@@ -115,6 +115,8 @@ static s8 get_clk_type(u8 id)
  */
 void dsp_clk_exit(void)
 {
+	dsp_clock_disable_all(dsp_clocks);
+
 	clk_put(iva2_clk);
 	clk_put(ssi.sst_fck);
 	clk_put(ssi.ssr_fck);
@@ -247,6 +249,25 @@ out:
 	return status;
 }
 
+/**
+ * dsp_clock_enable_all - Enable clocks used by the DSP
+ * @dev_context		Driver's device context strucure
+ *
+ * This function enables all the peripheral clocks that were requested by DSP.
+ */
+u32 dsp_clock_enable_all(u32 dsp_per_clocks)
+{
+	u32 clk_id;
+	u32 status = -EPERM;
+
+	for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
+		if (is_dsp_clk_active(dsp_per_clocks, clk_id))
+			status = dsp_clk_enable(clk_id);
+	}
+
+	return status;
+}
+
 /*
  *  ======== dsp_clk_disable ========
  *  Purpose:
@@ -295,6 +316,27 @@ out:
 	return status;
 }
 
+/**
+ * dsp_clock_disable_all - Disable all active clocks
+ * @dev_context		Driver's device context structure
+ *
+ * This function disables all the peripheral clocks that were enabled by DSP.
+ * It is meant to be called only when DSP is entering hibernation or when DSP
+ * is in error state.
+ */
+u32 dsp_clock_disable_all(u32 dsp_per_clocks)
+{
+	u32 clk_id;
+	u32 status = -EPERM;
+
+	for (clk_id = 0; clk_id < DSP_CLK_NOT_DEFINED; clk_id++) {
+		if (is_dsp_clk_active(dsp_per_clocks, clk_id))
+			status = dsp_clk_disable(clk_id);
+	}
+
+	return status;
+}
+
 u32 dsp_clk_get_iva2_rate(void)
 {
 	u32 clk_speed_khz;
@@ -332,3 +374,4 @@ void ssi_clk_prepare(bool FLAG)
 	__raw_writel(value, ssi_base + OMAP_SSI_SYSCONFIG_OFFSET);
 	iounmap(ssi_base);
 }
+
diff --git a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
index 6d1d557..906c2c5 100644
--- a/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
+++ b/drivers/dsp/bridge/wmd/tiomap3430_pwr.c
@@ -112,7 +112,7 @@ dsp_status handle_hibernation_from_dsp(struct wmd_dev_context *dev_context)
 		omap_mbox_save_ctx(dev_context->mbox);
 
 		/* Turn off DSP Peripheral clocks and DSP Load monitor timer */
-		status = dsp_peripheral_clocks_disable(dev_context, NULL);
+		status = dsp_clock_disable_all(dev_context->dsp_per_clks);
 
 		/* Disable wdt on hibernation. */
 		dsp_wdt_enable(false);
@@ -230,7 +230,7 @@ dsp_status sleep_dsp(struct wmd_dev_context *dev_context, IN u32 dw_cmd,
 		dsp_wdt_enable(false);
 
 		/* Turn off DSP Peripheral clocks */
-		status = dsp_peripheral_clocks_disable(dev_context, NULL);
+		status = dsp_clock_disable_all(dev_context->dsp_per_clks);
 		if (DSP_FAILED(status)) {
 			return status;
 		}
@@ -316,14 +316,15 @@ dsp_status dsp_peripheral_clk_ctrl(struct wmd_dev_context *dev_context,
 					  false);
 		if (DSP_SUCCEEDED(status)) {
 			(dev_context->dsp_per_clks) &=
-			    (~((u32) (1 << clk_id_index)));
+				(~((u32) (1 << bpwr_clks[clk_id_index].clk)));
 		}
 		break;
 	case BPWR_ENABLE_CLOCK:
 		status = dsp_clk_enable(bpwr_clks[clk_id_index].clk);
 		dsp_clk_wakeup_event_ctrl(bpwr_clks[clk_id_index].clk_id, true);
 		if (DSP_SUCCEEDED(status))
-			(dev_context->dsp_per_clks) |= (1 << clk_id_index);
+			(dev_context->dsp_per_clks) |=
+				(1 << bpwr_clks[clk_id_index].clk);
 		break;
 	default:
 		dev_dbg(bridge, "%s: Unsupported CMD\n", __func__);
@@ -409,44 +410,6 @@ dsp_status post_scale_dsp(struct wmd_dev_context *dev_context, IN void *pargs)
 	return status;
 }
 
-/*
- *  ========dsp_peripheral_clocks_disable========
- *  Disables all the peripheral clocks that were requested by DSP
- */
-dsp_status dsp_peripheral_clocks_disable(struct wmd_dev_context *dev_context,
-					 IN void *pargs)
-{
-	u32 clk_idx;
-	dsp_status status = DSP_SOK;
-
-	for (clk_idx = 0; clk_idx < MBX_PM_MAX_RESOURCES; clk_idx++) {
-		if (((dev_context->dsp_per_clks) >> clk_idx) & 0x01) {
-			/* Disables the clocks of the peripheral */
-			status = dsp_clk_disable(bpwr_clks[clk_idx].clk);
-		}
-	}
-	return status;
-}
-
-/*
- *  ========dsp_peripheral_clocks_enable========
- *  Enables all the peripheral clocks that were requested by DSP
- */
-dsp_status dsp_peripheral_clocks_enable(struct wmd_dev_context *dev_context,
-					IN void *pargs)
-{
-	u32 clk_idx;
-	dsp_status clk_status = -EPERM;
-
-	for (clk_idx = 0; clk_idx < MBX_PM_MAX_RESOURCES; clk_idx++) {
-		if (((dev_context->dsp_per_clks) >> clk_idx) & 0x01) {
-			/* Enable the clocks of the peripheral */
-			clk_status = dsp_clk_enable(bpwr_clks[clk_idx].clk);
-		}
-	}
-	return clk_status;
-}
-
 void dsp_clk_wakeup_event_ctrl(u32 ClkId, bool enable)
 {
 	struct cfg_hostres *resources;
diff --git a/drivers/dsp/bridge/wmd/tiomap_io.c b/drivers/dsp/bridge/wmd/tiomap_io.c
index 5880428..2ab7b7d 100644
--- a/drivers/dsp/bridge/wmd/tiomap_io.c
+++ b/drivers/dsp/bridge/wmd/tiomap_io.c
@@ -415,7 +415,7 @@ dsp_status sm_interrupt_dsp(struct wmd_dev_context *dev_context, u16 mb_val)
 		}
 #endif
 		/* Restart the peripheral clocks */
-		dsp_peripheral_clocks_enable(dev_context, NULL);
+		dsp_clock_enable_all(dev_context->dsp_per_clks);
 		dsp_wdt_enable(true);
 
 		/*
@@ -445,7 +445,7 @@ dsp_status sm_interrupt_dsp(struct wmd_dev_context *dev_context, u16 mb_val)
 		dev_context->dw_brd_state = BRD_RUNNING;
 	} else if (dev_context->dw_brd_state == BRD_RETENTION) {
 		/* Restart the peripheral clocks */
-		dsp_peripheral_clocks_enable(dev_context, NULL);
+		dsp_clock_enable_all(dev_context->dsp_per_clks);
 	}
 
 	status = omap_mbox_msg_send(dev_context->mbox, mb_val);
diff --git a/drivers/dsp/bridge/wmd/ue_deh.c b/drivers/dsp/bridge/wmd/ue_deh.c
index 03b29b6..55a6790 100644
--- a/drivers/dsp/bridge/wmd/ue_deh.c
+++ b/drivers/dsp/bridge/wmd/ue_deh.c
@@ -328,7 +328,7 @@ void bridge_deh_notify(struct deh_mgr *deh_mgr, u32 ulEventMask, u32 dwErrInfo)
 	/* Set the Board state as ERROR */
 	dev_context->dw_brd_state = BRD_ERROR;
 	/* Disable all the clocks that were enabled by DSP */
-	dsp_peripheral_clocks_disable(dev_context, NULL);
+	dsp_clock_disable_all(dev_context->dsp_per_clks);
 	/*
 	 * Avoid the subsequent WDT if it happens once,
 	 * also if fatal error occurs.
-- 
1.6.0.4

Re: [PATCH v2] generic clk module removal

[Nishanth Menon]

On 04/27/2010 08:29 PM, Omar Ramirez Luna wrote:
> This set of patches remove clk module from the services layer.
>
> Now:
> - GPT 5-8 are controlled through DM Timer framework.
> - MCBSP clocks are enabled by requesting the proper mcbsp device.
> - WDT is left for bridge driver to control rather than on request from dsp.
> - SSI is controlled by enabling/disabling its sst, ssr and ick clocks.
>
> v2:
> - rebased
> - keep iva2 handling as it is advised to turn off the clocks for iva reset
>    sources.
> - release all the clocks (disable&  free) if driver is uninstalled.
>
>
> Omar Ramirez Luna (5):
>    DSPBRIDGE: iva2 clock handling
>    DSPBRIDGE: dsp interface to enable ssi clocks
>    DSPBRIDGE: Balance the number of enable/disable
>    DSPBRIDGE: move clk to dsp-clock
>    DSPBRIDGE: reorganize the code to handle peripheral clocks
>    DSPBRIDGE: remove clk_handle from drv interface
>    DSPBRIDGE: fail if clk handle is NULL
>    DSPBRIDGE: Now actually fail if a clk handle is wrong
>    DSPBRIDGE: Rename services_clk_* to dsp_clk_*
>    DSPBRIDGE: remove unused clock sys_ck
>    DSPBRIDGE: remove function clk_set32k_hz
>    DSPBRIDGE: remove clk_get_use_cnt
>    DSPBRIDGE: trivial clock cleanup for unused code
>    DSPBRIDGE: function to get the type of clock requested by dsp
>    DSPBRIDGE: use dm timer framework for gpt timers
>    DSPBRIDGE: use omap mcbsp to enable mcbsp clocks
>    DSPBRIDGE: remove wdt3 from dsp control
>    DSPBRIDGE: use one call for both ick and fck clocks
>    DSPBRIDGE: Move MCBSP_CLOCKS code to a common place
is there a series numbering for this patchset?
Regards,
Nishanth Menon

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Felipe Contreras]

On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna <omar.ramirez@ti.com> wrote:
> This patch switches to use DM timer framework instead of
> a custom one for GPT timers, currently dsp can make use of
> gpt 5, 6, 7 or 8.

I heard someone that was using gpt 8 for something else. Is it
possible to configure dsp-bridge to not use it?

-- 
Felipe Contreras

Re: [PATCH v2] generic clk module removal

[Omar Ramirez Luna]

On 4/27/2010 8:34 PM, Nishanth Menon wrote:
> On 04/27/2010 08:29 PM, Omar Ramirez Luna wrote:
>> This set of patches remove clk module from the services layer.
>>
>> Now:
>> - GPT 5-8 are controlled through DM Timer framework.
>> - MCBSP clocks are enabled by requesting the proper mcbsp device.
>> - WDT is left for bridge driver to control rather than on request from dsp.
>> - SSI is controlled by enabling/disabling its sst, ssr and ick clocks.
>>
>> v2:
>> - rebased
>> - keep iva2 handling as it is advised to turn off the clocks for iva reset
>>     sources.
>> - release all the clocks (disable&   free) if driver is uninstalled.
>>
>>
[...]
> is there a series numbering for this patchset?

wrong sed substitution command to place "v2" :/

I will resend.

- omar

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Omar Ramirez Luna]

On 4/28/2010 2:46 AM, Felipe Contreras wrote:
> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>  wrote:
>> This patch switches to use DM timer framework instead of
>> a custom one for GPT timers, currently dsp can make use of
>> gpt 5, 6, 7 or 8.
>
> I heard someone that was using gpt 8 for something else. Is it
> possible to configure dsp-bridge to not use it?
>

There are two scenarios:

1. The request comes from the DSP side (afaik for video use case), the 
change should be in the DSP side binaries to request some other gpt 
instead. I don't know how possible is to get this changed.

2. bridge driver also requests gpt8 whenever a mmu fault is triggered, 
this to set a timer to interrupt the dsp after the mmu fault dump has 
been finished, I think this can be easily replaced in bridge to use some 
other gpt, but "1" is still there. (besides a new patch is needed to 
remove direct access to dm timer inside ue_deh and make it to go through 
dsp-clock)

Regards,
omar

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Kevin Hilman]

Omar Ramirez Luna <omar.ramirez@ti.com> writes:

> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>  wrote:
>>> This patch switches to use DM timer framework instead of
>>> a custom one for GPT timers, currently dsp can make use of
>>> gpt 5, 6, 7 or 8.
>>
>> I heard someone that was using gpt 8 for something else. Is it
>> possible to configure dsp-bridge to not use it?
>>
>
> There are two scenarios:
>
> 1. The request comes from the DSP side (afaik for video use case), the
> change should be in the DSP side binaries to request some other gpt
> instead. I don't know how possible is to get this changed.
>
> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
> this to set a timer to interrupt the dsp after the mmu fault dump has
> been finished, I think this can be easily replaced in bridge to use
> some other gpt, but "1" is still there. (besides a new patch is needed
> to remove direct access to dm timer inside ue_deh and make it to go
> through dsp-clock)

Why does Bridge care at all which specific timers it requests?  They
are all the same, with the exception of GPT1 which is in the WKUP
powerdomain and already used as the kernel clocksource.

Bridge should just use the generic _request() instead of
_request_specific()

Kevin

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Nishanth Menon]

Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
> Omar Ramirez Luna <omar.ramirez@ti.com> writes:
> 
>> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>  wrote:
>>>> This patch switches to use DM timer framework instead of
>>>> a custom one for GPT timers, currently dsp can make use of
>>>> gpt 5, 6, 7 or 8.
>>> I heard someone that was using gpt 8 for something else. Is it
>>> possible to configure dsp-bridge to not use it?
>>>
>> There are two scenarios:
>>
>> 1. The request comes from the DSP side (afaik for video use case), the
>> change should be in the DSP side binaries to request some other gpt
>> instead. I don't know how possible is to get this changed.
>>
>> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
>> this to set a timer to interrupt the dsp after the mmu fault dump has
>> been finished, I think this can be easily replaced in bridge to use
>> some other gpt, but "1" is still there. (besides a new patch is needed
>> to remove direct access to dm timer inside ue_deh and make it to go
>> through dsp-clock)
> 
> Why does Bridge care at all which specific timers it requests?  They
> are all the same, with the exception of GPT1 which is in the WKUP
> powerdomain and already used as the kernel clocksource.
> 
> Bridge should just use the generic _request() instead of
> _request_specific()
> 
trouble I believe is that DSP BIOS uses a specific timer.

-- 
Regards,
Nishanth Menon

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Omar Ramirez Luna]

On 4/28/2010 11:36 AM, Menon, Nishanth wrote:
> Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
>> Omar Ramirez Luna<omar.ramirez@ti.com>  writes:
>>
>>> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>>>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>   wrote:
>>>>> This patch switches to use DM timer framework instead of
>>>>> a custom one for GPT timers, currently dsp can make use of
>>>>> gpt 5, 6, 7 or 8.
>>>> I heard someone that was using gpt 8 for something else. Is it
>>>> possible to configure dsp-bridge to not use it?
>>>>
>>> There are two scenarios:
>>>
>>> 1. The request comes from the DSP side (afaik for video use case), the
>>> change should be in the DSP side binaries to request some other gpt
>>> instead. I don't know how possible is to get this changed.
>>>
>>> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
>>> this to set a timer to interrupt the dsp after the mmu fault dump has
>>> been finished, I think this can be easily replaced in bridge to use
>>> some other gpt, but "1" is still there. (besides a new patch is needed
>>> to remove direct access to dm timer inside ue_deh and make it to go
>>> through dsp-clock)
>>
>> Why does Bridge care at all which specific timers it requests?  They
>> are all the same, with the exception of GPT1 which is in the WKUP
>> powerdomain and already used as the kernel clocksource.
>>
>> Bridge should just use the generic _request() instead of
>> _request_specific()
>>
> trouble I believe is that DSP BIOS uses a specific timer.
>

yes, dsp side wants:
bios --> GPT5 (only used during boot up -> baseimage load)
load monitoring --> GPT 6 (used while the dsp is awake)
AV Sync --> GPT 8 (based on use case)

to generate the interrupt for mmu fault case it needs one connected to 
the dsp interrupt line and only 5, 6, 7 or 8 apply.

Regards,

Omar

RE: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Uribe de Leon, Armando]

Hi,

> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Menon, Nishanth
> Sent: Wednesday, April 28, 2010 11:36 AM
> To: Kevin Hilman
> Cc: Ramirez Luna, Omar; Felipe Contreras; linux-omap; Ameya Palande;
> Hiroshi Doyu; Felipe Contreras; Omar Ramirez Luna
> Subject: Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers
> 
> Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
> > Omar Ramirez Luna <omar.ramirez@ti.com> writes:
> >
> >> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
> >>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez
> Luna<omar.ramirez@ti.com>  wrote:
> >>>> This patch switches to use DM timer framework instead of
> >>>> a custom one for GPT timers, currently dsp can make use of
> >>>> gpt 5, 6, 7 or 8.
> >>> I heard someone that was using gpt 8 for something else. Is it
> >>> possible to configure dsp-bridge to not use it?
> >>>
> >> There are two scenarios:
> >>
> >> 1. The request comes from the DSP side (afaik for video use case), the
> >> change should be in the DSP side binaries to request some other gpt
> >> instead. I don't know how possible is to get this changed.
> >>
> >> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
> >> this to set a timer to interrupt the dsp after the mmu fault dump has
> >> been finished, I think this can be easily replaced in bridge to use
> >> some other gpt, but "1" is still there. (besides a new patch is needed
> >> to remove direct access to dm timer inside ue_deh and make it to go
> >> through dsp-clock)
> >
> > Why does Bridge care at all which specific timers it requests?  They
> > are all the same, with the exception of GPT1 which is in the WKUP
> > powerdomain and already used as the kernel clocksource.
> >
> > Bridge should just use the generic _request() instead of
> > _request_specific()
> >
> trouble I believe is that DSP BIOS uses a specific timer.

DSP/BIOS uses GPT5 on bridge boot up, after that the GPT5 is released.
The GPT6 is used in DSP Bridge for DSP CPU Load Monitoring.

Regards,
Armando.

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Felipe Contreras]

On Wed, Apr 28, 2010 at 7:36 PM, Nishanth Menon <nm@ti.com> wrote:
> Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
>>
>> Omar Ramirez Luna <omar.ramirez@ti.com> writes:
>>
>>> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>>>>
>>>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>
>>>>  wrote:
>>>>>
>>>>> This patch switches to use DM timer framework instead of
>>>>> a custom one for GPT timers, currently dsp can make use of
>>>>> gpt 5, 6, 7 or 8.
>>>>
>>>> I heard someone that was using gpt 8 for something else. Is it
>>>> possible to configure dsp-bridge to not use it?
>>>>
>>> There are two scenarios:
>>>
>>> 1. The request comes from the DSP side (afaik for video use case), the
>>> change should be in the DSP side binaries to request some other gpt
>>> instead. I don't know how possible is to get this changed.
>>>
>>> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
>>> this to set a timer to interrupt the dsp after the mmu fault dump has
>>> been finished, I think this can be easily replaced in bridge to use
>>> some other gpt, but "1" is still there. (besides a new patch is needed
>>> to remove direct access to dm timer inside ue_deh and make it to go
>>> through dsp-clock)
>>
>> Why does Bridge care at all which specific timers it requests?  They
>> are all the same, with the exception of GPT1 which is in the WKUP
>> powerdomain and already used as the kernel clocksource.
>>
>> Bridge should just use the generic _request() instead of
>> _request_specific()
>>
> trouble I believe is that DSP BIOS uses a specific timer.

FTR, this is the conversation... I don't understand what PWM is,
hopefully somebody else does:

<av500> felipec: ping
<felipec> av500: pong
<av500> dspbridge uses GPT8 which is one of the PWM capable ones
<av500> which is not so nice as my hw guy uses that PWM
<av500> otoh, only GPT5-8 can deliver IRQ to DSP
<av500> so I see code that handles 5-8, but somehow only GPT6 and GPT8
seem to be really used
<felipec> av500: you are wondering if it could use GPT7 or something?
<av500> yup
<av500> GPT8 is unfortunately in the DSP and the PWM set
<av500> DSP 5-8, PWM 8-11
<felipec> av500: I've no idea =/
<av500> felipec: ok, and who could?
<felipec> that's for the mailing list I guess
<av500> l-o?
<felipec> yup
<av500> k, thx
<felipec> orbarron maybe
<av500> orbarron: ^^^^^^^

Cheers.

-- 
Felipe Contreras
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Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Vladimir Pantelic]

Omar Ramirez Luna wrote:

> yes, dsp side wants:
> bios -->  GPT5 (only used during boot up ->  baseimage load)
> load monitoring -->  GPT 6 (used while the dsp is awake)
> AV Sync -->  GPT 8 (based on use case)
>
> to generate the interrupt for mmu fault case it needs one connected to
> the dsp interrupt line and only 5, 6, 7 or 8 apply.

and it is also GPT8 for mmu fault handling atm.

So, as GPT8 is one of the PWM capable, could that functionality be moved
to GPT7?

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Nishanth Menon]

Vladimir Pantelic had written, on 04/28/2010 12:11 PM, the following:
> Omar Ramirez Luna wrote:
> 
>> yes, dsp side wants:
>> bios -->  GPT5 (only used during boot up ->  baseimage load)
>> load monitoring -->  GPT 6 (used while the dsp is awake)
>> AV Sync -->  GPT 8 (based on use case)
>>
>> to generate the interrupt for mmu fault case it needs one connected to
>> the dsp interrupt line and only 5, 6, 7 or 8 apply.
> 
> and it is also GPT8 for mmu fault handling atm.
> 
> So, as GPT8 is one of the PWM capable, could that functionality be moved
> to GPT7?
> 
Obvious good point instead to tell DSP BIOS which timers to use as part 
of the params we pass to the DSP similar to what we do with frequencies 
for DSP Load balancer to work.. makes it scalable and does not allow DSP 
to hog a timer which could be used for LCD backlight dimming with PWM 
for example..

-- 
Regards,
Nishanth Menon

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Kevin Hilman]

Omar Ramirez Luna <omar.ramirez@ti.com> writes:

> On 4/28/2010 11:36 AM, Menon, Nishanth wrote:
>> Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
>>> Omar Ramirez Luna<omar.ramirez@ti.com>  writes:
>>>
>>>> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>>>>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>   wrote:
>>>>>> This patch switches to use DM timer framework instead of
>>>>>> a custom one for GPT timers, currently dsp can make use of
>>>>>> gpt 5, 6, 7 or 8.
>>>>> I heard someone that was using gpt 8 for something else. Is it
>>>>> possible to configure dsp-bridge to not use it?
>>>>>
>>>> There are two scenarios:
>>>>
>>>> 1. The request comes from the DSP side (afaik for video use case), the
>>>> change should be in the DSP side binaries to request some other gpt
>>>> instead. I don't know how possible is to get this changed.
>>>>
>>>> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
>>>> this to set a timer to interrupt the dsp after the mmu fault dump has
>>>> been finished, I think this can be easily replaced in bridge to use
>>>> some other gpt, but "1" is still there. (besides a new patch is needed
>>>> to remove direct access to dm timer inside ue_deh and make it to go
>>>> through dsp-clock)
>>>
>>> Why does Bridge care at all which specific timers it requests?  They
>>> are all the same, with the exception of GPT1 which is in the WKUP
>>> powerdomain and already used as the kernel clocksource.
>>>
>>> Bridge should just use the generic _request() instead of
>>> _request_specific()
>>>
>> trouble I believe is that DSP BIOS uses a specific timer.
>>
>
> yes, dsp side wants:
> bios --> GPT5 (only used during boot up -> baseimage load)
> load monitoring --> GPT 6 (used while the dsp is awake)
> AV Sync --> GPT 8 (based on use case)
>
> to generate the interrupt for mmu fault case it needs one connected to
> the dsp interrupt line and only 5, 6, 7 or 8 apply.

Then DSP bios is broken by hard-coding *general purpose* timers.

Kevin

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Nishanth Menon]

Kevin Hilman had written, on 04/28/2010 12:59 PM, the following:
> Omar Ramirez Luna <omar.ramirez@ti.com> writes:
> 
>> On 4/28/2010 11:36 AM, Menon, Nishanth wrote:
>>> Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
>>>> Omar Ramirez Luna<omar.ramirez@ti.com>  writes:
>>>>
>>>>> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>>>>>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>   wrote:
>>>>>>> This patch switches to use DM timer framework instead of
>>>>>>> a custom one for GPT timers, currently dsp can make use of
>>>>>>> gpt 5, 6, 7 or 8.
>>>>>> I heard someone that was using gpt 8 for something else. Is it
>>>>>> possible to configure dsp-bridge to not use it?
>>>>>>
>>>>> There are two scenarios:
>>>>>
>>>>> 1. The request comes from the DSP side (afaik for video use case), the
>>>>> change should be in the DSP side binaries to request some other gpt
>>>>> instead. I don't know how possible is to get this changed.
>>>>>
>>>>> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
>>>>> this to set a timer to interrupt the dsp after the mmu fault dump has
>>>>> been finished, I think this can be easily replaced in bridge to use
>>>>> some other gpt, but "1" is still there. (besides a new patch is needed
>>>>> to remove direct access to dm timer inside ue_deh and make it to go
>>>>> through dsp-clock)
>>>> Why does Bridge care at all which specific timers it requests?  They
>>>> are all the same, with the exception of GPT1 which is in the WKUP
>>>> powerdomain and already used as the kernel clocksource.
>>>>
>>>> Bridge should just use the generic _request() instead of
>>>> _request_specific()
>>>>
>>> trouble I believe is that DSP BIOS uses a specific timer.
>>>
>> yes, dsp side wants:
>> bios --> GPT5 (only used during boot up -> baseimage load)
>> load monitoring --> GPT 6 (used while the dsp is awake)
>> AV Sync --> GPT 8 (based on use case)
>>
>> to generate the interrupt for mmu fault case it needs one connected to
>> the dsp interrupt line and only 5, 6, 7 or 8 apply.
> 
> Then DSP bios is broken by hard-coding *general purpose* timers.
  /me just eats my own words.
Not really.. I just got educated internally that DSP does not get 
interrupts from all GPTs.
Ref: http://focus.ti.com/pdfs/wtbu/SWPU114Q_PrelimFinal_EPDF_03_05_2009.pdf
page 1753 -> only mentioned these timers can generate interrupts for 
DSP, and hence for BIOS's usage. Added to this, the fact that GPT PWM is 
usable on 9,10,11 as well, makes me believe this is something to 
consider as part of board design based on which peripherals one uses and 
their constraints. BIOS is not at fault here to use the resources it 
requires, but is part of system design to look at options, constraints 
and select the ones appropriately..

A similar example is mux pins, you have options to plug to one of many 
options, but if you plug in both a interrupt and a data line to the same 
pin which could run in two different modes, there is a problem there 
right? Alright, that is too obvious i suppose....

-- 
Regards,
Nishanth Menon

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Vladimir Pantelic]

Nishanth Menon wrote:
> Kevin Hilman had written, on 04/28/2010 12:59 PM, the following:
>> Omar Ramirez Luna <omar.ramirez@ti.com> writes:
>>
>>> On 4/28/2010 11:36 AM, Menon, Nishanth wrote:
>>>> Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
>>>>> Omar Ramirez Luna<omar.ramirez@ti.com>  writes:
>>>>>
>>>>>> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>>>>>>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez
>>>>>>> Luna<omar.ramirez@ti.com>   wrote:
>>>>>>>> This patch switches to use DM timer framework instead of
>>>>>>>> a custom one for GPT timers, currently dsp can make use of
>>>>>>>> gpt 5, 6, 7 or 8.
>>>>>>> I heard someone that was using gpt 8 for something else. Is it
>>>>>>> possible to configure dsp-bridge to not use it?
>>>>>>>
>>>>>> There are two scenarios:
>>>>>>
>>>>>> 1. The request comes from the DSP side (afaik for video use case),
>>>>>> the
>>>>>> change should be in the DSP side binaries to request some other gpt
>>>>>> instead. I don't know how possible is to get this changed.
>>>>>>
>>>>>> 2. bridge driver also requests gpt8 whenever a mmu fault is
>>>>>> triggered,
>>>>>> this to set a timer to interrupt the dsp after the mmu fault dump has
>>>>>> been finished, I think this can be easily replaced in bridge to use
>>>>>> some other gpt, but "1" is still there. (besides a new patch is
>>>>>> needed
>>>>>> to remove direct access to dm timer inside ue_deh and make it to go
>>>>>> through dsp-clock)
>>>>> Why does Bridge care at all which specific timers it requests?  They
>>>>> are all the same, with the exception of GPT1 which is in the WKUP
>>>>> powerdomain and already used as the kernel clocksource.
>>>>>
>>>>> Bridge should just use the generic _request() instead of
>>>>> _request_specific()
>>>>>
>>>> trouble I believe is that DSP BIOS uses a specific timer.
>>>>
>>> yes, dsp side wants:
>>> bios --> GPT5 (only used during boot up -> baseimage load)
>>> load monitoring --> GPT 6 (used while the dsp is awake)
>>> AV Sync --> GPT 8 (based on use case)
>>>
>>> to generate the interrupt for mmu fault case it needs one connected to
>>> the dsp interrupt line and only 5, 6, 7 or 8 apply.
>>
>> Then DSP bios is broken by hard-coding *general purpose* timers.
>  /me just eats my own words.
> Not really.. I just got educated internally that DSP does not get
> interrupts from all GPTs.
> Ref: http://focus.ti.com/pdfs/wtbu/SWPU114Q_PrelimFinal_EPDF_03_05_2009.pdf
> page 1753 -> only mentioned these timers can generate interrupts for
> DSP, and hence for BIOS's usage. Added to this, the fact that GPT PWM is
> usable on 9,10,11 as well, makes me believe this is something to
> consider as part of board design based on which peripherals one uses and
> their constraints. BIOS is not at fault here to use the resources it
> requires, but is part of system design to look at options, constraints
> and select the ones appropriately..
> 
> A similar example is mux pins, you have options to plug to one of many
> options, but if you plug in both a interrupt and a data line to the same
> pin which could run in two different modes, there is a problem there
> right? Alright, that is too obvious i suppose....

Yes, just that pin mux issues are pretty obvious reading the TRM and DM,
but the fact that bridge blocks GPT5,6 and 8 is not.

You are telling me that using all 4 GPTs for PWM or input event capture
is not possible when using dspbridge? As I understand, bridge mostly
uses 2 of the GPTs (6 for load monitoring, 8 for sync/mmu fault), so
I think moving GPT8 to 7 should make both sides happy, no?

Regards,

Vladimir

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Nishanth Menon]

Vladimir Pantelic had written, on 04/28/2010 02:52 PM, the following:
> Nishanth Menon wrote:
[...]

>>>>> trouble I believe is that DSP BIOS uses a specific timer.
>>>>>
>>>> yes, dsp side wants:
>>>> bios --> GPT5 (only used during boot up -> baseimage load)
>>>> load monitoring --> GPT 6 (used while the dsp is awake)
>>>> AV Sync --> GPT 8 (based on use case)
>>>>
>>>> to generate the interrupt for mmu fault case it needs one connected to
>>>> the dsp interrupt line and only 5, 6, 7 or 8 apply.
>>> Then DSP bios is broken by hard-coding *general purpose* timers.
>>  /me just eats my own words.
>> Not really.. I just got educated internally that DSP does not get
>> interrupts from all GPTs.
>> Ref: http://focus.ti.com/pdfs/wtbu/SWPU114Q_PrelimFinal_EPDF_03_05_2009.pdf
>> page 1753 -> only mentioned these timers can generate interrupts for
>> DSP, and hence for BIOS's usage. Added to this, the fact that GPT PWM is
>> usable on 9,10,11 as well, makes me believe this is something to
>> consider as part of board design based on which peripherals one uses and
>> their constraints. BIOS is not at fault here to use the resources it
>> requires, but is part of system design to look at options, constraints
>> and select the ones appropriately..
>>
>> A similar example is mux pins, you have options to plug to one of many
>> options, but if you plug in both a interrupt and a data line to the same
>> pin which could run in two different modes, there is a problem there
>> right? Alright, that is too obvious i suppose....
> 
> Yes, just that pin mux issues are pretty obvious reading the TRM and DM,
> but the fact that bridge blocks GPT5,6 and 8 is not.
> 
> You are telling me that using all 4 GPTs for PWM or input event capture
> is not possible when using dspbridge? As I understand, bridge mostly
> uses 2 of the GPTs (6 for load monitoring, 8 for sync/mmu fault), so
> I think moving GPT8 to 7 should make both sides happy, no?

Seriously, is this debate going to close even then?
case a) some other guy is gonna use GPT7 then we are all screwed again
case b) the DSPBIOS guys need more GPT to do something else later on (I 
dont know what.. but just guessing), again screwed?
case c) *what if* some bloke is already using GPT7 for some reason of 
his own and he already has a board working, is'nt he screwed if we 
switch to GPT7 now?

-- 
Regards,
Nishanth Menon

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Kevin Hilman]

Nishanth Menon <nm@ti.com> writes:

> Kevin Hilman had written, on 04/28/2010 12:59 PM, the following:
>> Omar Ramirez Luna <omar.ramirez@ti.com> writes:
>>
>>> On 4/28/2010 11:36 AM, Menon, Nishanth wrote:
>>>> Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
>>>>> Omar Ramirez Luna<omar.ramirez@ti.com>  writes:
>>>>>
>>>>>> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>>>>>>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>   wrote:
>>>>>>>> This patch switches to use DM timer framework instead of
>>>>>>>> a custom one for GPT timers, currently dsp can make use of
>>>>>>>> gpt 5, 6, 7 or 8.
>>>>>>> I heard someone that was using gpt 8 for something else. Is it
>>>>>>> possible to configure dsp-bridge to not use it?
>>>>>>>
>>>>>> There are two scenarios:
>>>>>>
>>>>>> 1. The request comes from the DSP side (afaik for video use case), the
>>>>>> change should be in the DSP side binaries to request some other gpt
>>>>>> instead. I don't know how possible is to get this changed.
>>>>>>
>>>>>> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
>>>>>> this to set a timer to interrupt the dsp after the mmu fault dump has
>>>>>> been finished, I think this can be easily replaced in bridge to use
>>>>>> some other gpt, but "1" is still there. (besides a new patch is needed
>>>>>> to remove direct access to dm timer inside ue_deh and make it to go
>>>>>> through dsp-clock)
>>>>> Why does Bridge care at all which specific timers it requests?  They
>>>>> are all the same, with the exception of GPT1 which is in the WKUP
>>>>> powerdomain and already used as the kernel clocksource.
>>>>>
>>>>> Bridge should just use the generic _request() instead of
>>>>> _request_specific()
>>>>>
>>>> trouble I believe is that DSP BIOS uses a specific timer.
>>>>
>>> yes, dsp side wants:
>>> bios --> GPT5 (only used during boot up -> baseimage load)
>>> load monitoring --> GPT 6 (used while the dsp is awake)
>>> AV Sync --> GPT 8 (based on use case)
>>>
>>> to generate the interrupt for mmu fault case it needs one connected to
>>> the dsp interrupt line and only 5, 6, 7 or 8 apply.
>>
>> Then DSP bios is broken by hard-coding *general purpose* timers.
>  /me just eats my own words.
> Not really.. I just got educated internally that DSP does not get
> interrupts from all GPTs.
> Ref: http://focus.ti.com/pdfs/wtbu/SWPU114Q_PrelimFinal_EPDF_03_05_2009.pdf
> page 1753 -> only mentioned these timers can generate interrupts for
> DSP, and hence for BIOS's usage. 

OK, now that part makes sense.

Kevin

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Benoit Cousson]

On 4/28/2010 10:50 PM, Kevin Hilman wrote:
> Nishanth Menon<nm@ti.com>  writes:
>
>> Kevin Hilman had written, on 04/28/2010 12:59 PM, the following:
>>> Omar Ramirez Luna<omar.ramirez@ti.com>  writes:
>>>
>>>> On 4/28/2010 11:36 AM, Menon, Nishanth wrote:
>>>>> Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
>>>>>> Omar Ramirez Luna<omar.ramirez@ti.com>   writes:
>>>>>>
>>>>>>> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>>>>>>>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>    wrote:
>>>>>>>>> This patch switches to use DM timer framework instead of
>>>>>>>>> a custom one for GPT timers, currently dsp can make use of
>>>>>>>>> gpt 5, 6, 7 or 8.
>>>>>>>> I heard someone that was using gpt 8 for something else. Is it
>>>>>>>> possible to configure dsp-bridge to not use it?
>>>>>>>>
>>>>>>> There are two scenarios:
>>>>>>>
>>>>>>> 1. The request comes from the DSP side (afaik for video use case), the
>>>>>>> change should be in the DSP side binaries to request some other gpt
>>>>>>> instead. I don't know how possible is to get this changed.
>>>>>>>
>>>>>>> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
>>>>>>> this to set a timer to interrupt the dsp after the mmu fault dump has
>>>>>>> been finished, I think this can be easily replaced in bridge to use
>>>>>>> some other gpt, but "1" is still there. (besides a new patch is needed
>>>>>>> to remove direct access to dm timer inside ue_deh and make it to go
>>>>>>> through dsp-clock)
>>>>>> Why does Bridge care at all which specific timers it requests?  They
>>>>>> are all the same, with the exception of GPT1 which is in the WKUP
>>>>>> powerdomain and already used as the kernel clocksource.
>>>>>>
>>>>>> Bridge should just use the generic _request() instead of
>>>>>> _request_specific()
>>>>>>
>>>>> trouble I believe is that DSP BIOS uses a specific timer.
>>>>>
>>>> yes, dsp side wants:
>>>> bios -->  GPT5 (only used during boot up ->  baseimage load)
>>>> load monitoring -->  GPT 6 (used while the dsp is awake)
>>>> AV Sync -->  GPT 8 (based on use case)
>>>>
>>>> to generate the interrupt for mmu fault case it needs one connected to
>>>> the dsp interrupt line and only 5, 6, 7 or 8 apply.
>>>
>>> Then DSP bios is broken by hard-coding *general purpose* timers.
>>   /me just eats my own words.
>> Not really.. I just got educated internally that DSP does not get
>> interrupts from all GPTs.
>> Ref: http://focus.ti.com/pdfs/wtbu/SWPU114Q_PrelimFinal_EPDF_03_05_2009.pdf
>> page 1753 ->  only mentioned these timers can generate interrupts for
>> DSP, and hence for BIOS's usage.
>
> OK, now that part makes sense.

This issue will be even worse on OMAP4 with the CortexM3 (aka Ducati), 
because several IPs like GPIO or GPTIMER will have different IRQ / 
functionality / power partitioning depending of the instance.
One of the proposed solution we considered, at least for the GPTIMERs, 
was to add an extra API that can allow to request a timer based on the 
needed capabilities and not based on index.

We can easily encode in each GPTIMER HWMOD the specificity of an 
instance like (HAS_DSP_IRQ, HAS_IPU_IRQ, HAS_PWM, IN_WKUP_DOMAIN, 
IN_AUDIO_DOMAIN...).
Driver can then use a request_timer_per_functionalies(HAS_DSP_IRQ | 
HAS_IPU_IRQ...).
It will allow driver to be much more independent of the current IP 
implementation for an OMAP version.

Any thoughts?

Regards,
Benoit

Re: [PATCH v2] DSPBRIDGE: use dm timer framework for gpt timers

[Kevin Hilman]

Benoit Cousson <b-cousson@ti.com> writes:

> On 4/28/2010 10:50 PM, Kevin Hilman wrote:
>> Nishanth Menon<nm@ti.com>  writes:
>>
>>> Kevin Hilman had written, on 04/28/2010 12:59 PM, the following:
>>>> Omar Ramirez Luna<omar.ramirez@ti.com>  writes:
>>>>
>>>>> On 4/28/2010 11:36 AM, Menon, Nishanth wrote:
>>>>>> Kevin Hilman had written, on 04/28/2010 11:29 AM, the following:
>>>>>>> Omar Ramirez Luna<omar.ramirez@ti.com>   writes:
>>>>>>>
>>>>>>>> On 4/28/2010 2:46 AM, Felipe Contreras wrote:
>>>>>>>>> On Wed, Apr 28, 2010 at 4:29 AM, Omar Ramirez Luna<omar.ramirez@ti.com>    wrote:
>>>>>>>>>> This patch switches to use DM timer framework instead of
>>>>>>>>>> a custom one for GPT timers, currently dsp can make use of
>>>>>>>>>> gpt 5, 6, 7 or 8.
>>>>>>>>> I heard someone that was using gpt 8 for something else. Is it
>>>>>>>>> possible to configure dsp-bridge to not use it?
>>>>>>>>>
>>>>>>>> There are two scenarios:
>>>>>>>>
>>>>>>>> 1. The request comes from the DSP side (afaik for video use case), the
>>>>>>>> change should be in the DSP side binaries to request some other gpt
>>>>>>>> instead. I don't know how possible is to get this changed.
>>>>>>>>
>>>>>>>> 2. bridge driver also requests gpt8 whenever a mmu fault is triggered,
>>>>>>>> this to set a timer to interrupt the dsp after the mmu fault dump has
>>>>>>>> been finished, I think this can be easily replaced in bridge to use
>>>>>>>> some other gpt, but "1" is still there. (besides a new patch is needed
>>>>>>>> to remove direct access to dm timer inside ue_deh and make it to go
>>>>>>>> through dsp-clock)
>>>>>>> Why does Bridge care at all which specific timers it requests?  They
>>>>>>> are all the same, with the exception of GPT1 which is in the WKUP
>>>>>>> powerdomain and already used as the kernel clocksource.
>>>>>>>
>>>>>>> Bridge should just use the generic _request() instead of
>>>>>>> _request_specific()
>>>>>>>
>>>>>> trouble I believe is that DSP BIOS uses a specific timer.
>>>>>>
>>>>> yes, dsp side wants:
>>>>> bios -->  GPT5 (only used during boot up ->  baseimage load)
>>>>> load monitoring -->  GPT 6 (used while the dsp is awake)
>>>>> AV Sync -->  GPT 8 (based on use case)
>>>>>
>>>>> to generate the interrupt for mmu fault case it needs one connected to
>>>>> the dsp interrupt line and only 5, 6, 7 or 8 apply.
>>>>
>>>> Then DSP bios is broken by hard-coding *general purpose* timers.
>>>   /me just eats my own words.
>>> Not really.. I just got educated internally that DSP does not get
>>> interrupts from all GPTs.
>>> Ref: http://focus.ti.com/pdfs/wtbu/SWPU114Q_PrelimFinal_EPDF_03_05_2009.pdf
>>> page 1753 ->  only mentioned these timers can generate interrupts for
>>> DSP, and hence for BIOS's usage.
>>
>> OK, now that part makes sense.
>
> This issue will be even worse on OMAP4 with the CortexM3 (aka Ducati),
> because several IPs like GPIO or GPTIMER will have different IRQ /
> functionality / power partitioning depending of the instance.
> One of the proposed solution we considered, at least for the GPTIMERs,
> was to add an extra API that can allow to request a timer based on the
> needed capabilities and not based on index.
>
> We can easily encode in each GPTIMER HWMOD the specificity of an
> instance like (HAS_DSP_IRQ, HAS_IPU_IRQ, HAS_PWM, IN_WKUP_DOMAIN,
> IN_AUDIO_DOMAIN...).
> Driver can then use a request_timer_per_functionalies(HAS_DSP_IRQ |
> HAS_IPU_IRQ...).
> It will allow driver to be much more independent of the current IP
> implementation for an OMAP version.
>
> Any thoughts?

Yes, this sounds much better.  It makes a lot more sense than
hard-coding specific GPT numbers.

Kevin