* [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4
@ 2010-06-03 0:26 Richard Henderson
2010-06-03 0:26 ` [Qemu-devel] [PATCH 1/2] tcg: Add TYPE parameter to tcg_out_mov Richard Henderson
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Richard Henderson @ 2010-06-03 0:26 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
The tcg_out_mov patch you've seen before, but now contains a
TCG_TYPE_REG that should address the concerns you had with
the changes to the sparc port. It's also been updated to HEAD
to reflect the changes in tcg/i386.
The second patch is new.
r~
Richard Henderson (2):
tcg: Add TYPE parameter to tcg_out_mov.
tcg: Make some tcg-target.c routines static.
tcg/arm/tcg-target.c | 6 ++--
tcg/hppa/tcg-target.c | 42 +++++++++++++++++++-------------------
tcg/i386/tcg-target.c | 40 ++++++++++++++++++------------------
tcg/ia64/tcg-target.c | 7 +++--
tcg/mips/tcg-target.c | 32 ++++++++++++++--------------
tcg/ppc/tcg-target.c | 52 +++++++++++++++++++++++-----------------------
tcg/ppc64/tcg-target.c | 14 ++++++------
tcg/s390/tcg-target.c | 6 ++--
tcg/sparc/tcg-target.c | 14 ++++++------
tcg/tcg.c | 14 +++++++-----
tcg/tcg.h | 14 ++++++++----
tcg/x86_64/tcg-target.c | 49 ++++++++++++++++++--------------------------
12 files changed, 144 insertions(+), 146 deletions(-)
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 1/2] tcg: Add TYPE parameter to tcg_out_mov.
2010-06-03 0:26 [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 Richard Henderson
@ 2010-06-03 0:26 ` Richard Henderson
2010-06-04 19:19 ` Blue Swirl
2010-06-03 0:26 ` [Qemu-devel] [PATCH 2/2] tcg: Make some tcg-target.c routines static Richard Henderson
` (3 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Richard Henderson @ 2010-06-03 0:26 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64
to perform the move at the proper width, which may elide a REX prefix.
Introduce a TCG_TYPE_REG enumerator to represent the "native width"
of the host register, and to distinguish the usage from "pointer data"
as represented by the existing TCG_TYPE_PTR.
Update all targets to match.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/arm/tcg-target.c | 2 +-
tcg/hppa/tcg-target.c | 38 ++++++++++++++++++------------------
tcg/i386/tcg-target.c | 36 +++++++++++++++++-----------------
tcg/ia64/tcg-target.c | 3 +-
tcg/mips/tcg-target.c | 28 +++++++++++++-------------
tcg/ppc/tcg-target.c | 48 +++++++++++++++++++++++-----------------------
tcg/ppc64/tcg-target.c | 10 ++++----
tcg/s390/tcg-target.c | 2 +-
tcg/sparc/tcg-target.c | 10 ++++----
tcg/tcg.c | 12 +++++-----
tcg/tcg.h | 11 ++++++++-
tcg/x86_64/tcg-target.c | 45 +++++++++++++++++--------------------------
12 files changed, 122 insertions(+), 123 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 8d23f47..b3169a9 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1798,7 +1798,7 @@ static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
}
}
-static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
+static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
{
tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
}
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 558c21f..a5f2162 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -338,7 +338,7 @@ static int tcg_target_const_match(tcg_target_long val,
/* supplied by libgcc */
extern void *__canonicalize_funcptr_for_compare(void *);
-static void tcg_out_mov(TCGContext *s, int ret, int arg)
+static void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
{
/* PA1.1 defines COPY as OR r,0,t; PA2.0 defines COPY as LDO 0(r),t
but hppa-dis.c is unaware of this definition */
@@ -498,7 +498,7 @@ static void tcg_out_ori(TCGContext *s, int ret, int arg, tcg_target_ulong m)
}
assert(bs1 == 32 || (1ul << bs1) > m);
- tcg_out_mov(s, ret, arg);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, arg);
tcg_out32(s, INSN_DEPI | INSN_R2(ret) | INSN_IM5(-1)
| INSN_SHDEP_CP(31 - bs0) | INSN_DEP_LEN(bs1 - bs0));
}
@@ -528,7 +528,7 @@ static void tcg_out_andi(TCGContext *s, int ret, int arg, tcg_target_ulong m)
if (ls1 == 32) {
tcg_out_extr(s, ret, arg, 0, ls0, 0);
} else {
- tcg_out_mov(s, ret, arg);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, arg);
tcg_out32(s, INSN_DEPI | INSN_R2(ret) | INSN_IM5(0)
| INSN_SHDEP_CP(31 - ls0) | INSN_DEP_LEN(ls1 - ls0));
}
@@ -608,7 +608,7 @@ static void tcg_out_rotr(TCGContext *s, int ret, int arg, int creg)
static void tcg_out_bswap16(TCGContext *s, int ret, int arg, int sign)
{
if (ret != arg) {
- tcg_out_mov(s, ret, arg); /* arg = xxAB */
+ tcg_out_mov(s, TCG_TYPE_I32, ret, arg); /* arg = xxAB */
}
tcg_out_dep(s, ret, ret, 16, 8); /* ret = xBAB */
tcg_out_extr(s, ret, ret, 8, 16, sign); /* ret = ..BA */
@@ -638,7 +638,7 @@ static void tcg_out_call(TCGContext *s, void *func)
tcg_out32(s, INSN_LDIL | INSN_R2(TCG_REG_R20) | reassemble_21(hi));
tcg_out32(s, INSN_BLE_SR4 | INSN_R2(TCG_REG_R20)
| reassemble_17(lo >> 2));
- tcg_out_mov(s, TCG_REG_RP, TCG_REG_R31);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_RP, TCG_REG_R31);
}
}
@@ -685,7 +685,7 @@ static void tcg_out_add2(TCGContext *s, int destl, int desth,
}
tcg_out_arith(s, desth, ah, bh, INSN_ADDC);
- tcg_out_mov(s, destl, tmp);
+ tcg_out_mov(s, TCG_TYPE_I32, destl, tmp);
}
static void tcg_out_sub2(TCGContext *s, int destl, int desth, int al, int ah,
@@ -706,7 +706,7 @@ static void tcg_out_sub2(TCGContext *s, int destl, int desth, int al, int ah,
}
tcg_out_arith(s, desth, ah, bh, INSN_SUBB);
- tcg_out_mov(s, destl, tmp);
+ tcg_out_mov(s, TCG_TYPE_I32, destl, tmp);
}
static void tcg_out_branch(TCGContext *s, int label_index, int nul)
@@ -869,7 +869,7 @@ static void tcg_out_setcond2(TCGContext *s, int cond, TCGArg ret,
break;
}
- tcg_out_mov(s, ret, scratch);
+ tcg_out_mov(s, TCG_TYPE_I32, ret, scratch);
}
#if defined(CONFIG_SOFTMMU)
@@ -1048,9 +1048,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
tcg_out_label(s, lab1, (tcg_target_long)s->code_ptr);
argreg = TCG_REG_R26;
- tcg_out_mov(s, argreg--, addrlo_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, argreg--, addrlo_reg);
if (TARGET_LONG_BITS == 64) {
- tcg_out_mov(s, argreg--, addrhi_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, argreg--, addrhi_reg);
}
tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
@@ -1071,11 +1071,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
break;
case 2:
case 2 | 4:
- tcg_out_mov(s, datalo_reg, TCG_REG_RET0);
+ tcg_out_mov(s, TCG_TYPE_I32, datalo_reg, TCG_REG_RET0);
break;
case 3:
- tcg_out_mov(s, datahi_reg, TCG_REG_RET0);
- tcg_out_mov(s, datalo_reg, TCG_REG_RET1);
+ tcg_out_mov(s, TCG_TYPE_I32, datahi_reg, TCG_REG_RET0);
+ tcg_out_mov(s, TCG_TYPE_I32, datalo_reg, TCG_REG_RET1);
break;
default:
tcg_abort();
@@ -1167,9 +1167,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_out_label(s, lab1, (tcg_target_long)s->code_ptr);
argreg = TCG_REG_R26;
- tcg_out_mov(s, argreg--, addrlo_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, argreg--, addrlo_reg);
if (TARGET_LONG_BITS == 64) {
- tcg_out_mov(s, argreg--, addrhi_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, argreg--, addrhi_reg);
}
switch(opc) {
@@ -1182,7 +1182,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
break;
case 2:
- tcg_out_mov(s, argreg--, datalo_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, argreg--, datalo_reg);
tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
break;
case 3:
@@ -1196,8 +1196,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
argreg = TCG_REG_R20;
tcg_out_movi(s, TCG_TYPE_I32, argreg, mem_index);
}
- tcg_out_mov(s, TCG_REG_R23, datahi_reg);
- tcg_out_mov(s, TCG_REG_R24, datalo_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R23, datahi_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R24, datalo_reg);
tcg_out_st(s, TCG_TYPE_I32, argreg, TCG_REG_SP,
TCG_TARGET_CALL_STACK_OFFSET - 4);
break;
@@ -1637,7 +1637,7 @@ void tcg_target_qemu_prologue(TCGContext *s)
/* Jump to TB, and adjust R18 to be the return address. */
tcg_out32(s, INSN_BLE_SR4 | INSN_R2(TCG_REG_R26));
- tcg_out_mov(s, TCG_REG_R18, TCG_REG_R31);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R18, TCG_REG_R31);
/* Restore callee saved registers. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_RP, TCG_REG_SP, -frame_size - 20);
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 3600c35..8745ad1 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -348,7 +348,7 @@ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3), dest, src);
}
-static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
+static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
{
if (arg != ret) {
tcg_out_modrm(s, OPC_MOVL_GvEv, ret, arg);
@@ -733,8 +733,8 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
const int r0 = TCG_REG_EAX;
const int r1 = TCG_REG_EDX;
- tcg_out_mov(s, r1, addrlo);
- tcg_out_mov(s, r0, addrlo);
+ tcg_out_mov(s, TCG_TYPE_I32, r1, addrlo);
+ tcg_out_mov(s, TCG_TYPE_I32, r0, addrlo);
tcg_out_shifti(s, SHIFT_SHR, r1, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
@@ -748,7 +748,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
/* cmp 0(r1), r0 */
tcg_out_modrm_offset(s, OPC_CMP_GvEv, r0, r1, 0);
- tcg_out_mov(s, r0, addrlo);
+ tcg_out_mov(s, TCG_TYPE_I32, r0, addrlo);
/* jne label1 */
tcg_out8(s, OPC_JCC_short + JCC_JNE);
@@ -881,7 +881,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
/* EAX is already loaded. */
arg_idx = 1;
if (TARGET_LONG_BITS == 64) {
- tcg_out_mov(s, tcg_target_call_iarg_regs[arg_idx++],
+ tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx++],
args[addrlo_idx + 1]);
}
tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx],
@@ -903,16 +903,16 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
break;
case 2:
default:
- tcg_out_mov(s, data_reg, TCG_REG_EAX);
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
break;
case 3:
if (data_reg == TCG_REG_EDX) {
/* xchg %edx, %eax */
tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX);
- tcg_out_mov(s, data_reg2, TCG_REG_EAX);
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EAX);
} else {
- tcg_out_mov(s, data_reg, TCG_REG_EAX);
- tcg_out_mov(s, data_reg2, TCG_REG_EDX);
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EDX);
}
break;
}
@@ -945,7 +945,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
break;
case 1:
if (bswap) {
- tcg_out_mov(s, scratch, datalo);
+ tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
tcg_out_rolw_8(s, scratch);
datalo = scratch;
}
@@ -955,7 +955,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
break;
case 2:
if (bswap) {
- tcg_out_mov(s, scratch, datalo);
+ tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
tcg_out_bswap32(s, scratch);
datalo = scratch;
}
@@ -963,10 +963,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
break;
case 3:
if (bswap) {
- tcg_out_mov(s, scratch, datahi);
+ tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi);
tcg_out_bswap32(s, scratch);
tcg_out_st(s, TCG_TYPE_I32, scratch, base, ofs);
- tcg_out_mov(s, scratch, datalo);
+ tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
tcg_out_bswap32(s, scratch);
tcg_out_st(s, TCG_TYPE_I32, scratch, base, ofs + 4);
} else {
@@ -1022,9 +1022,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
/* XXX: move that code at the end of the TB */
if (TARGET_LONG_BITS == 32) {
- tcg_out_mov(s, TCG_REG_EDX, data_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_EDX, data_reg);
if (opc == 3) {
- tcg_out_mov(s, TCG_REG_ECX, data_reg2);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_ECX, data_reg2);
tcg_out_pushi(s, mem_index);
stack_adjust = 4;
} else {
@@ -1033,13 +1033,13 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
}
} else {
if (opc == 3) {
- tcg_out_mov(s, TCG_REG_EDX, args[addrlo_idx + 1]);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_EDX, args[addrlo_idx + 1]);
tcg_out_pushi(s, mem_index);
tcg_out_push(s, data_reg2);
tcg_out_push(s, data_reg);
stack_adjust = 12;
} else {
- tcg_out_mov(s, TCG_REG_EDX, args[addrlo_idx + 1]);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_EDX, args[addrlo_idx + 1]);
switch(opc) {
case 0:
tcg_out_ext8u(s, TCG_REG_ECX, data_reg);
@@ -1048,7 +1048,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_out_ext16u(s, TCG_REG_ECX, data_reg);
break;
case 2:
- tcg_out_mov(s, TCG_REG_ECX, data_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_ECX, data_reg);
break;
}
tcg_out_pushi(s, mem_index);
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 905f48b..0d275e9 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -827,7 +827,8 @@ static inline void tcg_out_bundle(TCGContext *s, int template,
s->code_ptr += 16;
}
-static inline void tcg_out_mov(TCGContext *s, TCGArg ret, TCGArg arg)
+static inline void tcg_out_mov(TCGContext *s, TCGType type,
+ TCGArg ret, TCGArg arg)
{
tcg_out_bundle(s, mmI,
tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index f38eb28..8d9c12f 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -377,7 +377,7 @@ static inline void tcg_out_nop(TCGContext *s)
tcg_out32(s, 0);
}
-static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
+static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
{
tcg_out_opc_reg(s, OPC_ADDU, ret, arg, TCG_REG_ZERO);
}
@@ -849,9 +849,9 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
/* slow path */
sp_args = TCG_REG_A0;
- tcg_out_mov(s, sp_args++, addr_reg1);
+ tcg_out_mov(s, TCG_TYPE_I32, sp_args++, addr_reg1);
# if TARGET_LONG_BITS == 64
- tcg_out_mov(s, sp_args++, addr_reg2);
+ tcg_out_mov(s, TCG_TYPE_I32, sp_args++, addr_reg2);
# endif
tcg_out_movi(s, TCG_TYPE_I32, sp_args++, mem_index);
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_T9, (tcg_target_long)qemu_ld_helpers[s_bits]);
@@ -872,11 +872,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
tcg_out_ext16s(s, data_reg1, TCG_REG_V0);
break;
case 2:
- tcg_out_mov(s, data_reg1, TCG_REG_V0);
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg1, TCG_REG_V0);
break;
case 3:
- tcg_out_mov(s, data_reg2, TCG_REG_V1);
- tcg_out_mov(s, data_reg1, TCG_REG_V0);
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_V1);
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg1, TCG_REG_V0);
break;
default:
tcg_abort();
@@ -1035,9 +1035,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
/* slow path */
sp_args = TCG_REG_A0;
- tcg_out_mov(s, sp_args++, addr_reg1);
+ tcg_out_mov(s, TCG_TYPE_I32, sp_args++, addr_reg1);
# if TARGET_LONG_BITS == 64
- tcg_out_mov(s, sp_args++, addr_reg2);
+ tcg_out_mov(s, TCG_TYPE_I32, sp_args++, addr_reg2);
# endif
switch(opc) {
case 0:
@@ -1047,12 +1047,12 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_out_opc_imm(s, OPC_ANDI, sp_args++, data_reg1, 0xffff);
break;
case 2:
- tcg_out_mov(s, sp_args++, data_reg1);
+ tcg_out_mov(s, TCG_TYPE_I32, sp_args++, data_reg1);
break;
case 3:
sp_args = (sp_args + 1) & ~1;
- tcg_out_mov(s, sp_args++, data_reg1);
- tcg_out_mov(s, sp_args++, data_reg2);
+ tcg_out_mov(s, TCG_TYPE_I32, sp_args++, data_reg1);
+ tcg_out_mov(s, TCG_TYPE_I32, sp_args++, data_reg2);
break;
default:
tcg_abort();
@@ -1165,7 +1165,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_i32:
- tcg_out_mov(s, args[0], args[1]);
+ tcg_out_mov(s, TCG_TYPE_I32, args[0], args[1]);
break;
case INDEX_op_movi_i32:
tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
@@ -1216,7 +1216,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_reg(s, OPC_ADDU, args[1], args[3], args[5]);
}
tcg_out_opc_reg(s, OPC_ADDU, args[1], args[1], TCG_REG_T0);
- tcg_out_mov(s, args[0], TCG_REG_AT);
+ tcg_out_mov(s, TCG_TYPE_I32, args[0], TCG_REG_AT);
break;
case INDEX_op_sub_i32:
if (const_args[2]) {
@@ -1238,7 +1238,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_opc_reg(s, OPC_SUBU, args[1], args[3], args[5]);
}
tcg_out_opc_reg(s, OPC_SUBU, args[1], args[1], TCG_REG_T0);
- tcg_out_mov(s, args[0], TCG_REG_AT);
+ tcg_out_mov(s, TCG_TYPE_I32, args[0], TCG_REG_AT);
break;
case INDEX_op_mul_i32:
tcg_out_opc_reg(s, OPC_MULT, 0, args[1], args[2]);
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 2b85928..ce078e4 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -437,7 +437,7 @@ static const uint32_t tcg_to_bc[10] = {
[TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
};
-static void tcg_out_mov(TCGContext *s, int ret, int arg)
+static void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
{
tcg_out32 (s, OR | SAB (arg, ret, arg));
}
@@ -591,11 +591,11 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
/* slow path */
#if TARGET_LONG_BITS == 32
- tcg_out_mov (s, 3, addr_reg);
+ tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg);
tcg_out_movi (s, TCG_TYPE_I32, 4, mem_index);
#else
- tcg_out_mov (s, 3, addr_reg2);
- tcg_out_mov (s, 4, addr_reg);
+ tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2);
+ tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg);
tcg_out_movi (s, TCG_TYPE_I32, 5, mem_index);
#endif
@@ -611,23 +611,23 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
case 1:
case 2:
if (data_reg != 3)
- tcg_out_mov (s, data_reg, 3);
+ tcg_out_mov (s, TCG_TYPE_I32, data_reg, 3);
break;
case 3:
if (data_reg == 3) {
if (data_reg2 == 4) {
- tcg_out_mov (s, 0, 4);
- tcg_out_mov (s, 4, 3);
- tcg_out_mov (s, 3, 0);
+ tcg_out_mov (s, TCG_TYPE_I32, 0, 4);
+ tcg_out_mov (s, TCG_TYPE_I32, 4, 3);
+ tcg_out_mov (s, TCG_TYPE_I32, 3, 0);
}
else {
- tcg_out_mov (s, data_reg2, 3);
- tcg_out_mov (s, 3, 4);
+ tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
+ tcg_out_mov (s, TCG_TYPE_I32, 3, 4);
}
}
else {
- if (data_reg != 4) tcg_out_mov (s, data_reg, 4);
- if (data_reg2 != 3) tcg_out_mov (s, data_reg2, 3);
+ if (data_reg != 4) tcg_out_mov (s, TCG_TYPE_I32, data_reg, 4);
+ if (data_reg2 != 3) tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3);
}
break;
}
@@ -705,7 +705,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
if (r0 == data_reg2) {
tcg_out32 (s, LWZ | RT (0) | RA (r0));
tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
- tcg_out_mov (s, data_reg2, 0);
+ tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 0);
}
else {
tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
@@ -787,11 +787,11 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
/* slow path */
#if TARGET_LONG_BITS == 32
- tcg_out_mov (s, 3, addr_reg);
+ tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg);
ir = 4;
#else
- tcg_out_mov (s, 3, addr_reg2);
- tcg_out_mov (s, 4, addr_reg);
+ tcg_out_mov (s, TCG_TYPE_I32, 3, addr_reg2);
+ tcg_out_mov (s, TCG_TYPE_I32, 4, addr_reg);
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
ir = 5;
#else
@@ -817,14 +817,14 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
| ME (31)));
break;
case 2:
- tcg_out_mov (s, ir, data_reg);
+ tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
break;
case 3:
#ifdef TCG_TARGET_CALL_ALIGN_ARGS
ir = 5;
#endif
- tcg_out_mov (s, ir++, data_reg2);
- tcg_out_mov (s, ir, data_reg);
+ tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2);
+ tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg);
break;
}
ir++;
@@ -1526,7 +1526,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
if (args[0] == args[2] || args[0] == args[3]) {
tcg_out32 (s, MULLW | TAB (0, args[2], args[3]));
tcg_out32 (s, MULHWU | TAB (args[1], args[2], args[3]));
- tcg_out_mov (s, args[0], 0);
+ tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
}
else {
tcg_out32 (s, MULLW | TAB (args[0], args[2], args[3]));
@@ -1584,7 +1584,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_rotr_i32:
if (const_args[2]) {
if (!args[2]) {
- tcg_out_mov (s, args[0], args[1]);
+ tcg_out_mov (s, TCG_TYPE_I32, args[0], args[1]);
}
else {
tcg_out32 (s, RLWINM
@@ -1612,7 +1612,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
if (args[0] == args[3] || args[0] == args[5]) {
tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5]));
- tcg_out_mov (s, args[0], 0);
+ tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
}
else {
tcg_out32 (s, ADDC | TAB (args[0], args[2], args[4]));
@@ -1623,7 +1623,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
if (args[0] == args[3] || args[0] == args[5]) {
tcg_out32 (s, SUBFC | TAB (0, args[4], args[2]));
tcg_out32 (s, SUBFE | TAB (args[1], args[5], args[3]));
- tcg_out_mov (s, args[0], 0);
+ tcg_out_mov (s, TCG_TYPE_I32, args[0], 0);
}
else {
tcg_out32 (s, SUBFC | TAB (args[0], args[4], args[2]));
@@ -1782,7 +1782,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
);
if (!a0) {
- tcg_out_mov (s, args[0], a0);
+ tcg_out_mov (s, TCG_TYPE_I32, args[0], a0);
}
}
break;
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 0b6c61f..2d436a5 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -435,7 +435,7 @@ static const uint32_t tcg_to_bc[10] = {
[TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
};
-static void tcg_out_mov (TCGContext *s, int ret, int arg)
+static void tcg_out_mov (TCGContext *s, TCGType type, int ret, int arg)
{
tcg_out32 (s, OR | SAB (arg, ret, arg));
}
@@ -644,7 +644,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
#endif
/* slow path */
- tcg_out_mov (s, 3, addr_reg);
+ tcg_out_mov (s, TCG_TYPE_I64, 3, addr_reg);
tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
@@ -664,7 +664,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
case 2:
case 3:
if (data_reg != 3)
- tcg_out_mov (s, data_reg, 3);
+ tcg_out_mov (s, TCG_TYPE_I64, data_reg, 3);
break;
}
label2_ptr = s->code_ptr;
@@ -746,7 +746,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0));
#else
if (bswap) {
- tcg_out_movi32 (s, 0, 4);
+ tcg_out_movi32 (s, TCG_TYPE_I64, 0, 4);
tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
tcg_out32 (s, LWBRX | RT ( r1) | RA (r0));
tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
@@ -790,7 +790,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
#endif
/* slow path */
- tcg_out_mov (s, 3, addr_reg);
+ tcg_out_mov (s, TCG_TYPE_I64, 3, addr_reg);
tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc)));
tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 265194a..06b6db3 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -94,7 +94,7 @@ void tcg_target_qemu_prologue(TCGContext *s)
/* gets called with KVM */
}
-static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
+static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
{
tcg_abort();
}
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index e460d44..9f970cd 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -304,7 +304,7 @@ static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
| (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
}
-static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
+static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
{
tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
}
@@ -795,7 +795,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
tcg_out32(s, 0);
/* mov (delay slot) */
- tcg_out_mov(s, arg0, addr_reg);
+ tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
/* mov */
tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
@@ -845,7 +845,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
case 3:
default:
/* mov */
- tcg_out_mov(s, data_reg, arg0);
+ tcg_out_mov(s, TCG_TYPE_REG, data_reg, arg0);
break;
}
@@ -1007,10 +1007,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_out32(s, 0);
/* mov (delay slot) */
- tcg_out_mov(s, arg0, addr_reg);
+ tcg_out_mov(s, TCG_TYPE_PTR, arg0, addr_reg);
/* mov */
- tcg_out_mov(s, arg1, data_reg);
+ tcg_out_mov(s, TCG_TYPE_REG, arg1, data_reg);
/* mov */
tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 880e7ce..32f9e17 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1547,7 +1547,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
reg = tcg_reg_alloc(s, arg_ct->u.regs, s->reserved_regs);
}
if (ts->reg != reg) {
- tcg_out_mov(s, reg, ts->reg);
+ tcg_out_mov(s, ots->type, reg, ts->reg);
}
}
} else if (ts->val_type == TEMP_VAL_MEM) {
@@ -1652,7 +1652,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
/* allocate a new register matching the constraint
and move the temporary register into it */
reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
- tcg_out_mov(s, reg, ts->reg);
+ tcg_out_mov(s, ts->type, reg, ts->reg);
}
new_args[i] = reg;
const_args[i] = 0;
@@ -1734,7 +1734,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
ts = &s->temps[args[i]];
reg = new_args[i];
if (ts->fixed_reg && ts->reg != reg) {
- tcg_out_mov(s, ts->reg, reg);
+ tcg_out_mov(s, ts->type, ts->reg, reg);
}
}
}
@@ -1820,7 +1820,7 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
tcg_reg_free(s, reg);
if (ts->val_type == TEMP_VAL_REG) {
if (ts->reg != reg) {
- tcg_out_mov(s, reg, ts->reg);
+ tcg_out_mov(s, ts->type, reg, ts->reg);
}
} else if (ts->val_type == TEMP_VAL_MEM) {
tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
@@ -1849,7 +1849,7 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
reg = ts->reg;
if (!tcg_regset_test_reg(arg_ct->u.regs, reg)) {
reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
- tcg_out_mov(s, reg, ts->reg);
+ tcg_out_mov(s, ts->type, reg, ts->reg);
}
func_arg = reg;
tcg_regset_set_reg(allocated_regs, reg);
@@ -1908,7 +1908,7 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
assert(s->reg_to_temp[reg] == -1);
if (ts->fixed_reg) {
if (ts->reg != reg) {
- tcg_out_mov(s, ts->reg, reg);
+ tcg_out_mov(s, ts->type, ts->reg, reg);
}
} else {
if (ts->val_type == TEMP_VAL_REG)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 5853823..d6cb9e7 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -101,11 +101,18 @@ typedef enum TCGType {
TCG_TYPE_I64,
TCG_TYPE_COUNT, /* number of different types */
+ /* An alias for the size of the host register. */
#if TCG_TARGET_REG_BITS == 32
- TCG_TYPE_PTR = TCG_TYPE_I32,
+ TCG_TYPE_REG = TCG_TYPE_I32,
#else
- TCG_TYPE_PTR = TCG_TYPE_I64,
+ TCG_TYPE_REG = TCG_TYPE_I64,
#endif
+
+ /* An alias for the size of the native pointer. We don't currently
+ support any hosts with 64-bit registers and 32-bit pointers. */
+ TCG_TYPE_PTR = TCG_TYPE_REG,
+
+ /* An alias for the size of the target "long", aka register. */
#if TARGET_LONG_BITS == 64
TCG_TYPE_TL = TCG_TYPE_I64,
#else
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
index 3892f75..9844a57 100644
--- a/tcg/x86_64/tcg-target.c
+++ b/tcg/x86_64/tcg-target.c
@@ -354,9 +354,10 @@ static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
}
#endif
-static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
+static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
{
- tcg_out_modrm(s, 0x8b | P_REXW, ret, arg);
+ int rexw = (type == TCG_TYPE_I64 ? P_REXW : 0);
+ tcg_out_modrm(s, 0x8b | rexw, ret, arg);
}
static inline void tcg_out_movi(TCGContext *s, TCGType type,
@@ -577,11 +578,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
rexw = P_REXW;
#endif
#if defined(CONFIG_SOFTMMU)
- /* mov */
- tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
-
- /* mov */
- tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
+ tcg_out_mov(s, TCG_TYPE_TL, r1, addr_reg);
+ tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
@@ -599,8 +597,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
/* cmp 0(r1), r0 */
tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
- /* mov */
- tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
+ tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
/* je label1 */
tcg_out8(s, 0x70 + JCC_JE);
@@ -634,11 +631,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
break;
case 2:
default:
- /* movl */
- tcg_out_modrm(s, 0x8b, data_reg, TCG_REG_RAX);
+ tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_RAX);
break;
case 3:
- tcg_out_mov(s, data_reg, TCG_REG_RAX);
+ tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);
break;
}
@@ -772,11 +768,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
rexw = P_REXW;
#endif
#if defined(CONFIG_SOFTMMU)
- /* mov */
- tcg_out_modrm(s, 0x8b | rexw, r1, addr_reg);
-
- /* mov */
- tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
+ tcg_out_mov(s, TCG_TYPE_TL, r1, addr_reg);
+ tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
@@ -793,10 +786,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
/* cmp 0(r1), r0 */
tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
-
- /* mov */
- tcg_out_modrm(s, 0x8b | rexw, r0, addr_reg);
-
+
+ tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
+
/* je label1 */
tcg_out8(s, 0x70 + JCC_JE);
label1_ptr = s->code_ptr;
@@ -813,12 +805,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
break;
case 2:
- /* movl */
- tcg_out_modrm(s, 0x8b, TCG_REG_RSI, data_reg);
+ tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_RSI, data_reg);
break;
default:
case 3:
- tcg_out_mov(s, TCG_REG_RSI, data_reg);
+ tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_RSI, data_reg);
break;
}
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
@@ -863,7 +854,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
break;
case 1:
if (bswap) {
- tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
+ tcg_out_mov(s, TCG_TYPE_I32, r1, data_reg);
tcg_out8(s, 0x66); /* rolw $8, %ecx */
tcg_out_modrm(s, 0xc1, 0, r1);
tcg_out8(s, 8);
@@ -875,7 +866,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
break;
case 2:
if (bswap) {
- tcg_out_modrm(s, 0x8b, r1, data_reg); /* movl */
+ tcg_out_mov(s, TCG_TYPE_I32, r1, data_reg);
/* bswap data_reg */
tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
data_reg = r1;
@@ -885,7 +876,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
break;
case 3:
if (bswap) {
- tcg_out_mov(s, r1, data_reg);
+ tcg_out_mov(s, TCG_TYPE_I64, r1, data_reg);
/* bswap data_reg */
tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
data_reg = r1;
--
1.7.0.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 2/2] tcg: Make some tcg-target.c routines static.
2010-06-03 0:26 [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 Richard Henderson
2010-06-03 0:26 ` [Qemu-devel] [PATCH 1/2] tcg: Add TYPE parameter to tcg_out_mov Richard Henderson
@ 2010-06-03 0:26 ` Richard Henderson
2010-06-03 9:23 ` [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 malc
` (2 subsequent siblings)
4 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2010-06-03 0:26 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
Both tcg_target_init and tcg_target_qemu_prologue
are unused outside of tcg.c.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/arm/tcg-target.c | 4 ++--
tcg/hppa/tcg-target.c | 4 ++--
tcg/i386/tcg-target.c | 4 ++--
tcg/ia64/tcg-target.c | 4 ++--
tcg/mips/tcg-target.c | 4 ++--
tcg/ppc/tcg-target.c | 4 ++--
tcg/ppc64/tcg-target.c | 4 ++--
tcg/s390/tcg-target.c | 4 ++--
tcg/sparc/tcg-target.c | 4 ++--
tcg/tcg.c | 2 ++
tcg/tcg.h | 3 ---
tcg/x86_64/tcg-target.c | 4 ++--
12 files changed, 22 insertions(+), 23 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index b3169a9..a3af5b2 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1746,7 +1746,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ -1 },
};
-void tcg_target_init(TCGContext *s)
+static void tcg_target_init(TCGContext *s)
{
#if !defined(CONFIG_USER_ONLY)
/* fail safe */
@@ -1809,7 +1809,7 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,
tcg_out_movi32(s, COND_AL, ret, arg);
}
-void tcg_target_qemu_prologue(TCGContext *s)
+static void tcg_target_qemu_prologue(TCGContext *s)
{
/* There is no need to save r7, it is used to store the address
of the env structure and is not modified by GCC. */
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index a5f2162..7f4653e 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -1600,7 +1600,7 @@ static int tcg_target_callee_save_regs[] = {
TCG_REG_R18
};
-void tcg_target_qemu_prologue(TCGContext *s)
+static void tcg_target_qemu_prologue(TCGContext *s)
{
int frame_size, i;
@@ -1652,7 +1652,7 @@ void tcg_target_qemu_prologue(TCGContext *s)
TCG_REG_SP, -frame_size, INSN_LDWM);
}
-void tcg_target_init(TCGContext *s)
+static void tcg_target_init(TCGContext *s)
{
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 8745ad1..147ba17 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -1430,7 +1430,7 @@ static int tcg_target_callee_save_regs[] = {
};
/* Generate global QEMU prologue and epilogue code */
-void tcg_target_qemu_prologue(TCGContext *s)
+static void tcg_target_qemu_prologue(TCGContext *s)
{
int i, frame_size, push_size, stack_addend;
@@ -1458,7 +1458,7 @@ void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_opc(s, OPC_RET);
}
-void tcg_target_init(TCGContext *s)
+static void tcg_target_init(TCGContext *s)
{
#if !defined(CONFIG_USER_ONLY)
/* fail safe */
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 0d275e9..a0f3877 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -2266,7 +2266,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
};
/* Generate global QEMU prologue and epilogue code */
-void tcg_target_qemu_prologue(TCGContext *s)
+static void tcg_target_qemu_prologue(TCGContext *s)
{
int frame_size;
@@ -2321,7 +2321,7 @@ void tcg_target_qemu_prologue(TCGContext *s)
TCG_REG_B0));
}
-void tcg_target_init(TCGContext *s)
+static void tcg_target_init(TCGContext *s)
{
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
0xffffffffffffffffull);
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 8d9c12f..2af7a2e 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -1466,7 +1466,7 @@ static int tcg_target_callee_save_regs[] = {
};
/* Generate global QEMU prologue and epilogue code */
-void tcg_target_qemu_prologue(TCGContext *s)
+static void tcg_target_qemu_prologue(TCGContext *s)
{
int i, frame_size;
@@ -1498,7 +1498,7 @@ void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_addi(s, TCG_REG_SP, frame_size);
}
-void tcg_target_init(TCGContext *s)
+static void tcg_target_init(TCGContext *s)
{
tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff);
tcg_regset_set(tcg_target_call_clobber_regs,
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index ce078e4..2e5bb9f 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -900,7 +900,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
#endif
}
-void tcg_target_qemu_prologue (TCGContext *s)
+static void tcg_target_qemu_prologue (TCGContext *s)
{
int i, frame_size;
@@ -1885,7 +1885,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ -1 },
};
-void tcg_target_init(TCGContext *s)
+static void tcg_target_init(TCGContext *s)
{
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 2d436a5..0483d6b 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -860,7 +860,7 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
#endif
}
-void tcg_target_qemu_prologue (TCGContext *s)
+static void tcg_target_qemu_prologue (TCGContext *s)
{
int i, frame_size;
#ifndef __APPLE__
@@ -1663,7 +1663,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ -1 },
};
-void tcg_target_init (TCGContext *s)
+static void tcg_target_init (TCGContext *s)
{
tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 06b6db3..6f08aa4 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -84,12 +84,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_abort();
}
-void tcg_target_init(TCGContext *s)
+static void tcg_target_init(TCGContext *s)
{
/* gets called with KVM */
}
-void tcg_target_qemu_prologue(TCGContext *s)
+static void tcg_target_qemu_prologue(TCGContext *s)
{
/* gets called with KVM */
}
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 9f970cd..5f1353a 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -691,7 +691,7 @@ static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret,
#endif
/* Generate global QEMU prologue and epilogue code */
-void tcg_target_qemu_prologue(TCGContext *s)
+static void tcg_target_qemu_prologue(TCGContext *s)
{
tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
@@ -1533,7 +1533,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ -1 },
};
-void tcg_target_init(TCGContext *s)
+static void tcg_target_init(TCGContext *s)
{
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
#if TCG_TARGET_REG_BITS == 64
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 32f9e17..3368d93 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -63,6 +63,8 @@
#error GUEST_BASE not supported on this host.
#endif
+static void tcg_target_init(TCGContext *s);
+static void tcg_target_qemu_prologue(TCGContext *s);
static void patch_reloc(uint8_t *code_ptr, int type,
tcg_target_long value, tcg_target_long addend);
diff --git a/tcg/tcg.h b/tcg/tcg.h
index d6cb9e7..9134700 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -435,9 +435,6 @@ typedef struct TCGTargetOpDef {
const char *args_ct_str[TCG_MAX_OP_ARGS];
} TCGTargetOpDef;
-void tcg_target_init(TCGContext *s);
-void tcg_target_qemu_prologue(TCGContext *s);
-
#define tcg_abort() \
do {\
fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
index 9844a57..490666e 100644
--- a/tcg/x86_64/tcg-target.c
+++ b/tcg/x86_64/tcg-target.c
@@ -1279,7 +1279,7 @@ static inline void tcg_out_pop(TCGContext *s, int reg)
}
/* Generate global QEMU prologue and epilogue code */
-void tcg_target_qemu_prologue(TCGContext *s)
+static void tcg_target_qemu_prologue(TCGContext *s)
{
int i, frame_size, push_size, stack_addend;
@@ -1417,7 +1417,7 @@ static const TCGTargetOpDef x86_64_op_defs[] = {
{ -1 },
};
-void tcg_target_init(TCGContext *s)
+static void tcg_target_init(TCGContext *s)
{
#if !defined(CONFIG_USER_ONLY)
/* fail safe */
--
1.7.0.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4
2010-06-03 0:26 [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 Richard Henderson
2010-06-03 0:26 ` [Qemu-devel] [PATCH 1/2] tcg: Add TYPE parameter to tcg_out_mov Richard Henderson
2010-06-03 0:26 ` [Qemu-devel] [PATCH 2/2] tcg: Make some tcg-target.c routines static Richard Henderson
@ 2010-06-03 9:23 ` malc
2010-06-04 0:35 ` [Qemu-devel] [PATCH 0/2] tcg-i386: merge 64-bit, guest_base improvement Richard Henderson
2010-06-09 9:42 ` [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 Aurelien Jarno
4 siblings, 0 replies; 13+ messages in thread
From: malc @ 2010-06-03 9:23 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, aurelien
On Wed, 2 Jun 2010, Richard Henderson wrote:
> The tcg_out_mov patch you've seen before, but now contains a
> TCG_TYPE_REG that should address the concerns you had with
> the changes to the sparc port. It's also been updated to HEAD
> to reflect the changes in tcg/i386.
>
> The second patch is new.
>
PPC parts are fine with me.
[..snip..]
--
mailto:av1474@comtv.ru
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 0/2] tcg-i386: merge 64-bit, guest_base improvement
2010-06-03 0:26 [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 Richard Henderson
` (2 preceding siblings ...)
2010-06-03 9:23 ` [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 malc
@ 2010-06-04 0:35 ` Richard Henderson
2010-06-04 0:35 ` [Qemu-devel] [PATCH 1/2] tcg-i386: Merge 64-bit generation Richard Henderson
2010-06-04 0:35 ` [Qemu-devel] [PATCH 2/2] tcg-i386: Use segment registers to implement GUEST_BASE Richard Henderson
2010-06-09 9:42 ` [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 Aurelien Jarno
4 siblings, 2 replies; 13+ messages in thread
From: Richard Henderson @ 2010-06-04 0:35 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
This patch series is dependent on the "tcg cleanups, part 4"
patch series.
The first patch merges the 64-bit code generator with the cleaned-up
32-bit code generator. I think the result is going to be easier to
maintain than the two generators separately. I've spot-checked the
code for 32-bit at -O2; I think the compiler has done a good job
compiling away the 64-bit parts.
The second patch uses the segmentation registers to implement GUEST_BASE.
This is only a mild space-savings for 32-bit (3 bytes per guest access),
but for 64-bit it can be very helpful. Consider the new -R option for
reserving an address-space:
Reserved 0x80000000 bytes of guest address space
host mmap_min_addr=0x1000
guest_base 0x7fff74be1000
The area the OS reserved for us often turns out to be in high memory.
Before this patch, we wind up emitting
movq $large,%rax
addq %addr,%rax
The reduction by using a segment register is 11 bytes (and 2 insns)
per guest access.
r~
Richard Henderson (2):
tcg-i386: Merge 64-bit generation.
tcg-i386: Use segment registers to implement GUEST_BASE.
configure | 2 +
tcg/i386/tcg-target.c | 1276 ++++++++++++++++++++++++++++++-----------
tcg/i386/tcg-target.h | 61 ++-
tcg/x86_64/tcg-target.c | 1445 -----------------------------------------------
tcg/x86_64/tcg-target.h | 101 ----
5 files changed, 996 insertions(+), 1889 deletions(-)
delete mode 100644 tcg/x86_64/tcg-target.c
delete mode 100644 tcg/x86_64/tcg-target.h
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 1/2] tcg-i386: Merge 64-bit generation.
2010-06-04 0:35 ` [Qemu-devel] [PATCH 0/2] tcg-i386: merge 64-bit, guest_base improvement Richard Henderson
@ 2010-06-04 0:35 ` Richard Henderson
2010-06-09 22:18 ` Aurelien Jarno
2010-06-04 0:35 ` [Qemu-devel] [PATCH 2/2] tcg-i386: Use segment registers to implement GUEST_BASE Richard Henderson
1 sibling, 1 reply; 13+ messages in thread
From: Richard Henderson @ 2010-06-04 0:35 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
configure | 2 +
tcg/i386/tcg-target.c | 1158 +++++++++++++++++++++++++++-----------
tcg/i386/tcg-target.h | 61 ++-
tcg/x86_64/tcg-target.c | 1445 -----------------------------------------------
tcg/x86_64/tcg-target.h | 101 ----
5 files changed, 890 insertions(+), 1877 deletions(-)
delete mode 100644 tcg/x86_64/tcg-target.c
delete mode 100644 tcg/x86_64/tcg-target.h
diff --git a/configure b/configure
index 653c8d2..1f25dba 100755
--- a/configure
+++ b/configure
@@ -2635,6 +2635,8 @@ if test "$ARCH" = "sparc64" ; then
cflags="-I\$(SRC_PATH)/tcg/sparc $cflags"
elif test "$ARCH" = "s390x" ; then
cflags="-I\$(SRC_PATH)/tcg/s390 $cflags"
+elif test "$ARCH" = "x86_64" ; then
+ cflags="-I\$(SRC_PATH)/tcg/i386 $cflags"
else
cflags="-I\$(SRC_PATH)/tcg/\$(ARCH) $cflags"
fi
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index 147ba17..fab2a30 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -24,18 +24,33 @@
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "%eax",
- "%ecx",
- "%edx",
- "%ebx",
- "%esp",
- "%ebp",
- "%esi",
- "%edi",
+#if TCG_TARGET_REG_BITS == 64
+ "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
+ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
+#else
+ "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
+#endif
};
#endif
static const int tcg_target_reg_alloc_order[] = {
+#if TCG_TARGET_REG_BITS == 64
+ TCG_REG_RBP,
+ TCG_REG_RBX,
+ TCG_REG_R12,
+ TCG_REG_R13,
+ TCG_REG_R14,
+ TCG_REG_R15,
+ TCG_REG_R10,
+ TCG_REG_R11,
+ TCG_REG_R9,
+ TCG_REG_R8,
+ TCG_REG_RCX,
+ TCG_REG_RDX,
+ TCG_REG_RSI,
+ TCG_REG_RDI,
+ TCG_REG_RAX,
+#else
TCG_REG_EBX,
TCG_REG_ESI,
TCG_REG_EDI,
@@ -43,10 +58,28 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_ECX,
TCG_REG_EDX,
TCG_REG_EAX,
+#endif
};
-static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
-static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
+static const int tcg_target_call_iarg_regs[] = {
+#if TCG_TARGET_REG_BITS == 64
+ TCG_REG_RDI,
+ TCG_REG_RSI,
+ TCG_REG_RDX,
+ TCG_REG_RCX,
+ TCG_REG_R8,
+ TCG_REG_R9,
+#else
+ TCG_REG_EAX,
+ TCG_REG_EDX,
+ TCG_REG_ECX
+#endif
+};
+
+static const int tcg_target_call_oarg_regs[2] = {
+ TCG_REG_EAX,
+ TCG_REG_EDX
+};
static uint8_t *tb_ret_addr;
@@ -55,14 +88,15 @@ static void patch_reloc(uint8_t *code_ptr, int type,
{
value += addend;
switch(type) {
- case R_386_32:
- *(uint32_t *)code_ptr = value;
- break;
case R_386_PC32:
- *(uint32_t *)code_ptr = value - (long)code_ptr;
+ value -= (uintptr_t)code_ptr;
+ if (value != (int32_t)value) {
+ tcg_abort();
+ }
+ *(uint32_t *)code_ptr = value;
break;
case R_386_PC8:
- value -= (long)code_ptr;
+ value -= (uintptr_t)code_ptr;
if (value != (int8_t)value) {
tcg_abort();
}
@@ -76,6 +110,10 @@ static void patch_reloc(uint8_t *code_ptr, int type,
/* maximum number of register used for input function arguments */
static inline int tcg_target_get_call_iarg_regs_count(int flags)
{
+ if (TCG_TARGET_REG_BITS == 64) {
+ return 6;
+ }
+
flags &= TCG_CALL_TYPE_MASK;
switch(flags) {
case TCG_CALL_TYPE_STD:
@@ -122,20 +160,42 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
break;
case 'q':
ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xf);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_regset_set32(ct->u.regs, 0, 0xffff);
+ } else {
+ tcg_regset_set32(ct->u.regs, 0, 0xf);
+ }
break;
case 'r':
ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xff);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_regset_set32(ct->u.regs, 0, 0xffff);
+ } else {
+ tcg_regset_set32(ct->u.regs, 0, 0xff);
+ }
break;
/* qemu_ld/st address constraint */
case 'L':
ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xff);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_regset_set32(ct->u.regs, 0, 0xffff);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
+ } else {
+ tcg_regset_set32(ct->u.regs, 0, 0xff);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
+ }
+ break;
+
+ case 'e':
+ ct->ct |= TCG_CT_CONST_S32;
+ break;
+ case 'Z':
+ ct->ct |= TCG_CT_CONST_U32;
break;
+
default:
return -1;
}
@@ -148,16 +208,38 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
static inline int tcg_target_const_match(tcg_target_long val,
const TCGArgConstraint *arg_ct)
{
- int ct;
- ct = arg_ct->ct;
- if (ct & TCG_CT_CONST)
+ int ct = arg_ct->ct;
+ if (ct & TCG_CT_CONST) {
return 1;
- else
- return 0;
+ }
+ if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
+ return 1;
+ }
+ if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
+ return 1;
+ }
+ return 0;
}
+#if TCG_TARGET_REG_BITS == 64
+# define LOWREGMASK(x) ((x) & 7)
+#else
+# define LOWREGMASK(x) (x)
+#endif
+
#define P_EXT 0x100 /* 0x0f opcode prefix */
#define P_DATA16 0x200 /* 0x66 opcode prefix */
+#if TCG_TARGET_REG_BITS == 64
+# define P_ADDR32 0x400 /* 0x67 opcode prefix */
+# define P_REXW 0x800 /* Set REX.W = 1 */
+# define P_REXB_R 0x1000 /* REG field as byte register */
+# define P_REXB_RM 0x2000 /* R/M field as byte register */
+#else
+# define P_ADDR32 0
+# define P_REXW 0
+# define P_REXB_R 0
+# define P_REXB_RM 0
+#endif
#define OPC_ARITH_EvIz (0x81)
#define OPC_ARITH_EvIb (0x83)
@@ -179,9 +261,11 @@ static inline int tcg_target_const_match(tcg_target_long val,
#define OPC_MOVB_EvGv (0x88) /* stores, more or less */
#define OPC_MOVL_EvGv (0x89) /* stores, more or less */
#define OPC_MOVL_GvEv (0x8b) /* loads, more or less */
+#define OPC_MOVL_EvIz (0xc7)
#define OPC_MOVL_Iv (0xb8)
#define OPC_MOVSBL (0xbe | P_EXT)
#define OPC_MOVSWL (0xbf | P_EXT)
+#define OPC_MOVSLQ (0x63 | P_REXW)
#define OPC_MOVZBL (0xb6 | P_EXT)
#define OPC_MOVZWL (0xb7 | P_EXT)
#define OPC_POP_r32 (0x58)
@@ -189,7 +273,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
#define OPC_PUSH_Iv (0x68)
#define OPC_PUSH_Ib (0x6a)
#define OPC_RET (0xc3)
-#define OPC_SETCC (0x90 | P_EXT) /* ... plus condition code */
+#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */
#define OPC_SHIFT_1 (0xd1)
#define OPC_SHIFT_Ib (0xc1)
#define OPC_SHIFT_cl (0xd3)
@@ -226,6 +310,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
#define EXT3_IDIV 7
/* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */
+#define EXT5_INC_Ev 0
+#define EXT5_DEC_Ev 1
#define EXT5_CALLN_Ev 2
#define EXT5_JMPN_Ev 4
@@ -261,7 +347,45 @@ static const uint8_t tcg_cond_to_jcc[10] = {
[TCG_COND_GTU] = JCC_JA,
};
-static inline void tcg_out_opc(TCGContext *s, int opc)
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
+{
+ int rex;
+
+ if (opc & P_DATA16) {
+ /* We should never be asking for both 16 and 64-bit operation. */
+ assert((opc & P_REXW) == 0);
+ tcg_out8(s, 0x66);
+ }
+ if (opc & P_ADDR32) {
+ tcg_out8(s, 0x67);
+ }
+
+ rex = 0;
+ rex |= (opc & P_REXW) >> 8; /* REX.W */
+ rex |= (r & 8) >> 1; /* REX.R */
+ rex |= (x & 8) >> 2; /* REX.X */
+ rex |= (rm & 8) >> 3; /* REX.B */
+
+ /* P_REXB_{R,RM} indicates that the given register is the low byte.
+ For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
+ as otherwise the encoding indicates %[abcd]h. Note that the values
+ that are ORed in merely indicate that the REX byte must be present;
+ those bits get discarded in output. */
+ rex |= opc & (r >= 4 ? P_REXB_R : 0);
+ rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
+
+ if (rex) {
+ tcg_out8(s, (uint8_t)(rex | 0x40));
+ }
+
+ if (opc & P_EXT) {
+ tcg_out8(s, 0x0f);
+ }
+ tcg_out8(s, opc);
+}
+#else
+static void tcg_out_opc(TCGContext *s, int opc)
{
if (opc & P_DATA16) {
tcg_out8(s, 0x66);
@@ -271,36 +395,69 @@ static inline void tcg_out_opc(TCGContext *s, int opc)
}
tcg_out8(s, opc);
}
+/* Discard the register arguments to tcg_out_opc early, so as not to penalize
+ the 32-bit compilation paths. This method works with all versions of gcc,
+ whereas relying on optimization may not be able to exclude them. */
+#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc)
+#endif
-static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
+static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
{
- tcg_out_opc(s, opc);
- tcg_out8(s, 0xc0 | (r << 3) | rm);
+ tcg_out_opc(s, opc, r, rm, 0);
+ tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
}
-/* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
- We handle either RM and INDEX missing with a -1 value. */
+/* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
+ We handle either RM and INDEX missing with a negative value. In 64-bit
+ mode for absolute addresses, ~RM is the size of the immediate operand
+ that will follow the instruction. */
static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
- int index, int shift, int32_t offset)
+ int index, int shift,
+ tcg_target_long offset)
{
int mod, len;
- if (index == -1 && rm == -1) {
- /* Absolute address. */
- tcg_out_opc(s, opc);
- tcg_out8(s, (r << 3) | 5);
- tcg_out32(s, offset);
- return;
- }
+ if (index < 0 && rm < 0) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ /* Try for a rip-relative addressing mode. This has replaced
+ the 32-bit-mode absolute addressing encoding. */
+ tcg_target_long pc = (tcg_target_long)s->code_ptr + 5 + ~rm;
+ tcg_target_long disp = offset - pc;
+ if (disp == (int32_t)disp) {
+ tcg_out_opc(s, opc, r, 0, 0);
+ tcg_out8(s, (LOWREGMASK(r) << 3) | 5);
+ tcg_out32(s, disp);
+ return;
+ }
- tcg_out_opc(s, opc);
+ /* Try for an absolute address encoding. This requires the
+ use of the MODRM+SIB encoding and is therefore larger than
+ rip-relative addressing. */
+ if (offset == (int32_t)offset) {
+ tcg_out_opc(s, opc, r, 0, 0);
+ tcg_out8(s, (LOWREGMASK(r) << 3) | 4);
+ tcg_out8(s, (4 << 3) | 5);
+ tcg_out32(s, offset);
+ return;
+ }
+
+ /* ??? The memory isn't directly addressable. */
+ tcg_abort();
+ } else {
+ /* Absolute address. */
+ tcg_out_opc(s, opc, r, 0, 0);
+ tcg_out8(s, (r << 3) | 5);
+ tcg_out32(s, offset);
+ return;
+ }
+ }
/* Find the length of the immediate addend. Note that the encoding
that would be used for (%ebp) indicates absolute addressing. */
- if (rm == -1) {
+ if (rm < 0) {
mod = 0, len = 4, rm = 5;
- } else if (offset == 0 && rm != TCG_REG_EBP) {
+ } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) {
mod = 0, len = 0;
} else if (offset == (int8_t)offset) {
mod = 0x40, len = 1;
@@ -310,22 +467,25 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
/* Use a single byte MODRM format if possible. Note that the encoding
that would be used for %esp is the escape to the two byte form. */
- if (index == -1 && rm != TCG_REG_ESP) {
+ if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) {
/* Single byte MODRM format. */
- tcg_out8(s, mod | (r << 3) | rm);
+ tcg_out_opc(s, opc, r, rm, 0);
+ tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
} else {
/* Two byte MODRM+SIB format. */
/* Note that the encoding that would place %esp into the index
- field indicates no index register. */
- if (index == -1) {
+ field indicates no index register. In 64-bit mode, the REX.X
+ bit counts, so %r12 can be used as the index. */
+ if (index < 0) {
index = 4;
} else {
assert(index != TCG_REG_ESP);
}
- tcg_out8(s, mod | (r << 3) | 4);
- tcg_out8(s, (shift << 6) | (index << 3) | rm);
+ tcg_out_opc(s, opc, r, rm, index);
+ tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4);
+ tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm));
}
if (len == 1) {
@@ -335,9 +495,9 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
}
}
-/* rm == -1 means no register index */
-static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
- int32_t offset)
+/* A simplification of the above with no index or shift. */
+static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r,
+ int rm, tcg_target_long offset)
{
tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset);
}
@@ -345,58 +505,75 @@ static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */
static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
{
- tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3), dest, src);
+ /* Propagate an opcode prefix, such as P_REXW. */
+ int ext = subop & ~0x7;
+ subop &= 0x7;
+
+ tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src);
}
static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
{
if (arg != ret) {
- tcg_out_modrm(s, OPC_MOVL_GvEv, ret, arg);
+ int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
+ tcg_out_modrm(s, opc, ret, arg);
}
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- int ret, int32_t arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ int ret, tcg_target_long arg)
{
if (arg == 0) {
tgen_arithr(s, ARITH_XOR, ret, ret);
+ return;
+ } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
+ tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0);
+ tcg_out32(s, arg);
+ } else if (arg == (int32_t)arg) {
+ tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret);
+ tcg_out32(s, arg);
} else {
- tcg_out8(s, OPC_MOVL_Iv + ret);
+ tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0);
tcg_out32(s, arg);
+ tcg_out32(s, arg >> 31 >> 1);
}
}
static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
{
if (val == (int8_t)val) {
- tcg_out_opc(s, OPC_PUSH_Ib);
+ tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0);
tcg_out8(s, val);
- } else {
- tcg_out_opc(s, OPC_PUSH_Iv);
+ } else if (val == (int32_t)val) {
+ tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0);
tcg_out32(s, val);
+ } else {
+ tcg_abort();
}
}
static inline void tcg_out_push(TCGContext *s, int reg)
{
- tcg_out_opc(s, OPC_PUSH_r32 + reg);
+ tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0);
}
static inline void tcg_out_pop(TCGContext *s, int reg)
{
- tcg_out_opc(s, OPC_POP_r32 + reg);
+ tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0);
}
static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
int arg1, tcg_target_long arg2)
{
- tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2);
+ int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
+ tcg_out_modrm_offset(s, opc, ret, arg1, arg2);
}
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
int arg1, tcg_target_long arg2)
{
- tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2);
+ int opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0);
+ tcg_out_modrm_offset(s, opc, arg, arg1, arg2);
}
static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count)
@@ -406,35 +583,35 @@ static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count)
subopc &= 0x7;
if (count == 1) {
- tcg_out_modrm(s, OPC_SHIFT_1 | ext, subopc, reg);
+ tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg);
} else {
- tcg_out_modrm(s, OPC_SHIFT_Ib | ext, subopc, reg);
+ tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg);
tcg_out8(s, count);
}
}
static inline void tcg_out_bswap32(TCGContext *s, int reg)
{
- tcg_out_opc(s, OPC_BSWAP + reg);
+ tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0);
}
static inline void tcg_out_rolw_8(TCGContext *s, int reg)
{
- tcg_out_shifti(s, SHIFT_ROL | P_DATA16, reg, 8);
+ tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8);
}
static inline void tcg_out_ext8u(TCGContext *s, int dest, int src)
{
/* movzbl */
- assert(src < 4);
- tcg_out_modrm(s, OPC_MOVZBL, dest, src);
+ assert(src < 4 || TCG_TARGET_REG_BITS == 64);
+ tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src);
}
-static void tcg_out_ext8s(TCGContext *s, int dest, int src)
+static void tcg_out_ext8s(TCGContext *s, int dest, int src, int rexw)
{
/* movsbl */
- assert(src < 4);
- tcg_out_modrm(s, OPC_MOVSBL, dest, src);
+ assert(src < 4 || TCG_TARGET_REG_BITS == 64);
+ tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src);
}
static inline void tcg_out_ext16u(TCGContext *s, int dest, int src)
@@ -443,38 +620,94 @@ static inline void tcg_out_ext16u(TCGContext *s, int dest, int src)
tcg_out_modrm(s, OPC_MOVZWL, dest, src);
}
-static inline void tcg_out_ext16s(TCGContext *s, int dest, int src)
+static inline void tcg_out_ext16s(TCGContext *s, int dest, int src, int rexw)
{
- /* movswl */
- tcg_out_modrm(s, OPC_MOVSWL, dest, src);
+ /* movsw[lq] */
+ tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src);
}
-static inline void tgen_arithi(TCGContext *s, int c, int r0,
- int32_t val, int cf)
+static inline void tcg_out_ext32u(TCGContext *s, int dest, int src)
{
+ /* 32-bit mov zero extends. */
+ tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src);
+}
+
+static inline void tcg_out_ext32s(TCGContext *s, int dest, int src)
+{
+ tcg_out_modrm(s, OPC_MOVSLQ, dest, src);
+}
+
+static inline void tcg_out_bswap64(TCGContext *s, int reg)
+{
+ tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0);
+}
+
+static void tgen_arithi(TCGContext *s, int c, int r0,
+ tcg_target_long val, int cf)
+{
+ int rexw = 0;
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ rexw = c & -8;
+ c &= 7;
+ }
+
/* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
partial flags update stalls on Pentium4 and are not recommended
by current Intel optimization manuals. */
if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) {
- int opc = ((c == ARITH_ADD) ^ (val < 0) ? OPC_INC_r32 : OPC_DEC_r32);
- tcg_out_opc(s, opc + r0);
- } else if (val == (int8_t)val) {
- tcg_out_modrm(s, OPC_ARITH_EvIb, c, r0);
+ _Bool is_inc = (c == ARITH_ADD) ^ (val < 0);
+ if (TCG_TARGET_REG_BITS == 64) {
+ /* The single-byte increment encodings are re-tasked as the
+ REX prefixes. Use the MODRM encoding. */
+ tcg_out_modrm(s, OPC_GRP5 + rexw,
+ (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
+ } else {
+ tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
+ }
+ return;
+ }
+
+ if (c == ARITH_AND) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (val == 0xffffffffu) {
+ tcg_out_ext32u(s, r0, r0);
+ return;
+ }
+ if (val == (uint32_t)val) {
+ /* AND with no high bits set can use a 32-bit operation. */
+ rexw = 0;
+ }
+ }
+ if (val == 0xffu) {
+ tcg_out_ext8u(s, r0, r0);
+ return;
+ }
+ if (val == 0xffffu) {
+ tcg_out_ext16u(s, r0, r0);
+ return;
+ }
+ }
+
+ if (val == (int8_t)val) {
+ tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0);
tcg_out8(s, val);
- } else if (c == ARITH_AND && val == 0xffu && r0 < 4) {
- tcg_out_ext8u(s, r0, r0);
- } else if (c == ARITH_AND && val == 0xffffu) {
- tcg_out_ext16u(s, r0, r0);
- } else {
- tcg_out_modrm(s, OPC_ARITH_EvIz, c, r0);
+ return;
+ }
+ if (rexw == 0 || val == (int32_t)val) {
+ tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0);
tcg_out32(s, val);
+ return;
}
+
+ tcg_abort();
}
static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
{
- if (val != 0)
- tgen_arithi(s, ARITH_ADD, reg, val, 0);
+ if (val != 0) {
+ tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0);
+ }
}
/* Use SMALL != 0 to force a short forward branch. */
@@ -501,7 +734,7 @@ static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small)
tcg_out8(s, OPC_JMP_long);
tcg_out32(s, val - 5);
} else {
- tcg_out_opc(s, OPC_JCC_long + opc);
+ tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0);
tcg_out32(s, val - 6);
}
}
@@ -517,7 +750,7 @@ static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small)
if (opc == -1) {
tcg_out8(s, OPC_JMP_long);
} else {
- tcg_out_opc(s, OPC_JCC_long + opc);
+ tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0);
}
tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
s->code_ptr += 4;
@@ -525,28 +758,37 @@ static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small)
}
static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
- int const_arg2)
+ int const_arg2, int rexw)
{
if (const_arg2) {
if (arg2 == 0) {
/* test r, r */
- tcg_out_modrm(s, OPC_TESTL, arg1, arg1);
+ tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1);
} else {
- tgen_arithi(s, ARITH_CMP, arg1, arg2, 0);
+ tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0);
}
} else {
- tgen_arithr(s, ARITH_CMP, arg1, arg2);
+ tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2);
}
}
-static void tcg_out_brcond(TCGContext *s, TCGCond cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- int label_index, int small)
+static void tcg_out_brcond32(TCGContext *s, TCGCond cond,
+ TCGArg arg1, TCGArg arg2, int const_arg2,
+ int label_index, int small)
{
- tcg_out_cmp(s, arg1, arg2, const_arg2);
+ tcg_out_cmp(s, arg1, arg2, const_arg2, 0);
tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, small);
}
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_brcond64(TCGContext *s, TCGCond cond,
+ TCGArg arg1, TCGArg arg2, int const_arg2,
+ int label_index, int small)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW);
+ tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, small);
+}
+#else
/* XXX: we implement it at the target level to avoid having to
handle cross basic blocks temporaries */
static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
@@ -556,87 +798,97 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
label_next = gen_new_label();
switch(args[4]) {
case TCG_COND_EQ:
- tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2],
- label_next, 1);
- tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2],
+ label_next, 1);
+ tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3],
+ args[5], small);
break;
case TCG_COND_NE:
- tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2],
- args[5], small);
- tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2],
+ args[5], small);
+ tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3],
+ args[5], small);
break;
case TCG_COND_LT:
- tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3],
+ args[5], small);
tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_LE:
- tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3],
+ args[5], small);
tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_GT:
- tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3],
+ args[5], small);
tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_GE:
- tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3],
+ args[5], small);
tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_LTU:
- tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3],
+ args[5], small);
tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_LEU:
- tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3],
+ args[5], small);
tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_GTU:
- tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3],
+ args[5], small);
tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2],
+ args[5], small);
break;
case TCG_COND_GEU:
- tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3],
+ args[5], small);
tcg_out_jxx(s, JCC_JNE, label_next, 1);
- tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2],
- args[5], small);
+ tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2],
+ args[5], small);
break;
default:
tcg_abort();
}
tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
}
+#endif
-static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg dest,
- TCGArg arg1, TCGArg arg2, int const_arg2)
+static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest,
+ TCGArg arg1, TCGArg arg2, int const_arg2)
{
- tcg_out_cmp(s, arg1, arg2, const_arg2);
+ tcg_out_cmp(s, arg1, arg2, const_arg2, 0);
tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest);
tcg_out_ext8u(s, dest, dest);
}
+#if TCG_TARGET_REG_BITS == 64
+static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest,
+ TCGArg arg1, TCGArg arg2, int const_arg2)
+{
+ tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW);
+ tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest);
+ tcg_out_ext8u(s, dest, dest);
+}
+#else
static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
const int *const_args)
{
@@ -678,11 +930,30 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
tcg_out_label(s, label_over, (tcg_target_long)s->code_ptr);
}
}
+#endif
+
+static void tcg_out_branch(TCGContext *s, int call, tcg_target_long dest)
+{
+ tcg_target_long disp = dest - (tcg_target_long)s->code_ptr - 5;
+
+ if (disp == (int32_t)disp) {
+ tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0);
+ tcg_out32(s, disp);
+ } else {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, dest);
+ tcg_out_modrm(s, OPC_GRP5,
+ call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev, TCG_REG_R10);
+ }
+}
+
+static inline void tcg_out_calli(TCGContext *s, tcg_target_long dest)
+{
+ tcg_out_branch(s, 1, dest);
+}
-static void tcg_out_calli(TCGContext *s, tcg_target_long dest)
+static void tcg_out_jmp(TCGContext *s, tcg_target_long dest)
{
- tcg_out_opc(s, OPC_CALL_Jz);
- tcg_out32(s, dest - (tcg_target_long)s->code_ptr - 4);
+ tcg_out_branch(s, 0, dest);
}
#if defined(CONFIG_SOFTMMU)
@@ -718,11 +989,12 @@ static void *qemu_st_helpers[4] = {
LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses)
positions of the displacements of forward jumps to the TLB miss case.
- EAX is loaded with the low part of the address. In the TLB hit case,
- it has been adjusted as indicated by the TLB and so is a host address.
- In the TLB miss case, it continues to hold a guest address.
+ First argument register is loaded with the low part of the address.
+ In the TLB hit case, it has been adjusted as indicated by the TLB
+ and so is a host address. In the TLB miss case, it continues to
+ hold a guest address.
- EDX is clobbered. */
+ Second argument register is clobbered. */
static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
int mem_index, int s_bits,
@@ -730,32 +1002,42 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
uint8_t **label_ptr, int which)
{
const int addrlo = args[addrlo_idx];
- const int r0 = TCG_REG_EAX;
- const int r1 = TCG_REG_EDX;
+ const int r0 = tcg_target_call_iarg_regs[0];
+ const int r1 = tcg_target_call_iarg_regs[1];
+ TCGType type = TCG_TYPE_I32;
+ int rexw = 0;
+
+ if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 64) {
+ type = TCG_TYPE_I64;
+ rexw = P_REXW;
+ }
- tcg_out_mov(s, TCG_TYPE_I32, r1, addrlo);
- tcg_out_mov(s, TCG_TYPE_I32, r0, addrlo);
+ tcg_out_mov(s, type, r1, addrlo);
+ tcg_out_mov(s, type, r0, addrlo);
- tcg_out_shifti(s, SHIFT_SHR, r1, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+ tcg_out_shifti(s, SHIFT_SHR + rexw, r1,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
- tgen_arithi(s, ARITH_AND, r0, TARGET_PAGE_MASK | ((1 << s_bits) - 1), 0);
- tgen_arithi(s, ARITH_AND, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
+ tgen_arithi(s, ARITH_AND + rexw, r0,
+ TARGET_PAGE_MASK | ((1 << s_bits) - 1), 0);
+ tgen_arithi(s, ARITH_AND + rexw, r1,
+ (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
- tcg_out_modrm_sib_offset(s, OPC_LEA, r1, TCG_AREG0, r1, 0,
+ tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, r1, TCG_AREG0, r1, 0,
offsetof(CPUState, tlb_table[mem_index][0])
+ which);
/* cmp 0(r1), r0 */
- tcg_out_modrm_offset(s, OPC_CMP_GvEv, r0, r1, 0);
+ tcg_out_modrm_offset(s, OPC_CMP_GvEv + rexw, r0, r1, 0);
- tcg_out_mov(s, TCG_TYPE_I32, r0, addrlo);
+ tcg_out_mov(s, type, r0, addrlo);
/* jne label1 */
tcg_out8(s, OPC_JCC_short + JCC_JNE);
label_ptr[0] = s->code_ptr;
s->code_ptr++;
- if (TARGET_LONG_BITS == 64) {
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
/* cmp 4(r1), addrhi */
tcg_out_modrm_offset(s, OPC_CMP_GvEv, args[addrlo_idx+1], r1, 4);
@@ -768,7 +1050,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
/* TLB Hit. */
/* add addend(r1), r0 */
- tcg_out_modrm_offset(s, OPC_ADD_GvEv, r0, r1,
+ tcg_out_modrm_offset(s, OPC_ADD_GvEv + P_REXW, r0, r1,
offsetof(CPUTLBEntry, addend) - which);
}
#endif
@@ -783,26 +1065,24 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
#endif
switch (sizeop) {
case 0:
- /* movzbl */
tcg_out_modrm_offset(s, OPC_MOVZBL, datalo, base, ofs);
break;
case 0 | 4:
- /* movsbl */
- tcg_out_modrm_offset(s, OPC_MOVSBL, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVSBL + P_REXW, datalo, base, ofs);
break;
case 1:
- /* movzwl */
tcg_out_modrm_offset(s, OPC_MOVZWL, datalo, base, ofs);
if (bswap) {
tcg_out_rolw_8(s, datalo);
}
break;
case 1 | 4:
- /* movswl */
- tcg_out_modrm_offset(s, OPC_MOVSWL, datalo, base, ofs);
if (bswap) {
+ tcg_out_modrm_offset(s, OPC_MOVZWL, datalo, base, ofs);
tcg_out_rolw_8(s, datalo);
- tcg_out_modrm(s, OPC_MOVSWL, datalo, datalo);
+ tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo);
+ } else {
+ tcg_out_modrm_offset(s, OPC_MOVSWL + P_REXW, datalo, base, ofs);
}
break;
case 2:
@@ -811,22 +1091,40 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
tcg_out_bswap32(s, datalo);
}
break;
- case 3:
+#if TCG_TARGET_REG_BITS == 64
+ case 2 | 4:
if (bswap) {
- int t = datalo;
- datalo = datahi;
- datahi = t;
- }
- if (base != datalo) {
tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
- tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
+ tcg_out_bswap32(s, datalo);
+ tcg_out_ext32s(s, datalo, datalo);
} else {
- tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
- tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVSLQ, datalo, base, ofs);
}
- if (bswap) {
- tcg_out_bswap32(s, datalo);
- tcg_out_bswap32(s, datahi);
+ break;
+#endif
+ case 3:
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_ld(s, TCG_TYPE_I64, datalo, base, ofs);
+ if (bswap) {
+ tcg_out_bswap64(s, datalo);
+ }
+ } else {
+ if (bswap) {
+ int t = datalo;
+ datalo = datahi;
+ datahi = t;
+ }
+ if (base != datalo) {
+ tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
+ tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
+ } else {
+ tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
+ tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
+ }
+ if (bswap) {
+ tcg_out_bswap32(s, datalo);
+ tcg_out_bswap32(s, datahi);
+ }
}
break;
default:
@@ -849,20 +1147,21 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
data_reg = args[0];
addrlo_idx = 1;
- if (opc == 3) {
+ if (TCG_TARGET_REG_BITS == 32 && opc == 3) {
data_reg2 = args[1];
addrlo_idx = 2;
}
#if defined(CONFIG_SOFTMMU)
- mem_index = args[addrlo_idx + (TARGET_LONG_BITS / 32)];
+ mem_index = args[addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS)];
s_bits = opc & 3;
tcg_out_tlb_load(s, addrlo_idx, mem_index, s_bits, args,
label_ptr, offsetof(CPUTLBEntry, addr_read));
/* TLB Hit. */
- tcg_out_qemu_ld_direct(s, data_reg, data_reg2, TCG_REG_EAX, 0, opc);
+ tcg_out_qemu_ld_direct(s, data_reg, data_reg2,
+ tcg_target_call_iarg_regs[0], 0, opc);
/* jmp label2 */
tcg_out8(s, OPC_JMP_short);
@@ -873,14 +1172,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
/* label1: */
*label_ptr[0] = s->code_ptr - label_ptr[0] - 1;
- if (TARGET_LONG_BITS == 64) {
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
*label_ptr[1] = s->code_ptr - label_ptr[1] - 1;
}
/* XXX: move that code at the end of the TB */
- /* EAX is already loaded. */
+ /* The first argument is already loaded with addrlo. */
arg_idx = 1;
- if (TARGET_LONG_BITS == 64) {
+ if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 64) {
tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx++],
args[addrlo_idx + 1]);
}
@@ -890,10 +1189,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
switch(opc) {
case 0 | 4:
- tcg_out_ext8s(s, data_reg, TCG_REG_EAX);
+ tcg_out_ext8s(s, data_reg, TCG_REG_EAX, P_REXW);
break;
case 1 | 4:
- tcg_out_ext16s(s, data_reg, TCG_REG_EAX);
+ tcg_out_ext16s(s, data_reg, TCG_REG_EAX, P_REXW);
break;
case 0:
tcg_out_ext8u(s, data_reg, TCG_REG_EAX);
@@ -902,26 +1201,52 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
tcg_out_ext16u(s, data_reg, TCG_REG_EAX);
break;
case 2:
- default:
tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
break;
+#if TCG_TARGET_REG_BITS == 64
+ case 2 | 4:
+ tcg_out_ext32s(s, data_reg, TCG_REG_EAX);
+ break;
+#endif
case 3:
- if (data_reg == TCG_REG_EDX) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);
+ } else if (data_reg == TCG_REG_EDX) {
/* xchg %edx, %eax */
- tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX);
+ tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0);
tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EAX);
} else {
tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EDX);
}
break;
+ default:
+ tcg_abort();
}
/* label2: */
*label_ptr[2] = s->code_ptr - label_ptr[2] - 1;
#else
- tcg_out_qemu_ld_direct(s, data_reg, data_reg2,
- args[addrlo_idx], GUEST_BASE, opc);
+ {
+ int32_t offset = GUEST_BASE;
+ int base = args[addrlo_idx];
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ /* ??? We assume all operations have left us with register
+ contents that are zero extended. So far this appears to
+ be true. If we want to enforce this, we can either do
+ an explicit zero-extension here, or (if GUEST_BASE == 0)
+ use the ADDR32 prefix. For now, do nothing. */
+
+ if (offset != GUEST_BASE) {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE);
+ tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base);
+ base = TCG_REG_RDI, offset = 0;
+ }
+ }
+
+ tcg_out_qemu_ld_direct(s, data_reg, data_reg2, base, offset, opc);
+ }
#endif
}
@@ -936,12 +1261,12 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
/* ??? Ideally we wouldn't need a scratch register. For user-only,
we could perform the bswap twice to restore the original value
instead of moving to the scratch. But as it is, the L constraint
- means that EDX is definitely free here. */
- int scratch = TCG_REG_EDX;
+ means that the second argument reg is definitely free here. */
+ int scratch = tcg_target_call_iarg_regs[1];
switch (sizeop) {
case 0:
- tcg_out_modrm_offset(s, OPC_MOVB_EvGv, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R, datalo, base, ofs);
break;
case 1:
if (bswap) {
@@ -949,9 +1274,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
tcg_out_rolw_8(s, scratch);
datalo = scratch;
}
- /* movw */
- tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16,
- datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_DATA16, datalo, base, ofs);
break;
case 2:
if (bswap) {
@@ -962,7 +1285,14 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
tcg_out_st(s, TCG_TYPE_I32, datalo, base, ofs);
break;
case 3:
- if (bswap) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (bswap) {
+ tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo);
+ tcg_out_bswap64(s, scratch);
+ datalo = scratch;
+ }
+ tcg_out_st(s, TCG_TYPE_I64, datalo, base, ofs);
+ } else if (bswap) {
tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi);
tcg_out_bswap32(s, scratch);
tcg_out_st(s, TCG_TYPE_I32, scratch, base, ofs);
@@ -992,20 +1322,21 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
data_reg = args[0];
addrlo_idx = 1;
- if (opc == 3) {
+ if (TCG_TARGET_REG_BITS == 32 && opc == 3) {
data_reg2 = args[1];
addrlo_idx = 2;
}
#if defined(CONFIG_SOFTMMU)
- mem_index = args[addrlo_idx + (TARGET_LONG_BITS / 32)];
+ mem_index = args[addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS)];
s_bits = opc;
tcg_out_tlb_load(s, addrlo_idx, mem_index, s_bits, args,
label_ptr, offsetof(CPUTLBEntry, addr_write));
/* TLB Hit. */
- tcg_out_qemu_st_direct(s, data_reg, data_reg2, TCG_REG_EAX, 0, opc);
+ tcg_out_qemu_st_direct(s, data_reg, data_reg2,
+ tcg_target_call_iarg_regs[0], 0, opc);
/* jmp label2 */
tcg_out8(s, OPC_JMP_short);
@@ -1016,12 +1347,17 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
/* label1: */
*label_ptr[0] = s->code_ptr - label_ptr[0] - 1;
- if (TARGET_LONG_BITS == 64) {
+ if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
*label_ptr[1] = s->code_ptr - label_ptr[1] - 1;
}
/* XXX: move that code at the end of the TB */
- if (TARGET_LONG_BITS == 32) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32),
+ TCG_REG_RSI, data_reg);
+ tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
+ stack_adjust = 0;
+ } else if (TARGET_LONG_BITS == 32) {
tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_EDX, data_reg);
if (opc == 3) {
tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_ECX, data_reg2);
@@ -1058,7 +1394,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]);
- if (stack_adjust == 4) {
+ if (stack_adjust == (TCG_TARGET_REG_BITS / 8)) {
/* Pop and discard. This is 2 bytes smaller than the add. */
tcg_out_pop(s, TCG_REG_ECX);
} else if (stack_adjust != 0) {
@@ -1068,21 +1404,48 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
/* label2: */
*label_ptr[2] = s->code_ptr - label_ptr[2] - 1;
#else
- tcg_out_qemu_st_direct(s, data_reg, data_reg2,
- args[addrlo_idx], GUEST_BASE, opc);
+ {
+ int32_t offset = GUEST_BASE;
+ int base = args[addrlo_idx];
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ /* ??? We assume all operations have left us with register
+ contents that are zero extended. So far this appears to
+ be true. If we want to enforce this, we can either do
+ an explicit zero-extension here, or (if GUEST_BASE == 0)
+ use the ADDR32 prefix. For now, do nothing. */
+
+ if (offset != GUEST_BASE) {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE);
+ tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base);
+ base = TCG_REG_RDI, offset = 0;
+ }
+ }
+
+ tcg_out_qemu_st_direct(s, data_reg, data_reg2, base, offset, opc);
+ }
#endif
}
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
- int c;
+ int c, rexw = 0;
+
+#if TCG_TARGET_REG_BITS == 64
+# define OP_32_64(x) \
+ case glue(glue(INDEX_op_, x), _i64): \
+ rexw = P_REXW; /* FALLTHRU */ \
+ case glue(glue(INDEX_op_, x), _i32)
+#else
+# define OP_32_64(x) \
+ case glue(glue(INDEX_op_, x), _i32)
+#endif
switch(opc) {
case INDEX_op_exit_tb:
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
- tcg_out8(s, OPC_JMP_long); /* jmp tb_ret_addr */
- tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, args[0]);
+ tcg_out_jmp(s, (tcg_target_long) tb_ret_addr);
break;
case INDEX_op_goto_tb:
if (s->tb_jmp_offset) {
@@ -1107,8 +1470,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_jmp:
if (const_args[0]) {
- tcg_out8(s, OPC_JMP_long);
- tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
+ tcg_out_jmp(s, args[0]);
} else {
/* jmp *reg */
tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, args[0]);
@@ -1120,38 +1482,43 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_movi_i32:
tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
break;
- case INDEX_op_ld8u_i32:
- /* movzbl */
+ OP_32_64(ld8u):
+ /* Note that we can ignore REXW for the zero-extend to 64-bit. */
tcg_out_modrm_offset(s, OPC_MOVZBL, args[0], args[1], args[2]);
break;
- case INDEX_op_ld8s_i32:
- /* movsbl */
- tcg_out_modrm_offset(s, OPC_MOVSBL, args[0], args[1], args[2]);
+ OP_32_64(ld8s):
+ tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, args[0], args[1], args[2]);
break;
- case INDEX_op_ld16u_i32:
- /* movzwl */
+ OP_32_64(ld16u):
+ /* Note that we can ignore REXW for the zero-extend to 64-bit. */
tcg_out_modrm_offset(s, OPC_MOVZWL, args[0], args[1], args[2]);
break;
- case INDEX_op_ld16s_i32:
- /* movswl */
- tcg_out_modrm_offset(s, OPC_MOVSWL, args[0], args[1], args[2]);
+ OP_32_64(ld16s):
+ tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, args[0], args[1], args[2]);
break;
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_ld32u_i64:
+#endif
case INDEX_op_ld_i32:
tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
break;
- case INDEX_op_st8_i32:
- /* movb */
- tcg_out_modrm_offset(s, OPC_MOVB_EvGv, args[0], args[1], args[2]);
+
+ OP_32_64(st8):
+ tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R,
+ args[0], args[1], args[2]);
break;
- case INDEX_op_st16_i32:
- /* movw */
+ OP_32_64(st16):
tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16,
args[0], args[1], args[2]);
break;
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_st32_i64:
+#endif
case INDEX_op_st_i32:
tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
break;
- case INDEX_op_add_i32:
+
+ OP_32_64(add):
/* For 3-operand addition, use LEA. */
if (args[0] != args[1]) {
TCGArg a0 = args[0], a1 = args[1], a2 = args[2], c3 = 0;
@@ -1161,147 +1528,117 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
} else if (a0 == a2) {
/* Watch out for dest = src + dest, since we've removed
the matching constraint on the add. */
- tgen_arithr(s, ARITH_ADD, a0, a1);
+ tgen_arithr(s, ARITH_ADD + rexw, a0, a1);
break;
}
- tcg_out_modrm_sib_offset(s, OPC_LEA, a0, a1, a2, 0, c3);
+ tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3);
break;
}
c = ARITH_ADD;
goto gen_arith;
- case INDEX_op_sub_i32:
+ OP_32_64(sub):
c = ARITH_SUB;
goto gen_arith;
- case INDEX_op_and_i32:
+ OP_32_64(and):
c = ARITH_AND;
goto gen_arith;
- case INDEX_op_or_i32:
+ OP_32_64(or):
c = ARITH_OR;
goto gen_arith;
- case INDEX_op_xor_i32:
+ OP_32_64(xor):
c = ARITH_XOR;
goto gen_arith;
gen_arith:
if (const_args[2]) {
- tgen_arithi(s, c, args[0], args[2], 0);
+ tgen_arithi(s, c + rexw, args[0], args[2], 0);
} else {
- tgen_arithr(s, c, args[0], args[2]);
+ tgen_arithr(s, c + rexw, args[0], args[2]);
}
break;
- case INDEX_op_mul_i32:
+
+ OP_32_64(mul):
if (const_args[2]) {
int32_t val;
val = args[2];
if (val == (int8_t)val) {
- tcg_out_modrm(s, OPC_IMUL_GvEvIb, args[0], args[0]);
+ tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, args[0], args[0]);
tcg_out8(s, val);
} else {
- tcg_out_modrm(s, OPC_IMUL_GvEvIz, args[0], args[0]);
+ tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, args[0], args[0]);
tcg_out32(s, val);
}
} else {
- tcg_out_modrm(s, OPC_IMUL_GvEv, args[0], args[2]);
+ tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, args[0], args[2]);
}
break;
- case INDEX_op_mulu2_i32:
- tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_MUL, args[3]);
- break;
- case INDEX_op_div2_i32:
- tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_IDIV, args[4]);
+
+ OP_32_64(div2):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]);
break;
- case INDEX_op_divu2_i32:
- tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_DIV, args[4]);
+ OP_32_64(divu2):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]);
break;
- case INDEX_op_shl_i32:
+
+ OP_32_64(shl):
c = SHIFT_SHL;
- gen_shift32:
- if (const_args[2]) {
- tcg_out_shifti(s, c, args[0], args[2]);
- } else {
- tcg_out_modrm(s, OPC_SHIFT_cl, c, args[0]);
- }
- break;
- case INDEX_op_shr_i32:
+ goto gen_shift;
+ OP_32_64(shr):
c = SHIFT_SHR;
- goto gen_shift32;
- case INDEX_op_sar_i32:
+ goto gen_shift;
+ OP_32_64(sar):
c = SHIFT_SAR;
- goto gen_shift32;
- case INDEX_op_rotl_i32:
+ goto gen_shift;
+ OP_32_64(rotl):
c = SHIFT_ROL;
- goto gen_shift32;
- case INDEX_op_rotr_i32:
+ goto gen_shift;
+ OP_32_64(rotr):
c = SHIFT_ROR;
- goto gen_shift32;
-
- case INDEX_op_add2_i32:
- if (const_args[4]) {
- tgen_arithi(s, ARITH_ADD, args[0], args[4], 1);
- } else {
- tgen_arithr(s, ARITH_ADD, args[0], args[4]);
- }
- if (const_args[5]) {
- tgen_arithi(s, ARITH_ADC, args[1], args[5], 1);
+ goto gen_shift;
+ gen_shift:
+ if (const_args[2]) {
+ tcg_out_shifti(s, c + rexw, args[0], args[2]);
} else {
- tgen_arithr(s, ARITH_ADC, args[1], args[5]);
- }
- break;
- case INDEX_op_sub2_i32:
- if (const_args[4]) {
- tgen_arithi(s, ARITH_SUB, args[0], args[4], 1);
- } else {
- tgen_arithr(s, ARITH_SUB, args[0], args[4]);
- }
- if (const_args[5]) {
- tgen_arithi(s, ARITH_SBB, args[1], args[5], 1);
- } else {
- tgen_arithr(s, ARITH_SBB, args[1], args[5]);
+ tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, args[0]);
}
break;
+
case INDEX_op_brcond_i32:
- tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
- args[3], 0);
+ tcg_out_brcond32(s, args[2], args[0], args[1], const_args[1],
+ args[3], 0);
break;
- case INDEX_op_brcond2_i32:
- tcg_out_brcond2(s, args, const_args, 0);
+ case INDEX_op_setcond_i32:
+ tcg_out_setcond32(s, args[3], args[0], args[1],
+ args[2], const_args[2]);
break;
- case INDEX_op_bswap16_i32:
+ OP_32_64(bswap16):
tcg_out_rolw_8(s, args[0]);
break;
- case INDEX_op_bswap32_i32:
+ OP_32_64(bswap32):
tcg_out_bswap32(s, args[0]);
break;
- case INDEX_op_neg_i32:
- tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, args[0]);
+ OP_32_64(neg):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, args[0]);
break;
-
- case INDEX_op_not_i32:
- tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NOT, args[0]);
+ OP_32_64(not):
+ tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, args[0]);
break;
- case INDEX_op_ext8s_i32:
- tcg_out_ext8s(s, args[0], args[1]);
+ OP_32_64(ext8s):
+ tcg_out_ext8s(s, args[0], args[1], rexw);
break;
- case INDEX_op_ext16s_i32:
- tcg_out_ext16s(s, args[0], args[1]);
+ OP_32_64(ext16s):
+ tcg_out_ext16s(s, args[0], args[1], rexw);
break;
- case INDEX_op_ext8u_i32:
+ OP_32_64(ext8u):
tcg_out_ext8u(s, args[0], args[1]);
break;
- case INDEX_op_ext16u_i32:
+ OP_32_64(ext16u):
tcg_out_ext16u(s, args[0], args[1]);
break;
- case INDEX_op_setcond_i32:
- tcg_out_setcond(s, args[3], args[0], args[1], args[2], const_args[2]);
- break;
- case INDEX_op_setcond2_i32:
- tcg_out_setcond2(s, args, const_args);
- break;
-
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
@@ -1314,6 +1651,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_qemu_ld16s:
tcg_out_qemu_ld(s, args, 1 | 4);
break;
+#if TCG_TARGET_REG_BITS == 64
+ case INDEX_op_qemu_ld32u:
+#endif
case INDEX_op_qemu_ld32:
tcg_out_qemu_ld(s, args, 2);
break;
@@ -1334,9 +1674,82 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_qemu_st(s, args, 3);
break;
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_brcond2_i32:
+ tcg_out_brcond2(s, args, const_args, 0);
+ break;
+ case INDEX_op_setcond2_i32:
+ tcg_out_setcond2(s, args, const_args);
+ break;
+ case INDEX_op_mulu2_i32:
+ tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_MUL, args[3]);
+ break;
+ case INDEX_op_add2_i32:
+ if (const_args[4]) {
+ tgen_arithi(s, ARITH_ADD, args[0], args[4], 1);
+ } else {
+ tgen_arithr(s, ARITH_ADD, args[0], args[4]);
+ }
+ if (const_args[5]) {
+ tgen_arithi(s, ARITH_ADC, args[1], args[5], 1);
+ } else {
+ tgen_arithr(s, ARITH_ADC, args[1], args[5]);
+ }
+ break;
+ case INDEX_op_sub2_i32:
+ if (const_args[4]) {
+ tgen_arithi(s, ARITH_SUB, args[0], args[4], 1);
+ } else {
+ tgen_arithr(s, ARITH_SUB, args[0], args[4]);
+ }
+ if (const_args[5]) {
+ tgen_arithi(s, ARITH_SBB, args[1], args[5], 1);
+ } else {
+ tgen_arithr(s, ARITH_SBB, args[1], args[5]);
+ }
+ break;
+#else /* TCG_TARGET_REG_BITS == 64 */
+ case INDEX_op_movi_i64:
+ tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
+ break;
+ case INDEX_op_ld32s_i64:
+ tcg_out_modrm_offset(s, OPC_MOVSLQ, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_ld_i64:
+ tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_st_i64:
+ tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
+ break;
+ case INDEX_op_qemu_ld32s:
+ tcg_out_qemu_ld(s, args, 2 | 4);
+ break;
+
+ case INDEX_op_brcond_i64:
+ tcg_out_brcond64(s, args[2], args[0], args[1], const_args[1],
+ args[3], 0);
+ break;
+ case INDEX_op_setcond_i64:
+ tcg_out_setcond64(s, args[3], args[0], args[1],
+ args[2], const_args[2]);
+ break;
+
+ case INDEX_op_bswap64_i64:
+ tcg_out_bswap64(s, args[0]);
+ break;
+ case INDEX_op_ext32u_i64:
+ tcg_out_ext32u(s, args[0], args[1]);
+ break;
+ case INDEX_op_ext32s_i64:
+ tcg_out_ext32s(s, args[0], args[1]);
+ break;
+#endif
+
default:
tcg_abort();
}
+
+#undef OP_32_64
}
static const TCGTargetOpDef x86_op_defs[] = {
@@ -1359,7 +1772,6 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_add_i32, { "r", "r", "ri" } },
{ INDEX_op_sub_i32, { "r", "0", "ri" } },
{ INDEX_op_mul_i32, { "r", "0", "ri" } },
- { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
{ INDEX_op_and_i32, { "r", "0", "ri" } },
@@ -1374,10 +1786,6 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_brcond_i32, { "r", "ri" } },
- { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
- { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
- { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
-
{ INDEX_op_bswap16_i32, { "r", "0" } },
{ INDEX_op_bswap32_i32, { "r", "0" } },
@@ -1391,9 +1799,75 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_ext16u_i32, { "r", "r" } },
{ INDEX_op_setcond_i32, { "q", "r", "ri" } },
+
+#if TCG_TARGET_REG_BITS == 32
+ { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
+ { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
+ { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
+ { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
{ INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
+#else
+ { INDEX_op_mov_i64, { "r", "r" } },
+ { INDEX_op_movi_i64, { "r" } },
+ { INDEX_op_ld8u_i64, { "r", "r" } },
+ { INDEX_op_ld8s_i64, { "r", "r" } },
+ { INDEX_op_ld16u_i64, { "r", "r" } },
+ { INDEX_op_ld16s_i64, { "r", "r" } },
+ { INDEX_op_ld32u_i64, { "r", "r" } },
+ { INDEX_op_ld32s_i64, { "r", "r" } },
+ { INDEX_op_ld_i64, { "r", "r" } },
+ { INDEX_op_st8_i64, { "r", "r" } },
+ { INDEX_op_st16_i64, { "r", "r" } },
+ { INDEX_op_st32_i64, { "r", "r" } },
+ { INDEX_op_st_i64, { "r", "r" } },
+
+ { INDEX_op_add_i64, { "r", "0", "re" } },
+ { INDEX_op_mul_i64, { "r", "0", "re" } },
+ { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
+ { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
+ { INDEX_op_sub_i64, { "r", "0", "re" } },
+ { INDEX_op_and_i64, { "r", "0", "reZ" } },
+ { INDEX_op_or_i64, { "r", "0", "re" } },
+ { INDEX_op_xor_i64, { "r", "0", "re" } },
+
+ { INDEX_op_shl_i64, { "r", "0", "ci" } },
+ { INDEX_op_shr_i64, { "r", "0", "ci" } },
+ { INDEX_op_sar_i64, { "r", "0", "ci" } },
+ { INDEX_op_rotl_i64, { "r", "0", "ci" } },
+ { INDEX_op_rotr_i64, { "r", "0", "ci" } },
+
+ { INDEX_op_brcond_i64, { "r", "re" } },
+ { INDEX_op_setcond_i64, { "r", "r", "re" } },
+
+ { INDEX_op_bswap16_i64, { "r", "0" } },
+ { INDEX_op_bswap32_i64, { "r", "0" } },
+ { INDEX_op_bswap64_i64, { "r", "0" } },
+ { INDEX_op_neg_i64, { "r", "0" } },
+ { INDEX_op_not_i64, { "r", "0" } },
+
+ { INDEX_op_ext8s_i64, { "r", "r" } },
+ { INDEX_op_ext16s_i64, { "r", "r" } },
+ { INDEX_op_ext32s_i64, { "r", "r" } },
+ { INDEX_op_ext8u_i64, { "r", "r" } },
+ { INDEX_op_ext16u_i64, { "r", "r" } },
+ { INDEX_op_ext32u_i64, { "r", "r" } },
+#endif
-#if TARGET_LONG_BITS == 32
+#if TCG_TARGET_REG_BITS == 64
+ { INDEX_op_qemu_ld8u, { "r", "L" } },
+ { INDEX_op_qemu_ld8s, { "r", "L" } },
+ { INDEX_op_qemu_ld16u, { "r", "L" } },
+ { INDEX_op_qemu_ld16s, { "r", "L" } },
+ { INDEX_op_qemu_ld32, { "r", "L" } },
+ { INDEX_op_qemu_ld32u, { "r", "L" } },
+ { INDEX_op_qemu_ld32s, { "r", "L" } },
+ { INDEX_op_qemu_ld64, { "r", "L" } },
+
+ { INDEX_op_qemu_st8, { "L", "L" } },
+ { INDEX_op_qemu_st16, { "L", "L" } },
+ { INDEX_op_qemu_st32, { "L", "L" } },
+ { INDEX_op_qemu_st64, { "L", "L" } },
+#elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
{ INDEX_op_qemu_ld8u, { "r", "L" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
{ INDEX_op_qemu_ld16u, { "r", "L" } },
@@ -1422,11 +1896,19 @@ static const TCGTargetOpDef x86_op_defs[] = {
};
static int tcg_target_callee_save_regs[] = {
- /* TCG_REG_EBP, */ /* currently used for the global env, so no
- need to save */
+#if TCG_TARGET_REG_BITS == 64
+ TCG_REG_RBP,
+ TCG_REG_RBX,
+ TCG_REG_R12,
+ TCG_REG_R13,
+ /* TCG_REG_R14, */ /* Currently used for the global env. */
+ TCG_REG_R15,
+#else
+ /* TCG_REG_EBP, */ /* Currently used for the global env. */
TCG_REG_EBX,
TCG_REG_ESI,
TCG_REG_EDI,
+#endif
};
/* Generate global QEMU prologue and epilogue code */
@@ -1435,27 +1917,34 @@ static void tcg_target_qemu_prologue(TCGContext *s)
int i, frame_size, push_size, stack_addend;
/* TB prologue */
- /* save all callee saved registers */
- for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+
+ /* Save all callee saved registers. */
+ for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
tcg_out_push(s, tcg_target_callee_save_regs[i]);
}
- /* reserve some stack space */
- push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
+
+ /* Reserve some stack space. */
+ push_size = 1 + ARRAY_SIZE(tcg_target_callee_save_regs);
+ push_size *= TCG_TARGET_REG_BITS / 8;
+
frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
~(TCG_TARGET_STACK_ALIGN - 1);
stack_addend = frame_size - push_size;
tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
- tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_EAX); /* jmp *%eax */
+ /* jmp *tb. */
+ tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[0]);
/* TB epilogue */
tb_ret_addr = s->code_ptr;
+
tcg_out_addi(s, TCG_REG_ESP, stack_addend);
- for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
+
+ for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
tcg_out_pop(s, tcg_target_callee_save_regs[i]);
}
- tcg_out_opc(s, OPC_RET);
+ tcg_out_opc(s, OPC_RET, 0, 0, 0);
}
static void tcg_target_init(TCGContext *s)
@@ -1466,12 +1955,25 @@ static void tcg_target_init(TCGContext *s)
tcg_abort();
#endif
- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
+ tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
+ } else {
+ tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
+ }
tcg_regset_clear(tcg_target_call_clobber_regs);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
+ }
tcg_regset_clear(s->reserved_regs);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index ca1d730..bfafbfc 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -23,10 +23,18 @@
*/
#define TCG_TARGET_I386 1
-#define TCG_TARGET_REG_BITS 32
+#if defined(__x86_64__)
+# define TCG_TARGET_REG_BITS 64
+#else
+# define TCG_TARGET_REG_BITS 32
+#endif
//#define TCG_TARGET_WORDS_BIGENDIAN
-#define TCG_TARGET_NB_REGS 8
+#if TCG_TARGET_REG_BITS == 64
+# define TCG_TARGET_NB_REGS 16
+#else
+# define TCG_TARGET_NB_REGS 8
+#endif
enum {
TCG_REG_EAX = 0,
@@ -37,8 +45,30 @@ enum {
TCG_REG_EBP,
TCG_REG_ESI,
TCG_REG_EDI,
+
+ /* 64-bit registers; always define the symbols to avoid
+ too much if-deffing. */
+ TCG_REG_R8,
+ TCG_REG_R9,
+ TCG_REG_R10,
+ TCG_REG_R11,
+ TCG_REG_R12,
+ TCG_REG_R13,
+ TCG_REG_R14,
+ TCG_REG_R15,
+ TCG_REG_RAX = TCG_REG_EAX,
+ TCG_REG_RCX = TCG_REG_ECX,
+ TCG_REG_RDX = TCG_REG_EDX,
+ TCG_REG_RBX = TCG_REG_EBX,
+ TCG_REG_RSP = TCG_REG_ESP,
+ TCG_REG_RBP = TCG_REG_EBP,
+ TCG_REG_RSI = TCG_REG_ESI,
+ TCG_REG_RDI = TCG_REG_EDI,
};
+#define TCG_CT_CONST_S32 0x100
+#define TCG_CT_CONST_U32 0x200
+
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_ESP
#define TCG_TARGET_STACK_ALIGN 16
@@ -61,10 +91,35 @@ enum {
// #define TCG_TARGET_HAS_nand_i32
// #define TCG_TARGET_HAS_nor_i32
+#if TCG_TARGET_REG_BITS == 64
+#define TCG_TARGET_HAS_div2_i64
+#define TCG_TARGET_HAS_rot_i64
+#define TCG_TARGET_HAS_ext8s_i64
+#define TCG_TARGET_HAS_ext16s_i64
+#define TCG_TARGET_HAS_ext32s_i64
+#define TCG_TARGET_HAS_ext8u_i64
+#define TCG_TARGET_HAS_ext16u_i64
+#define TCG_TARGET_HAS_ext32u_i64
+#define TCG_TARGET_HAS_bswap16_i64
+#define TCG_TARGET_HAS_bswap32_i64
+#define TCG_TARGET_HAS_bswap64_i64
+#define TCG_TARGET_HAS_neg_i64
+#define TCG_TARGET_HAS_not_i64
+// #define TCG_TARGET_HAS_andc_i64
+// #define TCG_TARGET_HAS_orc_i64
+// #define TCG_TARGET_HAS_eqv_i64
+// #define TCG_TARGET_HAS_nand_i64
+// #define TCG_TARGET_HAS_nor_i64
+#endif
+
#define TCG_TARGET_HAS_GUEST_BASE
/* Note: must be synced with dyngen-exec.h */
-#define TCG_AREG0 TCG_REG_EBP
+#if TCG_TARGET_REG_BITS == 64
+# define TCG_AREG0 TCG_REG_R14
+#else
+# define TCG_AREG0 TCG_REG_EBP
+#endif
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
deleted file mode 100644
index 490666e..0000000
--- a/tcg/x86_64/tcg-target.c
+++ /dev/null
@@ -1,1445 +0,0 @@
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifndef NDEBUG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "%rax",
- "%rcx",
- "%rdx",
- "%rbx",
- "%rsp",
- "%rbp",
- "%rsi",
- "%rdi",
- "%r8",
- "%r9",
- "%r10",
- "%r11",
- "%r12",
- "%r13",
- "%r14",
- "%r15",
-};
-#endif
-
-static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_RBP,
- TCG_REG_RBX,
- TCG_REG_R12,
- TCG_REG_R13,
- TCG_REG_R14,
- TCG_REG_R15,
- TCG_REG_R10,
- TCG_REG_R11,
- TCG_REG_R9,
- TCG_REG_R8,
- TCG_REG_RCX,
- TCG_REG_RDX,
- TCG_REG_RSI,
- TCG_REG_RDI,
- TCG_REG_RAX,
-};
-
-static const int tcg_target_call_iarg_regs[6] = {
- TCG_REG_RDI,
- TCG_REG_RSI,
- TCG_REG_RDX,
- TCG_REG_RCX,
- TCG_REG_R8,
- TCG_REG_R9,
-};
-
-static const int tcg_target_call_oarg_regs[2] = {
- TCG_REG_RAX,
- TCG_REG_RDX
-};
-
-static uint8_t *tb_ret_addr;
-
-static void patch_reloc(uint8_t *code_ptr, int type,
- tcg_target_long value, tcg_target_long addend)
-{
- value += addend;
- switch(type) {
- case R_X86_64_32:
- if (value != (uint32_t)value)
- tcg_abort();
- *(uint32_t *)code_ptr = value;
- break;
- case R_X86_64_32S:
- if (value != (int32_t)value)
- tcg_abort();
- *(uint32_t *)code_ptr = value;
- break;
- case R_386_PC32:
- value -= (long)code_ptr;
- if (value != (int32_t)value)
- tcg_abort();
- *(uint32_t *)code_ptr = value;
- break;
- default:
- tcg_abort();
- }
-}
-
-/* maximum number of register used for input function arguments */
-static inline int tcg_target_get_call_iarg_regs_count(int flags)
-{
- return 6;
-}
-
-/* parse target specific constraints */
-static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
-{
- const char *ct_str;
-
- ct_str = *pct_str;
- switch(ct_str[0]) {
- case 'a':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
- break;
- case 'b':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
- break;
- case 'c':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
- break;
- case 'd':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
- break;
- case 'S':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
- break;
- case 'D':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
- break;
- case 'q':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xf);
- break;
- case 'r':
- ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xffff);
- break;
- case 'L': /* qemu_ld/st constraint */
- ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xffff);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
- break;
- case 'e':
- ct->ct |= TCG_CT_CONST_S32;
- break;
- case 'Z':
- ct->ct |= TCG_CT_CONST_U32;
- break;
- default:
- return -1;
- }
- ct_str++;
- *pct_str = ct_str;
- return 0;
-}
-
-/* test if a constant matches the constraint */
-static inline int tcg_target_const_match(tcg_target_long val,
- const TCGArgConstraint *arg_ct)
-{
- int ct;
- ct = arg_ct->ct;
- if (ct & TCG_CT_CONST)
- return 1;
- else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
- return 1;
- else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
- return 1;
- else
- return 0;
-}
-
-#define ARITH_ADD 0
-#define ARITH_OR 1
-#define ARITH_ADC 2
-#define ARITH_SBB 3
-#define ARITH_AND 4
-#define ARITH_SUB 5
-#define ARITH_XOR 6
-#define ARITH_CMP 7
-
-#define SHIFT_ROL 0
-#define SHIFT_ROR 1
-#define SHIFT_SHL 4
-#define SHIFT_SHR 5
-#define SHIFT_SAR 7
-
-#define JCC_JMP (-1)
-#define JCC_JO 0x0
-#define JCC_JNO 0x1
-#define JCC_JB 0x2
-#define JCC_JAE 0x3
-#define JCC_JE 0x4
-#define JCC_JNE 0x5
-#define JCC_JBE 0x6
-#define JCC_JA 0x7
-#define JCC_JS 0x8
-#define JCC_JNS 0x9
-#define JCC_JP 0xa
-#define JCC_JNP 0xb
-#define JCC_JL 0xc
-#define JCC_JGE 0xd
-#define JCC_JLE 0xe
-#define JCC_JG 0xf
-
-#define P_EXT 0x100 /* 0x0f opcode prefix */
-#define P_REXW 0x200 /* set rex.w = 1 */
-#define P_REXB_R 0x400 /* REG field as byte register */
-#define P_REXB_RM 0x800 /* R/M field as byte register */
-
-static const uint8_t tcg_cond_to_jcc[10] = {
- [TCG_COND_EQ] = JCC_JE,
- [TCG_COND_NE] = JCC_JNE,
- [TCG_COND_LT] = JCC_JL,
- [TCG_COND_GE] = JCC_JGE,
- [TCG_COND_LE] = JCC_JLE,
- [TCG_COND_GT] = JCC_JG,
- [TCG_COND_LTU] = JCC_JB,
- [TCG_COND_GEU] = JCC_JAE,
- [TCG_COND_LEU] = JCC_JBE,
- [TCG_COND_GTU] = JCC_JA,
-};
-
-static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
-{
- int rex = 0;
-
- rex |= (opc & P_REXW) >> 6; /* REX.W */
- rex |= (r & 8) >> 1; /* REX.R */
- rex |= (x & 8) >> 2; /* REX.X */
- rex |= (rm & 8) >> 3; /* REX.B */
-
- /* P_REXB_{R,RM} indicates that the given register is the low byte.
- For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
- as otherwise the encoding indicates %[abcd]h. Note that the values
- that are ORed in merely indicate that the REX byte must be present;
- those bits get discarded in output. */
- rex |= opc & (r >= 4 ? P_REXB_R : 0);
- rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
-
- if (rex) {
- tcg_out8(s, (uint8_t)(rex | 0x40));
- }
- if (opc & P_EXT) {
- tcg_out8(s, 0x0f);
- }
- tcg_out8(s, opc & 0xff);
-}
-
-static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
-{
- tcg_out_opc(s, opc, r, rm, 0);
- tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
-}
-
-/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
-static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
- tcg_target_long offset)
-{
- if (rm < 0) {
- tcg_target_long val;
- tcg_out_opc(s, opc, r, 0, 0);
- val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
- if (val == (int32_t)val) {
- /* eip relative */
- tcg_out8(s, 0x05 | ((r & 7) << 3));
- tcg_out32(s, val);
- } else if (offset == (int32_t)offset) {
- tcg_out8(s, 0x04 | ((r & 7) << 3));
- tcg_out8(s, 0x25); /* sib */
- tcg_out32(s, offset);
- } else {
- tcg_abort();
- }
- } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
- tcg_out_opc(s, opc, r, rm, 0);
- if ((rm & 7) == TCG_REG_RSP) {
- tcg_out8(s, 0x04 | ((r & 7) << 3));
- tcg_out8(s, 0x24);
- } else {
- tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
- }
- } else if ((int8_t)offset == offset) {
- tcg_out_opc(s, opc, r, rm, 0);
- if ((rm & 7) == TCG_REG_RSP) {
- tcg_out8(s, 0x44 | ((r & 7) << 3));
- tcg_out8(s, 0x24);
- } else {
- tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
- }
- tcg_out8(s, offset);
- } else {
- tcg_out_opc(s, opc, r, rm, 0);
- if ((rm & 7) == TCG_REG_RSP) {
- tcg_out8(s, 0x84 | ((r & 7) << 3));
- tcg_out8(s, 0x24);
- } else {
- tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
- }
- tcg_out32(s, offset);
- }
-}
-
-#if defined(CONFIG_SOFTMMU)
-/* XXX: incomplete. index must be different from ESP */
-static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
- int index, int shift,
- tcg_target_long offset)
-{
- int mod;
- if (rm == -1)
- tcg_abort();
- if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
- mod = 0;
- } else if (offset == (int8_t)offset) {
- mod = 0x40;
- } else if (offset == (int32_t)offset) {
- mod = 0x80;
- } else {
- tcg_abort();
- }
- if (index == -1) {
- tcg_out_opc(s, opc, r, rm, 0);
- if ((rm & 7) == TCG_REG_RSP) {
- tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
- tcg_out8(s, 0x04 | (rm & 7));
- } else {
- tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
- }
- } else {
- tcg_out_opc(s, opc, r, rm, index);
- tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
- tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
- }
- if (mod == 0x40) {
- tcg_out8(s, offset);
- } else if (mod == 0x80) {
- tcg_out32(s, offset);
- }
-}
-#endif
-
-static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
-{
- int rexw = (type == TCG_TYPE_I64 ? P_REXW : 0);
- tcg_out_modrm(s, 0x8b | rexw, ret, arg);
-}
-
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- int ret, tcg_target_long arg)
-{
- if (arg == 0) {
- tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
- } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
- tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
- tcg_out32(s, arg);
- } else if (arg == (int32_t)arg) {
- tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
- tcg_out32(s, arg);
- } else {
- tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
- tcg_out32(s, arg);
- tcg_out32(s, arg >> 32);
- }
-}
-
-static void tcg_out_goto(TCGContext *s, int call, uint8_t *target)
-{
- int32_t disp;
-
- disp = target - s->code_ptr - 5;
- if (disp == (target - s->code_ptr - 5)) {
- tcg_out8(s, call ? 0xe8 : 0xe9);
- tcg_out32(s, disp);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (tcg_target_long) target);
- tcg_out_modrm(s, 0xff, call ? 2 : 4, TCG_REG_R10);
- }
-}
-
-static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
- int arg1, tcg_target_long arg2)
-{
- if (type == TCG_TYPE_I32)
- tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
- else
- tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
-}
-
-static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
- int arg1, tcg_target_long arg2)
-{
- if (type == TCG_TYPE_I32)
- tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
- else
- tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
-}
-
-static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
-{
- if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) {
- /* inc */
- tcg_out_modrm(s, 0xff, 0, r0);
- } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
- /* dec */
- tcg_out_modrm(s, 0xff, 1, r0);
- } else if (val == (int8_t)val) {
- tcg_out_modrm(s, 0x83, c, r0);
- tcg_out8(s, val);
- } else if (c == ARITH_AND && val == 0xffu) {
- /* movzbl */
- tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, r0, r0);
- } else if (c == ARITH_AND && val == 0xffffu) {
- /* movzwl */
- tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
- } else {
- tcg_out_modrm(s, 0x81, c, r0);
- tcg_out32(s, val);
- }
-}
-
-static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
-{
- if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) {
- /* inc */
- tcg_out_modrm(s, 0xff | P_REXW, 0, r0);
- } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
- /* dec */
- tcg_out_modrm(s, 0xff | P_REXW, 1, r0);
- } else if (c == ARITH_AND && val == 0xffffffffu) {
- /* 32-bit mov zero extends */
- tcg_out_modrm(s, 0x8b, r0, r0);
- } else if (c == ARITH_AND && val == (uint32_t)val) {
- /* AND with no high bits set can use a 32-bit operation. */
- tgen_arithi32(s, c, r0, (uint32_t)val);
- } else if (val == (int8_t)val) {
- tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
- tcg_out8(s, val);
- } else if (val == (int32_t)val) {
- tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
- tcg_out32(s, val);
- } else {
- tcg_abort();
- }
-}
-
-static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
-{
- if (val != 0)
- tgen_arithi64(s, ARITH_ADD, reg, val);
-}
-
-static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
-{
- int32_t val, val1;
- TCGLabel *l = &s->labels[label_index];
-
- if (l->has_value) {
- val = l->u.value - (tcg_target_long)s->code_ptr;
- val1 = val - 2;
- if ((int8_t)val1 == val1) {
- if (opc == -1)
- tcg_out8(s, 0xeb);
- else
- tcg_out8(s, 0x70 + opc);
- tcg_out8(s, val1);
- } else {
- if (opc == -1) {
- tcg_out8(s, 0xe9);
- tcg_out32(s, val - 5);
- } else {
- tcg_out8(s, 0x0f);
- tcg_out8(s, 0x80 + opc);
- tcg_out32(s, val - 6);
- }
- }
- } else {
- if (opc == -1) {
- tcg_out8(s, 0xe9);
- } else {
- tcg_out8(s, 0x0f);
- tcg_out8(s, 0x80 + opc);
- }
- tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
- s->code_ptr += 4;
- }
-}
-
-static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
- int const_arg2, int rexw)
-{
- if (const_arg2) {
- if (arg2 == 0) {
- /* test r, r */
- tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
- } else {
- if (rexw) {
- tgen_arithi64(s, ARITH_CMP, arg1, arg2);
- } else {
- tgen_arithi32(s, ARITH_CMP, arg1, arg2);
- }
- }
- } else {
- tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
- }
-}
-
-static void tcg_out_brcond(TCGContext *s, TCGCond cond,
- TCGArg arg1, TCGArg arg2, int const_arg2,
- int label_index, int rexw)
-{
- tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
- tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
-}
-
-static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg dest,
- TCGArg arg1, TCGArg arg2, int const_arg2, int rexw)
-{
- tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
- /* setcc */
- tcg_out_modrm(s, 0x90 | tcg_cond_to_jcc[cond] | P_EXT | P_REXB_RM, 0, dest);
- tgen_arithi32(s, ARITH_AND, dest, 0xff);
-}
-
-#if defined(CONFIG_SOFTMMU)
-
-#include "../../softmmu_defs.h"
-
-static void *qemu_ld_helpers[4] = {
- __ldb_mmu,
- __ldw_mmu,
- __ldl_mmu,
- __ldq_mmu,
-};
-
-static void *qemu_st_helpers[4] = {
- __stb_mmu,
- __stw_mmu,
- __stl_mmu,
- __stq_mmu,
-};
-#endif
-
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
- int opc)
-{
- int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
- int32_t offset;
-#if defined(CONFIG_SOFTMMU)
- uint8_t *label1_ptr, *label2_ptr;
-#endif
-
- data_reg = *args++;
- addr_reg = *args++;
- mem_index = *args;
- s_bits = opc & 3;
-
- r0 = TCG_REG_RDI;
- r1 = TCG_REG_RSI;
-
-#if TARGET_LONG_BITS == 32
- rexw = 0;
-#else
- rexw = P_REXW;
-#endif
-#if defined(CONFIG_SOFTMMU)
- tcg_out_mov(s, TCG_TYPE_TL, r1, addr_reg);
- tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
-
- tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
- tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
-
- tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
- tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
-
- tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
- tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
-
- /* lea offset(r1, env), r1 */
- tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
- offsetof(CPUState, tlb_table[mem_index][0].addr_read));
-
- /* cmp 0(r1), r0 */
- tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
-
- tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
-
- /* je label1 */
- tcg_out8(s, 0x70 + JCC_JE);
- label1_ptr = s->code_ptr;
- s->code_ptr++;
-
- /* XXX: move that code at the end of the TB */
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
- tcg_out_goto(s, 1, qemu_ld_helpers[s_bits]);
-
- switch(opc) {
- case 0 | 4:
- /* movsbq */
- tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
- break;
- case 1 | 4:
- /* movswq */
- tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
- break;
- case 2 | 4:
- /* movslq */
- tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
- break;
- case 0:
- /* movzbq */
- tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
- break;
- case 1:
- /* movzwq */
- tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
- break;
- case 2:
- default:
- tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_RAX);
- break;
- case 3:
- tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);
- break;
- }
-
- /* jmp label2 */
- tcg_out8(s, 0xeb);
- label2_ptr = s->code_ptr;
- s->code_ptr++;
-
- /* label1: */
- *label1_ptr = s->code_ptr - label1_ptr - 1;
-
- /* add x(r1), r0 */
- tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
- offsetof(CPUTLBEntry, addr_read));
- offset = 0;
-#else
- if (GUEST_BASE == (int32_t)GUEST_BASE) {
- r0 = addr_reg;
- offset = GUEST_BASE;
- } else {
- offset = 0;
- /* movq $GUEST_BASE, r0 */
- tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
- tcg_out32(s, GUEST_BASE);
- tcg_out32(s, GUEST_BASE >> 32);
- /* addq addr_reg, r0 */
- tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
- }
-#endif
-
-#ifdef TARGET_WORDS_BIGENDIAN
- bswap = 1;
-#else
- bswap = 0;
-#endif
- switch(opc) {
- case 0:
- /* movzbl */
- tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset);
- break;
- case 0 | 4:
- /* movsbX */
- tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset);
- break;
- case 1:
- /* movzwl */
- tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
- if (bswap) {
- /* rolw $8, data_reg */
- tcg_out8(s, 0x66);
- tcg_out_modrm(s, 0xc1, 0, data_reg);
- tcg_out8(s, 8);
- }
- break;
- case 1 | 4:
- if (bswap) {
- /* movzwl */
- tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
- /* rolw $8, data_reg */
- tcg_out8(s, 0x66);
- tcg_out_modrm(s, 0xc1, 0, data_reg);
- tcg_out8(s, 8);
-
- /* movswX data_reg, data_reg */
- tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
- } else {
- /* movswX */
- tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset);
- }
- break;
- case 2:
- /* movl (r0), data_reg */
- tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
- if (bswap) {
- /* bswap */
- tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
- }
- break;
- case 2 | 4:
- if (bswap) {
- /* movl (r0), data_reg */
- tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
- /* bswap */
- tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
- /* movslq */
- tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
- } else {
- /* movslq */
- tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset);
- }
- break;
- case 3:
- /* movq (r0), data_reg */
- tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset);
- if (bswap) {
- /* bswap */
- tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
- }
- break;
- default:
- tcg_abort();
- }
-
-#if defined(CONFIG_SOFTMMU)
- /* label2: */
- *label2_ptr = s->code_ptr - label2_ptr - 1;
-#endif
-}
-
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
- int opc)
-{
- int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
- int32_t offset;
-#if defined(CONFIG_SOFTMMU)
- uint8_t *label1_ptr, *label2_ptr;
-#endif
-
- data_reg = *args++;
- addr_reg = *args++;
- mem_index = *args;
-
- s_bits = opc;
-
- r0 = TCG_REG_RDI;
- r1 = TCG_REG_RSI;
-
-#if TARGET_LONG_BITS == 32
- rexw = 0;
-#else
- rexw = P_REXW;
-#endif
-#if defined(CONFIG_SOFTMMU)
- tcg_out_mov(s, TCG_TYPE_TL, r1, addr_reg);
- tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
-
- tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
- tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
-
- tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
- tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
-
- tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
- tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
-
- /* lea offset(r1, env), r1 */
- tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
- offsetof(CPUState, tlb_table[mem_index][0].addr_write));
-
- /* cmp 0(r1), r0 */
- tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
-
- tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
-
- /* je label1 */
- tcg_out8(s, 0x70 + JCC_JE);
- label1_ptr = s->code_ptr;
- s->code_ptr++;
-
- /* XXX: move that code at the end of the TB */
- switch(opc) {
- case 0:
- /* movzbl */
- tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, TCG_REG_RSI, data_reg);
- break;
- case 1:
- /* movzwl */
- tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
- break;
- case 2:
- tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_RSI, data_reg);
- break;
- default:
- case 3:
- tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_RSI, data_reg);
- break;
- }
- tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
- tcg_out_goto(s, 1, qemu_st_helpers[s_bits]);
-
- /* jmp label2 */
- tcg_out8(s, 0xeb);
- label2_ptr = s->code_ptr;
- s->code_ptr++;
-
- /* label1: */
- *label1_ptr = s->code_ptr - label1_ptr - 1;
-
- /* add x(r1), r0 */
- tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
- offsetof(CPUTLBEntry, addr_write));
- offset = 0;
-#else
- if (GUEST_BASE == (int32_t)GUEST_BASE) {
- r0 = addr_reg;
- offset = GUEST_BASE;
- } else {
- offset = 0;
- /* movq $GUEST_BASE, r0 */
- tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
- tcg_out32(s, GUEST_BASE);
- tcg_out32(s, GUEST_BASE >> 32);
- /* addq addr_reg, r0 */
- tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
- }
-#endif
-
-#ifdef TARGET_WORDS_BIGENDIAN
- bswap = 1;
-#else
- bswap = 0;
-#endif
- switch(opc) {
- case 0:
- /* movb */
- tcg_out_modrm_offset(s, 0x88 | P_REXB_R, data_reg, r0, offset);
- break;
- case 1:
- if (bswap) {
- tcg_out_mov(s, TCG_TYPE_I32, r1, data_reg);
- tcg_out8(s, 0x66); /* rolw $8, %ecx */
- tcg_out_modrm(s, 0xc1, 0, r1);
- tcg_out8(s, 8);
- data_reg = r1;
- }
- /* movw */
- tcg_out8(s, 0x66);
- tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
- break;
- case 2:
- if (bswap) {
- tcg_out_mov(s, TCG_TYPE_I32, r1, data_reg);
- /* bswap data_reg */
- tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
- data_reg = r1;
- }
- /* movl */
- tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
- break;
- case 3:
- if (bswap) {
- tcg_out_mov(s, TCG_TYPE_I64, r1, data_reg);
- /* bswap data_reg */
- tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
- data_reg = r1;
- }
- /* movq */
- tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset);
- break;
- default:
- tcg_abort();
- }
-
-#if defined(CONFIG_SOFTMMU)
- /* label2: */
- *label2_ptr = s->code_ptr - label2_ptr - 1;
-#endif
-}
-
-static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
- const int *const_args)
-{
- int c;
-
- switch(opc) {
- case INDEX_op_exit_tb:
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
- tcg_out_goto(s, 0, tb_ret_addr);
- break;
- case INDEX_op_goto_tb:
- if (s->tb_jmp_offset) {
- /* direct jump method */
- tcg_out8(s, 0xe9); /* jmp im */
- s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
- tcg_out32(s, 0);
- } else {
- /* indirect jump method */
- /* jmp Ev */
- tcg_out_modrm_offset(s, 0xff, 4, -1,
- (tcg_target_long)(s->tb_next +
- args[0]));
- }
- s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
- break;
- case INDEX_op_call:
- if (const_args[0]) {
- tcg_out_goto(s, 1, (void *) args[0]);
- } else {
- tcg_out_modrm(s, 0xff, 2, args[0]);
- }
- break;
- case INDEX_op_jmp:
- if (const_args[0]) {
- tcg_out_goto(s, 0, (void *) args[0]);
- } else {
- tcg_out_modrm(s, 0xff, 4, args[0]);
- }
- break;
- case INDEX_op_br:
- tcg_out_jxx(s, JCC_JMP, args[0]);
- break;
- case INDEX_op_movi_i32:
- tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
- break;
- case INDEX_op_movi_i64:
- tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
- break;
- case INDEX_op_ld8u_i32:
- case INDEX_op_ld8u_i64:
- /* movzbl */
- tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld8s_i32:
- /* movsbl */
- tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld8s_i64:
- /* movsbq */
- tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld16u_i32:
- case INDEX_op_ld16u_i64:
- /* movzwl */
- tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld16s_i32:
- /* movswl */
- tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld16s_i64:
- /* movswq */
- tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld_i32:
- case INDEX_op_ld32u_i64:
- /* movl */
- tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld32s_i64:
- /* movslq */
- tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
- break;
- case INDEX_op_ld_i64:
- /* movq */
- tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_st8_i32:
- case INDEX_op_st8_i64:
- /* movb */
- tcg_out_modrm_offset(s, 0x88 | P_REXB_R, args[0], args[1], args[2]);
- break;
- case INDEX_op_st16_i32:
- case INDEX_op_st16_i64:
- /* movw */
- tcg_out8(s, 0x66);
- tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i32:
- case INDEX_op_st32_i64:
- /* movl */
- tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
- break;
- case INDEX_op_st_i64:
- /* movq */
- tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
- break;
-
- case INDEX_op_sub_i32:
- c = ARITH_SUB;
- goto gen_arith32;
- case INDEX_op_and_i32:
- c = ARITH_AND;
- goto gen_arith32;
- case INDEX_op_or_i32:
- c = ARITH_OR;
- goto gen_arith32;
- case INDEX_op_xor_i32:
- c = ARITH_XOR;
- goto gen_arith32;
- case INDEX_op_add_i32:
- c = ARITH_ADD;
- gen_arith32:
- if (const_args[2]) {
- tgen_arithi32(s, c, args[0], args[2]);
- } else {
- tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
- }
- break;
-
- case INDEX_op_sub_i64:
- c = ARITH_SUB;
- goto gen_arith64;
- case INDEX_op_and_i64:
- c = ARITH_AND;
- goto gen_arith64;
- case INDEX_op_or_i64:
- c = ARITH_OR;
- goto gen_arith64;
- case INDEX_op_xor_i64:
- c = ARITH_XOR;
- goto gen_arith64;
- case INDEX_op_add_i64:
- c = ARITH_ADD;
- gen_arith64:
- if (const_args[2]) {
- tgen_arithi64(s, c, args[0], args[2]);
- } else {
- tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
- }
- break;
-
- case INDEX_op_mul_i32:
- if (const_args[2]) {
- int32_t val;
- val = args[2];
- if (val == (int8_t)val) {
- tcg_out_modrm(s, 0x6b, args[0], args[0]);
- tcg_out8(s, val);
- } else {
- tcg_out_modrm(s, 0x69, args[0], args[0]);
- tcg_out32(s, val);
- }
- } else {
- tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
- }
- break;
- case INDEX_op_mul_i64:
- if (const_args[2]) {
- int32_t val;
- val = args[2];
- if (val == (int8_t)val) {
- tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
- tcg_out8(s, val);
- } else {
- tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
- tcg_out32(s, val);
- }
- } else {
- tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
- }
- break;
- case INDEX_op_div2_i32:
- tcg_out_modrm(s, 0xf7, 7, args[4]);
- break;
- case INDEX_op_divu2_i32:
- tcg_out_modrm(s, 0xf7, 6, args[4]);
- break;
- case INDEX_op_div2_i64:
- tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
- break;
- case INDEX_op_divu2_i64:
- tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
- break;
-
- case INDEX_op_shl_i32:
- c = SHIFT_SHL;
- gen_shift32:
- if (const_args[2]) {
- if (args[2] == 1) {
- tcg_out_modrm(s, 0xd1, c, args[0]);
- } else {
- tcg_out_modrm(s, 0xc1, c, args[0]);
- tcg_out8(s, args[2]);
- }
- } else {
- tcg_out_modrm(s, 0xd3, c, args[0]);
- }
- break;
- case INDEX_op_shr_i32:
- c = SHIFT_SHR;
- goto gen_shift32;
- case INDEX_op_sar_i32:
- c = SHIFT_SAR;
- goto gen_shift32;
- case INDEX_op_rotl_i32:
- c = SHIFT_ROL;
- goto gen_shift32;
- case INDEX_op_rotr_i32:
- c = SHIFT_ROR;
- goto gen_shift32;
-
- case INDEX_op_shl_i64:
- c = SHIFT_SHL;
- gen_shift64:
- if (const_args[2]) {
- if (args[2] == 1) {
- tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
- } else {
- tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
- tcg_out8(s, args[2]);
- }
- } else {
- tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
- }
- break;
- case INDEX_op_shr_i64:
- c = SHIFT_SHR;
- goto gen_shift64;
- case INDEX_op_sar_i64:
- c = SHIFT_SAR;
- goto gen_shift64;
- case INDEX_op_rotl_i64:
- c = SHIFT_ROL;
- goto gen_shift64;
- case INDEX_op_rotr_i64:
- c = SHIFT_ROR;
- goto gen_shift64;
-
- case INDEX_op_brcond_i32:
- tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
- args[3], 0);
- break;
- case INDEX_op_brcond_i64:
- tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
- args[3], P_REXW);
- break;
-
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap16_i64:
- tcg_out8(s, 0x66);
- tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
- tcg_out8(s, 8);
- break;
- case INDEX_op_bswap32_i32:
- case INDEX_op_bswap32_i64:
- tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
- break;
- case INDEX_op_bswap64_i64:
- tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
- break;
-
- case INDEX_op_neg_i32:
- tcg_out_modrm(s, 0xf7, 3, args[0]);
- break;
- case INDEX_op_neg_i64:
- tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
- break;
-
- case INDEX_op_not_i32:
- tcg_out_modrm(s, 0xf7, 2, args[0]);
- break;
- case INDEX_op_not_i64:
- tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]);
- break;
-
- case INDEX_op_ext8s_i32:
- tcg_out_modrm(s, 0xbe | P_EXT | P_REXB_RM, args[0], args[1]);
- break;
- case INDEX_op_ext16s_i32:
- tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
- break;
- case INDEX_op_ext8s_i64:
- tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
- break;
- case INDEX_op_ext16s_i64:
- tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
- break;
- case INDEX_op_ext32s_i64:
- tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
- break;
- case INDEX_op_ext8u_i32:
- case INDEX_op_ext8u_i64:
- tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, args[0], args[1]);
- break;
- case INDEX_op_ext16u_i32:
- case INDEX_op_ext16u_i64:
- tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]);
- break;
- case INDEX_op_ext32u_i64:
- tcg_out_modrm(s, 0x8b, args[0], args[1]);
- break;
-
- case INDEX_op_setcond_i32:
- tcg_out_setcond(s, args[3], args[0], args[1], args[2],
- const_args[2], 0);
- break;
- case INDEX_op_setcond_i64:
- tcg_out_setcond(s, args[3], args[0], args[1], args[2],
- const_args[2], P_REXW);
- break;
-
- case INDEX_op_qemu_ld8u:
- tcg_out_qemu_ld(s, args, 0);
- break;
- case INDEX_op_qemu_ld8s:
- tcg_out_qemu_ld(s, args, 0 | 4);
- break;
- case INDEX_op_qemu_ld16u:
- tcg_out_qemu_ld(s, args, 1);
- break;
- case INDEX_op_qemu_ld16s:
- tcg_out_qemu_ld(s, args, 1 | 4);
- break;
- case INDEX_op_qemu_ld32:
- case INDEX_op_qemu_ld32u:
- tcg_out_qemu_ld(s, args, 2);
- break;
- case INDEX_op_qemu_ld32s:
- tcg_out_qemu_ld(s, args, 2 | 4);
- break;
- case INDEX_op_qemu_ld64:
- tcg_out_qemu_ld(s, args, 3);
- break;
-
- case INDEX_op_qemu_st8:
- tcg_out_qemu_st(s, args, 0);
- break;
- case INDEX_op_qemu_st16:
- tcg_out_qemu_st(s, args, 1);
- break;
- case INDEX_op_qemu_st32:
- tcg_out_qemu_st(s, args, 2);
- break;
- case INDEX_op_qemu_st64:
- tcg_out_qemu_st(s, args, 3);
- break;
-
- default:
- tcg_abort();
- }
-}
-
-static int tcg_target_callee_save_regs[] = {
- TCG_REG_RBP,
- TCG_REG_RBX,
- TCG_REG_R12,
- TCG_REG_R13,
- /* TCG_REG_R14, */ /* currently used for the global env, so no
- need to save */
- TCG_REG_R15,
-};
-
-static inline void tcg_out_push(TCGContext *s, int reg)
-{
- tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
-}
-
-static inline void tcg_out_pop(TCGContext *s, int reg)
-{
- tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
-}
-
-/* Generate global QEMU prologue and epilogue code */
-static void tcg_target_qemu_prologue(TCGContext *s)
-{
- int i, frame_size, push_size, stack_addend;
-
- /* TB prologue */
- /* save all callee saved registers */
- for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
- tcg_out_push(s, tcg_target_callee_save_regs[i]);
-
- }
- /* reserve some stack space */
- push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
- frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
- frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
- ~(TCG_TARGET_STACK_ALIGN - 1);
- stack_addend = frame_size - push_size;
- tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
-
- tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
-
- /* TB epilogue */
- tb_ret_addr = s->code_ptr;
- tcg_out_addi(s, TCG_REG_RSP, stack_addend);
- for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
- tcg_out_pop(s, tcg_target_callee_save_regs[i]);
- }
- tcg_out8(s, 0xc3); /* ret */
-}
-
-static const TCGTargetOpDef x86_64_op_defs[] = {
- { INDEX_op_exit_tb, { } },
- { INDEX_op_goto_tb, { } },
- { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
- { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
- { INDEX_op_br, { } },
-
- { INDEX_op_mov_i32, { "r", "r" } },
- { INDEX_op_movi_i32, { "r" } },
- { INDEX_op_ld8u_i32, { "r", "r" } },
- { INDEX_op_ld8s_i32, { "r", "r" } },
- { INDEX_op_ld16u_i32, { "r", "r" } },
- { INDEX_op_ld16s_i32, { "r", "r" } },
- { INDEX_op_ld_i32, { "r", "r" } },
- { INDEX_op_st8_i32, { "r", "r" } },
- { INDEX_op_st16_i32, { "r", "r" } },
- { INDEX_op_st_i32, { "r", "r" } },
-
- { INDEX_op_add_i32, { "r", "0", "ri" } },
- { INDEX_op_mul_i32, { "r", "0", "ri" } },
- { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
- { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
- { INDEX_op_sub_i32, { "r", "0", "ri" } },
- { INDEX_op_and_i32, { "r", "0", "ri" } },
- { INDEX_op_or_i32, { "r", "0", "ri" } },
- { INDEX_op_xor_i32, { "r", "0", "ri" } },
-
- { INDEX_op_shl_i32, { "r", "0", "ci" } },
- { INDEX_op_shr_i32, { "r", "0", "ci" } },
- { INDEX_op_sar_i32, { "r", "0", "ci" } },
- { INDEX_op_rotl_i32, { "r", "0", "ci" } },
- { INDEX_op_rotr_i32, { "r", "0", "ci" } },
-
- { INDEX_op_brcond_i32, { "r", "ri" } },
-
- { INDEX_op_mov_i64, { "r", "r" } },
- { INDEX_op_movi_i64, { "r" } },
- { INDEX_op_ld8u_i64, { "r", "r" } },
- { INDEX_op_ld8s_i64, { "r", "r" } },
- { INDEX_op_ld16u_i64, { "r", "r" } },
- { INDEX_op_ld16s_i64, { "r", "r" } },
- { INDEX_op_ld32u_i64, { "r", "r" } },
- { INDEX_op_ld32s_i64, { "r", "r" } },
- { INDEX_op_ld_i64, { "r", "r" } },
- { INDEX_op_st8_i64, { "r", "r" } },
- { INDEX_op_st16_i64, { "r", "r" } },
- { INDEX_op_st32_i64, { "r", "r" } },
- { INDEX_op_st_i64, { "r", "r" } },
-
- { INDEX_op_add_i64, { "r", "0", "re" } },
- { INDEX_op_mul_i64, { "r", "0", "re" } },
- { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
- { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
- { INDEX_op_sub_i64, { "r", "0", "re" } },
- { INDEX_op_and_i64, { "r", "0", "reZ" } },
- { INDEX_op_or_i64, { "r", "0", "re" } },
- { INDEX_op_xor_i64, { "r", "0", "re" } },
-
- { INDEX_op_shl_i64, { "r", "0", "ci" } },
- { INDEX_op_shr_i64, { "r", "0", "ci" } },
- { INDEX_op_sar_i64, { "r", "0", "ci" } },
- { INDEX_op_rotl_i64, { "r", "0", "ci" } },
- { INDEX_op_rotr_i64, { "r", "0", "ci" } },
-
- { INDEX_op_brcond_i64, { "r", "re" } },
-
- { INDEX_op_bswap16_i32, { "r", "0" } },
- { INDEX_op_bswap16_i64, { "r", "0" } },
- { INDEX_op_bswap32_i32, { "r", "0" } },
- { INDEX_op_bswap32_i64, { "r", "0" } },
- { INDEX_op_bswap64_i64, { "r", "0" } },
-
- { INDEX_op_neg_i32, { "r", "0" } },
- { INDEX_op_neg_i64, { "r", "0" } },
-
- { INDEX_op_not_i32, { "r", "0" } },
- { INDEX_op_not_i64, { "r", "0" } },
-
- { INDEX_op_ext8s_i32, { "r", "r"} },
- { INDEX_op_ext16s_i32, { "r", "r"} },
- { INDEX_op_ext8s_i64, { "r", "r"} },
- { INDEX_op_ext16s_i64, { "r", "r"} },
- { INDEX_op_ext32s_i64, { "r", "r"} },
- { INDEX_op_ext8u_i32, { "r", "r"} },
- { INDEX_op_ext16u_i32, { "r", "r"} },
- { INDEX_op_ext8u_i64, { "r", "r"} },
- { INDEX_op_ext16u_i64, { "r", "r"} },
- { INDEX_op_ext32u_i64, { "r", "r"} },
-
- { INDEX_op_setcond_i32, { "r", "r", "ri" } },
- { INDEX_op_setcond_i64, { "r", "r", "re" } },
-
- { INDEX_op_qemu_ld8u, { "r", "L" } },
- { INDEX_op_qemu_ld8s, { "r", "L" } },
- { INDEX_op_qemu_ld16u, { "r", "L" } },
- { INDEX_op_qemu_ld16s, { "r", "L" } },
- { INDEX_op_qemu_ld32, { "r", "L" } },
- { INDEX_op_qemu_ld32u, { "r", "L" } },
- { INDEX_op_qemu_ld32s, { "r", "L" } },
- { INDEX_op_qemu_ld64, { "r", "L" } },
-
- { INDEX_op_qemu_st8, { "L", "L" } },
- { INDEX_op_qemu_st16, { "L", "L" } },
- { INDEX_op_qemu_st32, { "L", "L" } },
- { INDEX_op_qemu_st64, { "L", "L" } },
-
- { -1 },
-};
-
-static void tcg_target_init(TCGContext *s)
-{
-#if !defined(CONFIG_USER_ONLY)
- /* fail safe */
- if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
- tcg_abort();
-#endif
-
- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
- tcg_regset_set32(tcg_target_call_clobber_regs, 0,
- (1 << TCG_REG_RDI) |
- (1 << TCG_REG_RSI) |
- (1 << TCG_REG_RDX) |
- (1 << TCG_REG_RCX) |
- (1 << TCG_REG_R8) |
- (1 << TCG_REG_R9) |
- (1 << TCG_REG_RAX) |
- (1 << TCG_REG_R10) |
- (1 << TCG_REG_R11));
-
- tcg_regset_clear(s->reserved_regs);
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
-
- tcg_add_target_add_op_defs(x86_64_op_defs);
-}
diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h
deleted file mode 100644
index e0eabaa..0000000
--- a/tcg/x86_64/tcg-target.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Tiny Code Generator for QEMU
- *
- * Copyright (c) 2008 Fabrice Bellard
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-#define TCG_TARGET_X86_64 1
-
-#define TCG_TARGET_REG_BITS 64
-//#define TCG_TARGET_WORDS_BIGENDIAN
-
-#define TCG_TARGET_NB_REGS 16
-
-enum {
- TCG_REG_RAX = 0,
- TCG_REG_RCX,
- TCG_REG_RDX,
- TCG_REG_RBX,
- TCG_REG_RSP,
- TCG_REG_RBP,
- TCG_REG_RSI,
- TCG_REG_RDI,
- TCG_REG_R8,
- TCG_REG_R9,
- TCG_REG_R10,
- TCG_REG_R11,
- TCG_REG_R12,
- TCG_REG_R13,
- TCG_REG_R14,
- TCG_REG_R15,
-};
-
-#define TCG_CT_CONST_S32 0x100
-#define TCG_CT_CONST_U32 0x200
-
-/* used for function call generation */
-#define TCG_REG_CALL_STACK TCG_REG_RSP
-#define TCG_TARGET_STACK_ALIGN 16
-#define TCG_TARGET_CALL_STACK_OFFSET 0
-
-/* optional instructions */
-#define TCG_TARGET_HAS_div2_i32
-#define TCG_TARGET_HAS_div2_i64
-#define TCG_TARGET_HAS_bswap16_i32
-#define TCG_TARGET_HAS_bswap16_i64
-#define TCG_TARGET_HAS_bswap32_i32
-#define TCG_TARGET_HAS_bswap32_i64
-#define TCG_TARGET_HAS_bswap64_i64
-#define TCG_TARGET_HAS_neg_i32
-#define TCG_TARGET_HAS_neg_i64
-#define TCG_TARGET_HAS_not_i32
-#define TCG_TARGET_HAS_not_i64
-#define TCG_TARGET_HAS_ext8s_i32
-#define TCG_TARGET_HAS_ext16s_i32
-#define TCG_TARGET_HAS_ext8s_i64
-#define TCG_TARGET_HAS_ext16s_i64
-#define TCG_TARGET_HAS_ext32s_i64
-#define TCG_TARGET_HAS_ext8u_i32
-#define TCG_TARGET_HAS_ext16u_i32
-#define TCG_TARGET_HAS_ext8u_i64
-#define TCG_TARGET_HAS_ext16u_i64
-#define TCG_TARGET_HAS_ext32u_i64
-#define TCG_TARGET_HAS_rot_i32
-#define TCG_TARGET_HAS_rot_i64
-
-// #define TCG_TARGET_HAS_andc_i32
-// #define TCG_TARGET_HAS_andc_i64
-// #define TCG_TARGET_HAS_orc_i32
-// #define TCG_TARGET_HAS_orc_i64
-// #define TCG_TARGET_HAS_eqv_i32
-// #define TCG_TARGET_HAS_eqv_i64
-// #define TCG_TARGET_HAS_nand_i32
-// #define TCG_TARGET_HAS_nand_i64
-// #define TCG_TARGET_HAS_nor_i32
-// #define TCG_TARGET_HAS_nor_i64
-
-#define TCG_TARGET_HAS_GUEST_BASE
-
-/* Note: must be synced with dyngen-exec.h */
-#define TCG_AREG0 TCG_REG_R14
-
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
-}
--
1.7.0.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH 2/2] tcg-i386: Use segment registers to implement GUEST_BASE.
2010-06-04 0:35 ` [Qemu-devel] [PATCH 0/2] tcg-i386: merge 64-bit, guest_base improvement Richard Henderson
2010-06-04 0:35 ` [Qemu-devel] [PATCH 1/2] tcg-i386: Merge 64-bit generation Richard Henderson
@ 2010-06-04 0:35 ` Richard Henderson
2010-06-04 6:35 ` Alexander Graf
1 sibling, 1 reply; 13+ messages in thread
From: Richard Henderson @ 2010-06-04 0:35 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
For 32-bit, using a segment override is smaller than the 4-byte
immediate offset. For 64-bit, segments can hold the entire 64-bit
offset whereas the 4-byte immediate cannot.
Only implemented for linux, with fallback to the immediate offset
if the system call fails.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/i386/tcg-target.c | 206 +++++++++++++++++++++++++++++++++++-------------
1 files changed, 150 insertions(+), 56 deletions(-)
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index fab2a30..e34254f 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -240,6 +240,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
# define P_REXB_R 0
# define P_REXB_RM 0
#endif
+#define P_FS 0x4000
+#define P_GS 0x8000
#define OPC_ARITH_EvIz (0x81)
#define OPC_ARITH_EvIb (0x83)
@@ -347,11 +349,29 @@ static const uint8_t tcg_cond_to_jcc[10] = {
[TCG_COND_GTU] = JCC_JA,
};
+static inline void tcg_out_seg_prefix(TCGContext *s, int opc)
+{
+ switch (opc & (P_FS | P_GS)) {
+ case 0:
+ break;
+ case P_FS:
+ tcg_out8(s, 0x64);
+ break;
+ case P_GS:
+ tcg_out8(s, 0x65);
+ break;
+ default:
+ tcg_abort();
+ }
+}
+
#if TCG_TARGET_REG_BITS == 64
static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
{
int rex;
+ tcg_out_seg_prefix(s, opc);
+
if (opc & P_DATA16) {
/* We should never be asking for both 16 and 64-bit operation. */
assert((opc & P_REXW) == 0);
@@ -387,6 +407,8 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
#else
static void tcg_out_opc(TCGContext *s, int opc)
{
+ tcg_out_seg_prefix(s, opc);
+
if (opc & P_DATA16) {
tcg_out8(s, 0x66);
}
@@ -956,6 +978,48 @@ static void tcg_out_jmp(TCGContext *s, tcg_target_long dest)
tcg_out_branch(s, 0, dest);
}
+#ifndef GUEST_BASE
+#define GUEST_BASE 0
+#endif
+
+#if defined(__x86_64__) && defined(__linux__)
+# include <sys/syscall.h>
+# include <asm/prctl.h>
+
+static int guest_base_flags;
+static inline void setup_guest_base_seg(void)
+{
+ if (syscall(__NR_arch_prctl, ARCH_SET_GS, GUEST_BASE) == 0) {
+ guest_base_flags = P_GS;
+ }
+}
+#elif defined(__i386__) && defined(__linux__)
+# include <sys/syscall.h>
+# include <asm/ldt.h>
+
+static int guest_base_flags;
+static inline void setup_guest_base_seg(void)
+{
+ struct user_desc d;
+
+ memset(&d, 0, sizeof(d));
+ d.entry_number = -1; /* let the kernel choose */
+ d.base_addr = GUEST_BASE;
+ d.limit = 0xfffff; /* 4GB segment */
+ d.seg_32bit = 1;
+ d.limit_in_pages = 1;
+ d.useable = 1;
+
+ if (syscall(__NR_set_thread_area, &d) == 0) {
+ asm volatile("movw %w0, %%fs" : : "r"(d.entry_number * 8 + 3));
+ guest_base_flags = P_FS;
+ }
+}
+#else
+# define guest_base_flags 0
+static inline void setup_guest_base_seg(void) { }
+#endif
+
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
@@ -1056,37 +1120,41 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
#endif
static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
- int base, tcg_target_long ofs, int sizeop)
+ int base, tcg_target_long ofs, int sizeop,
+ int prefix)
{
#ifdef TARGET_WORDS_BIGENDIAN
const int bswap = 1;
#else
const int bswap = 0;
#endif
+ int rexw = (TARGET_LONG_BITS == 64 ? P_REXW : 0);
+
switch (sizeop) {
case 0:
- tcg_out_modrm_offset(s, OPC_MOVZBL, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVZBL + prefix, datalo, base, ofs);
break;
case 0 | 4:
- tcg_out_modrm_offset(s, OPC_MOVSBL + P_REXW, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVSBL + prefix + rexw, datalo, base, ofs);
break;
case 1:
- tcg_out_modrm_offset(s, OPC_MOVZWL, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVZWL + prefix, datalo, base, ofs);
if (bswap) {
tcg_out_rolw_8(s, datalo);
}
break;
case 1 | 4:
if (bswap) {
- tcg_out_modrm_offset(s, OPC_MOVZWL, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVZWL + prefix, datalo, base, ofs);
tcg_out_rolw_8(s, datalo);
- tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo);
+ tcg_out_modrm(s, OPC_MOVSWL + rexw, datalo, datalo);
} else {
- tcg_out_modrm_offset(s, OPC_MOVSWL + P_REXW, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVSWL + prefix + rexw,
+ datalo, base, ofs);
}
break;
case 2:
- tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv + prefix, datalo, base, ofs);
if (bswap) {
tcg_out_bswap32(s, datalo);
}
@@ -1094,17 +1162,18 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
#if TCG_TARGET_REG_BITS == 64
case 2 | 4:
if (bswap) {
- tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv + prefix, datalo, base, ofs);
tcg_out_bswap32(s, datalo);
tcg_out_ext32s(s, datalo, datalo);
} else {
- tcg_out_modrm_offset(s, OPC_MOVSLQ, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVSLQ + prefix, datalo, base, ofs);
}
break;
#endif
case 3:
if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_ld(s, TCG_TYPE_I64, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv + prefix + P_REXW,
+ datalo, base, ofs);
if (bswap) {
tcg_out_bswap64(s, datalo);
}
@@ -1115,11 +1184,15 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
datahi = t;
}
if (base != datalo) {
- tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
- tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv + prefix,
+ datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv + prefix,
+ datahi, base, ofs + 4);
} else {
- tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
- tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv + prefix,
+ datahi, base, ofs + 4);
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv + prefix,
+ datalo, base, ofs);
}
if (bswap) {
tcg_out_bswap32(s, datalo);
@@ -1135,8 +1208,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
EAX. It will be useful once fixed registers globals are less
common. */
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
- int opc)
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
{
int data_reg, data_reg2 = 0;
int addrlo_idx;
@@ -1161,7 +1233,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
/* TLB Hit. */
tcg_out_qemu_ld_direct(s, data_reg, data_reg2,
- tcg_target_call_iarg_regs[0], 0, opc);
+ tcg_target_call_iarg_regs[0], 0, opc, 0);
/* jmp label2 */
tcg_out8(s, OPC_JMP_short);
@@ -1230,28 +1302,32 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
{
int32_t offset = GUEST_BASE;
int base = args[addrlo_idx];
-
- if (TCG_TARGET_REG_BITS == 64) {
- /* ??? We assume all operations have left us with register
- contents that are zero extended. So far this appears to
- be true. If we want to enforce this, we can either do
- an explicit zero-extension here, or (if GUEST_BASE == 0)
- use the ADDR32 prefix. For now, do nothing. */
-
- if (offset != GUEST_BASE) {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE);
- tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base);
- base = TCG_REG_RDI, offset = 0;
- }
+ int prefix = 0;
+
+ /* ??? For 64-bit, we assume all operations have left us with register
+ contents that are zero extended. So far this appears to be true.
+ If we want to enforce this, we can either do an explicit zero
+ extension here, or (if GUEST_BASE == 0 or guest_base_flags) use
+ the ADDR32 prefix. For now, do nothing. */
+
+ if (GUEST_BASE && guest_base_flags) {
+ prefix = guest_base_flags;
+ offset = 0;
+ } else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE);
+ tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base);
+ base = TCG_REG_RDI, offset = 0;
}
- tcg_out_qemu_ld_direct(s, data_reg, data_reg2, base, offset, opc);
+ tcg_out_qemu_ld_direct(s, data_reg, data_reg2, base,
+ offset, opc, prefix);
}
#endif
}
static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
- int base, tcg_target_long ofs, int sizeop)
+ int base, tcg_target_long ofs, int sizeop,
+ int prefix)
{
#ifdef TARGET_WORDS_BIGENDIAN
const int bswap = 1;
@@ -1266,7 +1342,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
switch (sizeop) {
case 0:
- tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + prefix,
+ datalo, base, ofs);
break;
case 1:
if (bswap) {
@@ -1274,7 +1351,8 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
tcg_out_rolw_8(s, scratch);
datalo = scratch;
}
- tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_DATA16, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_DATA16 + prefix,
+ datalo, base, ofs);
break;
case 2:
if (bswap) {
@@ -1282,7 +1360,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
tcg_out_bswap32(s, scratch);
datalo = scratch;
}
- tcg_out_st(s, TCG_TYPE_I32, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv + prefix, datalo, base, ofs);
break;
case 3:
if (TCG_TARGET_REG_BITS == 64) {
@@ -1291,17 +1369,22 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
tcg_out_bswap64(s, scratch);
datalo = scratch;
}
- tcg_out_st(s, TCG_TYPE_I64, datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_REXW + prefix,
+ datalo, base, ofs);
} else if (bswap) {
tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi);
tcg_out_bswap32(s, scratch);
- tcg_out_st(s, TCG_TYPE_I32, scratch, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv + prefix,
+ scratch, base, ofs);
tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
tcg_out_bswap32(s, scratch);
- tcg_out_st(s, TCG_TYPE_I32, scratch, base, ofs + 4);
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv + prefix,
+ scratch, base, ofs + 4);
} else {
- tcg_out_st(s, TCG_TYPE_I32, datalo, base, ofs);
- tcg_out_st(s, TCG_TYPE_I32, datahi, base, ofs + 4);
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv + prefix,
+ datalo, base, ofs);
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv + prefix,
+ datahi, base, ofs + 4);
}
break;
default:
@@ -1336,7 +1419,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
/* TLB Hit. */
tcg_out_qemu_st_direct(s, data_reg, data_reg2,
- tcg_target_call_iarg_regs[0], 0, opc);
+ tcg_target_call_iarg_regs[0], 0, opc, 0);
/* jmp label2 */
tcg_out8(s, OPC_JMP_short);
@@ -1407,22 +1490,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
{
int32_t offset = GUEST_BASE;
int base = args[addrlo_idx];
-
- if (TCG_TARGET_REG_BITS == 64) {
- /* ??? We assume all operations have left us with register
- contents that are zero extended. So far this appears to
- be true. If we want to enforce this, we can either do
- an explicit zero-extension here, or (if GUEST_BASE == 0)
- use the ADDR32 prefix. For now, do nothing. */
-
- if (offset != GUEST_BASE) {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE);
- tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base);
- base = TCG_REG_RDI, offset = 0;
- }
+ int prefix = 0;
+
+ /* ??? For 64-bit, we assume all operations have left us with register
+ contents that are zero extended. So far this appears to be true.
+ If we want to enforce this, we can either do an explicit zero
+ extension here, or (if GUEST_BASE == 0 or guest_base_flags) use
+ the ADDR32 prefix. For now, do nothing. */
+
+ if (GUEST_BASE && guest_base_flags) {
+ prefix = guest_base_flags;
+ offset = 0;
+ } else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) {
+ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE);
+ tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base);
+ base = TCG_REG_RDI, offset = 0;
}
- tcg_out_qemu_st_direct(s, data_reg, data_reg2, base, offset, opc);
+ tcg_out_qemu_st_direct(s, data_reg, data_reg2, base,
+ offset, opc, prefix);
}
#endif
}
@@ -1945,6 +2031,14 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_pop(s, tcg_target_callee_save_regs[i]);
}
tcg_out_opc(s, OPC_RET, 0, 0, 0);
+
+ /* Try to set up %fs or %gs (whichever isn't already used for TLS)
+ to point to GUEST_BASE. The 1-byte segment override prefix is
+ always smaller than the 4-byte offset we'd have to encode into
+ the address, and is also able to handle the full 64-bit offset. */
+ if (GUEST_BASE) {
+ setup_guest_base_seg();
+ }
}
static void tcg_target_init(TCGContext *s)
--
1.7.0.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] tcg-i386: Use segment registers to implement GUEST_BASE.
2010-06-04 0:35 ` [Qemu-devel] [PATCH 2/2] tcg-i386: Use segment registers to implement GUEST_BASE Richard Henderson
@ 2010-06-04 6:35 ` Alexander Graf
2010-06-07 19:45 ` Richard Henderson
0 siblings, 1 reply; 13+ messages in thread
From: Alexander Graf @ 2010-06-04 6:35 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, aurelien
On 04.06.2010, at 02:35, Richard Henderson wrote:
> For 32-bit, using a segment override is smaller than the 4-byte
> immediate offset. For 64-bit, segments can hold the entire 64-bit
> offset whereas the 4-byte immediate cannot.
Very nice idea indeed :). Have you found it to be faster? IIRC segment accesses are slower when seg_offs != 0. But then again the code is smaller, so it might weigh it up.
> Only implemented for linux, with fallback to the immediate offset
> if the system call fails.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/i386/tcg-target.c | 206 +++++++++++++++++++++++++++++++++++-------------
> 1 files changed, 150 insertions(+), 56 deletions(-)
>
> diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
> index fab2a30..e34254f 100644
> --- a/tcg/i386/tcg-target.c
> +++ b/tcg/i386/tcg-target.c
> @@ -240,6 +240,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
> # define P_REXB_R 0
> # define P_REXB_RM 0
> #endif
> +#define P_FS 0x4000
> +#define P_GS 0x8000
>
> #define OPC_ARITH_EvIz (0x81)
> #define OPC_ARITH_EvIb (0x83)
> @@ -347,11 +349,29 @@ static const uint8_t tcg_cond_to_jcc[10] = {
> [TCG_COND_GTU] = JCC_JA,
> };
>
> +static inline void tcg_out_seg_prefix(TCGContext *s, int opc)
> +{
> + switch (opc & (P_FS | P_GS)) {
> + case 0:
> + break;
> + case P_FS:
> + tcg_out8(s, 0x64);
> + break;
> + case P_GS:
> + tcg_out8(s, 0x65);
> + break;
> + default:
> + tcg_abort();
> + }
> +}
> +
> #if TCG_TARGET_REG_BITS == 64
> static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
> {
> int rex;
>
> + tcg_out_seg_prefix(s, opc);
> +
> if (opc & P_DATA16) {
> /* We should never be asking for both 16 and 64-bit operation. */
> assert((opc & P_REXW) == 0);
> @@ -387,6 +407,8 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
> #else
> static void tcg_out_opc(TCGContext *s, int opc)
> {
> + tcg_out_seg_prefix(s, opc);
> +
> if (opc & P_DATA16) {
> tcg_out8(s, 0x66);
> }
> @@ -956,6 +978,48 @@ static void tcg_out_jmp(TCGContext *s, tcg_target_long dest)
> tcg_out_branch(s, 0, dest);
> }
>
> +#ifndef GUEST_BASE
> +#define GUEST_BASE 0
> +#endif
> +
> +#if defined(__x86_64__) && defined(__linux__)
> +# include <sys/syscall.h>
> +# include <asm/prctl.h>
> +
> +static int guest_base_flags;
> +static inline void setup_guest_base_seg(void)
> +{
> + if (syscall(__NR_arch_prctl, ARCH_SET_GS, GUEST_BASE) == 0) {
> + guest_base_flags = P_GS;
I'd like to see a comment here stating that FS is used for TLS.
> + }
> +}
> +#elif defined(__i386__) && defined(__linux__)
> +# include <sys/syscall.h>
> +# include <asm/ldt.h>
> +
> +static int guest_base_flags;
> +static inline void setup_guest_base_seg(void)
> +{
> + struct user_desc d;
> +
> + memset(&d, 0, sizeof(d));
> + d.entry_number = -1; /* let the kernel choose */
> + d.base_addr = GUEST_BASE;
> + d.limit = 0xfffff; /* 4GB segment */
> + d.seg_32bit = 1;
> + d.limit_in_pages = 1;
> + d.useable = 1;
> +
> + if (syscall(__NR_set_thread_area, &d) == 0) {
> + asm volatile("movw %w0, %%fs" : : "r"(d.entry_number * 8 + 3));
Same here for %gs.
[snip]
> @@ -1945,6 +2031,14 @@ static void tcg_target_qemu_prologue(TCGContext *s)
> tcg_out_pop(s, tcg_target_callee_save_regs[i]);
> }
> tcg_out_opc(s, OPC_RET, 0, 0, 0);
> +
> + /* Try to set up %fs or %gs (whichever isn't already used for TLS)
> + to point to GUEST_BASE. The 1-byte segment override prefix is
> + always smaller than the 4-byte offset we'd have to encode into
> + the address, and is also able to handle the full 64-bit offset. */
Ah, so that's where the comment hides. Uh. Better be safe than sorry and have it in both locations, no? :)
Alex
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] tcg: Add TYPE parameter to tcg_out_mov.
2010-06-03 0:26 ` [Qemu-devel] [PATCH 1/2] tcg: Add TYPE parameter to tcg_out_mov Richard Henderson
@ 2010-06-04 19:19 ` Blue Swirl
2010-06-04 19:34 ` Richard Henderson
0 siblings, 1 reply; 13+ messages in thread
From: Blue Swirl @ 2010-06-04 19:19 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, aurelien
On Thu, Jun 3, 2010 at 12:26 AM, Richard Henderson <rth@twiddle.net> wrote:
> Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64
> to perform the move at the proper width, which may elide a REX prefix.
>
> Introduce a TCG_TYPE_REG enumerator to represent the "native width"
> of the host register, and to distinguish the usage from "pointer data"
> as represented by the existing TCG_TYPE_PTR.
>
> Update all targets to match.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
Sparc part looks fine to me.
> +
> + /* An alias for the size of the native pointer. We don't currently
> + support any hosts with 64-bit registers and 32-bit pointers. */
Sparc32plus would match, though the ABI does not guarantee that higher
32 bits are preserved.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] tcg: Add TYPE parameter to tcg_out_mov.
2010-06-04 19:19 ` Blue Swirl
@ 2010-06-04 19:34 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2010-06-04 19:34 UTC (permalink / raw)
To: Blue Swirl; +Cc: qemu-devel, aurelien
On 06/04/2010 12:19 PM, Blue Swirl wrote:
> Sparc32plus would match, though the ABI does not guarantee that higher
> 32 bits are preserved.
Actually, it does for %g and %o registers. See section 2.1.1.
I've thought before about how to adjust the __sparcv8plus__ TCG
to use full 64-bit registers and operations when required, but
have not yet gotten around to it.
All of sparc, mips, ppc, and s390 have a mode with 32-bit pointers
running on a machine with 64-bit registers and operations available.
Unfortunately the hppa linux kernel doesn't save the full 64-bit
register on interrupt, so we're strictly limited to pa1.1 there,
even when running on a pa2 machine.
Something for the future...
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] tcg-i386: Use segment registers to implement GUEST_BASE.
2010-06-04 6:35 ` Alexander Graf
@ 2010-06-07 19:45 ` Richard Henderson
0 siblings, 0 replies; 13+ messages in thread
From: Richard Henderson @ 2010-06-07 19:45 UTC (permalink / raw)
To: Alexander Graf; +Cc: qemu-devel, aurelien
On 06/03/2010 11:35 PM, Alexander Graf wrote:
>
> On 04.06.2010, at 02:35, Richard Henderson wrote:
>
>> For 32-bit, using a segment override is smaller than the 4-byte
>> immediate offset. For 64-bit, segments can hold the entire 64-bit
>> offset whereas the 4-byte immediate cannot.
>
> Very nice idea indeed :). Have you found it to be faster? IIRC
> segment accesses are slower when seg_offs != 0. But then again the
> code is smaller, so it might weigh it up.
I've not yet tried to do any proper benchmarking.
I had thought that the segment access was slower only when limit != 4G,
i.e. when the segment boundaries need to be checked. And that 64-bit
segments don't have boundaries, so the slowdown does not apply there either.
I'll put it on my queue for the weekend.
r~
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4
2010-06-03 0:26 [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 Richard Henderson
` (3 preceding siblings ...)
2010-06-04 0:35 ` [Qemu-devel] [PATCH 0/2] tcg-i386: merge 64-bit, guest_base improvement Richard Henderson
@ 2010-06-09 9:42 ` Aurelien Jarno
4 siblings, 0 replies; 13+ messages in thread
From: Aurelien Jarno @ 2010-06-09 9:42 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Wed, Jun 02, 2010 at 05:26:54PM -0700, Richard Henderson wrote:
> The tcg_out_mov patch you've seen before, but now contains a
> TCG_TYPE_REG that should address the concerns you had with
> the changes to the sparc port. It's also been updated to HEAD
> to reflect the changes in tcg/i386.
>
> The second patch is new.
>
>
> r~
>
>
>
> Richard Henderson (2):
> tcg: Add TYPE parameter to tcg_out_mov.
> tcg: Make some tcg-target.c routines static.
>
> tcg/arm/tcg-target.c | 6 ++--
> tcg/hppa/tcg-target.c | 42 +++++++++++++++++++-------------------
> tcg/i386/tcg-target.c | 40 ++++++++++++++++++------------------
> tcg/ia64/tcg-target.c | 7 +++--
> tcg/mips/tcg-target.c | 32 ++++++++++++++--------------
> tcg/ppc/tcg-target.c | 52 +++++++++++++++++++++++-----------------------
> tcg/ppc64/tcg-target.c | 14 ++++++------
> tcg/s390/tcg-target.c | 6 ++--
> tcg/sparc/tcg-target.c | 14 ++++++------
> tcg/tcg.c | 14 +++++++-----
> tcg/tcg.h | 14 ++++++++----
> tcg/x86_64/tcg-target.c | 49 ++++++++++++++++++--------------------------
> 12 files changed, 144 insertions(+), 146 deletions(-)
>
Thanks, applied.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] tcg-i386: Merge 64-bit generation.
2010-06-04 0:35 ` [Qemu-devel] [PATCH 1/2] tcg-i386: Merge 64-bit generation Richard Henderson
@ 2010-06-09 22:18 ` Aurelien Jarno
0 siblings, 0 replies; 13+ messages in thread
From: Aurelien Jarno @ 2010-06-09 22:18 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, Jun 03, 2010 at 05:35:17PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> configure | 2 +
> tcg/i386/tcg-target.c | 1158 +++++++++++++++++++++++++++-----------
> tcg/i386/tcg-target.h | 61 ++-
> tcg/x86_64/tcg-target.c | 1445 -----------------------------------------------
> tcg/x86_64/tcg-target.h | 101 ----
> 5 files changed, 890 insertions(+), 1877 deletions(-)
> delete mode 100644 tcg/x86_64/tcg-target.c
> delete mode 100644 tcg/x86_64/tcg-target.h
Thanks, applied.
> diff --git a/configure b/configure
> index 653c8d2..1f25dba 100755
> --- a/configure
> +++ b/configure
> @@ -2635,6 +2635,8 @@ if test "$ARCH" = "sparc64" ; then
> cflags="-I\$(SRC_PATH)/tcg/sparc $cflags"
> elif test "$ARCH" = "s390x" ; then
> cflags="-I\$(SRC_PATH)/tcg/s390 $cflags"
> +elif test "$ARCH" = "x86_64" ; then
> + cflags="-I\$(SRC_PATH)/tcg/i386 $cflags"
> else
> cflags="-I\$(SRC_PATH)/tcg/\$(ARCH) $cflags"
> fi
> diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
> index 147ba17..fab2a30 100644
> --- a/tcg/i386/tcg-target.c
> +++ b/tcg/i386/tcg-target.c
> @@ -24,18 +24,33 @@
>
> #ifndef NDEBUG
> static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
> - "%eax",
> - "%ecx",
> - "%edx",
> - "%ebx",
> - "%esp",
> - "%ebp",
> - "%esi",
> - "%edi",
> +#if TCG_TARGET_REG_BITS == 64
> + "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
> + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
> +#else
> + "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
> +#endif
> };
> #endif
>
> static const int tcg_target_reg_alloc_order[] = {
> +#if TCG_TARGET_REG_BITS == 64
> + TCG_REG_RBP,
> + TCG_REG_RBX,
> + TCG_REG_R12,
> + TCG_REG_R13,
> + TCG_REG_R14,
> + TCG_REG_R15,
> + TCG_REG_R10,
> + TCG_REG_R11,
> + TCG_REG_R9,
> + TCG_REG_R8,
> + TCG_REG_RCX,
> + TCG_REG_RDX,
> + TCG_REG_RSI,
> + TCG_REG_RDI,
> + TCG_REG_RAX,
> +#else
> TCG_REG_EBX,
> TCG_REG_ESI,
> TCG_REG_EDI,
> @@ -43,10 +58,28 @@ static const int tcg_target_reg_alloc_order[] = {
> TCG_REG_ECX,
> TCG_REG_EDX,
> TCG_REG_EAX,
> +#endif
> };
>
> -static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX };
> -static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX };
> +static const int tcg_target_call_iarg_regs[] = {
> +#if TCG_TARGET_REG_BITS == 64
> + TCG_REG_RDI,
> + TCG_REG_RSI,
> + TCG_REG_RDX,
> + TCG_REG_RCX,
> + TCG_REG_R8,
> + TCG_REG_R9,
> +#else
> + TCG_REG_EAX,
> + TCG_REG_EDX,
> + TCG_REG_ECX
> +#endif
> +};
> +
> +static const int tcg_target_call_oarg_regs[2] = {
> + TCG_REG_EAX,
> + TCG_REG_EDX
> +};
>
> static uint8_t *tb_ret_addr;
>
> @@ -55,14 +88,15 @@ static void patch_reloc(uint8_t *code_ptr, int type,
> {
> value += addend;
> switch(type) {
> - case R_386_32:
> - *(uint32_t *)code_ptr = value;
> - break;
> case R_386_PC32:
> - *(uint32_t *)code_ptr = value - (long)code_ptr;
> + value -= (uintptr_t)code_ptr;
> + if (value != (int32_t)value) {
> + tcg_abort();
> + }
> + *(uint32_t *)code_ptr = value;
> break;
> case R_386_PC8:
> - value -= (long)code_ptr;
> + value -= (uintptr_t)code_ptr;
> if (value != (int8_t)value) {
> tcg_abort();
> }
> @@ -76,6 +110,10 @@ static void patch_reloc(uint8_t *code_ptr, int type,
> /* maximum number of register used for input function arguments */
> static inline int tcg_target_get_call_iarg_regs_count(int flags)
> {
> + if (TCG_TARGET_REG_BITS == 64) {
> + return 6;
> + }
> +
> flags &= TCG_CALL_TYPE_MASK;
> switch(flags) {
> case TCG_CALL_TYPE_STD:
> @@ -122,20 +160,42 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> break;
> case 'q':
> ct->ct |= TCG_CT_REG;
> - tcg_regset_set32(ct->u.regs, 0, 0xf);
> + if (TCG_TARGET_REG_BITS == 64) {
> + tcg_regset_set32(ct->u.regs, 0, 0xffff);
> + } else {
> + tcg_regset_set32(ct->u.regs, 0, 0xf);
> + }
> break;
> case 'r':
> ct->ct |= TCG_CT_REG;
> - tcg_regset_set32(ct->u.regs, 0, 0xff);
> + if (TCG_TARGET_REG_BITS == 64) {
> + tcg_regset_set32(ct->u.regs, 0, 0xffff);
> + } else {
> + tcg_regset_set32(ct->u.regs, 0, 0xff);
> + }
> break;
>
> /* qemu_ld/st address constraint */
> case 'L':
> ct->ct |= TCG_CT_REG;
> - tcg_regset_set32(ct->u.regs, 0, 0xff);
> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
> + if (TCG_TARGET_REG_BITS == 64) {
> + tcg_regset_set32(ct->u.regs, 0, 0xffff);
> + tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
> + tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
> + } else {
> + tcg_regset_set32(ct->u.regs, 0, 0xff);
> + tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX);
> + tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX);
> + }
> + break;
> +
> + case 'e':
> + ct->ct |= TCG_CT_CONST_S32;
> + break;
> + case 'Z':
> + ct->ct |= TCG_CT_CONST_U32;
> break;
> +
> default:
> return -1;
> }
> @@ -148,16 +208,38 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> static inline int tcg_target_const_match(tcg_target_long val,
> const TCGArgConstraint *arg_ct)
> {
> - int ct;
> - ct = arg_ct->ct;
> - if (ct & TCG_CT_CONST)
> + int ct = arg_ct->ct;
> + if (ct & TCG_CT_CONST) {
> return 1;
> - else
> - return 0;
> + }
> + if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
> + return 1;
> + }
> + if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
> + return 1;
> + }
> + return 0;
> }
>
> +#if TCG_TARGET_REG_BITS == 64
> +# define LOWREGMASK(x) ((x) & 7)
> +#else
> +# define LOWREGMASK(x) (x)
> +#endif
> +
> #define P_EXT 0x100 /* 0x0f opcode prefix */
> #define P_DATA16 0x200 /* 0x66 opcode prefix */
> +#if TCG_TARGET_REG_BITS == 64
> +# define P_ADDR32 0x400 /* 0x67 opcode prefix */
> +# define P_REXW 0x800 /* Set REX.W = 1 */
> +# define P_REXB_R 0x1000 /* REG field as byte register */
> +# define P_REXB_RM 0x2000 /* R/M field as byte register */
> +#else
> +# define P_ADDR32 0
> +# define P_REXW 0
> +# define P_REXB_R 0
> +# define P_REXB_RM 0
> +#endif
>
> #define OPC_ARITH_EvIz (0x81)
> #define OPC_ARITH_EvIb (0x83)
> @@ -179,9 +261,11 @@ static inline int tcg_target_const_match(tcg_target_long val,
> #define OPC_MOVB_EvGv (0x88) /* stores, more or less */
> #define OPC_MOVL_EvGv (0x89) /* stores, more or less */
> #define OPC_MOVL_GvEv (0x8b) /* loads, more or less */
> +#define OPC_MOVL_EvIz (0xc7)
> #define OPC_MOVL_Iv (0xb8)
> #define OPC_MOVSBL (0xbe | P_EXT)
> #define OPC_MOVSWL (0xbf | P_EXT)
> +#define OPC_MOVSLQ (0x63 | P_REXW)
> #define OPC_MOVZBL (0xb6 | P_EXT)
> #define OPC_MOVZWL (0xb7 | P_EXT)
> #define OPC_POP_r32 (0x58)
> @@ -189,7 +273,7 @@ static inline int tcg_target_const_match(tcg_target_long val,
> #define OPC_PUSH_Iv (0x68)
> #define OPC_PUSH_Ib (0x6a)
> #define OPC_RET (0xc3)
> -#define OPC_SETCC (0x90 | P_EXT) /* ... plus condition code */
> +#define OPC_SETCC (0x90 | P_EXT | P_REXB_RM) /* ... plus cc */
> #define OPC_SHIFT_1 (0xd1)
> #define OPC_SHIFT_Ib (0xc1)
> #define OPC_SHIFT_cl (0xd3)
> @@ -226,6 +310,8 @@ static inline int tcg_target_const_match(tcg_target_long val,
> #define EXT3_IDIV 7
>
> /* Group 5 opcode extensions for 0xff. To be used with OPC_GRP5. */
> +#define EXT5_INC_Ev 0
> +#define EXT5_DEC_Ev 1
> #define EXT5_CALLN_Ev 2
> #define EXT5_JMPN_Ev 4
>
> @@ -261,7 +347,45 @@ static const uint8_t tcg_cond_to_jcc[10] = {
> [TCG_COND_GTU] = JCC_JA,
> };
>
> -static inline void tcg_out_opc(TCGContext *s, int opc)
> +#if TCG_TARGET_REG_BITS == 64
> +static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
> +{
> + int rex;
> +
> + if (opc & P_DATA16) {
> + /* We should never be asking for both 16 and 64-bit operation. */
> + assert((opc & P_REXW) == 0);
> + tcg_out8(s, 0x66);
> + }
> + if (opc & P_ADDR32) {
> + tcg_out8(s, 0x67);
> + }
> +
> + rex = 0;
> + rex |= (opc & P_REXW) >> 8; /* REX.W */
> + rex |= (r & 8) >> 1; /* REX.R */
> + rex |= (x & 8) >> 2; /* REX.X */
> + rex |= (rm & 8) >> 3; /* REX.B */
> +
> + /* P_REXB_{R,RM} indicates that the given register is the low byte.
> + For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
> + as otherwise the encoding indicates %[abcd]h. Note that the values
> + that are ORed in merely indicate that the REX byte must be present;
> + those bits get discarded in output. */
> + rex |= opc & (r >= 4 ? P_REXB_R : 0);
> + rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
> +
> + if (rex) {
> + tcg_out8(s, (uint8_t)(rex | 0x40));
> + }
> +
> + if (opc & P_EXT) {
> + tcg_out8(s, 0x0f);
> + }
> + tcg_out8(s, opc);
> +}
> +#else
> +static void tcg_out_opc(TCGContext *s, int opc)
> {
> if (opc & P_DATA16) {
> tcg_out8(s, 0x66);
> @@ -271,36 +395,69 @@ static inline void tcg_out_opc(TCGContext *s, int opc)
> }
> tcg_out8(s, opc);
> }
> +/* Discard the register arguments to tcg_out_opc early, so as not to penalize
> + the 32-bit compilation paths. This method works with all versions of gcc,
> + whereas relying on optimization may not be able to exclude them. */
> +#define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc)
> +#endif
>
> -static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
> +static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
> {
> - tcg_out_opc(s, opc);
> - tcg_out8(s, 0xc0 | (r << 3) | rm);
> + tcg_out_opc(s, opc, r, rm, 0);
> + tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
> }
>
> -/* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
> - We handle either RM and INDEX missing with a -1 value. */
> +/* Output an opcode with a full "rm + (index<<shift) + offset" address mode.
> + We handle either RM and INDEX missing with a negative value. In 64-bit
> + mode for absolute addresses, ~RM is the size of the immediate operand
> + that will follow the instruction. */
>
> static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
> - int index, int shift, int32_t offset)
> + int index, int shift,
> + tcg_target_long offset)
> {
> int mod, len;
>
> - if (index == -1 && rm == -1) {
> - /* Absolute address. */
> - tcg_out_opc(s, opc);
> - tcg_out8(s, (r << 3) | 5);
> - tcg_out32(s, offset);
> - return;
> - }
> + if (index < 0 && rm < 0) {
> + if (TCG_TARGET_REG_BITS == 64) {
> + /* Try for a rip-relative addressing mode. This has replaced
> + the 32-bit-mode absolute addressing encoding. */
> + tcg_target_long pc = (tcg_target_long)s->code_ptr + 5 + ~rm;
> + tcg_target_long disp = offset - pc;
> + if (disp == (int32_t)disp) {
> + tcg_out_opc(s, opc, r, 0, 0);
> + tcg_out8(s, (LOWREGMASK(r) << 3) | 5);
> + tcg_out32(s, disp);
> + return;
> + }
>
> - tcg_out_opc(s, opc);
> + /* Try for an absolute address encoding. This requires the
> + use of the MODRM+SIB encoding and is therefore larger than
> + rip-relative addressing. */
> + if (offset == (int32_t)offset) {
> + tcg_out_opc(s, opc, r, 0, 0);
> + tcg_out8(s, (LOWREGMASK(r) << 3) | 4);
> + tcg_out8(s, (4 << 3) | 5);
> + tcg_out32(s, offset);
> + return;
> + }
> +
> + /* ??? The memory isn't directly addressable. */
> + tcg_abort();
> + } else {
> + /* Absolute address. */
> + tcg_out_opc(s, opc, r, 0, 0);
> + tcg_out8(s, (r << 3) | 5);
> + tcg_out32(s, offset);
> + return;
> + }
> + }
>
> /* Find the length of the immediate addend. Note that the encoding
> that would be used for (%ebp) indicates absolute addressing. */
> - if (rm == -1) {
> + if (rm < 0) {
> mod = 0, len = 4, rm = 5;
> - } else if (offset == 0 && rm != TCG_REG_EBP) {
> + } else if (offset == 0 && LOWREGMASK(rm) != TCG_REG_EBP) {
> mod = 0, len = 0;
> } else if (offset == (int8_t)offset) {
> mod = 0x40, len = 1;
> @@ -310,22 +467,25 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
>
> /* Use a single byte MODRM format if possible. Note that the encoding
> that would be used for %esp is the escape to the two byte form. */
> - if (index == -1 && rm != TCG_REG_ESP) {
> + if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) {
> /* Single byte MODRM format. */
> - tcg_out8(s, mod | (r << 3) | rm);
> + tcg_out_opc(s, opc, r, rm, 0);
> + tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
> } else {
> /* Two byte MODRM+SIB format. */
>
> /* Note that the encoding that would place %esp into the index
> - field indicates no index register. */
> - if (index == -1) {
> + field indicates no index register. In 64-bit mode, the REX.X
> + bit counts, so %r12 can be used as the index. */
> + if (index < 0) {
> index = 4;
> } else {
> assert(index != TCG_REG_ESP);
> }
>
> - tcg_out8(s, mod | (r << 3) | 4);
> - tcg_out8(s, (shift << 6) | (index << 3) | rm);
> + tcg_out_opc(s, opc, r, rm, index);
> + tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4);
> + tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm));
> }
>
> if (len == 1) {
> @@ -335,9 +495,9 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
> }
> }
>
> -/* rm == -1 means no register index */
> -static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
> - int32_t offset)
> +/* A simplification of the above with no index or shift. */
> +static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r,
> + int rm, tcg_target_long offset)
> {
> tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset);
> }
> @@ -345,58 +505,75 @@ static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
> /* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */
> static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
> {
> - tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3), dest, src);
> + /* Propagate an opcode prefix, such as P_REXW. */
> + int ext = subop & ~0x7;
> + subop &= 0x7;
> +
> + tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src);
> }
>
> static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
> {
> if (arg != ret) {
> - tcg_out_modrm(s, OPC_MOVL_GvEv, ret, arg);
> + int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
> + tcg_out_modrm(s, opc, ret, arg);
> }
> }
>
> -static inline void tcg_out_movi(TCGContext *s, TCGType type,
> - int ret, int32_t arg)
> +static void tcg_out_movi(TCGContext *s, TCGType type,
> + int ret, tcg_target_long arg)
> {
> if (arg == 0) {
> tgen_arithr(s, ARITH_XOR, ret, ret);
> + return;
> + } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
> + tcg_out_opc(s, OPC_MOVL_Iv + LOWREGMASK(ret), 0, ret, 0);
> + tcg_out32(s, arg);
> + } else if (arg == (int32_t)arg) {
> + tcg_out_modrm(s, OPC_MOVL_EvIz + P_REXW, 0, ret);
> + tcg_out32(s, arg);
> } else {
> - tcg_out8(s, OPC_MOVL_Iv + ret);
> + tcg_out_opc(s, OPC_MOVL_Iv + P_REXW + LOWREGMASK(ret), 0, ret, 0);
> tcg_out32(s, arg);
> + tcg_out32(s, arg >> 31 >> 1);
> }
> }
>
> static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
> {
> if (val == (int8_t)val) {
> - tcg_out_opc(s, OPC_PUSH_Ib);
> + tcg_out_opc(s, OPC_PUSH_Ib, 0, 0, 0);
> tcg_out8(s, val);
> - } else {
> - tcg_out_opc(s, OPC_PUSH_Iv);
> + } else if (val == (int32_t)val) {
> + tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0);
> tcg_out32(s, val);
> + } else {
> + tcg_abort();
> }
> }
>
> static inline void tcg_out_push(TCGContext *s, int reg)
> {
> - tcg_out_opc(s, OPC_PUSH_r32 + reg);
> + tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0);
> }
>
> static inline void tcg_out_pop(TCGContext *s, int reg)
> {
> - tcg_out_opc(s, OPC_POP_r32 + reg);
> + tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0);
> }
>
> static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
> int arg1, tcg_target_long arg2)
> {
> - tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2);
> + int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
> + tcg_out_modrm_offset(s, opc, ret, arg1, arg2);
> }
>
> static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
> int arg1, tcg_target_long arg2)
> {
> - tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2);
> + int opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0);
> + tcg_out_modrm_offset(s, opc, arg, arg1, arg2);
> }
>
> static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count)
> @@ -406,35 +583,35 @@ static void tcg_out_shifti(TCGContext *s, int subopc, int reg, int count)
> subopc &= 0x7;
>
> if (count == 1) {
> - tcg_out_modrm(s, OPC_SHIFT_1 | ext, subopc, reg);
> + tcg_out_modrm(s, OPC_SHIFT_1 + ext, subopc, reg);
> } else {
> - tcg_out_modrm(s, OPC_SHIFT_Ib | ext, subopc, reg);
> + tcg_out_modrm(s, OPC_SHIFT_Ib + ext, subopc, reg);
> tcg_out8(s, count);
> }
> }
>
> static inline void tcg_out_bswap32(TCGContext *s, int reg)
> {
> - tcg_out_opc(s, OPC_BSWAP + reg);
> + tcg_out_opc(s, OPC_BSWAP + LOWREGMASK(reg), 0, reg, 0);
> }
>
> static inline void tcg_out_rolw_8(TCGContext *s, int reg)
> {
> - tcg_out_shifti(s, SHIFT_ROL | P_DATA16, reg, 8);
> + tcg_out_shifti(s, SHIFT_ROL + P_DATA16, reg, 8);
> }
>
> static inline void tcg_out_ext8u(TCGContext *s, int dest, int src)
> {
> /* movzbl */
> - assert(src < 4);
> - tcg_out_modrm(s, OPC_MOVZBL, dest, src);
> + assert(src < 4 || TCG_TARGET_REG_BITS == 64);
> + tcg_out_modrm(s, OPC_MOVZBL + P_REXB_RM, dest, src);
> }
>
> -static void tcg_out_ext8s(TCGContext *s, int dest, int src)
> +static void tcg_out_ext8s(TCGContext *s, int dest, int src, int rexw)
> {
> /* movsbl */
> - assert(src < 4);
> - tcg_out_modrm(s, OPC_MOVSBL, dest, src);
> + assert(src < 4 || TCG_TARGET_REG_BITS == 64);
> + tcg_out_modrm(s, OPC_MOVSBL + P_REXB_RM + rexw, dest, src);
> }
>
> static inline void tcg_out_ext16u(TCGContext *s, int dest, int src)
> @@ -443,38 +620,94 @@ static inline void tcg_out_ext16u(TCGContext *s, int dest, int src)
> tcg_out_modrm(s, OPC_MOVZWL, dest, src);
> }
>
> -static inline void tcg_out_ext16s(TCGContext *s, int dest, int src)
> +static inline void tcg_out_ext16s(TCGContext *s, int dest, int src, int rexw)
> {
> - /* movswl */
> - tcg_out_modrm(s, OPC_MOVSWL, dest, src);
> + /* movsw[lq] */
> + tcg_out_modrm(s, OPC_MOVSWL + rexw, dest, src);
> }
>
> -static inline void tgen_arithi(TCGContext *s, int c, int r0,
> - int32_t val, int cf)
> +static inline void tcg_out_ext32u(TCGContext *s, int dest, int src)
> {
> + /* 32-bit mov zero extends. */
> + tcg_out_modrm(s, OPC_MOVL_GvEv, dest, src);
> +}
> +
> +static inline void tcg_out_ext32s(TCGContext *s, int dest, int src)
> +{
> + tcg_out_modrm(s, OPC_MOVSLQ, dest, src);
> +}
> +
> +static inline void tcg_out_bswap64(TCGContext *s, int reg)
> +{
> + tcg_out_opc(s, OPC_BSWAP + P_REXW + LOWREGMASK(reg), 0, reg, 0);
> +}
> +
> +static void tgen_arithi(TCGContext *s, int c, int r0,
> + tcg_target_long val, int cf)
> +{
> + int rexw = 0;
> +
> + if (TCG_TARGET_REG_BITS == 64) {
> + rexw = c & -8;
> + c &= 7;
> + }
> +
> /* ??? While INC is 2 bytes shorter than ADDL $1, they also induce
> partial flags update stalls on Pentium4 and are not recommended
> by current Intel optimization manuals. */
> if (!cf && (c == ARITH_ADD || c == ARITH_SUB) && (val == 1 || val == -1)) {
> - int opc = ((c == ARITH_ADD) ^ (val < 0) ? OPC_INC_r32 : OPC_DEC_r32);
> - tcg_out_opc(s, opc + r0);
> - } else if (val == (int8_t)val) {
> - tcg_out_modrm(s, OPC_ARITH_EvIb, c, r0);
> + _Bool is_inc = (c == ARITH_ADD) ^ (val < 0);
> + if (TCG_TARGET_REG_BITS == 64) {
> + /* The single-byte increment encodings are re-tasked as the
> + REX prefixes. Use the MODRM encoding. */
> + tcg_out_modrm(s, OPC_GRP5 + rexw,
> + (is_inc ? EXT5_INC_Ev : EXT5_DEC_Ev), r0);
> + } else {
> + tcg_out8(s, (is_inc ? OPC_INC_r32 : OPC_DEC_r32) + r0);
> + }
> + return;
> + }
> +
> + if (c == ARITH_AND) {
> + if (TCG_TARGET_REG_BITS == 64) {
> + if (val == 0xffffffffu) {
> + tcg_out_ext32u(s, r0, r0);
> + return;
> + }
> + if (val == (uint32_t)val) {
> + /* AND with no high bits set can use a 32-bit operation. */
> + rexw = 0;
> + }
> + }
> + if (val == 0xffu) {
> + tcg_out_ext8u(s, r0, r0);
> + return;
> + }
> + if (val == 0xffffu) {
> + tcg_out_ext16u(s, r0, r0);
> + return;
> + }
> + }
> +
> + if (val == (int8_t)val) {
> + tcg_out_modrm(s, OPC_ARITH_EvIb + rexw, c, r0);
> tcg_out8(s, val);
> - } else if (c == ARITH_AND && val == 0xffu && r0 < 4) {
> - tcg_out_ext8u(s, r0, r0);
> - } else if (c == ARITH_AND && val == 0xffffu) {
> - tcg_out_ext16u(s, r0, r0);
> - } else {
> - tcg_out_modrm(s, OPC_ARITH_EvIz, c, r0);
> + return;
> + }
> + if (rexw == 0 || val == (int32_t)val) {
> + tcg_out_modrm(s, OPC_ARITH_EvIz + rexw, c, r0);
> tcg_out32(s, val);
> + return;
> }
> +
> + tcg_abort();
> }
>
> static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
> {
> - if (val != 0)
> - tgen_arithi(s, ARITH_ADD, reg, val, 0);
> + if (val != 0) {
> + tgen_arithi(s, ARITH_ADD + P_REXW, reg, val, 0);
> + }
> }
>
> /* Use SMALL != 0 to force a short forward branch. */
> @@ -501,7 +734,7 @@ static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small)
> tcg_out8(s, OPC_JMP_long);
> tcg_out32(s, val - 5);
> } else {
> - tcg_out_opc(s, OPC_JCC_long + opc);
> + tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0);
> tcg_out32(s, val - 6);
> }
> }
> @@ -517,7 +750,7 @@ static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small)
> if (opc == -1) {
> tcg_out8(s, OPC_JMP_long);
> } else {
> - tcg_out_opc(s, OPC_JCC_long + opc);
> + tcg_out_opc(s, OPC_JCC_long + opc, 0, 0, 0);
> }
> tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
> s->code_ptr += 4;
> @@ -525,28 +758,37 @@ static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small)
> }
>
> static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
> - int const_arg2)
> + int const_arg2, int rexw)
> {
> if (const_arg2) {
> if (arg2 == 0) {
> /* test r, r */
> - tcg_out_modrm(s, OPC_TESTL, arg1, arg1);
> + tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1);
> } else {
> - tgen_arithi(s, ARITH_CMP, arg1, arg2, 0);
> + tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0);
> }
> } else {
> - tgen_arithr(s, ARITH_CMP, arg1, arg2);
> + tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2);
> }
> }
>
> -static void tcg_out_brcond(TCGContext *s, TCGCond cond,
> - TCGArg arg1, TCGArg arg2, int const_arg2,
> - int label_index, int small)
> +static void tcg_out_brcond32(TCGContext *s, TCGCond cond,
> + TCGArg arg1, TCGArg arg2, int const_arg2,
> + int label_index, int small)
> {
> - tcg_out_cmp(s, arg1, arg2, const_arg2);
> + tcg_out_cmp(s, arg1, arg2, const_arg2, 0);
> tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, small);
> }
>
> +#if TCG_TARGET_REG_BITS == 64
> +static void tcg_out_brcond64(TCGContext *s, TCGCond cond,
> + TCGArg arg1, TCGArg arg2, int const_arg2,
> + int label_index, int small)
> +{
> + tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW);
> + tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, small);
> +}
> +#else
> /* XXX: we implement it at the target level to avoid having to
> handle cross basic blocks temporaries */
> static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
> @@ -556,87 +798,97 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
> label_next = gen_new_label();
> switch(args[4]) {
> case TCG_COND_EQ:
> - tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2],
> - label_next, 1);
> - tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2],
> + label_next, 1);
> + tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3],
> + args[5], small);
> break;
> case TCG_COND_NE:
> - tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2],
> - args[5], small);
> - tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2],
> + args[5], small);
> + tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3],
> + args[5], small);
> break;
> case TCG_COND_LT:
> - tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3],
> + args[5], small);
> tcg_out_jxx(s, JCC_JNE, label_next, 1);
> - tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2],
> + args[5], small);
> break;
> case TCG_COND_LE:
> - tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3],
> + args[5], small);
> tcg_out_jxx(s, JCC_JNE, label_next, 1);
> - tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2],
> + args[5], small);
> break;
> case TCG_COND_GT:
> - tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3],
> + args[5], small);
> tcg_out_jxx(s, JCC_JNE, label_next, 1);
> - tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2],
> + args[5], small);
> break;
> case TCG_COND_GE:
> - tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3],
> + args[5], small);
> tcg_out_jxx(s, JCC_JNE, label_next, 1);
> - tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2],
> + args[5], small);
> break;
> case TCG_COND_LTU:
> - tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3],
> + args[5], small);
> tcg_out_jxx(s, JCC_JNE, label_next, 1);
> - tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2],
> + args[5], small);
> break;
> case TCG_COND_LEU:
> - tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3],
> + args[5], small);
> tcg_out_jxx(s, JCC_JNE, label_next, 1);
> - tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2],
> + args[5], small);
> break;
> case TCG_COND_GTU:
> - tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3],
> + args[5], small);
> tcg_out_jxx(s, JCC_JNE, label_next, 1);
> - tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2],
> + args[5], small);
> break;
> case TCG_COND_GEU:
> - tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3],
> + args[5], small);
> tcg_out_jxx(s, JCC_JNE, label_next, 1);
> - tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2],
> - args[5], small);
> + tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2],
> + args[5], small);
> break;
> default:
> tcg_abort();
> }
> tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
> }
> +#endif
>
> -static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg dest,
> - TCGArg arg1, TCGArg arg2, int const_arg2)
> +static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest,
> + TCGArg arg1, TCGArg arg2, int const_arg2)
> {
> - tcg_out_cmp(s, arg1, arg2, const_arg2);
> + tcg_out_cmp(s, arg1, arg2, const_arg2, 0);
> tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest);
> tcg_out_ext8u(s, dest, dest);
> }
>
> +#if TCG_TARGET_REG_BITS == 64
> +static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest,
> + TCGArg arg1, TCGArg arg2, int const_arg2)
> +{
> + tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW);
> + tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest);
> + tcg_out_ext8u(s, dest, dest);
> +}
> +#else
> static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
> const int *const_args)
> {
> @@ -678,11 +930,30 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
> tcg_out_label(s, label_over, (tcg_target_long)s->code_ptr);
> }
> }
> +#endif
> +
> +static void tcg_out_branch(TCGContext *s, int call, tcg_target_long dest)
> +{
> + tcg_target_long disp = dest - (tcg_target_long)s->code_ptr - 5;
> +
> + if (disp == (int32_t)disp) {
> + tcg_out_opc(s, call ? OPC_CALL_Jz : OPC_JMP_long, 0, 0, 0);
> + tcg_out32(s, disp);
> + } else {
> + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, dest);
> + tcg_out_modrm(s, OPC_GRP5,
> + call ? EXT5_CALLN_Ev : EXT5_JMPN_Ev, TCG_REG_R10);
> + }
> +}
> +
> +static inline void tcg_out_calli(TCGContext *s, tcg_target_long dest)
> +{
> + tcg_out_branch(s, 1, dest);
> +}
>
> -static void tcg_out_calli(TCGContext *s, tcg_target_long dest)
> +static void tcg_out_jmp(TCGContext *s, tcg_target_long dest)
> {
> - tcg_out_opc(s, OPC_CALL_Jz);
> - tcg_out32(s, dest - (tcg_target_long)s->code_ptr - 4);
> + tcg_out_branch(s, 0, dest);
> }
>
> #if defined(CONFIG_SOFTMMU)
> @@ -718,11 +989,12 @@ static void *qemu_st_helpers[4] = {
> LABEL_PTRS is filled with 1 (32-bit addresses) or 2 (64-bit addresses)
> positions of the displacements of forward jumps to the TLB miss case.
>
> - EAX is loaded with the low part of the address. In the TLB hit case,
> - it has been adjusted as indicated by the TLB and so is a host address.
> - In the TLB miss case, it continues to hold a guest address.
> + First argument register is loaded with the low part of the address.
> + In the TLB hit case, it has been adjusted as indicated by the TLB
> + and so is a host address. In the TLB miss case, it continues to
> + hold a guest address.
>
> - EDX is clobbered. */
> + Second argument register is clobbered. */
>
> static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
> int mem_index, int s_bits,
> @@ -730,32 +1002,42 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
> uint8_t **label_ptr, int which)
> {
> const int addrlo = args[addrlo_idx];
> - const int r0 = TCG_REG_EAX;
> - const int r1 = TCG_REG_EDX;
> + const int r0 = tcg_target_call_iarg_regs[0];
> + const int r1 = tcg_target_call_iarg_regs[1];
> + TCGType type = TCG_TYPE_I32;
> + int rexw = 0;
> +
> + if (TCG_TARGET_REG_BITS == 64 && TARGET_LONG_BITS == 64) {
> + type = TCG_TYPE_I64;
> + rexw = P_REXW;
> + }
>
> - tcg_out_mov(s, TCG_TYPE_I32, r1, addrlo);
> - tcg_out_mov(s, TCG_TYPE_I32, r0, addrlo);
> + tcg_out_mov(s, type, r1, addrlo);
> + tcg_out_mov(s, type, r0, addrlo);
>
> - tcg_out_shifti(s, SHIFT_SHR, r1, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
> + tcg_out_shifti(s, SHIFT_SHR + rexw, r1,
> + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
>
> - tgen_arithi(s, ARITH_AND, r0, TARGET_PAGE_MASK | ((1 << s_bits) - 1), 0);
> - tgen_arithi(s, ARITH_AND, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
> + tgen_arithi(s, ARITH_AND + rexw, r0,
> + TARGET_PAGE_MASK | ((1 << s_bits) - 1), 0);
> + tgen_arithi(s, ARITH_AND + rexw, r1,
> + (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS, 0);
>
> - tcg_out_modrm_sib_offset(s, OPC_LEA, r1, TCG_AREG0, r1, 0,
> + tcg_out_modrm_sib_offset(s, OPC_LEA + P_REXW, r1, TCG_AREG0, r1, 0,
> offsetof(CPUState, tlb_table[mem_index][0])
> + which);
>
> /* cmp 0(r1), r0 */
> - tcg_out_modrm_offset(s, OPC_CMP_GvEv, r0, r1, 0);
> + tcg_out_modrm_offset(s, OPC_CMP_GvEv + rexw, r0, r1, 0);
>
> - tcg_out_mov(s, TCG_TYPE_I32, r0, addrlo);
> + tcg_out_mov(s, type, r0, addrlo);
>
> /* jne label1 */
> tcg_out8(s, OPC_JCC_short + JCC_JNE);
> label_ptr[0] = s->code_ptr;
> s->code_ptr++;
>
> - if (TARGET_LONG_BITS == 64) {
> + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
> /* cmp 4(r1), addrhi */
> tcg_out_modrm_offset(s, OPC_CMP_GvEv, args[addrlo_idx+1], r1, 4);
>
> @@ -768,7 +1050,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
> /* TLB Hit. */
>
> /* add addend(r1), r0 */
> - tcg_out_modrm_offset(s, OPC_ADD_GvEv, r0, r1,
> + tcg_out_modrm_offset(s, OPC_ADD_GvEv + P_REXW, r0, r1,
> offsetof(CPUTLBEntry, addend) - which);
> }
> #endif
> @@ -783,26 +1065,24 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
> #endif
> switch (sizeop) {
> case 0:
> - /* movzbl */
> tcg_out_modrm_offset(s, OPC_MOVZBL, datalo, base, ofs);
> break;
> case 0 | 4:
> - /* movsbl */
> - tcg_out_modrm_offset(s, OPC_MOVSBL, datalo, base, ofs);
> + tcg_out_modrm_offset(s, OPC_MOVSBL + P_REXW, datalo, base, ofs);
> break;
> case 1:
> - /* movzwl */
> tcg_out_modrm_offset(s, OPC_MOVZWL, datalo, base, ofs);
> if (bswap) {
> tcg_out_rolw_8(s, datalo);
> }
> break;
> case 1 | 4:
> - /* movswl */
> - tcg_out_modrm_offset(s, OPC_MOVSWL, datalo, base, ofs);
> if (bswap) {
> + tcg_out_modrm_offset(s, OPC_MOVZWL, datalo, base, ofs);
> tcg_out_rolw_8(s, datalo);
> - tcg_out_modrm(s, OPC_MOVSWL, datalo, datalo);
> + tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo);
> + } else {
> + tcg_out_modrm_offset(s, OPC_MOVSWL + P_REXW, datalo, base, ofs);
> }
> break;
> case 2:
> @@ -811,22 +1091,40 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int datalo, int datahi,
> tcg_out_bswap32(s, datalo);
> }
> break;
> - case 3:
> +#if TCG_TARGET_REG_BITS == 64
> + case 2 | 4:
> if (bswap) {
> - int t = datalo;
> - datalo = datahi;
> - datahi = t;
> - }
> - if (base != datalo) {
> tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
> - tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
> + tcg_out_bswap32(s, datalo);
> + tcg_out_ext32s(s, datalo, datalo);
> } else {
> - tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
> - tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
> + tcg_out_modrm_offset(s, OPC_MOVSLQ, datalo, base, ofs);
> }
> - if (bswap) {
> - tcg_out_bswap32(s, datalo);
> - tcg_out_bswap32(s, datahi);
> + break;
> +#endif
> + case 3:
> + if (TCG_TARGET_REG_BITS == 64) {
> + tcg_out_ld(s, TCG_TYPE_I64, datalo, base, ofs);
> + if (bswap) {
> + tcg_out_bswap64(s, datalo);
> + }
> + } else {
> + if (bswap) {
> + int t = datalo;
> + datalo = datahi;
> + datahi = t;
> + }
> + if (base != datalo) {
> + tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
> + tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
> + } else {
> + tcg_out_ld(s, TCG_TYPE_I32, datahi, base, ofs + 4);
> + tcg_out_ld(s, TCG_TYPE_I32, datalo, base, ofs);
> + }
> + if (bswap) {
> + tcg_out_bswap32(s, datalo);
> + tcg_out_bswap32(s, datahi);
> + }
> }
> break;
> default:
> @@ -849,20 +1147,21 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>
> data_reg = args[0];
> addrlo_idx = 1;
> - if (opc == 3) {
> + if (TCG_TARGET_REG_BITS == 32 && opc == 3) {
> data_reg2 = args[1];
> addrlo_idx = 2;
> }
>
> #if defined(CONFIG_SOFTMMU)
> - mem_index = args[addrlo_idx + (TARGET_LONG_BITS / 32)];
> + mem_index = args[addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS)];
> s_bits = opc & 3;
>
> tcg_out_tlb_load(s, addrlo_idx, mem_index, s_bits, args,
> label_ptr, offsetof(CPUTLBEntry, addr_read));
>
> /* TLB Hit. */
> - tcg_out_qemu_ld_direct(s, data_reg, data_reg2, TCG_REG_EAX, 0, opc);
> + tcg_out_qemu_ld_direct(s, data_reg, data_reg2,
> + tcg_target_call_iarg_regs[0], 0, opc);
>
> /* jmp label2 */
> tcg_out8(s, OPC_JMP_short);
> @@ -873,14 +1172,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>
> /* label1: */
> *label_ptr[0] = s->code_ptr - label_ptr[0] - 1;
> - if (TARGET_LONG_BITS == 64) {
> + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
> *label_ptr[1] = s->code_ptr - label_ptr[1] - 1;
> }
>
> /* XXX: move that code at the end of the TB */
> - /* EAX is already loaded. */
> + /* The first argument is already loaded with addrlo. */
> arg_idx = 1;
> - if (TARGET_LONG_BITS == 64) {
> + if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 64) {
> tcg_out_mov(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[arg_idx++],
> args[addrlo_idx + 1]);
> }
> @@ -890,10 +1189,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
>
> switch(opc) {
> case 0 | 4:
> - tcg_out_ext8s(s, data_reg, TCG_REG_EAX);
> + tcg_out_ext8s(s, data_reg, TCG_REG_EAX, P_REXW);
> break;
> case 1 | 4:
> - tcg_out_ext16s(s, data_reg, TCG_REG_EAX);
> + tcg_out_ext16s(s, data_reg, TCG_REG_EAX, P_REXW);
> break;
> case 0:
> tcg_out_ext8u(s, data_reg, TCG_REG_EAX);
> @@ -902,26 +1201,52 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
> tcg_out_ext16u(s, data_reg, TCG_REG_EAX);
> break;
> case 2:
> - default:
> tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
> break;
> +#if TCG_TARGET_REG_BITS == 64
> + case 2 | 4:
> + tcg_out_ext32s(s, data_reg, TCG_REG_EAX);
> + break;
> +#endif
> case 3:
> - if (data_reg == TCG_REG_EDX) {
> + if (TCG_TARGET_REG_BITS == 64) {
> + tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);
> + } else if (data_reg == TCG_REG_EDX) {
> /* xchg %edx, %eax */
> - tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX);
> + tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0);
> tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EAX);
> } else {
> tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX);
> tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EDX);
> }
> break;
> + default:
> + tcg_abort();
> }
>
> /* label2: */
> *label_ptr[2] = s->code_ptr - label_ptr[2] - 1;
> #else
> - tcg_out_qemu_ld_direct(s, data_reg, data_reg2,
> - args[addrlo_idx], GUEST_BASE, opc);
> + {
> + int32_t offset = GUEST_BASE;
> + int base = args[addrlo_idx];
> +
> + if (TCG_TARGET_REG_BITS == 64) {
> + /* ??? We assume all operations have left us with register
> + contents that are zero extended. So far this appears to
> + be true. If we want to enforce this, we can either do
> + an explicit zero-extension here, or (if GUEST_BASE == 0)
> + use the ADDR32 prefix. For now, do nothing. */
> +
> + if (offset != GUEST_BASE) {
> + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE);
> + tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base);
> + base = TCG_REG_RDI, offset = 0;
> + }
> + }
> +
> + tcg_out_qemu_ld_direct(s, data_reg, data_reg2, base, offset, opc);
> + }
> #endif
> }
>
> @@ -936,12 +1261,12 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
> /* ??? Ideally we wouldn't need a scratch register. For user-only,
> we could perform the bswap twice to restore the original value
> instead of moving to the scratch. But as it is, the L constraint
> - means that EDX is definitely free here. */
> - int scratch = TCG_REG_EDX;
> + means that the second argument reg is definitely free here. */
> + int scratch = tcg_target_call_iarg_regs[1];
>
> switch (sizeop) {
> case 0:
> - tcg_out_modrm_offset(s, OPC_MOVB_EvGv, datalo, base, ofs);
> + tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R, datalo, base, ofs);
> break;
> case 1:
> if (bswap) {
> @@ -949,9 +1274,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
> tcg_out_rolw_8(s, scratch);
> datalo = scratch;
> }
> - /* movw */
> - tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16,
> - datalo, base, ofs);
> + tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_DATA16, datalo, base, ofs);
> break;
> case 2:
> if (bswap) {
> @@ -962,7 +1285,14 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int datalo, int datahi,
> tcg_out_st(s, TCG_TYPE_I32, datalo, base, ofs);
> break;
> case 3:
> - if (bswap) {
> + if (TCG_TARGET_REG_BITS == 64) {
> + if (bswap) {
> + tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo);
> + tcg_out_bswap64(s, scratch);
> + datalo = scratch;
> + }
> + tcg_out_st(s, TCG_TYPE_I64, datalo, base, ofs);
> + } else if (bswap) {
> tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi);
> tcg_out_bswap32(s, scratch);
> tcg_out_st(s, TCG_TYPE_I32, scratch, base, ofs);
> @@ -992,20 +1322,21 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
>
> data_reg = args[0];
> addrlo_idx = 1;
> - if (opc == 3) {
> + if (TCG_TARGET_REG_BITS == 32 && opc == 3) {
> data_reg2 = args[1];
> addrlo_idx = 2;
> }
>
> #if defined(CONFIG_SOFTMMU)
> - mem_index = args[addrlo_idx + (TARGET_LONG_BITS / 32)];
> + mem_index = args[addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS)];
> s_bits = opc;
>
> tcg_out_tlb_load(s, addrlo_idx, mem_index, s_bits, args,
> label_ptr, offsetof(CPUTLBEntry, addr_write));
>
> /* TLB Hit. */
> - tcg_out_qemu_st_direct(s, data_reg, data_reg2, TCG_REG_EAX, 0, opc);
> + tcg_out_qemu_st_direct(s, data_reg, data_reg2,
> + tcg_target_call_iarg_regs[0], 0, opc);
>
> /* jmp label2 */
> tcg_out8(s, OPC_JMP_short);
> @@ -1016,12 +1347,17 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
>
> /* label1: */
> *label_ptr[0] = s->code_ptr - label_ptr[0] - 1;
> - if (TARGET_LONG_BITS == 64) {
> + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
> *label_ptr[1] = s->code_ptr - label_ptr[1] - 1;
> }
>
> /* XXX: move that code at the end of the TB */
> - if (TARGET_LONG_BITS == 32) {
> + if (TCG_TARGET_REG_BITS == 64) {
> + tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32),
> + TCG_REG_RSI, data_reg);
> + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
> + stack_adjust = 0;
> + } else if (TARGET_LONG_BITS == 32) {
> tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_EDX, data_reg);
> if (opc == 3) {
> tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_ECX, data_reg2);
> @@ -1058,7 +1394,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
>
> tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]);
>
> - if (stack_adjust == 4) {
> + if (stack_adjust == (TCG_TARGET_REG_BITS / 8)) {
> /* Pop and discard. This is 2 bytes smaller than the add. */
> tcg_out_pop(s, TCG_REG_ECX);
> } else if (stack_adjust != 0) {
> @@ -1068,21 +1404,48 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
> /* label2: */
> *label_ptr[2] = s->code_ptr - label_ptr[2] - 1;
> #else
> - tcg_out_qemu_st_direct(s, data_reg, data_reg2,
> - args[addrlo_idx], GUEST_BASE, opc);
> + {
> + int32_t offset = GUEST_BASE;
> + int base = args[addrlo_idx];
> +
> + if (TCG_TARGET_REG_BITS == 64) {
> + /* ??? We assume all operations have left us with register
> + contents that are zero extended. So far this appears to
> + be true. If we want to enforce this, we can either do
> + an explicit zero-extension here, or (if GUEST_BASE == 0)
> + use the ADDR32 prefix. For now, do nothing. */
> +
> + if (offset != GUEST_BASE) {
> + tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_RDI, GUEST_BASE);
> + tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_RDI, base);
> + base = TCG_REG_RDI, offset = 0;
> + }
> + }
> +
> + tcg_out_qemu_st_direct(s, data_reg, data_reg2, base, offset, opc);
> + }
> #endif
> }
>
> static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> const TCGArg *args, const int *const_args)
> {
> - int c;
> + int c, rexw = 0;
> +
> +#if TCG_TARGET_REG_BITS == 64
> +# define OP_32_64(x) \
> + case glue(glue(INDEX_op_, x), _i64): \
> + rexw = P_REXW; /* FALLTHRU */ \
> + case glue(glue(INDEX_op_, x), _i32)
> +#else
> +# define OP_32_64(x) \
> + case glue(glue(INDEX_op_, x), _i32)
> +#endif
>
> switch(opc) {
> case INDEX_op_exit_tb:
> - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
> - tcg_out8(s, OPC_JMP_long); /* jmp tb_ret_addr */
> - tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
> + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_EAX, args[0]);
> + tcg_out_jmp(s, (tcg_target_long) tb_ret_addr);
> break;
> case INDEX_op_goto_tb:
> if (s->tb_jmp_offset) {
> @@ -1107,8 +1470,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> break;
> case INDEX_op_jmp:
> if (const_args[0]) {
> - tcg_out8(s, OPC_JMP_long);
> - tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4);
> + tcg_out_jmp(s, args[0]);
> } else {
> /* jmp *reg */
> tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, args[0]);
> @@ -1120,38 +1482,43 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> case INDEX_op_movi_i32:
> tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
> break;
> - case INDEX_op_ld8u_i32:
> - /* movzbl */
> + OP_32_64(ld8u):
> + /* Note that we can ignore REXW for the zero-extend to 64-bit. */
> tcg_out_modrm_offset(s, OPC_MOVZBL, args[0], args[1], args[2]);
> break;
> - case INDEX_op_ld8s_i32:
> - /* movsbl */
> - tcg_out_modrm_offset(s, OPC_MOVSBL, args[0], args[1], args[2]);
> + OP_32_64(ld8s):
> + tcg_out_modrm_offset(s, OPC_MOVSBL + rexw, args[0], args[1], args[2]);
> break;
> - case INDEX_op_ld16u_i32:
> - /* movzwl */
> + OP_32_64(ld16u):
> + /* Note that we can ignore REXW for the zero-extend to 64-bit. */
> tcg_out_modrm_offset(s, OPC_MOVZWL, args[0], args[1], args[2]);
> break;
> - case INDEX_op_ld16s_i32:
> - /* movswl */
> - tcg_out_modrm_offset(s, OPC_MOVSWL, args[0], args[1], args[2]);
> + OP_32_64(ld16s):
> + tcg_out_modrm_offset(s, OPC_MOVSWL + rexw, args[0], args[1], args[2]);
> break;
> +#if TCG_TARGET_REG_BITS == 64
> + case INDEX_op_ld32u_i64:
> +#endif
> case INDEX_op_ld_i32:
> tcg_out_ld(s, TCG_TYPE_I32, args[0], args[1], args[2]);
> break;
> - case INDEX_op_st8_i32:
> - /* movb */
> - tcg_out_modrm_offset(s, OPC_MOVB_EvGv, args[0], args[1], args[2]);
> +
> + OP_32_64(st8):
> + tcg_out_modrm_offset(s, OPC_MOVB_EvGv | P_REXB_R,
> + args[0], args[1], args[2]);
> break;
> - case INDEX_op_st16_i32:
> - /* movw */
> + OP_32_64(st16):
> tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_DATA16,
> args[0], args[1], args[2]);
> break;
> +#if TCG_TARGET_REG_BITS == 64
> + case INDEX_op_st32_i64:
> +#endif
> case INDEX_op_st_i32:
> tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
> break;
> - case INDEX_op_add_i32:
> +
> + OP_32_64(add):
> /* For 3-operand addition, use LEA. */
> if (args[0] != args[1]) {
> TCGArg a0 = args[0], a1 = args[1], a2 = args[2], c3 = 0;
> @@ -1161,147 +1528,117 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> } else if (a0 == a2) {
> /* Watch out for dest = src + dest, since we've removed
> the matching constraint on the add. */
> - tgen_arithr(s, ARITH_ADD, a0, a1);
> + tgen_arithr(s, ARITH_ADD + rexw, a0, a1);
> break;
> }
>
> - tcg_out_modrm_sib_offset(s, OPC_LEA, a0, a1, a2, 0, c3);
> + tcg_out_modrm_sib_offset(s, OPC_LEA + rexw, a0, a1, a2, 0, c3);
> break;
> }
> c = ARITH_ADD;
> goto gen_arith;
> - case INDEX_op_sub_i32:
> + OP_32_64(sub):
> c = ARITH_SUB;
> goto gen_arith;
> - case INDEX_op_and_i32:
> + OP_32_64(and):
> c = ARITH_AND;
> goto gen_arith;
> - case INDEX_op_or_i32:
> + OP_32_64(or):
> c = ARITH_OR;
> goto gen_arith;
> - case INDEX_op_xor_i32:
> + OP_32_64(xor):
> c = ARITH_XOR;
> goto gen_arith;
> gen_arith:
> if (const_args[2]) {
> - tgen_arithi(s, c, args[0], args[2], 0);
> + tgen_arithi(s, c + rexw, args[0], args[2], 0);
> } else {
> - tgen_arithr(s, c, args[0], args[2]);
> + tgen_arithr(s, c + rexw, args[0], args[2]);
> }
> break;
> - case INDEX_op_mul_i32:
> +
> + OP_32_64(mul):
> if (const_args[2]) {
> int32_t val;
> val = args[2];
> if (val == (int8_t)val) {
> - tcg_out_modrm(s, OPC_IMUL_GvEvIb, args[0], args[0]);
> + tcg_out_modrm(s, OPC_IMUL_GvEvIb + rexw, args[0], args[0]);
> tcg_out8(s, val);
> } else {
> - tcg_out_modrm(s, OPC_IMUL_GvEvIz, args[0], args[0]);
> + tcg_out_modrm(s, OPC_IMUL_GvEvIz + rexw, args[0], args[0]);
> tcg_out32(s, val);
> }
> } else {
> - tcg_out_modrm(s, OPC_IMUL_GvEv, args[0], args[2]);
> + tcg_out_modrm(s, OPC_IMUL_GvEv + rexw, args[0], args[2]);
> }
> break;
> - case INDEX_op_mulu2_i32:
> - tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_MUL, args[3]);
> - break;
> - case INDEX_op_div2_i32:
> - tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_IDIV, args[4]);
> +
> + OP_32_64(div2):
> + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IDIV, args[4]);
> break;
> - case INDEX_op_divu2_i32:
> - tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_DIV, args[4]);
> + OP_32_64(divu2):
> + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_DIV, args[4]);
> break;
> - case INDEX_op_shl_i32:
> +
> + OP_32_64(shl):
> c = SHIFT_SHL;
> - gen_shift32:
> - if (const_args[2]) {
> - tcg_out_shifti(s, c, args[0], args[2]);
> - } else {
> - tcg_out_modrm(s, OPC_SHIFT_cl, c, args[0]);
> - }
> - break;
> - case INDEX_op_shr_i32:
> + goto gen_shift;
> + OP_32_64(shr):
> c = SHIFT_SHR;
> - goto gen_shift32;
> - case INDEX_op_sar_i32:
> + goto gen_shift;
> + OP_32_64(sar):
> c = SHIFT_SAR;
> - goto gen_shift32;
> - case INDEX_op_rotl_i32:
> + goto gen_shift;
> + OP_32_64(rotl):
> c = SHIFT_ROL;
> - goto gen_shift32;
> - case INDEX_op_rotr_i32:
> + goto gen_shift;
> + OP_32_64(rotr):
> c = SHIFT_ROR;
> - goto gen_shift32;
> -
> - case INDEX_op_add2_i32:
> - if (const_args[4]) {
> - tgen_arithi(s, ARITH_ADD, args[0], args[4], 1);
> - } else {
> - tgen_arithr(s, ARITH_ADD, args[0], args[4]);
> - }
> - if (const_args[5]) {
> - tgen_arithi(s, ARITH_ADC, args[1], args[5], 1);
> + goto gen_shift;
> + gen_shift:
> + if (const_args[2]) {
> + tcg_out_shifti(s, c + rexw, args[0], args[2]);
> } else {
> - tgen_arithr(s, ARITH_ADC, args[1], args[5]);
> - }
> - break;
> - case INDEX_op_sub2_i32:
> - if (const_args[4]) {
> - tgen_arithi(s, ARITH_SUB, args[0], args[4], 1);
> - } else {
> - tgen_arithr(s, ARITH_SUB, args[0], args[4]);
> - }
> - if (const_args[5]) {
> - tgen_arithi(s, ARITH_SBB, args[1], args[5], 1);
> - } else {
> - tgen_arithr(s, ARITH_SBB, args[1], args[5]);
> + tcg_out_modrm(s, OPC_SHIFT_cl + rexw, c, args[0]);
> }
> break;
> +
> case INDEX_op_brcond_i32:
> - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
> - args[3], 0);
> + tcg_out_brcond32(s, args[2], args[0], args[1], const_args[1],
> + args[3], 0);
> break;
> - case INDEX_op_brcond2_i32:
> - tcg_out_brcond2(s, args, const_args, 0);
> + case INDEX_op_setcond_i32:
> + tcg_out_setcond32(s, args[3], args[0], args[1],
> + args[2], const_args[2]);
> break;
>
> - case INDEX_op_bswap16_i32:
> + OP_32_64(bswap16):
> tcg_out_rolw_8(s, args[0]);
> break;
> - case INDEX_op_bswap32_i32:
> + OP_32_64(bswap32):
> tcg_out_bswap32(s, args[0]);
> break;
>
> - case INDEX_op_neg_i32:
> - tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, args[0]);
> + OP_32_64(neg):
> + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, args[0]);
> break;
> -
> - case INDEX_op_not_i32:
> - tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NOT, args[0]);
> + OP_32_64(not):
> + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, args[0]);
> break;
>
> - case INDEX_op_ext8s_i32:
> - tcg_out_ext8s(s, args[0], args[1]);
> + OP_32_64(ext8s):
> + tcg_out_ext8s(s, args[0], args[1], rexw);
> break;
> - case INDEX_op_ext16s_i32:
> - tcg_out_ext16s(s, args[0], args[1]);
> + OP_32_64(ext16s):
> + tcg_out_ext16s(s, args[0], args[1], rexw);
> break;
> - case INDEX_op_ext8u_i32:
> + OP_32_64(ext8u):
> tcg_out_ext8u(s, args[0], args[1]);
> break;
> - case INDEX_op_ext16u_i32:
> + OP_32_64(ext16u):
> tcg_out_ext16u(s, args[0], args[1]);
> break;
>
> - case INDEX_op_setcond_i32:
> - tcg_out_setcond(s, args[3], args[0], args[1], args[2], const_args[2]);
> - break;
> - case INDEX_op_setcond2_i32:
> - tcg_out_setcond2(s, args, const_args);
> - break;
> -
> case INDEX_op_qemu_ld8u:
> tcg_out_qemu_ld(s, args, 0);
> break;
> @@ -1314,6 +1651,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> case INDEX_op_qemu_ld16s:
> tcg_out_qemu_ld(s, args, 1 | 4);
> break;
> +#if TCG_TARGET_REG_BITS == 64
> + case INDEX_op_qemu_ld32u:
> +#endif
> case INDEX_op_qemu_ld32:
> tcg_out_qemu_ld(s, args, 2);
> break;
> @@ -1334,9 +1674,82 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
> tcg_out_qemu_st(s, args, 3);
> break;
>
> +#if TCG_TARGET_REG_BITS == 32
> + case INDEX_op_brcond2_i32:
> + tcg_out_brcond2(s, args, const_args, 0);
> + break;
> + case INDEX_op_setcond2_i32:
> + tcg_out_setcond2(s, args, const_args);
> + break;
> + case INDEX_op_mulu2_i32:
> + tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_MUL, args[3]);
> + break;
> + case INDEX_op_add2_i32:
> + if (const_args[4]) {
> + tgen_arithi(s, ARITH_ADD, args[0], args[4], 1);
> + } else {
> + tgen_arithr(s, ARITH_ADD, args[0], args[4]);
> + }
> + if (const_args[5]) {
> + tgen_arithi(s, ARITH_ADC, args[1], args[5], 1);
> + } else {
> + tgen_arithr(s, ARITH_ADC, args[1], args[5]);
> + }
> + break;
> + case INDEX_op_sub2_i32:
> + if (const_args[4]) {
> + tgen_arithi(s, ARITH_SUB, args[0], args[4], 1);
> + } else {
> + tgen_arithr(s, ARITH_SUB, args[0], args[4]);
> + }
> + if (const_args[5]) {
> + tgen_arithi(s, ARITH_SBB, args[1], args[5], 1);
> + } else {
> + tgen_arithr(s, ARITH_SBB, args[1], args[5]);
> + }
> + break;
> +#else /* TCG_TARGET_REG_BITS == 64 */
> + case INDEX_op_movi_i64:
> + tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
> + break;
> + case INDEX_op_ld32s_i64:
> + tcg_out_modrm_offset(s, OPC_MOVSLQ, args[0], args[1], args[2]);
> + break;
> + case INDEX_op_ld_i64:
> + tcg_out_ld(s, TCG_TYPE_I64, args[0], args[1], args[2]);
> + break;
> + case INDEX_op_st_i64:
> + tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
> + break;
> + case INDEX_op_qemu_ld32s:
> + tcg_out_qemu_ld(s, args, 2 | 4);
> + break;
> +
> + case INDEX_op_brcond_i64:
> + tcg_out_brcond64(s, args[2], args[0], args[1], const_args[1],
> + args[3], 0);
> + break;
> + case INDEX_op_setcond_i64:
> + tcg_out_setcond64(s, args[3], args[0], args[1],
> + args[2], const_args[2]);
> + break;
> +
> + case INDEX_op_bswap64_i64:
> + tcg_out_bswap64(s, args[0]);
> + break;
> + case INDEX_op_ext32u_i64:
> + tcg_out_ext32u(s, args[0], args[1]);
> + break;
> + case INDEX_op_ext32s_i64:
> + tcg_out_ext32s(s, args[0], args[1]);
> + break;
> +#endif
> +
> default:
> tcg_abort();
> }
> +
> +#undef OP_32_64
> }
>
> static const TCGTargetOpDef x86_op_defs[] = {
> @@ -1359,7 +1772,6 @@ static const TCGTargetOpDef x86_op_defs[] = {
> { INDEX_op_add_i32, { "r", "r", "ri" } },
> { INDEX_op_sub_i32, { "r", "0", "ri" } },
> { INDEX_op_mul_i32, { "r", "0", "ri" } },
> - { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
> { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
> { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
> { INDEX_op_and_i32, { "r", "0", "ri" } },
> @@ -1374,10 +1786,6 @@ static const TCGTargetOpDef x86_op_defs[] = {
>
> { INDEX_op_brcond_i32, { "r", "ri" } },
>
> - { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
> - { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
> - { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
> -
> { INDEX_op_bswap16_i32, { "r", "0" } },
> { INDEX_op_bswap32_i32, { "r", "0" } },
>
> @@ -1391,9 +1799,75 @@ static const TCGTargetOpDef x86_op_defs[] = {
> { INDEX_op_ext16u_i32, { "r", "r" } },
>
> { INDEX_op_setcond_i32, { "q", "r", "ri" } },
> +
> +#if TCG_TARGET_REG_BITS == 32
> + { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
> + { INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
> + { INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
> + { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
> { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
> +#else
> + { INDEX_op_mov_i64, { "r", "r" } },
> + { INDEX_op_movi_i64, { "r" } },
> + { INDEX_op_ld8u_i64, { "r", "r" } },
> + { INDEX_op_ld8s_i64, { "r", "r" } },
> + { INDEX_op_ld16u_i64, { "r", "r" } },
> + { INDEX_op_ld16s_i64, { "r", "r" } },
> + { INDEX_op_ld32u_i64, { "r", "r" } },
> + { INDEX_op_ld32s_i64, { "r", "r" } },
> + { INDEX_op_ld_i64, { "r", "r" } },
> + { INDEX_op_st8_i64, { "r", "r" } },
> + { INDEX_op_st16_i64, { "r", "r" } },
> + { INDEX_op_st32_i64, { "r", "r" } },
> + { INDEX_op_st_i64, { "r", "r" } },
> +
> + { INDEX_op_add_i64, { "r", "0", "re" } },
> + { INDEX_op_mul_i64, { "r", "0", "re" } },
> + { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
> + { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
> + { INDEX_op_sub_i64, { "r", "0", "re" } },
> + { INDEX_op_and_i64, { "r", "0", "reZ" } },
> + { INDEX_op_or_i64, { "r", "0", "re" } },
> + { INDEX_op_xor_i64, { "r", "0", "re" } },
> +
> + { INDEX_op_shl_i64, { "r", "0", "ci" } },
> + { INDEX_op_shr_i64, { "r", "0", "ci" } },
> + { INDEX_op_sar_i64, { "r", "0", "ci" } },
> + { INDEX_op_rotl_i64, { "r", "0", "ci" } },
> + { INDEX_op_rotr_i64, { "r", "0", "ci" } },
> +
> + { INDEX_op_brcond_i64, { "r", "re" } },
> + { INDEX_op_setcond_i64, { "r", "r", "re" } },
> +
> + { INDEX_op_bswap16_i64, { "r", "0" } },
> + { INDEX_op_bswap32_i64, { "r", "0" } },
> + { INDEX_op_bswap64_i64, { "r", "0" } },
> + { INDEX_op_neg_i64, { "r", "0" } },
> + { INDEX_op_not_i64, { "r", "0" } },
> +
> + { INDEX_op_ext8s_i64, { "r", "r" } },
> + { INDEX_op_ext16s_i64, { "r", "r" } },
> + { INDEX_op_ext32s_i64, { "r", "r" } },
> + { INDEX_op_ext8u_i64, { "r", "r" } },
> + { INDEX_op_ext16u_i64, { "r", "r" } },
> + { INDEX_op_ext32u_i64, { "r", "r" } },
> +#endif
>
> -#if TARGET_LONG_BITS == 32
> +#if TCG_TARGET_REG_BITS == 64
> + { INDEX_op_qemu_ld8u, { "r", "L" } },
> + { INDEX_op_qemu_ld8s, { "r", "L" } },
> + { INDEX_op_qemu_ld16u, { "r", "L" } },
> + { INDEX_op_qemu_ld16s, { "r", "L" } },
> + { INDEX_op_qemu_ld32, { "r", "L" } },
> + { INDEX_op_qemu_ld32u, { "r", "L" } },
> + { INDEX_op_qemu_ld32s, { "r", "L" } },
> + { INDEX_op_qemu_ld64, { "r", "L" } },
> +
> + { INDEX_op_qemu_st8, { "L", "L" } },
> + { INDEX_op_qemu_st16, { "L", "L" } },
> + { INDEX_op_qemu_st32, { "L", "L" } },
> + { INDEX_op_qemu_st64, { "L", "L" } },
> +#elif TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
> { INDEX_op_qemu_ld8u, { "r", "L" } },
> { INDEX_op_qemu_ld8s, { "r", "L" } },
> { INDEX_op_qemu_ld16u, { "r", "L" } },
> @@ -1422,11 +1896,19 @@ static const TCGTargetOpDef x86_op_defs[] = {
> };
>
> static int tcg_target_callee_save_regs[] = {
> - /* TCG_REG_EBP, */ /* currently used for the global env, so no
> - need to save */
> +#if TCG_TARGET_REG_BITS == 64
> + TCG_REG_RBP,
> + TCG_REG_RBX,
> + TCG_REG_R12,
> + TCG_REG_R13,
> + /* TCG_REG_R14, */ /* Currently used for the global env. */
> + TCG_REG_R15,
> +#else
> + /* TCG_REG_EBP, */ /* Currently used for the global env. */
> TCG_REG_EBX,
> TCG_REG_ESI,
> TCG_REG_EDI,
> +#endif
> };
>
> /* Generate global QEMU prologue and epilogue code */
> @@ -1435,27 +1917,34 @@ static void tcg_target_qemu_prologue(TCGContext *s)
> int i, frame_size, push_size, stack_addend;
>
> /* TB prologue */
> - /* save all callee saved registers */
> - for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
> +
> + /* Save all callee saved registers. */
> + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
> tcg_out_push(s, tcg_target_callee_save_regs[i]);
> }
> - /* reserve some stack space */
> - push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4;
> +
> + /* Reserve some stack space. */
> + push_size = 1 + ARRAY_SIZE(tcg_target_callee_save_regs);
> + push_size *= TCG_TARGET_REG_BITS / 8;
> +
> frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
> frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
> ~(TCG_TARGET_STACK_ALIGN - 1);
> stack_addend = frame_size - push_size;
> tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
>
> - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_EAX); /* jmp *%eax */
> + /* jmp *tb. */
> + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[0]);
>
> /* TB epilogue */
> tb_ret_addr = s->code_ptr;
> +
> tcg_out_addi(s, TCG_REG_ESP, stack_addend);
> - for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
> +
> + for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
> tcg_out_pop(s, tcg_target_callee_save_regs[i]);
> }
> - tcg_out_opc(s, OPC_RET);
> + tcg_out_opc(s, OPC_RET, 0, 0, 0);
> }
>
> static void tcg_target_init(TCGContext *s)
> @@ -1466,12 +1955,25 @@ static void tcg_target_init(TCGContext *s)
> tcg_abort();
> #endif
>
> - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
> + if (TCG_TARGET_REG_BITS == 64) {
> + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
> + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
> + } else {
> + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff);
> + }
>
> tcg_regset_clear(tcg_target_call_clobber_regs);
> tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EAX);
> tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_EDX);
> tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_ECX);
> + if (TCG_TARGET_REG_BITS == 64) {
> + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RDI);
> + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_RSI);
> + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
> + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
> + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
> + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
> + }
>
> tcg_regset_clear(s->reserved_regs);
> tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP);
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index ca1d730..bfafbfc 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -23,10 +23,18 @@
> */
> #define TCG_TARGET_I386 1
>
> -#define TCG_TARGET_REG_BITS 32
> +#if defined(__x86_64__)
> +# define TCG_TARGET_REG_BITS 64
> +#else
> +# define TCG_TARGET_REG_BITS 32
> +#endif
> //#define TCG_TARGET_WORDS_BIGENDIAN
>
> -#define TCG_TARGET_NB_REGS 8
> +#if TCG_TARGET_REG_BITS == 64
> +# define TCG_TARGET_NB_REGS 16
> +#else
> +# define TCG_TARGET_NB_REGS 8
> +#endif
>
> enum {
> TCG_REG_EAX = 0,
> @@ -37,8 +45,30 @@ enum {
> TCG_REG_EBP,
> TCG_REG_ESI,
> TCG_REG_EDI,
> +
> + /* 64-bit registers; always define the symbols to avoid
> + too much if-deffing. */
> + TCG_REG_R8,
> + TCG_REG_R9,
> + TCG_REG_R10,
> + TCG_REG_R11,
> + TCG_REG_R12,
> + TCG_REG_R13,
> + TCG_REG_R14,
> + TCG_REG_R15,
> + TCG_REG_RAX = TCG_REG_EAX,
> + TCG_REG_RCX = TCG_REG_ECX,
> + TCG_REG_RDX = TCG_REG_EDX,
> + TCG_REG_RBX = TCG_REG_EBX,
> + TCG_REG_RSP = TCG_REG_ESP,
> + TCG_REG_RBP = TCG_REG_EBP,
> + TCG_REG_RSI = TCG_REG_ESI,
> + TCG_REG_RDI = TCG_REG_EDI,
> };
>
> +#define TCG_CT_CONST_S32 0x100
> +#define TCG_CT_CONST_U32 0x200
> +
> /* used for function call generation */
> #define TCG_REG_CALL_STACK TCG_REG_ESP
> #define TCG_TARGET_STACK_ALIGN 16
> @@ -61,10 +91,35 @@ enum {
> // #define TCG_TARGET_HAS_nand_i32
> // #define TCG_TARGET_HAS_nor_i32
>
> +#if TCG_TARGET_REG_BITS == 64
> +#define TCG_TARGET_HAS_div2_i64
> +#define TCG_TARGET_HAS_rot_i64
> +#define TCG_TARGET_HAS_ext8s_i64
> +#define TCG_TARGET_HAS_ext16s_i64
> +#define TCG_TARGET_HAS_ext32s_i64
> +#define TCG_TARGET_HAS_ext8u_i64
> +#define TCG_TARGET_HAS_ext16u_i64
> +#define TCG_TARGET_HAS_ext32u_i64
> +#define TCG_TARGET_HAS_bswap16_i64
> +#define TCG_TARGET_HAS_bswap32_i64
> +#define TCG_TARGET_HAS_bswap64_i64
> +#define TCG_TARGET_HAS_neg_i64
> +#define TCG_TARGET_HAS_not_i64
> +// #define TCG_TARGET_HAS_andc_i64
> +// #define TCG_TARGET_HAS_orc_i64
> +// #define TCG_TARGET_HAS_eqv_i64
> +// #define TCG_TARGET_HAS_nand_i64
> +// #define TCG_TARGET_HAS_nor_i64
> +#endif
> +
> #define TCG_TARGET_HAS_GUEST_BASE
>
> /* Note: must be synced with dyngen-exec.h */
> -#define TCG_AREG0 TCG_REG_EBP
> +#if TCG_TARGET_REG_BITS == 64
> +# define TCG_AREG0 TCG_REG_R14
> +#else
> +# define TCG_AREG0 TCG_REG_EBP
> +#endif
>
> static inline void flush_icache_range(unsigned long start, unsigned long stop)
> {
> diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c
> deleted file mode 100644
> index 490666e..0000000
> --- a/tcg/x86_64/tcg-target.c
> +++ /dev/null
> @@ -1,1445 +0,0 @@
> -/*
> - * Tiny Code Generator for QEMU
> - *
> - * Copyright (c) 2008 Fabrice Bellard
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a copy
> - * of this software and associated documentation files (the "Software"), to deal
> - * in the Software without restriction, including without limitation the rights
> - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> - * copies of the Software, and to permit persons to whom the Software is
> - * furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> - * THE SOFTWARE.
> - */
> -
> -#ifndef NDEBUG
> -static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
> - "%rax",
> - "%rcx",
> - "%rdx",
> - "%rbx",
> - "%rsp",
> - "%rbp",
> - "%rsi",
> - "%rdi",
> - "%r8",
> - "%r9",
> - "%r10",
> - "%r11",
> - "%r12",
> - "%r13",
> - "%r14",
> - "%r15",
> -};
> -#endif
> -
> -static const int tcg_target_reg_alloc_order[] = {
> - TCG_REG_RBP,
> - TCG_REG_RBX,
> - TCG_REG_R12,
> - TCG_REG_R13,
> - TCG_REG_R14,
> - TCG_REG_R15,
> - TCG_REG_R10,
> - TCG_REG_R11,
> - TCG_REG_R9,
> - TCG_REG_R8,
> - TCG_REG_RCX,
> - TCG_REG_RDX,
> - TCG_REG_RSI,
> - TCG_REG_RDI,
> - TCG_REG_RAX,
> -};
> -
> -static const int tcg_target_call_iarg_regs[6] = {
> - TCG_REG_RDI,
> - TCG_REG_RSI,
> - TCG_REG_RDX,
> - TCG_REG_RCX,
> - TCG_REG_R8,
> - TCG_REG_R9,
> -};
> -
> -static const int tcg_target_call_oarg_regs[2] = {
> - TCG_REG_RAX,
> - TCG_REG_RDX
> -};
> -
> -static uint8_t *tb_ret_addr;
> -
> -static void patch_reloc(uint8_t *code_ptr, int type,
> - tcg_target_long value, tcg_target_long addend)
> -{
> - value += addend;
> - switch(type) {
> - case R_X86_64_32:
> - if (value != (uint32_t)value)
> - tcg_abort();
> - *(uint32_t *)code_ptr = value;
> - break;
> - case R_X86_64_32S:
> - if (value != (int32_t)value)
> - tcg_abort();
> - *(uint32_t *)code_ptr = value;
> - break;
> - case R_386_PC32:
> - value -= (long)code_ptr;
> - if (value != (int32_t)value)
> - tcg_abort();
> - *(uint32_t *)code_ptr = value;
> - break;
> - default:
> - tcg_abort();
> - }
> -}
> -
> -/* maximum number of register used for input function arguments */
> -static inline int tcg_target_get_call_iarg_regs_count(int flags)
> -{
> - return 6;
> -}
> -
> -/* parse target specific constraints */
> -static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
> -{
> - const char *ct_str;
> -
> - ct_str = *pct_str;
> - switch(ct_str[0]) {
> - case 'a':
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set_reg(ct->u.regs, TCG_REG_RAX);
> - break;
> - case 'b':
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set_reg(ct->u.regs, TCG_REG_RBX);
> - break;
> - case 'c':
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set_reg(ct->u.regs, TCG_REG_RCX);
> - break;
> - case 'd':
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set_reg(ct->u.regs, TCG_REG_RDX);
> - break;
> - case 'S':
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set_reg(ct->u.regs, TCG_REG_RSI);
> - break;
> - case 'D':
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set_reg(ct->u.regs, TCG_REG_RDI);
> - break;
> - case 'q':
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set32(ct->u.regs, 0, 0xf);
> - break;
> - case 'r':
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set32(ct->u.regs, 0, 0xffff);
> - break;
> - case 'L': /* qemu_ld/st constraint */
> - ct->ct |= TCG_CT_REG;
> - tcg_regset_set32(ct->u.regs, 0, 0xffff);
> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_RSI);
> - tcg_regset_reset_reg(ct->u.regs, TCG_REG_RDI);
> - break;
> - case 'e':
> - ct->ct |= TCG_CT_CONST_S32;
> - break;
> - case 'Z':
> - ct->ct |= TCG_CT_CONST_U32;
> - break;
> - default:
> - return -1;
> - }
> - ct_str++;
> - *pct_str = ct_str;
> - return 0;
> -}
> -
> -/* test if a constant matches the constraint */
> -static inline int tcg_target_const_match(tcg_target_long val,
> - const TCGArgConstraint *arg_ct)
> -{
> - int ct;
> - ct = arg_ct->ct;
> - if (ct & TCG_CT_CONST)
> - return 1;
> - else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val)
> - return 1;
> - else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val)
> - return 1;
> - else
> - return 0;
> -}
> -
> -#define ARITH_ADD 0
> -#define ARITH_OR 1
> -#define ARITH_ADC 2
> -#define ARITH_SBB 3
> -#define ARITH_AND 4
> -#define ARITH_SUB 5
> -#define ARITH_XOR 6
> -#define ARITH_CMP 7
> -
> -#define SHIFT_ROL 0
> -#define SHIFT_ROR 1
> -#define SHIFT_SHL 4
> -#define SHIFT_SHR 5
> -#define SHIFT_SAR 7
> -
> -#define JCC_JMP (-1)
> -#define JCC_JO 0x0
> -#define JCC_JNO 0x1
> -#define JCC_JB 0x2
> -#define JCC_JAE 0x3
> -#define JCC_JE 0x4
> -#define JCC_JNE 0x5
> -#define JCC_JBE 0x6
> -#define JCC_JA 0x7
> -#define JCC_JS 0x8
> -#define JCC_JNS 0x9
> -#define JCC_JP 0xa
> -#define JCC_JNP 0xb
> -#define JCC_JL 0xc
> -#define JCC_JGE 0xd
> -#define JCC_JLE 0xe
> -#define JCC_JG 0xf
> -
> -#define P_EXT 0x100 /* 0x0f opcode prefix */
> -#define P_REXW 0x200 /* set rex.w = 1 */
> -#define P_REXB_R 0x400 /* REG field as byte register */
> -#define P_REXB_RM 0x800 /* R/M field as byte register */
> -
> -static const uint8_t tcg_cond_to_jcc[10] = {
> - [TCG_COND_EQ] = JCC_JE,
> - [TCG_COND_NE] = JCC_JNE,
> - [TCG_COND_LT] = JCC_JL,
> - [TCG_COND_GE] = JCC_JGE,
> - [TCG_COND_LE] = JCC_JLE,
> - [TCG_COND_GT] = JCC_JG,
> - [TCG_COND_LTU] = JCC_JB,
> - [TCG_COND_GEU] = JCC_JAE,
> - [TCG_COND_LEU] = JCC_JBE,
> - [TCG_COND_GTU] = JCC_JA,
> -};
> -
> -static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
> -{
> - int rex = 0;
> -
> - rex |= (opc & P_REXW) >> 6; /* REX.W */
> - rex |= (r & 8) >> 1; /* REX.R */
> - rex |= (x & 8) >> 2; /* REX.X */
> - rex |= (rm & 8) >> 3; /* REX.B */
> -
> - /* P_REXB_{R,RM} indicates that the given register is the low byte.
> - For %[abcd]l we need no REX prefix, but for %{si,di,bp,sp}l we do,
> - as otherwise the encoding indicates %[abcd]h. Note that the values
> - that are ORed in merely indicate that the REX byte must be present;
> - those bits get discarded in output. */
> - rex |= opc & (r >= 4 ? P_REXB_R : 0);
> - rex |= opc & (rm >= 4 ? P_REXB_RM : 0);
> -
> - if (rex) {
> - tcg_out8(s, (uint8_t)(rex | 0x40));
> - }
> - if (opc & P_EXT) {
> - tcg_out8(s, 0x0f);
> - }
> - tcg_out8(s, opc & 0xff);
> -}
> -
> -static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
> -{
> - tcg_out_opc(s, opc, r, rm, 0);
> - tcg_out8(s, 0xc0 | ((r & 7) << 3) | (rm & 7));
> -}
> -
> -/* rm < 0 means no register index plus (-rm - 1 immediate bytes) */
> -static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm,
> - tcg_target_long offset)
> -{
> - if (rm < 0) {
> - tcg_target_long val;
> - tcg_out_opc(s, opc, r, 0, 0);
> - val = offset - ((tcg_target_long)s->code_ptr + 5 + (-rm - 1));
> - if (val == (int32_t)val) {
> - /* eip relative */
> - tcg_out8(s, 0x05 | ((r & 7) << 3));
> - tcg_out32(s, val);
> - } else if (offset == (int32_t)offset) {
> - tcg_out8(s, 0x04 | ((r & 7) << 3));
> - tcg_out8(s, 0x25); /* sib */
> - tcg_out32(s, offset);
> - } else {
> - tcg_abort();
> - }
> - } else if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
> - tcg_out_opc(s, opc, r, rm, 0);
> - if ((rm & 7) == TCG_REG_RSP) {
> - tcg_out8(s, 0x04 | ((r & 7) << 3));
> - tcg_out8(s, 0x24);
> - } else {
> - tcg_out8(s, 0x00 | ((r & 7) << 3) | (rm & 7));
> - }
> - } else if ((int8_t)offset == offset) {
> - tcg_out_opc(s, opc, r, rm, 0);
> - if ((rm & 7) == TCG_REG_RSP) {
> - tcg_out8(s, 0x44 | ((r & 7) << 3));
> - tcg_out8(s, 0x24);
> - } else {
> - tcg_out8(s, 0x40 | ((r & 7) << 3) | (rm & 7));
> - }
> - tcg_out8(s, offset);
> - } else {
> - tcg_out_opc(s, opc, r, rm, 0);
> - if ((rm & 7) == TCG_REG_RSP) {
> - tcg_out8(s, 0x84 | ((r & 7) << 3));
> - tcg_out8(s, 0x24);
> - } else {
> - tcg_out8(s, 0x80 | ((r & 7) << 3) | (rm & 7));
> - }
> - tcg_out32(s, offset);
> - }
> -}
> -
> -#if defined(CONFIG_SOFTMMU)
> -/* XXX: incomplete. index must be different from ESP */
> -static void tcg_out_modrm_offset2(TCGContext *s, int opc, int r, int rm,
> - int index, int shift,
> - tcg_target_long offset)
> -{
> - int mod;
> - if (rm == -1)
> - tcg_abort();
> - if (offset == 0 && (rm & 7) != TCG_REG_RBP) {
> - mod = 0;
> - } else if (offset == (int8_t)offset) {
> - mod = 0x40;
> - } else if (offset == (int32_t)offset) {
> - mod = 0x80;
> - } else {
> - tcg_abort();
> - }
> - if (index == -1) {
> - tcg_out_opc(s, opc, r, rm, 0);
> - if ((rm & 7) == TCG_REG_RSP) {
> - tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
> - tcg_out8(s, 0x04 | (rm & 7));
> - } else {
> - tcg_out8(s, mod | ((r & 7) << 3) | (rm & 7));
> - }
> - } else {
> - tcg_out_opc(s, opc, r, rm, index);
> - tcg_out8(s, mod | ((r & 7) << 3) | 0x04);
> - tcg_out8(s, (shift << 6) | ((index & 7) << 3) | (rm & 7));
> - }
> - if (mod == 0x40) {
> - tcg_out8(s, offset);
> - } else if (mod == 0x80) {
> - tcg_out32(s, offset);
> - }
> -}
> -#endif
> -
> -static inline void tcg_out_mov(TCGContext *s, TCGType type, int ret, int arg)
> -{
> - int rexw = (type == TCG_TYPE_I64 ? P_REXW : 0);
> - tcg_out_modrm(s, 0x8b | rexw, ret, arg);
> -}
> -
> -static inline void tcg_out_movi(TCGContext *s, TCGType type,
> - int ret, tcg_target_long arg)
> -{
> - if (arg == 0) {
> - tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); /* xor r0,r0 */
> - } else if (arg == (uint32_t)arg || type == TCG_TYPE_I32) {
> - tcg_out_opc(s, 0xb8 + (ret & 7), 0, ret, 0);
> - tcg_out32(s, arg);
> - } else if (arg == (int32_t)arg) {
> - tcg_out_modrm(s, 0xc7 | P_REXW, 0, ret);
> - tcg_out32(s, arg);
> - } else {
> - tcg_out_opc(s, (0xb8 + (ret & 7)) | P_REXW, 0, ret, 0);
> - tcg_out32(s, arg);
> - tcg_out32(s, arg >> 32);
> - }
> -}
> -
> -static void tcg_out_goto(TCGContext *s, int call, uint8_t *target)
> -{
> - int32_t disp;
> -
> - disp = target - s->code_ptr - 5;
> - if (disp == (target - s->code_ptr - 5)) {
> - tcg_out8(s, call ? 0xe8 : 0xe9);
> - tcg_out32(s, disp);
> - } else {
> - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R10, (tcg_target_long) target);
> - tcg_out_modrm(s, 0xff, call ? 2 : 4, TCG_REG_R10);
> - }
> -}
> -
> -static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
> - int arg1, tcg_target_long arg2)
> -{
> - if (type == TCG_TYPE_I32)
> - tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2); /* movl */
> - else
> - tcg_out_modrm_offset(s, 0x8b | P_REXW, ret, arg1, arg2); /* movq */
> -}
> -
> -static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
> - int arg1, tcg_target_long arg2)
> -{
> - if (type == TCG_TYPE_I32)
> - tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2); /* movl */
> - else
> - tcg_out_modrm_offset(s, 0x89 | P_REXW, arg, arg1, arg2); /* movq */
> -}
> -
> -static inline void tgen_arithi32(TCGContext *s, int c, int r0, int32_t val)
> -{
> - if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) {
> - /* inc */
> - tcg_out_modrm(s, 0xff, 0, r0);
> - } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
> - /* dec */
> - tcg_out_modrm(s, 0xff, 1, r0);
> - } else if (val == (int8_t)val) {
> - tcg_out_modrm(s, 0x83, c, r0);
> - tcg_out8(s, val);
> - } else if (c == ARITH_AND && val == 0xffu) {
> - /* movzbl */
> - tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, r0, r0);
> - } else if (c == ARITH_AND && val == 0xffffu) {
> - /* movzwl */
> - tcg_out_modrm(s, 0xb7 | P_EXT, r0, r0);
> - } else {
> - tcg_out_modrm(s, 0x81, c, r0);
> - tcg_out32(s, val);
> - }
> -}
> -
> -static inline void tgen_arithi64(TCGContext *s, int c, int r0, int64_t val)
> -{
> - if ((c == ARITH_ADD && val == 1) || (c == ARITH_SUB && val == -1)) {
> - /* inc */
> - tcg_out_modrm(s, 0xff | P_REXW, 0, r0);
> - } else if ((c == ARITH_ADD && val == -1) || (c == ARITH_SUB && val == 1)) {
> - /* dec */
> - tcg_out_modrm(s, 0xff | P_REXW, 1, r0);
> - } else if (c == ARITH_AND && val == 0xffffffffu) {
> - /* 32-bit mov zero extends */
> - tcg_out_modrm(s, 0x8b, r0, r0);
> - } else if (c == ARITH_AND && val == (uint32_t)val) {
> - /* AND with no high bits set can use a 32-bit operation. */
> - tgen_arithi32(s, c, r0, (uint32_t)val);
> - } else if (val == (int8_t)val) {
> - tcg_out_modrm(s, 0x83 | P_REXW, c, r0);
> - tcg_out8(s, val);
> - } else if (val == (int32_t)val) {
> - tcg_out_modrm(s, 0x81 | P_REXW, c, r0);
> - tcg_out32(s, val);
> - } else {
> - tcg_abort();
> - }
> -}
> -
> -static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
> -{
> - if (val != 0)
> - tgen_arithi64(s, ARITH_ADD, reg, val);
> -}
> -
> -static void tcg_out_jxx(TCGContext *s, int opc, int label_index)
> -{
> - int32_t val, val1;
> - TCGLabel *l = &s->labels[label_index];
> -
> - if (l->has_value) {
> - val = l->u.value - (tcg_target_long)s->code_ptr;
> - val1 = val - 2;
> - if ((int8_t)val1 == val1) {
> - if (opc == -1)
> - tcg_out8(s, 0xeb);
> - else
> - tcg_out8(s, 0x70 + opc);
> - tcg_out8(s, val1);
> - } else {
> - if (opc == -1) {
> - tcg_out8(s, 0xe9);
> - tcg_out32(s, val - 5);
> - } else {
> - tcg_out8(s, 0x0f);
> - tcg_out8(s, 0x80 + opc);
> - tcg_out32(s, val - 6);
> - }
> - }
> - } else {
> - if (opc == -1) {
> - tcg_out8(s, 0xe9);
> - } else {
> - tcg_out8(s, 0x0f);
> - tcg_out8(s, 0x80 + opc);
> - }
> - tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
> - s->code_ptr += 4;
> - }
> -}
> -
> -static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2,
> - int const_arg2, int rexw)
> -{
> - if (const_arg2) {
> - if (arg2 == 0) {
> - /* test r, r */
> - tcg_out_modrm(s, 0x85 | rexw, arg1, arg1);
> - } else {
> - if (rexw) {
> - tgen_arithi64(s, ARITH_CMP, arg1, arg2);
> - } else {
> - tgen_arithi32(s, ARITH_CMP, arg1, arg2);
> - }
> - }
> - } else {
> - tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3) | rexw, arg2, arg1);
> - }
> -}
> -
> -static void tcg_out_brcond(TCGContext *s, TCGCond cond,
> - TCGArg arg1, TCGArg arg2, int const_arg2,
> - int label_index, int rexw)
> -{
> - tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
> - tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index);
> -}
> -
> -static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg dest,
> - TCGArg arg1, TCGArg arg2, int const_arg2, int rexw)
> -{
> - tcg_out_cmp(s, arg1, arg2, const_arg2, rexw);
> - /* setcc */
> - tcg_out_modrm(s, 0x90 | tcg_cond_to_jcc[cond] | P_EXT | P_REXB_RM, 0, dest);
> - tgen_arithi32(s, ARITH_AND, dest, 0xff);
> -}
> -
> -#if defined(CONFIG_SOFTMMU)
> -
> -#include "../../softmmu_defs.h"
> -
> -static void *qemu_ld_helpers[4] = {
> - __ldb_mmu,
> - __ldw_mmu,
> - __ldl_mmu,
> - __ldq_mmu,
> -};
> -
> -static void *qemu_st_helpers[4] = {
> - __stb_mmu,
> - __stw_mmu,
> - __stl_mmu,
> - __stq_mmu,
> -};
> -#endif
> -
> -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
> - int opc)
> -{
> - int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
> - int32_t offset;
> -#if defined(CONFIG_SOFTMMU)
> - uint8_t *label1_ptr, *label2_ptr;
> -#endif
> -
> - data_reg = *args++;
> - addr_reg = *args++;
> - mem_index = *args;
> - s_bits = opc & 3;
> -
> - r0 = TCG_REG_RDI;
> - r1 = TCG_REG_RSI;
> -
> -#if TARGET_LONG_BITS == 32
> - rexw = 0;
> -#else
> - rexw = P_REXW;
> -#endif
> -#if defined(CONFIG_SOFTMMU)
> - tcg_out_mov(s, TCG_TYPE_TL, r1, addr_reg);
> - tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
> -
> - tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
> - tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
> -
> - tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
> - tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
> -
> - tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
> - tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
> -
> - /* lea offset(r1, env), r1 */
> - tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
> - offsetof(CPUState, tlb_table[mem_index][0].addr_read));
> -
> - /* cmp 0(r1), r0 */
> - tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
> -
> - tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
> -
> - /* je label1 */
> - tcg_out8(s, 0x70 + JCC_JE);
> - label1_ptr = s->code_ptr;
> - s->code_ptr++;
> -
> - /* XXX: move that code at the end of the TB */
> - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RSI, mem_index);
> - tcg_out_goto(s, 1, qemu_ld_helpers[s_bits]);
> -
> - switch(opc) {
> - case 0 | 4:
> - /* movsbq */
> - tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
> - break;
> - case 1 | 4:
> - /* movswq */
> - tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
> - break;
> - case 2 | 4:
> - /* movslq */
> - tcg_out_modrm(s, 0x63 | P_REXW, data_reg, TCG_REG_RAX);
> - break;
> - case 0:
> - /* movzbq */
> - tcg_out_modrm(s, 0xb6 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
> - break;
> - case 1:
> - /* movzwq */
> - tcg_out_modrm(s, 0xb7 | P_EXT | P_REXW, data_reg, TCG_REG_RAX);
> - break;
> - case 2:
> - default:
> - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_RAX);
> - break;
> - case 3:
> - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX);
> - break;
> - }
> -
> - /* jmp label2 */
> - tcg_out8(s, 0xeb);
> - label2_ptr = s->code_ptr;
> - s->code_ptr++;
> -
> - /* label1: */
> - *label1_ptr = s->code_ptr - label1_ptr - 1;
> -
> - /* add x(r1), r0 */
> - tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
> - offsetof(CPUTLBEntry, addr_read));
> - offset = 0;
> -#else
> - if (GUEST_BASE == (int32_t)GUEST_BASE) {
> - r0 = addr_reg;
> - offset = GUEST_BASE;
> - } else {
> - offset = 0;
> - /* movq $GUEST_BASE, r0 */
> - tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
> - tcg_out32(s, GUEST_BASE);
> - tcg_out32(s, GUEST_BASE >> 32);
> - /* addq addr_reg, r0 */
> - tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
> - }
> -#endif
> -
> -#ifdef TARGET_WORDS_BIGENDIAN
> - bswap = 1;
> -#else
> - bswap = 0;
> -#endif
> - switch(opc) {
> - case 0:
> - /* movzbl */
> - tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, offset);
> - break;
> - case 0 | 4:
> - /* movsbX */
> - tcg_out_modrm_offset(s, 0xbe | P_EXT | rexw, data_reg, r0, offset);
> - break;
> - case 1:
> - /* movzwl */
> - tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
> - if (bswap) {
> - /* rolw $8, data_reg */
> - tcg_out8(s, 0x66);
> - tcg_out_modrm(s, 0xc1, 0, data_reg);
> - tcg_out8(s, 8);
> - }
> - break;
> - case 1 | 4:
> - if (bswap) {
> - /* movzwl */
> - tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, offset);
> - /* rolw $8, data_reg */
> - tcg_out8(s, 0x66);
> - tcg_out_modrm(s, 0xc1, 0, data_reg);
> - tcg_out8(s, 8);
> -
> - /* movswX data_reg, data_reg */
> - tcg_out_modrm(s, 0xbf | P_EXT | rexw, data_reg, data_reg);
> - } else {
> - /* movswX */
> - tcg_out_modrm_offset(s, 0xbf | P_EXT | rexw, data_reg, r0, offset);
> - }
> - break;
> - case 2:
> - /* movl (r0), data_reg */
> - tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
> - if (bswap) {
> - /* bswap */
> - tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
> - }
> - break;
> - case 2 | 4:
> - if (bswap) {
> - /* movl (r0), data_reg */
> - tcg_out_modrm_offset(s, 0x8b, data_reg, r0, offset);
> - /* bswap */
> - tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT, 0, data_reg, 0);
> - /* movslq */
> - tcg_out_modrm(s, 0x63 | P_REXW, data_reg, data_reg);
> - } else {
> - /* movslq */
> - tcg_out_modrm_offset(s, 0x63 | P_REXW, data_reg, r0, offset);
> - }
> - break;
> - case 3:
> - /* movq (r0), data_reg */
> - tcg_out_modrm_offset(s, 0x8b | P_REXW, data_reg, r0, offset);
> - if (bswap) {
> - /* bswap */
> - tcg_out_opc(s, (0xc8 + (data_reg & 7)) | P_EXT | P_REXW, 0, data_reg, 0);
> - }
> - break;
> - default:
> - tcg_abort();
> - }
> -
> -#if defined(CONFIG_SOFTMMU)
> - /* label2: */
> - *label2_ptr = s->code_ptr - label2_ptr - 1;
> -#endif
> -}
> -
> -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
> - int opc)
> -{
> - int addr_reg, data_reg, r0, r1, mem_index, s_bits, bswap, rexw;
> - int32_t offset;
> -#if defined(CONFIG_SOFTMMU)
> - uint8_t *label1_ptr, *label2_ptr;
> -#endif
> -
> - data_reg = *args++;
> - addr_reg = *args++;
> - mem_index = *args;
> -
> - s_bits = opc;
> -
> - r0 = TCG_REG_RDI;
> - r1 = TCG_REG_RSI;
> -
> -#if TARGET_LONG_BITS == 32
> - rexw = 0;
> -#else
> - rexw = P_REXW;
> -#endif
> -#if defined(CONFIG_SOFTMMU)
> - tcg_out_mov(s, TCG_TYPE_TL, r1, addr_reg);
> - tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
> -
> - tcg_out_modrm(s, 0xc1 | rexw, 5, r1); /* shr $x, r1 */
> - tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
> -
> - tcg_out_modrm(s, 0x81 | rexw, 4, r0); /* andl $x, r0 */
> - tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
> -
> - tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */
> - tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
> -
> - /* lea offset(r1, env), r1 */
> - tcg_out_modrm_offset2(s, 0x8d | P_REXW, r1, r1, TCG_AREG0, 0,
> - offsetof(CPUState, tlb_table[mem_index][0].addr_write));
> -
> - /* cmp 0(r1), r0 */
> - tcg_out_modrm_offset(s, 0x3b | rexw, r0, r1, 0);
> -
> - tcg_out_mov(s, TCG_TYPE_TL, r0, addr_reg);
> -
> - /* je label1 */
> - tcg_out8(s, 0x70 + JCC_JE);
> - label1_ptr = s->code_ptr;
> - s->code_ptr++;
> -
> - /* XXX: move that code at the end of the TB */
> - switch(opc) {
> - case 0:
> - /* movzbl */
> - tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, TCG_REG_RSI, data_reg);
> - break;
> - case 1:
> - /* movzwl */
> - tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_RSI, data_reg);
> - break;
> - case 2:
> - tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_RSI, data_reg);
> - break;
> - default:
> - case 3:
> - tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_RSI, data_reg);
> - break;
> - }
> - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_RDX, mem_index);
> - tcg_out_goto(s, 1, qemu_st_helpers[s_bits]);
> -
> - /* jmp label2 */
> - tcg_out8(s, 0xeb);
> - label2_ptr = s->code_ptr;
> - s->code_ptr++;
> -
> - /* label1: */
> - *label1_ptr = s->code_ptr - label1_ptr - 1;
> -
> - /* add x(r1), r0 */
> - tcg_out_modrm_offset(s, 0x03 | P_REXW, r0, r1, offsetof(CPUTLBEntry, addend) -
> - offsetof(CPUTLBEntry, addr_write));
> - offset = 0;
> -#else
> - if (GUEST_BASE == (int32_t)GUEST_BASE) {
> - r0 = addr_reg;
> - offset = GUEST_BASE;
> - } else {
> - offset = 0;
> - /* movq $GUEST_BASE, r0 */
> - tcg_out_opc(s, (0xb8 + (r0 & 7)) | P_REXW, 0, r0, 0);
> - tcg_out32(s, GUEST_BASE);
> - tcg_out32(s, GUEST_BASE >> 32);
> - /* addq addr_reg, r0 */
> - tcg_out_modrm(s, 0x01 | P_REXW, addr_reg, r0);
> - }
> -#endif
> -
> -#ifdef TARGET_WORDS_BIGENDIAN
> - bswap = 1;
> -#else
> - bswap = 0;
> -#endif
> - switch(opc) {
> - case 0:
> - /* movb */
> - tcg_out_modrm_offset(s, 0x88 | P_REXB_R, data_reg, r0, offset);
> - break;
> - case 1:
> - if (bswap) {
> - tcg_out_mov(s, TCG_TYPE_I32, r1, data_reg);
> - tcg_out8(s, 0x66); /* rolw $8, %ecx */
> - tcg_out_modrm(s, 0xc1, 0, r1);
> - tcg_out8(s, 8);
> - data_reg = r1;
> - }
> - /* movw */
> - tcg_out8(s, 0x66);
> - tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
> - break;
> - case 2:
> - if (bswap) {
> - tcg_out_mov(s, TCG_TYPE_I32, r1, data_reg);
> - /* bswap data_reg */
> - tcg_out_opc(s, (0xc8 + r1) | P_EXT, 0, r1, 0);
> - data_reg = r1;
> - }
> - /* movl */
> - tcg_out_modrm_offset(s, 0x89, data_reg, r0, offset);
> - break;
> - case 3:
> - if (bswap) {
> - tcg_out_mov(s, TCG_TYPE_I64, r1, data_reg);
> - /* bswap data_reg */
> - tcg_out_opc(s, (0xc8 + r1) | P_EXT | P_REXW, 0, r1, 0);
> - data_reg = r1;
> - }
> - /* movq */
> - tcg_out_modrm_offset(s, 0x89 | P_REXW, data_reg, r0, offset);
> - break;
> - default:
> - tcg_abort();
> - }
> -
> -#if defined(CONFIG_SOFTMMU)
> - /* label2: */
> - *label2_ptr = s->code_ptr - label2_ptr - 1;
> -#endif
> -}
> -
> -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> - const int *const_args)
> -{
> - int c;
> -
> - switch(opc) {
> - case INDEX_op_exit_tb:
> - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, args[0]);
> - tcg_out_goto(s, 0, tb_ret_addr);
> - break;
> - case INDEX_op_goto_tb:
> - if (s->tb_jmp_offset) {
> - /* direct jump method */
> - tcg_out8(s, 0xe9); /* jmp im */
> - s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
> - tcg_out32(s, 0);
> - } else {
> - /* indirect jump method */
> - /* jmp Ev */
> - tcg_out_modrm_offset(s, 0xff, 4, -1,
> - (tcg_target_long)(s->tb_next +
> - args[0]));
> - }
> - s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
> - break;
> - case INDEX_op_call:
> - if (const_args[0]) {
> - tcg_out_goto(s, 1, (void *) args[0]);
> - } else {
> - tcg_out_modrm(s, 0xff, 2, args[0]);
> - }
> - break;
> - case INDEX_op_jmp:
> - if (const_args[0]) {
> - tcg_out_goto(s, 0, (void *) args[0]);
> - } else {
> - tcg_out_modrm(s, 0xff, 4, args[0]);
> - }
> - break;
> - case INDEX_op_br:
> - tcg_out_jxx(s, JCC_JMP, args[0]);
> - break;
> - case INDEX_op_movi_i32:
> - tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
> - break;
> - case INDEX_op_movi_i64:
> - tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
> - break;
> - case INDEX_op_ld8u_i32:
> - case INDEX_op_ld8u_i64:
> - /* movzbl */
> - tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_ld8s_i32:
> - /* movsbl */
> - tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_ld8s_i64:
> - /* movsbq */
> - tcg_out_modrm_offset(s, 0xbe | P_EXT | P_REXW, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_ld16u_i32:
> - case INDEX_op_ld16u_i64:
> - /* movzwl */
> - tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_ld16s_i32:
> - /* movswl */
> - tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_ld16s_i64:
> - /* movswq */
> - tcg_out_modrm_offset(s, 0xbf | P_EXT | P_REXW, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_ld_i32:
> - case INDEX_op_ld32u_i64:
> - /* movl */
> - tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_ld32s_i64:
> - /* movslq */
> - tcg_out_modrm_offset(s, 0x63 | P_REXW, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_ld_i64:
> - /* movq */
> - tcg_out_modrm_offset(s, 0x8b | P_REXW, args[0], args[1], args[2]);
> - break;
> -
> - case INDEX_op_st8_i32:
> - case INDEX_op_st8_i64:
> - /* movb */
> - tcg_out_modrm_offset(s, 0x88 | P_REXB_R, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_st16_i32:
> - case INDEX_op_st16_i64:
> - /* movw */
> - tcg_out8(s, 0x66);
> - tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_st_i32:
> - case INDEX_op_st32_i64:
> - /* movl */
> - tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]);
> - break;
> - case INDEX_op_st_i64:
> - /* movq */
> - tcg_out_modrm_offset(s, 0x89 | P_REXW, args[0], args[1], args[2]);
> - break;
> -
> - case INDEX_op_sub_i32:
> - c = ARITH_SUB;
> - goto gen_arith32;
> - case INDEX_op_and_i32:
> - c = ARITH_AND;
> - goto gen_arith32;
> - case INDEX_op_or_i32:
> - c = ARITH_OR;
> - goto gen_arith32;
> - case INDEX_op_xor_i32:
> - c = ARITH_XOR;
> - goto gen_arith32;
> - case INDEX_op_add_i32:
> - c = ARITH_ADD;
> - gen_arith32:
> - if (const_args[2]) {
> - tgen_arithi32(s, c, args[0], args[2]);
> - } else {
> - tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]);
> - }
> - break;
> -
> - case INDEX_op_sub_i64:
> - c = ARITH_SUB;
> - goto gen_arith64;
> - case INDEX_op_and_i64:
> - c = ARITH_AND;
> - goto gen_arith64;
> - case INDEX_op_or_i64:
> - c = ARITH_OR;
> - goto gen_arith64;
> - case INDEX_op_xor_i64:
> - c = ARITH_XOR;
> - goto gen_arith64;
> - case INDEX_op_add_i64:
> - c = ARITH_ADD;
> - gen_arith64:
> - if (const_args[2]) {
> - tgen_arithi64(s, c, args[0], args[2]);
> - } else {
> - tcg_out_modrm(s, 0x01 | (c << 3) | P_REXW, args[2], args[0]);
> - }
> - break;
> -
> - case INDEX_op_mul_i32:
> - if (const_args[2]) {
> - int32_t val;
> - val = args[2];
> - if (val == (int8_t)val) {
> - tcg_out_modrm(s, 0x6b, args[0], args[0]);
> - tcg_out8(s, val);
> - } else {
> - tcg_out_modrm(s, 0x69, args[0], args[0]);
> - tcg_out32(s, val);
> - }
> - } else {
> - tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]);
> - }
> - break;
> - case INDEX_op_mul_i64:
> - if (const_args[2]) {
> - int32_t val;
> - val = args[2];
> - if (val == (int8_t)val) {
> - tcg_out_modrm(s, 0x6b | P_REXW, args[0], args[0]);
> - tcg_out8(s, val);
> - } else {
> - tcg_out_modrm(s, 0x69 | P_REXW, args[0], args[0]);
> - tcg_out32(s, val);
> - }
> - } else {
> - tcg_out_modrm(s, 0xaf | P_EXT | P_REXW, args[0], args[2]);
> - }
> - break;
> - case INDEX_op_div2_i32:
> - tcg_out_modrm(s, 0xf7, 7, args[4]);
> - break;
> - case INDEX_op_divu2_i32:
> - tcg_out_modrm(s, 0xf7, 6, args[4]);
> - break;
> - case INDEX_op_div2_i64:
> - tcg_out_modrm(s, 0xf7 | P_REXW, 7, args[4]);
> - break;
> - case INDEX_op_divu2_i64:
> - tcg_out_modrm(s, 0xf7 | P_REXW, 6, args[4]);
> - break;
> -
> - case INDEX_op_shl_i32:
> - c = SHIFT_SHL;
> - gen_shift32:
> - if (const_args[2]) {
> - if (args[2] == 1) {
> - tcg_out_modrm(s, 0xd1, c, args[0]);
> - } else {
> - tcg_out_modrm(s, 0xc1, c, args[0]);
> - tcg_out8(s, args[2]);
> - }
> - } else {
> - tcg_out_modrm(s, 0xd3, c, args[0]);
> - }
> - break;
> - case INDEX_op_shr_i32:
> - c = SHIFT_SHR;
> - goto gen_shift32;
> - case INDEX_op_sar_i32:
> - c = SHIFT_SAR;
> - goto gen_shift32;
> - case INDEX_op_rotl_i32:
> - c = SHIFT_ROL;
> - goto gen_shift32;
> - case INDEX_op_rotr_i32:
> - c = SHIFT_ROR;
> - goto gen_shift32;
> -
> - case INDEX_op_shl_i64:
> - c = SHIFT_SHL;
> - gen_shift64:
> - if (const_args[2]) {
> - if (args[2] == 1) {
> - tcg_out_modrm(s, 0xd1 | P_REXW, c, args[0]);
> - } else {
> - tcg_out_modrm(s, 0xc1 | P_REXW, c, args[0]);
> - tcg_out8(s, args[2]);
> - }
> - } else {
> - tcg_out_modrm(s, 0xd3 | P_REXW, c, args[0]);
> - }
> - break;
> - case INDEX_op_shr_i64:
> - c = SHIFT_SHR;
> - goto gen_shift64;
> - case INDEX_op_sar_i64:
> - c = SHIFT_SAR;
> - goto gen_shift64;
> - case INDEX_op_rotl_i64:
> - c = SHIFT_ROL;
> - goto gen_shift64;
> - case INDEX_op_rotr_i64:
> - c = SHIFT_ROR;
> - goto gen_shift64;
> -
> - case INDEX_op_brcond_i32:
> - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
> - args[3], 0);
> - break;
> - case INDEX_op_brcond_i64:
> - tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
> - args[3], P_REXW);
> - break;
> -
> - case INDEX_op_bswap16_i32:
> - case INDEX_op_bswap16_i64:
> - tcg_out8(s, 0x66);
> - tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]);
> - tcg_out8(s, 8);
> - break;
> - case INDEX_op_bswap32_i32:
> - case INDEX_op_bswap32_i64:
> - tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT, 0, args[0], 0);
> - break;
> - case INDEX_op_bswap64_i64:
> - tcg_out_opc(s, (0xc8 + (args[0] & 7)) | P_EXT | P_REXW, 0, args[0], 0);
> - break;
> -
> - case INDEX_op_neg_i32:
> - tcg_out_modrm(s, 0xf7, 3, args[0]);
> - break;
> - case INDEX_op_neg_i64:
> - tcg_out_modrm(s, 0xf7 | P_REXW, 3, args[0]);
> - break;
> -
> - case INDEX_op_not_i32:
> - tcg_out_modrm(s, 0xf7, 2, args[0]);
> - break;
> - case INDEX_op_not_i64:
> - tcg_out_modrm(s, 0xf7 | P_REXW, 2, args[0]);
> - break;
> -
> - case INDEX_op_ext8s_i32:
> - tcg_out_modrm(s, 0xbe | P_EXT | P_REXB_RM, args[0], args[1]);
> - break;
> - case INDEX_op_ext16s_i32:
> - tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]);
> - break;
> - case INDEX_op_ext8s_i64:
> - tcg_out_modrm(s, 0xbe | P_EXT | P_REXW, args[0], args[1]);
> - break;
> - case INDEX_op_ext16s_i64:
> - tcg_out_modrm(s, 0xbf | P_EXT | P_REXW, args[0], args[1]);
> - break;
> - case INDEX_op_ext32s_i64:
> - tcg_out_modrm(s, 0x63 | P_REXW, args[0], args[1]);
> - break;
> - case INDEX_op_ext8u_i32:
> - case INDEX_op_ext8u_i64:
> - tcg_out_modrm(s, 0xb6 | P_EXT | P_REXB_RM, args[0], args[1]);
> - break;
> - case INDEX_op_ext16u_i32:
> - case INDEX_op_ext16u_i64:
> - tcg_out_modrm(s, 0xb7 | P_EXT, args[0], args[1]);
> - break;
> - case INDEX_op_ext32u_i64:
> - tcg_out_modrm(s, 0x8b, args[0], args[1]);
> - break;
> -
> - case INDEX_op_setcond_i32:
> - tcg_out_setcond(s, args[3], args[0], args[1], args[2],
> - const_args[2], 0);
> - break;
> - case INDEX_op_setcond_i64:
> - tcg_out_setcond(s, args[3], args[0], args[1], args[2],
> - const_args[2], P_REXW);
> - break;
> -
> - case INDEX_op_qemu_ld8u:
> - tcg_out_qemu_ld(s, args, 0);
> - break;
> - case INDEX_op_qemu_ld8s:
> - tcg_out_qemu_ld(s, args, 0 | 4);
> - break;
> - case INDEX_op_qemu_ld16u:
> - tcg_out_qemu_ld(s, args, 1);
> - break;
> - case INDEX_op_qemu_ld16s:
> - tcg_out_qemu_ld(s, args, 1 | 4);
> - break;
> - case INDEX_op_qemu_ld32:
> - case INDEX_op_qemu_ld32u:
> - tcg_out_qemu_ld(s, args, 2);
> - break;
> - case INDEX_op_qemu_ld32s:
> - tcg_out_qemu_ld(s, args, 2 | 4);
> - break;
> - case INDEX_op_qemu_ld64:
> - tcg_out_qemu_ld(s, args, 3);
> - break;
> -
> - case INDEX_op_qemu_st8:
> - tcg_out_qemu_st(s, args, 0);
> - break;
> - case INDEX_op_qemu_st16:
> - tcg_out_qemu_st(s, args, 1);
> - break;
> - case INDEX_op_qemu_st32:
> - tcg_out_qemu_st(s, args, 2);
> - break;
> - case INDEX_op_qemu_st64:
> - tcg_out_qemu_st(s, args, 3);
> - break;
> -
> - default:
> - tcg_abort();
> - }
> -}
> -
> -static int tcg_target_callee_save_regs[] = {
> - TCG_REG_RBP,
> - TCG_REG_RBX,
> - TCG_REG_R12,
> - TCG_REG_R13,
> - /* TCG_REG_R14, */ /* currently used for the global env, so no
> - need to save */
> - TCG_REG_R15,
> -};
> -
> -static inline void tcg_out_push(TCGContext *s, int reg)
> -{
> - tcg_out_opc(s, (0x50 + (reg & 7)), 0, reg, 0);
> -}
> -
> -static inline void tcg_out_pop(TCGContext *s, int reg)
> -{
> - tcg_out_opc(s, (0x58 + (reg & 7)), 0, reg, 0);
> -}
> -
> -/* Generate global QEMU prologue and epilogue code */
> -static void tcg_target_qemu_prologue(TCGContext *s)
> -{
> - int i, frame_size, push_size, stack_addend;
> -
> - /* TB prologue */
> - /* save all callee saved registers */
> - for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
> - tcg_out_push(s, tcg_target_callee_save_regs[i]);
> -
> - }
> - /* reserve some stack space */
> - push_size = 8 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8;
> - frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE;
> - frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
> - ~(TCG_TARGET_STACK_ALIGN - 1);
> - stack_addend = frame_size - push_size;
> - tcg_out_addi(s, TCG_REG_RSP, -stack_addend);
> -
> - tcg_out_modrm(s, 0xff, 4, TCG_REG_RDI); /* jmp *%rdi */
> -
> - /* TB epilogue */
> - tb_ret_addr = s->code_ptr;
> - tcg_out_addi(s, TCG_REG_RSP, stack_addend);
> - for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
> - tcg_out_pop(s, tcg_target_callee_save_regs[i]);
> - }
> - tcg_out8(s, 0xc3); /* ret */
> -}
> -
> -static const TCGTargetOpDef x86_64_op_defs[] = {
> - { INDEX_op_exit_tb, { } },
> - { INDEX_op_goto_tb, { } },
> - { INDEX_op_call, { "ri" } }, /* XXX: might need a specific constant constraint */
> - { INDEX_op_jmp, { "ri" } }, /* XXX: might need a specific constant constraint */
> - { INDEX_op_br, { } },
> -
> - { INDEX_op_mov_i32, { "r", "r" } },
> - { INDEX_op_movi_i32, { "r" } },
> - { INDEX_op_ld8u_i32, { "r", "r" } },
> - { INDEX_op_ld8s_i32, { "r", "r" } },
> - { INDEX_op_ld16u_i32, { "r", "r" } },
> - { INDEX_op_ld16s_i32, { "r", "r" } },
> - { INDEX_op_ld_i32, { "r", "r" } },
> - { INDEX_op_st8_i32, { "r", "r" } },
> - { INDEX_op_st16_i32, { "r", "r" } },
> - { INDEX_op_st_i32, { "r", "r" } },
> -
> - { INDEX_op_add_i32, { "r", "0", "ri" } },
> - { INDEX_op_mul_i32, { "r", "0", "ri" } },
> - { INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } },
> - { INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } },
> - { INDEX_op_sub_i32, { "r", "0", "ri" } },
> - { INDEX_op_and_i32, { "r", "0", "ri" } },
> - { INDEX_op_or_i32, { "r", "0", "ri" } },
> - { INDEX_op_xor_i32, { "r", "0", "ri" } },
> -
> - { INDEX_op_shl_i32, { "r", "0", "ci" } },
> - { INDEX_op_shr_i32, { "r", "0", "ci" } },
> - { INDEX_op_sar_i32, { "r", "0", "ci" } },
> - { INDEX_op_rotl_i32, { "r", "0", "ci" } },
> - { INDEX_op_rotr_i32, { "r", "0", "ci" } },
> -
> - { INDEX_op_brcond_i32, { "r", "ri" } },
> -
> - { INDEX_op_mov_i64, { "r", "r" } },
> - { INDEX_op_movi_i64, { "r" } },
> - { INDEX_op_ld8u_i64, { "r", "r" } },
> - { INDEX_op_ld8s_i64, { "r", "r" } },
> - { INDEX_op_ld16u_i64, { "r", "r" } },
> - { INDEX_op_ld16s_i64, { "r", "r" } },
> - { INDEX_op_ld32u_i64, { "r", "r" } },
> - { INDEX_op_ld32s_i64, { "r", "r" } },
> - { INDEX_op_ld_i64, { "r", "r" } },
> - { INDEX_op_st8_i64, { "r", "r" } },
> - { INDEX_op_st16_i64, { "r", "r" } },
> - { INDEX_op_st32_i64, { "r", "r" } },
> - { INDEX_op_st_i64, { "r", "r" } },
> -
> - { INDEX_op_add_i64, { "r", "0", "re" } },
> - { INDEX_op_mul_i64, { "r", "0", "re" } },
> - { INDEX_op_div2_i64, { "a", "d", "0", "1", "r" } },
> - { INDEX_op_divu2_i64, { "a", "d", "0", "1", "r" } },
> - { INDEX_op_sub_i64, { "r", "0", "re" } },
> - { INDEX_op_and_i64, { "r", "0", "reZ" } },
> - { INDEX_op_or_i64, { "r", "0", "re" } },
> - { INDEX_op_xor_i64, { "r", "0", "re" } },
> -
> - { INDEX_op_shl_i64, { "r", "0", "ci" } },
> - { INDEX_op_shr_i64, { "r", "0", "ci" } },
> - { INDEX_op_sar_i64, { "r", "0", "ci" } },
> - { INDEX_op_rotl_i64, { "r", "0", "ci" } },
> - { INDEX_op_rotr_i64, { "r", "0", "ci" } },
> -
> - { INDEX_op_brcond_i64, { "r", "re" } },
> -
> - { INDEX_op_bswap16_i32, { "r", "0" } },
> - { INDEX_op_bswap16_i64, { "r", "0" } },
> - { INDEX_op_bswap32_i32, { "r", "0" } },
> - { INDEX_op_bswap32_i64, { "r", "0" } },
> - { INDEX_op_bswap64_i64, { "r", "0" } },
> -
> - { INDEX_op_neg_i32, { "r", "0" } },
> - { INDEX_op_neg_i64, { "r", "0" } },
> -
> - { INDEX_op_not_i32, { "r", "0" } },
> - { INDEX_op_not_i64, { "r", "0" } },
> -
> - { INDEX_op_ext8s_i32, { "r", "r"} },
> - { INDEX_op_ext16s_i32, { "r", "r"} },
> - { INDEX_op_ext8s_i64, { "r", "r"} },
> - { INDEX_op_ext16s_i64, { "r", "r"} },
> - { INDEX_op_ext32s_i64, { "r", "r"} },
> - { INDEX_op_ext8u_i32, { "r", "r"} },
> - { INDEX_op_ext16u_i32, { "r", "r"} },
> - { INDEX_op_ext8u_i64, { "r", "r"} },
> - { INDEX_op_ext16u_i64, { "r", "r"} },
> - { INDEX_op_ext32u_i64, { "r", "r"} },
> -
> - { INDEX_op_setcond_i32, { "r", "r", "ri" } },
> - { INDEX_op_setcond_i64, { "r", "r", "re" } },
> -
> - { INDEX_op_qemu_ld8u, { "r", "L" } },
> - { INDEX_op_qemu_ld8s, { "r", "L" } },
> - { INDEX_op_qemu_ld16u, { "r", "L" } },
> - { INDEX_op_qemu_ld16s, { "r", "L" } },
> - { INDEX_op_qemu_ld32, { "r", "L" } },
> - { INDEX_op_qemu_ld32u, { "r", "L" } },
> - { INDEX_op_qemu_ld32s, { "r", "L" } },
> - { INDEX_op_qemu_ld64, { "r", "L" } },
> -
> - { INDEX_op_qemu_st8, { "L", "L" } },
> - { INDEX_op_qemu_st16, { "L", "L" } },
> - { INDEX_op_qemu_st32, { "L", "L" } },
> - { INDEX_op_qemu_st64, { "L", "L" } },
> -
> - { -1 },
> -};
> -
> -static void tcg_target_init(TCGContext *s)
> -{
> -#if !defined(CONFIG_USER_ONLY)
> - /* fail safe */
> - if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
> - tcg_abort();
> -#endif
> -
> - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
> - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
> - tcg_regset_set32(tcg_target_call_clobber_regs, 0,
> - (1 << TCG_REG_RDI) |
> - (1 << TCG_REG_RSI) |
> - (1 << TCG_REG_RDX) |
> - (1 << TCG_REG_RCX) |
> - (1 << TCG_REG_R8) |
> - (1 << TCG_REG_R9) |
> - (1 << TCG_REG_RAX) |
> - (1 << TCG_REG_R10) |
> - (1 << TCG_REG_R11));
> -
> - tcg_regset_clear(s->reserved_regs);
> - tcg_regset_set_reg(s->reserved_regs, TCG_REG_RSP);
> -
> - tcg_add_target_add_op_defs(x86_64_op_defs);
> -}
> diff --git a/tcg/x86_64/tcg-target.h b/tcg/x86_64/tcg-target.h
> deleted file mode 100644
> index e0eabaa..0000000
> --- a/tcg/x86_64/tcg-target.h
> +++ /dev/null
> @@ -1,101 +0,0 @@
> -/*
> - * Tiny Code Generator for QEMU
> - *
> - * Copyright (c) 2008 Fabrice Bellard
> - *
> - * Permission is hereby granted, free of charge, to any person obtaining a copy
> - * of this software and associated documentation files (the "Software"), to deal
> - * in the Software without restriction, including without limitation the rights
> - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> - * copies of the Software, and to permit persons to whom the Software is
> - * furnished to do so, subject to the following conditions:
> - *
> - * The above copyright notice and this permission notice shall be included in
> - * all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> - * THE SOFTWARE.
> - */
> -#define TCG_TARGET_X86_64 1
> -
> -#define TCG_TARGET_REG_BITS 64
> -//#define TCG_TARGET_WORDS_BIGENDIAN
> -
> -#define TCG_TARGET_NB_REGS 16
> -
> -enum {
> - TCG_REG_RAX = 0,
> - TCG_REG_RCX,
> - TCG_REG_RDX,
> - TCG_REG_RBX,
> - TCG_REG_RSP,
> - TCG_REG_RBP,
> - TCG_REG_RSI,
> - TCG_REG_RDI,
> - TCG_REG_R8,
> - TCG_REG_R9,
> - TCG_REG_R10,
> - TCG_REG_R11,
> - TCG_REG_R12,
> - TCG_REG_R13,
> - TCG_REG_R14,
> - TCG_REG_R15,
> -};
> -
> -#define TCG_CT_CONST_S32 0x100
> -#define TCG_CT_CONST_U32 0x200
> -
> -/* used for function call generation */
> -#define TCG_REG_CALL_STACK TCG_REG_RSP
> -#define TCG_TARGET_STACK_ALIGN 16
> -#define TCG_TARGET_CALL_STACK_OFFSET 0
> -
> -/* optional instructions */
> -#define TCG_TARGET_HAS_div2_i32
> -#define TCG_TARGET_HAS_div2_i64
> -#define TCG_TARGET_HAS_bswap16_i32
> -#define TCG_TARGET_HAS_bswap16_i64
> -#define TCG_TARGET_HAS_bswap32_i32
> -#define TCG_TARGET_HAS_bswap32_i64
> -#define TCG_TARGET_HAS_bswap64_i64
> -#define TCG_TARGET_HAS_neg_i32
> -#define TCG_TARGET_HAS_neg_i64
> -#define TCG_TARGET_HAS_not_i32
> -#define TCG_TARGET_HAS_not_i64
> -#define TCG_TARGET_HAS_ext8s_i32
> -#define TCG_TARGET_HAS_ext16s_i32
> -#define TCG_TARGET_HAS_ext8s_i64
> -#define TCG_TARGET_HAS_ext16s_i64
> -#define TCG_TARGET_HAS_ext32s_i64
> -#define TCG_TARGET_HAS_ext8u_i32
> -#define TCG_TARGET_HAS_ext16u_i32
> -#define TCG_TARGET_HAS_ext8u_i64
> -#define TCG_TARGET_HAS_ext16u_i64
> -#define TCG_TARGET_HAS_ext32u_i64
> -#define TCG_TARGET_HAS_rot_i32
> -#define TCG_TARGET_HAS_rot_i64
> -
> -// #define TCG_TARGET_HAS_andc_i32
> -// #define TCG_TARGET_HAS_andc_i64
> -// #define TCG_TARGET_HAS_orc_i32
> -// #define TCG_TARGET_HAS_orc_i64
> -// #define TCG_TARGET_HAS_eqv_i32
> -// #define TCG_TARGET_HAS_eqv_i64
> -// #define TCG_TARGET_HAS_nand_i32
> -// #define TCG_TARGET_HAS_nand_i64
> -// #define TCG_TARGET_HAS_nor_i32
> -// #define TCG_TARGET_HAS_nor_i64
> -
> -#define TCG_TARGET_HAS_GUEST_BASE
> -
> -/* Note: must be synced with dyngen-exec.h */
> -#define TCG_AREG0 TCG_REG_R14
> -
> -static inline void flush_icache_range(unsigned long start, unsigned long stop)
> -{
> -}
> --
> 1.7.0.1
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2010-06-09 22:18 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-06-03 0:26 [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 Richard Henderson
2010-06-03 0:26 ` [Qemu-devel] [PATCH 1/2] tcg: Add TYPE parameter to tcg_out_mov Richard Henderson
2010-06-04 19:19 ` Blue Swirl
2010-06-04 19:34 ` Richard Henderson
2010-06-03 0:26 ` [Qemu-devel] [PATCH 2/2] tcg: Make some tcg-target.c routines static Richard Henderson
2010-06-03 9:23 ` [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 malc
2010-06-04 0:35 ` [Qemu-devel] [PATCH 0/2] tcg-i386: merge 64-bit, guest_base improvement Richard Henderson
2010-06-04 0:35 ` [Qemu-devel] [PATCH 1/2] tcg-i386: Merge 64-bit generation Richard Henderson
2010-06-09 22:18 ` Aurelien Jarno
2010-06-04 0:35 ` [Qemu-devel] [PATCH 2/2] tcg-i386: Use segment registers to implement GUEST_BASE Richard Henderson
2010-06-04 6:35 ` Alexander Graf
2010-06-07 19:45 ` Richard Henderson
2010-06-09 9:42 ` [Qemu-devel] [PATCH 0/2] tcg cleanups, part 4 Aurelien Jarno
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