* [U-Boot] [PATCH 0/4] make egiga common to kirkwood and orion5x
@ 2010-07-02 16:53 Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga Albert Aribaud
0 siblings, 1 reply; 18+ messages in thread
From: Albert Aribaud @ 2010-07-02 16:53 UTC (permalink / raw)
To: u-boot
Republishing the patchset as a submission as the RFC did not
meet any comment so far.
SHORT STORY
This patchset separates egiga from kirkwood then adds orion5x support
in egiga. It has been duly, and successfully, tested on an OpenRD-Client
after each of the four commits and on an EDMini V2 after the last commit.
LONG STORY
This is a set of four atomic commits.
the first commit separates the file renames from the content changes
so that the renaming remains visible in git at 100% similarity.
The second commit removes functional dependencies (calls to kirkwood
functions from egiga; these were RAM base and size functions, actually
accessible via the global gd variable, just like other drivers do).
The third commit deals with mostly cosmetic changes by removing any
"KIRKWOOD", "KW", "kirkwood" or "kw" from egiga symbols which are not
actually kirkwood-related, and renames kirkwood_egiga_initialize to
egiga_initialize in the egiga driver, in netdev.h and in cpu.c of the
kirkwood SoC support code.
These three commits together perform the separation of egiga from
kirkwood.
The last commit adds the actual orion5s support. Note that it contains
an important change to egiga: the addition of the 'volatile' qualifier
to members of the structs representing egiga registers and descriptors.
This was needed on orion5x, as without the volatile qualifiers, reads
and writes th these structs could happen in unexpected order; in
egiga_send() this caused the egiga DMA engine to get started before
the DMA TX descriptor was actually filled in, with the effect that
the actual sent packet was all zeroes. I cannot explain why this did
not happen on kirkwood, except that maybe the CPU speed difference made
it possible for the core to finish writing the descriptor before the DMA
engine could start.
All commits were tested on a kirkwood-based OpenRD Client for regression
avoidance; the last commit was also tested on an orion5x-based ED Mini V2
for functionality validation.
Albert Aribaud (4):
ARM: Rename kirkwood_egiga driver to egiga
egiga: Remove functional dependency on kirkwood
egiga: remove references to kirkwood SoC
egiga: add support for orion5x
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 4 +-
arch/arm/cpu/arm926ejs/orion5x/cpu.c | 18 +
arch/arm/include/asm/arch-kirkwood/kirkwood.h | 10 +
arch/arm/include/asm/arch-orion5x/orion5x.h | 5 +
board/LaCie/edminiv2/edminiv2.c | 36 ++
board/LaCie/edminiv2/edminiv2.h | 41 ++
drivers/net/Makefile | 2 +-
drivers/net/egiga.c | 728 +++++++++++++++++++++++++
drivers/net/egiga.h | 505 +++++++++++++++++
drivers/net/kirkwood_egiga.c | 719 ------------------------
drivers/net/kirkwood_egiga.h | 505 -----------------
include/configs/edminiv2.h | 30 +-
include/configs/guruplug.h | 4 +-
include/configs/km_arm.h | 4 +-
include/configs/mv88f6281gtw_ge.h | 4 +-
include/configs/openrd_base.h | 4 +-
include/configs/rd6281a.h | 4 +-
include/configs/sheevaplug.h | 4 +-
include/netdev.h | 2 +-
19 files changed, 1382 insertions(+), 1247 deletions(-)
create mode 100644 board/LaCie/edminiv2/edminiv2.h
create mode 100644 drivers/net/egiga.c
create mode 100644 drivers/net/egiga.h
delete mode 100644 drivers/net/kirkwood_egiga.c
delete mode 100644 drivers/net/kirkwood_egiga.h
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga
2010-07-02 16:53 [U-Boot] [PATCH 0/4] make egiga common to kirkwood and orion5x Albert Aribaud
@ 2010-07-02 16:53 ` Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Albert Aribaud
` (2 more replies)
0 siblings, 3 replies; 18+ messages in thread
From: Albert Aribaud @ 2010-07-02 16:53 UTC (permalink / raw)
To: u-boot
The names of the egiga files mention kirkwood
even though they are not kirkwood-specific - change them.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
drivers/net/Makefile | 2 +-
drivers/net/egiga.c | 719 ++++++++++++++++++++++++++++++++++++++++++
drivers/net/egiga.h | 505 +++++++++++++++++++++++++++++
drivers/net/kirkwood_egiga.c | 719 ------------------------------------------
drivers/net/kirkwood_egiga.h | 505 -----------------------------
5 files changed, 1225 insertions(+), 1225 deletions(-)
create mode 100644 drivers/net/egiga.c
create mode 100644 drivers/net/egiga.h
delete mode 100644 drivers/net/kirkwood_egiga.c
delete mode 100644 drivers/net/kirkwood_egiga.h
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b75c02f..8853908 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -46,7 +46,7 @@ COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
COBJS-$(CONFIG_GRETH) += greth.o
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
-COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
+COBJS-$(CONFIG_KIRKWOOD_EGIGA) += egiga.o
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
COBJS-$(CONFIG_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_MACB) += macb.o
diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
new file mode 100644
index 0000000..50e8ff3
--- /dev/null
+++ b/drivers/net/egiga.c
@@ -0,0 +1,719 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * (C) Copyright 2003
+ * Ingo Assmus <ingo.assmus@keymile.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh at galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <asm/errno.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <asm/arch/kirkwood.h>
+#include "egiga.h"
+
+#define KIRKWOOD_PHY_ADR_REQUEST 0xee
+#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
+
+/*
+ * smi_reg_read - miiphy_read callback function.
+ *
+ * Returns 16bit phy register value, or 0xffff on error
+ */
+static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+ struct kwgbe_registers *regs = dkwgbe->regs;
+ u32 smi_reg;
+ u32 timeout;
+
+ /* Phyadr read request */
+ if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
+ reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
+ /* */
+ *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
+ return 0;
+ }
+ /* check parameters */
+ if (phy_adr > PHYADR_MASK) {
+ printf("Err..(%s) Invalid PHY address %d\n",
+ __FUNCTION__, phy_adr);
+ return -EFAULT;
+ }
+ if (reg_ofs > PHYREG_MASK) {
+ printf("Err..(%s) Invalid register offset %d\n",
+ __FUNCTION__, reg_ofs);
+ return -EFAULT;
+ }
+
+ timeout = KWGBE_PHY_SMI_TIMEOUT;
+ /* wait till the SMI is not busy */
+ do {
+ /* read smi register */
+ smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ if (timeout-- == 0) {
+ printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
+ return -EFAULT;
+ }
+ } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+
+ /* fill the phy address and regiser offset and read opcode */
+ smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
+ | KWGBE_PHY_SMI_OPCODE_READ;
+
+ /* write the smi register */
+ KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+
+ /*wait till read value is ready */
+ timeout = KWGBE_PHY_SMI_TIMEOUT;
+
+ do {
+ /* read smi register */
+ smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ if (timeout-- == 0) {
+ printf("Err..(%s) SMI read ready timeout\n",
+ __FUNCTION__);
+ return -EFAULT;
+ }
+ } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
+
+ /* Wait for the data to update in the SMI register */
+ for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
+
+ *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
+
+ debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
+ reg_ofs, *data);
+
+ return 0;
+}
+
+/*
+ * smi_reg_write - imiiphy_write callback function.
+ *
+ * Returns 0 if write succeed, -EINVAL on bad parameters
+ * -ETIME on timeout
+ */
+static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+ struct kwgbe_registers *regs = dkwgbe->regs;
+ u32 smi_reg;
+ u32 timeout;
+
+ /* Phyadr write request*/
+ if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
+ reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
+ KWGBEREG_WR(regs->phyadr, data);
+ return 0;
+ }
+
+ /* check parameters */
+ if (phy_adr > PHYADR_MASK) {
+ printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
+ return -EINVAL;
+ }
+ if (reg_ofs > PHYREG_MASK) {
+ printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
+ return -EINVAL;
+ }
+
+ /* wait till the SMI is not busy */
+ timeout = KWGBE_PHY_SMI_TIMEOUT;
+ do {
+ /* read smi register */
+ smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ if (timeout-- == 0) {
+ printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
+ return -ETIME;
+ }
+ } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+
+ /* fill the phy addr and reg offset and write opcode and data */
+ smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
+ smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
+ smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
+
+ /* write the smi register */
+ KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+
+ return 0;
+}
+
+/* Stop and checks all queues */
+static void stop_queue(u32 * qreg)
+{
+ u32 reg_data;
+
+ reg_data = readl(qreg);
+
+ if (reg_data & 0xFF) {
+ /* Issue stop command for active channels only */
+ writel((reg_data << 8), qreg);
+
+ /* Wait for all queue activity to terminate. */
+ do {
+ /*
+ * Check port cause register that all queues
+ * are stopped
+ */
+ reg_data = readl(qreg);
+ }
+ while (reg_data & 0xFF);
+ }
+}
+
+/*
+ * set_access_control - Config address decode parameters for Ethernet unit
+ *
+ * This function configures the address decode parameters for the Gigabit
+ * Ethernet Controller according the given parameters struct.
+ *
+ * @regs Register struct pointer.
+ * @param Address decode parameter struct.
+ */
+static void set_access_control(struct kwgbe_registers *regs,
+ struct kwgbe_winparam *param)
+{
+ u32 access_prot_reg;
+
+ /* Set access control register */
+ access_prot_reg = KWGBEREG_RD(regs->epap);
+ /* clear window permission */
+ access_prot_reg &= (~(3 << (param->win * 2)));
+ access_prot_reg |= (param->access_ctrl << (param->win * 2));
+ KWGBEREG_WR(regs->epap, access_prot_reg);
+
+ /* Set window Size reg (SR) */
+ KWGBEREG_WR(regs->barsz[param->win].size,
+ (((param->size / 0x10000) - 1) << 16));
+
+ /* Set window Base address reg (BA) */
+ KWGBEREG_WR(regs->barsz[param->win].bar,
+ (param->target | param->attrib | param->base_addr));
+ /* High address remap reg (HARR) */
+ if (param->win < 4)
+ KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
+
+ /* Base address enable reg (BARER) */
+ if (param->enable == 1)
+ KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
+ else
+ KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
+}
+
+static void set_dram_access(struct kwgbe_registers *regs)
+{
+ struct kwgbe_winparam win_param;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ /* Set access parameters for DRAM bank i */
+ win_param.win = i; /* Use Ethernet window i */
+ /* Window target - DDR */
+ win_param.target = KWGBE_TARGET_DRAM;
+ /* Enable full access */
+ win_param.access_ctrl = EWIN_ACCESS_FULL;
+ win_param.high_addr = 0;
+ /* Get bank base */
+ win_param.base_addr = kw_sdram_bar(i);
+ win_param.size = kw_sdram_bs(i); /* Get bank size */
+ if (win_param.size == 0)
+ win_param.enable = 0;
+ else
+ win_param.enable = 1; /* Enable the access */
+
+ /* Enable DRAM bank */
+ switch (i) {
+ case 0:
+ win_param.attrib = EBAR_DRAM_CS0;
+ break;
+ case 1:
+ win_param.attrib = EBAR_DRAM_CS1;
+ break;
+ case 2:
+ win_param.attrib = EBAR_DRAM_CS2;
+ break;
+ case 3:
+ win_param.attrib = EBAR_DRAM_CS3;
+ break;
+ default:
+ /* invalide bank, disable access */
+ win_param.enable = 0;
+ win_param.attrib = 0;
+ break;
+ }
+ /* Set the access control for address window(EPAPR) RD/WR */
+ set_access_control(regs, &win_param);
+ }
+}
+
+/*
+ * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
+ *
+ * Go through all the DA filter tables (Unicast, Special Multicast & Other
+ * Multicast) and set each entry to 0.
+ */
+static void port_init_mac_tables(struct kwgbe_registers *regs)
+{
+ int table_index;
+
+ /* Clear DA filter unicast table (Ex_dFUT) */
+ for (table_index = 0; table_index < 4; ++table_index)
+ KWGBEREG_WR(regs->dfut[table_index], 0);
+
+ for (table_index = 0; table_index < 64; ++table_index) {
+ /* Clear DA filter special multicast table (Ex_dFSMT) */
+ KWGBEREG_WR(regs->dfsmt[table_index], 0);
+ /* Clear DA filter other multicast table (Ex_dFOMT) */
+ KWGBEREG_WR(regs->dfomt[table_index], 0);
+ }
+}
+
+/*
+ * port_uc_addr - This function Set the port unicast address table
+ *
+ * This function locates the proper entry in the Unicast table for the
+ * specified MAC nibble and sets its properties according to function
+ * parameters.
+ * This function add/removes MAC addresses from the port unicast address
+ * table.
+ *
+ * @uc_nibble Unicast MAC Address last nibble.
+ * @option 0 = Add, 1 = remove address.
+ *
+ * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
+ */
+static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
+ int option)
+{
+ u32 unicast_reg;
+ u32 tbl_offset;
+ u32 reg_offset;
+
+ /* Locate the Unicast table entry */
+ uc_nibble = (0xf & uc_nibble);
+ /* Register offset from unicast table base */
+ tbl_offset = (uc_nibble / 4);
+ /* Entry offset within the above register */
+ reg_offset = uc_nibble % 4;
+
+ switch (option) {
+ case REJECT_MAC_ADDR:
+ /*
+ * Clear accepts frame bit at specified unicast
+ * DA table entry
+ */
+ unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+ unicast_reg &= (0xFF << (8 * reg_offset));
+ KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+ break;
+ case ACCEPT_MAC_ADDR:
+ /* Set accepts frame bit at unicast DA filter table entry */
+ unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+ unicast_reg &= (0xFF << (8 * reg_offset));
+ unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
+ KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+ break;
+ default:
+ return 0;
+ }
+ return 1;
+}
+
+/*
+ * port_uc_addr_set - This function Set the port Unicast address.
+ */
+static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
+{
+ u32 mac_h;
+ u32 mac_l;
+
+ mac_l = (p_addr[4] << 8) | (p_addr[5]);
+ mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
+ (p_addr[3] << 0);
+
+ KWGBEREG_WR(regs->macal, mac_l);
+ KWGBEREG_WR(regs->macah, mac_h);
+
+ /* Accept frames of this address */
+ port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
+}
+
+/*
+ * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ */
+static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
+{
+ struct kwgbe_rxdesc *p_rx_desc;
+ int i;
+
+ /* initialize the Rx descriptors ring */
+ p_rx_desc = dkwgbe->p_rxdesc;
+ for (i = 0; i < RINGSZ; i++) {
+ p_rx_desc->cmd_sts =
+ KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+ p_rx_desc->buf_size = PKTSIZE_ALIGN;
+ p_rx_desc->byte_cnt = 0;
+ p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
+ if (i == (RINGSZ - 1))
+ p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
+ else {
+ p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
+ ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
+ p_rx_desc = p_rx_desc->nxtdesc_p;
+ }
+ }
+ dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
+}
+
+static int kwgbe_init(struct eth_device *dev)
+{
+ struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+ struct kwgbe_registers *regs = dkwgbe->regs;
+#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
+ && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+ int i;
+#endif
+ /* setup RX rings */
+ kwgbe_init_rx_desc_ring(dkwgbe);
+
+ /* Clear the ethernet port interrupts */
+ KWGBEREG_WR(regs->ic, 0);
+ KWGBEREG_WR(regs->ice, 0);
+ /* Unmask RX buffer and TX end interrupt */
+ KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
+ /* Unmask phy and link status changes interrupts */
+ KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
+
+ set_dram_access(regs);
+ port_init_mac_tables(regs);
+ port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+
+ /* Assign port configuration and command. */
+ KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
+ KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
+ KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
+
+ /* Assign port SDMA configuration */
+ KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
+ KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
+ KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
+ /* Turn off the port/RXUQ bandwidth limitation */
+ KWGBEREG_WR(regs->pmtu, 0);
+
+ /* Set maximum receive buffer to 9700 bytes */
+ KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
+ | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
+
+ /* Enable port initially */
+ KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+
+ /*
+ * Set ethernet MTU for leaky bucket mechanism to 0 - this will
+ * disable the leaky bucket mechanism .
+ */
+ KWGBEREG_WR(regs->pmtu, 0);
+
+ /* Assignment of Rx CRDB of given RXUQ */
+ KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
+ /* Enable port Rx. */
+ KWGBEREG_WR(regs->rqc, (1 << RXUQ));
+
+#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
+ && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+ /* Wait up to 5s for the link status */
+ for (i = 0; i < 5; i++) {
+ u16 phyadr;
+
+ miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
+ KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
+ /* Return if we get link up */
+ if (miiphy_link(dev->name, phyadr))
+ return 0;
+ udelay(1000000);
+ }
+
+ printf("No link on %s\n", dev->name);
+ return -1;
+#endif
+ return 0;
+}
+
+static int kwgbe_halt(struct eth_device *dev)
+{
+ struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+ struct kwgbe_registers *regs = dkwgbe->regs;
+
+ /* Disable all gigE address decoder */
+ KWGBEREG_WR(regs->bare, 0x3f);
+
+ stop_queue(®s->tqc);
+ stop_queue(®s->rqc);
+
+ /* Disable port */
+ KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+ /* Set port is not reset */
+ KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
+#ifdef CONFIG_SYS_MII_MODE
+ /* Set MMI interface up */
+ KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
+#endif
+ /* Disable & mask ethernet port interrupts */
+ KWGBEREG_WR(regs->ic, 0);
+ KWGBEREG_WR(regs->ice, 0);
+ KWGBEREG_WR(regs->pim, 0);
+ KWGBEREG_WR(regs->peim, 0);
+
+ return 0;
+}
+
+static int kwgbe_write_hwaddr(struct eth_device *dev)
+{
+ struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+ struct kwgbe_registers *regs = dkwgbe->regs;
+
+ /* Programs net device MAC address after initialization */
+ port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+ return 0;
+}
+
+static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
+ int datasize)
+{
+ struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+ struct kwgbe_registers *regs = dkwgbe->regs;
+ struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
+ void *p = (void *)dataptr;
+ u32 cmd_sts;
+
+ /* Copy buffer if it's misaligned */
+ if ((u32) dataptr & 0x07) {
+ if (datasize > PKTSIZE_ALIGN) {
+ printf("Non-aligned data too large (%d)\n",
+ datasize);
+ return -1;
+ }
+
+ memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
+ p = dkwgbe->p_aligned_txbuf;
+ }
+
+ p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
+ p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
+ p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
+ p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
+ p_txdesc->buf_ptr = (u8 *) p;
+ p_txdesc->byte_cnt = datasize;
+
+ /* Apply send command using zeroth TXUQ */
+ KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
+ KWGBEREG_WR(regs->tqc, (1 << TXUQ));
+
+ /*
+ * wait for packet xmit completion
+ */
+ cmd_sts = readl(&p_txdesc->cmd_sts);
+ while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
+ /* return fail if error is detected */
+ if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
+ (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
+ cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
+ printf("Err..(%s) in xmit packet\n", __FUNCTION__);
+ return -1;
+ }
+ cmd_sts = readl(&p_txdesc->cmd_sts);
+ };
+ return 0;
+}
+
+static int kwgbe_recv(struct eth_device *dev)
+{
+ struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
+ struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
+ u32 cmd_sts;
+ u32 timeout = 0;
+
+ /* wait untill rx packet available or timeout */
+ do {
+ if (timeout < KWGBE_PHY_SMI_TIMEOUT)
+ timeout++;
+ else {
+ debug("%s time out...\n", __FUNCTION__);
+ return -1;
+ }
+ } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
+
+ if (p_rxdesc_curr->byte_cnt != 0) {
+ debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
+ __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
+ (u32) p_rxdesc_curr->buf_ptr,
+ (u32) p_rxdesc_curr->cmd_sts);
+ }
+
+ /*
+ * In case received a packet without first/last bits on
+ * OR the error summary bit is on,
+ * the packets needs to be dropeed.
+ */
+ cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
+
+ if ((cmd_sts &
+ (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
+ != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
+
+ printf("Err..(%s) Dropping packet spread on"
+ " multiple descriptors\n", __FUNCTION__);
+
+ } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
+
+ printf("Err..(%s) Dropping packet with errors\n",
+ __FUNCTION__);
+
+ } else {
+ /* !!! call higher layer processing */
+ debug("%s: Sending Received packet to"
+ " upper layer (NetReceive)\n", __FUNCTION__);
+
+ /* let the upper layer handle the packet */
+ NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
+ (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
+ }
+ /*
+ * free these descriptors and point next in the ring
+ */
+ p_rxdesc_curr->cmd_sts =
+ KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+ p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
+ p_rxdesc_curr->byte_cnt = 0;
+
+ writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
+
+ return 0;
+}
+
+int kirkwood_egiga_initialize(bd_t * bis)
+{
+ struct kwgbe_device *dkwgbe;
+ struct eth_device *dev;
+ int devnum;
+ char *s;
+ u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
+
+ for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
+ /*skip if port is configured not to use */
+ if (used_ports[devnum] == 0)
+ continue;
+
+ if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
+ goto error1;
+
+ memset(dkwgbe, 0, sizeof(struct kwgbe_device));
+
+ if (!(dkwgbe->p_rxdesc =
+ (struct kwgbe_rxdesc *)memalign(PKTALIGN,
+ KW_RXQ_DESC_ALIGNED_SIZE
+ * RINGSZ + 1)))
+ goto error2;
+
+ if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
+ * PKTSIZE_ALIGN + 1)))
+ goto error3;
+
+ if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
+ goto error4;
+
+ if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
+ memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
+ free(dkwgbe->p_aligned_txbuf);
+ error4:
+ free(dkwgbe->p_rxbuf);
+ error3:
+ free(dkwgbe->p_rxdesc);
+ error2:
+ free(dkwgbe);
+ error1:
+ printf("Err.. %s Failed to allocate memory\n",
+ __FUNCTION__);
+ return -1;
+ }
+
+ dev = &dkwgbe->dev;
+
+ /* must be less than NAMESIZE (16) */
+ sprintf(dev->name, "egiga%d", devnum);
+
+ /* Extract the MAC address from the environment */
+ switch (devnum) {
+ case 0:
+ dkwgbe->regs = (void *)KW_EGIGA0_BASE;
+ s = "ethaddr";
+ break;
+ case 1:
+ dkwgbe->regs = (void *)KW_EGIGA1_BASE;
+ s = "eth1addr";
+ break;
+ default: /* this should never happen */
+ printf("Err..(%s) Invalid device number %d\n",
+ __FUNCTION__, devnum);
+ return -1;
+ }
+
+ while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
+ /* Generate Random Private MAC addr if not set */
+ dev->enetaddr[0] = 0x02;
+ dev->enetaddr[1] = 0x50;
+ dev->enetaddr[2] = 0x43;
+ dev->enetaddr[3] = get_random_hex();
+ dev->enetaddr[4] = get_random_hex();
+ dev->enetaddr[5] = get_random_hex();
+ eth_setenv_enetaddr(s, dev->enetaddr);
+ }
+
+ dev->init = (void *)kwgbe_init;
+ dev->halt = (void *)kwgbe_halt;
+ dev->send = (void *)kwgbe_send;
+ dev->recv = (void *)kwgbe_recv;
+ dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
+
+ eth_register(dev);
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+ miiphy_register(dev->name, smi_reg_read, smi_reg_write);
+ /* Set phy address of the port */
+ miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
+ KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
+#endif
+ }
+ return 0;
+}
diff --git a/drivers/net/egiga.h b/drivers/net/egiga.h
new file mode 100644
index 0000000..30c773c
--- /dev/null
+++ b/drivers/net/egiga.h
@@ -0,0 +1,505 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * based on - Driver for MV64360X ethernet ports
+ * Copyright (C) 2002 rabeeh at galileo.co.il
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EGIGA_H__
+#define __EGIGA_H__
+
+#define MAX_KWGBE_DEVS 2 /*controller has two ports */
+
+/* PHY_BASE_ADR is board specific and can be configured */
+#if defined (CONFIG_PHY_BASE_ADR)
+#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
+#else
+#define PHY_BASE_ADR 0x08 /* default phy base addr */
+#endif
+
+/* Constants */
+#define INT_CAUSE_UNMASK_ALL 0x0007ffff
+#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
+#define MRU_MASK 0xfff1ffff
+#define PHYADR_MASK 0x0000001f
+#define PHYREG_MASK 0x0000001f
+#define QTKNBKT_DEF_VAL 0x3fffffff
+#define QMTBS_DEF_VAL 0x000003ff
+#define QTKNRT_DEF_VAL 0x0000fcff
+#define RXUQ 0 /* Used Rx queue */
+#define TXUQ 0 /* Used Rx queue */
+
+#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
+#define KWGBEREG_WR(adr, val) writel(val, &adr)
+#define KWGBEREG_RD(adr) readl(&adr)
+#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
+#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
+
+/* Default port configuration value */
+#define PRT_CFG_VAL ( \
+ KWGBE_UCAST_MOD_NRML | \
+ KWGBE_DFLT_RXQ(RXUQ) | \
+ KWGBE_DFLT_RX_ARPQ(RXUQ) | \
+ KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
+ KWGBE_RX_BC_IF_IP | \
+ KWGBE_RX_BC_IF_ARP | \
+ KWGBE_CPTR_TCP_FRMS_DIS | \
+ KWGBE_CPTR_UDP_FRMS_DIS | \
+ KWGBE_DFLT_RX_TCPQ(RXUQ) | \
+ KWGBE_DFLT_RX_UDPQ(RXUQ) | \
+ KWGBE_DFLT_RX_BPDUQ(RXUQ))
+
+/* Default port extend configuration value */
+#define PORT_CFG_EXTEND_VALUE \
+ KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
+ KWGBE_PARTITION_DIS | \
+ KWGBE_TX_CRC_GENERATION_EN
+
+#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
+
+/* Default sdma control value */
+#define PORT_SDMA_CFG_VALUE ( \
+ KWGBE_RX_BURST_SIZE_16_64BIT | \
+ KWGBE_BLM_RX_NO_SWAP | \
+ KWGBE_BLM_TX_NO_SWAP | \
+ GT_KWGBE_IPG_INT_RX(RXUQ) | \
+ KWGBE_TX_BURST_SIZE_16_64BIT)
+
+/* Default port serial control value */
+#define PORT_SERIAL_CONTROL_VALUE ( \
+ KWGBE_FORCE_LINK_PASS | \
+ KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
+ KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
+ KWGBE_ADV_NO_FLOW_CTRL | \
+ KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ KWGBE_FORCE_BP_MODE_NO_JAM | \
+ (1 << 9) /* Reserved bit has to be 1 */ | \
+ KWGBE_DO_NOT_FORCE_LINK_FAIL | \
+ KWGBE_EN_AUTO_NEG_SPEED_GMII | \
+ KWGBE_DTE_ADV_0 | \
+ KWGBE_MIIPHY_MAC_MODE | \
+ KWGBE_AUTO_NEG_NO_CHANGE | \
+ KWGBE_MAX_RX_PACKET_1552BYTE | \
+ KWGBE_CLR_EXT_LOOPBACK | \
+ KWGBE_SET_FULL_DUPLEX_MODE | \
+ KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
+
+/* Tx WRR confoguration macros */
+#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
+#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
+#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
+/* MAC accepet/reject macros */
+#define ACCEPT_MAC_ADDR 0
+#define REJECT_MAC_ADDR 1
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define KW_RXQ_DESC_ALIGNED_SIZE \
+ (((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
+/* Buffer offset from buffer pointer */
+#define RX_BUF_OFFSET 0x2
+
+/* Port serial status reg (PSR) */
+#define KWGBE_INTERFACE_GMII_MII 0
+#define KWGBE_INTERFACE_PCM 1
+#define KWGBE_LINK_IS_DOWN 0
+#define KWGBE_LINK_IS_UP (1 << 1)
+#define KWGBE_PORT_AT_HALF_DUPLEX 0
+#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2)
+#define KWGBE_RX_FLOW_CTRL_DISD 0
+#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
+#define KWGBE_GMII_SPEED_100_10 0
+#define KWGBE_GMII_SPEED_1000 (1 << 4)
+#define KWGBE_MII_SPEED_10 0
+#define KWGBE_MII_SPEED_100 (1 << 5)
+#define KWGBE_NO_TX 0
+#define KWGBE_TX_IN_PROGRESS (1 << 7)
+#define KWGBE_BYPASS_NO_ACTIVE 0
+#define KWGBE_BYPASS_ACTIVE (1 << 8)
+#define KWGBE_PORT_NOT_AT_PARTN_STT 0
+#define KWGBE_PORT_AT_PARTN_STT (1 << 9)
+#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0
+#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10)
+
+/* These macros describes the Port configuration reg (Px_cR) bits */
+#define KWGBE_UCAST_MOD_NRML 0
+#define KWGBE_UNICAST_PROMISCUOUS_MODE 1
+#define KWGBE_DFLT_RXQ(_x) (_x << 1)
+#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4)
+#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0
+#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
+#define KWGBE_RX_BC_IF_IP 0
+#define KWGBE_REJECT_BC_IF_IP (1 << 8)
+#define KWGBE_RX_BC_IF_ARP 0
+#define KWGBE_REJECT_BC_IF_ARP (1 << 9)
+#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
+#define KWGBE_CPTR_TCP_FRMS_DIS 0
+#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14)
+#define KWGBE_CPTR_UDP_FRMS_DIS 0
+#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15)
+#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16)
+#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19)
+#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
+#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
+
+/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+#define KWGBE_CLASSIFY_EN 1
+#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
+#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
+#define KWGBE_PARTITION_DIS 0
+#define KWGBE_PARTITION_EN (1 << 2)
+#define KWGBE_TX_CRC_GENERATION_EN 0
+#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3)
+
+/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+#define KWGBE_RIFB 1
+#define KWGBE_RX_BURST_SIZE_1_64BIT 0
+#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
+#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
+#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
+#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
+#define KWGBE_BLM_RX_NO_SWAP (1 << 4)
+#define KWGBE_BLM_RX_BYTE_SWAP 0
+#define KWGBE_BLM_TX_NO_SWAP (1 << 5)
+#define KWGBE_BLM_TX_BYTE_SWAP 0
+#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
+#define KWGBE_DESCRIPTORS_NO_SWAP 0
+#define KWGBE_TX_BURST_SIZE_1_64BIT 0
+#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
+#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
+#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
+#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
+
+/* These macros describes the Port serial control reg (PSCR) bits */
+#define KWGBE_SERIAL_PORT_DIS 0
+#define KWGBE_SERIAL_PORT_EN 1
+#define KWGBE_FORCE_LINK_PASS (1 << 1)
+#define KWGBE_DO_NOT_FORCE_LINK_PASS 0
+#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0
+#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
+#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
+#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
+#define KWGBE_ADV_NO_FLOW_CTRL 0
+#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
+#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
+#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
+#define KWGBE_FORCE_BP_MODE_NO_JAM 0
+#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
+#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
+#define KWGBE_FORCE_LINK_FAIL 0
+#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
+#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
+#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0
+#define KWGBE_DTE_ADV_0 0
+#define KWGBE_DTE_ADV_1 (1 << 14)
+#define KWGBE_MIIPHY_MAC_MODE 0
+#define KWGBE_MIIPHY_PHY_MODE (1 << 15)
+#define KWGBE_AUTO_NEG_NO_CHANGE 0
+#define KWGBE_RESTART_AUTO_NEG (1 << 16)
+#define KWGBE_MAX_RX_PACKET_1518BYTE 0
+#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
+#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
+#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
+#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
+#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
+#define KWGBE_SET_EXT_LOOPBACK (1 << 20)
+#define KWGBE_CLR_EXT_LOOPBACK 0
+#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21)
+#define KWGBE_SET_HALF_DUPLEX_MODE 0
+#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
+#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+#define KWGBE_SET_GMII_SPEED_TO_10_100 0
+#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
+#define KWGBE_SET_MII_SPEED_TO_10 0
+#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24)
+
+/* SMI register fields */
+#define KWGBE_PHY_SMI_TIMEOUT 10000
+#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */
+#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS)
+#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
+#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
+#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
+#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
+#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
+#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS)
+#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS)
+#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS)
+#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
+#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
+
+/* SDMA command status fields macros */
+/* Tx & Rx descriptors status */
+#define KWGBE_ERROR_SUMMARY 1
+/* Tx & Rx descriptors command */
+#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31)
+/* Tx descriptors status */
+#define KWGBE_LC_ERROR 0
+#define KWGBE_UR_ERROR (1 << 1)
+#define KWGBE_RL_ERROR (1 << 2)
+#define KWGBE_LLC_SNAP_FORMAT (1 << 9)
+#define KWGBE_TX_LAST_FRAME (1 << 20)
+
+/* Rx descriptors status */
+#define KWGBE_CRC_ERROR 0
+#define KWGBE_OVERRUN_ERROR (1 << 1)
+#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
+#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
+#define KWGBE_VLAN_TAGGED (1 << 19)
+#define KWGBE_BPDU_FRAME (1 << 20)
+#define KWGBE_TCP_FRAME_OVER_IP_V_4 0
+#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
+#define KWGBE_OTHER_FRAME_TYPE (1 << 22)
+#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23)
+#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24)
+#define KWGBE_FRAME_HEADER_OK (1 << 25)
+#define KWGBE_RX_LAST_DESC (1 << 26)
+#define KWGBE_RX_FIRST_DESC (1 << 27)
+#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
+#define KWGBE_RX_EN_INTERRUPT (1 << 29)
+#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30)
+
+/* Rx descriptors byte count */
+#define KWGBE_FRAME_FRAGMENTED (1 << 2)
+
+/* Tx descriptors command */
+#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
+#define KWGBE_FRAME_SET_TO_VLAN (1 << 15)
+#define KWGBE_TCP_FRAME 0
+#define KWGBE_UDP_FRAME (1 << 16)
+#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
+#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
+#define KWGBE_ZERO_PADDING (1 << 19)
+#define KWGBE_TX_LAST_DESC (1 << 20)
+#define KWGBE_TX_FIRST_DESC (1 << 21)
+#define KWGBE_GEN_CRC (1 << 22)
+#define KWGBE_TX_EN_INTERRUPT (1 << 23)
+#define KWGBE_AUTO_MODE (1 << 30)
+
+/* Address decode parameters */
+/* Ethernet Base Address Register bits */
+#define EBAR_TARGET_DRAM 0x00000000
+#define EBAR_TARGET_DEVICE 0x00000001
+#define EBAR_TARGET_CBS 0x00000002
+#define EBAR_TARGET_PCI0 0x00000003
+#define EBAR_TARGET_PCI1 0x00000004
+#define EBAR_TARGET_CUNIT 0x00000005
+#define EBAR_TARGET_AUNIT 0x00000006
+#define EBAR_TARGET_GUNIT 0x00000007
+
+/* Window attrib */
+#define EBAR_DRAM_CS0 0x00000E00
+#define EBAR_DRAM_CS1 0x00000D00
+#define EBAR_DRAM_CS2 0x00000B00
+#define EBAR_DRAM_CS3 0x00000700
+
+/* DRAM Target interface */
+#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
+#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
+#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
+
+/* Device Bus Target interface */
+#define EBAR_DEVICE_DEVCS0 0x00001E00
+#define EBAR_DEVICE_DEVCS1 0x00001D00
+#define EBAR_DEVICE_DEVCS2 0x00001B00
+#define EBAR_DEVICE_DEVCS3 0x00001700
+#define EBAR_DEVICE_BOOTCS3 0x00000F00
+
+/* PCI Target interface */
+#define EBAR_PCI_BYTE_SWAP 0x00000000
+#define EBAR_PCI_NO_SWAP 0x00000100
+#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
+#define EBAR_PCI_WORD_SWAP 0x00000300
+#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
+#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
+#define EBAR_PCI_IO_SPACE 0x00000000
+#define EBAR_PCI_MEMORY_SPACE 0x00000800
+#define EBAR_PCI_REQ64_FORCE 0x00000000
+#define EBAR_PCI_REQ64_SIZE 0x00001000
+
+/* Window access control */
+#define EWIN_ACCESS_NOT_ALLOWED 0
+#define EWIN_ACCESS_READ_ONLY 1
+#define EWIN_ACCESS_FULL ((1 << 1) | 1)
+
+/* structures represents Controller registers */
+struct kwgbe_barsz {
+ u32 bar;
+ u32 size;
+};
+
+struct kwgbe_rxcdp {
+ struct kwgbe_rxdesc *rxcdp;
+ u32 rxcdp_pad[3];
+};
+
+struct kwgbe_tqx {
+ u32 qxttbc;
+ u32 tqxtbc;
+ u32 tqxac;
+ u32 tqxpad;
+};
+
+struct kwgbe_registers {
+ u32 phyadr;
+ u32 smi;
+ u32 euda;
+ u32 eudid;
+ u8 pad1[0x080 - 0x00c - 4];
+ u32 euic;
+ u32 euim;
+ u8 pad2[0x094 - 0x084 - 4];
+ u32 euea;
+ u32 euiae;
+ u8 pad3[0x0b0 - 0x098 - 4];
+ u32 euc;
+ u8 pad3a[0x200 - 0x0b0 - 4];
+ struct kwgbe_barsz barsz[6];
+ u8 pad4[0x280 - 0x22c - 4];
+ u32 ha_remap[4];
+ u32 bare;
+ u32 epap;
+ u8 pad5[0x400 - 0x294 - 4];
+ u32 pxc;
+ u32 pxcx;
+ u32 mii_ser_params;
+ u8 pad6[0x410 - 0x408 - 4];
+ u32 evlane;
+ u32 macal;
+ u32 macah;
+ u32 sdc;
+ u32 dscp[7];
+ u32 psc0;
+ u32 vpt2p;
+ u32 ps0;
+ u32 tqc;
+ u32 psc1;
+ u32 ps1;
+ u32 mrvl_header;
+ u8 pad7[0x460 - 0x454 - 4];
+ u32 ic;
+ u32 ice;
+ u32 pim;
+ u32 peim;
+ u8 pad8[0x474 - 0x46c - 4];
+ u32 pxtfut;
+ u32 pad9;
+ u32 pxmfs;
+ u32 pad10;
+ u32 pxdfc;
+ u32 pxofc;
+ u8 pad11[0x494 - 0x488 - 4];
+ u32 peuiae;
+ u8 pad12[0x4bc - 0x494 - 4];
+ u32 eth_type_prio;
+ u8 pad13[0x4dc - 0x4bc - 4];
+ u32 tqfpc;
+ u32 pttbrc;
+ u32 tqc1;
+ u32 pmtu;
+ u32 pmtbs;
+ u8 pad14[0x60c - 0x4ec - 4];
+ struct kwgbe_rxcdp rxcdp[7];
+ struct kwgbe_rxdesc *rxcdp7;
+ u32 rqc;
+ struct kwgbe_txdesc *tcsdp;
+ u8 pad15[0x6c0 - 0x684 - 4];
+ struct kwgbe_txdesc *tcqdp[8];
+ u8 pad16[0x700 - 0x6dc - 4];
+ struct kwgbe_tqx tqx[8];
+ u32 pttbc;
+ u8 pad17[0x7a8 - 0x780 - 4];
+ u32 tqxipg0;
+ u32 pad18[3];
+ u32 tqxipg1;
+ u8 pad19[0x7c0 - 0x7b8 - 4];
+ u32 hitkninlopkt;
+ u32 hitkninasyncpkt;
+ u32 lotkninasyncpkt;
+ u32 pad20;
+ u32 ts;
+ u8 pad21[0x3000 - 0x27d0 - 4];
+ u32 pad20_1[32]; /* mib counter registes */
+ u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
+ u32 dfsmt[64];
+ u32 dfomt[64];
+ u32 dfut[4];
+ u8 pad23[0xe20c0 - 0x7360c - 4];
+ u32 pmbus_top_arbiter;
+};
+
+/* structures/enums needed by driver */
+enum kwgbe_adrwin {
+ KWGBE_WIN0,
+ KWGBE_WIN1,
+ KWGBE_WIN2,
+ KWGBE_WIN3,
+ KWGBE_WIN4,
+ KWGBE_WIN5
+};
+
+enum kwgbe_target {
+ KWGBE_TARGET_DRAM,
+ KWGBE_TARGET_DEV,
+ KWGBE_TARGET_CBS,
+ KWGBE_TARGET_PCI0,
+ KWGBE_TARGET_PCI1
+};
+
+struct kwgbe_winparam {
+ enum kwgbe_adrwin win; /* Window number */
+ enum kwgbe_target target; /* System targets */
+ u16 attrib; /* BAR attrib. See above macros */
+ u32 base_addr; /* Window base address in u32 form */
+ u32 high_addr; /* Window high address in u32 form */
+ u32 size; /* Size in MBytes. Must be % 64Kbyte. */
+ int enable; /* Enable/disable access to the window. */
+ u16 access_ctrl; /*Access ctrl register. see above macros */
+};
+
+struct kwgbe_rxdesc {
+ u32 cmd_sts; /* Descriptor command status */
+ u16 buf_size; /* Buffer size */
+ u16 byte_cnt; /* Descriptor buffer byte count */
+ u8 *buf_ptr; /* Descriptor buffer pointer */
+ struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
+};
+
+struct kwgbe_txdesc {
+ u32 cmd_sts; /* Descriptor command status */
+ u16 l4i_chk; /* CPU provided TCP Checksum */
+ u16 byte_cnt; /* Descriptor buffer byte count */
+ u8 *buf_ptr; /* Descriptor buffer ptr */
+ struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
+};
+
+/* port device data struct */
+struct kwgbe_device {
+ struct eth_device dev;
+ struct kwgbe_registers *regs;
+ struct kwgbe_txdesc *p_txdesc;
+ struct kwgbe_rxdesc *p_rxdesc;
+ struct kwgbe_rxdesc *p_rxdesc_curr;
+ u8 *p_rxbuf;
+ u8 *p_aligned_txbuf;
+};
+
+#endif /* __EGIGA_H__ */
diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c
deleted file mode 100644
index 932792e..0000000
--- a/drivers/net/kirkwood_egiga.c
+++ /dev/null
@@ -1,719 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * (C) Copyright 2003
- * Ingo Assmus <ingo.assmus@keymile.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh at galileo.co.il
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <net.h>
-#include <malloc.h>
-#include <miiphy.h>
-#include <asm/errno.h>
-#include <asm/types.h>
-#include <asm/byteorder.h>
-#include <asm/arch/kirkwood.h>
-#include "kirkwood_egiga.h"
-
-#define KIRKWOOD_PHY_ADR_REQUEST 0xee
-#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
-
-/*
- * smi_reg_read - miiphy_read callback function.
- *
- * Returns 16bit phy register value, or 0xffff on error
- */
-static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
-{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
- u32 smi_reg;
- u32 timeout;
-
- /* Phyadr read request */
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
- /* */
- *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
- return 0;
- }
- /* check parameters */
- if (phy_adr > PHYADR_MASK) {
- printf("Err..(%s) Invalid PHY address %d\n",
- __FUNCTION__, phy_adr);
- return -EFAULT;
- }
- if (reg_ofs > PHYREG_MASK) {
- printf("Err..(%s) Invalid register offset %d\n",
- __FUNCTION__, reg_ofs);
- return -EFAULT;
- }
-
- timeout = KWGBE_PHY_SMI_TIMEOUT;
- /* wait till the SMI is not busy */
- do {
- /* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
- if (timeout-- == 0) {
- printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
- return -EFAULT;
- }
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
-
- /* fill the phy address and regiser offset and read opcode */
- smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
- | KWGBE_PHY_SMI_OPCODE_READ;
-
- /* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
-
- /*wait till read value is ready */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
-
- do {
- /* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
- if (timeout-- == 0) {
- printf("Err..(%s) SMI read ready timeout\n",
- __FUNCTION__);
- return -EFAULT;
- }
- } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
-
- /* Wait for the data to update in the SMI register */
- for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
-
- *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
-
- debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
- reg_ofs, *data);
-
- return 0;
-}
-
-/*
- * smi_reg_write - imiiphy_write callback function.
- *
- * Returns 0 if write succeed, -EINVAL on bad parameters
- * -ETIME on timeout
- */
-static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
-{
- struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
- u32 smi_reg;
- u32 timeout;
-
- /* Phyadr write request*/
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
- KWGBEREG_WR(regs->phyadr, data);
- return 0;
- }
-
- /* check parameters */
- if (phy_adr > PHYADR_MASK) {
- printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
- return -EINVAL;
- }
- if (reg_ofs > PHYREG_MASK) {
- printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
- return -EINVAL;
- }
-
- /* wait till the SMI is not busy */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
- do {
- /* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
- if (timeout-- == 0) {
- printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
- return -ETIME;
- }
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
-
- /* fill the phy addr and reg offset and write opcode and data */
- smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
- smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
- smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
-
- /* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
-
- return 0;
-}
-
-/* Stop and checks all queues */
-static void stop_queue(u32 * qreg)
-{
- u32 reg_data;
-
- reg_data = readl(qreg);
-
- if (reg_data & 0xFF) {
- /* Issue stop command for active channels only */
- writel((reg_data << 8), qreg);
-
- /* Wait for all queue activity to terminate. */
- do {
- /*
- * Check port cause register that all queues
- * are stopped
- */
- reg_data = readl(qreg);
- }
- while (reg_data & 0xFF);
- }
-}
-
-/*
- * set_access_control - Config address decode parameters for Ethernet unit
- *
- * This function configures the address decode parameters for the Gigabit
- * Ethernet Controller according the given parameters struct.
- *
- * @regs Register struct pointer.
- * @param Address decode parameter struct.
- */
-static void set_access_control(struct kwgbe_registers *regs,
- struct kwgbe_winparam *param)
-{
- u32 access_prot_reg;
-
- /* Set access control register */
- access_prot_reg = KWGBEREG_RD(regs->epap);
- /* clear window permission */
- access_prot_reg &= (~(3 << (param->win * 2)));
- access_prot_reg |= (param->access_ctrl << (param->win * 2));
- KWGBEREG_WR(regs->epap, access_prot_reg);
-
- /* Set window Size reg (SR) */
- KWGBEREG_WR(regs->barsz[param->win].size,
- (((param->size / 0x10000) - 1) << 16));
-
- /* Set window Base address reg (BA) */
- KWGBEREG_WR(regs->barsz[param->win].bar,
- (param->target | param->attrib | param->base_addr));
- /* High address remap reg (HARR) */
- if (param->win < 4)
- KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
-
- /* Base address enable reg (BARER) */
- if (param->enable == 1)
- KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
- else
- KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
-}
-
-static void set_dram_access(struct kwgbe_registers *regs)
-{
- struct kwgbe_winparam win_param;
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- /* Set access parameters for DRAM bank i */
- win_param.win = i; /* Use Ethernet window i */
- /* Window target - DDR */
- win_param.target = KWGBE_TARGET_DRAM;
- /* Enable full access */
- win_param.access_ctrl = EWIN_ACCESS_FULL;
- win_param.high_addr = 0;
- /* Get bank base */
- win_param.base_addr = kw_sdram_bar(i);
- win_param.size = kw_sdram_bs(i); /* Get bank size */
- if (win_param.size == 0)
- win_param.enable = 0;
- else
- win_param.enable = 1; /* Enable the access */
-
- /* Enable DRAM bank */
- switch (i) {
- case 0:
- win_param.attrib = EBAR_DRAM_CS0;
- break;
- case 1:
- win_param.attrib = EBAR_DRAM_CS1;
- break;
- case 2:
- win_param.attrib = EBAR_DRAM_CS2;
- break;
- case 3:
- win_param.attrib = EBAR_DRAM_CS3;
- break;
- default:
- /* invalide bank, disable access */
- win_param.enable = 0;
- win_param.attrib = 0;
- break;
- }
- /* Set the access control for address window(EPAPR) RD/WR */
- set_access_control(regs, &win_param);
- }
-}
-
-/*
- * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
- *
- * Go through all the DA filter tables (Unicast, Special Multicast & Other
- * Multicast) and set each entry to 0.
- */
-static void port_init_mac_tables(struct kwgbe_registers *regs)
-{
- int table_index;
-
- /* Clear DA filter unicast table (Ex_dFUT) */
- for (table_index = 0; table_index < 4; ++table_index)
- KWGBEREG_WR(regs->dfut[table_index], 0);
-
- for (table_index = 0; table_index < 64; ++table_index) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- KWGBEREG_WR(regs->dfsmt[table_index], 0);
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- KWGBEREG_WR(regs->dfomt[table_index], 0);
- }
-}
-
-/*
- * port_uc_addr - This function Set the port unicast address table
- *
- * This function locates the proper entry in the Unicast table for the
- * specified MAC nibble and sets its properties according to function
- * parameters.
- * This function add/removes MAC addresses from the port unicast address
- * table.
- *
- * @uc_nibble Unicast MAC Address last nibble.
- * @option 0 = Add, 1 = remove address.
- *
- * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
- */
-static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
- int option)
-{
- u32 unicast_reg;
- u32 tbl_offset;
- u32 reg_offset;
-
- /* Locate the Unicast table entry */
- uc_nibble = (0xf & uc_nibble);
- /* Register offset from unicast table base */
- tbl_offset = (uc_nibble / 4);
- /* Entry offset within the above register */
- reg_offset = uc_nibble % 4;
-
- switch (option) {
- case REJECT_MAC_ADDR:
- /*
- * Clear accepts frame bit at specified unicast
- * DA table entry
- */
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
- unicast_reg &= (0xFF << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
- break;
- case ACCEPT_MAC_ADDR:
- /* Set accepts frame bit at unicast DA filter table entry */
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
- unicast_reg &= (0xFF << (8 * reg_offset));
- unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
- break;
- default:
- return 0;
- }
- return 1;
-}
-
-/*
- * port_uc_addr_set - This function Set the port Unicast address.
- */
-static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
-{
- u32 mac_h;
- u32 mac_l;
-
- mac_l = (p_addr[4] << 8) | (p_addr[5]);
- mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
- (p_addr[3] << 0);
-
- KWGBEREG_WR(regs->macal, mac_l);
- KWGBEREG_WR(regs->macah, mac_h);
-
- /* Accept frames of this address */
- port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
-}
-
-/*
- * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
- */
-static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
-{
- struct kwgbe_rxdesc *p_rx_desc;
- int i;
-
- /* initialize the Rx descriptors ring */
- p_rx_desc = dkwgbe->p_rxdesc;
- for (i = 0; i < RINGSZ; i++) {
- p_rx_desc->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
- p_rx_desc->buf_size = PKTSIZE_ALIGN;
- p_rx_desc->byte_cnt = 0;
- p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
- if (i == (RINGSZ - 1))
- p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
- else {
- p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
- ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
- p_rx_desc = p_rx_desc->nxtdesc_p;
- }
- }
- dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
-}
-
-static int kwgbe_init(struct eth_device *dev)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
- && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
- int i;
-#endif
- /* setup RX rings */
- kwgbe_init_rx_desc_ring(dkwgbe);
-
- /* Clear the ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
- /* Unmask RX buffer and TX end interrupt */
- KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
- /* Unmask phy and link status changes interrupts */
- KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
-
- set_dram_access(regs);
- port_init_mac_tables(regs);
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
-
- /* Assign port configuration and command. */
- KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
- KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
- KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
-
- /* Assign port SDMA configuration */
- KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
- KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
- KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
- /* Turn off the port/RXUQ bandwidth limitation */
- KWGBEREG_WR(regs->pmtu, 0);
-
- /* Set maximum receive buffer to 9700 bytes */
- KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
- | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
-
- /* Enable port initially */
- KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
-
- /*
- * Set ethernet MTU for leaky bucket mechanism to 0 - this will
- * disable the leaky bucket mechanism .
- */
- KWGBEREG_WR(regs->pmtu, 0);
-
- /* Assignment of Rx CRDB of given RXUQ */
- KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
- /* Enable port Rx. */
- KWGBEREG_WR(regs->rqc, (1 << RXUQ));
-
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
- && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
- /* Wait up to 5s for the link status */
- for (i = 0; i < 5; i++) {
- u16 phyadr;
-
- miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
- /* Return if we get link up */
- if (miiphy_link(dev->name, phyadr))
- return 0;
- udelay(1000000);
- }
-
- printf("No link on %s\n", dev->name);
- return -1;
-#endif
- return 0;
-}
-
-static int kwgbe_halt(struct eth_device *dev)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
-
- /* Disable all gigE address decoder */
- KWGBEREG_WR(regs->bare, 0x3f);
-
- stop_queue(®s->tqc);
- stop_queue(®s->rqc);
-
- /* Disable port */
- KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
- /* Set port is not reset */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
-#ifdef CONFIG_SYS_MII_MODE
- /* Set MMI interface up */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
-#endif
- /* Disable & mask ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
- KWGBEREG_WR(regs->pim, 0);
- KWGBEREG_WR(regs->peim, 0);
-
- return 0;
-}
-
-static int kwgbe_write_hwaddr(struct eth_device *dev)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
-
- /* Programs net device MAC address after initialization */
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
- return 0;
-}
-
-static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
- int datasize)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
- struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
- void *p = (void *)dataptr;
- u32 cmd_sts;
-
- /* Copy buffer if it's misaligned */
- if ((u32) dataptr & 0x07) {
- if (datasize > PKTSIZE_ALIGN) {
- printf("Non-aligned data too large (%d)\n",
- datasize);
- return -1;
- }
-
- memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
- p = dkwgbe->p_aligned_txbuf;
- }
-
- p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
- p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
- p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
- p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
- p_txdesc->buf_ptr = (u8 *) p;
- p_txdesc->byte_cnt = datasize;
-
- /* Apply send command using zeroth TXUQ */
- KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
- KWGBEREG_WR(regs->tqc, (1 << TXUQ));
-
- /*
- * wait for packet xmit completion
- */
- cmd_sts = readl(&p_txdesc->cmd_sts);
- while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
- /* return fail if error is detected */
- if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
- (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
- cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
- printf("Err..(%s) in xmit packet\n", __FUNCTION__);
- return -1;
- }
- cmd_sts = readl(&p_txdesc->cmd_sts);
- };
- return 0;
-}
-
-static int kwgbe_recv(struct eth_device *dev)
-{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
- u32 cmd_sts;
- u32 timeout = 0;
-
- /* wait untill rx packet available or timeout */
- do {
- if (timeout < KWGBE_PHY_SMI_TIMEOUT)
- timeout++;
- else {
- debug("%s time out...\n", __FUNCTION__);
- return -1;
- }
- } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
-
- if (p_rxdesc_curr->byte_cnt != 0) {
- debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
- __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
- (u32) p_rxdesc_curr->buf_ptr,
- (u32) p_rxdesc_curr->cmd_sts);
- }
-
- /*
- * In case received a packet without first/last bits on
- * OR the error summary bit is on,
- * the packets needs to be dropeed.
- */
- cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
-
- if ((cmd_sts &
- (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
- != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
-
- printf("Err..(%s) Dropping packet spread on"
- " multiple descriptors\n", __FUNCTION__);
-
- } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
-
- printf("Err..(%s) Dropping packet with errors\n",
- __FUNCTION__);
-
- } else {
- /* !!! call higher layer processing */
- debug("%s: Sending Received packet to"
- " upper layer (NetReceive)\n", __FUNCTION__);
-
- /* let the upper layer handle the packet */
- NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
- (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
- }
- /*
- * free these descriptors and point next in the ring
- */
- p_rxdesc_curr->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
- p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
- p_rxdesc_curr->byte_cnt = 0;
-
- writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
-
- return 0;
-}
-
-int kirkwood_egiga_initialize(bd_t * bis)
-{
- struct kwgbe_device *dkwgbe;
- struct eth_device *dev;
- int devnum;
- char *s;
- u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
-
- for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
- /*skip if port is configured not to use */
- if (used_ports[devnum] == 0)
- continue;
-
- if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
- goto error1;
-
- memset(dkwgbe, 0, sizeof(struct kwgbe_device));
-
- if (!(dkwgbe->p_rxdesc =
- (struct kwgbe_rxdesc *)memalign(PKTALIGN,
- KW_RXQ_DESC_ALIGNED_SIZE
- * RINGSZ + 1)))
- goto error2;
-
- if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
- * PKTSIZE_ALIGN + 1)))
- goto error3;
-
- if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
- goto error4;
-
- if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
- memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
- free(dkwgbe->p_aligned_txbuf);
- error4:
- free(dkwgbe->p_rxbuf);
- error3:
- free(dkwgbe->p_rxdesc);
- error2:
- free(dkwgbe);
- error1:
- printf("Err.. %s Failed to allocate memory\n",
- __FUNCTION__);
- return -1;
- }
-
- dev = &dkwgbe->dev;
-
- /* must be less than NAMESIZE (16) */
- sprintf(dev->name, "egiga%d", devnum);
-
- /* Extract the MAC address from the environment */
- switch (devnum) {
- case 0:
- dkwgbe->regs = (void *)KW_EGIGA0_BASE;
- s = "ethaddr";
- break;
- case 1:
- dkwgbe->regs = (void *)KW_EGIGA1_BASE;
- s = "eth1addr";
- break;
- default: /* this should never happen */
- printf("Err..(%s) Invalid device number %d\n",
- __FUNCTION__, devnum);
- return -1;
- }
-
- while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
- /* Generate Random Private MAC addr if not set */
- dev->enetaddr[0] = 0x02;
- dev->enetaddr[1] = 0x50;
- dev->enetaddr[2] = 0x43;
- dev->enetaddr[3] = get_random_hex();
- dev->enetaddr[4] = get_random_hex();
- dev->enetaddr[5] = get_random_hex();
- eth_setenv_enetaddr(s, dev->enetaddr);
- }
-
- dev->init = (void *)kwgbe_init;
- dev->halt = (void *)kwgbe_halt;
- dev->send = (void *)kwgbe_send;
- dev->recv = (void *)kwgbe_recv;
- dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
-
- eth_register(dev);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
- miiphy_register(dev->name, smi_reg_read, smi_reg_write);
- /* Set phy address of the port */
- miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
-#endif
- }
- return 0;
-}
diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/kirkwood_egiga.h
deleted file mode 100644
index 30c773c..0000000
--- a/drivers/net/kirkwood_egiga.h
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * based on - Driver for MV64360X ethernet ports
- * Copyright (C) 2002 rabeeh at galileo.co.il
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __EGIGA_H__
-#define __EGIGA_H__
-
-#define MAX_KWGBE_DEVS 2 /*controller has two ports */
-
-/* PHY_BASE_ADR is board specific and can be configured */
-#if defined (CONFIG_PHY_BASE_ADR)
-#define PHY_BASE_ADR CONFIG_PHY_BASE_ADR
-#else
-#define PHY_BASE_ADR 0x08 /* default phy base addr */
-#endif
-
-/* Constants */
-#define INT_CAUSE_UNMASK_ALL 0x0007ffff
-#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
-#define MRU_MASK 0xfff1ffff
-#define PHYADR_MASK 0x0000001f
-#define PHYREG_MASK 0x0000001f
-#define QTKNBKT_DEF_VAL 0x3fffffff
-#define QMTBS_DEF_VAL 0x000003ff
-#define QTKNRT_DEF_VAL 0x0000fcff
-#define RXUQ 0 /* Used Rx queue */
-#define TXUQ 0 /* Used Rx queue */
-
-#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
-#define KWGBEREG_WR(adr, val) writel(val, &adr)
-#define KWGBEREG_RD(adr) readl(&adr)
-#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
-#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
-
-/* Default port configuration value */
-#define PRT_CFG_VAL ( \
- KWGBE_UCAST_MOD_NRML | \
- KWGBE_DFLT_RXQ(RXUQ) | \
- KWGBE_DFLT_RX_ARPQ(RXUQ) | \
- KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
- KWGBE_RX_BC_IF_IP | \
- KWGBE_RX_BC_IF_ARP | \
- KWGBE_CPTR_TCP_FRMS_DIS | \
- KWGBE_CPTR_UDP_FRMS_DIS | \
- KWGBE_DFLT_RX_TCPQ(RXUQ) | \
- KWGBE_DFLT_RX_UDPQ(RXUQ) | \
- KWGBE_DFLT_RX_BPDUQ(RXUQ))
-
-/* Default port extend configuration value */
-#define PORT_CFG_EXTEND_VALUE \
- KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
- KWGBE_PARTITION_DIS | \
- KWGBE_TX_CRC_GENERATION_EN
-
-#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
-
-/* Default sdma control value */
-#define PORT_SDMA_CFG_VALUE ( \
- KWGBE_RX_BURST_SIZE_16_64BIT | \
- KWGBE_BLM_RX_NO_SWAP | \
- KWGBE_BLM_TX_NO_SWAP | \
- GT_KWGBE_IPG_INT_RX(RXUQ) | \
- KWGBE_TX_BURST_SIZE_16_64BIT)
-
-/* Default port serial control value */
-#define PORT_SERIAL_CONTROL_VALUE ( \
- KWGBE_FORCE_LINK_PASS | \
- KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
- KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
- KWGBE_ADV_NO_FLOW_CTRL | \
- KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- KWGBE_FORCE_BP_MODE_NO_JAM | \
- (1 << 9) /* Reserved bit has to be 1 */ | \
- KWGBE_DO_NOT_FORCE_LINK_FAIL | \
- KWGBE_EN_AUTO_NEG_SPEED_GMII | \
- KWGBE_DTE_ADV_0 | \
- KWGBE_MIIPHY_MAC_MODE | \
- KWGBE_AUTO_NEG_NO_CHANGE | \
- KWGBE_MAX_RX_PACKET_1552BYTE | \
- KWGBE_CLR_EXT_LOOPBACK | \
- KWGBE_SET_FULL_DUPLEX_MODE | \
- KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
-
-/* Tx WRR confoguration macros */
-#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
-#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
-#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
-/* MAC accepet/reject macros */
-#define ACCEPT_MAC_ADDR 0
-#define REJECT_MAC_ADDR 1
-/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define KW_RXQ_DESC_ALIGNED_SIZE \
- (((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
-/* Buffer offset from buffer pointer */
-#define RX_BUF_OFFSET 0x2
-
-/* Port serial status reg (PSR) */
-#define KWGBE_INTERFACE_GMII_MII 0
-#define KWGBE_INTERFACE_PCM 1
-#define KWGBE_LINK_IS_DOWN 0
-#define KWGBE_LINK_IS_UP (1 << 1)
-#define KWGBE_PORT_AT_HALF_DUPLEX 0
-#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2)
-#define KWGBE_RX_FLOW_CTRL_DISD 0
-#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
-#define KWGBE_GMII_SPEED_100_10 0
-#define KWGBE_GMII_SPEED_1000 (1 << 4)
-#define KWGBE_MII_SPEED_10 0
-#define KWGBE_MII_SPEED_100 (1 << 5)
-#define KWGBE_NO_TX 0
-#define KWGBE_TX_IN_PROGRESS (1 << 7)
-#define KWGBE_BYPASS_NO_ACTIVE 0
-#define KWGBE_BYPASS_ACTIVE (1 << 8)
-#define KWGBE_PORT_NOT_AT_PARTN_STT 0
-#define KWGBE_PORT_AT_PARTN_STT (1 << 9)
-#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0
-#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10)
-
-/* These macros describes the Port configuration reg (Px_cR) bits */
-#define KWGBE_UCAST_MOD_NRML 0
-#define KWGBE_UNICAST_PROMISCUOUS_MODE 1
-#define KWGBE_DFLT_RXQ(_x) (_x << 1)
-#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4)
-#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0
-#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
-#define KWGBE_RX_BC_IF_IP 0
-#define KWGBE_REJECT_BC_IF_IP (1 << 8)
-#define KWGBE_RX_BC_IF_ARP 0
-#define KWGBE_REJECT_BC_IF_ARP (1 << 9)
-#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
-#define KWGBE_CPTR_TCP_FRMS_DIS 0
-#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14)
-#define KWGBE_CPTR_UDP_FRMS_DIS 0
-#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15)
-#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16)
-#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19)
-#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
-#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
-
-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define KWGBE_CLASSIFY_EN 1
-#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
-#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
-#define KWGBE_PARTITION_DIS 0
-#define KWGBE_PARTITION_EN (1 << 2)
-#define KWGBE_TX_CRC_GENERATION_EN 0
-#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3)
-
-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define KWGBE_RIFB 1
-#define KWGBE_RX_BURST_SIZE_1_64BIT 0
-#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
-#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
-#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
-#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
-#define KWGBE_BLM_RX_NO_SWAP (1 << 4)
-#define KWGBE_BLM_RX_BYTE_SWAP 0
-#define KWGBE_BLM_TX_NO_SWAP (1 << 5)
-#define KWGBE_BLM_TX_BYTE_SWAP 0
-#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
-#define KWGBE_DESCRIPTORS_NO_SWAP 0
-#define KWGBE_TX_BURST_SIZE_1_64BIT 0
-#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
-#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
-#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
-#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
-
-/* These macros describes the Port serial control reg (PSCR) bits */
-#define KWGBE_SERIAL_PORT_DIS 0
-#define KWGBE_SERIAL_PORT_EN 1
-#define KWGBE_FORCE_LINK_PASS (1 << 1)
-#define KWGBE_DO_NOT_FORCE_LINK_PASS 0
-#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0
-#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
-#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
-#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
-#define KWGBE_ADV_NO_FLOW_CTRL 0
-#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
-#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
-#define KWGBE_FORCE_BP_MODE_NO_JAM 0
-#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
-#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
-#define KWGBE_FORCE_LINK_FAIL 0
-#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
-#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
-#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0
-#define KWGBE_DTE_ADV_0 0
-#define KWGBE_DTE_ADV_1 (1 << 14)
-#define KWGBE_MIIPHY_MAC_MODE 0
-#define KWGBE_MIIPHY_PHY_MODE (1 << 15)
-#define KWGBE_AUTO_NEG_NO_CHANGE 0
-#define KWGBE_RESTART_AUTO_NEG (1 << 16)
-#define KWGBE_MAX_RX_PACKET_1518BYTE 0
-#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
-#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
-#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
-#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
-#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
-#define KWGBE_SET_EXT_LOOPBACK (1 << 20)
-#define KWGBE_CLR_EXT_LOOPBACK 0
-#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21)
-#define KWGBE_SET_HALF_DUPLEX_MODE 0
-#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
-#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define KWGBE_SET_GMII_SPEED_TO_10_100 0
-#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
-#define KWGBE_SET_MII_SPEED_TO_10 0
-#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24)
-
-/* SMI register fields */
-#define KWGBE_PHY_SMI_TIMEOUT 10000
-#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */
-#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS)
-#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
-#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
-#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
-#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
-#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
-#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
-
-/* SDMA command status fields macros */
-/* Tx & Rx descriptors status */
-#define KWGBE_ERROR_SUMMARY 1
-/* Tx & Rx descriptors command */
-#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31)
-/* Tx descriptors status */
-#define KWGBE_LC_ERROR 0
-#define KWGBE_UR_ERROR (1 << 1)
-#define KWGBE_RL_ERROR (1 << 2)
-#define KWGBE_LLC_SNAP_FORMAT (1 << 9)
-#define KWGBE_TX_LAST_FRAME (1 << 20)
-
-/* Rx descriptors status */
-#define KWGBE_CRC_ERROR 0
-#define KWGBE_OVERRUN_ERROR (1 << 1)
-#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
-#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
-#define KWGBE_VLAN_TAGGED (1 << 19)
-#define KWGBE_BPDU_FRAME (1 << 20)
-#define KWGBE_TCP_FRAME_OVER_IP_V_4 0
-#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
-#define KWGBE_OTHER_FRAME_TYPE (1 << 22)
-#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23)
-#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24)
-#define KWGBE_FRAME_HEADER_OK (1 << 25)
-#define KWGBE_RX_LAST_DESC (1 << 26)
-#define KWGBE_RX_FIRST_DESC (1 << 27)
-#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
-#define KWGBE_RX_EN_INTERRUPT (1 << 29)
-#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30)
-
-/* Rx descriptors byte count */
-#define KWGBE_FRAME_FRAGMENTED (1 << 2)
-
-/* Tx descriptors command */
-#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
-#define KWGBE_FRAME_SET_TO_VLAN (1 << 15)
-#define KWGBE_TCP_FRAME 0
-#define KWGBE_UDP_FRAME (1 << 16)
-#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
-#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
-#define KWGBE_ZERO_PADDING (1 << 19)
-#define KWGBE_TX_LAST_DESC (1 << 20)
-#define KWGBE_TX_FIRST_DESC (1 << 21)
-#define KWGBE_GEN_CRC (1 << 22)
-#define KWGBE_TX_EN_INTERRUPT (1 << 23)
-#define KWGBE_AUTO_MODE (1 << 30)
-
-/* Address decode parameters */
-/* Ethernet Base Address Register bits */
-#define EBAR_TARGET_DRAM 0x00000000
-#define EBAR_TARGET_DEVICE 0x00000001
-#define EBAR_TARGET_CBS 0x00000002
-#define EBAR_TARGET_PCI0 0x00000003
-#define EBAR_TARGET_PCI1 0x00000004
-#define EBAR_TARGET_CUNIT 0x00000005
-#define EBAR_TARGET_AUNIT 0x00000006
-#define EBAR_TARGET_GUNIT 0x00000007
-
-/* Window attrib */
-#define EBAR_DRAM_CS0 0x00000E00
-#define EBAR_DRAM_CS1 0x00000D00
-#define EBAR_DRAM_CS2 0x00000B00
-#define EBAR_DRAM_CS3 0x00000700
-
-/* DRAM Target interface */
-#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
-#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
-#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
-
-/* Device Bus Target interface */
-#define EBAR_DEVICE_DEVCS0 0x00001E00
-#define EBAR_DEVICE_DEVCS1 0x00001D00
-#define EBAR_DEVICE_DEVCS2 0x00001B00
-#define EBAR_DEVICE_DEVCS3 0x00001700
-#define EBAR_DEVICE_BOOTCS3 0x00000F00
-
-/* PCI Target interface */
-#define EBAR_PCI_BYTE_SWAP 0x00000000
-#define EBAR_PCI_NO_SWAP 0x00000100
-#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
-#define EBAR_PCI_WORD_SWAP 0x00000300
-#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
-#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
-#define EBAR_PCI_IO_SPACE 0x00000000
-#define EBAR_PCI_MEMORY_SPACE 0x00000800
-#define EBAR_PCI_REQ64_FORCE 0x00000000
-#define EBAR_PCI_REQ64_SIZE 0x00001000
-
-/* Window access control */
-#define EWIN_ACCESS_NOT_ALLOWED 0
-#define EWIN_ACCESS_READ_ONLY 1
-#define EWIN_ACCESS_FULL ((1 << 1) | 1)
-
-/* structures represents Controller registers */
-struct kwgbe_barsz {
- u32 bar;
- u32 size;
-};
-
-struct kwgbe_rxcdp {
- struct kwgbe_rxdesc *rxcdp;
- u32 rxcdp_pad[3];
-};
-
-struct kwgbe_tqx {
- u32 qxttbc;
- u32 tqxtbc;
- u32 tqxac;
- u32 tqxpad;
-};
-
-struct kwgbe_registers {
- u32 phyadr;
- u32 smi;
- u32 euda;
- u32 eudid;
- u8 pad1[0x080 - 0x00c - 4];
- u32 euic;
- u32 euim;
- u8 pad2[0x094 - 0x084 - 4];
- u32 euea;
- u32 euiae;
- u8 pad3[0x0b0 - 0x098 - 4];
- u32 euc;
- u8 pad3a[0x200 - 0x0b0 - 4];
- struct kwgbe_barsz barsz[6];
- u8 pad4[0x280 - 0x22c - 4];
- u32 ha_remap[4];
- u32 bare;
- u32 epap;
- u8 pad5[0x400 - 0x294 - 4];
- u32 pxc;
- u32 pxcx;
- u32 mii_ser_params;
- u8 pad6[0x410 - 0x408 - 4];
- u32 evlane;
- u32 macal;
- u32 macah;
- u32 sdc;
- u32 dscp[7];
- u32 psc0;
- u32 vpt2p;
- u32 ps0;
- u32 tqc;
- u32 psc1;
- u32 ps1;
- u32 mrvl_header;
- u8 pad7[0x460 - 0x454 - 4];
- u32 ic;
- u32 ice;
- u32 pim;
- u32 peim;
- u8 pad8[0x474 - 0x46c - 4];
- u32 pxtfut;
- u32 pad9;
- u32 pxmfs;
- u32 pad10;
- u32 pxdfc;
- u32 pxofc;
- u8 pad11[0x494 - 0x488 - 4];
- u32 peuiae;
- u8 pad12[0x4bc - 0x494 - 4];
- u32 eth_type_prio;
- u8 pad13[0x4dc - 0x4bc - 4];
- u32 tqfpc;
- u32 pttbrc;
- u32 tqc1;
- u32 pmtu;
- u32 pmtbs;
- u8 pad14[0x60c - 0x4ec - 4];
- struct kwgbe_rxcdp rxcdp[7];
- struct kwgbe_rxdesc *rxcdp7;
- u32 rqc;
- struct kwgbe_txdesc *tcsdp;
- u8 pad15[0x6c0 - 0x684 - 4];
- struct kwgbe_txdesc *tcqdp[8];
- u8 pad16[0x700 - 0x6dc - 4];
- struct kwgbe_tqx tqx[8];
- u32 pttbc;
- u8 pad17[0x7a8 - 0x780 - 4];
- u32 tqxipg0;
- u32 pad18[3];
- u32 tqxipg1;
- u8 pad19[0x7c0 - 0x7b8 - 4];
- u32 hitkninlopkt;
- u32 hitkninasyncpkt;
- u32 lotkninasyncpkt;
- u32 pad20;
- u32 ts;
- u8 pad21[0x3000 - 0x27d0 - 4];
- u32 pad20_1[32]; /* mib counter registes */
- u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
- u32 dfsmt[64];
- u32 dfomt[64];
- u32 dfut[4];
- u8 pad23[0xe20c0 - 0x7360c - 4];
- u32 pmbus_top_arbiter;
-};
-
-/* structures/enums needed by driver */
-enum kwgbe_adrwin {
- KWGBE_WIN0,
- KWGBE_WIN1,
- KWGBE_WIN2,
- KWGBE_WIN3,
- KWGBE_WIN4,
- KWGBE_WIN5
-};
-
-enum kwgbe_target {
- KWGBE_TARGET_DRAM,
- KWGBE_TARGET_DEV,
- KWGBE_TARGET_CBS,
- KWGBE_TARGET_PCI0,
- KWGBE_TARGET_PCI1
-};
-
-struct kwgbe_winparam {
- enum kwgbe_adrwin win; /* Window number */
- enum kwgbe_target target; /* System targets */
- u16 attrib; /* BAR attrib. See above macros */
- u32 base_addr; /* Window base address in u32 form */
- u32 high_addr; /* Window high address in u32 form */
- u32 size; /* Size in MBytes. Must be % 64Kbyte. */
- int enable; /* Enable/disable access to the window. */
- u16 access_ctrl; /*Access ctrl register. see above macros */
-};
-
-struct kwgbe_rxdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 buf_size; /* Buffer size */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer pointer */
- struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
-};
-
-struct kwgbe_txdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 l4i_chk; /* CPU provided TCP Checksum */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer ptr */
- struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
-};
-
-/* port device data struct */
-struct kwgbe_device {
- struct eth_device dev;
- struct kwgbe_registers *regs;
- struct kwgbe_txdesc *p_txdesc;
- struct kwgbe_rxdesc *p_rxdesc;
- struct kwgbe_rxdesc *p_rxdesc_curr;
- u8 *p_rxbuf;
- u8 *p_aligned_txbuf;
-};
-
-#endif /* __EGIGA_H__ */
--
1.6.4.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood
2010-07-02 16:53 ` [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga Albert Aribaud
@ 2010-07-02 16:53 ` Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC Albert Aribaud
2010-07-05 11:03 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Prafulla Wadaskar
2010-07-02 17:20 ` [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga Ben Warren
2010-07-05 11:02 ` Prafulla Wadaskar
2 siblings, 2 replies; 18+ messages in thread
From: Albert Aribaud @ 2010-07-02 16:53 UTC (permalink / raw)
To: u-boot
Set DRAM windows by using gd as other drivers do,
instead of calling kirkwood-specific functions.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
drivers/net/egiga.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
index 50e8ff3..cbe4748 100644
--- a/drivers/net/egiga.c
+++ b/drivers/net/egiga.c
@@ -38,6 +38,8 @@
#include <asm/arch/kirkwood.h>
#include "egiga.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define KIRKWOOD_PHY_ADR_REQUEST 0xee
#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
@@ -246,8 +248,8 @@ static void set_dram_access(struct kwgbe_registers *regs)
win_param.access_ctrl = EWIN_ACCESS_FULL;
win_param.high_addr = 0;
/* Get bank base */
- win_param.base_addr = kw_sdram_bar(i);
- win_param.size = kw_sdram_bs(i); /* Get bank size */
+ win_param.base_addr = gd->bd->bi_dram[i].start;
+ win_param.size = gd->bd->bi_dram[i].size;
if (win_param.size == 0)
win_param.enable = 0;
else
--
1.6.4.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC
2010-07-02 16:53 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Albert Aribaud
@ 2010-07-02 16:53 ` Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 4/4] egiga: add support for orion5x Albert Aribaud
2010-07-05 11:02 ` [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC Prafulla Wadaskar
2010-07-05 11:03 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Prafulla Wadaskar
1 sibling, 2 replies; 18+ messages in thread
From: Albert Aribaud @ 2010-07-02 16:53 UTC (permalink / raw)
To: u-boot
Macros, types, variables, functions in egiga
refer to kirkwood even though they are not
kirkwood-specific. Rename them, across the
whole source tree when necessary.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 4 +-
arch/arm/include/asm/arch-kirkwood/kirkwood.h | 10 +
drivers/net/Makefile | 2 +-
drivers/net/egiga.c | 321 +++++++++---------
drivers/net/egiga.h | 466 ++++++++++++------------
include/configs/guruplug.h | 4 +-
include/configs/km_arm.h | 4 +-
include/configs/mv88f6281gtw_ge.h | 4 +-
include/configs/openrd_base.h | 4 +-
include/configs/rd6281a.h | 4 +-
include/configs/sheevaplug.h | 4 +-
include/netdev.h | 2 +-
12 files changed, 422 insertions(+), 407 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 6fc3902..8d38c85 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -378,10 +378,10 @@ int arch_misc_init(void)
}
#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_KIRKWOOD_EGIGA
+#ifdef CONFIG_EGIGA
int cpu_eth_init(bd_t *bis)
{
- kirkwood_egiga_initialize(bis);
+ egiga_initialize(bis);
return 0;
}
#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index 2470efb..6aa1f6d 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -60,6 +60,16 @@
#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
+/*
+ * If board supports the EGIGA driver, then EGIGA0 and EGIGA1
+ * must be defined.
+ */
+
+#if defined(CONFIG_EGIGA)
+#define EGIGA0_BASE KW_EGIGA0_BASE
+#define EGIGA1_BASE KW_EGIGA1_BASE
+#endif
+
#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
#elif defined (CONFIG_KW88F6192)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 8853908..a60e384 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
COBJS-$(CONFIG_DNET) += dnet.o
COBJS-$(CONFIG_E1000) += e1000.o
COBJS-$(CONFIG_EEPRO100) += eepro100.o
+COBJS-$(CONFIG_EGIGA) += egiga.o
COBJS-$(CONFIG_ENC28J60) += enc28j60.o
COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o
COBJS-$(CONFIG_ETHOC) += ethoc.o
@@ -46,7 +47,6 @@ COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
COBJS-$(CONFIG_GRETH) += greth.o
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
-COBJS-$(CONFIG_KIRKWOOD_EGIGA) += egiga.o
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
COBJS-$(CONFIG_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_MACB) += macb.o
diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
index cbe4748..bb0de68 100644
--- a/drivers/net/egiga.c
+++ b/drivers/net/egiga.c
@@ -35,13 +35,16 @@
#include <asm/errno.h>
#include <asm/types.h>
#include <asm/byteorder.h>
+#if defined (CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
+#endif
#include "egiga.h"
DECLARE_GLOBAL_DATA_PTR;
-#define KIRKWOOD_PHY_ADR_REQUEST 0xee
-#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
+#define EGIGA_PHY_ADR_REQUEST 0xee
+#define EGIGA_SMI_REG (((struct egiga_registers *)EGIGA0_BASE)->smi)
+#define EGIGA_PSC1_REG(base) (((struct egiga_registers *)base)->psc1)
/*
* smi_reg_read - miiphy_read callback function.
@@ -51,16 +54,16 @@ DECLARE_GLOBAL_DATA_PTR;
static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr read request */
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
+ if (phy_adr == EGIGA_PHY_ADR_REQUEST &&
+ reg_ofs == EGIGA_PHY_ADR_REQUEST) {
/* */
- *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
+ *data = (u16) (EGIGA_REG_RD(regs->phyadr) & PHYADR_MASK);
return 0;
}
/* check parameters */
@@ -75,42 +78,42 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
return -EFAULT;
}
- timeout = KWGBE_PHY_SMI_TIMEOUT;
+ timeout = EGIGA_PHY_SMI_TIMEOUT;
/* wait till the SMI is not busy */
do {
/* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ smi_reg = EGIGA_REG_RD(EGIGA_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -EFAULT;
}
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+ } while (smi_reg & EGIGA_PHY_SMI_BUSY_MASK);
/* fill the phy address and regiser offset and read opcode */
- smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
- | KWGBE_PHY_SMI_OPCODE_READ;
+ smi_reg = (phy_adr << EGIGA_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << EGIGA_SMI_REG_ADDR_OFFS)
+ | EGIGA_PHY_SMI_OPCODE_READ;
/* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+ EGIGA_REG_WR(EGIGA_SMI_REG, smi_reg);
/*wait till read value is ready */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
+ timeout = EGIGA_PHY_SMI_TIMEOUT;
do {
/* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ smi_reg = EGIGA_REG_RD(EGIGA_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI read ready timeout\n",
__FUNCTION__);
return -EFAULT;
}
- } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
+ } while (!(smi_reg & EGIGA_PHY_SMI_READ_VALID_MASK));
/* Wait for the data to update in the SMI register */
- for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
+ for (timeout = 0; timeout < EGIGA_PHY_SMI_TIMEOUT; timeout++) ;
- *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
+ *data = (u16) (EGIGA_REG_RD(EGIGA_SMI_REG) & EGIGA_PHY_SMI_DATA_MASK);
debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
reg_ofs, *data);
@@ -127,15 +130,15 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr write request*/
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
- KWGBEREG_WR(regs->phyadr, data);
+ if (phy_adr == EGIGA_PHY_ADR_REQUEST &&
+ reg_ofs == EGIGA_PHY_ADR_REQUEST) {
+ EGIGA_REG_WR(regs->phyadr, data);
return 0;
}
@@ -150,24 +153,24 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
}
/* wait till the SMI is not busy */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
+ timeout = EGIGA_PHY_SMI_TIMEOUT;
do {
/* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ smi_reg = EGIGA_REG_RD(EGIGA_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -ETIME;
}
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+ } while (smi_reg & EGIGA_PHY_SMI_BUSY_MASK);
/* fill the phy addr and reg offset and write opcode and data */
- smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
- smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
- smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
+ smi_reg = (data << EGIGA_PHY_SMI_DATA_OFFS);
+ smi_reg |= (phy_adr << EGIGA_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << EGIGA_SMI_REG_ADDR_OFFS);
+ smi_reg &= ~EGIGA_PHY_SMI_OPCODE_READ;
/* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+ EGIGA_REG_WR(EGIGA_SMI_REG, smi_reg);
return 0;
}
@@ -204,46 +207,46 @@ static void stop_queue(u32 * qreg)
* @regs Register struct pointer.
* @param Address decode parameter struct.
*/
-static void set_access_control(struct kwgbe_registers *regs,
- struct kwgbe_winparam *param)
+static void set_access_control(struct egiga_registers *regs,
+ struct egiga_winparam *param)
{
u32 access_prot_reg;
/* Set access control register */
- access_prot_reg = KWGBEREG_RD(regs->epap);
+ access_prot_reg = EGIGA_REG_RD(regs->epap);
/* clear window permission */
access_prot_reg &= (~(3 << (param->win * 2)));
access_prot_reg |= (param->access_ctrl << (param->win * 2));
- KWGBEREG_WR(regs->epap, access_prot_reg);
+ EGIGA_REG_WR(regs->epap, access_prot_reg);
/* Set window Size reg (SR) */
- KWGBEREG_WR(regs->barsz[param->win].size,
+ EGIGA_REG_WR(regs->barsz[param->win].size,
(((param->size / 0x10000) - 1) << 16));
/* Set window Base address reg (BA) */
- KWGBEREG_WR(regs->barsz[param->win].bar,
+ EGIGA_REG_WR(regs->barsz[param->win].bar,
(param->target | param->attrib | param->base_addr));
/* High address remap reg (HARR) */
if (param->win < 4)
- KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
+ EGIGA_REG_WR(regs->ha_remap[param->win], param->high_addr);
/* Base address enable reg (BARER) */
if (param->enable == 1)
- KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
+ EGIGA_REG_BITS_RESET(regs->bare, (1 << param->win));
else
- KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
+ EGIGA_REG_BITS_SET(regs->bare, (1 << param->win));
}
-static void set_dram_access(struct kwgbe_registers *regs)
+static void set_dram_access(struct egiga_registers *regs)
{
- struct kwgbe_winparam win_param;
+ struct egiga_winparam win_param;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Set access parameters for DRAM bank i */
win_param.win = i; /* Use Ethernet window i */
/* Window target - DDR */
- win_param.target = KWGBE_TARGET_DRAM;
+ win_param.target = EGIGA_TARGET_DRAM;
/* Enable full access */
win_param.access_ctrl = EWIN_ACCESS_FULL;
win_param.high_addr = 0;
@@ -286,19 +289,19 @@ static void set_dram_access(struct kwgbe_registers *regs)
* Go through all the DA filter tables (Unicast, Special Multicast & Other
* Multicast) and set each entry to 0.
*/
-static void port_init_mac_tables(struct kwgbe_registers *regs)
+static void port_init_mac_tables(struct egiga_registers *regs)
{
int table_index;
/* Clear DA filter unicast table (Ex_dFUT) */
for (table_index = 0; table_index < 4; ++table_index)
- KWGBEREG_WR(regs->dfut[table_index], 0);
+ EGIGA_REG_WR(regs->dfut[table_index], 0);
for (table_index = 0; table_index < 64; ++table_index) {
/* Clear DA filter special multicast table (Ex_dFSMT) */
- KWGBEREG_WR(regs->dfsmt[table_index], 0);
+ EGIGA_REG_WR(regs->dfsmt[table_index], 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */
- KWGBEREG_WR(regs->dfomt[table_index], 0);
+ EGIGA_REG_WR(regs->dfomt[table_index], 0);
}
}
@@ -316,7 +319,7 @@ static void port_init_mac_tables(struct kwgbe_registers *regs)
*
* RETURN: 1 if output succeeded. 0 if option parameter is invalid.
*/
-static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
+static int port_uc_addr(struct egiga_registers *regs, u8 uc_nibble,
int option)
{
u32 unicast_reg;
@@ -336,16 +339,16 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
* Clear accepts frame bit at specified unicast
* DA table entry
*/
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+ unicast_reg = EGIGA_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+ EGIGA_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
case ACCEPT_MAC_ADDR:
/* Set accepts frame bit at unicast DA filter table entry */
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+ unicast_reg = EGIGA_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+ EGIGA_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
default:
return 0;
@@ -356,7 +359,7 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
/*
* port_uc_addr_set - This function Set the port Unicast address.
*/
-static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
+static void port_uc_addr_set(struct egiga_registers *regs, u8 * p_addr)
{
u32 mac_h;
u32 mac_l;
@@ -365,92 +368,92 @@ static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
(p_addr[3] << 0);
- KWGBEREG_WR(regs->macal, mac_l);
- KWGBEREG_WR(regs->macah, mac_h);
+ EGIGA_REG_WR(regs->macal, mac_l);
+ EGIGA_REG_WR(regs->macah, mac_h);
/* Accept frames of this address */
port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
}
/*
- * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ * egiga_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
*/
-static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
+static void egiga_init_rx_desc_ring(struct egiga_device *dgbe)
{
- struct kwgbe_rxdesc *p_rx_desc;
+ struct egiga_rxdesc *p_rx_desc;
int i;
/* initialize the Rx descriptors ring */
- p_rx_desc = dkwgbe->p_rxdesc;
+ p_rx_desc = dgbe->p_rxdesc;
for (i = 0; i < RINGSZ; i++) {
p_rx_desc->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+ EGIGA_BUFFER_OWNED_BY_DMA | EGIGA_RX_EN_INTERRUPT;
p_rx_desc->buf_size = PKTSIZE_ALIGN;
p_rx_desc->byte_cnt = 0;
- p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
+ p_rx_desc->buf_ptr = dgbe->p_rxbuf + i * PKTSIZE_ALIGN;
if (i == (RINGSZ - 1))
- p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
+ p_rx_desc->nxtdesc_p = dgbe->p_rxdesc;
else {
- p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
- ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
+ p_rx_desc->nxtdesc_p = (struct egiga_rxdesc *)
+ ((u32) p_rx_desc + EGIGA_RXQ_DESC_ALIGNED_SIZE);
p_rx_desc = p_rx_desc->nxtdesc_p;
}
}
- dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
+ dgbe->p_rxdesc_curr = dgbe->p_rxdesc;
}
-static int kwgbe_init(struct eth_device *dev)
+static int egiga_init(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
- kwgbe_init_rx_desc_ring(dkwgbe);
+ egiga_init_rx_desc_ring(dgbe);
/* Clear the ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
+ EGIGA_REG_WR(regs->ic, 0);
+ EGIGA_REG_WR(regs->ice, 0);
/* Unmask RX buffer and TX end interrupt */
- KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
+ EGIGA_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
/* Unmask phy and link status changes interrupts */
- KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
+ EGIGA_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
set_dram_access(regs);
port_init_mac_tables(regs);
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+ port_uc_addr_set(regs, dgbe->dev.enetaddr);
/* Assign port configuration and command. */
- KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
- KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
- KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
+ EGIGA_REG_WR(regs->pxc, PRT_CFG_VAL);
+ EGIGA_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
+ EGIGA_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
/* Assign port SDMA configuration */
- KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
- KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
- KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
+ EGIGA_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
+ EGIGA_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
+ EGIGA_REG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
/* Turn off the port/RXUQ bandwidth limitation */
- KWGBEREG_WR(regs->pmtu, 0);
+ EGIGA_REG_WR(regs->pmtu, 0);
/* Set maximum receive buffer to 9700 bytes */
- KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
- | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
+ EGIGA_REG_WR(regs->psc0, EGIGA_MAX_RX_PACKET_9700BYTE
+ | (EGIGA_REG_RD(regs->psc0) & MRU_MASK));
/* Enable port initially */
- KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+ EGIGA_REG_BITS_SET(regs->psc0, EGIGA_SERIAL_PORT_EN);
/*
* Set ethernet MTU for leaky bucket mechanism to 0 - this will
* disable the leaky bucket mechanism .
*/
- KWGBEREG_WR(regs->pmtu, 0);
+ EGIGA_REG_WR(regs->pmtu, 0);
/* Assignment of Rx CRDB of given RXUQ */
- KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
+ EGIGA_REG_WR(regs->rxcdp[RXUQ], (u32) dgbe->p_rxdesc_curr);
/* Enable port Rx. */
- KWGBEREG_WR(regs->rqc, (1 << RXUQ));
+ EGIGA_REG_WR(regs->rqc, (1 << RXUQ));
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
@@ -458,8 +461,8 @@ static int kwgbe_init(struct eth_device *dev)
for (i = 0; i < 5; i++) {
u16 phyadr;
- miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
+ miiphy_read(dev->name, EGIGA_PHY_ADR_REQUEST,
+ EGIGA_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
if (miiphy_link(dev->name, phyadr))
return 0;
@@ -472,50 +475,50 @@ static int kwgbe_init(struct eth_device *dev)
return 0;
}
-static int kwgbe_halt(struct eth_device *dev)
+static int egiga_halt(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
/* Disable all gigE address decoder */
- KWGBEREG_WR(regs->bare, 0x3f);
+ EGIGA_REG_WR(regs->bare, 0x3f);
stop_queue(®s->tqc);
stop_queue(®s->rqc);
/* Disable port */
- KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+ EGIGA_REG_BITS_RESET(regs->psc0, EGIGA_SERIAL_PORT_EN);
/* Set port is not reset */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
+ EGIGA_REG_BITS_RESET(regs->psc1, 1 << 4);
#ifdef CONFIG_SYS_MII_MODE
/* Set MMI interface up */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
+ EGIGA_REG_BITS_RESET(regs->psc1, 1 << 3);
#endif
/* Disable & mask ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
- KWGBEREG_WR(regs->pim, 0);
- KWGBEREG_WR(regs->peim, 0);
+ EGIGA_REG_WR(regs->ic, 0);
+ EGIGA_REG_WR(regs->ice, 0);
+ EGIGA_REG_WR(regs->pim, 0);
+ EGIGA_REG_WR(regs->peim, 0);
return 0;
}
-static int kwgbe_write_hwaddr(struct eth_device *dev)
+static int egiga_write_hwaddr(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
/* Programs net device MAC address after initialization */
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+ port_uc_addr_set(regs, dgbe->dev.enetaddr);
return 0;
}
-static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
+static int egiga_send(struct eth_device *dev, volatile void *dataptr,
int datasize)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
- struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_registers *regs = dgbe->regs;
+ struct egiga_txdesc *p_txdesc = dgbe->p_txdesc;
void *p = (void *)dataptr;
u32 cmd_sts;
@@ -527,30 +530,30 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return -1;
}
- memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
- p = dkwgbe->p_aligned_txbuf;
+ memcpy(dgbe->p_aligned_txbuf, p, datasize);
+ p = dgbe->p_aligned_txbuf;
}
- p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
- p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
- p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
- p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
+ p_txdesc->cmd_sts = EGIGA_ZERO_PADDING | EGIGA_GEN_CRC;
+ p_txdesc->cmd_sts |= EGIGA_TX_FIRST_DESC | EGIGA_TX_LAST_DESC;
+ p_txdesc->cmd_sts |= EGIGA_BUFFER_OWNED_BY_DMA;
+ p_txdesc->cmd_sts |= EGIGA_TX_EN_INTERRUPT;
p_txdesc->buf_ptr = (u8 *) p;
p_txdesc->byte_cnt = datasize;
/* Apply send command using zeroth TXUQ */
- KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
- KWGBEREG_WR(regs->tqc, (1 << TXUQ));
+ EGIGA_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
+ EGIGA_REG_WR(regs->tqc, (1 << TXUQ));
/*
* wait for packet xmit completion
*/
cmd_sts = readl(&p_txdesc->cmd_sts);
- while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
+ while (cmd_sts & EGIGA_BUFFER_OWNED_BY_DMA) {
/* return fail if error is detected */
- if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
- (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
- cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
+ if ((cmd_sts & (EGIGA_ERROR_SUMMARY | EGIGA_TX_LAST_FRAME)) ==
+ (EGIGA_ERROR_SUMMARY | EGIGA_TX_LAST_FRAME) &&
+ cmd_sts & (EGIGA_UR_ERROR | EGIGA_RL_ERROR)) {
printf("Err..(%s) in xmit packet\n", __FUNCTION__);
return -1;
}
@@ -559,22 +562,22 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return 0;
}
-static int kwgbe_recv(struct eth_device *dev)
+static int egiga_recv(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
+ struct egiga_device *dgbe = to_dgbe(dev);
+ struct egiga_rxdesc *p_rxdesc_curr = dgbe->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
/* wait untill rx packet available or timeout */
do {
- if (timeout < KWGBE_PHY_SMI_TIMEOUT)
+ if (timeout < EGIGA_PHY_SMI_TIMEOUT)
timeout++;
else {
debug("%s time out...\n", __FUNCTION__);
return -1;
}
- } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
+ } while (readl(&p_rxdesc_curr->cmd_sts) & EGIGA_BUFFER_OWNED_BY_DMA);
if (p_rxdesc_curr->byte_cnt != 0) {
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
@@ -591,13 +594,13 @@ static int kwgbe_recv(struct eth_device *dev)
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
if ((cmd_sts &
- (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
- != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
+ (EGIGA_RX_FIRST_DESC | EGIGA_RX_LAST_DESC))
+ != (EGIGA_RX_FIRST_DESC | EGIGA_RX_LAST_DESC)) {
printf("Err..(%s) Dropping packet spread on"
" multiple descriptors\n", __FUNCTION__);
- } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
+ } else if (cmd_sts & EGIGA_ERROR_SUMMARY) {
printf("Err..(%s) Dropping packet with errors\n",
__FUNCTION__);
@@ -615,62 +618,62 @@ static int kwgbe_recv(struct eth_device *dev)
* free these descriptors and point next in the ring
*/
p_rxdesc_curr->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+ EGIGA_BUFFER_OWNED_BY_DMA | EGIGA_RX_EN_INTERRUPT;
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
- writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
+ writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dgbe->p_rxdesc_curr);
return 0;
}
-int kirkwood_egiga_initialize(bd_t * bis)
+int egiga_initialize(bd_t * bis)
{
- struct kwgbe_device *dkwgbe;
+ struct egiga_device *dgbe;
struct eth_device *dev;
int devnum;
char *s;
- u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
+ u8 used_ports[MAX_GBE_DEVS] = CONFIG_EGIGA_PORTS;
- for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
+ for (devnum = 0; devnum < MAX_GBE_DEVS; devnum++) {
/*skip if port is configured not to use */
if (used_ports[devnum] == 0)
continue;
- if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
+ if (!(dgbe = malloc(sizeof(struct egiga_device))))
goto error1;
- memset(dkwgbe, 0, sizeof(struct kwgbe_device));
+ memset(dgbe, 0, sizeof(struct egiga_device));
- if (!(dkwgbe->p_rxdesc =
- (struct kwgbe_rxdesc *)memalign(PKTALIGN,
- KW_RXQ_DESC_ALIGNED_SIZE
+ if (!(dgbe->p_rxdesc =
+ (struct egiga_rxdesc *)memalign(PKTALIGN,
+ EGIGA_RXQ_DESC_ALIGNED_SIZE
* RINGSZ + 1)))
goto error2;
- if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
+ if (!(dgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
* PKTSIZE_ALIGN + 1)))
goto error3;
- if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
+ if (!(dgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
goto error4;
- if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
- memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
- free(dkwgbe->p_aligned_txbuf);
+ if (!(dgbe->p_txdesc = (struct egiga_txdesc *)
+ memalign(PKTALIGN, sizeof(struct egiga_txdesc) + 1))) {
+ free(dgbe->p_aligned_txbuf);
error4:
- free(dkwgbe->p_rxbuf);
+ free(dgbe->p_rxbuf);
error3:
- free(dkwgbe->p_rxdesc);
+ free(dgbe->p_rxdesc);
error2:
- free(dkwgbe);
+ free(dgbe);
error1:
printf("Err.. %s Failed to allocate memory\n",
__FUNCTION__);
return -1;
}
- dev = &dkwgbe->dev;
+ dev = &dgbe->dev;
/* must be less than NAMESIZE (16) */
sprintf(dev->name, "egiga%d", devnum);
@@ -678,13 +681,15 @@ int kirkwood_egiga_initialize(bd_t * bis)
/* Extract the MAC address from the environment */
switch (devnum) {
case 0:
- dkwgbe->regs = (void *)KW_EGIGA0_BASE;
+ dgbe->regs = (void *)EGIGA0_BASE;
s = "ethaddr";
break;
+#if defined (EGIGA1_BASE)
case 1:
- dkwgbe->regs = (void *)KW_EGIGA1_BASE;
+ dgbe->regs = (void *)EGIGA1_BASE;
s = "eth1addr";
break;
+#endif
default: /* this should never happen */
printf("Err..(%s) Invalid device number %d\n",
__FUNCTION__, devnum);
@@ -702,19 +707,19 @@ int kirkwood_egiga_initialize(bd_t * bis)
eth_setenv_enetaddr(s, dev->enetaddr);
}
- dev->init = (void *)kwgbe_init;
- dev->halt = (void *)kwgbe_halt;
- dev->send = (void *)kwgbe_send;
- dev->recv = (void *)kwgbe_recv;
- dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
+ dev->init = (void *)egiga_init;
+ dev->halt = (void *)egiga_halt;
+ dev->send = (void *)egiga_send;
+ dev->recv = (void *)egiga_recv;
+ dev->write_hwaddr = (void *)egiga_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, smi_reg_read, smi_reg_write);
/* Set phy address of the port */
- miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
+ miiphy_write(dev->name, EGIGA_PHY_ADR_REQUEST,
+ EGIGA_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
#endif
}
return 0;
diff --git a/drivers/net/egiga.h b/drivers/net/egiga.h
index 30c773c..f758d3c 100644
--- a/drivers/net/egiga.h
+++ b/drivers/net/egiga.h
@@ -28,7 +28,7 @@
#ifndef __EGIGA_H__
#define __EGIGA_H__
-#define MAX_KWGBE_DEVS 2 /*controller has two ports */
+#define MAX_GBE_DEVS 2 /*controller has two ports */
/* PHY_BASE_ADR is board specific and can be configured */
#if defined (CONFIG_PHY_BASE_ADR)
@@ -49,60 +49,60 @@
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
-#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
-#define KWGBEREG_WR(adr, val) writel(val, &adr)
-#define KWGBEREG_RD(adr) readl(&adr)
-#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
-#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
+#define to_dgbe(_ed) container_of(_ed, struct egiga_device, dev)
+#define EGIGA_REG_WR(adr, val) writel(val, &adr)
+#define EGIGA_REG_RD(adr) readl(&adr)
+#define EGIGA_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
+#define EGIGA_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
/* Default port configuration value */
#define PRT_CFG_VAL ( \
- KWGBE_UCAST_MOD_NRML | \
- KWGBE_DFLT_RXQ(RXUQ) | \
- KWGBE_DFLT_RX_ARPQ(RXUQ) | \
- KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
- KWGBE_RX_BC_IF_IP | \
- KWGBE_RX_BC_IF_ARP | \
- KWGBE_CPTR_TCP_FRMS_DIS | \
- KWGBE_CPTR_UDP_FRMS_DIS | \
- KWGBE_DFLT_RX_TCPQ(RXUQ) | \
- KWGBE_DFLT_RX_UDPQ(RXUQ) | \
- KWGBE_DFLT_RX_BPDUQ(RXUQ))
+ EGIGA_UCAST_MOD_NRML | \
+ EGIGA_DFLT_RXQ(RXUQ) | \
+ EGIGA_DFLT_RX_ARPQ(RXUQ) | \
+ EGIGA_RX_BC_IF_NOT_IP_OR_ARP | \
+ EGIGA_RX_BC_IF_IP | \
+ EGIGA_RX_BC_IF_ARP | \
+ EGIGA_CPTR_TCP_FRMS_DIS | \
+ EGIGA_CPTR_UDP_FRMS_DIS | \
+ EGIGA_DFLT_RX_TCPQ(RXUQ) | \
+ EGIGA_DFLT_RX_UDPQ(RXUQ) | \
+ EGIGA_DFLT_RX_BPDUQ(RXUQ))
/* Default port extend configuration value */
#define PORT_CFG_EXTEND_VALUE \
- KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
- KWGBE_PARTITION_DIS | \
- KWGBE_TX_CRC_GENERATION_EN
+ EGIGA_SPAN_BPDU_PACKETS_AS_NORMAL | \
+ EGIGA_PARTITION_DIS | \
+ EGIGA_TX_CRC_GENERATION_EN
-#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
+#define GT_EGIGA_IPG_INT_RX(value) ((value & 0x3fff) << 8)
/* Default sdma control value */
#define PORT_SDMA_CFG_VALUE ( \
- KWGBE_RX_BURST_SIZE_16_64BIT | \
- KWGBE_BLM_RX_NO_SWAP | \
- KWGBE_BLM_TX_NO_SWAP | \
- GT_KWGBE_IPG_INT_RX(RXUQ) | \
- KWGBE_TX_BURST_SIZE_16_64BIT)
+ EGIGA_RX_BURST_SIZE_16_64BIT | \
+ EGIGA_BLM_RX_NO_SWAP | \
+ EGIGA_BLM_TX_NO_SWAP | \
+ GT_EGIGA_IPG_INT_RX(RXUQ) | \
+ EGIGA_TX_BURST_SIZE_16_64BIT)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE ( \
- KWGBE_FORCE_LINK_PASS | \
- KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
- KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
- KWGBE_ADV_NO_FLOW_CTRL | \
- KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- KWGBE_FORCE_BP_MODE_NO_JAM | \
+ EGIGA_FORCE_LINK_PASS | \
+ EGIGA_DIS_AUTO_NEG_FOR_DUPLX | \
+ EGIGA_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
+ EGIGA_ADV_NO_FLOW_CTRL | \
+ EGIGA_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ EGIGA_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
- KWGBE_DO_NOT_FORCE_LINK_FAIL | \
- KWGBE_EN_AUTO_NEG_SPEED_GMII | \
- KWGBE_DTE_ADV_0 | \
- KWGBE_MIIPHY_MAC_MODE | \
- KWGBE_AUTO_NEG_NO_CHANGE | \
- KWGBE_MAX_RX_PACKET_1552BYTE | \
- KWGBE_CLR_EXT_LOOPBACK | \
- KWGBE_SET_FULL_DUPLEX_MODE | \
- KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
+ EGIGA_DO_NOT_FORCE_LINK_FAIL | \
+ EGIGA_EN_AUTO_NEG_SPEED_GMII | \
+ EGIGA_DTE_ADV_0 | \
+ EGIGA_MIIPHY_MAC_MODE | \
+ EGIGA_AUTO_NEG_NO_CHANGE | \
+ EGIGA_MAX_RX_PACKET_1552BYTE | \
+ EGIGA_CLR_EXT_LOOPBACK | \
+ EGIGA_SET_FULL_DUPLEX_MODE | \
+ EGIGA_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
@@ -112,187 +112,187 @@
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define KW_RXQ_DESC_ALIGNED_SIZE \
- (((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
+#define EGIGA_RXQ_DESC_ALIGNED_SIZE \
+ (((sizeof(struct egiga_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Port serial status reg (PSR) */
-#define KWGBE_INTERFACE_GMII_MII 0
-#define KWGBE_INTERFACE_PCM 1
-#define KWGBE_LINK_IS_DOWN 0
-#define KWGBE_LINK_IS_UP (1 << 1)
-#define KWGBE_PORT_AT_HALF_DUPLEX 0
-#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2)
-#define KWGBE_RX_FLOW_CTRL_DISD 0
-#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
-#define KWGBE_GMII_SPEED_100_10 0
-#define KWGBE_GMII_SPEED_1000 (1 << 4)
-#define KWGBE_MII_SPEED_10 0
-#define KWGBE_MII_SPEED_100 (1 << 5)
-#define KWGBE_NO_TX 0
-#define KWGBE_TX_IN_PROGRESS (1 << 7)
-#define KWGBE_BYPASS_NO_ACTIVE 0
-#define KWGBE_BYPASS_ACTIVE (1 << 8)
-#define KWGBE_PORT_NOT_AT_PARTN_STT 0
-#define KWGBE_PORT_AT_PARTN_STT (1 << 9)
-#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0
-#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10)
+#define EGIGA_INTERFACE_GMII_MII 0
+#define EGIGA_INTERFACE_PCM 1
+#define EGIGA_LINK_IS_DOWN 0
+#define EGIGA_LINK_IS_UP (1 << 1)
+#define EGIGA_PORT_AT_HALF_DUPLEX 0
+#define EGIGA_PORT_AT_FULL_DUPLEX (1 << 2)
+#define EGIGA_RX_FLOW_CTRL_DISD 0
+#define EGIGA_RX_FLOW_CTRL_ENBALED (1 << 3)
+#define EGIGA_GMII_SPEED_100_10 0
+#define EGIGA_GMII_SPEED_1000 (1 << 4)
+#define EGIGA_MII_SPEED_10 0
+#define EGIGA_MII_SPEED_100 (1 << 5)
+#define EGIGA_NO_TX 0
+#define EGIGA_TX_IN_PROGRESS (1 << 7)
+#define EGIGA_BYPASS_NO_ACTIVE 0
+#define EGIGA_BYPASS_ACTIVE (1 << 8)
+#define EGIGA_PORT_NOT_AT_PARTN_STT 0
+#define EGIGA_PORT_AT_PARTN_STT (1 << 9)
+#define EGIGA_PORT_TX_FIFO_NOT_EMPTY 0
+#define EGIGA_PORT_TX_FIFO_EMPTY (1 << 10)
/* These macros describes the Port configuration reg (Px_cR) bits */
-#define KWGBE_UCAST_MOD_NRML 0
-#define KWGBE_UNICAST_PROMISCUOUS_MODE 1
-#define KWGBE_DFLT_RXQ(_x) (_x << 1)
-#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4)
-#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0
-#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
-#define KWGBE_RX_BC_IF_IP 0
-#define KWGBE_REJECT_BC_IF_IP (1 << 8)
-#define KWGBE_RX_BC_IF_ARP 0
-#define KWGBE_REJECT_BC_IF_ARP (1 << 9)
-#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
-#define KWGBE_CPTR_TCP_FRMS_DIS 0
-#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14)
-#define KWGBE_CPTR_UDP_FRMS_DIS 0
-#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15)
-#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16)
-#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19)
-#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
-#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
+#define EGIGA_UCAST_MOD_NRML 0
+#define EGIGA_UNICAST_PROMISCUOUS_MODE 1
+#define EGIGA_DFLT_RXQ(_x) (_x << 1)
+#define EGIGA_DFLT_RX_ARPQ(_x) (_x << 4)
+#define EGIGA_RX_BC_IF_NOT_IP_OR_ARP 0
+#define EGIGA_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
+#define EGIGA_RX_BC_IF_IP 0
+#define EGIGA_REJECT_BC_IF_IP (1 << 8)
+#define EGIGA_RX_BC_IF_ARP 0
+#define EGIGA_REJECT_BC_IF_ARP (1 << 9)
+#define EGIGA_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
+#define EGIGA_CPTR_TCP_FRMS_DIS 0
+#define EGIGA_CPTR_TCP_FRMS_EN (1 << 14)
+#define EGIGA_CPTR_UDP_FRMS_DIS 0
+#define EGIGA_CPTR_UDP_FRMS_EN (1 << 15)
+#define EGIGA_DFLT_RX_TCPQ(_x) (_x << 16)
+#define EGIGA_DFLT_RX_UDPQ(_x) (_x << 19)
+#define EGIGA_DFLT_RX_BPDUQ(_x) (_x << 22)
+#define EGIGA_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define KWGBE_CLASSIFY_EN 1
-#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
-#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
-#define KWGBE_PARTITION_DIS 0
-#define KWGBE_PARTITION_EN (1 << 2)
-#define KWGBE_TX_CRC_GENERATION_EN 0
-#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3)
+#define EGIGA_CLASSIFY_EN 1
+#define EGIGA_SPAN_BPDU_PACKETS_AS_NORMAL 0
+#define EGIGA_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
+#define EGIGA_PARTITION_DIS 0
+#define EGIGA_PARTITION_EN (1 << 2)
+#define EGIGA_TX_CRC_GENERATION_EN 0
+#define EGIGA_TX_CRC_GENERATION_DIS (1 << 3)
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define KWGBE_RIFB 1
-#define KWGBE_RX_BURST_SIZE_1_64BIT 0
-#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
-#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
-#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
-#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
-#define KWGBE_BLM_RX_NO_SWAP (1 << 4)
-#define KWGBE_BLM_RX_BYTE_SWAP 0
-#define KWGBE_BLM_TX_NO_SWAP (1 << 5)
-#define KWGBE_BLM_TX_BYTE_SWAP 0
-#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
-#define KWGBE_DESCRIPTORS_NO_SWAP 0
-#define KWGBE_TX_BURST_SIZE_1_64BIT 0
-#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
-#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
-#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
-#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
+#define EGIGA_RIFB 1
+#define EGIGA_RX_BURST_SIZE_1_64BIT 0
+#define EGIGA_RX_BURST_SIZE_2_64BIT (1 << 1)
+#define EGIGA_RX_BURST_SIZE_4_64BIT (1 << 2)
+#define EGIGA_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
+#define EGIGA_RX_BURST_SIZE_16_64BIT (1 << 3)
+#define EGIGA_BLM_RX_NO_SWAP (1 << 4)
+#define EGIGA_BLM_RX_BYTE_SWAP 0
+#define EGIGA_BLM_TX_NO_SWAP (1 << 5)
+#define EGIGA_BLM_TX_BYTE_SWAP 0
+#define EGIGA_DESCRIPTORS_BYTE_SWAP (1 << 6)
+#define EGIGA_DESCRIPTORS_NO_SWAP 0
+#define EGIGA_TX_BURST_SIZE_1_64BIT 0
+#define EGIGA_TX_BURST_SIZE_2_64BIT (1 << 22)
+#define EGIGA_TX_BURST_SIZE_4_64BIT (1 << 23)
+#define EGIGA_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
+#define EGIGA_TX_BURST_SIZE_16_64BIT (1 << 24)
/* These macros describes the Port serial control reg (PSCR) bits */
-#define KWGBE_SERIAL_PORT_DIS 0
-#define KWGBE_SERIAL_PORT_EN 1
-#define KWGBE_FORCE_LINK_PASS (1 << 1)
-#define KWGBE_DO_NOT_FORCE_LINK_PASS 0
-#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0
-#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
-#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
-#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
-#define KWGBE_ADV_NO_FLOW_CTRL 0
-#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
-#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
-#define KWGBE_FORCE_BP_MODE_NO_JAM 0
-#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
-#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
-#define KWGBE_FORCE_LINK_FAIL 0
-#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
-#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
-#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0
-#define KWGBE_DTE_ADV_0 0
-#define KWGBE_DTE_ADV_1 (1 << 14)
-#define KWGBE_MIIPHY_MAC_MODE 0
-#define KWGBE_MIIPHY_PHY_MODE (1 << 15)
-#define KWGBE_AUTO_NEG_NO_CHANGE 0
-#define KWGBE_RESTART_AUTO_NEG (1 << 16)
-#define KWGBE_MAX_RX_PACKET_1518BYTE 0
-#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
-#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
-#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
-#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
-#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
-#define KWGBE_SET_EXT_LOOPBACK (1 << 20)
-#define KWGBE_CLR_EXT_LOOPBACK 0
-#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21)
-#define KWGBE_SET_HALF_DUPLEX_MODE 0
-#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
-#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define KWGBE_SET_GMII_SPEED_TO_10_100 0
-#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
-#define KWGBE_SET_MII_SPEED_TO_10 0
-#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24)
+#define EGIGA_SERIAL_PORT_DIS 0
+#define EGIGA_SERIAL_PORT_EN 1
+#define EGIGA_FORCE_LINK_PASS (1 << 1)
+#define EGIGA_DO_NOT_FORCE_LINK_PASS 0
+#define EGIGA_EN_AUTO_NEG_FOR_DUPLX 0
+#define EGIGA_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
+#define EGIGA_EN_AUTO_NEG_FOR_FLOW_CTRL 0
+#define EGIGA_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
+#define EGIGA_ADV_NO_FLOW_CTRL 0
+#define EGIGA_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
+#define EGIGA_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
+#define EGIGA_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
+#define EGIGA_FORCE_BP_MODE_NO_JAM 0
+#define EGIGA_FORCE_BP_MODE_JAM_TX (1 << 7)
+#define EGIGA_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
+#define EGIGA_FORCE_LINK_FAIL 0
+#define EGIGA_DO_NOT_FORCE_LINK_FAIL (1 << 10)
+#define EGIGA_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
+#define EGIGA_EN_AUTO_NEG_SPEED_GMII 0
+#define EGIGA_DTE_ADV_0 0
+#define EGIGA_DTE_ADV_1 (1 << 14)
+#define EGIGA_MIIPHY_MAC_MODE 0
+#define EGIGA_MIIPHY_PHY_MODE (1 << 15)
+#define EGIGA_AUTO_NEG_NO_CHANGE 0
+#define EGIGA_RESTART_AUTO_NEG (1 << 16)
+#define EGIGA_MAX_RX_PACKET_1518BYTE 0
+#define EGIGA_MAX_RX_PACKET_1522BYTE (1 << 17)
+#define EGIGA_MAX_RX_PACKET_1552BYTE (1 << 18)
+#define EGIGA_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
+#define EGIGA_MAX_RX_PACKET_9192BYTE (1 << 19)
+#define EGIGA_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
+#define EGIGA_SET_EXT_LOOPBACK (1 << 20)
+#define EGIGA_CLR_EXT_LOOPBACK 0
+#define EGIGA_SET_FULL_DUPLEX_MODE (1 << 21)
+#define EGIGA_SET_HALF_DUPLEX_MODE 0
+#define EGIGA_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
+#define EGIGA_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+#define EGIGA_SET_GMII_SPEED_TO_10_100 0
+#define EGIGA_SET_GMII_SPEED_TO_1000 (1 << 23)
+#define EGIGA_SET_MII_SPEED_TO_10 0
+#define EGIGA_SET_MII_SPEED_TO_100 (1 << 24)
/* SMI register fields */
-#define KWGBE_PHY_SMI_TIMEOUT 10000
-#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */
-#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS)
-#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
-#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
-#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
-#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
-#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
-#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
+#define EGIGA_PHY_SMI_TIMEOUT 10000
+#define EGIGA_PHY_SMI_DATA_OFFS 0 /* Data */
+#define EGIGA_PHY_SMI_DATA_MASK (0xffff << EGIGA_PHY_SMI_DATA_OFFS)
+#define EGIGA_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
+#define EGIGA_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << EGIGA_PHY_SMI_DEV_ADDR_OFFS)
+#define EGIGA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
+#define EGIGA_SMI_REG_ADDR_MASK (PHYADR_MASK << EGIGA_SMI_REG_ADDR_OFFS)
+#define EGIGA_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
+#define EGIGA_PHY_SMI_OPCODE_MASK (3 << EGIGA_PHY_SMI_OPCODE_OFFS)
+#define EGIGA_PHY_SMI_OPCODE_WRITE (0 << EGIGA_PHY_SMI_OPCODE_OFFS)
+#define EGIGA_PHY_SMI_OPCODE_READ (1 << EGIGA_PHY_SMI_OPCODE_OFFS)
+#define EGIGA_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
+#define EGIGA_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
-#define KWGBE_ERROR_SUMMARY 1
+#define EGIGA_ERROR_SUMMARY 1
/* Tx & Rx descriptors command */
-#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31)
+#define EGIGA_BUFFER_OWNED_BY_DMA (1 << 31)
/* Tx descriptors status */
-#define KWGBE_LC_ERROR 0
-#define KWGBE_UR_ERROR (1 << 1)
-#define KWGBE_RL_ERROR (1 << 2)
-#define KWGBE_LLC_SNAP_FORMAT (1 << 9)
-#define KWGBE_TX_LAST_FRAME (1 << 20)
+#define EGIGA_LC_ERROR 0
+#define EGIGA_UR_ERROR (1 << 1)
+#define EGIGA_RL_ERROR (1 << 2)
+#define EGIGA_LLC_SNAP_FORMAT (1 << 9)
+#define EGIGA_TX_LAST_FRAME (1 << 20)
/* Rx descriptors status */
-#define KWGBE_CRC_ERROR 0
-#define KWGBE_OVERRUN_ERROR (1 << 1)
-#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
-#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
-#define KWGBE_VLAN_TAGGED (1 << 19)
-#define KWGBE_BPDU_FRAME (1 << 20)
-#define KWGBE_TCP_FRAME_OVER_IP_V_4 0
-#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
-#define KWGBE_OTHER_FRAME_TYPE (1 << 22)
-#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23)
-#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24)
-#define KWGBE_FRAME_HEADER_OK (1 << 25)
-#define KWGBE_RX_LAST_DESC (1 << 26)
-#define KWGBE_RX_FIRST_DESC (1 << 27)
-#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
-#define KWGBE_RX_EN_INTERRUPT (1 << 29)
-#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30)
+#define EGIGA_CRC_ERROR 0
+#define EGIGA_OVERRUN_ERROR (1 << 1)
+#define EGIGA_MAX_FRAME_LENGTH_ERROR (1 << 2)
+#define EGIGA_RESOURCE_ERROR ((1 << 2) | (1 << 1))
+#define EGIGA_VLAN_TAGGED (1 << 19)
+#define EGIGA_BPDU_FRAME (1 << 20)
+#define EGIGA_TCP_FRAME_OVER_IP_V_4 0
+#define EGIGA_UDP_FRAME_OVER_IP_V_4 (1 << 21)
+#define EGIGA_OTHER_FRAME_TYPE (1 << 22)
+#define EGIGA_LAYER_2_IS_EGIGA_V_2 (1 << 23)
+#define EGIGA_FRAME_TYPE_IP_V_4 (1 << 24)
+#define EGIGA_FRAME_HEADER_OK (1 << 25)
+#define EGIGA_RX_LAST_DESC (1 << 26)
+#define EGIGA_RX_FIRST_DESC (1 << 27)
+#define EGIGA_UNKNOWN_DESTINATION_ADDR (1 << 28)
+#define EGIGA_RX_EN_INTERRUPT (1 << 29)
+#define EGIGA_LAYER_4_CHECKSUM_OK (1 << 30)
/* Rx descriptors byte count */
-#define KWGBE_FRAME_FRAGMENTED (1 << 2)
+#define EGIGA_FRAME_FRAGMENTED (1 << 2)
/* Tx descriptors command */
-#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
-#define KWGBE_FRAME_SET_TO_VLAN (1 << 15)
-#define KWGBE_TCP_FRAME 0
-#define KWGBE_UDP_FRAME (1 << 16)
-#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
-#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
-#define KWGBE_ZERO_PADDING (1 << 19)
-#define KWGBE_TX_LAST_DESC (1 << 20)
-#define KWGBE_TX_FIRST_DESC (1 << 21)
-#define KWGBE_GEN_CRC (1 << 22)
-#define KWGBE_TX_EN_INTERRUPT (1 << 23)
-#define KWGBE_AUTO_MODE (1 << 30)
+#define EGIGA_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
+#define EGIGA_FRAME_SET_TO_VLAN (1 << 15)
+#define EGIGA_TCP_FRAME 0
+#define EGIGA_UDP_FRAME (1 << 16)
+#define EGIGA_GEN_TCP_UDP_CHECKSUM (1 << 17)
+#define EGIGA_GEN_IP_V_4_CHECKSUM (1 << 18)
+#define EGIGA_ZERO_PADDING (1 << 19)
+#define EGIGA_TX_LAST_DESC (1 << 20)
+#define EGIGA_TX_FIRST_DESC (1 << 21)
+#define EGIGA_GEN_CRC (1 << 22)
+#define EGIGA_TX_EN_INTERRUPT (1 << 23)
+#define EGIGA_AUTO_MODE (1 << 30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
@@ -341,24 +341,24 @@
#define EWIN_ACCESS_FULL ((1 << 1) | 1)
/* structures represents Controller registers */
-struct kwgbe_barsz {
+struct egiga_barsz {
u32 bar;
u32 size;
};
-struct kwgbe_rxcdp {
- struct kwgbe_rxdesc *rxcdp;
+struct egiga_rxcdp {
+ struct egiga_rxdesc *rxcdp;
u32 rxcdp_pad[3];
};
-struct kwgbe_tqx {
+struct egiga_tqx {
u32 qxttbc;
u32 tqxtbc;
u32 tqxac;
u32 tqxpad;
};
-struct kwgbe_registers {
+struct egiga_registers {
u32 phyadr;
u32 smi;
u32 euda;
@@ -372,7 +372,7 @@ struct kwgbe_registers {
u8 pad3[0x0b0 - 0x098 - 4];
u32 euc;
u8 pad3a[0x200 - 0x0b0 - 4];
- struct kwgbe_barsz barsz[6];
+ struct egiga_barsz barsz[6];
u8 pad4[0x280 - 0x22c - 4];
u32 ha_remap[4];
u32 bare;
@@ -417,14 +417,14 @@ struct kwgbe_registers {
u32 pmtu;
u32 pmtbs;
u8 pad14[0x60c - 0x4ec - 4];
- struct kwgbe_rxcdp rxcdp[7];
- struct kwgbe_rxdesc *rxcdp7;
+ struct egiga_rxcdp rxcdp[7];
+ struct egiga_rxdesc *rxcdp7;
u32 rqc;
- struct kwgbe_txdesc *tcsdp;
+ struct egiga_txdesc *tcsdp;
u8 pad15[0x6c0 - 0x684 - 4];
- struct kwgbe_txdesc *tcqdp[8];
+ struct egiga_txdesc *tcqdp[8];
u8 pad16[0x700 - 0x6dc - 4];
- struct kwgbe_tqx tqx[8];
+ struct egiga_tqx tqx[8];
u32 pttbc;
u8 pad17[0x7a8 - 0x780 - 4];
u32 tqxipg0;
@@ -447,26 +447,26 @@ struct kwgbe_registers {
};
/* structures/enums needed by driver */
-enum kwgbe_adrwin {
- KWGBE_WIN0,
- KWGBE_WIN1,
- KWGBE_WIN2,
- KWGBE_WIN3,
- KWGBE_WIN4,
- KWGBE_WIN5
+enum egiga_adrwin {
+ EGIGA_WIN0,
+ EGIGA_WIN1,
+ EGIGA_WIN2,
+ EGIGA_WIN3,
+ EGIGA_WIN4,
+ EGIGA_WIN5
};
-enum kwgbe_target {
- KWGBE_TARGET_DRAM,
- KWGBE_TARGET_DEV,
- KWGBE_TARGET_CBS,
- KWGBE_TARGET_PCI0,
- KWGBE_TARGET_PCI1
+enum egiga_target {
+ EGIGA_TARGET_DRAM,
+ EGIGA_TARGET_DEV,
+ EGIGA_TARGET_CBS,
+ EGIGA_TARGET_PCI0,
+ EGIGA_TARGET_PCI1
};
-struct kwgbe_winparam {
- enum kwgbe_adrwin win; /* Window number */
- enum kwgbe_target target; /* System targets */
+struct egiga_winparam {
+ enum egiga_adrwin win; /* Window number */
+ enum egiga_target target; /* System targets */
u16 attrib; /* BAR attrib. See above macros */
u32 base_addr; /* Window base address in u32 form */
u32 high_addr; /* Window high address in u32 form */
@@ -475,29 +475,29 @@ struct kwgbe_winparam {
u16 access_ctrl; /*Access ctrl register. see above macros */
};
-struct kwgbe_rxdesc {
+struct egiga_rxdesc {
u32 cmd_sts; /* Descriptor command status */
u16 buf_size; /* Buffer size */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer pointer */
- struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
+ struct egiga_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
-struct kwgbe_txdesc {
+struct egiga_txdesc {
u32 cmd_sts; /* Descriptor command status */
u16 l4i_chk; /* CPU provided TCP Checksum */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer ptr */
- struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
+ struct egiga_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
-struct kwgbe_device {
+struct egiga_device {
struct eth_device dev;
- struct kwgbe_registers *regs;
- struct kwgbe_txdesc *p_txdesc;
- struct kwgbe_rxdesc *p_rxdesc;
- struct kwgbe_rxdesc *p_rxdesc_curr;
+ struct egiga_registers *regs;
+ struct egiga_txdesc *p_txdesc;
+ struct egiga_rxdesc *p_rxdesc;
+ struct egiga_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
};
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 2fbc6ad..3015fc5 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -172,9 +172,9 @@
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_CMD_MII
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index a928c2c..489d34f 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -127,9 +127,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h
index 96b4d1c..951e66d 100644
--- a/include/configs/mv88f6281gtw_ge.h
+++ b/include/configs/mv88f6281gtw_ge.h
@@ -172,9 +172,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif /* CONFIG_CMD_NET */
diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h
index d2f4502..540ee83 100644
--- a/include/configs/openrd_base.h
+++ b/include/configs/openrd_base.h
@@ -183,9 +183,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0x8
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
index 3d8e25c..10882a6 100644
--- a/include/configs/rd6281a.h
+++ b/include/configs/rd6281a.h
@@ -171,8 +171,8 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index e9edc44..13b4708 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -174,9 +174,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_EGIGA /* Enable kirkwood Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
diff --git a/include/netdev.h b/include/netdev.h
index 882642a..c8c38c9 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -52,6 +52,7 @@ int davinci_emac_initialize(void);
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
int e1000_initialize(bd_t *bis);
int eepro100_initialize(bd_t *bis);
+int egiga_initialize(bd_t *bis);
int ep93xx_eth_initialize(u8 dev_num, int base_addr);
int ethoc_initialize(u8 dev_num, int base_addr);
int eth_3com_initialize (bd_t * bis);
@@ -61,7 +62,6 @@ int ftmac100_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
-int kirkwood_egiga_initialize(bd_t *bis);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
int mcdmafec_initialize(bd_t *bis);
--
1.6.4.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 4/4] egiga: add support for orion5x
2010-07-02 16:53 ` [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC Albert Aribaud
@ 2010-07-02 16:53 ` Albert Aribaud
2010-07-05 11:01 ` Prafulla Wadaskar
2010-07-05 11:02 ` [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC Prafulla Wadaskar
1 sibling, 1 reply; 18+ messages in thread
From: Albert Aribaud @ 2010-07-02 16:53 UTC (permalink / raw)
To: u-boot
Now that egiga is detached from kirkwood, we can add
support for orion5x. This requires making the structures
representing egiga registers and descriptors volatile,
otherwise writes to them happen in the wrong order --
this did not affect kirkwood but does affect orion5x.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
arch/arm/cpu/arm926ejs/orion5x/cpu.c | 18 +++
arch/arm/include/asm/arch-orion5x/orion5x.h | 5 +
board/LaCie/edminiv2/edminiv2.c | 36 +++++
board/LaCie/edminiv2/edminiv2.h | 41 ++++++
drivers/net/egiga.c | 4 +-
drivers/net/egiga.h | 198 +++++++++++++-------------
include/configs/edminiv2.h | 30 +++-
7 files changed, 225 insertions(+), 107 deletions(-)
create mode 100644 board/LaCie/edminiv2/edminiv2.h
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index 03c6d06..a468c4d 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -268,3 +268,21 @@ int arch_misc_init(void)
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_EGIGA
+int cpu_eth_init(bd_t *bis)
+{
+ egiga_initialize(bis);
+ return 0;
+}
+
+/*
+ * Generates a non-random hex number just to make egiga.c happy
+ * if a MAC address has to be generated
+ */
+unsigned char get_random_hex(void)
+{
+ static unsigned char seed = 0;
+ return seed++;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
index 4008c84..ffe26bd 100644
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -56,6 +56,11 @@
#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
+/* EGIGA expects EGIGA0 #define'd */
+#if defined (CONFIG_EGIGA)
+#define EGIGA0_BASE ORION5X_EGIGA_BASE
+#endif
+
#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
/* include here SoC variants. 5181, 5281, 6183 should go here when
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index 54c0ffe..d46ee4a 100644
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <miiphy.h>
#include <asm/arch/orion5x.h>
+#include "edminiv2.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -90,3 +91,38 @@ int board_init(void)
return 0;
}
+
+#if defined (CONFIG_CMD_NET) && defined (CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h
new file mode 100644
index 0000000..88e62b2
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_BASE_H
+#define __EDMINIV2_BASE_H
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __EDMINIV2_BASE_H */
diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
index bb0de68..320e2ca 100644
--- a/drivers/net/egiga.c
+++ b/drivers/net/egiga.c
@@ -37,6 +37,8 @@
#include <asm/byteorder.h>
#if defined (CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
+#elif defined CONFIG_ORION5X
+#include <asm/arch/orion5x.h>
#endif
#include "egiga.h"
@@ -273,7 +275,7 @@ static void set_dram_access(struct egiga_registers *regs)
win_param.attrib = EBAR_DRAM_CS3;
break;
default:
- /* invalide bank, disable access */
+ /* invalid bank, disable access */
win_param.enable = 0;
win_param.attrib = 0;
break;
diff --git a/drivers/net/egiga.h b/drivers/net/egiga.h
index f758d3c..89ac519 100644
--- a/drivers/net/egiga.h
+++ b/drivers/net/egiga.h
@@ -342,13 +342,13 @@
/* structures represents Controller registers */
struct egiga_barsz {
- u32 bar;
- u32 size;
+ volatile u32 bar;
+ volatile u32 size;
};
struct egiga_rxcdp {
- struct egiga_rxdesc *rxcdp;
- u32 rxcdp_pad[3];
+ volatile struct egiga_rxdesc *rxcdp;
+ volatile u32 rxcdp_pad[3];
};
struct egiga_tqx {
@@ -359,91 +359,91 @@ struct egiga_tqx {
};
struct egiga_registers {
- u32 phyadr;
- u32 smi;
- u32 euda;
- u32 eudid;
- u8 pad1[0x080 - 0x00c - 4];
- u32 euic;
- u32 euim;
- u8 pad2[0x094 - 0x084 - 4];
- u32 euea;
- u32 euiae;
- u8 pad3[0x0b0 - 0x098 - 4];
- u32 euc;
- u8 pad3a[0x200 - 0x0b0 - 4];
- struct egiga_barsz barsz[6];
- u8 pad4[0x280 - 0x22c - 4];
- u32 ha_remap[4];
- u32 bare;
- u32 epap;
- u8 pad5[0x400 - 0x294 - 4];
- u32 pxc;
- u32 pxcx;
- u32 mii_ser_params;
- u8 pad6[0x410 - 0x408 - 4];
- u32 evlane;
- u32 macal;
- u32 macah;
- u32 sdc;
- u32 dscp[7];
- u32 psc0;
- u32 vpt2p;
- u32 ps0;
- u32 tqc;
- u32 psc1;
- u32 ps1;
- u32 mrvl_header;
- u8 pad7[0x460 - 0x454 - 4];
- u32 ic;
- u32 ice;
- u32 pim;
- u32 peim;
- u8 pad8[0x474 - 0x46c - 4];
- u32 pxtfut;
- u32 pad9;
- u32 pxmfs;
- u32 pad10;
- u32 pxdfc;
- u32 pxofc;
- u8 pad11[0x494 - 0x488 - 4];
- u32 peuiae;
- u8 pad12[0x4bc - 0x494 - 4];
- u32 eth_type_prio;
- u8 pad13[0x4dc - 0x4bc - 4];
- u32 tqfpc;
- u32 pttbrc;
- u32 tqc1;
- u32 pmtu;
- u32 pmtbs;
- u8 pad14[0x60c - 0x4ec - 4];
- struct egiga_rxcdp rxcdp[7];
- struct egiga_rxdesc *rxcdp7;
- u32 rqc;
- struct egiga_txdesc *tcsdp;
- u8 pad15[0x6c0 - 0x684 - 4];
- struct egiga_txdesc *tcqdp[8];
- u8 pad16[0x700 - 0x6dc - 4];
- struct egiga_tqx tqx[8];
- u32 pttbc;
- u8 pad17[0x7a8 - 0x780 - 4];
- u32 tqxipg0;
- u32 pad18[3];
- u32 tqxipg1;
- u8 pad19[0x7c0 - 0x7b8 - 4];
- u32 hitkninlopkt;
- u32 hitkninasyncpkt;
- u32 lotkninasyncpkt;
- u32 pad20;
- u32 ts;
- u8 pad21[0x3000 - 0x27d0 - 4];
- u32 pad20_1[32]; /* mib counter registes */
- u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
- u32 dfsmt[64];
- u32 dfomt[64];
- u32 dfut[4];
- u8 pad23[0xe20c0 - 0x7360c - 4];
- u32 pmbus_top_arbiter;
+ volatile u32 phyadr;
+ volatile u32 smi;
+ volatile u32 euda;
+ volatile u32 eudid;
+ volatile u8 pad1[0x080 - 0x00c - 4];
+ volatile u32 euic;
+ volatile u32 euim;
+ volatile u8 pad2[0x094 - 0x084 - 4];
+ volatile u32 euea;
+ volatile u32 euiae;
+ volatile u8 pad3[0x0b0 - 0x098 - 4];
+ volatile u32 euc;
+ volatile u8 pad3a[0x200 - 0x0b0 - 4];
+ volatile struct egiga_barsz barsz[6];
+ volatile u8 pad4[0x280 - 0x22c - 4];
+ volatile u32 ha_remap[4];
+ volatile u32 bare;
+ volatile u32 epap;
+ volatile u8 pad5[0x400 - 0x294 - 4];
+ volatile u32 pxc;
+ volatile u32 pxcx;
+ volatile u32 mii_ser_params;
+ volatile u8 pad6[0x410 - 0x408 - 4];
+ volatile u32 evlane;
+ volatile u32 macal;
+ volatile u32 macah;
+ volatile u32 sdc;
+ volatile u32 dscp[7];
+ volatile u32 psc0;
+ volatile u32 vpt2p;
+ volatile u32 ps0;
+ volatile u32 tqc;
+ volatile u32 psc1;
+ volatile u32 ps1;
+ volatile u32 mrvl_header;
+ volatile u8 pad7[0x460 - 0x454 - 4];
+ volatile u32 ic;
+ volatile u32 ice;
+ volatile u32 pim;
+ volatile u32 peim;
+ volatile u8 pad8[0x474 - 0x46c - 4];
+ volatile u32 pxtfut;
+ volatile u32 pad9;
+ volatile u32 pxmfs;
+ volatile u32 pad10;
+ volatile u32 pxdfc;
+ volatile u32 pxofc;
+ volatile u8 pad11[0x494 - 0x488 - 4];
+ volatile u32 peuiae;
+ volatile u8 pad12[0x4bc - 0x494 - 4];
+ volatile u32 eth_type_prio;
+ volatile u8 pad13[0x4dc - 0x4bc - 4];
+ volatile u32 tqfpc;
+ volatile u32 pttbrc;
+ volatile u32 tqc1;
+ volatile u32 pmtu;
+ volatile u32 pmtbs;
+ volatile u8 pad14[0x60c - 0x4ec - 4];
+ volatile struct egiga_rxcdp rxcdp[7];
+ volatile struct egiga_rxdesc *rxcdp7;
+ volatile u32 rqc;
+ volatile struct egiga_txdesc *tcsdp;
+ volatile u8 pad15[0x6c0 - 0x684 - 4];
+ volatile struct egiga_txdesc *tcqdp[8];
+ volatile u8 pad16[0x700 - 0x6dc - 4];
+ volatile struct egiga_tqx tqx[8];
+ volatile u32 pttbc;
+ volatile u8 pad17[0x7a8 - 0x780 - 4];
+ volatile u32 tqxipg0;
+ volatile u32 pad18[3];
+ volatile u32 tqxipg1;
+ volatile u8 pad19[0x7c0 - 0x7b8 - 4];
+ volatile u32 hitkninlopkt;
+ volatile u32 hitkninasyncpkt;
+ volatile u32 lotkninasyncpkt;
+ volatile u32 pad20;
+ volatile u32 ts;
+ volatile u8 pad21[0x3000 - 0x27d0 - 4];
+ volatile u32 pad20_1[32]; /* mib counter registes */
+ volatile u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
+ volatile u32 dfsmt[64];
+ volatile u32 dfomt[64];
+ volatile u32 dfut[4];
+ volatile u8 pad23[0xe20c0 - 0x7360c - 4];
+ volatile u32 pmbus_top_arbiter;
};
/* structures/enums needed by driver */
@@ -476,19 +476,19 @@ struct egiga_winparam {
};
struct egiga_rxdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 buf_size; /* Buffer size */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer pointer */
- struct egiga_rxdesc *nxtdesc_p; /* Next descriptor pointer */
+ volatile u32 cmd_sts; /* Descriptor command status */
+ volatile u16 buf_size; /* Buffer size */
+ volatile u16 byte_cnt; /* Descriptor buffer byte count */
+ volatile u8 *buf_ptr; /* Descriptor buffer pointer */
+ volatile struct egiga_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
struct egiga_txdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 l4i_chk; /* CPU provided TCP Checksum */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer ptr */
- struct egiga_txdesc *nxtdesc_p; /* Next descriptor ptr */
+ volatile u32 cmd_sts; /* Descriptor command status */
+ volatile u16 l4i_chk; /* CPU provided TCP Checksum */
+ volatile u16 byte_cnt; /* Descriptor buffer byte count */
+ volatile u8 *buf_ptr; /* Descriptor buffer ptr */
+ volatile struct egiga_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index c3d95a0..1f75920 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -60,7 +60,7 @@
#define ORION5X_MPP0_7 0x00000003
#define ORION5X_MPP8_15 0x55550000
-#define ORION5X_MPP16_23 0x00000000
+#define ORION5X_MPP16_23 0x00005555
/*
* Board-specific values for Orion5x GPIO low level init:
@@ -110,6 +110,14 @@
#define CONFIG_SYS_FLASH_SECTSZ \
{16384, 8192, 8192, 32768, \
65536, 65536, 65536, 65536, 65536, 65536, 65536}
+/*
+ * Ethernet
+ */
+
+#define CONFIG_EGIGA /* Enable Egiga Gbe Controller Driver */
+#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0x8
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
@@ -131,12 +139,20 @@
* Commands configuration - using default command set for now
*/
#include <config_cmd_default.h>
-/*
- * Disabling some default commands for staggered bring-up
- */
-#undef CONFIG_CMD_BOOTD /* no bootd since no net */
-#undef CONFIG_CMD_NET /* no net since no eth */
-#undef CONFIG_CMD_NFS /* no NFS since no net */
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#endif
/*
* Environment variables configurations
--
1.6.4.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga
2010-07-02 16:53 ` [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Albert Aribaud
@ 2010-07-02 17:20 ` Ben Warren
2010-07-02 17:27 ` Albert ARIBAUD
2010-07-05 11:02 ` Prafulla Wadaskar
2 siblings, 1 reply; 18+ messages in thread
From: Ben Warren @ 2010-07-02 17:20 UTC (permalink / raw)
To: u-boot
Hi Albert,
On 7/2/2010 9:53 AM, Albert Aribaud wrote:
> The names of the egiga files mention kirkwood
> even though they are not kirkwood-specific - change them.
>
>
I'm not a git expert so there may be a better way than this, but we want
this to show up as a rename, rather than an add/delete. I would
accomplish this using 'git mv', followed by 'git format-patch -C'
regards,
Ben
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga
2010-07-02 17:20 ` [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga Ben Warren
@ 2010-07-02 17:27 ` Albert ARIBAUD
0 siblings, 0 replies; 18+ messages in thread
From: Albert ARIBAUD @ 2010-07-02 17:27 UTC (permalink / raw)
To: u-boot
Le 02/07/2010 19:20, Ben Warren a ?crit :
> Hi Albert,
>
> On 7/2/2010 9:53 AM, Albert Aribaud wrote:
>> The names of the egiga files mention kirkwood
>> even though they are not kirkwood-specific - change them.
>>
> I'm not a git expert so there may be a better way than this, but we want
> this to show up as a rename, rather than an add/delete. I would
> accomplish this using 'git mv', followed by 'git format-patch -C'
>
> regards,
> Ben
Thanks Ben -- I am no git expert as well, so I did not know about the -C
option. I will use it for subsequent patch versions.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 4/4] egiga: add support for orion5x
2010-07-02 16:53 ` [U-Boot] [PATCH 4/4] egiga: add support for orion5x Albert Aribaud
@ 2010-07-05 11:01 ` Prafulla Wadaskar
0 siblings, 0 replies; 18+ messages in thread
From: Prafulla Wadaskar @ 2010-07-05 11:01 UTC (permalink / raw)
To: u-boot
Prefer subject : Orion5X: add egiga driver support
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Friday, July 02, 2010 10:23 PM
> To: u-boot at lists.denx.de
> Subject: [U-Boot] [PATCH 4/4] egiga: add support for orion5x
>
> Now that egiga is detached from kirkwood, we can add
> support for orion5x. This requires making the structures
> representing egiga registers and descriptors volatile,
> otherwise writes to them happen in the wrong order --
> this did not affect kirkwood but does affect orion5x.
>
> Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
> ---
> arch/arm/cpu/arm926ejs/orion5x/cpu.c | 18 +++
> arch/arm/include/asm/arch-orion5x/orion5x.h | 5 +
> board/LaCie/edminiv2/edminiv2.c | 36 +++++
> board/LaCie/edminiv2/edminiv2.h | 41 ++++++
> drivers/net/egiga.c | 4 +-
> drivers/net/egiga.h | 198
> +++++++++++++-------------
> include/configs/edminiv2.h | 30 +++-
> 7 files changed, 225 insertions(+), 107 deletions(-)
> create mode 100644 board/LaCie/edminiv2/edminiv2.h
>
> diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
> b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
> index 03c6d06..a468c4d 100644
> --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
> +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
> @@ -268,3 +268,21 @@ int arch_misc_init(void)
> return 0;
> }
> #endif /* CONFIG_ARCH_MISC_INIT */
> +
> +#ifdef CONFIG_EGIGA
> +int cpu_eth_init(bd_t *bis)
> +{
> + egiga_initialize(bis);
> + return 0;
> +}
> +
> +/*
> + * Generates a non-random hex number just to make egiga.c happy
Do not make anybody happy
This is misleading for generic code,
instead you can eliminate this support under CONFIG_SYS_GEN_RANDOM_MAC macro
> + * if a MAC address has to be generated
> + */
> +unsigned char get_random_hex(void)
> +{
> + static unsigned char seed = 0;
> + return seed++;
> +}
> +#endif
> diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h
> b/arch/arm/include/asm/arch-orion5x/orion5x.h
> index 4008c84..ffe26bd 100644
> --- a/arch/arm/include/asm/arch-orion5x/orion5x.h
> +++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
> @@ -56,6 +56,11 @@
> #define ORION5X_USB20_PORT1_BASE
> (ORION5X_REGISTER(0xA0000))
> #define ORION5X_EGIGA_BASE
> (ORION5X_REGISTER(0x72000))
>
> +/* EGIGA expects EGIGA0 #define'd */
> +#if defined (CONFIG_EGIGA)
> +#define EGIGA0_BASE ORION5X_EGIGA_BASE
> +#endif
> +
> #define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
>
> /* include here SoC variants. 5181, 5281, 6183 should go here when
> diff --git a/board/LaCie/edminiv2/edminiv2.c
> b/board/LaCie/edminiv2/edminiv2.c
> index 54c0ffe..d46ee4a 100644
> --- a/board/LaCie/edminiv2/edminiv2.c
> +++ b/board/LaCie/edminiv2/edminiv2.c
> @@ -27,6 +27,7 @@
> #include <common.h>
> #include <miiphy.h>
> #include <asm/arch/orion5x.h>
> +#include "edminiv2.h"
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -90,3 +91,38 @@ int board_init(void)
>
> return 0;
> }
Its better if you abstract reset_phy out from here, it is irreverent to patch subject.
secondly it should go as patch for board support (will be picked by different custodians)
> +
> +#if defined (CONFIG_CMD_NET) && defined (CONFIG_RESET_PHY_R)
> +/* Configure and enable MV88E1116 PHY */
> +void reset_phy(void)
> +{
> + u16 reg;
> + u16 devadr;
> + char *name = "egiga0";
> +
> + if (miiphy_set_current_dev(name))
> + return;
> +
> + /* command to read PHY dev address */
> + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
> + printf("Err..%s could not read PHY dev address\n",
> + __FUNCTION__);
> + return;
> + }
> +
> + /*
> + * Enable RGMII delay on Tx and Rx for CPU port
> + * Ref: sec 4.7.2 of chip datasheet
> + */
> + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
> + miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
> + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
> + miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
> + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
> +
> + /* reset the phy */
> + miiphy_reset(name, devadr);
> +
> + printf("88E1116 Initialized on %s\n", name);
> +}
> +#endif /* CONFIG_RESET_PHY_R */
> diff --git a/board/LaCie/edminiv2/edminiv2.h
> b/board/LaCie/edminiv2/edminiv2.h
> new file mode 100644
> index 0000000..88e62b2
> --- /dev/null
> +++ b/board/LaCie/edminiv2/edminiv2.h
> @@ -0,0 +1,41 @@
> +/*
> + * (C) Copyright 2009
> + * Net Insight <www.netinsight.net>
> + * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
> + *
> + * Based on sheevaplug.h:
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef __EDMINIV2_BASE_H
> +#define __EDMINIV2_BASE_H
> +
> +/* PHY related */
> +#define MV88E1116_LED_FCTRL_REG 10
> +#define MV88E1116_CPRSP_CR3_REG 21
> +#define MV88E1116_MAC_CTRL_REG 21
> +#define MV88E1116_PGADR_REG 22
> +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
> +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
> +
> +#endif /* __EDMINIV2_BASE_H */
> diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
> index bb0de68..320e2ca 100644
> --- a/drivers/net/egiga.c
> +++ b/drivers/net/egiga.c
> @@ -37,6 +37,8 @@
> #include <asm/byteorder.h>
> #if defined (CONFIG_KIRKWOOD)
> #include <asm/arch/kirkwood.h>
> +#elif defined CONFIG_ORION5X
> +#include <asm/arch/orion5x.h>
> #endif
> #include "egiga.h"
>
> @@ -273,7 +275,7 @@ static void set_dram_access(struct
> egiga_registers *regs)
> win_param.attrib = EBAR_DRAM_CS3;
> break;
> default:
> - /* invalide bank, disable access */
> + /* invalid bank, disable access */
do not mix this, make this change as part of patch 1/4
> win_param.enable = 0;
> win_param.attrib = 0;
> break;
> diff --git a/drivers/net/egiga.h b/drivers/net/egiga.h
> index f758d3c..89ac519 100644
> --- a/drivers/net/egiga.h
> +++ b/drivers/net/egiga.h
> @@ -342,13 +342,13 @@
>
> /* structures represents Controller registers */
> struct egiga_barsz {
> - u32 bar;
> - u32 size;
> + volatile u32 bar;
> + volatile u32 size;
As you said in 0/4,
abstract volatile change as separate patch, this can be on the last patch in series.
Since most of the places registers are accessed through volatile pointers,
may be for DMA programming it is missing somewhere,
this need to be debugged instead of making volatile everywhere.
...snip...
> /* port device data struct */
> diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
> index c3d95a0..1f75920 100644
> --- a/include/configs/edminiv2.h
> +++ b/include/configs/edminiv2.h
> @@ -60,7 +60,7 @@
>
> #define ORION5X_MPP0_7 0x00000003
> #define ORION5X_MPP8_15 0x55550000
> -#define ORION5X_MPP16_23 0x00000000
> +#define ORION5X_MPP16_23 0x00005555
>
> /*
> * Board-specific values for Orion5x GPIO low level init:
> @@ -110,6 +110,14 @@
> #define CONFIG_SYS_FLASH_SECTSZ \
> {16384, 8192, 8192, 32768, \
> 65536, 65536, 65536, 65536, 65536, 65536, 65536}
> +/*
> + * Ethernet
> + */
> +
> +#define CONFIG_EGIGA /* Enable Egiga Gbe Controller Driver */
> +#define CONFIG_EGIGA_PORTS {1,0} /* enable port 0 only */
> +#define CONFIG_PHY_BASE_ADR 0x8
> +#define CONFIG_RESET_PHY_R /* use reset_phy() to init
> mv8831116 PHY */
Please move these definitions below inside #ifdef CONFIG_CMD_NET
>
> /* auto boot */
> #define CONFIG_BOOTDELAY 3 /* default enable autoboot */
> @@ -131,12 +139,20 @@
> * Commands configuration - using default command set for now
> */
> #include <config_cmd_default.h>
> -/*
> - * Disabling some default commands for staggered bring-up
> - */
> -#undef CONFIG_CMD_BOOTD /* no bootd since no net */
> -#undef CONFIG_CMD_NET /* no net since no eth */
> -#undef CONFIG_CMD_NFS /* no NFS since no net */
> +#define CONFIG_CMD_AUTOSCRIPT
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_ENV
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_PING
These are irrelevant to the patch subject, post separate patch for this
also check sheevaplug.h for making use of config_cmd_default.h (if not used)
> +
> +#ifdef CONFIG_CMD_NET
> +#define CONFIG_NETCONSOLE /* include NetConsole support */
> +#define CONFIG_NET_MULTI /* specify more that one ports
> available */
> +#define CONFIG_MII /* expose smi ove
> miiphy interface */
> +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link
> using phy */
> +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
> +#define CONFIG_EGIGA_INIT /* Enable GbePort0/1 for kernel */
> +#endif
regards..
Prafulla . .
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga
2010-07-02 16:53 ` [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Albert Aribaud
2010-07-02 17:20 ` [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga Ben Warren
@ 2010-07-05 11:02 ` Prafulla Wadaskar
2010-07-05 11:36 ` Albert ARIBAUD
2 siblings, 1 reply; 18+ messages in thread
From: Prafulla Wadaskar @ 2010-07-05 11:02 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Friday, July 02, 2010 10:23 PM
> To: u-boot at lists.denx.de
> Subject: [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga
> driver to egiga
>
> The names of the egiga files mention kirkwood
> even though they are not kirkwood-specific - change them.
>
> Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
> ---
> drivers/net/Makefile | 2 +-
> drivers/net/egiga.c | 719
> ++++++++++++++++++++++++++++++++++++++++++
> drivers/net/egiga.h | 505 +++++++++++++++++++++++++++++
> drivers/net/kirkwood_egiga.c | 719
> ------------------------------------------
> drivers/net/kirkwood_egiga.h | 505 -----------------------------
> 5 files changed, 1225 insertions(+), 1225 deletions(-)
> create mode 100644 drivers/net/egiga.c
> create mode 100644 drivers/net/egiga.h
if it is generic gigabit Ethernet driver abstraction, could be applicable to any kind of SOC then the same egiga is relevant. which is not the case here
if it is Marvell specific then the name should be like- mv_egiga
I think we should sync on the arch first, that would same lot of coding/review efforts
I have below mentioned architecture for this driver -
1. Abstract generic SoC independent driver skeleton into mv"_egiga.c/h
2. Abstract and put Kirkwood specific functions is arch/arm/cpu/kirkwood/egiga.c
3. Create and put Orion specific functions is arch/arm/cpu/orion5x/egiga.c
4. Use common APIs/Macros to call SoC specific functions in generic driver
5. same strategy should be applied for header files abstraction.
> delete mode 100644 drivers/net/kirkwood_egiga.c
> delete mode 100644 drivers/net/kirkwood_egiga.h
>
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index b75c02f..8853908 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -46,7 +46,7 @@ COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
> COBJS-$(CONFIG_FTMAC100) += ftmac100.o
> COBJS-$(CONFIG_GRETH) += greth.o
> COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
> -COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
> +COBJS-$(CONFIG_KIRKWOOD_EGIGA) += egiga.o
there should be generic CONFIG to address this build, and CONFIG_KIRKWOOD_EGIGA should address its SOC specific dependency, you have done this in patch 3/4
> COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
> COBJS-$(CONFIG_LAN91C96) += lan91c96.o
> COBJS-$(CONFIG_MACB) += macb.o
> diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
As suggested by Ben rest should be rename activity than delete/add for 1/x patch
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC
2010-07-02 16:53 ` [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 4/4] egiga: add support for orion5x Albert Aribaud
@ 2010-07-05 11:02 ` Prafulla Wadaskar
2010-07-05 11:41 ` Albert ARIBAUD
1 sibling, 1 reply; 18+ messages in thread
From: Prafulla Wadaskar @ 2010-07-05 11:02 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Friday, July 02, 2010 10:23 PM
> To: u-boot at lists.denx.de
> Subject: [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC
>
> Macros, types, variables, functions in egiga
> refer to kirkwood even though they are not
> kirkwood-specific. Rename them, across the
> whole source tree when necessary.
NAK, as commented for Patch 1/4
you can address it more like splitting a driver into generic and specific interfaces
and then adding new support
Regards..
Prafulla ..
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood
2010-07-02 16:53 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC Albert Aribaud
@ 2010-07-05 11:03 ` Prafulla Wadaskar
2010-07-05 17:59 ` Albert ARIBAUD
1 sibling, 1 reply; 18+ messages in thread
From: Prafulla Wadaskar @ 2010-07-05 11:03 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Friday, July 02, 2010 10:23 PM
> To: u-boot at lists.denx.de
> Subject: [U-Boot] [PATCH 2/4] egiga: Remove functional
> dependency on kirkwood
>
> Set DRAM windows by using gd as other drivers do,
> instead of calling kirkwood-specific functions.
>
> Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
> ---
> drivers/net/egiga.c | 6 ++++--
> 1 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
> index 50e8ff3..cbe4748 100644
> --- a/drivers/net/egiga.c
> +++ b/drivers/net/egiga.c
> @@ -38,6 +38,8 @@
> #include <asm/arch/kirkwood.h>
> #include "egiga.h"
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> #define KIRKWOOD_PHY_ADR_REQUEST 0xee
> #define KWGBE_SMI_REG (((struct kwgbe_registers
> *)KW_EGIGA0_BASE)->smi)
>
> @@ -246,8 +248,8 @@ static void set_dram_access(struct
> kwgbe_registers *regs)
> win_param.access_ctrl = EWIN_ACCESS_FULL;
> win_param.high_addr = 0;
> /* Get bank base */
> - win_param.base_addr = kw_sdram_bar(i);
> - win_param.size = kw_sdram_bs(i); /* Get
> bank size */
> + win_param.base_addr = gd->bd->bi_dram[i].start;
> + win_param.size = gd->bd->bi_dram[i].size;
> if (win_param.size == 0)
> win_param.enable = 0;
> else
this is good patch indeed to make the driver more generic, which is independent of this activity
please post this patch for current version i.e. kirkwood_egiga.c
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga
2010-07-05 11:02 ` Prafulla Wadaskar
@ 2010-07-05 11:36 ` Albert ARIBAUD
2010-07-05 12:01 ` Prafulla Wadaskar
0 siblings, 1 reply; 18+ messages in thread
From: Albert ARIBAUD @ 2010-07-05 11:36 UTC (permalink / raw)
To: u-boot
Le 05/07/2010 13:02, Prafulla Wadaskar a ?crit :
> if it is generic gigabit Ethernet driver abstraction, could be applicable to any kind of SOC then the same egiga is relevant. which is not the case here
> if it is Marvell specific then the name should be like- mv_egiga
As it is Marvell-IP specific, I'll rename it to mv_egiga.
> I think we should sync on the arch first, that would same lot of coding/review efforts
> I have below mentioned architecture for this driver -
> 1. Abstract generic SoC independent driver skeleton into mv"_egiga.c/h
> 2. Abstract and put Kirkwood specific functions is arch/arm/cpu/kirkwood/egiga.c
> 3. Create and put Orion specific functions is arch/arm/cpu/orion5x/egiga.c
> 4. Use common APIs/Macros to call SoC specific functions in generic driver
> 5. same strategy should be applied for header files abstraction.
Agree.
> there should be generic CONFIG to address this build, and CONFIG_KIRKWOOD_EGIGA
> should address its SOC specific dependency, you have done this in patch 3/4
Yes, I have. Do you mean you would prefer everything--file renaming,
symbol renaming--in a single commit?
> As suggested by Ben rest should be rename activity than delete/add for 1/x patch
Ok.
Thanks for the feedback. I'll provide an updated patchset once I get
your answer to my question above.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC
2010-07-05 11:02 ` [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC Prafulla Wadaskar
@ 2010-07-05 11:41 ` Albert ARIBAUD
2010-07-05 12:02 ` Prafulla Wadaskar
0 siblings, 1 reply; 18+ messages in thread
From: Albert ARIBAUD @ 2010-07-05 11:41 UTC (permalink / raw)
To: u-boot
Le 05/07/2010 13:02, Prafulla Wadaskar a ?crit :
>> -----Original Message-----
>> From: u-boot-bounces at lists.denx.de
>> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
>> Sent: Friday, July 02, 2010 10:23 PM
>> To: u-boot at lists.denx.de
>> Subject: [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC
>>
>> Macros, types, variables, functions in egiga
>> refer to kirkwood even though they are not
>> kirkwood-specific. Rename them, across the
>> whole source tree when necessary.
>
> NAK, as commented for Patch 1/4
> you can address it more like splitting a driver into generic and specific interfaces
> and then adding new support
I'm not sure I get your meaning here. Do you suggest I submit not four
but only two patches, one with all egiga-out-of-kirkwood changes and one
with orion5x support? Or is is something else entirely?
> Regards..
> Prafulla ..
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga
2010-07-05 11:36 ` Albert ARIBAUD
@ 2010-07-05 12:01 ` Prafulla Wadaskar
2010-07-05 13:15 ` Albert ARIBAUD
0 siblings, 1 reply; 18+ messages in thread
From: Prafulla Wadaskar @ 2010-07-05 12:01 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Monday, July 05, 2010 5:06 PM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga
> driver to egiga
>
> Le 05/07/2010 13:02, Prafulla Wadaskar a ?crit :
>
> > if it is generic gigabit Ethernet driver abstraction, could
> be applicable to any kind of SOC then the same egiga is
> relevant. which is not the case here
> > if it is Marvell specific then the name should be like- mv_egiga
>
> As it is Marvell-IP specific, I'll rename it to mv_egiga.
>
> > I think we should sync on the arch first, that would same
> lot of coding/review efforts
> > I have below mentioned architecture for this driver -
> > 1. Abstract generic SoC independent driver skeleton into
> mv"_egiga.c/h
> > 2. Abstract and put Kirkwood specific functions is
> arch/arm/cpu/kirkwood/egiga.c
> > 3. Create and put Orion specific functions is
> arch/arm/cpu/orion5x/egiga.c
> > 4. Use common APIs/Macros to call SoC specific functions in
> generic driver
> > 5. same strategy should be applied for header files abstraction.
>
> Agree.
>
> > there should be generic CONFIG to address this build, and
> CONFIG_KIRKWOOD_EGIGA
> > should address its SOC specific dependency, you have done
> this in patch 3/4
>
> Yes, I have. Do you mean you would prefer everything--file renaming,
> symbol renaming--in a single commit?
Ideally, patch should be small as per functionality and objective,
that gives better understanding even for someone who is not directly related.
also it is easier to be get accepted acked faster.
I feel you should create a patches as below:
standalone patches
1. kirkwood_egiga: Updates: using global data ptr for DRAM configuration and cosmetic fix
2. edbiniv2: board configuration cleanup and enhancements
patch series:
1. [1/5] net: rename: kirkwood_egiga as mv_egiga
2. [2/5] net: mv_egiga: Split SoC specific (Kirkwood) code to support other SoCs
3. [3/5] net: mv_egiga: add support for orion5x gigabit Ethernet controller
5. [4/5] net" mv_egiga: bugfix: DMA issued fixed using volatile
5. [5/5] edminiv2: add Ethernet support
Regards..
Prafulla. .
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC
2010-07-05 11:41 ` Albert ARIBAUD
@ 2010-07-05 12:02 ` Prafulla Wadaskar
0 siblings, 0 replies; 18+ messages in thread
From: Prafulla Wadaskar @ 2010-07-05 12:02 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Monday, July 05, 2010 5:12 PM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 3/4] egiga: remove references to
> kirkwood SoC
>
> Le 05/07/2010 13:02, Prafulla Wadaskar a ?crit :
>
> >> -----Original Message-----
> >> From: u-boot-bounces at lists.denx.de
> >> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> >> Sent: Friday, July 02, 2010 10:23 PM
> >> To: u-boot at lists.denx.de
> >> Subject: [U-Boot] [PATCH 3/4] egiga: remove references to
> kirkwood SoC
> >>
> >> Macros, types, variables, functions in egiga
> >> refer to kirkwood even though they are not
> >> kirkwood-specific. Rename them, across the
> >> whole source tree when necessary.
> >
> > NAK, as commented for Patch 1/4
> > you can address it more like splitting a driver into
> generic and specific interfaces
> > and then adding new support
>
> I'm not sure I get your meaning here. Do you suggest I submit
> not four
> but only two patches, one with all egiga-out-of-kirkwood
> changes and one
> with orion5x support? Or is is something else entirely?
I have clarified it in earlier email, hope it is clear now
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga
2010-07-05 12:01 ` Prafulla Wadaskar
@ 2010-07-05 13:15 ` Albert ARIBAUD
0 siblings, 0 replies; 18+ messages in thread
From: Albert ARIBAUD @ 2010-07-05 13:15 UTC (permalink / raw)
To: u-boot
Le 05/07/2010 14:01, Prafulla Wadaskar a ?crit :
> I feel you should create a patches as below:
>
> standalone patches
> 1. kirkwood_egiga: Updates: using global data ptr for DRAM configuration and cosmetic fix
> 2. edbiniv2: board configuration cleanup and enhancements
>
> patch series:
> 1. [1/5] net: rename: kirkwood_egiga as mv_egiga
> 2. [2/5] net: mv_egiga: Split SoC specific (Kirkwood) code to support other SoCs
> 3. [3/5] net: mv_egiga: add support for orion5x gigabit Ethernet controller
> 5. [4/5] net" mv_egiga: bugfix: DMA issued fixed using volatile
> 5. [5/5] edminiv2: add Ethernet support
Ok--I'll re-post the independent patches and patch series as suggested
later today.
Thanks for the guidance!
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood
2010-07-05 11:03 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Prafulla Wadaskar
@ 2010-07-05 17:59 ` Albert ARIBAUD
2010-07-05 19:54 ` Prafulla Wadaskar
0 siblings, 1 reply; 18+ messages in thread
From: Albert ARIBAUD @ 2010-07-05 17:59 UTC (permalink / raw)
To: u-boot
Le 05/07/2010 13:03, Prafulla Wadaskar a ?crit :
>
>> -----Original Message-----
>> From: u-boot-bounces at lists.denx.de
>> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
>> Sent: Friday, July 02, 2010 10:23 PM
>> To: u-boot at lists.denx.de
>> Subject: [U-Boot] [PATCH 2/4] egiga: Remove functional
>> dependency on kirkwood
>>
>> Set DRAM windows by using gd as other drivers do,
>> instead of calling kirkwood-specific functions.
>>
>> Signed-off-by: Albert Aribaud<albert.aribaud@free.fr>
>> ---
>> drivers/net/egiga.c | 6 ++++--
>> 1 files changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
>> index 50e8ff3..cbe4748 100644
>> --- a/drivers/net/egiga.c
>> +++ b/drivers/net/egiga.c
>> @@ -38,6 +38,8 @@
>> #include<asm/arch/kirkwood.h>
>> #include "egiga.h"
>>
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> #define KIRKWOOD_PHY_ADR_REQUEST 0xee
>> #define KWGBE_SMI_REG (((struct kwgbe_registers
>> *)KW_EGIGA0_BASE)->smi)
>>
>> @@ -246,8 +248,8 @@ static void set_dram_access(struct
>> kwgbe_registers *regs)
>> win_param.access_ctrl = EWIN_ACCESS_FULL;
>> win_param.high_addr = 0;
>> /* Get bank base */
>> - win_param.base_addr = kw_sdram_bar(i);
>> - win_param.size = kw_sdram_bs(i); /* Get
>> bank size */
>> + win_param.base_addr = gd->bd->bi_dram[i].start;
>> + win_param.size = gd->bd->bi_dram[i].size;
>> if (win_param.size == 0)
>> win_param.enable = 0;
>> else
>
> this is good patch indeed to make the driver more generic, which is independent of this activity
> please post this patch for current version i.e. kirkwood_egiga.c
>
> Regards..
> Prafulla . .
There is also a similar fix (move from kw_sdram_{bar,bs} to gd) to be
done on drivers/usb/host/ehci-kirkwood.c, apparently. As I wasn't
planning supporting USB with this patchset, I'd ignored it, but if you
want I can submit a separate patch for it too.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 18+ messages in thread
* [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood
2010-07-05 17:59 ` Albert ARIBAUD
@ 2010-07-05 19:54 ` Prafulla Wadaskar
0 siblings, 0 replies; 18+ messages in thread
From: Prafulla Wadaskar @ 2010-07-05 19:54 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Monday, July 05, 2010 11:30 PM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de
> Subject: Re: [PATCH 2/4] egiga: Remove functional dependency
> on kirkwood
>
> Le 05/07/2010 13:03, Prafulla Wadaskar a ?crit :
> >
> >> -----Original Message-----
> >> From: u-boot-bounces at lists.denx.de
> >> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> >> Sent: Friday, July 02, 2010 10:23 PM
> >> To: u-boot at lists.denx.de
> >> Subject: [U-Boot] [PATCH 2/4] egiga: Remove functional
> >> dependency on kirkwood
> >>
> >> Set DRAM windows by using gd as other drivers do,
> >> instead of calling kirkwood-specific functions.
> >>
> >> Signed-off-by: Albert Aribaud<albert.aribaud@free.fr>
> >> ---
> >> drivers/net/egiga.c | 6 ++++--
> >> 1 files changed, 4 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/net/egiga.c b/drivers/net/egiga.c
> >> index 50e8ff3..cbe4748 100644
> >> --- a/drivers/net/egiga.c
> >> +++ b/drivers/net/egiga.c
> >> @@ -38,6 +38,8 @@
> >> #include<asm/arch/kirkwood.h>
> >> #include "egiga.h"
> >>
> >> +DECLARE_GLOBAL_DATA_PTR;
> >> +
> >> #define KIRKWOOD_PHY_ADR_REQUEST 0xee
> >> #define KWGBE_SMI_REG (((struct kwgbe_registers
> >> *)KW_EGIGA0_BASE)->smi)
> >>
> >> @@ -246,8 +248,8 @@ static void set_dram_access(struct
> >> kwgbe_registers *regs)
> >> win_param.access_ctrl = EWIN_ACCESS_FULL;
> >> win_param.high_addr = 0;
> >> /* Get bank base */
> >> - win_param.base_addr = kw_sdram_bar(i);
> >> - win_param.size = kw_sdram_bs(i); /* Get
> >> bank size */
> >> + win_param.base_addr = gd->bd->bi_dram[i].start;
> >> + win_param.size = gd->bd->bi_dram[i].size;
> >> if (win_param.size == 0)
> >> win_param.enable = 0;
> >> else
> >
> > this is good patch indeed to make the driver more generic,
> which is independent of this activity
> > please post this patch for current version i.e. kirkwood_egiga.c
> >
> > Regards..
> > Prafulla . .
>
> There is also a similar fix (move from kw_sdram_{bar,bs} to gd) to be
> done on drivers/usb/host/ehci-kirkwood.c, apparently. As I wasn't
> planning supporting USB with this patchset, I'd ignored it,
> but if you
> want I can submit a separate patch for it too.
I know, I checked this, I was planning to post patches for the same, if you wish, you are welcomed !!!
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2010-07-05 19:54 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
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2010-07-02 16:53 [U-Boot] [PATCH 0/4] make egiga common to kirkwood and orion5x Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC Albert Aribaud
2010-07-02 16:53 ` [U-Boot] [PATCH 4/4] egiga: add support for orion5x Albert Aribaud
2010-07-05 11:01 ` Prafulla Wadaskar
2010-07-05 11:02 ` [U-Boot] [PATCH 3/4] egiga: remove references to kirkwood SoC Prafulla Wadaskar
2010-07-05 11:41 ` Albert ARIBAUD
2010-07-05 12:02 ` Prafulla Wadaskar
2010-07-05 11:03 ` [U-Boot] [PATCH 2/4] egiga: Remove functional dependency on kirkwood Prafulla Wadaskar
2010-07-05 17:59 ` Albert ARIBAUD
2010-07-05 19:54 ` Prafulla Wadaskar
2010-07-02 17:20 ` [U-Boot] [PATCH 1/4] ARM: Rename kirkwood_egiga driver to egiga Ben Warren
2010-07-02 17:27 ` Albert ARIBAUD
2010-07-05 11:02 ` Prafulla Wadaskar
2010-07-05 11:36 ` Albert ARIBAUD
2010-07-05 12:01 ` Prafulla Wadaskar
2010-07-05 13:15 ` Albert ARIBAUD
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