* [U-Boot] [PATCH V2 0/6] Marvell egiga multiple SoC support
@ 2010-07-09 6:34 Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga as mv_egiga Albert Aribaud
0 siblings, 1 reply; 17+ messages in thread
From: Albert Aribaud @ 2010-07-09 6:34 UTC (permalink / raw)
To: u-boot
NOTE
This patchset depends on the previously posted and Acked-by patch
"kirkwood_egiga: updates: fix DRAM mapping and typo", originally
part of V1 and available on the mailing list archives at
<http://lists.denx.de/pipermail/u-boot/2010-July/073590.html>.
PATCHSET HISTORY
V1: First submission.
V2: Reorganization as per Prafulla Wadasakar's suggestion.
Used -C in format-patch to render renames correctly.
Removal of DRAM patch posted standalone.
Removal of unrelated changes.
SHORT STORY
This patchset separates egiga from kirkwood then adds orion5x support
in egiga. It has been duly, and successfully, tested on an OpenRD-Client
after each of the four commits and on an EDMini V2 after the last commit.
LONG STORY
This is a set of six atomic commits.
the first commit renames kirkwood_egiga.[ch] to mv_egiga.[ch] in
drivers/net/ (also modifies Makefile) to make sur the renaming
remains visible in git at 100% similarity.
The second commit makes removes all dependency of mv_egiga on kirkwood.
Kirkwood references in all mv_egiga symbols are replaced with mv_egiga
references throughout the source tree.
The third commit adds the "volatile" qualifier to several mv_egiga
structures representing the controller registers and descriptors.
This is needed on orion5x, as without the volatile qualifiers, reads
and writes to these structs could happen in unexpected order; in
egiga_send() this caused the egiga DMA engine to get started before
the DMA TX descriptor was actually filled in, with the effect that
the actual sent packet was all zeroes. I cannot explain why this did
not happen on kirkwood, except that maybe the CPU speed difference made
it possible for the core to finish writing the descriptor before the DMA
engine could start.
The fourth commit limits the randomization of local MAC addresses to the
kirkwood SoC case, because not all SoCs have random number generation
(orion5x has not).
The fifth commit adds orion5x support to mv_egiga.
The sixth commit adds edminiv2 support for the orion5x egiga controller.
All commits were tested on a kirkwood-based OpenRD Client for regression
avoidance; the last commit was also tested on an orion5x-based ED Mini V2
for functionality validation.
Albert Aribaud (6):
net: rename: kirkwood_egiga as mv_egiga
mv_egiga: support SoCs other than kirkwood
mv_egiga: bugfix: DMA issue fixed using volatile
mv_egiga: only randomize MAC on kirkwood
mv_egiga: add support for orion5x egiga controller
edminiv2: add ethernet support
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 4 +-
arch/arm/cpu/arm926ejs/orion5x/cpu.c | 8 +
arch/arm/include/asm/arch-kirkwood/kirkwood.h | 5 +
arch/arm/include/asm/arch-orion5x/orion5x.h | 5 +
board/LaCie/edminiv2/edminiv2.c | 36 ++
board/LaCie/edminiv2/edminiv2.h | 41 ++
drivers/net/Makefile | 2 +-
drivers/net/kirkwood_egiga.h | 505 -------------------------
drivers/net/{kirkwood_egiga.c => mv_egiga.c} | 338 +++++++++--------
drivers/net/mv_egiga.h | 505 +++++++++++++++++++++++++
include/configs/edminiv2.h | 22 +-
include/configs/guruplug.h | 4 +-
include/configs/km_arm.h | 4 +-
include/configs/mv88f6281gtw_ge.h | 4 +-
include/configs/openrd_base.h | 4 +-
include/configs/rd6281a.h | 4 +-
include/configs/sheevaplug.h | 4 +-
include/netdev.h | 2 +-
18 files changed, 809 insertions(+), 688 deletions(-)
create mode 100644 board/LaCie/edminiv2/edminiv2.h
delete mode 100644 drivers/net/kirkwood_egiga.h
rename drivers/net/{kirkwood_egiga.c => mv_egiga.c} (60%)
create mode 100644 drivers/net/mv_egiga.h
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga as mv_egiga
2010-07-09 6:34 [U-Boot] [PATCH V2 0/6] Marvell egiga multiple SoC support Albert Aribaud
@ 2010-07-09 6:34 ` Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 2/6] mv_egiga: support SoCs other than kirkwood Albert Aribaud
2010-07-09 9:08 ` [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga as mv_egiga Prafulla Wadaskar
0 siblings, 2 replies; 17+ messages in thread
From: Albert Aribaud @ 2010-07-09 6:34 UTC (permalink / raw)
To: u-boot
This is the first of two changes aimed at separating the
Marvell egiga driver from the kirkwood SoC in order to
use it from other SoCs which implement it.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
drivers/net/Makefile | 2 +-
drivers/net/{kirkwood_egiga.c => mv_egiga.c} | 2 +-
drivers/net/{kirkwood_egiga.h => mv_egiga.h} | 0
3 files changed, 2 insertions(+), 2 deletions(-)
rename drivers/net/{kirkwood_egiga.c => mv_egiga.c} (99%)
rename drivers/net/{kirkwood_egiga.h => mv_egiga.h} (100%)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b75c02f..1599c26 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -46,13 +46,13 @@ COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
COBJS-$(CONFIG_FTMAC100) += ftmac100.o
COBJS-$(CONFIG_GRETH) += greth.o
COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
-COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
COBJS-$(CONFIG_LAN91C96) += lan91c96.o
COBJS-$(CONFIG_MACB) += macb.o
COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
+COBJS-$(CONFIG_KIRKWOOD_EGIGA) += mv_egiga.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/mv_egiga.c
similarity index 99%
rename from drivers/net/kirkwood_egiga.c
rename to drivers/net/mv_egiga.c
index b7374b5..e635414 100644
--- a/drivers/net/kirkwood_egiga.c
+++ b/drivers/net/mv_egiga.c
@@ -36,7 +36,7 @@
#include <asm/types.h>
#include <asm/byteorder.h>
#include <asm/arch/kirkwood.h>
-#include "kirkwood_egiga.h"
+#include "mv_egiga.h"
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/mv_egiga.h
similarity index 100%
rename from drivers/net/kirkwood_egiga.h
rename to drivers/net/mv_egiga.h
--
1.6.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 2/6] mv_egiga: support SoCs other than kirkwood
2010-07-09 6:34 ` [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga as mv_egiga Albert Aribaud
@ 2010-07-09 6:34 ` Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile Albert Aribaud
2010-07-09 9:08 ` [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga as mv_egiga Prafulla Wadaskar
1 sibling, 1 reply; 17+ messages in thread
From: Albert Aribaud @ 2010-07-09 6:34 UTC (permalink / raw)
To: u-boot
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
arch/arm/cpu/arm926ejs/kirkwood/cpu.c | 4 +-
arch/arm/include/asm/arch-kirkwood/kirkwood.h | 5 +
drivers/net/Makefile | 2 +-
drivers/net/mv_egiga.c | 322 +++++++++---------
drivers/net/mv_egiga.h | 466 ++++++++++++------------
include/configs/guruplug.h | 4 +-
include/configs/km_arm.h | 4 +-
include/configs/mv88f6281gtw_ge.h | 4 +-
include/configs/openrd_base.h | 4 +-
include/configs/rd6281a.h | 4 +-
include/configs/sheevaplug.h | 4 +-
include/netdev.h | 2 +-
12 files changed, 418 insertions(+), 407 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 6fc3902..786ffc6 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -378,10 +378,10 @@ int arch_misc_init(void)
}
#endif /* CONFIG_ARCH_MISC_INIT */
-#ifdef CONFIG_KIRKWOOD_EGIGA
+#ifdef CONFIG_MV_EGIGA
int cpu_eth_init(bd_t *bis)
{
- kirkwood_egiga_initialize(bis);
+ mv_egiga_initialize(bis);
return 0;
}
#endif
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index 2470efb..9200605 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -60,6 +60,11 @@
#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
+#if defined (CONFIG_MV_EGIGA)
+#define MV_EGIGA0_BASE KW_EGIGA0_BASE
+#define MV_EGIGA1_BASE KW_EGIGA1_BASE
+#endif
+
#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
#elif defined (CONFIG_KW88F6192)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 1599c26..04f8de0 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -52,7 +52,7 @@ COBJS-$(CONFIG_MACB) += macb.o
COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
-COBJS-$(CONFIG_KIRKWOOD_EGIGA) += mv_egiga.o
+COBJS-$(CONFIG_MV_EGIGA) += mv_egiga.o
COBJS-$(CONFIG_NATSEMI) += natsemi.o
COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
diff --git a/drivers/net/mv_egiga.c b/drivers/net/mv_egiga.c
index e635414..0da4c4b 100644
--- a/drivers/net/mv_egiga.c
+++ b/drivers/net/mv_egiga.c
@@ -35,13 +35,17 @@
#include <asm/errno.h>
#include <asm/types.h>
#include <asm/byteorder.h>
+
+#if defined (CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
+#endif
+
#include "mv_egiga.h"
DECLARE_GLOBAL_DATA_PTR;
-#define KIRKWOOD_PHY_ADR_REQUEST 0xee
-#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
+#define MV_PHY_ADR_REQUEST 0xee
+#define MV_EGIGA_SMI_REG (((struct mv_egiga_registers *)MV_EGIGA0_BASE)->smi)
/*
* smi_reg_read - miiphy_read callback function.
@@ -51,16 +55,16 @@ DECLARE_GLOBAL_DATA_PTR;
static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct mv_egiga_device *dmvegiga = to_mv_egiga(dev);
+ struct mv_egiga_registers *regs = dmvegiga->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr read request */
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
+ if (phy_adr == MV_PHY_ADR_REQUEST &&
+ reg_ofs == MV_PHY_ADR_REQUEST) {
/* */
- *data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
+ *data = (u16) (MV_EGIGA_REG_RD(regs->phyadr) & PHYADR_MASK);
return 0;
}
/* check parameters */
@@ -75,42 +79,42 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
return -EFAULT;
}
- timeout = KWGBE_PHY_SMI_TIMEOUT;
+ timeout = MV_EGIGA_PHY_SMI_TIMEOUT;
/* wait till the SMI is not busy */
do {
/* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ smi_reg = MV_EGIGA_REG_RD(MV_EGIGA_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -EFAULT;
}
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+ } while (smi_reg & MV_EGIGA_PHY_SMI_BUSY_MASK);
/* fill the phy address and regiser offset and read opcode */
- smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
- | KWGBE_PHY_SMI_OPCODE_READ;
+ smi_reg = (phy_adr << MV_EGIGA_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << MV_EGIGA_SMI_REG_ADDR_OFFS)
+ | MV_EGIGA_PHY_SMI_OPCODE_READ;
/* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+ MV_EGIGA_REG_WR(MV_EGIGA_SMI_REG, smi_reg);
/*wait till read value is ready */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
+ timeout = MV_EGIGA_PHY_SMI_TIMEOUT;
do {
/* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ smi_reg = MV_EGIGA_REG_RD(MV_EGIGA_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI read ready timeout\n",
__FUNCTION__);
return -EFAULT;
}
- } while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
+ } while (!(smi_reg & MV_EGIGA_PHY_SMI_READ_VALID_MASK));
/* Wait for the data to update in the SMI register */
- for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
+ for (timeout = 0; timeout < MV_EGIGA_PHY_SMI_TIMEOUT; timeout++) ;
- *data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
+ *data = (u16) (MV_EGIGA_REG_RD(MV_EGIGA_SMI_REG) & MV_EGIGA_PHY_SMI_DATA_MASK);
debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
reg_ofs, *data);
@@ -127,15 +131,15 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
{
struct eth_device *dev = eth_get_dev_by_name(devname);
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct mv_egiga_device *dmvegiga = to_mv_egiga(dev);
+ struct mv_egiga_registers *regs = dmvegiga->regs;
u32 smi_reg;
u32 timeout;
/* Phyadr write request*/
- if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
- reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
- KWGBEREG_WR(regs->phyadr, data);
+ if (phy_adr == MV_PHY_ADR_REQUEST &&
+ reg_ofs == MV_PHY_ADR_REQUEST) {
+ MV_EGIGA_REG_WR(regs->phyadr, data);
return 0;
}
@@ -150,24 +154,24 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
}
/* wait till the SMI is not busy */
- timeout = KWGBE_PHY_SMI_TIMEOUT;
+ timeout = MV_EGIGA_PHY_SMI_TIMEOUT;
do {
/* read smi register */
- smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+ smi_reg = MV_EGIGA_REG_RD(MV_EGIGA_SMI_REG);
if (timeout-- == 0) {
printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
return -ETIME;
}
- } while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+ } while (smi_reg & MV_EGIGA_PHY_SMI_BUSY_MASK);
/* fill the phy addr and reg offset and write opcode and data */
- smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
- smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
- | (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
- smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
+ smi_reg = (data << MV_EGIGA_PHY_SMI_DATA_OFFS);
+ smi_reg |= (phy_adr << MV_EGIGA_PHY_SMI_DEV_ADDR_OFFS)
+ | (reg_ofs << MV_EGIGA_SMI_REG_ADDR_OFFS);
+ smi_reg &= ~MV_EGIGA_PHY_SMI_OPCODE_READ;
/* write the smi register */
- KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+ MV_EGIGA_REG_WR(MV_EGIGA_SMI_REG, smi_reg);
return 0;
}
@@ -204,46 +208,46 @@ static void stop_queue(u32 * qreg)
* @regs Register struct pointer.
* @param Address decode parameter struct.
*/
-static void set_access_control(struct kwgbe_registers *regs,
- struct kwgbe_winparam *param)
+static void set_access_control(struct mv_egiga_registers *regs,
+ struct mv_egiga_winparam *param)
{
u32 access_prot_reg;
/* Set access control register */
- access_prot_reg = KWGBEREG_RD(regs->epap);
+ access_prot_reg = MV_EGIGA_REG_RD(regs->epap);
/* clear window permission */
access_prot_reg &= (~(3 << (param->win * 2)));
access_prot_reg |= (param->access_ctrl << (param->win * 2));
- KWGBEREG_WR(regs->epap, access_prot_reg);
+ MV_EGIGA_REG_WR(regs->epap, access_prot_reg);
/* Set window Size reg (SR) */
- KWGBEREG_WR(regs->barsz[param->win].size,
+ MV_EGIGA_REG_WR(regs->barsz[param->win].size,
(((param->size / 0x10000) - 1) << 16));
/* Set window Base address reg (BA) */
- KWGBEREG_WR(regs->barsz[param->win].bar,
+ MV_EGIGA_REG_WR(regs->barsz[param->win].bar,
(param->target | param->attrib | param->base_addr));
/* High address remap reg (HARR) */
if (param->win < 4)
- KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
+ MV_EGIGA_REG_WR(regs->ha_remap[param->win], param->high_addr);
/* Base address enable reg (BARER) */
if (param->enable == 1)
- KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
+ MV_EGIGA_REG_BITS_RESET(regs->bare, (1 << param->win));
else
- KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
+ MV_EGIGA_REG_BITS_SET(regs->bare, (1 << param->win));
}
-static void set_dram_access(struct kwgbe_registers *regs)
+static void set_dram_access(struct mv_egiga_registers *regs)
{
- struct kwgbe_winparam win_param;
+ struct mv_egiga_winparam win_param;
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
/* Set access parameters for DRAM bank i */
win_param.win = i; /* Use Ethernet window i */
/* Window target - DDR */
- win_param.target = KWGBE_TARGET_DRAM;
+ win_param.target = MV_EGIGA_TARGET_DRAM;
/* Enable full access */
win_param.access_ctrl = EWIN_ACCESS_FULL;
win_param.high_addr = 0;
@@ -286,19 +290,19 @@ static void set_dram_access(struct kwgbe_registers *regs)
* Go through all the DA filter tables (Unicast, Special Multicast & Other
* Multicast) and set each entry to 0.
*/
-static void port_init_mac_tables(struct kwgbe_registers *regs)
+static void port_init_mac_tables(struct mv_egiga_registers *regs)
{
int table_index;
/* Clear DA filter unicast table (Ex_dFUT) */
for (table_index = 0; table_index < 4; ++table_index)
- KWGBEREG_WR(regs->dfut[table_index], 0);
+ MV_EGIGA_REG_WR(regs->dfut[table_index], 0);
for (table_index = 0; table_index < 64; ++table_index) {
/* Clear DA filter special multicast table (Ex_dFSMT) */
- KWGBEREG_WR(regs->dfsmt[table_index], 0);
+ MV_EGIGA_REG_WR(regs->dfsmt[table_index], 0);
/* Clear DA filter other multicast table (Ex_dFOMT) */
- KWGBEREG_WR(regs->dfomt[table_index], 0);
+ MV_EGIGA_REG_WR(regs->dfomt[table_index], 0);
}
}
@@ -316,7 +320,7 @@ static void port_init_mac_tables(struct kwgbe_registers *regs)
*
* RETURN: 1 if output succeeded. 0 if option parameter is invalid.
*/
-static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
+static int port_uc_addr(struct mv_egiga_registers *regs, u8 uc_nibble,
int option)
{
u32 unicast_reg;
@@ -336,16 +340,16 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
* Clear accepts frame bit at specified unicast
* DA table entry
*/
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+ unicast_reg = MV_EGIGA_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+ MV_EGIGA_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
case ACCEPT_MAC_ADDR:
/* Set accepts frame bit at unicast DA filter table entry */
- unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+ unicast_reg = MV_EGIGA_REG_RD(regs->dfut[tbl_offset]);
unicast_reg &= (0xFF << (8 * reg_offset));
unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
- KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+ MV_EGIGA_REG_WR(regs->dfut[tbl_offset], unicast_reg);
break;
default:
return 0;
@@ -356,7 +360,7 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
/*
* port_uc_addr_set - This function Set the port Unicast address.
*/
-static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
+static void port_uc_addr_set(struct mv_egiga_registers *regs, u8 * p_addr)
{
u32 mac_h;
u32 mac_l;
@@ -365,92 +369,92 @@ static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
(p_addr[3] << 0);
- KWGBEREG_WR(regs->macal, mac_l);
- KWGBEREG_WR(regs->macah, mac_h);
+ MV_EGIGA_REG_WR(regs->macal, mac_l);
+ MV_EGIGA_REG_WR(regs->macah, mac_h);
/* Accept frames of this address */
port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
}
/*
- * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ * mv_egiga_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
*/
-static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
+static void mv_egiga_init_rx_desc_ring(struct mv_egiga_device *dmvegiga)
{
- struct kwgbe_rxdesc *p_rx_desc;
+ struct mv_egiga_rxdesc *p_rx_desc;
int i;
/* initialize the Rx descriptors ring */
- p_rx_desc = dkwgbe->p_rxdesc;
+ p_rx_desc = dmvegiga->p_rxdesc;
for (i = 0; i < RINGSZ; i++) {
p_rx_desc->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+ MV_EGIGA_BUFFER_OWNED_BY_DMA | MV_EGIGA_RX_EN_INTERRUPT;
p_rx_desc->buf_size = PKTSIZE_ALIGN;
p_rx_desc->byte_cnt = 0;
- p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
+ p_rx_desc->buf_ptr = dmvegiga->p_rxbuf + i * PKTSIZE_ALIGN;
if (i == (RINGSZ - 1))
- p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
+ p_rx_desc->nxtdesc_p = dmvegiga->p_rxdesc;
else {
- p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
- ((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
+ p_rx_desc->nxtdesc_p = (struct mv_egiga_rxdesc *)
+ ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
p_rx_desc = p_rx_desc->nxtdesc_p;
}
}
- dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
+ dmvegiga->p_rxdesc_curr = dmvegiga->p_rxdesc;
}
-static int kwgbe_init(struct eth_device *dev)
+static int mv_egiga_init(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct mv_egiga_device *dmvegiga = to_mv_egiga(dev);
+ struct mv_egiga_registers *regs = dmvegiga->regs;
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
- kwgbe_init_rx_desc_ring(dkwgbe);
+ mv_egiga_init_rx_desc_ring(dmvegiga);
/* Clear the ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
+ MV_EGIGA_REG_WR(regs->ic, 0);
+ MV_EGIGA_REG_WR(regs->ice, 0);
/* Unmask RX buffer and TX end interrupt */
- KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
+ MV_EGIGA_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
/* Unmask phy and link status changes interrupts */
- KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
+ MV_EGIGA_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
set_dram_access(regs);
port_init_mac_tables(regs);
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+ port_uc_addr_set(regs, dmvegiga->dev.enetaddr);
/* Assign port configuration and command. */
- KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
- KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
- KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
+ MV_EGIGA_REG_WR(regs->pxc, PRT_CFG_VAL);
+ MV_EGIGA_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
+ MV_EGIGA_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
/* Assign port SDMA configuration */
- KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
- KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
- KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
+ MV_EGIGA_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
+ MV_EGIGA_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
+ MV_EGIGA_REG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
/* Turn off the port/RXUQ bandwidth limitation */
- KWGBEREG_WR(regs->pmtu, 0);
+ MV_EGIGA_REG_WR(regs->pmtu, 0);
/* Set maximum receive buffer to 9700 bytes */
- KWGBEREG_WR(regs->psc0, KWGBE_MAX_RX_PACKET_9700BYTE
- | (KWGBEREG_RD(regs->psc0) & MRU_MASK));
+ MV_EGIGA_REG_WR(regs->psc0, MV_EGIGA_MAX_RX_PACKET_9700BYTE
+ | (MV_EGIGA_REG_RD(regs->psc0) & MRU_MASK));
/* Enable port initially */
- KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+ MV_EGIGA_REG_BITS_SET(regs->psc0, MV_EGIGA_SERIAL_PORT_EN);
/*
* Set ethernet MTU for leaky bucket mechanism to 0 - this will
* disable the leaky bucket mechanism .
*/
- KWGBEREG_WR(regs->pmtu, 0);
+ MV_EGIGA_REG_WR(regs->pmtu, 0);
/* Assignment of Rx CRDB of given RXUQ */
- KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
+ MV_EGIGA_REG_WR(regs->rxcdp[RXUQ], (u32) dmvegiga->p_rxdesc_curr);
/* Enable port Rx. */
- KWGBEREG_WR(regs->rqc, (1 << RXUQ));
+ MV_EGIGA_REG_WR(regs->rqc, (1 << RXUQ));
#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
&& defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
@@ -458,8 +462,8 @@ static int kwgbe_init(struct eth_device *dev)
for (i = 0; i < 5; i++) {
u16 phyadr;
- miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
+ miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
+ MV_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
if (miiphy_link(dev->name, phyadr))
return 0;
@@ -472,50 +476,50 @@ static int kwgbe_init(struct eth_device *dev)
return 0;
}
-static int kwgbe_halt(struct eth_device *dev)
+static int mv_egiga_halt(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct mv_egiga_device *dmvegiga = to_mv_egiga(dev);
+ struct mv_egiga_registers *regs = dmvegiga->regs;
/* Disable all gigE address decoder */
- KWGBEREG_WR(regs->bare, 0x3f);
+ MV_EGIGA_REG_WR(regs->bare, 0x3f);
stop_queue(®s->tqc);
stop_queue(®s->rqc);
/* Disable port */
- KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+ MV_EGIGA_REG_BITS_RESET(regs->psc0, MV_EGIGA_SERIAL_PORT_EN);
/* Set port is not reset */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
+ MV_EGIGA_REG_BITS_RESET(regs->psc1, 1 << 4);
#ifdef CONFIG_SYS_MII_MODE
/* Set MMI interface up */
- KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
+ MV_EGIGA_REG_BITS_RESET(regs->psc1, 1 << 3);
#endif
/* Disable & mask ethernet port interrupts */
- KWGBEREG_WR(regs->ic, 0);
- KWGBEREG_WR(regs->ice, 0);
- KWGBEREG_WR(regs->pim, 0);
- KWGBEREG_WR(regs->peim, 0);
+ MV_EGIGA_REG_WR(regs->ic, 0);
+ MV_EGIGA_REG_WR(regs->ice, 0);
+ MV_EGIGA_REG_WR(regs->pim, 0);
+ MV_EGIGA_REG_WR(regs->peim, 0);
return 0;
}
-static int kwgbe_write_hwaddr(struct eth_device *dev)
+static int mv_egiga_write_hwaddr(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
+ struct mv_egiga_device *dmvegiga = to_mv_egiga(dev);
+ struct mv_egiga_registers *regs = dmvegiga->regs;
/* Programs net device MAC address after initialization */
- port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+ port_uc_addr_set(regs, dmvegiga->dev.enetaddr);
return 0;
}
-static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
+static int mv_egiga_send(struct eth_device *dev, volatile void *dataptr,
int datasize)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_registers *regs = dkwgbe->regs;
- struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
+ struct mv_egiga_device *dmvegiga = to_mv_egiga(dev);
+ struct mv_egiga_registers *regs = dmvegiga->regs;
+ struct mv_egiga_txdesc *p_txdesc = dmvegiga->p_txdesc;
void *p = (void *)dataptr;
u32 cmd_sts;
@@ -527,30 +531,30 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return -1;
}
- memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
- p = dkwgbe->p_aligned_txbuf;
+ memcpy(dmvegiga->p_aligned_txbuf, p, datasize);
+ p = dmvegiga->p_aligned_txbuf;
}
- p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
- p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
- p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
- p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
+ p_txdesc->cmd_sts = MV_EGIGA_ZERO_PADDING | MV_EGIGA_GEN_CRC;
+ p_txdesc->cmd_sts |= MV_EGIGA_TX_FIRST_DESC | MV_EGIGA_TX_LAST_DESC;
+ p_txdesc->cmd_sts |= MV_EGIGA_BUFFER_OWNED_BY_DMA;
+ p_txdesc->cmd_sts |= MV_EGIGA_TX_EN_INTERRUPT;
p_txdesc->buf_ptr = (u8 *) p;
p_txdesc->byte_cnt = datasize;
/* Apply send command using zeroth TXUQ */
- KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
- KWGBEREG_WR(regs->tqc, (1 << TXUQ));
+ MV_EGIGA_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
+ MV_EGIGA_REG_WR(regs->tqc, (1 << TXUQ));
/*
* wait for packet xmit completion
*/
cmd_sts = readl(&p_txdesc->cmd_sts);
- while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
+ while (cmd_sts & MV_EGIGA_BUFFER_OWNED_BY_DMA) {
/* return fail if error is detected */
- if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
- (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
- cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
+ if ((cmd_sts & (MV_EGIGA_ERROR_SUMMARY | MV_EGIGA_TX_LAST_FRAME)) ==
+ (MV_EGIGA_ERROR_SUMMARY | MV_EGIGA_TX_LAST_FRAME) &&
+ cmd_sts & (MV_EGIGA_UR_ERROR | MV_EGIGA_RL_ERROR)) {
printf("Err..(%s) in xmit packet\n", __FUNCTION__);
return -1;
}
@@ -559,22 +563,22 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
return 0;
}
-static int kwgbe_recv(struct eth_device *dev)
+static int mv_egiga_recv(struct eth_device *dev)
{
- struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
- struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
+ struct mv_egiga_device *dmvegiga = to_mv_egiga(dev);
+ struct mv_egiga_rxdesc *p_rxdesc_curr = dmvegiga->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
/* wait untill rx packet available or timeout */
do {
- if (timeout < KWGBE_PHY_SMI_TIMEOUT)
+ if (timeout < MV_EGIGA_PHY_SMI_TIMEOUT)
timeout++;
else {
debug("%s time out...\n", __FUNCTION__);
return -1;
}
- } while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
+ } while (readl(&p_rxdesc_curr->cmd_sts) & MV_EGIGA_BUFFER_OWNED_BY_DMA);
if (p_rxdesc_curr->byte_cnt != 0) {
debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
@@ -591,13 +595,13 @@ static int kwgbe_recv(struct eth_device *dev)
cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
if ((cmd_sts &
- (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
- != (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
+ (MV_EGIGA_RX_FIRST_DESC | MV_EGIGA_RX_LAST_DESC))
+ != (MV_EGIGA_RX_FIRST_DESC | MV_EGIGA_RX_LAST_DESC)) {
printf("Err..(%s) Dropping packet spread on"
" multiple descriptors\n", __FUNCTION__);
- } else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
+ } else if (cmd_sts & MV_EGIGA_ERROR_SUMMARY) {
printf("Err..(%s) Dropping packet with errors\n",
__FUNCTION__);
@@ -615,62 +619,62 @@ static int kwgbe_recv(struct eth_device *dev)
* free these descriptors and point next in the ring
*/
p_rxdesc_curr->cmd_sts =
- KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+ MV_EGIGA_BUFFER_OWNED_BY_DMA | MV_EGIGA_RX_EN_INTERRUPT;
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
- writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
+ writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dmvegiga->p_rxdesc_curr);
return 0;
}
-int kirkwood_egiga_initialize(bd_t * bis)
+int mv_egiga_initialize(bd_t * bis)
{
- struct kwgbe_device *dkwgbe;
+ struct mv_egiga_device *dmvegiga;
struct eth_device *dev;
int devnum;
char *s;
- u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
+ u8 used_ports[MAX_MV_EGIGA_DEVS] = CONFIG_MV_EGIGA_PORTS;
- for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
+ for (devnum = 0; devnum < MAX_MV_EGIGA_DEVS; devnum++) {
/*skip if port is configured not to use */
if (used_ports[devnum] == 0)
continue;
- if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
+ if (!(dmvegiga = malloc(sizeof(struct mv_egiga_device))))
goto error1;
- memset(dkwgbe, 0, sizeof(struct kwgbe_device));
+ memset(dmvegiga, 0, sizeof(struct mv_egiga_device));
- if (!(dkwgbe->p_rxdesc =
- (struct kwgbe_rxdesc *)memalign(PKTALIGN,
- KW_RXQ_DESC_ALIGNED_SIZE
+ if (!(dmvegiga->p_rxdesc =
+ (struct mv_egiga_rxdesc *)memalign(PKTALIGN,
+ MV_RXQ_DESC_ALIGNED_SIZE
* RINGSZ + 1)))
goto error2;
- if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
+ if (!(dmvegiga->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
* PKTSIZE_ALIGN + 1)))
goto error3;
- if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
+ if (!(dmvegiga->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
goto error4;
- if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
- memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
- free(dkwgbe->p_aligned_txbuf);
+ if (!(dmvegiga->p_txdesc = (struct mv_egiga_txdesc *)
+ memalign(PKTALIGN, sizeof(struct mv_egiga_txdesc) + 1))) {
+ free(dmvegiga->p_aligned_txbuf);
error4:
- free(dkwgbe->p_rxbuf);
+ free(dmvegiga->p_rxbuf);
error3:
- free(dkwgbe->p_rxdesc);
+ free(dmvegiga->p_rxdesc);
error2:
- free(dkwgbe);
+ free(dmvegiga);
error1:
printf("Err.. %s Failed to allocate memory\n",
__FUNCTION__);
return -1;
}
- dev = &dkwgbe->dev;
+ dev = &dmvegiga->dev;
/* must be less than NAMESIZE (16) */
sprintf(dev->name, "egiga%d", devnum);
@@ -678,13 +682,15 @@ int kirkwood_egiga_initialize(bd_t * bis)
/* Extract the MAC address from the environment */
switch (devnum) {
case 0:
- dkwgbe->regs = (void *)KW_EGIGA0_BASE;
+ dmvegiga->regs = (void *)MV_EGIGA0_BASE;
s = "ethaddr";
break;
+#if defined (MV_EGIGA1_BASE)
case 1:
- dkwgbe->regs = (void *)KW_EGIGA1_BASE;
+ dmvegiga->regs = (void *)MV_EGIGA1_BASE;
s = "eth1addr";
break;
+#endif
default: /* this should never happen */
printf("Err..(%s) Invalid device number %d\n",
__FUNCTION__, devnum);
@@ -702,19 +708,19 @@ int kirkwood_egiga_initialize(bd_t * bis)
eth_setenv_enetaddr(s, dev->enetaddr);
}
- dev->init = (void *)kwgbe_init;
- dev->halt = (void *)kwgbe_halt;
- dev->send = (void *)kwgbe_send;
- dev->recv = (void *)kwgbe_recv;
- dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
+ dev->init = (void *)mv_egiga_init;
+ dev->halt = (void *)mv_egiga_halt;
+ dev->send = (void *)mv_egiga_send;
+ dev->recv = (void *)mv_egiga_recv;
+ dev->write_hwaddr = (void *)mv_egiga_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, smi_reg_read, smi_reg_write);
/* Set phy address of the port */
- miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
- KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
+ miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
+ MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
#endif
}
return 0;
diff --git a/drivers/net/mv_egiga.h b/drivers/net/mv_egiga.h
index 30c773c..61c3157 100644
--- a/drivers/net/mv_egiga.h
+++ b/drivers/net/mv_egiga.h
@@ -28,7 +28,7 @@
#ifndef __EGIGA_H__
#define __EGIGA_H__
-#define MAX_KWGBE_DEVS 2 /*controller has two ports */
+#define MAX_MV_EGIGA_DEVS 2 /*controller has two ports */
/* PHY_BASE_ADR is board specific and can be configured */
#if defined (CONFIG_PHY_BASE_ADR)
@@ -49,60 +49,60 @@
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
-#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
-#define KWGBEREG_WR(adr, val) writel(val, &adr)
-#define KWGBEREG_RD(adr) readl(&adr)
-#define KWGBEREG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
-#define KWGBEREG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
+#define to_mv_egiga(_d) container_of(_d, struct mv_egiga_device, dev)
+#define MV_EGIGA_REG_WR(adr, val) writel(val, &adr)
+#define MV_EGIGA_REG_RD(adr) readl(&adr)
+#define MV_EGIGA_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
+#define MV_EGIGA_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
/* Default port configuration value */
#define PRT_CFG_VAL ( \
- KWGBE_UCAST_MOD_NRML | \
- KWGBE_DFLT_RXQ(RXUQ) | \
- KWGBE_DFLT_RX_ARPQ(RXUQ) | \
- KWGBE_RX_BC_IF_NOT_IP_OR_ARP | \
- KWGBE_RX_BC_IF_IP | \
- KWGBE_RX_BC_IF_ARP | \
- KWGBE_CPTR_TCP_FRMS_DIS | \
- KWGBE_CPTR_UDP_FRMS_DIS | \
- KWGBE_DFLT_RX_TCPQ(RXUQ) | \
- KWGBE_DFLT_RX_UDPQ(RXUQ) | \
- KWGBE_DFLT_RX_BPDUQ(RXUQ))
+ MV_EGIGA_UCAST_MOD_NRML | \
+ MV_EGIGA_DFLT_RXQ(RXUQ) | \
+ MV_EGIGA_DFLT_RX_ARPQ(RXUQ) | \
+ MV_EGIGA_RX_BC_IF_NOT_IP_OR_ARP | \
+ MV_EGIGA_RX_BC_IF_IP | \
+ MV_EGIGA_RX_BC_IF_ARP | \
+ MV_EGIGA_CPTR_TCP_FRMS_DIS | \
+ MV_EGIGA_CPTR_UDP_FRMS_DIS | \
+ MV_EGIGA_DFLT_RX_TCPQ(RXUQ) | \
+ MV_EGIGA_DFLT_RX_UDPQ(RXUQ) | \
+ MV_EGIGA_DFLT_RX_BPDUQ(RXUQ))
/* Default port extend configuration value */
#define PORT_CFG_EXTEND_VALUE \
- KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
- KWGBE_PARTITION_DIS | \
- KWGBE_TX_CRC_GENERATION_EN
+ MV_EGIGA_SPAN_BPDU_PACKETS_AS_NORMAL | \
+ MV_EGIGA_PARTITION_DIS | \
+ MV_EGIGA_TX_CRC_GENERATION_EN
-#define GT_KWGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
+#define GT_MV_EGIGA_IPG_INT_RX(value) ((value & 0x3fff) << 8)
/* Default sdma control value */
#define PORT_SDMA_CFG_VALUE ( \
- KWGBE_RX_BURST_SIZE_16_64BIT | \
- KWGBE_BLM_RX_NO_SWAP | \
- KWGBE_BLM_TX_NO_SWAP | \
- GT_KWGBE_IPG_INT_RX(RXUQ) | \
- KWGBE_TX_BURST_SIZE_16_64BIT)
+ MV_EGIGA_RX_BURST_SIZE_16_64BIT | \
+ MV_EGIGA_BLM_RX_NO_SWAP | \
+ MV_EGIGA_BLM_TX_NO_SWAP | \
+ GT_MV_EGIGA_IPG_INT_RX(RXUQ) | \
+ MV_EGIGA_TX_BURST_SIZE_16_64BIT)
/* Default port serial control value */
#define PORT_SERIAL_CONTROL_VALUE ( \
- KWGBE_FORCE_LINK_PASS | \
- KWGBE_DIS_AUTO_NEG_FOR_DUPLX | \
- KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
- KWGBE_ADV_NO_FLOW_CTRL | \
- KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- KWGBE_FORCE_BP_MODE_NO_JAM | \
+ MV_EGIGA_FORCE_LINK_PASS | \
+ MV_EGIGA_DIS_AUTO_NEG_FOR_DUPLX | \
+ MV_EGIGA_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
+ MV_EGIGA_ADV_NO_FLOW_CTRL | \
+ MV_EGIGA_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+ MV_EGIGA_FORCE_BP_MODE_NO_JAM | \
(1 << 9) /* Reserved bit has to be 1 */ | \
- KWGBE_DO_NOT_FORCE_LINK_FAIL | \
- KWGBE_EN_AUTO_NEG_SPEED_GMII | \
- KWGBE_DTE_ADV_0 | \
- KWGBE_MIIPHY_MAC_MODE | \
- KWGBE_AUTO_NEG_NO_CHANGE | \
- KWGBE_MAX_RX_PACKET_1552BYTE | \
- KWGBE_CLR_EXT_LOOPBACK | \
- KWGBE_SET_FULL_DUPLEX_MODE | \
- KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
+ MV_EGIGA_DO_NOT_FORCE_LINK_FAIL | \
+ MV_EGIGA_EN_AUTO_NEG_SPEED_GMII | \
+ MV_EGIGA_DTE_ADV_0 | \
+ MV_EGIGA_MIIPHY_MAC_MODE | \
+ MV_EGIGA_AUTO_NEG_NO_CHANGE | \
+ MV_EGIGA_MAX_RX_PACKET_1552BYTE | \
+ MV_EGIGA_CLR_EXT_LOOPBACK | \
+ MV_EGIGA_SET_FULL_DUPLEX_MODE | \
+ MV_EGIGA_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
/* Tx WRR confoguration macros */
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
@@ -112,187 +112,187 @@
#define ACCEPT_MAC_ADDR 0
#define REJECT_MAC_ADDR 1
/* Size of a Tx/Rx descriptor used in chain list data structure */
-#define KW_RXQ_DESC_ALIGNED_SIZE \
- (((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
+#define MV_RXQ_DESC_ALIGNED_SIZE \
+ (((sizeof(struct mv_egiga_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
/* Buffer offset from buffer pointer */
#define RX_BUF_OFFSET 0x2
/* Port serial status reg (PSR) */
-#define KWGBE_INTERFACE_GMII_MII 0
-#define KWGBE_INTERFACE_PCM 1
-#define KWGBE_LINK_IS_DOWN 0
-#define KWGBE_LINK_IS_UP (1 << 1)
-#define KWGBE_PORT_AT_HALF_DUPLEX 0
-#define KWGBE_PORT_AT_FULL_DUPLEX (1 << 2)
-#define KWGBE_RX_FLOW_CTRL_DISD 0
-#define KWGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
-#define KWGBE_GMII_SPEED_100_10 0
-#define KWGBE_GMII_SPEED_1000 (1 << 4)
-#define KWGBE_MII_SPEED_10 0
-#define KWGBE_MII_SPEED_100 (1 << 5)
-#define KWGBE_NO_TX 0
-#define KWGBE_TX_IN_PROGRESS (1 << 7)
-#define KWGBE_BYPASS_NO_ACTIVE 0
-#define KWGBE_BYPASS_ACTIVE (1 << 8)
-#define KWGBE_PORT_NOT_AT_PARTN_STT 0
-#define KWGBE_PORT_AT_PARTN_STT (1 << 9)
-#define KWGBE_PORT_TX_FIFO_NOT_EMPTY 0
-#define KWGBE_PORT_TX_FIFO_EMPTY (1 << 10)
+#define MV_EGIGA_INTERFACE_GMII_MII 0
+#define MV_EGIGA_INTERFACE_PCM 1
+#define MV_EGIGA_LINK_IS_DOWN 0
+#define MV_EGIGA_LINK_IS_UP (1 << 1)
+#define MV_EGIGA_PORT_AT_HALF_DUPLEX 0
+#define MV_EGIGA_PORT_AT_FULL_DUPLEX (1 << 2)
+#define MV_EGIGA_RX_FLOW_CTRL_DISD 0
+#define MV_EGIGA_RX_FLOW_CTRL_ENBALED (1 << 3)
+#define MV_EGIGA_GMII_SPEED_100_10 0
+#define MV_EGIGA_GMII_SPEED_1000 (1 << 4)
+#define MV_EGIGA_MII_SPEED_10 0
+#define MV_EGIGA_MII_SPEED_100 (1 << 5)
+#define MV_EGIGA_NO_TX 0
+#define MV_EGIGA_TX_IN_PROGRESS (1 << 7)
+#define MV_EGIGA_BYPASS_NO_ACTIVE 0
+#define MV_EGIGA_BYPASS_ACTIVE (1 << 8)
+#define MV_EGIGA_PORT_NOT_AT_PARTN_STT 0
+#define MV_EGIGA_PORT_AT_PARTN_STT (1 << 9)
+#define MV_EGIGA_PORT_TX_FIFO_NOT_EMPTY 0
+#define MV_EGIGA_PORT_TX_FIFO_EMPTY (1 << 10)
/* These macros describes the Port configuration reg (Px_cR) bits */
-#define KWGBE_UCAST_MOD_NRML 0
-#define KWGBE_UNICAST_PROMISCUOUS_MODE 1
-#define KWGBE_DFLT_RXQ(_x) (_x << 1)
-#define KWGBE_DFLT_RX_ARPQ(_x) (_x << 4)
-#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP 0
-#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
-#define KWGBE_RX_BC_IF_IP 0
-#define KWGBE_REJECT_BC_IF_IP (1 << 8)
-#define KWGBE_RX_BC_IF_ARP 0
-#define KWGBE_REJECT_BC_IF_ARP (1 << 9)
-#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
-#define KWGBE_CPTR_TCP_FRMS_DIS 0
-#define KWGBE_CPTR_TCP_FRMS_EN (1 << 14)
-#define KWGBE_CPTR_UDP_FRMS_DIS 0
-#define KWGBE_CPTR_UDP_FRMS_EN (1 << 15)
-#define KWGBE_DFLT_RX_TCPQ(_x) (_x << 16)
-#define KWGBE_DFLT_RX_UDPQ(_x) (_x << 19)
-#define KWGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
-#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
+#define MV_EGIGA_UCAST_MOD_NRML 0
+#define MV_EGIGA_UNICAST_PROMISCUOUS_MODE 1
+#define MV_EGIGA_DFLT_RXQ(_x) (_x << 1)
+#define MV_EGIGA_DFLT_RX_ARPQ(_x) (_x << 4)
+#define MV_EGIGA_RX_BC_IF_NOT_IP_OR_ARP 0
+#define MV_EGIGA_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
+#define MV_EGIGA_RX_BC_IF_IP 0
+#define MV_EGIGA_REJECT_BC_IF_IP (1 << 8)
+#define MV_EGIGA_RX_BC_IF_ARP 0
+#define MV_EGIGA_REJECT_BC_IF_ARP (1 << 9)
+#define MV_EGIGA_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
+#define MV_EGIGA_CPTR_TCP_FRMS_DIS 0
+#define MV_EGIGA_CPTR_TCP_FRMS_EN (1 << 14)
+#define MV_EGIGA_CPTR_UDP_FRMS_DIS 0
+#define MV_EGIGA_CPTR_UDP_FRMS_EN (1 << 15)
+#define MV_EGIGA_DFLT_RX_TCPQ(_x) (_x << 16)
+#define MV_EGIGA_DFLT_RX_UDPQ(_x) (_x << 19)
+#define MV_EGIGA_DFLT_RX_BPDUQ(_x) (_x << 22)
+#define MV_EGIGA_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define KWGBE_CLASSIFY_EN 1
-#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
-#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
-#define KWGBE_PARTITION_DIS 0
-#define KWGBE_PARTITION_EN (1 << 2)
-#define KWGBE_TX_CRC_GENERATION_EN 0
-#define KWGBE_TX_CRC_GENERATION_DIS (1 << 3)
+#define MV_EGIGA_CLASSIFY_EN 1
+#define MV_EGIGA_SPAN_BPDU_PACKETS_AS_NORMAL 0
+#define MV_EGIGA_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
+#define MV_EGIGA_PARTITION_DIS 0
+#define MV_EGIGA_PARTITION_EN (1 << 2)
+#define MV_EGIGA_TX_CRC_GENERATION_EN 0
+#define MV_EGIGA_TX_CRC_GENERATION_DIS (1 << 3)
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define KWGBE_RIFB 1
-#define KWGBE_RX_BURST_SIZE_1_64BIT 0
-#define KWGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
-#define KWGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
-#define KWGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
-#define KWGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
-#define KWGBE_BLM_RX_NO_SWAP (1 << 4)
-#define KWGBE_BLM_RX_BYTE_SWAP 0
-#define KWGBE_BLM_TX_NO_SWAP (1 << 5)
-#define KWGBE_BLM_TX_BYTE_SWAP 0
-#define KWGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
-#define KWGBE_DESCRIPTORS_NO_SWAP 0
-#define KWGBE_TX_BURST_SIZE_1_64BIT 0
-#define KWGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
-#define KWGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
-#define KWGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
-#define KWGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
+#define MV_EGIGA_RIFB 1
+#define MV_EGIGA_RX_BURST_SIZE_1_64BIT 0
+#define MV_EGIGA_RX_BURST_SIZE_2_64BIT (1 << 1)
+#define MV_EGIGA_RX_BURST_SIZE_4_64BIT (1 << 2)
+#define MV_EGIGA_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
+#define MV_EGIGA_RX_BURST_SIZE_16_64BIT (1 << 3)
+#define MV_EGIGA_BLM_RX_NO_SWAP (1 << 4)
+#define MV_EGIGA_BLM_RX_BYTE_SWAP 0
+#define MV_EGIGA_BLM_TX_NO_SWAP (1 << 5)
+#define MV_EGIGA_BLM_TX_BYTE_SWAP 0
+#define MV_EGIGA_DESCRIPTORS_BYTE_SWAP (1 << 6)
+#define MV_EGIGA_DESCRIPTORS_NO_SWAP 0
+#define MV_EGIGA_TX_BURST_SIZE_1_64BIT 0
+#define MV_EGIGA_TX_BURST_SIZE_2_64BIT (1 << 22)
+#define MV_EGIGA_TX_BURST_SIZE_4_64BIT (1 << 23)
+#define MV_EGIGA_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
+#define MV_EGIGA_TX_BURST_SIZE_16_64BIT (1 << 24)
/* These macros describes the Port serial control reg (PSCR) bits */
-#define KWGBE_SERIAL_PORT_DIS 0
-#define KWGBE_SERIAL_PORT_EN 1
-#define KWGBE_FORCE_LINK_PASS (1 << 1)
-#define KWGBE_DO_NOT_FORCE_LINK_PASS 0
-#define KWGBE_EN_AUTO_NEG_FOR_DUPLX 0
-#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
-#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
-#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
-#define KWGBE_ADV_NO_FLOW_CTRL 0
-#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
-#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
-#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
-#define KWGBE_FORCE_BP_MODE_NO_JAM 0
-#define KWGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
-#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
-#define KWGBE_FORCE_LINK_FAIL 0
-#define KWGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
-#define KWGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
-#define KWGBE_EN_AUTO_NEG_SPEED_GMII 0
-#define KWGBE_DTE_ADV_0 0
-#define KWGBE_DTE_ADV_1 (1 << 14)
-#define KWGBE_MIIPHY_MAC_MODE 0
-#define KWGBE_MIIPHY_PHY_MODE (1 << 15)
-#define KWGBE_AUTO_NEG_NO_CHANGE 0
-#define KWGBE_RESTART_AUTO_NEG (1 << 16)
-#define KWGBE_MAX_RX_PACKET_1518BYTE 0
-#define KWGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
-#define KWGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
-#define KWGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
-#define KWGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
-#define KWGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
-#define KWGBE_SET_EXT_LOOPBACK (1 << 20)
-#define KWGBE_CLR_EXT_LOOPBACK 0
-#define KWGBE_SET_FULL_DUPLEX_MODE (1 << 21)
-#define KWGBE_SET_HALF_DUPLEX_MODE 0
-#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
-#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define KWGBE_SET_GMII_SPEED_TO_10_100 0
-#define KWGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
-#define KWGBE_SET_MII_SPEED_TO_10 0
-#define KWGBE_SET_MII_SPEED_TO_100 (1 << 24)
+#define MV_EGIGA_SERIAL_PORT_DIS 0
+#define MV_EGIGA_SERIAL_PORT_EN 1
+#define MV_EGIGA_FORCE_LINK_PASS (1 << 1)
+#define MV_EGIGA_DO_NOT_FORCE_LINK_PASS 0
+#define MV_EGIGA_EN_AUTO_NEG_FOR_DUPLX 0
+#define MV_EGIGA_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
+#define MV_EGIGA_EN_AUTO_NEG_FOR_FLOW_CTRL 0
+#define MV_EGIGA_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
+#define MV_EGIGA_ADV_NO_FLOW_CTRL 0
+#define MV_EGIGA_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
+#define MV_EGIGA_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
+#define MV_EGIGA_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
+#define MV_EGIGA_FORCE_BP_MODE_NO_JAM 0
+#define MV_EGIGA_FORCE_BP_MODE_JAM_TX (1 << 7)
+#define MV_EGIGA_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
+#define MV_EGIGA_FORCE_LINK_FAIL 0
+#define MV_EGIGA_DO_NOT_FORCE_LINK_FAIL (1 << 10)
+#define MV_EGIGA_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
+#define MV_EGIGA_EN_AUTO_NEG_SPEED_GMII 0
+#define MV_EGIGA_DTE_ADV_0 0
+#define MV_EGIGA_DTE_ADV_1 (1 << 14)
+#define MV_EGIGA_MIIPHY_MAC_MODE 0
+#define MV_EGIGA_MIIPHY_PHY_MODE (1 << 15)
+#define MV_EGIGA_AUTO_NEG_NO_CHANGE 0
+#define MV_EGIGA_RESTART_AUTO_NEG (1 << 16)
+#define MV_EGIGA_MAX_RX_PACKET_1518BYTE 0
+#define MV_EGIGA_MAX_RX_PACKET_1522BYTE (1 << 17)
+#define MV_EGIGA_MAX_RX_PACKET_1552BYTE (1 << 18)
+#define MV_EGIGA_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
+#define MV_EGIGA_MAX_RX_PACKET_9192BYTE (1 << 19)
+#define MV_EGIGA_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
+#define MV_EGIGA_SET_EXT_LOOPBACK (1 << 20)
+#define MV_EGIGA_CLR_EXT_LOOPBACK 0
+#define MV_EGIGA_SET_FULL_DUPLEX_MODE (1 << 21)
+#define MV_EGIGA_SET_HALF_DUPLEX_MODE 0
+#define MV_EGIGA_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
+#define MV_EGIGA_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+#define MV_EGIGA_SET_GMII_SPEED_TO_10_100 0
+#define MV_EGIGA_SET_GMII_SPEED_TO_1000 (1 << 23)
+#define MV_EGIGA_SET_MII_SPEED_TO_10 0
+#define MV_EGIGA_SET_MII_SPEED_TO_100 (1 << 24)
/* SMI register fields */
-#define KWGBE_PHY_SMI_TIMEOUT 10000
-#define KWGBE_PHY_SMI_DATA_OFFS 0 /* Data */
-#define KWGBE_PHY_SMI_DATA_MASK (0xffff << KWGBE_PHY_SMI_DATA_OFFS)
-#define KWGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
-#define KWGBE_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
-#define KWGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
-#define KWGBE_SMI_REG_ADDR_MASK (PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
-#define KWGBE_PHY_SMI_OPCODE_MASK (3 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_WRITE (0 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_READ (1 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
-#define KWGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
+#define MV_EGIGA_PHY_SMI_TIMEOUT 10000
+#define MV_EGIGA_PHY_SMI_DATA_OFFS 0 /* Data */
+#define MV_EGIGA_PHY_SMI_DATA_MASK (0xffff << MV_EGIGA_PHY_SMI_DATA_OFFS)
+#define MV_EGIGA_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
+#define MV_EGIGA_PHY_SMI_DEV_ADDR_MASK (PHYADR_MASK << MV_EGIGA_PHY_SMI_DEV_ADDR_OFFS)
+#define MV_EGIGA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
+#define MV_EGIGA_SMI_REG_ADDR_MASK (PHYADR_MASK << MV_EGIGA_SMI_REG_ADDR_OFFS)
+#define MV_EGIGA_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
+#define MV_EGIGA_PHY_SMI_OPCODE_MASK (3 << MV_EGIGA_PHY_SMI_OPCODE_OFFS)
+#define MV_EGIGA_PHY_SMI_OPCODE_WRITE (0 << MV_EGIGA_PHY_SMI_OPCODE_OFFS)
+#define MV_EGIGA_PHY_SMI_OPCODE_READ (1 << MV_EGIGA_PHY_SMI_OPCODE_OFFS)
+#define MV_EGIGA_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
+#define MV_EGIGA_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
/* SDMA command status fields macros */
/* Tx & Rx descriptors status */
-#define KWGBE_ERROR_SUMMARY 1
+#define MV_EGIGA_ERROR_SUMMARY 1
/* Tx & Rx descriptors command */
-#define KWGBE_BUFFER_OWNED_BY_DMA (1 << 31)
+#define MV_EGIGA_BUFFER_OWNED_BY_DMA (1 << 31)
/* Tx descriptors status */
-#define KWGBE_LC_ERROR 0
-#define KWGBE_UR_ERROR (1 << 1)
-#define KWGBE_RL_ERROR (1 << 2)
-#define KWGBE_LLC_SNAP_FORMAT (1 << 9)
-#define KWGBE_TX_LAST_FRAME (1 << 20)
+#define MV_EGIGA_LC_ERROR 0
+#define MV_EGIGA_UR_ERROR (1 << 1)
+#define MV_EGIGA_RL_ERROR (1 << 2)
+#define MV_EGIGA_LLC_SNAP_FORMAT (1 << 9)
+#define MV_EGIGA_TX_LAST_FRAME (1 << 20)
/* Rx descriptors status */
-#define KWGBE_CRC_ERROR 0
-#define KWGBE_OVERRUN_ERROR (1 << 1)
-#define KWGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
-#define KWGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
-#define KWGBE_VLAN_TAGGED (1 << 19)
-#define KWGBE_BPDU_FRAME (1 << 20)
-#define KWGBE_TCP_FRAME_OVER_IP_V_4 0
-#define KWGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
-#define KWGBE_OTHER_FRAME_TYPE (1 << 22)
-#define KWGBE_LAYER_2_IS_KWGBE_V_2 (1 << 23)
-#define KWGBE_FRAME_TYPE_IP_V_4 (1 << 24)
-#define KWGBE_FRAME_HEADER_OK (1 << 25)
-#define KWGBE_RX_LAST_DESC (1 << 26)
-#define KWGBE_RX_FIRST_DESC (1 << 27)
-#define KWGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
-#define KWGBE_RX_EN_INTERRUPT (1 << 29)
-#define KWGBE_LAYER_4_CHECKSUM_OK (1 << 30)
+#define MV_EGIGA_CRC_ERROR 0
+#define MV_EGIGA_OVERRUN_ERROR (1 << 1)
+#define MV_EGIGA_MAX_FRAME_LENGTH_ERROR (1 << 2)
+#define MV_EGIGA_RESOURCE_ERROR ((1 << 2) | (1 << 1))
+#define MV_EGIGA_VLAN_TAGGED (1 << 19)
+#define MV_EGIGA_BPDU_FRAME (1 << 20)
+#define MV_EGIGA_TCP_FRAME_OVER_IP_V_4 0
+#define MV_EGIGA_UDP_FRAME_OVER_IP_V_4 (1 << 21)
+#define MV_EGIGA_OTHER_FRAME_TYPE (1 << 22)
+#define MV_EGIGA_LAYER_2_IS_MV_EGIGA_V_2 (1 << 23)
+#define MV_EGIGA_FRAME_TYPE_IP_V_4 (1 << 24)
+#define MV_EGIGA_FRAME_HEADER_OK (1 << 25)
+#define MV_EGIGA_RX_LAST_DESC (1 << 26)
+#define MV_EGIGA_RX_FIRST_DESC (1 << 27)
+#define MV_EGIGA_UNKNOWN_DESTINATION_ADDR (1 << 28)
+#define MV_EGIGA_RX_EN_INTERRUPT (1 << 29)
+#define MV_EGIGA_LAYER_4_CHECKSUM_OK (1 << 30)
/* Rx descriptors byte count */
-#define KWGBE_FRAME_FRAGMENTED (1 << 2)
+#define MV_EGIGA_FRAME_FRAGMENTED (1 << 2)
/* Tx descriptors command */
-#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
-#define KWGBE_FRAME_SET_TO_VLAN (1 << 15)
-#define KWGBE_TCP_FRAME 0
-#define KWGBE_UDP_FRAME (1 << 16)
-#define KWGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
-#define KWGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
-#define KWGBE_ZERO_PADDING (1 << 19)
-#define KWGBE_TX_LAST_DESC (1 << 20)
-#define KWGBE_TX_FIRST_DESC (1 << 21)
-#define KWGBE_GEN_CRC (1 << 22)
-#define KWGBE_TX_EN_INTERRUPT (1 << 23)
-#define KWGBE_AUTO_MODE (1 << 30)
+#define MV_EGIGA_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
+#define MV_EGIGA_FRAME_SET_TO_VLAN (1 << 15)
+#define MV_EGIGA_TCP_FRAME 0
+#define MV_EGIGA_UDP_FRAME (1 << 16)
+#define MV_EGIGA_GEN_TCP_UDP_CHECKSUM (1 << 17)
+#define MV_EGIGA_GEN_IP_V_4_CHECKSUM (1 << 18)
+#define MV_EGIGA_ZERO_PADDING (1 << 19)
+#define MV_EGIGA_TX_LAST_DESC (1 << 20)
+#define MV_EGIGA_TX_FIRST_DESC (1 << 21)
+#define MV_EGIGA_GEN_CRC (1 << 22)
+#define MV_EGIGA_TX_EN_INTERRUPT (1 << 23)
+#define MV_EGIGA_AUTO_MODE (1 << 30)
/* Address decode parameters */
/* Ethernet Base Address Register bits */
@@ -341,24 +341,24 @@
#define EWIN_ACCESS_FULL ((1 << 1) | 1)
/* structures represents Controller registers */
-struct kwgbe_barsz {
+struct mv_egiga_barsz {
u32 bar;
u32 size;
};
-struct kwgbe_rxcdp {
- struct kwgbe_rxdesc *rxcdp;
+struct mv_egiga_rxcdp {
+ struct mv_egiga_rxdesc *rxcdp;
u32 rxcdp_pad[3];
};
-struct kwgbe_tqx {
+struct mv_egiga_tqx {
u32 qxttbc;
u32 tqxtbc;
u32 tqxac;
u32 tqxpad;
};
-struct kwgbe_registers {
+struct mv_egiga_registers {
u32 phyadr;
u32 smi;
u32 euda;
@@ -372,7 +372,7 @@ struct kwgbe_registers {
u8 pad3[0x0b0 - 0x098 - 4];
u32 euc;
u8 pad3a[0x200 - 0x0b0 - 4];
- struct kwgbe_barsz barsz[6];
+ struct mv_egiga_barsz barsz[6];
u8 pad4[0x280 - 0x22c - 4];
u32 ha_remap[4];
u32 bare;
@@ -417,14 +417,14 @@ struct kwgbe_registers {
u32 pmtu;
u32 pmtbs;
u8 pad14[0x60c - 0x4ec - 4];
- struct kwgbe_rxcdp rxcdp[7];
- struct kwgbe_rxdesc *rxcdp7;
+ struct mv_egiga_rxcdp rxcdp[7];
+ struct mv_egiga_rxdesc *rxcdp7;
u32 rqc;
- struct kwgbe_txdesc *tcsdp;
+ struct mv_egiga_txdesc *tcsdp;
u8 pad15[0x6c0 - 0x684 - 4];
- struct kwgbe_txdesc *tcqdp[8];
+ struct mv_egiga_txdesc *tcqdp[8];
u8 pad16[0x700 - 0x6dc - 4];
- struct kwgbe_tqx tqx[8];
+ struct mv_egiga_tqx tqx[8];
u32 pttbc;
u8 pad17[0x7a8 - 0x780 - 4];
u32 tqxipg0;
@@ -447,26 +447,26 @@ struct kwgbe_registers {
};
/* structures/enums needed by driver */
-enum kwgbe_adrwin {
- KWGBE_WIN0,
- KWGBE_WIN1,
- KWGBE_WIN2,
- KWGBE_WIN3,
- KWGBE_WIN4,
- KWGBE_WIN5
+enum mv_egiga_adrwin {
+ MV_EGIGA_WIN0,
+ MV_EGIGA_WIN1,
+ MV_EGIGA_WIN2,
+ MV_EGIGA_WIN3,
+ MV_EGIGA_WIN4,
+ MV_EGIGA_WIN5
};
-enum kwgbe_target {
- KWGBE_TARGET_DRAM,
- KWGBE_TARGET_DEV,
- KWGBE_TARGET_CBS,
- KWGBE_TARGET_PCI0,
- KWGBE_TARGET_PCI1
+enum mv_egiga_target {
+ MV_EGIGA_TARGET_DRAM,
+ MV_EGIGA_TARGET_DEV,
+ MV_EGIGA_TARGET_CBS,
+ MV_EGIGA_TARGET_PCI0,
+ MV_EGIGA_TARGET_PCI1
};
-struct kwgbe_winparam {
- enum kwgbe_adrwin win; /* Window number */
- enum kwgbe_target target; /* System targets */
+struct mv_egiga_winparam {
+ enum mv_egiga_adrwin win; /* Window number */
+ enum mv_egiga_target target; /* System targets */
u16 attrib; /* BAR attrib. See above macros */
u32 base_addr; /* Window base address in u32 form */
u32 high_addr; /* Window high address in u32 form */
@@ -475,29 +475,29 @@ struct kwgbe_winparam {
u16 access_ctrl; /*Access ctrl register. see above macros */
};
-struct kwgbe_rxdesc {
+struct mv_egiga_rxdesc {
u32 cmd_sts; /* Descriptor command status */
u16 buf_size; /* Buffer size */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer pointer */
- struct kwgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
+ struct mv_egiga_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
-struct kwgbe_txdesc {
+struct mv_egiga_txdesc {
u32 cmd_sts; /* Descriptor command status */
u16 l4i_chk; /* CPU provided TCP Checksum */
u16 byte_cnt; /* Descriptor buffer byte count */
u8 *buf_ptr; /* Descriptor buffer ptr */
- struct kwgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
+ struct mv_egiga_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
-struct kwgbe_device {
+struct mv_egiga_device {
struct eth_device dev;
- struct kwgbe_registers *regs;
- struct kwgbe_txdesc *p_txdesc;
- struct kwgbe_rxdesc *p_rxdesc;
- struct kwgbe_rxdesc *p_rxdesc_curr;
+ struct mv_egiga_registers *regs;
+ struct mv_egiga_txdesc *p_txdesc;
+ struct mv_egiga_rxdesc *p_rxdesc;
+ struct mv_egiga_rxdesc *p_rxdesc_curr;
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
};
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 2fbc6ad..f933017 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -172,9 +172,9 @@
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_CMD_MII
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MV_EGIGA /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_MV_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv88e1121 PHY */
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index a928c2c..ec7d9c5 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -127,9 +127,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MV_EGIGA /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_MV_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h
index 96b4d1c..8281d49 100644
--- a/include/configs/mv88f6281gtw_ge.h
+++ b/include/configs/mv88f6281gtw_ge.h
@@ -172,9 +172,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MV_EGIGA /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_MV_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#endif /* CONFIG_CMD_NET */
diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h
index d2f4502..03ee2ad 100644
--- a/include/configs/openrd_base.h
+++ b/include/configs/openrd_base.h
@@ -183,9 +183,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MV_EGIGA /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_MV_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0x8
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
index 3d8e25c..799f50b 100644
--- a/include/configs/rd6281a.h
+++ b/include/configs/rd6281a.h
@@ -171,8 +171,8 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,1} /* enable both ports */
+#define CONFIG_MV_EGIGA /* Enable Marvell Gbe Controller Driver */
+#define CONFIG_MV_EGIGA_PORTS {1,1} /* enable both ports */
#define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
#define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
#define CONFIG_PHY_SPEED _1000BASET /*Force PHYspeed to 1GBPs */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index e9edc44..40c3f96 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -174,9 +174,9 @@
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MV_EGIGA /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_MV_EGIGA_PORTS {1,0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
diff --git a/include/netdev.h b/include/netdev.h
index 882642a..434848d 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -61,7 +61,6 @@ int ftmac100_initialize(bd_t *bits);
int greth_initialize(bd_t *bis);
void gt6426x_eth_initialize(bd_t *bis);
int inca_switch_initialize(bd_t *bis);
-int kirkwood_egiga_initialize(bd_t *bis);
int lan91c96_initialize(u8 dev_num, int base_addr);
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
int mcdmafec_initialize(bd_t *bis);
@@ -70,6 +69,7 @@ int mpc512x_fec_initialize(bd_t *bis);
int mpc5xxx_fec_initialize(bd_t *bis);
int mpc8220_fec_initialize(bd_t *bis);
int mpc82xx_scc_enet_initialize(bd_t *bis);
+int mv_egiga_initialize(bd_t *bis);
int natsemi_initialize(bd_t *bis);
int npe_initialize(bd_t *bis);
int ns8382x_initialize(bd_t *bis);
--
1.6.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile
2010-07-09 6:34 ` [U-Boot] [PATCH V2 2/6] mv_egiga: support SoCs other than kirkwood Albert Aribaud
@ 2010-07-09 6:34 ` Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood Albert Aribaud
2010-07-09 9:16 ` [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile Prafulla Wadaskar
0 siblings, 2 replies; 17+ messages in thread
From: Albert Aribaud @ 2010-07-09 6:34 UTC (permalink / raw)
To: u-boot
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
drivers/net/mv_egiga.c | 2 +-
drivers/net/mv_egiga.h | 206 ++++++++++++++++++++++++------------------------
2 files changed, 104 insertions(+), 104 deletions(-)
diff --git a/drivers/net/mv_egiga.c b/drivers/net/mv_egiga.c
index 0da4c4b..96e6a5a 100644
--- a/drivers/net/mv_egiga.c
+++ b/drivers/net/mv_egiga.c
@@ -177,7 +177,7 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
}
/* Stop and checks all queues */
-static void stop_queue(u32 * qreg)
+static void stop_queue(volatile u32 * qreg)
{
u32 reg_data;
diff --git a/drivers/net/mv_egiga.h b/drivers/net/mv_egiga.h
index 61c3157..c49bf40 100644
--- a/drivers/net/mv_egiga.h
+++ b/drivers/net/mv_egiga.h
@@ -342,108 +342,108 @@
/* structures represents Controller registers */
struct mv_egiga_barsz {
- u32 bar;
- u32 size;
+ volatile u32 bar;
+ volatile u32 size;
};
struct mv_egiga_rxcdp {
- struct mv_egiga_rxdesc *rxcdp;
- u32 rxcdp_pad[3];
+ volatile struct mv_egiga_rxdesc *rxcdp;
+ volatile u32 rxcdp_pad[3];
};
struct mv_egiga_tqx {
- u32 qxttbc;
- u32 tqxtbc;
- u32 tqxac;
- u32 tqxpad;
+ volatile u32 qxttbc;
+ volatile u32 tqxtbc;
+ volatile u32 tqxac;
+ volatile u32 tqxpad;
};
struct mv_egiga_registers {
- u32 phyadr;
- u32 smi;
- u32 euda;
- u32 eudid;
- u8 pad1[0x080 - 0x00c - 4];
- u32 euic;
- u32 euim;
- u8 pad2[0x094 - 0x084 - 4];
- u32 euea;
- u32 euiae;
- u8 pad3[0x0b0 - 0x098 - 4];
- u32 euc;
- u8 pad3a[0x200 - 0x0b0 - 4];
- struct mv_egiga_barsz barsz[6];
- u8 pad4[0x280 - 0x22c - 4];
- u32 ha_remap[4];
- u32 bare;
- u32 epap;
- u8 pad5[0x400 - 0x294 - 4];
- u32 pxc;
- u32 pxcx;
- u32 mii_ser_params;
- u8 pad6[0x410 - 0x408 - 4];
- u32 evlane;
- u32 macal;
- u32 macah;
- u32 sdc;
- u32 dscp[7];
- u32 psc0;
- u32 vpt2p;
- u32 ps0;
- u32 tqc;
- u32 psc1;
- u32 ps1;
- u32 mrvl_header;
- u8 pad7[0x460 - 0x454 - 4];
- u32 ic;
- u32 ice;
- u32 pim;
- u32 peim;
- u8 pad8[0x474 - 0x46c - 4];
- u32 pxtfut;
- u32 pad9;
- u32 pxmfs;
- u32 pad10;
- u32 pxdfc;
- u32 pxofc;
- u8 pad11[0x494 - 0x488 - 4];
- u32 peuiae;
- u8 pad12[0x4bc - 0x494 - 4];
- u32 eth_type_prio;
- u8 pad13[0x4dc - 0x4bc - 4];
- u32 tqfpc;
- u32 pttbrc;
- u32 tqc1;
- u32 pmtu;
- u32 pmtbs;
- u8 pad14[0x60c - 0x4ec - 4];
- struct mv_egiga_rxcdp rxcdp[7];
- struct mv_egiga_rxdesc *rxcdp7;
- u32 rqc;
- struct mv_egiga_txdesc *tcsdp;
- u8 pad15[0x6c0 - 0x684 - 4];
- struct mv_egiga_txdesc *tcqdp[8];
- u8 pad16[0x700 - 0x6dc - 4];
- struct mv_egiga_tqx tqx[8];
- u32 pttbc;
- u8 pad17[0x7a8 - 0x780 - 4];
- u32 tqxipg0;
- u32 pad18[3];
- u32 tqxipg1;
- u8 pad19[0x7c0 - 0x7b8 - 4];
- u32 hitkninlopkt;
- u32 hitkninasyncpkt;
- u32 lotkninasyncpkt;
- u32 pad20;
- u32 ts;
- u8 pad21[0x3000 - 0x27d0 - 4];
- u32 pad20_1[32]; /* mib counter registes */
- u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
- u32 dfsmt[64];
- u32 dfomt[64];
- u32 dfut[4];
- u8 pad23[0xe20c0 - 0x7360c - 4];
- u32 pmbus_top_arbiter;
+ volatile u32 phyadr;
+ volatile u32 smi;
+ volatile u32 euda;
+ volatile u32 eudid;
+ volatile u8 pad1[0x080 - 0x00c - 4];
+ volatile u32 euic;
+ volatile u32 euim;
+ volatile u8 pad2[0x094 - 0x084 - 4];
+ volatile u32 euea;
+ volatile u32 euiae;
+ volatile u8 pad3[0x0b0 - 0x098 - 4];
+ volatile u32 euc;
+ volatile u8 pad3a[0x200 - 0x0b0 - 4];
+ volatile struct mv_egiga_barsz barsz[6];
+ volatile u8 pad4[0x280 - 0x22c - 4];
+ volatile u32 ha_remap[4];
+ volatile u32 bare;
+ volatile u32 epap;
+ volatile u8 pad5[0x400 - 0x294 - 4];
+ volatile u32 pxc;
+ volatile u32 pxcx;
+ volatile u32 mii_ser_params;
+ volatile u8 pad6[0x410 - 0x408 - 4];
+ volatile u32 evlane;
+ volatile u32 macal;
+ volatile u32 macah;
+ volatile u32 sdc;
+ volatile u32 dscp[7];
+ volatile u32 psc0;
+ volatile u32 vpt2p;
+ volatile u32 ps0;
+ volatile u32 tqc;
+ volatile u32 psc1;
+ volatile u32 ps1;
+ volatile u32 mrvl_header;
+ volatile u8 pad7[0x460 - 0x454 - 4];
+ volatile u32 ic;
+ volatile u32 ice;
+ volatile u32 pim;
+ volatile u32 peim;
+ volatile u8 pad8[0x474 - 0x46c - 4];
+ volatile u32 pxtfut;
+ volatile u32 pad9;
+ volatile u32 pxmfs;
+ volatile u32 pad10;
+ volatile u32 pxdfc;
+ volatile u32 pxofc;
+ volatile u8 pad11[0x494 - 0x488 - 4];
+ volatile u32 peuiae;
+ volatile u8 pad12[0x4bc - 0x494 - 4];
+ volatile u32 eth_type_prio;
+ volatile u8 pad13[0x4dc - 0x4bc - 4];
+ volatile u32 tqfpc;
+ volatile u32 pttbrc;
+ volatile u32 tqc1;
+ volatile u32 pmtu;
+ volatile u32 pmtbs;
+ volatile u8 pad14[0x60c - 0x4ec - 4];
+ volatile struct mv_egiga_rxcdp rxcdp[7];
+ volatile struct mv_egiga_rxdesc *rxcdp7;
+ volatile u32 rqc;
+ volatile struct mv_egiga_txdesc *tcsdp;
+ volatile u8 pad15[0x6c0 - 0x684 - 4];
+ volatile struct mv_egiga_txdesc *tcqdp[8];
+ volatile u8 pad16[0x700 - 0x6dc - 4];
+ volatile struct mv_egiga_tqx tqx[8];
+ volatile u32 pttbc;
+ volatile u8 pad17[0x7a8 - 0x780 - 4];
+ volatile u32 tqxipg0;
+ volatile u32 pad18[3];
+ volatile u32 tqxipg1;
+ volatile u8 pad19[0x7c0 - 0x7b8 - 4];
+ volatile u32 hitkninlopkt;
+ volatile u32 hitkninasyncpkt;
+ volatile u32 lotkninasyncpkt;
+ volatile u32 pad20;
+ volatile u32 ts;
+ volatile u8 pad21[0x3000 - 0x27d0 - 4];
+ volatile u32 pad20_1[32]; /* mib counter registes */
+ volatile u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
+ volatile u32 dfsmt[64];
+ volatile u32 dfomt[64];
+ volatile u32 dfut[4];
+ volatile u8 pad23[0xe20c0 - 0x7360c - 4];
+ volatile u32 pmbus_top_arbiter;
};
/* structures/enums needed by driver */
@@ -476,19 +476,19 @@ struct mv_egiga_winparam {
};
struct mv_egiga_rxdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 buf_size; /* Buffer size */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer pointer */
- struct mv_egiga_rxdesc *nxtdesc_p; /* Next descriptor pointer */
+ volatile u32 cmd_sts; /* Descriptor command status */
+ volatile u16 buf_size; /* Buffer size */
+ volatile u16 byte_cnt; /* Descriptor buffer byte count */
+ volatile u8 *buf_ptr; /* Descriptor buffer pointer */
+ volatile struct mv_egiga_rxdesc *nxtdesc_p; /* Next descriptor pointer */
};
struct mv_egiga_txdesc {
- u32 cmd_sts; /* Descriptor command status */
- u16 l4i_chk; /* CPU provided TCP Checksum */
- u16 byte_cnt; /* Descriptor buffer byte count */
- u8 *buf_ptr; /* Descriptor buffer ptr */
- struct mv_egiga_txdesc *nxtdesc_p; /* Next descriptor ptr */
+ volatile u32 cmd_sts; /* Descriptor command status */
+ volatile u16 l4i_chk; /* CPU provided TCP Checksum */
+ volatile u16 byte_cnt; /* Descriptor buffer byte count */
+ volatile u8 *buf_ptr; /* Descriptor buffer ptr */
+ volatile struct mv_egiga_txdesc *nxtdesc_p; /* Next descriptor ptr */
};
/* port device data struct */
--
1.6.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood
2010-07-09 6:34 ` [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile Albert Aribaud
@ 2010-07-09 6:34 ` Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 5/6] mv_egiga: add support for orion5x egiga controller Albert Aribaud
2010-07-09 8:58 ` [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood Prafulla Wadaskar
2010-07-09 9:16 ` [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile Prafulla Wadaskar
1 sibling, 2 replies; 17+ messages in thread
From: Albert Aribaud @ 2010-07-09 6:34 UTC (permalink / raw)
To: u-boot
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
drivers/net/mv_egiga.c | 10 +++++++++-
1 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/drivers/net/mv_egiga.c b/drivers/net/mv_egiga.c
index 96e6a5a..9db24ba 100644
--- a/drivers/net/mv_egiga.c
+++ b/drivers/net/mv_egiga.c
@@ -698,13 +698,21 @@ int mv_egiga_initialize(bd_t * bis)
}
while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
- /* Generate Random Private MAC addr if not set */
+ /* Generate Private MAC addr if not set */
dev->enetaddr[0] = 0x02;
dev->enetaddr[1] = 0x50;
dev->enetaddr[2] = 0x43;
+#if defined (CONFIG_KIRKWOOD)
+ /* Generate random lower MAC half */
dev->enetaddr[3] = get_random_hex();
dev->enetaddr[4] = get_random_hex();
dev->enetaddr[5] = get_random_hex();
+#else
+ /* Generate fixed lower MAC half using devnum */
+ dev->enetaddr[3] = 0;
+ dev->enetaddr[4] = 0;
+ dev->enetaddr[5] = devnum;
+#endif
eth_setenv_enetaddr(s, dev->enetaddr);
}
--
1.6.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 5/6] mv_egiga: add support for orion5x egiga controller
2010-07-09 6:34 ` [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood Albert Aribaud
@ 2010-07-09 6:34 ` Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 6/6] edminiv2: add ethernet support Albert Aribaud
2010-07-09 8:58 ` [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood Prafulla Wadaskar
1 sibling, 1 reply; 17+ messages in thread
From: Albert Aribaud @ 2010-07-09 6:34 UTC (permalink / raw)
To: u-boot
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
arch/arm/cpu/arm926ejs/orion5x/cpu.c | 8 ++++++++
arch/arm/include/asm/arch-orion5x/orion5x.h | 5 +++++
drivers/net/mv_egiga.c | 2 ++
3 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
index 03c6d06..fc9455e 100644
--- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c
+++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c
@@ -268,3 +268,11 @@ int arch_misc_init(void)
return 0;
}
#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_MV_EGIGA
+int cpu_eth_init(bd_t *bis)
+{
+ mv_egiga_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-orion5x/orion5x.h b/arch/arm/include/asm/arch-orion5x/orion5x.h
index 4008c84..6783b74 100644
--- a/arch/arm/include/asm/arch-orion5x/orion5x.h
+++ b/arch/arm/include/asm/arch-orion5x/orion5x.h
@@ -56,6 +56,11 @@
#define ORION5X_USB20_PORT1_BASE (ORION5X_REGISTER(0xA0000))
#define ORION5X_EGIGA_BASE (ORION5X_REGISTER(0x72000))
+/* Oron5x has one Marvell egiga controller */
+#if defined (CONFIG_MV_EGIGA)
+#define MV_EGIGA0_BASE ORION5X_EGIGA_BASE
+#endif
+
#define CONFIG_MAX_RAM_BANK_SIZE (64*1024*1024)
/* include here SoC variants. 5181, 5281, 6183 should go here when
diff --git a/drivers/net/mv_egiga.c b/drivers/net/mv_egiga.c
index 9db24ba..83741fe 100644
--- a/drivers/net/mv_egiga.c
+++ b/drivers/net/mv_egiga.c
@@ -38,6 +38,8 @@
#if defined (CONFIG_KIRKWOOD)
#include <asm/arch/kirkwood.h>
+#elif defined (CONFIG_ORION5X)
+#include <asm/arch/orion5x.h>
#endif
#include "mv_egiga.h"
--
1.6.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 6/6] edminiv2: add ethernet support
2010-07-09 6:34 ` [U-Boot] [PATCH V2 5/6] mv_egiga: add support for orion5x egiga controller Albert Aribaud
@ 2010-07-09 6:34 ` Albert Aribaud
0 siblings, 0 replies; 17+ messages in thread
From: Albert Aribaud @ 2010-07-09 6:34 UTC (permalink / raw)
To: u-boot
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
board/LaCie/edminiv2/edminiv2.c | 36 ++++++++++++++++++++++++++++++++++
board/LaCie/edminiv2/edminiv2.h | 41 +++++++++++++++++++++++++++++++++++++++
include/configs/edminiv2.h | 22 +++++++++++++++-----
3 files changed, 93 insertions(+), 6 deletions(-)
create mode 100644 board/LaCie/edminiv2/edminiv2.h
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index 54c0ffe..d46ee4a 100644
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -27,6 +27,7 @@
#include <common.h>
#include <miiphy.h>
#include <asm/arch/orion5x.h>
+#include "edminiv2.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -90,3 +91,38 @@ int board_init(void)
return 0;
}
+
+#if defined (CONFIG_CMD_NET) && defined (CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+ u16 reg;
+ u16 devadr;
+ char *name = "egiga0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __FUNCTION__);
+ return;
+ }
+
+ /*
+ * Enable RGMII delay on Tx and Rx for CPU port
+ * Ref: sec 4.7.2 of chip datasheet
+ */
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+ miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
+ reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+ miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+ miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+ /* reset the phy */
+ miiphy_reset(name, devadr);
+
+ printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h
new file mode 100644
index 0000000..88e62b2
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_BASE_H
+#define __EDMINIV2_BASE_H
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG 10
+#define MV88E1116_CPRSP_CR3_REG 21
+#define MV88E1116_MAC_CTRL_REG 21
+#define MV88E1116_PGADR_REG 22
+#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __EDMINIV2_BASE_H */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index c3d95a0..a3e970c 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -110,6 +110,14 @@
#define CONFIG_SYS_FLASH_SECTSZ \
{16384, 8192, 8192, 32768, \
65536, 65536, 65536, 65536, 65536, 65536, 65536}
+/*
+ * Ethernet
+ */
+
+#define CONFIG_MV_EGIGA /* Enable Marvell egiga Controller Driver */
+#define CONFIG_MV_EGIGA_PORTS {1,0} /* enable port 0 only */
+#define CONFIG_PHY_BASE_ADR 0x8
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
@@ -131,12 +139,14 @@
* Commands configuration - using default command set for now
*/
#include <config_cmd_default.h>
-/*
- * Disabling some default commands for staggered bring-up
- */
-#undef CONFIG_CMD_BOOTD /* no bootd since no net */
-#undef CONFIG_CMD_NET /* no net since no eth */
-#undef CONFIG_CMD_NFS /* no NFS since no net */
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi ove miiphy interface */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#endif
/*
* Environment variables configurations
--
1.6.4.4
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood
2010-07-09 6:34 ` [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 5/6] mv_egiga: add support for orion5x egiga controller Albert Aribaud
@ 2010-07-09 8:58 ` Prafulla Wadaskar
2010-07-09 9:17 ` Albert ARIBAUD
1 sibling, 1 reply; 17+ messages in thread
From: Prafulla Wadaskar @ 2010-07-09 8:58 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Friday, July 09, 2010 12:04 PM
> To: u-boot at lists.denx.de
> Subject: [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC
> on kirkwood
Otherway: Some SOCs cannot generate random numbers required for Randomize MAC address generation.
Mostly on any SoC there are time varient registors than can be used to generate random number for system need.
If it is not possible on some SoC (ex. Orion5x) or not yet discovered, then skip this logic under CONFIG_SKIP_RANDOMNUMGEN (ex.)
>
>
> Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
> ---
> drivers/net/mv_egiga.c | 10 +++++++++-
> 1 files changed, 9 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/mv_egiga.c b/drivers/net/mv_egiga.c
> index 96e6a5a..9db24ba 100644
> --- a/drivers/net/mv_egiga.c
> +++ b/drivers/net/mv_egiga.c
> @@ -698,13 +698,21 @@ int mv_egiga_initialize(bd_t * bis)
> }
>
> while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
> - /* Generate Random Private MAC addr if
> not set */
> + /* Generate Private MAC addr if not set */
> dev->enetaddr[0] = 0x02;
> dev->enetaddr[1] = 0x50;
> dev->enetaddr[2] = 0x43;
> +#if defined (CONFIG_KIRKWOOD)
This should ifndef CONFIG_SKIP_RANDOMNUMGEN
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga as mv_egiga
2010-07-09 6:34 ` [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga as mv_egiga Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 2/6] mv_egiga: support SoCs other than kirkwood Albert Aribaud
@ 2010-07-09 9:08 ` Prafulla Wadaskar
1 sibling, 0 replies; 17+ messages in thread
From: Prafulla Wadaskar @ 2010-07-09 9:08 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Friday, July 09, 2010 12:04 PM
> To: u-boot at lists.denx.de
> Subject: [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga
> as mv_egiga
>
> This is the first of two changes aimed at separating the
> Marvell egiga driver from the kirkwood SoC in order to
> use it from other SoCs which implement it.
>
> Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
> ---
> drivers/net/Makefile | 2 +-
> drivers/net/{kirkwood_egiga.c => mv_egiga.c} | 2 +-
> drivers/net/{kirkwood_egiga.h => mv_egiga.h} | 0
> 3 files changed, 2 insertions(+), 2 deletions(-)
> rename drivers/net/{kirkwood_egiga.c => mv_egiga.c} (99%)
> rename drivers/net/{kirkwood_egiga.h => mv_egiga.h} (100%)
>
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index b75c02f..1599c26 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -46,13 +46,13 @@ COBJS-$(CONFIG_FSLDMAFEC) +=
> fsl_mcdmafec.o mcfmii.o
> COBJS-$(CONFIG_FTMAC100) += ftmac100.o
> COBJS-$(CONFIG_GRETH) += greth.o
> COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o
> -COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o
> COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
> COBJS-$(CONFIG_LAN91C96) += lan91c96.o
> COBJS-$(CONFIG_MACB) += macb.o
> COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
> COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
> COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
> +COBJS-$(CONFIG_KIRKWOOD_EGIGA) += mv_egiga.o
> COBJS-$(CONFIG_NATSEMI) += natsemi.o
> COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
> COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
> diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/mv_egiga.c
> similarity index 99%
> rename from drivers/net/kirkwood_egiga.c
> rename to drivers/net/mv_egiga.c
> index b7374b5..e635414 100644
> --- a/drivers/net/kirkwood_egiga.c
> +++ b/drivers/net/mv_egiga.c
> @@ -36,7 +36,7 @@
> #include <asm/types.h>
> #include <asm/byteorder.h>
> #include <asm/arch/kirkwood.h>
> -#include "kirkwood_egiga.h"
> +#include "mv_egiga.h"
>
> DECLARE_GLOBAL_DATA_PTR;
>
> diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/mv_egiga.h
> similarity index 100%
> rename from drivers/net/kirkwood_egiga.h
> rename to drivers/net/mv_egiga.h
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile
2010-07-09 6:34 ` [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood Albert Aribaud
@ 2010-07-09 9:16 ` Prafulla Wadaskar
2010-07-09 9:54 ` Albert ARIBAUD
1 sibling, 1 reply; 17+ messages in thread
From: Prafulla Wadaskar @ 2010-07-09 9:16 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Friday, July 09, 2010 12:04 PM
> To: u-boot at lists.denx.de
> Subject: [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue
> fixed using volatile
For each patch post, there must be some informative explanation about a patch that helps everybody to understand the objective of the patch, this is mostly applicable for all your patches
Change log is something different, that is for developers and reviewers, that will not reflect on the repository after acceptance.
>
>
> Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
> ---
> drivers/net/mv_egiga.c | 2 +-
> drivers/net/mv_egiga.h | 206
> ++++++++++++++++++++++++------------------------
> 2 files changed, 104 insertions(+), 104 deletions(-)
>
> diff --git a/drivers/net/mv_egiga.c b/drivers/net/mv_egiga.c
> index 0da4c4b..96e6a5a 100644
> --- a/drivers/net/mv_egiga.c
> +++ b/drivers/net/mv_egiga.c
> @@ -177,7 +177,7 @@ static int smi_reg_write(char *devname,
> u8 phy_adr, u8 reg_ofs, u16 data)
> }
>
> /* Stop and checks all queues */
> -static void stop_queue(u32 * qreg)
> +static void stop_queue(volatile u32 * qreg)
> {
> u32 reg_data;
>
> diff --git a/drivers/net/mv_egiga.h b/drivers/net/mv_egiga.h
> index 61c3157..c49bf40 100644
> --- a/drivers/net/mv_egiga.h
> +++ b/drivers/net/mv_egiga.h
> @@ -342,108 +342,108 @@
>
> /* structures represents Controller registers */
> struct mv_egiga_barsz {
> - u32 bar;
> - u32 size;
> + volatile u32 bar;
> + volatile u32 size;
May be, making all volatile solves problem at your end, that does not mean it is solution.
Mostly all registers are accessed as volatile (readl/writel), register pointers are also volatile.
I agree with you and suspect some code related to DMA pipes initialization has problem that's breaking it's functionality on Orion5X.
I think we should debug on this to fix the bug correctly.
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood
2010-07-09 8:58 ` [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood Prafulla Wadaskar
@ 2010-07-09 9:17 ` Albert ARIBAUD
0 siblings, 0 replies; 17+ messages in thread
From: Albert ARIBAUD @ 2010-07-09 9:17 UTC (permalink / raw)
To: u-boot
Le 09/07/2010 10:58, Prafulla Wadaskar a ?crit :
>> +#if defined (CONFIG_KIRKWOOD)
>
> This should ifndef CONFIG_SKIP_RANDOMNUMGEN
>
> Regards..
> Prafulla . .
Ok -- will change and republish patch 4/6.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile
2010-07-09 9:16 ` [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile Prafulla Wadaskar
@ 2010-07-09 9:54 ` Albert ARIBAUD
2010-07-09 11:11 ` Prafulla Wadaskar
2010-07-09 11:51 ` [U-Boot] mv_egiga: effect on making struct members volatile(was: [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile) Albert ARIBAUD
0 siblings, 2 replies; 17+ messages in thread
From: Albert ARIBAUD @ 2010-07-09 9:54 UTC (permalink / raw)
To: u-boot
Le 09/07/2010 11:16, Prafulla Wadaskar a ?crit :
>
>
>> -----Original Message-----
>> From: u-boot-bounces at lists.denx.de
>> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
>> Sent: Friday, July 09, 2010 12:04 PM
>> To: u-boot at lists.denx.de
>> Subject: [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue
>> fixed using volatile
>
> For each patch post, there must be some informative explanation about a patch that helps everybody to understand the objective of the patch, this is mostly applicable for all your patches
>
> Change log is something different, that is for developers and reviewers, that will not reflect on the repository after acceptance.
>
>>
>>
>> Signed-off-by: Albert Aribaud<albert.aribaud@free.fr>
>> ---
>> drivers/net/mv_egiga.c | 2 +-
>> drivers/net/mv_egiga.h | 206
>> ++++++++++++++++++++++++------------------------
>> 2 files changed, 104 insertions(+), 104 deletions(-)
>>
>> diff --git a/drivers/net/mv_egiga.c b/drivers/net/mv_egiga.c
>> index 0da4c4b..96e6a5a 100644
>> --- a/drivers/net/mv_egiga.c
>> +++ b/drivers/net/mv_egiga.c
>> @@ -177,7 +177,7 @@ static int smi_reg_write(char *devname,
>> u8 phy_adr, u8 reg_ofs, u16 data)
>> }
>>
>> /* Stop and checks all queues */
>> -static void stop_queue(u32 * qreg)
>> +static void stop_queue(volatile u32 * qreg)
>> {
>> u32 reg_data;
>>
>> diff --git a/drivers/net/mv_egiga.h b/drivers/net/mv_egiga.h
>> index 61c3157..c49bf40 100644
>> --- a/drivers/net/mv_egiga.h
>> +++ b/drivers/net/mv_egiga.h
>> @@ -342,108 +342,108 @@
>>
>> /* structures represents Controller registers */
>> struct mv_egiga_barsz {
>> - u32 bar;
>> - u32 size;
>> + volatile u32 bar;
>> + volatile u32 size;
>
> May be, making all volatile solves problem at your end, that does not mean it is solution.
> Mostly all registers are accessed as volatile (readl/writel), register pointers are also volatile.
>
> I agree with you and suspect some code related to DMA pipes initialization has problem that's breaking it's functionality on Orion5X.
>
> I think we should debug on this to fix the bug correctly.
>
> Regards..
> Prafulla . .
I have debugged the issue when it happened and found out that the it is
not really about doing volatile accesses, but about doing accesses
out-of-order: the compiler intermixes writes from adjacent source code
lines, which causes the write to the DMA start bit to occur before
writes to the descriptors are done. Apparently qualifying the struct
members volatile has an effect or write order that readl/writel have not.
I'll do a detailed comparison of disassembled code with and without the
volatile qualifiers.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile
2010-07-09 9:54 ` Albert ARIBAUD
@ 2010-07-09 11:11 ` Prafulla Wadaskar
2010-07-09 11:53 ` Albert ARIBAUD
2010-07-09 11:51 ` [U-Boot] mv_egiga: effect on making struct members volatile(was: [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile) Albert ARIBAUD
1 sibling, 1 reply; 17+ messages in thread
From: Prafulla Wadaskar @ 2010-07-09 11:11 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Friday, July 09, 2010 3:24 PM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de
> Subject: Re: [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed
> using volatile
>
Snip..
> >> diff --git a/drivers/net/mv_egiga.h b/drivers/net/mv_egiga.h
> >> index 61c3157..c49bf40 100644
> >> --- a/drivers/net/mv_egiga.h
> >> +++ b/drivers/net/mv_egiga.h
> >> @@ -342,108 +342,108 @@
> >>
> >> /* structures represents Controller registers */
> >> struct mv_egiga_barsz {
> >> - u32 bar;
> >> - u32 size;
> >> + volatile u32 bar;
> >> + volatile u32 size;
> >
> > May be, making all volatile solves problem at your end,
> that does not mean it is solution.
> > Mostly all registers are accessed as volatile
> (readl/writel), register pointers are also volatile.
> >
> > I agree with you and suspect some code related to DMA pipes
> initialization has problem that's breaking it's functionality
> on Orion5X.
> >
> > I think we should debug on this to fix the bug correctly.
> >
> > Regards..
> > Prafulla . .
>
> I have debugged the issue when it happened and found out that
> the it is
> not really about doing volatile accesses, but about doing accesses
> out-of-order: the compiler intermixes writes from adjacent
> source code
> lines, which causes the write to the DMA start bit to occur before
> writes to the descriptors are done. Apparently qualifying the struct
> members volatile has an effect or write order that
> readl/writel have not.
You can use volatile qualifier for the variables in DMA specific code instead of modifying structures,
Try to use memory barrier or something like that-
Some ref : http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html
may be someone c-expert on the list can suggest better
Regards..
Prafulla . .
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] mv_egiga: effect on making struct members volatile(was: [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile)
2010-07-09 9:54 ` Albert ARIBAUD
2010-07-09 11:11 ` Prafulla Wadaskar
@ 2010-07-09 11:51 ` Albert ARIBAUD
1 sibling, 0 replies; 17+ messages in thread
From: Albert ARIBAUD @ 2010-07-09 11:51 UTC (permalink / raw)
To: u-boot
Le 09/07/2010 11:54, Albert ARIBAUD a ?crit :
>> I think we should debug on this to fix the bug correctly.
>>
>> Regards..
>> Prafulla . .
>
> I have debugged the issue when it happened and found out that the it is
> not really about doing volatile accesses, but about doing accesses
> out-of-order: the compiler intermixes writes from adjacent source code
> lines, which causes the write to the DMA start bit to occur before
> writes to the descriptors are done. Apparently qualifying the struct
> members volatile has an effect or write order that readl/writel have not.
>
> I'll do a detailed comparison of disassembled code with and without the
> volatile qualifiers.
I've done builds with and without the volatile patch and an objdump -S
of each, concentrating on function mv_egiga_send around lines 540-545
(filling of TX descriptor) and 549-549 (actual launch of DMA) of mv_egiga.c.
These confirm that the issue is of write ordering, as making the members
volatile changes this ordering and solves the issue.
Most notably, there is one tx desc field, p_txdesc->byte_cnt, which is
filled in after start of DMA in the 'bad' case, and before start of DMA
in the 'good' case.
After reading arch/arm/include/asm/io.h correctly, it seems like in*()
and out*() macros do include sequence points to make sure their relative
order is preserved, but writel/readl don't. I'll try wihout volatile but
with a sequence point forced at the TQC register write.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile
2010-07-09 11:11 ` Prafulla Wadaskar
@ 2010-07-09 11:53 ` Albert ARIBAUD
2010-07-09 13:00 ` Albert ARIBAUD
0 siblings, 1 reply; 17+ messages in thread
From: Albert ARIBAUD @ 2010-07-09 11:53 UTC (permalink / raw)
To: u-boot
Le 09/07/2010 13:11, Prafulla Wadaskar a ?crit :
> You can use volatile qualifier for the variables in DMA specific code instead of modifying structures,
> Try to use memory barrier or something like that-
> Some ref : http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html
> may be someone c-expert on the list can suggest better
Seems we've followed the same line of reasoning. :)
I'll look into forcing a sequence point without resorting to asm.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile
2010-07-09 11:53 ` Albert ARIBAUD
@ 2010-07-09 13:00 ` Albert ARIBAUD
2010-07-10 6:41 ` Prafulla Wadaskar
0 siblings, 1 reply; 17+ messages in thread
From: Albert ARIBAUD @ 2010-07-09 13:00 UTC (permalink / raw)
To: u-boot
Le 09/07/2010 13:53, Albert ARIBAUD a ?crit :
> Le 09/07/2010 13:11, Prafulla Wadaskar a ?crit :
>
>> You can use volatile qualifier for the variables in DMA specific code instead of modifying structures,
>> Try to use memory barrier or something like that-
>> Some ref : http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html
>> may be someone c-expert on the list can suggest better
>
> Seems we've followed the same line of reasoning. :)
>
> I'll look into forcing a sequence point without resorting to asm.
Found it. arch/arm/include/asm/system.h provides isb() which expands to
an asm statement acting as a sequence point. Inserting an isb() right
before starting DMA ensures that all writes to the descriptor are
emitted before setting the TQC register for DMA, so that should work.
Shouldn't I send out the isb() fix as a separate patch? After all, it is
a fix for a bug (uncontrolled sequencing) which is present for kirkwood
even though we were lucky enough that it did not bite so far.
Amicalement,
--
Albert.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile
2010-07-09 13:00 ` Albert ARIBAUD
@ 2010-07-10 6:41 ` Prafulla Wadaskar
0 siblings, 0 replies; 17+ messages in thread
From: Prafulla Wadaskar @ 2010-07-10 6:41 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Albert ARIBAUD [mailto:albert.aribaud at free.fr]
> Sent: Friday, July 09, 2010 6:31 PM
> To: Prafulla Wadaskar; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA
> issue fixed using volatile
>
> Le 09/07/2010 13:53, Albert ARIBAUD a ?crit :
> > Le 09/07/2010 13:11, Prafulla Wadaskar a ?crit :
> >
> >> You can use volatile qualifier for the variables in DMA
> specific code instead of modifying structures,
> >> Try to use memory barrier or something like that-
> >> Some ref : http://gcc.gnu.org/ml/gcc/2003-04/msg01180.html
> >> may be someone c-expert on the list can suggest better
> >
> > Seems we've followed the same line of reasoning. :)
> >
> > I'll look into forcing a sequence point without resorting to asm.
>
> Found it. arch/arm/include/asm/system.h provides isb() which
> expands to
> an asm statement acting as a sequence point. Inserting an isb() right
> before starting DMA ensures that all writes to the descriptor are
> emitted before setting the TQC register for DMA, so that should work.
Good findings...
>
> Shouldn't I send out the isb() fix as a separate patch? After
> all, it is
> a fix for a bug (uncontrolled sequencing) which is present
> for kirkwood
> even though we were lucky enough that it did not bite so far.
Yes, Pls do the needful
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2010-07-10 6:41 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-07-09 6:34 [U-Boot] [PATCH V2 0/6] Marvell egiga multiple SoC support Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga as mv_egiga Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 2/6] mv_egiga: support SoCs other than kirkwood Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 5/6] mv_egiga: add support for orion5x egiga controller Albert Aribaud
2010-07-09 6:34 ` [U-Boot] [PATCH V2 6/6] edminiv2: add ethernet support Albert Aribaud
2010-07-09 8:58 ` [U-Boot] [PATCH V2 4/6] mv_egiga: only randomize MAC on kirkwood Prafulla Wadaskar
2010-07-09 9:17 ` Albert ARIBAUD
2010-07-09 9:16 ` [U-Boot] [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile Prafulla Wadaskar
2010-07-09 9:54 ` Albert ARIBAUD
2010-07-09 11:11 ` Prafulla Wadaskar
2010-07-09 11:53 ` Albert ARIBAUD
2010-07-09 13:00 ` Albert ARIBAUD
2010-07-10 6:41 ` Prafulla Wadaskar
2010-07-09 11:51 ` [U-Boot] mv_egiga: effect on making struct members volatile(was: [PATCH V2 3/6] mv_egiga: bugfix: DMA issue fixed using volatile) Albert ARIBAUD
2010-07-09 9:08 ` [U-Boot] [PATCH V2 1/6] net: rename: kirkwood_egiga as mv_egiga Prafulla Wadaskar
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