* [PATCH] drm/i915: Round up the watermark entries
@ 2010-07-19 18:31 Chris Wilson
2010-07-19 18:37 ` [PATCH] drm/i915: Round up the watermark entries (v2) Chris Wilson
0 siblings, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2010-07-19 18:31 UTC (permalink / raw)
To: intel-gfx
Even though "we have enough padding that it should be ok", round up the
watermark entries to the next unit to be on the safe side...
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f674b7a..5661f70 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2727,7 +2727,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
*/
entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1000;
- entries_required /= wm->cacheline_size;
+ entries_required = (entries_requied + wm->cacheline_size - 1) / wm->cacheline_size;
DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
--
1.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH] drm/i915: Round up the watermark entries (v2)
2010-07-19 18:31 [PATCH] drm/i915: Round up the watermark entries Chris Wilson
@ 2010-07-19 18:37 ` Chris Wilson
2010-07-19 18:43 ` Jesse Barnes
2010-07-19 18:59 ` [PATCH] drm/i915: Round up the watermark entries (v3) Chris Wilson
0 siblings, 2 replies; 5+ messages in thread
From: Chris Wilson @ 2010-07-19 18:37 UTC (permalink / raw)
To: intel-gfx
Even though "we have enough padding that it should be ok", round up the
watermark entries to the next unit to be on the safe side...
v2: Use the DIV_ROUND_UP macro
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f674b7a..aae3686 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2727,7 +2727,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
*/
entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1000;
- entries_required /= wm->cacheline_size;
+ entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
--
1.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Round up the watermark entries (v2)
2010-07-19 18:37 ` [PATCH] drm/i915: Round up the watermark entries (v2) Chris Wilson
@ 2010-07-19 18:43 ` Jesse Barnes
2010-07-19 18:59 ` [PATCH] drm/i915: Round up the watermark entries (v3) Chris Wilson
1 sibling, 0 replies; 5+ messages in thread
From: Jesse Barnes @ 2010-07-19 18:43 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Mon, 19 Jul 2010 19:37:07 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Even though "we have enough padding that it should be ok", round up the
> watermark entries to the next unit to be on the safe side...
>
> v2: Use the DIV_ROUND_UP macro
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f674b7a..aae3686 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2727,7 +2727,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
> */
> entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
> 1000;
> - entries_required /= wm->cacheline_size;
> + entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
>
> DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
>
Looks good to me, thanks.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] drm/i915: Round up the watermark entries (v3)
2010-07-19 18:37 ` [PATCH] drm/i915: Round up the watermark entries (v2) Chris Wilson
2010-07-19 18:43 ` Jesse Barnes
@ 2010-07-19 18:59 ` Chris Wilson
2010-08-02 2:47 ` Eric Anholt
1 sibling, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2010-07-19 18:59 UTC (permalink / raw)
To: intel-gfx
Even though "we have enough padding that it should be ok", round up the
watermark entries to the next unit to be on the safe side...
v2: Use the DIV_ROUND_UP macro
v3: Spotted a few more missing round-ups.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 44 +++++++++++++++------------------
1 files changed, 20 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f674b7a..2cf5b47 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2727,7 +2727,7 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
*/
entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1000;
- entries_required /= wm->cacheline_size;
+ entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
@@ -2848,11 +2848,9 @@ static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
uint32_t dsparb = I915_READ(DSPARB);
int size;
- if (plane == 0)
- size = dsparb & 0x7f;
- else
- size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
- (dsparb & 0x7f);
+ size = dsparb & 0x7f;
+ if (plane)
+ size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
plane ? "B" : "A", size);
@@ -2866,11 +2864,9 @@ static int i85x_get_fifo_size(struct drm_device *dev, int plane)
uint32_t dsparb = I915_READ(DSPARB);
int size;
- if (plane == 0)
- size = dsparb & 0x1ff;
- else
- size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
- (dsparb & 0x1ff);
+ size = dsparb & 0x1ff;
+ if (plane)
+ size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
size >>= 1; /* Convert to cachelines */
DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
@@ -3002,12 +2998,12 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
*/
entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
1000;
- entries_required /= G4X_FIFO_LINE_SIZE;
+ entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
planea_wm = entries_required + planea_params.guard_size;
entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
1000;
- entries_required /= G4X_FIFO_LINE_SIZE;
+ entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
planeb_wm = entries_required + planeb_params.guard_size;
cursora_wm = cursorb_wm = 16;
@@ -3026,12 +3022,12 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
/* Use ns/us then divide to preserve precision */
sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
pixel_size * sr_hdisplay;
- sr_entries = roundup(sr_entries / cacheline_size, 1);
+ sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
entries_required = (((sr_latency_ns / line_time_us) +
1000) / 1000) * pixel_size * 64;
- entries_required = roundup(entries_required /
- g4x_cursor_wm_info.cacheline_size, 1);
+ entries_required = DIV_ROUND_UP(entries_required,
+ g4x_cursor_wm_info.cacheline_size);
cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
if (cursor_sr > g4x_cursor_wm_info.max_wm)
@@ -3082,7 +3078,7 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
/* Use ns/us then divide to preserve precision */
sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
pixel_size * sr_hdisplay;
- sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
+ sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
srwm = I965_FIFO_SIZE - sr_entries;
if (srwm < 0)
@@ -3091,8 +3087,8 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
pixel_size * 64;
- sr_entries = roundup(sr_entries /
- i965_cursor_wm_info.cacheline_size, 1);
+ sr_entries = DIV_ROUND_UP(sr_entries,
+ i965_cursor_wm_info.cacheline_size);
cursor_sr = i965_cursor_wm_info.fifo_size -
(sr_entries + i965_cursor_wm_info.guard_size);
@@ -3174,7 +3170,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
/* Use ns/us then divide to preserve precision */
sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
pixel_size * sr_hdisplay;
- sr_entries = roundup(sr_entries / cacheline_size, 1);
+ sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
srwm = total_size - sr_entries;
if (srwm < 0)
@@ -3263,7 +3259,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
entries_required = ((planea_clock / 1000) * pixel_size *
ILK_LP0_PLANE_LATENCY) / 1000;
entries_required = DIV_ROUND_UP(entries_required,
- ironlake_display_wm_info.cacheline_size);
+ ironlake_display_wm_info.cacheline_size);
planea_wm = entries_required +
ironlake_display_wm_info.guard_size;
@@ -3297,7 +3293,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
entries_required = ((planeb_clock / 1000) * pixel_size *
ILK_LP0_PLANE_LATENCY) / 1000;
entries_required = DIV_ROUND_UP(entries_required,
- ironlake_display_wm_info.cacheline_size);
+ ironlake_display_wm_info.cacheline_size);
planeb_wm = entries_required +
ironlake_display_wm_info.guard_size;
@@ -3346,14 +3342,14 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
/* calculate the self-refresh watermark for display plane */
entries_required = line_count * sr_hdisplay * pixel_size;
entries_required = DIV_ROUND_UP(entries_required,
- ironlake_display_srwm_info.cacheline_size);
+ ironlake_display_srwm_info.cacheline_size);
sr_wm = entries_required +
ironlake_display_srwm_info.guard_size;
/* calculate the self-refresh watermark for display cursor */
entries_required = line_count * pixel_size * 64;
entries_required = DIV_ROUND_UP(entries_required,
- ironlake_cursor_srwm_info.cacheline_size);
+ ironlake_cursor_srwm_info.cacheline_size);
cursor_wm = entries_required +
ironlake_cursor_srwm_info.guard_size;
--
1.7.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915: Round up the watermark entries (v3)
2010-07-19 18:59 ` [PATCH] drm/i915: Round up the watermark entries (v3) Chris Wilson
@ 2010-08-02 2:47 ` Eric Anholt
0 siblings, 0 replies; 5+ messages in thread
From: Eric Anholt @ 2010-08-02 2:47 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 436 bytes --]
On Mon, 19 Jul 2010 19:59:52 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Even though "we have enough padding that it should be ok", round up the
> watermark entries to the next unit to be on the safe side...
>
> v2: Use the DIV_ROUND_UP macro
> v3: Spotted a few more missing round-ups.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Applied to -next.
[-- Attachment #1.2: Type: application/pgp-signature, Size: 197 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2010-08-02 2:47 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2010-07-19 18:31 [PATCH] drm/i915: Round up the watermark entries Chris Wilson
2010-07-19 18:37 ` [PATCH] drm/i915: Round up the watermark entries (v2) Chris Wilson
2010-07-19 18:43 ` Jesse Barnes
2010-07-19 18:59 ` [PATCH] drm/i915: Round up the watermark entries (v3) Chris Wilson
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