* [Qemu-devel] [PATCH 1/8] [MIPS] qdev: convert i8042 to sysbus device
2010-09-08 20:39 [Qemu-devel] [PATCH v2 0/8] Convert some MIPS Jazz devices to qdev Hervé Poussineau
@ 2010-09-08 20:39 ` Hervé Poussineau
2010-09-25 9:47 ` Markus Armbruster
2010-09-08 20:39 ` [Qemu-devel] [PATCH 2/8] [MIPS] qdev: convert ds1225y nvram " Hervé Poussineau
` (6 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Hervé Poussineau @ 2010-09-08 20:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Hervé Poussineau
Use it in Jazz emulation
Remove i8042_mm_init() function, which is not used anymore
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
hw/mips_jazz.c | 3 ++-
hw/pc.h | 3 ---
hw/pckbd.c | 55 +++++++++++++++++++++++++++++++++++--------------------
3 files changed, 37 insertions(+), 24 deletions(-)
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 5d5305a..e306839 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -37,6 +37,7 @@
#include "loader.h"
#include "mc146818rtc.h"
#include "blockdev.h"
+#include "sysbus.h"
enum jazz_model_e
{
@@ -263,7 +264,7 @@ void mips_jazz_init (ram_addr_t ram_size,
cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
/* Keyboard (i8042) */
- i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
+ sysbus_create_varargs("rc4030-i8042", 0x80005000, rc4030[6], rc4030[7], NULL);
/* Serial ports */
if (serial_hds[0]) {
diff --git a/hw/pc.h b/hw/pc.h
index 63b0249..e078fd9 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -74,9 +74,6 @@ void *vmmouse_init(void *m);
/* pckbd.c */
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
-void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, ram_addr_t size,
- target_phys_addr_t mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
diff --git a/hw/pckbd.c b/hw/pckbd.c
index 6e4e406..33dc953 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -26,6 +26,7 @@
#include "pc.h"
#include "ps2.h"
#include "sysemu.h"
+#include "sysbus.h"
/* debug PC keyboard */
//#define DEBUG_KBD
@@ -424,26 +425,6 @@ static CPUWriteMemoryFunc * const kbd_mm_write[] = {
&kbd_mm_writeb,
};
-void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, ram_addr_t size,
- target_phys_addr_t mask)
-{
- KBDState *s = qemu_mallocz(sizeof(KBDState));
- int s_io_memory;
-
- s->irq_kbd = kbd_irq;
- s->irq_mouse = mouse_irq;
- s->mask = mask;
-
- vmstate_register(NULL, 0, &vmstate_kbd, s);
- s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);
- cpu_register_physical_memory(base, size, s_io_memory);
-
- s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
- s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
- qemu_register_reset(kbd_reset, s);
-}
-
typedef struct ISAKBDState {
ISADevice dev;
KBDState kbd;
@@ -503,8 +484,42 @@ static ISADeviceInfo i8042_info = {
.init = i8042_initfn,
};
+typedef struct SysBusKBDState {
+ SysBusDevice busdev;
+ KBDState kbd;
+} SysBusKBDState;
+
+static int i8042_sysbus_initfn(SysBusDevice *dev)
+{
+ KBDState *s = &FROM_SYSBUS(SysBusKBDState, dev)->kbd;
+ int s_io;
+
+ sysbus_init_irq(dev, &s->irq_kbd);
+ sysbus_init_irq(dev, &s->irq_mouse);
+
+ s_io = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);
+ sysbus_init_mmio(dev, 0x1000, s_io);
+
+ s->mask = 0x1;
+ s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
+ s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
+ qemu_register_reset(kbd_reset, s);
+
+ return 0;
+}
+
+static SysBusDeviceInfo i8042_sysbus_info = {
+ .qdev.name = "rc4030-i8042",
+ .qdev.size = sizeof(SysBusKBDState),
+ .init = i8042_sysbus_initfn,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
+
static void i8042_register(void)
{
isa_qdev_register(&i8042_info);
+ sysbus_register_withprop(&i8042_sysbus_info);
}
device_init(i8042_register)
--
1.7.1.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 1/8] [MIPS] qdev: convert i8042 to sysbus device
2010-09-08 20:39 ` [Qemu-devel] [PATCH 1/8] [MIPS] qdev: convert i8042 to sysbus device Hervé Poussineau
@ 2010-09-25 9:47 ` Markus Armbruster
0 siblings, 0 replies; 18+ messages in thread
From: Markus Armbruster @ 2010-09-25 9:47 UTC (permalink / raw)
To: Hervé Poussineau; +Cc: qemu-devel
Hervé Poussineau <hpoussin@reactos.org> writes:
> Use it in Jazz emulation
> Remove i8042_mm_init() function, which is not used anymore
>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> ---
> hw/mips_jazz.c | 3 ++-
> hw/pc.h | 3 ---
> hw/pckbd.c | 55 +++++++++++++++++++++++++++++++++++--------------------
> 3 files changed, 37 insertions(+), 24 deletions(-)
>
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index 5d5305a..e306839 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -37,6 +37,7 @@
> #include "loader.h"
> #include "mc146818rtc.h"
> #include "blockdev.h"
> +#include "sysbus.h"
>
> enum jazz_model_e
> {
> @@ -263,7 +264,7 @@ void mips_jazz_init (ram_addr_t ram_size,
> cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
>
> /* Keyboard (i8042) */
> - i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
> + sysbus_create_varargs("rc4030-i8042", 0x80005000, rc4030[6], rc4030[7], NULL);
>
> /* Serial ports */
> if (serial_hds[0]) {
> diff --git a/hw/pc.h b/hw/pc.h
> index 63b0249..e078fd9 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -74,9 +74,6 @@ void *vmmouse_init(void *m);
> /* pckbd.c */
>
> void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
> -void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
> - target_phys_addr_t base, ram_addr_t size,
> - target_phys_addr_t mask);
> void i8042_isa_mouse_fake_event(void *opaque);
> void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
>
> diff --git a/hw/pckbd.c b/hw/pckbd.c
> index 6e4e406..33dc953 100644
> --- a/hw/pckbd.c
> +++ b/hw/pckbd.c
> @@ -26,6 +26,7 @@
> #include "pc.h"
> #include "ps2.h"
> #include "sysemu.h"
> +#include "sysbus.h"
>
> /* debug PC keyboard */
> //#define DEBUG_KBD
> @@ -424,26 +425,6 @@ static CPUWriteMemoryFunc * const kbd_mm_write[] = {
> &kbd_mm_writeb,
> };
>
> -void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
> - target_phys_addr_t base, ram_addr_t size,
> - target_phys_addr_t mask)
> -{
> - KBDState *s = qemu_mallocz(sizeof(KBDState));
> - int s_io_memory;
> -
> - s->irq_kbd = kbd_irq;
> - s->irq_mouse = mouse_irq;
> - s->mask = mask;
> -
> - vmstate_register(NULL, 0, &vmstate_kbd, s);
> - s_io_memory = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);
> - cpu_register_physical_memory(base, size, s_io_memory);
> -
> - s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
> - s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
> - qemu_register_reset(kbd_reset, s);
> -}
> -
> typedef struct ISAKBDState {
> ISADevice dev;
> KBDState kbd;
> @@ -503,8 +484,42 @@ static ISADeviceInfo i8042_info = {
> .init = i8042_initfn,
> };
>
> +typedef struct SysBusKBDState {
> + SysBusDevice busdev;
> + KBDState kbd;
> +} SysBusKBDState;
> +
> +static int i8042_sysbus_initfn(SysBusDevice *dev)
> +{
> + KBDState *s = &FROM_SYSBUS(SysBusKBDState, dev)->kbd;
> + int s_io;
> +
> + sysbus_init_irq(dev, &s->irq_kbd);
> + sysbus_init_irq(dev, &s->irq_mouse);
> +
> + s_io = cpu_register_io_memory(kbd_mm_read, kbd_mm_write, s);
> + sysbus_init_mmio(dev, 0x1000, s_io);
> +
> + s->mask = 0x1;
> + s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
> + s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
> + qemu_register_reset(kbd_reset, s);
> +
> + return 0;
> +}
> +
> +static SysBusDeviceInfo i8042_sysbus_info = {
> + .qdev.name = "rc4030-i8042",
> + .qdev.size = sizeof(SysBusKBDState),
> + .init = i8042_sysbus_initfn,
> + .qdev.props = (Property[]) {
> + DEFINE_PROP_END_OF_LIST(),
> + },
> +};
> +
Shouldn't you initialize qdev.vmsd here?
> static void i8042_register(void)
> {
> isa_qdev_register(&i8042_info);
> + sysbus_register_withprop(&i8042_sysbus_info);
> }
> device_init(i8042_register)
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH 2/8] [MIPS] qdev: convert ds1225y nvram to sysbus device
2010-09-08 20:39 [Qemu-devel] [PATCH v2 0/8] Convert some MIPS Jazz devices to qdev Hervé Poussineau
2010-09-08 20:39 ` [Qemu-devel] [PATCH 1/8] [MIPS] qdev: convert i8042 to sysbus device Hervé Poussineau
@ 2010-09-08 20:39 ` Hervé Poussineau
2010-09-09 14:21 ` Blue Swirl
2010-09-25 9:52 ` Markus Armbruster
2010-09-08 20:39 ` [Qemu-devel] [PATCH 3/8] [MIPS] qdev: convert jazz-led " Hervé Poussineau
` (5 subsequent siblings)
7 siblings, 2 replies; 18+ messages in thread
From: Hervé Poussineau @ 2010-09-08 20:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Hervé Poussineau
Use it in Jazz emulation
Remove protection stuff, which doesn't belong to this device
Remove ds1225y_init() and ds1225y_set_protection() functions, which are not used anymore
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
hw/ds1225y.c | 151 ++++++++++++++++++++++++++++++--------------------------
hw/mips.h | 4 --
hw/mips_jazz.c | 4 +-
3 files changed, 83 insertions(+), 76 deletions(-)
diff --git a/hw/ds1225y.c b/hw/ds1225y.c
index 009d127..046d1ec 100644
--- a/hw/ds1225y.c
+++ b/hw/ds1225y.c
@@ -22,31 +22,34 @@
* THE SOFTWARE.
*/
-#include "hw.h"
-#include "mips.h"
-#include "nvram.h"
+#include "sysbus.h"
//#define DEBUG_NVRAM
-typedef struct ds1225y_t
-{
- uint32_t chip_size;
+#ifdef DEBUG_NVRAM
+#define DPRINTF(fmt, ...) \
+ do { printf("nvram: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+typedef struct {
+ DeviceState qdev;
+ int32_t chip_size;
+ char* filename;
QEMUFile *file;
uint8_t *contents;
- uint8_t protection;
-} ds1225y_t;
-
+} NvRamState;
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
- ds1225y_t *s = opaque;
+ NvRamState *s = opaque;
uint32_t val;
val = s->contents[addr];
-#ifdef DEBUG_NVRAM
- printf("nvram: read 0x%x at " TARGET_FMT_lx "\n", val, addr);
-#endif
+ DPRINTF("read 0x%x at " TARGET_FMT_plx "\n", val, addr);
+
return val;
}
@@ -70,11 +73,9 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
{
- ds1225y_t *s = opaque;
+ NvRamState *s = opaque;
-#ifdef DEBUG_NVRAM
- printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr);
-#endif
+ DPRINTF("write 0x%x at " TARGET_FMT_plx "\n", val, addr);
s->contents[addr] = val & 0xff;
if (s->file) {
@@ -98,34 +99,6 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
}
-static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- ds1225y_t *s = opaque;
-
- if (s->protection != 7) {
-#ifdef DEBUG_NVRAM
- printf("nvram: prevent write of 0x%x at " TARGET_FMT_lx "\n", val, addr);
-#endif
- return;
- }
-
- nvram_writeb(opaque, addr, val);
-}
-
-static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- nvram_writeb_protected(opaque, addr, val & 0xff);
- nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
-}
-
-static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
-{
- nvram_writeb_protected(opaque, addr, val & 0xff);
- nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
- nvram_writeb_protected(opaque, addr + 2, (val >> 16) & 0xff);
- nvram_writeb_protected(opaque, addr + 3, (val >> 24) & 0xff);
-}
-
static CPUReadMemoryFunc * const nvram_read[] = {
&nvram_readb,
&nvram_readw,
@@ -138,43 +111,81 @@ static CPUWriteMemoryFunc * const nvram_write[] = {
&nvram_writel,
};
-static CPUWriteMemoryFunc * const nvram_write_protected[] = {
- &nvram_writeb_protected,
- &nvram_writew_protected,
- &nvram_writel_protected,
+static int nvram_post_load(void *opaque, int version_id)
+{
+ NvRamState *s = opaque;
+
+ if (s->file) {
+ qemu_fclose(s->file);
+ }
+
+ /* Write back nvram contents */
+ s->file = qemu_fopen(s->filename, "wb");
+ if (s->file) {
+ /* Write back contents, as 'wb' mode cleaned the file */
+ qemu_put_buffer(s->file, s->contents, s->chip_size);
+ qemu_fflush(s->file);
+ }
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_nvram = {
+ .name = "nvram",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .post_load = nvram_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_VARRAY_INT32(contents, NvRamState, chip_size, 0, vmstate_info_uint8,
+ uint8_t),
+ VMSTATE_END_OF_LIST()
+ }
};
-/* Initialisation routine */
-void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
+typedef struct {
+ SysBusDevice busdev;
+ NvRamState nvram;
+} SysBusNvRamState;
+
+static int nvram_sysbus_initfn(SysBusDevice *dev)
{
- ds1225y_t *s;
- int mem_indexRW, mem_indexRP;
+ NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
QEMUFile *file;
+ int s_io;
- s = qemu_mallocz(sizeof(ds1225y_t));
- s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
s->contents = qemu_mallocz(s->chip_size);
- s->protection = 7;
+
+ s_io = cpu_register_io_memory(nvram_read, nvram_write, s);
+ sysbus_init_mmio(dev, s->chip_size, s_io);
/* Read current file */
- file = qemu_fopen(filename, "rb");
+ file = qemu_fopen(s->filename, "rb");
if (file) {
/* Read nvram contents */
qemu_get_buffer(file, s->contents, s->chip_size);
qemu_fclose(file);
}
- s->file = qemu_fopen(filename, "wb");
- if (s->file) {
- /* Write back contents, as 'wb' mode cleaned the file */
- qemu_put_buffer(s->file, s->contents, s->chip_size);
- qemu_fflush(s->file);
- }
+ nvram_post_load(s, 0);
- /* Read/write memory */
- mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s);
- cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);
- /* Read/write protected memory */
- mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s);
- cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP);
- return s;
+ return 0;
}
+
+static SysBusDeviceInfo nvram_sysbus_info = {
+ .qdev.name = "nvram",
+ .qdev.size = sizeof(SysBusNvRamState),
+ .qdev.vmsd = &vmstate_nvram,
+ .init = nvram_sysbus_initfn,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_INT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
+ DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
+
+static void nvram_register(void)
+{
+ sysbus_register_withprop(&nvram_sysbus_info);
+}
+
+device_init(nvram_register)
diff --git a/hw/mips.h b/hw/mips.h
index 617ea10..8f32ba0 100644
--- a/hw/mips.h
+++ b/hw/mips.h
@@ -8,10 +8,6 @@ PCIBus *pci_gt64120_init(qemu_irq *pic);
/* bonito.c */
PCIBus *bonito_init(qemu_irq *pic);
-/* ds1225y.c */
-void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
-void ds1225y_set_protection(void *opaque, int protection);
-
/* g364fb.c */
int g364fb_mm_init(target_phys_addr_t vram_base,
target_phys_addr_t ctrl_base, int it_shift,
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index e306839..06968d3 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -290,8 +290,8 @@ void mips_jazz_init (ram_addr_t ram_size,
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
audio_init(i8259);
- /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
- ds1225y_init(0x80009000, "nvram");
+ /* NVRAM */
+ sysbus_create_simple("nvram", 0x80009000, NULL);
/* LED indicator */
jazz_led_init(0x8000f000);
--
1.7.1.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 2/8] [MIPS] qdev: convert ds1225y nvram to sysbus device
2010-09-08 20:39 ` [Qemu-devel] [PATCH 2/8] [MIPS] qdev: convert ds1225y nvram " Hervé Poussineau
@ 2010-09-09 14:21 ` Blue Swirl
2010-09-25 9:52 ` Markus Armbruster
1 sibling, 0 replies; 18+ messages in thread
From: Blue Swirl @ 2010-09-09 14:21 UTC (permalink / raw)
To: Hervé Poussineau; +Cc: qemu-devel
2010/9/8 Hervé Poussineau <hpoussin@reactos.org>:
> Use it in Jazz emulation
> Remove protection stuff, which doesn't belong to this device
> Remove ds1225y_init() and ds1225y_set_protection() functions, which are not used anymore
>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> ---
> hw/ds1225y.c | 151 ++++++++++++++++++++++++++++++--------------------------
> hw/mips.h | 4 --
> hw/mips_jazz.c | 4 +-
> 3 files changed, 83 insertions(+), 76 deletions(-)
>
> diff --git a/hw/ds1225y.c b/hw/ds1225y.c
> index 009d127..046d1ec 100644
> --- a/hw/ds1225y.c
> +++ b/hw/ds1225y.c
> @@ -22,31 +22,34 @@
> * THE SOFTWARE.
> */
>
> -#include "hw.h"
> -#include "mips.h"
> -#include "nvram.h"
> +#include "sysbus.h"
>
> //#define DEBUG_NVRAM
>
> -typedef struct ds1225y_t
> -{
> - uint32_t chip_size;
> +#ifdef DEBUG_NVRAM
> +#define DPRINTF(fmt, ...) \
> + do { printf("nvram: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...) do {} while (0)
> +#endif
> +
> +typedef struct {
> + DeviceState qdev;
> + int32_t chip_size;
> + char* filename;
> QEMUFile *file;
> uint8_t *contents;
> - uint8_t protection;
> -} ds1225y_t;
> -
> +} NvRamState;
>
> static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
> {
> - ds1225y_t *s = opaque;
> + NvRamState *s = opaque;
> uint32_t val;
>
> val = s->contents[addr];
>
> -#ifdef DEBUG_NVRAM
> - printf("nvram: read 0x%x at " TARGET_FMT_lx "\n", val, addr);
> -#endif
> + DPRINTF("read 0x%x at " TARGET_FMT_plx "\n", val, addr);
> +
> return val;
> }
>
> @@ -70,11 +73,9 @@ static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
>
> static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
> {
> - ds1225y_t *s = opaque;
> + NvRamState *s = opaque;
>
> -#ifdef DEBUG_NVRAM
> - printf("nvram: write 0x%x at " TARGET_FMT_lx "\n", val, addr);
> -#endif
> + DPRINTF("write 0x%x at " TARGET_FMT_plx "\n", val, addr);
>
> s->contents[addr] = val & 0xff;
> if (s->file) {
> @@ -98,34 +99,6 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
> nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
> }
>
> -static void nvram_writeb_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
> -{
> - ds1225y_t *s = opaque;
> -
> - if (s->protection != 7) {
> -#ifdef DEBUG_NVRAM
> - printf("nvram: prevent write of 0x%x at " TARGET_FMT_lx "\n", val, addr);
> -#endif
> - return;
> - }
> -
> - nvram_writeb(opaque, addr, val);
> -}
> -
> -static void nvram_writew_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
> -{
> - nvram_writeb_protected(opaque, addr, val & 0xff);
> - nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
> -}
> -
> -static void nvram_writel_protected (void *opaque, target_phys_addr_t addr, uint32_t val)
> -{
> - nvram_writeb_protected(opaque, addr, val & 0xff);
> - nvram_writeb_protected(opaque, addr + 1, (val >> 8) & 0xff);
> - nvram_writeb_protected(opaque, addr + 2, (val >> 16) & 0xff);
> - nvram_writeb_protected(opaque, addr + 3, (val >> 24) & 0xff);
> -}
> -
> static CPUReadMemoryFunc * const nvram_read[] = {
> &nvram_readb,
> &nvram_readw,
> @@ -138,43 +111,81 @@ static CPUWriteMemoryFunc * const nvram_write[] = {
> &nvram_writel,
> };
>
> -static CPUWriteMemoryFunc * const nvram_write_protected[] = {
> - &nvram_writeb_protected,
> - &nvram_writew_protected,
> - &nvram_writel_protected,
> +static int nvram_post_load(void *opaque, int version_id)
> +{
> + NvRamState *s = opaque;
> +
> + if (s->file) {
> + qemu_fclose(s->file);
> + }
> +
> + /* Write back nvram contents */
> + s->file = qemu_fopen(s->filename, "wb");
How about ftruncate(fileno(s->file), 0)?
> + if (s->file) {
> + /* Write back contents, as 'wb' mode cleaned the file */
> + qemu_put_buffer(s->file, s->contents, s->chip_size);
> + qemu_fflush(s->file);
> + }
> +
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_nvram = {
> + .name = "nvram",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .minimum_version_id_old = 0,
> + .post_load = nvram_post_load,
> + .fields = (VMStateField []) {
> + VMSTATE_VARRAY_INT32(contents, NvRamState, chip_size, 0, vmstate_info_uint8,
> + uint8_t),
> + VMSTATE_END_OF_LIST()
> + }
> };
>
> -/* Initialisation routine */
> -void *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
> +typedef struct {
> + SysBusDevice busdev;
> + NvRamState nvram;
> +} SysBusNvRamState;
> +
> +static int nvram_sysbus_initfn(SysBusDevice *dev)
> {
> - ds1225y_t *s;
> - int mem_indexRW, mem_indexRP;
> + NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
> QEMUFile *file;
> + int s_io;
>
> - s = qemu_mallocz(sizeof(ds1225y_t));
> - s->chip_size = 0x2000; /* Fixed for ds1225y chip: 8 KiB */
> s->contents = qemu_mallocz(s->chip_size);
> - s->protection = 7;
> +
> + s_io = cpu_register_io_memory(nvram_read, nvram_write, s);
> + sysbus_init_mmio(dev, s->chip_size, s_io);
>
> /* Read current file */
> - file = qemu_fopen(filename, "rb");
> + file = qemu_fopen(s->filename, "rb");
> if (file) {
> /* Read nvram contents */
> qemu_get_buffer(file, s->contents, s->chip_size);
> qemu_fclose(file);
> }
> - s->file = qemu_fopen(filename, "wb");
> - if (s->file) {
> - /* Write back contents, as 'wb' mode cleaned the file */
> - qemu_put_buffer(s->file, s->contents, s->chip_size);
> - qemu_fflush(s->file);
> - }
> + nvram_post_load(s, 0);
>
> - /* Read/write memory */
> - mem_indexRW = cpu_register_io_memory(nvram_read, nvram_write, s);
> - cpu_register_physical_memory(mem_base, s->chip_size, mem_indexRW);
> - /* Read/write protected memory */
> - mem_indexRP = cpu_register_io_memory(nvram_read, nvram_write_protected, s);
> - cpu_register_physical_memory(mem_base + s->chip_size, s->chip_size, mem_indexRP);
> - return s;
> + return 0;
> }
> +
> +static SysBusDeviceInfo nvram_sysbus_info = {
> + .qdev.name = "nvram",
> + .qdev.size = sizeof(SysBusNvRamState),
> + .qdev.vmsd = &vmstate_nvram,
> + .init = nvram_sysbus_initfn,
> + .qdev.props = (Property[]) {
> + DEFINE_PROP_INT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
> + DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
> + DEFINE_PROP_END_OF_LIST(),
> + },
> +};
> +
> +static void nvram_register(void)
> +{
> + sysbus_register_withprop(&nvram_sysbus_info);
> +}
> +
> +device_init(nvram_register)
> diff --git a/hw/mips.h b/hw/mips.h
> index 617ea10..8f32ba0 100644
> --- a/hw/mips.h
> +++ b/hw/mips.h
> @@ -8,10 +8,6 @@ PCIBus *pci_gt64120_init(qemu_irq *pic);
> /* bonito.c */
> PCIBus *bonito_init(qemu_irq *pic);
>
> -/* ds1225y.c */
> -void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
> -void ds1225y_set_protection(void *opaque, int protection);
> -
> /* g364fb.c */
> int g364fb_mm_init(target_phys_addr_t vram_base,
> target_phys_addr_t ctrl_base, int it_shift,
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index e306839..06968d3 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -290,8 +290,8 @@ void mips_jazz_init (ram_addr_t ram_size,
> /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
> audio_init(i8259);
>
> - /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
> - ds1225y_init(0x80009000, "nvram");
> + /* NVRAM */
> + sysbus_create_simple("nvram", 0x80009000, NULL);
>
> /* LED indicator */
> jazz_led_init(0x8000f000);
> --
> 1.7.1.GIT
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 2/8] [MIPS] qdev: convert ds1225y nvram to sysbus device
2010-09-08 20:39 ` [Qemu-devel] [PATCH 2/8] [MIPS] qdev: convert ds1225y nvram " Hervé Poussineau
2010-09-09 14:21 ` Blue Swirl
@ 2010-09-25 9:52 ` Markus Armbruster
1 sibling, 0 replies; 18+ messages in thread
From: Markus Armbruster @ 2010-09-25 9:52 UTC (permalink / raw)
To: Hervé Poussineau; +Cc: qemu-devel
Hervé Poussineau <hpoussin@reactos.org> writes:
> Use it in Jazz emulation
> Remove protection stuff, which doesn't belong to this device
> Remove ds1225y_init() and ds1225y_set_protection() functions, which are not used anymore
>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
I think this would be easier to review if you split it up some, perhaps
cleanup such as DPRINTF(), removal of protection stuff, and qdev
conversion.
> ---
> hw/ds1225y.c | 151 ++++++++++++++++++++++++++++++--------------------------
> hw/mips.h | 4 --
> hw/mips_jazz.c | 4 +-
> 3 files changed, 83 insertions(+), 76 deletions(-)
>
> diff --git a/hw/ds1225y.c b/hw/ds1225y.c
> index 009d127..046d1ec 100644
> --- a/hw/ds1225y.c
> +++ b/hw/ds1225y.c
> @@ -22,31 +22,34 @@
> * THE SOFTWARE.
> */
>
> -#include "hw.h"
> -#include "mips.h"
> -#include "nvram.h"
> +#include "sysbus.h"
>
> //#define DEBUG_NVRAM
>
> -typedef struct ds1225y_t
> -{
> - uint32_t chip_size;
> +#ifdef DEBUG_NVRAM
> +#define DPRINTF(fmt, ...) \
> + do { printf("nvram: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...) do {} while (0)
> +#endif
> +
> +typedef struct {
> + DeviceState qdev;
> + int32_t chip_size;
You change chip_size from unsigned to signed. Why?
> + char* filename;
> QEMUFile *file;
> uint8_t *contents;
> - uint8_t protection;
> -} ds1225y_t;
> -
> +} NvRamState;
[...]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH 3/8] [MIPS] qdev: convert jazz-led to sysbus device
2010-09-08 20:39 [Qemu-devel] [PATCH v2 0/8] Convert some MIPS Jazz devices to qdev Hervé Poussineau
2010-09-08 20:39 ` [Qemu-devel] [PATCH 1/8] [MIPS] qdev: convert i8042 to sysbus device Hervé Poussineau
2010-09-08 20:39 ` [Qemu-devel] [PATCH 2/8] [MIPS] qdev: convert ds1225y nvram " Hervé Poussineau
@ 2010-09-08 20:39 ` Hervé Poussineau
2010-09-25 9:55 ` Markus Armbruster
2010-09-08 20:39 ` [Qemu-devel] [PATCH 4/8] [MIPS] qdev: Use qdev floppy disk controller in Jazz emulation Hervé Poussineau
` (4 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Hervé Poussineau @ 2010-09-08 20:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Hervé Poussineau
Use it in Jazz emulation
Remove jazz_led_init() function, which is not used anymore
Compile jazz_led.c file only once
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
Makefile.objs | 1 +
Makefile.target | 2 +-
default-configs/mips-softmmu.mak | 1 +
default-configs/mips64-softmmu.mak | 1 +
default-configs/mips64el-softmmu.mak | 1 +
default-configs/mipsel-softmmu.mak | 1 +
hw/jazz_led.c | 81 ++++++++++++++++++++--------------
hw/mips.h | 3 -
hw/mips_jazz.c | 2 +-
9 files changed, 55 insertions(+), 38 deletions(-)
diff --git a/Makefile.objs b/Makefile.objs
index 4a1eaa1..fb25c66 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -231,6 +231,7 @@ hw-obj-$(CONFIG_RC4030) += rc4030.o
hw-obj-$(CONFIG_DP8393X) += dp8393x.o
hw-obj-$(CONFIG_DS1225Y) += ds1225y.o
hw-obj-$(CONFIG_MIPSNET) += mipsnet.o
+hw-obj-$(CONFIG_JAZZ_LED) += jazz_led.o
# Sound
sound-obj-y =
diff --git a/Makefile.target b/Makefile.target
index 18826bb..78b37ab 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -223,7 +223,7 @@ obj-ppc-$(CONFIG_FDT) += device_tree.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
obj-mips-y += vga.o i8259.o
-obj-mips-y += g364fb.o jazz_led.o
+obj-mips-y += g364fb.o
obj-mips-y += gt64xxx.o mc146818rtc.o
obj-mips-y += cirrus_vga.o
obj-mips-$(CONFIG_FULONG) += bonito.o vt82c686.o mips_fulong2e.o
diff --git a/default-configs/mips-softmmu.mak b/default-configs/mips-softmmu.mak
index 3d0af83..69bb235 100644
--- a/default-configs/mips-softmmu.mak
+++ b/default-configs/mips-softmmu.mak
@@ -30,3 +30,4 @@ CONFIG_DP8393X=y
CONFIG_DS1225Y=y
CONFIG_MIPSNET=y
CONFIG_PFLASH_CFI01=y
+CONFIG_JAZZ_LED=y
diff --git a/default-configs/mips64-softmmu.mak b/default-configs/mips64-softmmu.mak
index 0030de4..0421bb6 100644
--- a/default-configs/mips64-softmmu.mak
+++ b/default-configs/mips64-softmmu.mak
@@ -30,3 +30,4 @@ CONFIG_DP8393X=y
CONFIG_DS1225Y=y
CONFIG_MIPSNET=y
CONFIG_PFLASH_CFI01=y
+CONFIG_JAZZ_LED=y
diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak
index fa2a3ff..b5d4406 100644
--- a/default-configs/mips64el-softmmu.mak
+++ b/default-configs/mips64el-softmmu.mak
@@ -32,3 +32,4 @@ CONFIG_DS1225Y=y
CONFIG_MIPSNET=y
CONFIG_PFLASH_CFI01=y
CONFIG_FULONG=y
+CONFIG_JAZZ_LED=y
diff --git a/default-configs/mipsel-softmmu.mak b/default-configs/mipsel-softmmu.mak
index 238b73a..0d9a093 100644
--- a/default-configs/mipsel-softmmu.mak
+++ b/default-configs/mipsel-softmmu.mak
@@ -30,3 +30,4 @@ CONFIG_DP8393X=y
CONFIG_DS1225Y=y
CONFIG_MIPSNET=y
CONFIG_PFLASH_CFI01=y
+CONFIG_JAZZ_LED=y
diff --git a/hw/jazz_led.c b/hw/jazz_led.c
index 4cb680c..f364301 100644
--- a/hw/jazz_led.c
+++ b/hw/jazz_led.c
@@ -22,10 +22,9 @@
* THE SOFTWARE.
*/
-#include "hw.h"
-#include "mips.h"
#include "console.h"
#include "pixel_ops.h"
+#include "sysbus.h"
//#define DEBUG_LED
@@ -43,6 +42,7 @@ typedef enum {
} screen_state_t;
typedef struct LedState {
+ DeviceState qdev;
uint8_t segments;
DisplayState *ds;
screen_state_t state;
@@ -70,30 +70,18 @@ static uint32_t led_readb(void *opaque, target_phys_addr_t addr)
static uint32_t led_readw(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
-#ifdef TARGET_WORDS_BIGENDIAN
- v = led_readb(opaque, addr) << 8;
- v |= led_readb(opaque, addr + 1);
-#else
v = led_readb(opaque, addr);
v |= led_readb(opaque, addr + 1) << 8;
-#endif
return v;
}
static uint32_t led_readl(void *opaque, target_phys_addr_t addr)
{
uint32_t v;
-#ifdef TARGET_WORDS_BIGENDIAN
- v = led_readb(opaque, addr) << 24;
- v |= led_readb(opaque, addr + 1) << 16;
- v |= led_readb(opaque, addr + 2) << 8;
- v |= led_readb(opaque, addr + 3);
-#else
v = led_readb(opaque, addr);
v |= led_readb(opaque, addr + 1) << 8;
v |= led_readb(opaque, addr + 2) << 16;
v |= led_readb(opaque, addr + 3) << 24;
-#endif
return v;
}
@@ -116,28 +104,16 @@ static void led_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
static void led_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- led_writeb(opaque, addr, (val >> 8) & 0xff);
- led_writeb(opaque, addr + 1, val & 0xff);
-#else
led_writeb(opaque, addr, val & 0xff);
led_writeb(opaque, addr + 1, (val >> 8) & 0xff);
-#endif
}
static void led_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
-#ifdef TARGET_WORDS_BIGENDIAN
- led_writeb(opaque, addr, (val >> 24) & 0xff);
- led_writeb(opaque, addr + 1, (val >> 16) & 0xff);
- led_writeb(opaque, addr + 2, (val >> 8) & 0xff);
- led_writeb(opaque, addr + 3, val & 0xff);
-#else
led_writeb(opaque, addr, val & 0xff);
led_writeb(opaque, addr + 1, (val >> 8) & 0xff);
led_writeb(opaque, addr + 2, (val >> 16) & 0xff);
led_writeb(opaque, addr + 3, (val >> 24) & 0xff);
-#endif
}
static CPUReadMemoryFunc * const led_read[3] = {
@@ -307,21 +283,60 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata)
dpy_update(s->ds, 0, 0, 2, 1);
}
-void jazz_led_init(target_phys_addr_t base)
+static int led_post_load(void *opaque, int version_id)
{
- LedState *s;
- int io;
+ LedState *s = opaque;
- s = qemu_mallocz(sizeof(LedState));
+ jazz_led_invalidate_display(s);
+ return 0;
+}
- s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
+static const VMStateDescription vmstate_led = {
+ .name = "jazz-led",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .post_load = led_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT8(segments, LedState),
+ VMSTATE_END_OF_LIST()
+ }
+};
- io = cpu_register_io_memory(led_read, led_write, s);
- cpu_register_physical_memory(base, 1, io);
+typedef struct {
+ SysBusDevice busdev;
+ LedState leds;
+} SysBusLedState;
+
+static int led_sysbus_initfn(SysBusDevice *dev)
+{
+ LedState *s = &FROM_SYSBUS(SysBusLedState, dev)->leds;
+ int s_io;
+
+ s_io = cpu_register_io_memory(led_read, led_write, s);
+ sysbus_init_mmio(dev, 0x1000, s_io);
s->ds = graphic_console_init(jazz_led_update_display,
jazz_led_invalidate_display,
jazz_led_screen_dump,
jazz_led_text_update, s);
qemu_console_resize(s->ds, 60, 80);
+
+ led_post_load(s, 0);
+
+ return 0;
}
+
+static SysBusDeviceInfo led_sysbus_info = {
+ .qdev.name = "jazz-led",
+ .qdev.size = sizeof(SysBusLedState),
+ .qdev.vmsd = &vmstate_led,
+ .init = led_sysbus_initfn,
+};
+
+static void led_register(void)
+{
+ sysbus_register_withprop(&led_sysbus_info);
+}
+
+device_init(led_register)
diff --git a/hw/mips.h b/hw/mips.h
index 8f32ba0..285f7dc 100644
--- a/hw/mips.h
+++ b/hw/mips.h
@@ -16,9 +16,6 @@ int g364fb_mm_init(target_phys_addr_t vram_base,
/* mipsnet.c */
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
-/* jazz_led.c */
-extern void jazz_led_init(target_phys_addr_t base);
-
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 06968d3..0af4044 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -294,7 +294,7 @@ void mips_jazz_init (ram_addr_t ram_size,
sysbus_create_simple("nvram", 0x80009000, NULL);
/* LED indicator */
- jazz_led_init(0x8000f000);
+ sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}
static
--
1.7.1.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 3/8] [MIPS] qdev: convert jazz-led to sysbus device
2010-09-08 20:39 ` [Qemu-devel] [PATCH 3/8] [MIPS] qdev: convert jazz-led " Hervé Poussineau
@ 2010-09-25 9:55 ` Markus Armbruster
0 siblings, 0 replies; 18+ messages in thread
From: Markus Armbruster @ 2010-09-25 9:55 UTC (permalink / raw)
To: Hervé Poussineau; +Cc: qemu-devel
Hervé Poussineau <hpoussin@reactos.org> writes:
> Use it in Jazz emulation
> Remove jazz_led_init() function, which is not used anymore
> Compile jazz_led.c file only once
[...]
> diff --git a/hw/jazz_led.c b/hw/jazz_led.c
> index 4cb680c..f364301 100644
> --- a/hw/jazz_led.c
> +++ b/hw/jazz_led.c
[...]
> @@ -70,30 +70,18 @@ static uint32_t led_readb(void *opaque, target_phys_addr_t addr)
> static uint32_t led_readw(void *opaque, target_phys_addr_t addr)
> {
> uint32_t v;
> -#ifdef TARGET_WORDS_BIGENDIAN
> - v = led_readb(opaque, addr) << 8;
> - v |= led_readb(opaque, addr + 1);
> -#else
> v = led_readb(opaque, addr);
> v |= led_readb(opaque, addr + 1) << 8;
> -#endif
> return v;
> }
Stupid question: why can you drop the #if here?
[...]
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH 4/8] [MIPS] qdev: Use qdev floppy disk controller in Jazz emulation
2010-09-08 20:39 [Qemu-devel] [PATCH v2 0/8] Convert some MIPS Jazz devices to qdev Hervé Poussineau
` (2 preceding siblings ...)
2010-09-08 20:39 ` [Qemu-devel] [PATCH 3/8] [MIPS] qdev: convert jazz-led " Hervé Poussineau
@ 2010-09-08 20:39 ` Hervé Poussineau
2010-09-08 20:39 ` [Qemu-devel] [PATCH 5/8] [MIPS] qdev: convert ISA VGA MM to sysbus device Hervé Poussineau
` (3 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Hervé Poussineau @ 2010-09-08 20:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Hervé Poussineau
Remove fdctrl_init_sysbus() function, which is not used anymore
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
hw/fdc.c | 24 ------------------------
hw/fdc.h | 2 --
hw/mips_jazz.c | 10 +---------
3 files changed, 1 insertions(+), 35 deletions(-)
diff --git a/hw/fdc.c b/hw/fdc.c
index c159dcb..57d7e06 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -1889,30 +1889,6 @@ FDCtrl *fdctrl_init_isa(DriveInfo **fds)
return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
}
-FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base, DriveInfo **fds)
-{
- FDCtrl *fdctrl;
- DeviceState *dev;
- FDCtrlSysBus *sys;
-
- dev = qdev_create(NULL, "sysbus-fdc");
- sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
- fdctrl = &sys->state;
- fdctrl->dma_chann = dma_chann; /* FIXME */
- if (fds[0]) {
- qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
- }
- if (fds[1]) {
- qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
- }
- qdev_init_nofail(dev);
- sysbus_connect_irq(&sys->busdev, 0, irq);
- sysbus_mmio_map(&sys->busdev, 0, mmio_base);
-
- return fdctrl;
-}
-
FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
DriveInfo **fds, qemu_irq *fdc_tc)
{
diff --git a/hw/fdc.h b/hw/fdc.h
index 242730a..c99e08a 100644
--- a/hw/fdc.h
+++ b/hw/fdc.h
@@ -7,8 +7,6 @@
typedef struct FDCtrl FDCtrl;
FDCtrl *fdctrl_init_isa(DriveInfo **fds);
-FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
- target_phys_addr_t mmio_base, DriveInfo **fds);
FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
DriveInfo **fds, qemu_irq *fdc_tc);
int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num);
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 0af4044..5c66cd4 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -137,7 +137,6 @@ void mips_jazz_init (ram_addr_t ram_size,
int s_rtc, s_dma_dummy;
NICInfo *nd;
PITState *pit;
- DriveInfo *fds[MAX_FD];
qemu_irq esp_reset;
qemu_irq *cpu_exit_irq;
ram_addr_t ram_offset;
@@ -249,14 +248,7 @@ void mips_jazz_init (ram_addr_t ram_size,
rc4030[5], &esp_reset);
/* Floppy */
- if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
- fprintf(stderr, "qemu: too many floppy drives\n");
- exit(1);
- }
- for (n = 0; n < MAX_FD; n++) {
- fds[n] = drive_get(IF_FLOPPY, 0, n);
- }
- fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
+ sysbus_create_simple("sysbus-fdc", 0x80003000, rc4030[1]);
/* Real time clock */
rtc_init(1980, NULL);
--
1.7.1.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH 5/8] [MIPS] qdev: convert ISA VGA MM to sysbus device
2010-09-08 20:39 [Qemu-devel] [PATCH v2 0/8] Convert some MIPS Jazz devices to qdev Hervé Poussineau
` (3 preceding siblings ...)
2010-09-08 20:39 ` [Qemu-devel] [PATCH 4/8] [MIPS] qdev: Use qdev floppy disk controller in Jazz emulation Hervé Poussineau
@ 2010-09-08 20:39 ` Hervé Poussineau
2010-09-09 14:28 ` Blue Swirl
2010-09-08 20:39 ` [Qemu-devel] [PATCH 6/8] [MIPS] qdev: convert g364fb " Hervé Poussineau
` (2 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Hervé Poussineau @ 2010-09-08 20:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Hervé Poussineau
Use it in Jazz emulation
Remove isa_vga_mm_init() function, which is not used anymore
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
hw/mips_jazz.c | 2 +-
hw/pc.h | 2 -
hw/vga-isa-mm.c | 94 ++++++++++++++++++++++++++++++++-----------------------
3 files changed, 56 insertions(+), 42 deletions(-)
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 5c66cd4..98567d2 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -218,7 +218,7 @@ void mips_jazz_init (ram_addr_t ram_size,
g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
break;
case JAZZ_PICA61:
- isa_vga_mm_init(0x40000000, 0x60000000, 0);
+ sysbus_create_simple("sysbus-vga", 0x60000000, NULL);
break;
default:
break;
diff --git a/hw/pc.h b/hw/pc.h
index e078fd9..946ae78 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -153,8 +153,6 @@ extern enum vga_retrace_method vga_retrace_method;
int isa_vga_init(void);
int pci_vga_init(PCIBus *bus,
unsigned long vga_bios_offset, int vga_bios_size);
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift);
/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus);
diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c
index 680b557..ecd6a41 100644
--- a/hw/vga-isa-mm.c
+++ b/hw/vga-isa-mm.c
@@ -21,62 +21,58 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "hw.h"
+
#include "console.h"
-#include "pc.h"
#include "vga_int.h"
#include "pixel_ops.h"
-#include "qemu-timer.h"
+#include "sysbus.h"
-typedef struct ISAVGAMMState {
- VGACommonState vga;
- int it_shift;
-} ISAVGAMMState;
+#define VRAM_BASE 0x40000000
/* Memory mapped interface */
static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
{
- ISAVGAMMState *s = opaque;
+ VGACommonState *s = opaque;
- return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xff;
+ return vga_ioport_read(s, addr) & 0xff;
}
static void vga_mm_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ISAVGAMMState *s = opaque;
+ VGACommonState *s = opaque;
- vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
+ vga_ioport_write(s, addr, value & 0xff);
}
static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
{
- ISAVGAMMState *s = opaque;
+ VGACommonState *s = opaque;
- return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xffff;
+ return vga_ioport_read(s, addr) & 0xffff;
}
static void vga_mm_writew (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ISAVGAMMState *s = opaque;
+ VGACommonState *s = opaque;
- vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
+ vga_ioport_write(s, addr, value & 0xffff);
}
static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
{
- ISAVGAMMState *s = opaque;
+ VGACommonState *s = opaque;
- return vga_ioport_read(&s->vga, addr >> s->it_shift);
+ return vga_ioport_read(s, addr);
}
static void vga_mm_writel (void *opaque,
target_phys_addr_t addr, uint32_t value)
{
- ISAVGAMMState *s = opaque;
+ VGACommonState *s = opaque;
- vga_ioport_write(&s->vga, addr >> s->it_shift, value);
+ vga_ioport_write(s, addr, value);
}
static CPUReadMemoryFunc * const vga_mm_read_ctrl[] = {
@@ -91,36 +87,56 @@ static CPUWriteMemoryFunc * const vga_mm_write_ctrl[] = {
&vga_mm_writel,
};
-static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
+typedef struct {
+ SysBusDevice busdev;
+ VGACommonState vga;
+} SysBusVGAState;
+
+static const VMStateDescription vmstate_vga = {
+ .name = "sysbus-vga",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .fields = (VMStateField []) {
+ VMSTATE_STRUCT(vga, SysBusVGAState, 0, vmstate_vga_common, VGACommonState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static int vga_sysbus_initfn(SysBusDevice *dev)
{
+ VGACommonState *s = &FROM_SYSBUS(SysBusVGAState, dev)->vga;
int s_ioport_ctrl, vga_io_memory;
- s->it_shift = it_shift;
+ vga_common_init(s, VGA_RAM_SIZE);
+ s->bank_offset = 0;
+
s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s);
vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
- vmstate_register(NULL, 0, &vmstate_vga_common, s);
+ cpu_register_physical_memory(VRAM_BASE + 0x000a0000, 0x20000, vga_io_memory);
+ qemu_register_coalesced_mmio(VRAM_BASE + 0x000a0000, 0x20000);
- cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
- s->vga.bank_offset = 0;
- cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
- qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
-}
+ sysbus_init_mmio(dev, 0x100000, s_ioport_ctrl);
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift)
-{
- ISAVGAMMState *s;
+ s->ds = graphic_console_init(s->update, s->invalidate,
+ s->screen_dump, s->text_update, s);
- s = qemu_mallocz(sizeof(*s));
+ vga_init_vbe(s);
- vga_common_init(&s->vga, VGA_RAM_SIZE);
- vga_mm_init(s, vram_base, ctrl_base, it_shift);
+ return 0;
+}
- s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
- s->vga.screen_dump, s->vga.text_update, s);
+static SysBusDeviceInfo vga_sysbus_info = {
+ .qdev.name = "sysbus-vga",
+ .qdev.size = sizeof(SysBusVGAState),
+ .qdev.vmsd = &vmstate_vga,
+ .init = vga_sysbus_initfn,
+};
- vga_init_vbe(&s->vga);
- return 0;
+static void vga_register(void)
+{
+ sysbus_register_withprop(&vga_sysbus_info);
}
+
+device_init(vga_register)
--
1.7.1.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 5/8] [MIPS] qdev: convert ISA VGA MM to sysbus device
2010-09-08 20:39 ` [Qemu-devel] [PATCH 5/8] [MIPS] qdev: convert ISA VGA MM to sysbus device Hervé Poussineau
@ 2010-09-09 14:28 ` Blue Swirl
0 siblings, 0 replies; 18+ messages in thread
From: Blue Swirl @ 2010-09-09 14:28 UTC (permalink / raw)
To: Hervé Poussineau; +Cc: qemu-devel
2010/9/8 Hervé Poussineau <hpoussin@reactos.org>:
> Use it in Jazz emulation
> Remove isa_vga_mm_init() function, which is not used anymore
>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> ---
> hw/mips_jazz.c | 2 +-
> hw/pc.h | 2 -
> hw/vga-isa-mm.c | 94 ++++++++++++++++++++++++++++++++-----------------------
> 3 files changed, 56 insertions(+), 42 deletions(-)
>
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index 5c66cd4..98567d2 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -218,7 +218,7 @@ void mips_jazz_init (ram_addr_t ram_size,
> g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
> break;
> case JAZZ_PICA61:
> - isa_vga_mm_init(0x40000000, 0x60000000, 0);
> + sysbus_create_simple("sysbus-vga", 0x60000000, NULL);
> break;
> default:
> break;
> diff --git a/hw/pc.h b/hw/pc.h
> index e078fd9..946ae78 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -153,8 +153,6 @@ extern enum vga_retrace_method vga_retrace_method;
> int isa_vga_init(void);
> int pci_vga_init(PCIBus *bus,
> unsigned long vga_bios_offset, int vga_bios_size);
> -int isa_vga_mm_init(target_phys_addr_t vram_base,
> - target_phys_addr_t ctrl_base, int it_shift);
>
> /* cirrus_vga.c */
> void pci_cirrus_vga_init(PCIBus *bus);
> diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c
> index 680b557..ecd6a41 100644
> --- a/hw/vga-isa-mm.c
> +++ b/hw/vga-isa-mm.c
> @@ -21,62 +21,58 @@
> * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> * THE SOFTWARE.
> */
> -#include "hw.h"
> +
> #include "console.h"
> -#include "pc.h"
> #include "vga_int.h"
> #include "pixel_ops.h"
> -#include "qemu-timer.h"
> +#include "sysbus.h"
>
> -typedef struct ISAVGAMMState {
> - VGACommonState vga;
> - int it_shift;
> -} ISAVGAMMState;
> +#define VRAM_BASE 0x40000000
>
> /* Memory mapped interface */
> static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
> {
> - ISAVGAMMState *s = opaque;
> + VGACommonState *s = opaque;
>
> - return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xff;
> + return vga_ioport_read(s, addr) & 0xff;
> }
>
> static void vga_mm_writeb (void *opaque,
> target_phys_addr_t addr, uint32_t value)
> {
> - ISAVGAMMState *s = opaque;
> + VGACommonState *s = opaque;
>
> - vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xff);
> + vga_ioport_write(s, addr, value & 0xff);
> }
>
> static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
> {
> - ISAVGAMMState *s = opaque;
> + VGACommonState *s = opaque;
>
> - return vga_ioport_read(&s->vga, addr >> s->it_shift) & 0xffff;
> + return vga_ioport_read(s, addr) & 0xffff;
> }
>
> static void vga_mm_writew (void *opaque,
> target_phys_addr_t addr, uint32_t value)
> {
> - ISAVGAMMState *s = opaque;
> + VGACommonState *s = opaque;
>
> - vga_ioport_write(&s->vga, addr >> s->it_shift, value & 0xffff);
> + vga_ioport_write(s, addr, value & 0xffff);
> }
>
> static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
> {
> - ISAVGAMMState *s = opaque;
> + VGACommonState *s = opaque;
>
> - return vga_ioport_read(&s->vga, addr >> s->it_shift);
> + return vga_ioport_read(s, addr);
> }
>
> static void vga_mm_writel (void *opaque,
> target_phys_addr_t addr, uint32_t value)
> {
> - ISAVGAMMState *s = opaque;
> + VGACommonState *s = opaque;
>
> - vga_ioport_write(&s->vga, addr >> s->it_shift, value);
> + vga_ioport_write(s, addr, value);
> }
>
> static CPUReadMemoryFunc * const vga_mm_read_ctrl[] = {
> @@ -91,36 +87,56 @@ static CPUWriteMemoryFunc * const vga_mm_write_ctrl[] = {
> &vga_mm_writel,
> };
>
> -static void vga_mm_init(ISAVGAMMState *s, target_phys_addr_t vram_base,
> - target_phys_addr_t ctrl_base, int it_shift)
> +typedef struct {
> + SysBusDevice busdev;
> + VGACommonState vga;
> +} SysBusVGAState;
> +
> +static const VMStateDescription vmstate_vga = {
> + .name = "sysbus-vga",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .minimum_version_id_old = 0,
> + .fields = (VMStateField []) {
> + VMSTATE_STRUCT(vga, SysBusVGAState, 0, vmstate_vga_common, VGACommonState),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static int vga_sysbus_initfn(SysBusDevice *dev)
> {
> + VGACommonState *s = &FROM_SYSBUS(SysBusVGAState, dev)->vga;
> int s_ioport_ctrl, vga_io_memory;
>
> - s->it_shift = it_shift;
> + vga_common_init(s, VGA_RAM_SIZE);
> + s->bank_offset = 0;
> +
> s_ioport_ctrl = cpu_register_io_memory(vga_mm_read_ctrl, vga_mm_write_ctrl, s);
> vga_io_memory = cpu_register_io_memory(vga_mem_read, vga_mem_write, s);
>
> - vmstate_register(NULL, 0, &vmstate_vga_common, s);
> + cpu_register_physical_memory(VRAM_BASE + 0x000a0000, 0x20000, vga_io_memory);
> + qemu_register_coalesced_mmio(VRAM_BASE + 0x000a0000, 0x20000);
>
> - cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
> - s->vga.bank_offset = 0;
> - cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
> - qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
These should be created with sysbus_init_mmio(), but that doesn't
handle MMIO coalescing. Perhaps we need sysbus_init_coalesced_mmio().
> -}
> + sysbus_init_mmio(dev, 0x100000, s_ioport_ctrl);
>
> -int isa_vga_mm_init(target_phys_addr_t vram_base,
> - target_phys_addr_t ctrl_base, int it_shift)
> -{
> - ISAVGAMMState *s;
> + s->ds = graphic_console_init(s->update, s->invalidate,
> + s->screen_dump, s->text_update, s);
>
> - s = qemu_mallocz(sizeof(*s));
> + vga_init_vbe(s);
>
> - vga_common_init(&s->vga, VGA_RAM_SIZE);
> - vga_mm_init(s, vram_base, ctrl_base, it_shift);
> + return 0;
> +}
>
> - s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate,
> - s->vga.screen_dump, s->vga.text_update, s);
> +static SysBusDeviceInfo vga_sysbus_info = {
> + .qdev.name = "sysbus-vga",
> + .qdev.size = sizeof(SysBusVGAState),
> + .qdev.vmsd = &vmstate_vga,
> + .init = vga_sysbus_initfn,
> +};
>
> - vga_init_vbe(&s->vga);
> - return 0;
> +static void vga_register(void)
> +{
> + sysbus_register_withprop(&vga_sysbus_info);
> }
> +
> +device_init(vga_register)
> --
> 1.7.1.GIT
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH 6/8] [MIPS] qdev: convert g364fb to sysbus device
2010-09-08 20:39 [Qemu-devel] [PATCH v2 0/8] Convert some MIPS Jazz devices to qdev Hervé Poussineau
` (4 preceding siblings ...)
2010-09-08 20:39 ` [Qemu-devel] [PATCH 5/8] [MIPS] qdev: convert ISA VGA MM to sysbus device Hervé Poussineau
@ 2010-09-08 20:39 ` Hervé Poussineau
2010-09-09 14:32 ` Blue Swirl
2010-09-08 20:39 ` [Qemu-devel] [PATCH 7/8] [MIPS] qdev: convert jazz irq controller " Hervé Poussineau
2010-09-08 20:39 ` [Qemu-devel] [PATCH 8/8] [MIPS] qdev: convert rc4030 " Hervé Poussineau
7 siblings, 1 reply; 18+ messages in thread
From: Hervé Poussineau @ 2010-09-08 20:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Hervé Poussineau
Use it in Jazz emulation
Remove g364fb_mm_init() function, which is not used anymore
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
hw/g364fb.c | 120 +++++++++++++++++++++++++++++--------------------------
hw/mips.h | 5 --
hw/mips_jazz.c | 2 +-
3 files changed, 64 insertions(+), 63 deletions(-)
diff --git a/hw/g364fb.c b/hw/g364fb.c
index 3c8fb98..10c53fc 100644
--- a/hw/g364fb.c
+++ b/hw/g364fb.c
@@ -17,10 +17,9 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#include "hw.h"
-#include "mips.h"
#include "console.h"
#include "pixel_ops.h"
+#include "sysbus.h"
//#define DEBUG_G364
@@ -33,11 +32,14 @@ do { printf("g364: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0)
+#define VRAM_BASE 0x40000000
+
typedef struct G364State {
+ DeviceState qdev;
/* hardware */
uint8_t *vram;
ram_addr_t vram_offset;
- int vram_size;
+ uint32_t vram_size;
qemu_irq irq;
/* registers */
uint8_t color_palette[256][3];
@@ -279,9 +281,8 @@ static inline void g364fb_invalidate_display(void *opaque)
}
}
-static void g364fb_reset(void *opaque)
+static void g364fb_reset(G364State *s)
{
- G364State *s = opaque;
qemu_irq_lower(s->irq);
memset(s->color_palette, 0, sizeof(s->color_palette));
@@ -292,7 +293,7 @@ static void g364fb_reset(void *opaque)
s->top_of_screen = 0;
s->width = s->height = 0;
memset(s->vram, 0, s->vram_size);
- g364fb_invalidate_display(opaque);
+ g364fb_invalidate_display(s);
}
static void g364fb_screen_dump(void *opaque, const char *filename)
@@ -534,28 +535,9 @@ static CPUWriteMemoryFunc * const g364fb_ctrl_write[3] = {
g364fb_ctrl_writel,
};
-static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
+static int g364fb_post_load(void *opaque, int version_id)
{
G364State *s = opaque;
- unsigned int i, vram_size;
-
- if (version_id != 1)
- return -EINVAL;
-
- vram_size = qemu_get_be32(f);
- if (vram_size < s->vram_size)
- return -EINVAL;
- qemu_get_buffer(f, s->vram, s->vram_size);
- for (i = 0; i < 256; i++)
- qemu_get_buffer(f, s->color_palette[i], 3);
- for (i = 0; i < 3; i++)
- qemu_get_buffer(f, s->cursor_palette[i], 3);
- qemu_get_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
- s->cursor_position = qemu_get_be32(f);
- s->ctla = qemu_get_be32(f);
- s->top_of_screen = qemu_get_be32(f);
- s->width = qemu_get_be32(f);
- s->height = qemu_get_be32(f);
/* force refresh */
g364fb_update_depth(s);
@@ -564,51 +546,75 @@ static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
-static void g364fb_save(QEMUFile *f, void *opaque)
-{
- G364State *s = opaque;
- int i;
+static const VMStateDescription vmstate_g364fb = {
+ .name = "g364fb",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .post_load = g364fb_post_load,
+ .fields = (VMStateField []) {
+ /* FIXME: vram? */
+ VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
+ VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
+ VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
+ VMSTATE_UINT32(cursor_position, G364State),
+ VMSTATE_UINT32(ctla, G364State),
+ VMSTATE_UINT32(top_of_screen, G364State),
+ VMSTATE_UINT32(width, G364State),
+ VMSTATE_UINT32(height, G364State),
+ VMSTATE_END_OF_LIST()
+ }
+};
- qemu_put_be32(f, s->vram_size);
- qemu_put_buffer(f, s->vram, s->vram_size);
- for (i = 0; i < 256; i++)
- qemu_put_buffer(f, s->color_palette[i], 3);
- for (i = 0; i < 3; i++)
- qemu_put_buffer(f, s->cursor_palette[i], 3);
- qemu_put_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
- qemu_put_be32(f, s->cursor_position);
- qemu_put_be32(f, s->ctla);
- qemu_put_be32(f, s->top_of_screen);
- qemu_put_be32(f, s->width);
- qemu_put_be32(f, s->height);
-}
+typedef struct {
+ SysBusDevice busdev;
+ G364State g364;
+} SysBusG364State;
-int g364fb_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
- qemu_irq irq)
+static int g364fb_sysbus_initfn(SysBusDevice *dev)
{
- G364State *s;
+ G364State *s = &FROM_SYSBUS(SysBusG364State, dev)->g364;
int io_ctrl;
- s = qemu_mallocz(sizeof(G364State));
-
- s->vram_size = 8 * 1024 * 1024;
s->vram_offset = qemu_ram_alloc(NULL, "g364fb.vram", s->vram_size);
s->vram = qemu_get_ram_ptr(s->vram_offset);
- s->irq = irq;
-
- qemu_register_reset(g364fb_reset, s);
- register_savevm(NULL, "g364fb", 0, 1, g364fb_save, g364fb_load, s);
- g364fb_reset(s);
+ sysbus_init_irq(dev, &s->irq);
s->ds = graphic_console_init(g364fb_update_display,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
- cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
+ cpu_register_physical_memory(VRAM_BASE, s->vram_size, s->vram_offset);
io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s);
- cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
+ sysbus_init_mmio(dev, 0x200000, io_ctrl);
+
+ g364fb_post_load(s, 0);
return 0;
}
+
+static void g364fb_sysbus_reset(DeviceState *d)
+{
+ G364State *s = &container_of(d, SysBusG364State, busdev.qdev)->g364;
+ g364fb_reset(s);
+}
+
+static SysBusDeviceInfo g364fb_sysbus_info = {
+ .qdev.name = "g364",
+ .qdev.size = sizeof(SysBusG364State),
+ .qdev.vmsd = &vmstate_g364fb,
+ .qdev.reset = g364fb_sysbus_reset,
+ .init = g364fb_sysbus_initfn,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_HEX32("vram_size", SysBusG364State, g364.vram_size, 8 * 1024 * 1024),
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
+
+static void g364fb_register(void)
+{
+ sysbus_register_withprop(&g364fb_sysbus_info);
+}
+
+device_init(g364fb_register)
diff --git a/hw/mips.h b/hw/mips.h
index 285f7dc..75b7c3d 100644
--- a/hw/mips.h
+++ b/hw/mips.h
@@ -8,11 +8,6 @@ PCIBus *pci_gt64120_init(qemu_irq *pic);
/* bonito.c */
PCIBus *bonito_init(qemu_irq *pic);
-/* g364fb.c */
-int g364fb_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
- qemu_irq irq);
-
/* mipsnet.c */
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 98567d2..f24b5eb 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -215,7 +215,7 @@ void mips_jazz_init (ram_addr_t ram_size,
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
- g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
+ sysbus_create_simple("g364", 0x60000000, rc4030[3]);
break;
case JAZZ_PICA61:
sysbus_create_simple("sysbus-vga", 0x60000000, NULL);
--
1.7.1.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 6/8] [MIPS] qdev: convert g364fb to sysbus device
2010-09-08 20:39 ` [Qemu-devel] [PATCH 6/8] [MIPS] qdev: convert g364fb " Hervé Poussineau
@ 2010-09-09 14:32 ` Blue Swirl
0 siblings, 0 replies; 18+ messages in thread
From: Blue Swirl @ 2010-09-09 14:32 UTC (permalink / raw)
To: Hervé Poussineau; +Cc: qemu-devel
2010/9/8 Hervé Poussineau <hpoussin@reactos.org>:
> Use it in Jazz emulation
> Remove g364fb_mm_init() function, which is not used anymore
>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> ---
> hw/g364fb.c | 120 +++++++++++++++++++++++++++++--------------------------
> hw/mips.h | 5 --
> hw/mips_jazz.c | 2 +-
> 3 files changed, 64 insertions(+), 63 deletions(-)
>
> diff --git a/hw/g364fb.c b/hw/g364fb.c
> index 3c8fb98..10c53fc 100644
> --- a/hw/g364fb.c
> +++ b/hw/g364fb.c
> @@ -17,10 +17,9 @@
> * with this program; if not, see <http://www.gnu.org/licenses/>.
> */
>
> -#include "hw.h"
> -#include "mips.h"
> #include "console.h"
> #include "pixel_ops.h"
> +#include "sysbus.h"
>
> //#define DEBUG_G364
>
> @@ -33,11 +32,14 @@ do { printf("g364: " fmt , ## __VA_ARGS__); } while (0)
> #define BADF(fmt, ...) \
> do { fprintf(stderr, "g364 ERROR: " fmt , ## __VA_ARGS__);} while (0)
>
> +#define VRAM_BASE 0x40000000
> +
> typedef struct G364State {
> + DeviceState qdev;
> /* hardware */
> uint8_t *vram;
> ram_addr_t vram_offset;
> - int vram_size;
> + uint32_t vram_size;
> qemu_irq irq;
> /* registers */
> uint8_t color_palette[256][3];
> @@ -279,9 +281,8 @@ static inline void g364fb_invalidate_display(void *opaque)
> }
> }
>
> -static void g364fb_reset(void *opaque)
> +static void g364fb_reset(G364State *s)
> {
> - G364State *s = opaque;
> qemu_irq_lower(s->irq);
>
> memset(s->color_palette, 0, sizeof(s->color_palette));
> @@ -292,7 +293,7 @@ static void g364fb_reset(void *opaque)
> s->top_of_screen = 0;
> s->width = s->height = 0;
> memset(s->vram, 0, s->vram_size);
> - g364fb_invalidate_display(opaque);
> + g364fb_invalidate_display(s);
> }
>
> static void g364fb_screen_dump(void *opaque, const char *filename)
> @@ -534,28 +535,9 @@ static CPUWriteMemoryFunc * const g364fb_ctrl_write[3] = {
> g364fb_ctrl_writel,
> };
>
> -static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
> +static int g364fb_post_load(void *opaque, int version_id)
> {
> G364State *s = opaque;
> - unsigned int i, vram_size;
> -
> - if (version_id != 1)
> - return -EINVAL;
> -
> - vram_size = qemu_get_be32(f);
> - if (vram_size < s->vram_size)
> - return -EINVAL;
> - qemu_get_buffer(f, s->vram, s->vram_size);
> - for (i = 0; i < 256; i++)
> - qemu_get_buffer(f, s->color_palette[i], 3);
> - for (i = 0; i < 3; i++)
> - qemu_get_buffer(f, s->cursor_palette[i], 3);
> - qemu_get_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
> - s->cursor_position = qemu_get_be32(f);
> - s->ctla = qemu_get_be32(f);
> - s->top_of_screen = qemu_get_be32(f);
> - s->width = qemu_get_be32(f);
> - s->height = qemu_get_be32(f);
>
> /* force refresh */
> g364fb_update_depth(s);
> @@ -564,51 +546,75 @@ static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
> return 0;
> }
>
> -static void g364fb_save(QEMUFile *f, void *opaque)
> -{
> - G364State *s = opaque;
> - int i;
> +static const VMStateDescription vmstate_g364fb = {
> + .name = "g364fb",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .minimum_version_id_old = 0,
> + .post_load = g364fb_post_load,
> + .fields = (VMStateField []) {
> + /* FIXME: vram? */
> + VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
> + VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
> + VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
> + VMSTATE_UINT32(cursor_position, G364State),
> + VMSTATE_UINT32(ctla, G364State),
> + VMSTATE_UINT32(top_of_screen, G364State),
> + VMSTATE_UINT32(width, G364State),
> + VMSTATE_UINT32(height, G364State),
> + VMSTATE_END_OF_LIST()
> + }
> +};
>
> - qemu_put_be32(f, s->vram_size);
> - qemu_put_buffer(f, s->vram, s->vram_size);
> - for (i = 0; i < 256; i++)
> - qemu_put_buffer(f, s->color_palette[i], 3);
> - for (i = 0; i < 3; i++)
> - qemu_put_buffer(f, s->cursor_palette[i], 3);
> - qemu_put_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
> - qemu_put_be32(f, s->cursor_position);
> - qemu_put_be32(f, s->ctla);
> - qemu_put_be32(f, s->top_of_screen);
> - qemu_put_be32(f, s->width);
> - qemu_put_be32(f, s->height);
> -}
> +typedef struct {
> + SysBusDevice busdev;
> + G364State g364;
> +} SysBusG364State;
>
> -int g364fb_mm_init(target_phys_addr_t vram_base,
> - target_phys_addr_t ctrl_base, int it_shift,
> - qemu_irq irq)
> +static int g364fb_sysbus_initfn(SysBusDevice *dev)
> {
> - G364State *s;
> + G364State *s = &FROM_SYSBUS(SysBusG364State, dev)->g364;
> int io_ctrl;
>
> - s = qemu_mallocz(sizeof(G364State));
> -
> - s->vram_size = 8 * 1024 * 1024;
> s->vram_offset = qemu_ram_alloc(NULL, "g364fb.vram", s->vram_size);
> s->vram = qemu_get_ram_ptr(s->vram_offset);
> - s->irq = irq;
> -
> - qemu_register_reset(g364fb_reset, s);
> - register_savevm(NULL, "g364fb", 0, 1, g364fb_save, g364fb_load, s);
> - g364fb_reset(s);
> + sysbus_init_irq(dev, &s->irq);
>
> s->ds = graphic_console_init(g364fb_update_display,
> g364fb_invalidate_display,
> g364fb_screen_dump, NULL, s);
>
> - cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
> + cpu_register_physical_memory(VRAM_BASE, s->vram_size, s->vram_offset);
Just register another region with sysbus_init_mmio().
>
> io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s);
> - cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
> + sysbus_init_mmio(dev, 0x200000, io_ctrl);
> +
> + g364fb_post_load(s, 0);
>
> return 0;
> }
> +
> +static void g364fb_sysbus_reset(DeviceState *d)
> +{
> + G364State *s = &container_of(d, SysBusG364State, busdev.qdev)->g364;
> + g364fb_reset(s);
> +}
> +
> +static SysBusDeviceInfo g364fb_sysbus_info = {
> + .qdev.name = "g364",
> + .qdev.size = sizeof(SysBusG364State),
> + .qdev.vmsd = &vmstate_g364fb,
> + .qdev.reset = g364fb_sysbus_reset,
> + .init = g364fb_sysbus_initfn,
> + .qdev.props = (Property[]) {
> + DEFINE_PROP_HEX32("vram_size", SysBusG364State, g364.vram_size, 8 * 1024 * 1024),
> + DEFINE_PROP_END_OF_LIST(),
> + },
> +};
> +
> +static void g364fb_register(void)
> +{
> + sysbus_register_withprop(&g364fb_sysbus_info);
> +}
> +
> +device_init(g364fb_register)
> diff --git a/hw/mips.h b/hw/mips.h
> index 285f7dc..75b7c3d 100644
> --- a/hw/mips.h
> +++ b/hw/mips.h
> @@ -8,11 +8,6 @@ PCIBus *pci_gt64120_init(qemu_irq *pic);
> /* bonito.c */
> PCIBus *bonito_init(qemu_irq *pic);
>
> -/* g364fb.c */
> -int g364fb_mm_init(target_phys_addr_t vram_base,
> - target_phys_addr_t ctrl_base, int it_shift,
> - qemu_irq irq);
> -
> /* mipsnet.c */
> void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
>
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index 98567d2..f24b5eb 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -215,7 +215,7 @@ void mips_jazz_init (ram_addr_t ram_size,
> /* Video card */
> switch (jazz_model) {
> case JAZZ_MAGNUM:
> - g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
> + sysbus_create_simple("g364", 0x60000000, rc4030[3]);
> break;
> case JAZZ_PICA61:
> sysbus_create_simple("sysbus-vga", 0x60000000, NULL);
> --
> 1.7.1.GIT
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Qemu-devel] [PATCH 7/8] [MIPS] qdev: convert jazz irq controller to sysbus device
2010-09-08 20:39 [Qemu-devel] [PATCH v2 0/8] Convert some MIPS Jazz devices to qdev Hervé Poussineau
` (5 preceding siblings ...)
2010-09-08 20:39 ` [Qemu-devel] [PATCH 6/8] [MIPS] qdev: convert g364fb " Hervé Poussineau
@ 2010-09-08 20:39 ` Hervé Poussineau
2010-09-08 20:39 ` [Qemu-devel] [PATCH 8/8] [MIPS] qdev: convert rc4030 " Hervé Poussineau
7 siblings, 0 replies; 18+ messages in thread
From: Hervé Poussineau @ 2010-09-08 20:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Hervé Poussineau
Use it in Jazz emulation
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
hw/mips.h | 3 +-
hw/mips_jazz.c | 10 +++-
hw/rc4030.c | 145 +++++++++++++++++++++++++++++++++++++++-----------------
3 files changed, 111 insertions(+), 47 deletions(-)
diff --git a/hw/mips.h b/hw/mips.h
index 75b7c3d..2897ea6 100644
--- a/hw/mips.h
+++ b/hw/mips.h
@@ -17,8 +17,7 @@ void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, i
void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
-void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
- qemu_irq **irqs, rc4030_dma **dmas);
+void *rc4030_init(qemu_irq timer, rc4030_dma **dmas);
/* dp8393x.c */
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index f24b5eb..56739db 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -131,7 +131,8 @@ void mips_jazz_init (ram_addr_t ram_size,
char *filename;
int bios_size, n;
CPUState *env;
- qemu_irq *rc4030, *i8259;
+ DeviceState *dev;
+ qemu_irq rc4030[16], *i8259;
rc4030_dma *dmas;
void* rc4030_opaque;
int s_rtc, s_dma_dummy;
@@ -190,7 +191,12 @@ void mips_jazz_init (ram_addr_t ram_size,
cpu_mips_clock_init(env);
/* Chipset */
- rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
+ dev = sysbus_create_simple("jazzio", 0xf0000000, env->irq[3]);
+ for (n = 0; n < 16; n++) {
+ rc4030[n] = qdev_get_gpio_in(dev, n);
+ }
+
+ rc4030_opaque = rc4030_init(env->irq[6], &dmas);
s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
diff --git a/hw/rc4030.c b/hw/rc4030.c
index 2231373..811d12d 100644
--- a/hw/rc4030.c
+++ b/hw/rc4030.c
@@ -25,6 +25,7 @@
#include "hw.h"
#include "mips.h"
#include "qemu-timer.h"
+#include "sysbus.h"
/********************************************************/
/* debug rc4030 */
@@ -63,6 +64,13 @@ typedef struct dma_pagetable_entry {
#define DMA_FLAG_MEM_INTR 0x0200
#define DMA_FLAG_ADDR_INTR 0x0400
+typedef struct JazzIoState
+{
+ uint32_t mask; /* Local bus int enable mask */
+ uint32_t source; /* Local bus int source */
+ qemu_irq irq;
+} JazzIoState;
+
typedef struct rc4030State
{
uint32_t config; /* 0x0000: RC4030 config register */
@@ -86,15 +94,12 @@ typedef struct rc4030State
uint32_t offset210;
uint32_t nvram_protect; /* 0x0220: NV ram protect register */
uint32_t rem_speed[16];
- uint32_t imr_jazz; /* Local bus int enable mask */
- uint32_t isr_jazz; /* Local bus int source */
/* timer */
QEMUTimer *periodic_timer;
uint32_t itr; /* Interval timer reload */
qemu_irq timer_irq;
- qemu_irq jazz_bus_irq;
} rc4030State;
static void set_next_tick(rc4030State *s)
@@ -431,20 +436,20 @@ static CPUWriteMemoryFunc * const rc4030_write[3] = {
rc4030_writel,
};
-static void update_jazz_irq(rc4030State *s)
+static void update_jazz_irq(JazzIoState *s)
{
uint16_t pending;
- pending = s->isr_jazz & s->imr_jazz;
+ pending = s->source & s->mask;
#ifdef DEBUG_RC4030
- if (s->isr_jazz != 0) {
+ if (s->source != 0) {
uint32_t irq = 0;
DPRINTF("pending irqs:");
for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) {
- if (s->isr_jazz & (1 << irq)) {
+ if (s->source & (1 << irq)) {
printf(" %s", irq_names[irq]);
- if (!(s->imr_jazz & (1 << irq))) {
+ if (!(s->mask & (1 << irq))) {
printf("(ignored)");
}
}
@@ -454,22 +459,9 @@ static void update_jazz_irq(rc4030State *s)
#endif
if (pending != 0)
- qemu_irq_raise(s->jazz_bus_irq);
+ qemu_irq_raise(s->irq);
else
- qemu_irq_lower(s->jazz_bus_irq);
-}
-
-static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
-{
- rc4030State *s = opaque;
-
- if (level) {
- s->isr_jazz |= 1 << irq;
- } else {
- s->isr_jazz &= ~(1 << irq);
- }
-
- update_jazz_irq(s);
+ qemu_irq_lower(s->irq);
}
static void rc4030_periodic_timer(void *opaque)
@@ -482,7 +474,7 @@ static void rc4030_periodic_timer(void *opaque)
static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
{
- rc4030State *s = opaque;
+ JazzIoState *s = opaque;
uint32_t val;
uint32_t irq;
addr &= 0xfff;
@@ -490,7 +482,7 @@ static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
switch (addr) {
/* Local bus int source */
case 0x00: {
- uint32_t pending = s->isr_jazz & s->imr_jazz;
+ uint32_t pending = s->source & s->mask;
val = 0;
irq = 0;
while (pending) {
@@ -506,7 +498,7 @@ static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr)
}
/* Local bus int enable mask */
case 0x02:
- val = s->imr_jazz;
+ val = s->mask;
break;
default:
RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr);
@@ -535,7 +527,7 @@ static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr)
static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
{
- rc4030State *s = opaque;
+ JazzIoState *s = opaque;
addr &= 0xfff;
DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr);
@@ -543,7 +535,7 @@ static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
switch (addr) {
/* Local bus int enable mask */
case 0x02:
- s->imr_jazz = val;
+ s->mask = val;
update_jazz_irq(s);
break;
default:
@@ -585,6 +577,13 @@ static CPUWriteMemoryFunc * const jazzio_write[3] = {
jazzio_writel,
};
+static void jazzio_reset(JazzIoState* s)
+{
+ s->mask = 0x10; /* XXX: required by firmware, but why? */
+ s->source = 0;
+ qemu_irq_lower(s->irq);
+}
+
static void rc4030_reset(void *opaque)
{
rc4030State *s = opaque;
@@ -606,13 +605,10 @@ static void rc4030_reset(void *opaque)
s->nvram_protect = 7;
for (i = 0; i < 15; i++)
s->rem_speed[i] = 7;
- s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
- s->isr_jazz = 0;
s->itr = 0;
qemu_irq_lower(s->timer_irq);
- qemu_irq_lower(s->jazz_bus_irq);
}
static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
@@ -640,12 +636,9 @@ static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
s->nvram_protect = qemu_get_be32(f);
for (i = 0; i < 15; i++)
s->rem_speed[i] = qemu_get_be32(f);
- s->imr_jazz = qemu_get_be32(f);
- s->isr_jazz = qemu_get_be32(f);
s->itr = qemu_get_be32(f);
set_next_tick(s);
- update_jazz_irq(s);
return 0;
}
@@ -672,8 +665,6 @@ static void rc4030_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, s->nvram_protect);
for (i = 0; i < 15; i++)
qemu_put_be32(f, s->rem_speed[i]);
- qemu_put_be32(f, s->imr_jazz);
- qemu_put_be32(f, s->isr_jazz);
qemu_put_be32(f, s->itr);
}
@@ -797,20 +788,17 @@ static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
return s;
}
-void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
- qemu_irq **irqs, rc4030_dma **dmas)
+void *rc4030_init(qemu_irq timer, rc4030_dma **dmas)
{
rc4030State *s;
- int s_chipset, s_jazzio;
+ int s_chipset;
s = qemu_mallocz(sizeof(rc4030State));
- *irqs = qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16);
*dmas = rc4030_allocate_dmas(s, 4);
s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
s->timer_irq = timer;
- s->jazz_bus_irq = jazz_bus;
qemu_register_reset(rc4030_reset, s);
register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
@@ -818,8 +806,79 @@ void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s);
cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
- s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s);
- cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio);
return s;
}
+
+static int jazzio_post_load(void *opaque, int version_id)
+{
+ JazzIoState *s = opaque;
+ update_jazz_irq(s);
+ return 0;
+}
+
+static const VMStateDescription vmstate_jazzio = {
+ .name = "jazzio",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .post_load = jazzio_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32(mask, JazzIoState),
+ VMSTATE_UINT32(source, JazzIoState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+typedef struct {
+ SysBusDevice busdev;
+ JazzIoState jazzio;
+} SysBusJazzIoState;
+
+static void jazzio_sysbus_reset(DeviceState *d)
+{
+ JazzIoState *s = &container_of(d, SysBusJazzIoState, busdev.qdev)->jazzio;
+ jazzio_reset(s);
+}
+
+static void jazzio_set_irq(void *opaque, int irq, int level)
+{
+ JazzIoState *s = &container_of(opaque, SysBusJazzIoState, busdev.qdev)->jazzio;
+
+ if (level) {
+ s->source |= 1 << irq;
+ } else {
+ s->source &= ~(1 << irq);
+ }
+
+ update_jazz_irq(s);
+}
+
+static int jazzio_sysbus_initfn(SysBusDevice *dev)
+{
+ JazzIoState *s = &FROM_SYSBUS(SysBusJazzIoState, dev)->jazzio;
+ int s_jazzio;
+
+ qdev_init_gpio_in(&dev->qdev, jazzio_set_irq, 16);
+
+ s_jazzio = cpu_register_io_memory(jazzio_read, jazzio_write, s);
+ sysbus_init_mmio(dev, 0x00001000, s_jazzio);
+ sysbus_init_irq(dev, &s->irq);
+
+ return 0;
+}
+
+static SysBusDeviceInfo jazzio_sysbus_info = {
+ .qdev.name = "jazzio",
+ .qdev.size = sizeof(SysBusJazzIoState),
+ .qdev.vmsd = &vmstate_jazzio,
+ .qdev.reset = jazzio_sysbus_reset,
+ .init = jazzio_sysbus_initfn,
+};
+
+static void jazz_register(void)
+{
+ sysbus_register_withprop(&jazzio_sysbus_info);
+}
+
+device_init(jazz_register)
--
1.7.1.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH 8/8] [MIPS] qdev: convert rc4030 to sysbus device
2010-09-08 20:39 [Qemu-devel] [PATCH v2 0/8] Convert some MIPS Jazz devices to qdev Hervé Poussineau
` (6 preceding siblings ...)
2010-09-08 20:39 ` [Qemu-devel] [PATCH 7/8] [MIPS] qdev: convert jazz irq controller " Hervé Poussineau
@ 2010-09-08 20:39 ` Hervé Poussineau
2010-09-09 14:37 ` Blue Swirl
7 siblings, 1 reply; 18+ messages in thread
From: Hervé Poussineau @ 2010-09-08 20:39 UTC (permalink / raw)
To: qemu-devel; +Cc: Hervé Poussineau
Use it in Jazz emulation
Remove rc4030_init() function, which is not used anymore
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
---
hw/mips.h | 4 +-
hw/mips_jazz.c | 8 +--
hw/rc4030.c | 135 ++++++++++++++++++++++++++-----------------------------
3 files changed, 69 insertions(+), 78 deletions(-)
diff --git a/hw/mips.h b/hw/mips.h
index 2897ea6..bdbe024 100644
--- a/hw/mips.h
+++ b/hw/mips.h
@@ -16,8 +16,8 @@ typedef struct rc4030DMAState *rc4030_dma;
void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
-
-void *rc4030_init(qemu_irq timer, rc4030_dma **dmas);
+extern rc4030_dma *rc4030_dmas;
+extern void *rc4030_dma_opaque;
/* dp8393x.c */
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index 56739db..eec30c8 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -133,8 +133,6 @@ void mips_jazz_init (ram_addr_t ram_size,
CPUState *env;
DeviceState *dev;
qemu_irq rc4030[16], *i8259;
- rc4030_dma *dmas;
- void* rc4030_opaque;
int s_rtc, s_dma_dummy;
NICInfo *nd;
PITState *pit;
@@ -196,7 +194,7 @@ void mips_jazz_init (ram_addr_t ram_size,
rc4030[n] = qdev_get_gpio_in(dev, n);
}
- rc4030_opaque = rc4030_init(env->irq[6], &dmas);
+ sysbus_create_simple("rc4030", 0x80000000, env->irq[6]);
s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
@@ -237,7 +235,7 @@ void mips_jazz_init (ram_addr_t ram_size,
nd->model = qemu_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
dp83932_init(nd, 0x80001000, 2, rc4030[4],
- rc4030_opaque, rc4030_dma_memory_rw);
+ rc4030_dma_opaque, rc4030_dma_memory_rw);
break;
} else if (strcmp(nd->model, "?") == 0) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
@@ -250,7 +248,7 @@ void mips_jazz_init (ram_addr_t ram_size,
/* SCSI adapter */
esp_init(0x80002000, 0,
- rc4030_dma_read, rc4030_dma_write, dmas[0],
+ rc4030_dma_read, rc4030_dma_write, rc4030_dmas[0],
rc4030[5], &esp_reset);
/* Floppy */
diff --git a/hw/rc4030.c b/hw/rc4030.c
index 811d12d..0c77c44 100644
--- a/hw/rc4030.c
+++ b/hw/rc4030.c
@@ -45,6 +45,9 @@ static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
#define RC4030_ERROR(fmt, ...) \
do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
+rc4030_dma *rc4030_dmas = NULL;
+void *rc4030_dma_opaque = NULL;
+
/********************************************************/
/* rc4030 emulation */
@@ -584,9 +587,8 @@ static void jazzio_reset(JazzIoState* s)
qemu_irq_lower(s->irq);
}
-static void rc4030_reset(void *opaque)
+static void rc4030_reset(rc4030State *s)
{
- rc4030State *s = opaque;
int i;
s->config = 0x410; /* some boards seem to accept 0x104 too */
@@ -611,63 +613,6 @@ static void rc4030_reset(void *opaque)
qemu_irq_lower(s->timer_irq);
}
-static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
-{
- rc4030State* s = opaque;
- int i, j;
-
- if (version_id != 2)
- return -EINVAL;
-
- s->config = qemu_get_be32(f);
- s->invalid_address_register = qemu_get_be32(f);
- for (i = 0; i < 8; i++)
- for (j = 0; j < 4; j++)
- s->dma_regs[i][j] = qemu_get_be32(f);
- s->dma_tl_base = qemu_get_be32(f);
- s->dma_tl_limit = qemu_get_be32(f);
- s->cache_maint = qemu_get_be32(f);
- s->remote_failed_address = qemu_get_be32(f);
- s->memory_failed_address = qemu_get_be32(f);
- s->cache_ptag = qemu_get_be32(f);
- s->cache_ltag = qemu_get_be32(f);
- s->cache_bmask = qemu_get_be32(f);
- s->offset210 = qemu_get_be32(f);
- s->nvram_protect = qemu_get_be32(f);
- for (i = 0; i < 15; i++)
- s->rem_speed[i] = qemu_get_be32(f);
- s->itr = qemu_get_be32(f);
-
- set_next_tick(s);
-
- return 0;
-}
-
-static void rc4030_save(QEMUFile *f, void *opaque)
-{
- rc4030State* s = opaque;
- int i, j;
-
- qemu_put_be32(f, s->config);
- qemu_put_be32(f, s->invalid_address_register);
- for (i = 0; i < 8; i++)
- for (j = 0; j < 4; j++)
- qemu_put_be32(f, s->dma_regs[i][j]);
- qemu_put_be32(f, s->dma_tl_base);
- qemu_put_be32(f, s->dma_tl_limit);
- qemu_put_be32(f, s->cache_maint);
- qemu_put_be32(f, s->remote_failed_address);
- qemu_put_be32(f, s->memory_failed_address);
- qemu_put_be32(f, s->cache_ptag);
- qemu_put_be32(f, s->cache_ltag);
- qemu_put_be32(f, s->cache_bmask);
- qemu_put_be32(f, s->offset210);
- qemu_put_be32(f, s->nvram_protect);
- for (i = 0; i < 15; i++)
- qemu_put_be32(f, s->rem_speed[i]);
- qemu_put_be32(f, s->itr);
-}
-
void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
{
rc4030State *s = opaque;
@@ -788,28 +733,75 @@ static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
return s;
}
-void *rc4030_init(qemu_irq timer, rc4030_dma **dmas)
+static int rc4030_post_load(void *opaque, int version_id)
{
- rc4030State *s;
- int s_chipset;
-
- s = qemu_mallocz(sizeof(rc4030State));
+ rc4030State *s = opaque;
+ set_next_tick(s);
+ return 0;
+}
- *dmas = rc4030_allocate_dmas(s, 4);
+static const VMStateDescription vmstate_rc4030 = {
+ .name = "rc4030",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .post_load = rc4030_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32(config, rc4030State),
+ VMSTATE_UINT32(invalid_address_register, rc4030State),
+ VMSTATE_BUFFER_UNSAFE(dma_regs, rc4030State, 0, 8 * 3 * sizeof(uint32_t)),
+ VMSTATE_UINT32(dma_tl_base, rc4030State),
+ VMSTATE_UINT32(dma_tl_limit, rc4030State),
+ VMSTATE_UINT32(cache_maint, rc4030State),
+ VMSTATE_UINT32(remote_failed_address, rc4030State),
+ VMSTATE_UINT32(memory_failed_address, rc4030State),
+ VMSTATE_UINT32(cache_ptag, rc4030State),
+ VMSTATE_UINT32(cache_ltag, rc4030State),
+ VMSTATE_UINT32(cache_bmask, rc4030State),
+ VMSTATE_UINT32(offset210, rc4030State),
+ VMSTATE_UINT32(nvram_protect, rc4030State),
+ VMSTATE_UINT32_ARRAY(rem_speed, rc4030State, 16),
+ VMSTATE_UINT32(itr, rc4030State),
+ VMSTATE_END_OF_LIST()
+ }
+};
- s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
- s->timer_irq = timer;
+typedef struct {
+ SysBusDevice busdev;
+ rc4030State rc4030;
+} SysBusRc4030State;
- qemu_register_reset(rc4030_reset, s);
- register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
+static void rc4030_sysbus_reset(DeviceState *d)
+{
+ rc4030State *s = &container_of(d, SysBusRc4030State, busdev.qdev)->rc4030;
rc4030_reset(s);
+}
+
+static int rc4030_sysbus_initfn(SysBusDevice *dev)
+{
+ rc4030State *s = &FROM_SYSBUS(SysBusRc4030State, dev)->rc4030;
+ int s_chipset;
+
+ rc4030_dmas = rc4030_allocate_dmas(s, 4);
+ rc4030_dma_opaque = s;
+
+ s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
+ sysbus_init_irq(dev, &s->timer_irq);
s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s);
- cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
+ sysbus_init_mmio(dev, 0x300, s_chipset);
- return s;
+ return 0;
}
+static SysBusDeviceInfo rc4030_sysbus_info = {
+ .qdev.name = "rc4030",
+ .qdev.size = sizeof(SysBusRc4030State),
+ .qdev.vmsd = &vmstate_rc4030,
+ .qdev.reset = rc4030_sysbus_reset,
+ .init = rc4030_sysbus_initfn,
+};
+
static int jazzio_post_load(void *opaque, int version_id)
{
JazzIoState *s = opaque;
@@ -878,6 +870,7 @@ static SysBusDeviceInfo jazzio_sysbus_info = {
static void jazz_register(void)
{
+ sysbus_register_withprop(&rc4030_sysbus_info);
sysbus_register_withprop(&jazzio_sysbus_info);
}
--
1.7.1.GIT
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 8/8] [MIPS] qdev: convert rc4030 to sysbus device
2010-09-08 20:39 ` [Qemu-devel] [PATCH 8/8] [MIPS] qdev: convert rc4030 " Hervé Poussineau
@ 2010-09-09 14:37 ` Blue Swirl
2010-09-25 9:59 ` Markus Armbruster
0 siblings, 1 reply; 18+ messages in thread
From: Blue Swirl @ 2010-09-09 14:37 UTC (permalink / raw)
To: Hervé Poussineau; +Cc: qemu-devel
2010/9/8 Hervé Poussineau <hpoussin@reactos.org>:
> Use it in Jazz emulation
> Remove rc4030_init() function, which is not used anymore
>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> ---
> hw/mips.h | 4 +-
> hw/mips_jazz.c | 8 +--
> hw/rc4030.c | 135 ++++++++++++++++++++++++++-----------------------------
> 3 files changed, 69 insertions(+), 78 deletions(-)
>
> diff --git a/hw/mips.h b/hw/mips.h
> index 2897ea6..bdbe024 100644
> --- a/hw/mips.h
> +++ b/hw/mips.h
> @@ -16,8 +16,8 @@ typedef struct rc4030DMAState *rc4030_dma;
> void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
> void rc4030_dma_read(void *dma, uint8_t *buf, int len);
> void rc4030_dma_write(void *dma, uint8_t *buf, int len);
> -
> -void *rc4030_init(qemu_irq timer, rc4030_dma **dmas);
> +extern rc4030_dma *rc4030_dmas;
> +extern void *rc4030_dma_opaque;
These should be device properties (DEFINE_PROP_PTR, qdev_set_prop_ptr().
>
> /* dp8393x.c */
> void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index 56739db..eec30c8 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -133,8 +133,6 @@ void mips_jazz_init (ram_addr_t ram_size,
> CPUState *env;
> DeviceState *dev;
> qemu_irq rc4030[16], *i8259;
> - rc4030_dma *dmas;
> - void* rc4030_opaque;
> int s_rtc, s_dma_dummy;
> NICInfo *nd;
> PITState *pit;
> @@ -196,7 +194,7 @@ void mips_jazz_init (ram_addr_t ram_size,
> rc4030[n] = qdev_get_gpio_in(dev, n);
> }
>
> - rc4030_opaque = rc4030_init(env->irq[6], &dmas);
> + sysbus_create_simple("rc4030", 0x80000000, env->irq[6]);
> s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
> cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
>
> @@ -237,7 +235,7 @@ void mips_jazz_init (ram_addr_t ram_size,
> nd->model = qemu_strdup("dp83932");
> if (strcmp(nd->model, "dp83932") == 0) {
> dp83932_init(nd, 0x80001000, 2, rc4030[4],
> - rc4030_opaque, rc4030_dma_memory_rw);
> + rc4030_dma_opaque, rc4030_dma_memory_rw);
> break;
> } else if (strcmp(nd->model, "?") == 0) {
> fprintf(stderr, "qemu: Supported NICs: dp83932\n");
> @@ -250,7 +248,7 @@ void mips_jazz_init (ram_addr_t ram_size,
>
> /* SCSI adapter */
> esp_init(0x80002000, 0,
> - rc4030_dma_read, rc4030_dma_write, dmas[0],
> + rc4030_dma_read, rc4030_dma_write, rc4030_dmas[0],
> rc4030[5], &esp_reset);
>
> /* Floppy */
> diff --git a/hw/rc4030.c b/hw/rc4030.c
> index 811d12d..0c77c44 100644
> --- a/hw/rc4030.c
> +++ b/hw/rc4030.c
> @@ -45,6 +45,9 @@ static const char* irq_names[] = { "parallel", "floppy", "sound", "video",
> #define RC4030_ERROR(fmt, ...) \
> do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
>
> +rc4030_dma *rc4030_dmas = NULL;
> +void *rc4030_dma_opaque = NULL;
> +
> /********************************************************/
> /* rc4030 emulation */
>
> @@ -584,9 +587,8 @@ static void jazzio_reset(JazzIoState* s)
> qemu_irq_lower(s->irq);
> }
>
> -static void rc4030_reset(void *opaque)
> +static void rc4030_reset(rc4030State *s)
> {
> - rc4030State *s = opaque;
> int i;
>
> s->config = 0x410; /* some boards seem to accept 0x104 too */
> @@ -611,63 +613,6 @@ static void rc4030_reset(void *opaque)
> qemu_irq_lower(s->timer_irq);
> }
>
> -static int rc4030_load(QEMUFile *f, void *opaque, int version_id)
> -{
> - rc4030State* s = opaque;
> - int i, j;
> -
> - if (version_id != 2)
> - return -EINVAL;
> -
> - s->config = qemu_get_be32(f);
> - s->invalid_address_register = qemu_get_be32(f);
> - for (i = 0; i < 8; i++)
> - for (j = 0; j < 4; j++)
> - s->dma_regs[i][j] = qemu_get_be32(f);
> - s->dma_tl_base = qemu_get_be32(f);
> - s->dma_tl_limit = qemu_get_be32(f);
> - s->cache_maint = qemu_get_be32(f);
> - s->remote_failed_address = qemu_get_be32(f);
> - s->memory_failed_address = qemu_get_be32(f);
> - s->cache_ptag = qemu_get_be32(f);
> - s->cache_ltag = qemu_get_be32(f);
> - s->cache_bmask = qemu_get_be32(f);
> - s->offset210 = qemu_get_be32(f);
> - s->nvram_protect = qemu_get_be32(f);
> - for (i = 0; i < 15; i++)
> - s->rem_speed[i] = qemu_get_be32(f);
> - s->itr = qemu_get_be32(f);
> -
> - set_next_tick(s);
> -
> - return 0;
> -}
> -
> -static void rc4030_save(QEMUFile *f, void *opaque)
> -{
> - rc4030State* s = opaque;
> - int i, j;
> -
> - qemu_put_be32(f, s->config);
> - qemu_put_be32(f, s->invalid_address_register);
> - for (i = 0; i < 8; i++)
> - for (j = 0; j < 4; j++)
> - qemu_put_be32(f, s->dma_regs[i][j]);
> - qemu_put_be32(f, s->dma_tl_base);
> - qemu_put_be32(f, s->dma_tl_limit);
> - qemu_put_be32(f, s->cache_maint);
> - qemu_put_be32(f, s->remote_failed_address);
> - qemu_put_be32(f, s->memory_failed_address);
> - qemu_put_be32(f, s->cache_ptag);
> - qemu_put_be32(f, s->cache_ltag);
> - qemu_put_be32(f, s->cache_bmask);
> - qemu_put_be32(f, s->offset210);
> - qemu_put_be32(f, s->nvram_protect);
> - for (i = 0; i < 15; i++)
> - qemu_put_be32(f, s->rem_speed[i]);
> - qemu_put_be32(f, s->itr);
> -}
> -
> void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)
> {
> rc4030State *s = opaque;
> @@ -788,28 +733,75 @@ static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
> return s;
> }
>
> -void *rc4030_init(qemu_irq timer, rc4030_dma **dmas)
> +static int rc4030_post_load(void *opaque, int version_id)
> {
> - rc4030State *s;
> - int s_chipset;
> -
> - s = qemu_mallocz(sizeof(rc4030State));
> + rc4030State *s = opaque;
> + set_next_tick(s);
> + return 0;
> +}
>
> - *dmas = rc4030_allocate_dmas(s, 4);
> +static const VMStateDescription vmstate_rc4030 = {
> + .name = "rc4030",
> + .version_id = 0,
> + .minimum_version_id = 0,
> + .minimum_version_id_old = 0,
> + .post_load = rc4030_post_load,
> + .fields = (VMStateField []) {
> + VMSTATE_UINT32(config, rc4030State),
> + VMSTATE_UINT32(invalid_address_register, rc4030State),
> + VMSTATE_BUFFER_UNSAFE(dma_regs, rc4030State, 0, 8 * 3 * sizeof(uint32_t)),
> + VMSTATE_UINT32(dma_tl_base, rc4030State),
> + VMSTATE_UINT32(dma_tl_limit, rc4030State),
> + VMSTATE_UINT32(cache_maint, rc4030State),
> + VMSTATE_UINT32(remote_failed_address, rc4030State),
> + VMSTATE_UINT32(memory_failed_address, rc4030State),
> + VMSTATE_UINT32(cache_ptag, rc4030State),
> + VMSTATE_UINT32(cache_ltag, rc4030State),
> + VMSTATE_UINT32(cache_bmask, rc4030State),
> + VMSTATE_UINT32(offset210, rc4030State),
> + VMSTATE_UINT32(nvram_protect, rc4030State),
> + VMSTATE_UINT32_ARRAY(rem_speed, rc4030State, 16),
> + VMSTATE_UINT32(itr, rc4030State),
> + VMSTATE_END_OF_LIST()
> + }
> +};
>
> - s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
> - s->timer_irq = timer;
> +typedef struct {
> + SysBusDevice busdev;
> + rc4030State rc4030;
> +} SysBusRc4030State;
>
> - qemu_register_reset(rc4030_reset, s);
> - register_savevm(NULL, "rc4030", 0, 2, rc4030_save, rc4030_load, s);
> +static void rc4030_sysbus_reset(DeviceState *d)
> +{
> + rc4030State *s = &container_of(d, SysBusRc4030State, busdev.qdev)->rc4030;
> rc4030_reset(s);
> +}
> +
> +static int rc4030_sysbus_initfn(SysBusDevice *dev)
> +{
> + rc4030State *s = &FROM_SYSBUS(SysBusRc4030State, dev)->rc4030;
> + int s_chipset;
> +
> + rc4030_dmas = rc4030_allocate_dmas(s, 4);
> + rc4030_dma_opaque = s;
> +
> + s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s);
> + sysbus_init_irq(dev, &s->timer_irq);
>
> s_chipset = cpu_register_io_memory(rc4030_read, rc4030_write, s);
> - cpu_register_physical_memory(0x80000000, 0x300, s_chipset);
> + sysbus_init_mmio(dev, 0x300, s_chipset);
>
> - return s;
> + return 0;
> }
>
> +static SysBusDeviceInfo rc4030_sysbus_info = {
> + .qdev.name = "rc4030",
> + .qdev.size = sizeof(SysBusRc4030State),
> + .qdev.vmsd = &vmstate_rc4030,
> + .qdev.reset = rc4030_sysbus_reset,
> + .init = rc4030_sysbus_initfn,
> +};
> +
> static int jazzio_post_load(void *opaque, int version_id)
> {
> JazzIoState *s = opaque;
> @@ -878,6 +870,7 @@ static SysBusDeviceInfo jazzio_sysbus_info = {
>
> static void jazz_register(void)
> {
> + sysbus_register_withprop(&rc4030_sysbus_info);
> sysbus_register_withprop(&jazzio_sysbus_info);
> }
>
> --
> 1.7.1.GIT
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH 8/8] [MIPS] qdev: convert rc4030 to sysbus device
2010-09-09 14:37 ` Blue Swirl
@ 2010-09-25 9:59 ` Markus Armbruster
2010-09-25 10:43 ` Blue Swirl
0 siblings, 1 reply; 18+ messages in thread
From: Markus Armbruster @ 2010-09-25 9:59 UTC (permalink / raw)
To: Blue Swirl; +Cc: Hervé Poussineau, qemu-devel
Blue Swirl <blauwirbel@gmail.com> writes:
> 2010/9/8 Hervé Poussineau <hpoussin@reactos.org>:
>> Use it in Jazz emulation
>> Remove rc4030_init() function, which is not used anymore
>>
>> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
>> ---
>> hw/mips.h | 4 +-
>> hw/mips_jazz.c | 8 +--
>> hw/rc4030.c | 135 ++++++++++++++++++++++++++-----------------------------
>> 3 files changed, 69 insertions(+), 78 deletions(-)
>>
>> diff --git a/hw/mips.h b/hw/mips.h
>> index 2897ea6..bdbe024 100644
>> --- a/hw/mips.h
>> +++ b/hw/mips.h
>> @@ -16,8 +16,8 @@ typedef struct rc4030DMAState *rc4030_dma;
>> void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
>> void rc4030_dma_read(void *dma, uint8_t *buf, int len);
>> void rc4030_dma_write(void *dma, uint8_t *buf, int len);
>> -
>> -void *rc4030_init(qemu_irq timer, rc4030_dma **dmas);
>> +extern rc4030_dma *rc4030_dmas;
>> +extern void *rc4030_dma_opaque;
>
> These should be device properties (DEFINE_PROP_PTR, qdev_set_prop_ptr().
Note: DEFINE_PROP_PTR() & friends are for dirty hacks only. Maybe we
should talk about how to do it cleanly.
[...]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Qemu-devel] [PATCH 8/8] [MIPS] qdev: convert rc4030 to sysbus device
2010-09-25 9:59 ` Markus Armbruster
@ 2010-09-25 10:43 ` Blue Swirl
0 siblings, 0 replies; 18+ messages in thread
From: Blue Swirl @ 2010-09-25 10:43 UTC (permalink / raw)
To: Markus Armbruster; +Cc: Hervé Poussineau, qemu-devel
On Sat, Sep 25, 2010 at 9:59 AM, Markus Armbruster <armbru@redhat.com> wrote:
> Blue Swirl <blauwirbel@gmail.com> writes:
>
>> 2010/9/8 Hervé Poussineau <hpoussin@reactos.org>:
>>> Use it in Jazz emulation
>>> Remove rc4030_init() function, which is not used anymore
>>>
>>> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
>>> ---
>>> hw/mips.h | 4 +-
>>> hw/mips_jazz.c | 8 +--
>>> hw/rc4030.c | 135 ++++++++++++++++++++++++++-----------------------------
>>> 3 files changed, 69 insertions(+), 78 deletions(-)
>>>
>>> diff --git a/hw/mips.h b/hw/mips.h
>>> index 2897ea6..bdbe024 100644
>>> --- a/hw/mips.h
>>> +++ b/hw/mips.h
>>> @@ -16,8 +16,8 @@ typedef struct rc4030DMAState *rc4030_dma;
>>> void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
>>> void rc4030_dma_read(void *dma, uint8_t *buf, int len);
>>> void rc4030_dma_write(void *dma, uint8_t *buf, int len);
>>> -
>>> -void *rc4030_init(qemu_irq timer, rc4030_dma **dmas);
>>> +extern rc4030_dma *rc4030_dmas;
>>> +extern void *rc4030_dma_opaque;
>>
>> These should be device properties (DEFINE_PROP_PTR, qdev_set_prop_ptr().
>
> Note: DEFINE_PROP_PTR() & friends are for dirty hacks only. Maybe we
> should talk about how to do it cleanly.
We'd probably need something like an unified DMA structure at qdev
level. Then the global DMA access and mapping routines should be
hidden inside that structure.
Another interesting case is pcnet/lance, there also the bus is
different (PCI vs. SysBus). Can we still have common DMA structure, or
do we need PCIDMA and SysBusDMA?
^ permalink raw reply [flat|nested] 18+ messages in thread