* [PATCH] drm/i915: don't enable self-refresh on Ironlake
@ 2010-09-09 18:58 Jesse Barnes
2010-09-09 19:08 ` [PATCH] drm/i915: dont " Chris Wilson
0 siblings, 1 reply; 2+ messages in thread
From: Jesse Barnes @ 2010-09-09 18:58 UTC (permalink / raw)
To: intel-gfx
We don't know how to enable it safely, especially as outputs turn on and
off. When disabling LP1 we also need to make sure LP2 and 3 are already
disabled.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
drivers/gpu/drm/i915/intel_display.c | 6 ++++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d0b4b23..aa82b0a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2215,9 +2215,17 @@
#define WM1_LP_SR_EN (1<<31)
#define WM1_LP_LATENCY_SHIFT 24
#define WM1_LP_LATENCY_MASK (0x7f<<24)
+#define WM1_LP_FBC_LP1_MASK (0xf<<20)
+#define WM1_LP_FBC_LP1_SHIFT 20
#define WM1_LP_SR_MASK (0x1ff<<8)
#define WM1_LP_SR_SHIFT 8
#define WM1_LP_CURSOR_MASK (0x3f)
+#define WM2_LP_ILK 0x4510c
+#define WM2_LP_EN (1<<31)
+#define WM3_LP_ILK 0x45110
+#define WM3_LP_EN (1<<31)
+#define WM1S_LP_ILK 0x45120
+#define WM1S_LP_EN (1<<31)
/* Memory latency timer register */
#define MLTR_ILK 0x11222
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4b23646..8997bb7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3395,8 +3395,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
reg_value = I915_READ(WM1_LP_ILK);
reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
WM1_LP_CURSOR_MASK);
- reg_value |= WM1_LP_SR_EN |
- (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
+ reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
(sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
I915_WRITE(WM1_LP_ILK, reg_value);
@@ -5718,6 +5717,9 @@ void intel_init_clock_gating(struct drm_device *dev)
I915_WRITE(DISP_ARB_CTL,
(I915_READ(DISP_ARB_CTL) |
DISP_FBC_WM_DIS));
+ I915_WRITE(WM3_LP_ILK, 0);
+ I915_WRITE(WM2_LP_ILK, 0);
+ I915_WRITE(WM1_LP_ILK, 0);
}
/*
* Based on the document from hardware guys the following bits
--
1.6.3.3
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/i915: dont enable self-refresh on Ironlake
2010-09-09 18:58 [PATCH] drm/i915: don't enable self-refresh on Ironlake Jesse Barnes
@ 2010-09-09 19:08 ` Chris Wilson
0 siblings, 0 replies; 2+ messages in thread
From: Chris Wilson @ 2010-09-09 19:08 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
On Thu, 9 Sep 2010 11:58:02 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> We don't know how to enable it safely, especially as outputs turn on and
> off. When disabling LP1 we also need to make sure LP2 and 3 are already
> disabled.
Agreed. Even writing the same values back into the LP1 register makes the
hw go nuts currently.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 2+ messages in thread
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2010-09-09 18:58 [PATCH] drm/i915: don't enable self-refresh on Ironlake Jesse Barnes
2010-09-09 19:08 ` [PATCH] drm/i915: dont " Chris Wilson
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