[U-Boot] [PATCH 1/3] mpc8641hpcn: Update PCI code

[U-Boot] [PATCH 1/3] mpc8641hpcn: Update PCI code

[Peter Tyser]

Update to use the recent, common FSL PCI initialization code.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
I was making the same changes to X-ES code, so applied them to
other users of the old PCI init code.  I only compile tested
them on these boards.

 board/freescale/mpc8641hpcn/mpc8641hpcn.c |   97 +++++++----------------------
 1 files changed, 22 insertions(+), 75 deletions(-)

diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index fee310a..092ead6 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -142,56 +142,26 @@ int first_free_busno = 0;
 
 void pci_init_board(void)
 {
+	struct fsl_pci_info pci_info[2];
+	int pcie_ep;
+	int num = 0;
+
 #ifdef CONFIG_PCIE1
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	struct pci_controller *hose = &pcie1_hose;
-	struct pci_region *r = hose->regions;
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
-	uint devdisr = gur->devdisr;
+	uint devdisr = in_be32(&gur->devdisr);
 	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
 	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 
-#ifdef DEBUG
-	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
-		>> MPC8641_PORBMSR_HA_SHIFT;
-	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
-#endif
 	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
-		debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
-		debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
-		if (pci->pme_msg_det) {
-			pci->pme_msg_det = 0xffffffff;
-			debug(" with errors.  Clearing.  Now 0x%08x",
-			      pci->pme_msg_det);
-		}
-		debug("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BUS,
-			       CONFIG_SYS_PCIE1_MEM_PHYS,
-			       CONFIG_SYS_PCIE1_MEM_SIZE,
-			       PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_IO_BUS,
-			       CONFIG_SYS_PCIE1_IO_PHYS,
-			       CONFIG_SYS_PCIE1_IO_SIZE,
-			       PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno=first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		first_free_busno=hose->last_busno+1;
-		printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
-			hose->first_busno,hose->last_busno);
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+		printf("    PCIE1 connected to ULI as %s (base addr %lx)\n",
+				pcie_ep ? "Endpoint" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
 
 		/*
 		 * Activate ULI1575 legacy chip by performing a fake
@@ -201,45 +171,22 @@ void pci_init_board(void)
 				       + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
 
 	} else {
-		puts("PCI-EXPRESS 1: Disabled\n");
+		puts("    PCIE1: disabled\n");
 	}
-}
 #else
-	puts("PCI-EXPRESS1: Disabled\n");
+	puts("    PCIE1: disabled\n");
 #endif /* CONFIG_PCIE1 */
 
 #ifdef CONFIG_PCIE2
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-	struct pci_controller *hose = &pcie2_hose;
-	struct pci_region *r = hose->regions;
-
-	/* outbound memory */
-	pci_set_region(r++,
-		       CONFIG_SYS_PCIE2_MEM_BUS,
-		       CONFIG_SYS_PCIE2_MEM_PHYS,
-		       CONFIG_SYS_PCIE2_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* outbound io */
-	pci_set_region(r++,
-		       CONFIG_SYS_PCIE2_IO_BUS,
-		       CONFIG_SYS_PCIE2_IO_PHYS,
-		       CONFIG_SYS_PCIE2_IO_SIZE,
-		       PCI_REGION_IO);
-
-	hose->region_count = r - hose->regions;
-
-	hose->first_busno=first_free_busno;
-
-	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-	first_free_busno=hose->last_busno+1;
-	printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
-		hose->first_busno,hose->last_busno);
-}
+	SET_STD_PCIE_INFO(pci_info[num], 2);
+	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+	printf("    PCIE2 connected as %s (base addr %lx)\n",
+			pcie_ep ? "Endpoint" : "Root Complex",
+			pci_info[num].regs);
+	first_free_busno = fsl_pci_init_port(&pci_info[num++],
+				&pcie2_hose, first_free_busno);
 #else
-	puts("PCI-EXPRESS 2: Disabled\n");
+	puts("    PCIE2: disabled\n");
 #endif /* CONFIG_PCIE2 */
 
 }
-- 
1.7.0.4

[U-Boot] [PATCH 2/3] sbc8641d: Update PCI code

[Peter Tyser]

Update to use the recent, common FSL PCI initialization code.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: joe.hamman at embeddedspecialties.com
---
 board/sbc8641d/sbc8641d.c |  103 ++++++++++----------------------------------
 1 files changed, 24 insertions(+), 79 deletions(-)

diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 54b2d0b..d954d2f 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -206,100 +206,45 @@ int first_free_busno = 0;
 
 void pci_init_board(void)
 {
+	struct fsl_pci_info pci_info[2];
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
-	uint devdisr = gur->devdisr;
+	uint devdisr = in_be32(&gur->devdisr);
 	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
 		>> MPC8641_PORDEVSR_IO_SEL_SHIFT;
+	int pcie_ep;
+	int num = 0;
 
 #ifdef CONFIG_PCIE1
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
-	struct pci_controller *hose = &pcie1_hose;
-	struct pci_region *r = hose->regions;
-#ifdef DEBUG
-	uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
-		>> MPC8641_PORBMSR_HA_SHIFT;
-	uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
-#endif
-	if ((io_sel == 2 || io_sel == 3 || io_sel == 5
-	     || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
-	    && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
-		debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
-		debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
-		if (pci->pme_msg_det) {
-			pci->pme_msg_det = 0xffffffff;
-			debug(" with errors.  Clearing.  Now 0x%08x",
-			      pci->pme_msg_det);
-		}
-		debug("\n");
-
-		/* outbound memory */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_MEM_BUS,
-			       CONFIG_SYS_PCIE1_MEM_PHYS,
-			       CONFIG_SYS_PCIE1_MEM_SIZE,
-			       PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region(r++,
-			       CONFIG_SYS_PCIE1_IO_BUS,
-			       CONFIG_SYS_PCIE1_IO_PHYS,
-			       CONFIG_SYS_PCIE1_IO_SIZE,
-			       PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno=first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		first_free_busno=hose->last_busno+1;
-		printf ("    PCI-EXPRESS 1 on bus %02x - %02x\n",
-			hose->first_busno,hose->last_busno);
-
+	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+		printf("    PCIE1 connected as %s (base addr %lx)\n",
+				pcie_ep ? "Endpoint" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
 	} else {
-		puts("PCI-EXPRESS 1: Disabled\n");
+		puts("    PCIE1: disabled\n");
 	}
-}
 #else
-	puts("PCI-EXPRESS1: Disabled\n");
+	puts("    PCIE1: disabled\n");
 #endif /* CONFIG_PCIE1 */
 
 #ifdef CONFIG_PCIE2
-{
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
-	struct pci_controller *hose = &pcie2_hose;
-	struct pci_region *r = hose->regions;
-
-	/* outbound memory */
-	pci_set_region(r++,
-		       CONFIG_SYS_PCIE2_MEM_BUS,
-		       CONFIG_SYS_PCIE2_MEM_PHYS,
-		       CONFIG_SYS_PCIE2_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* outbound io */
-	pci_set_region(r++,
-		       CONFIG_SYS_PCIE2_IO_BUS,
-		       CONFIG_SYS_PCIE2_IO_PHYS,
-		       CONFIG_SYS_PCIE2_IO_SIZE,
-		       PCI_REGION_IO);
-
-	hose->region_count = r - hose->regions;
 
-	hose->first_busno=first_free_busno;
-
-	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-	first_free_busno=hose->last_busno+1;
-	printf ("    PCI-EXPRESS 2 on bus %02x - %02x\n",
-		hose->first_busno,hose->last_busno);
-}
+	SET_STD_PCIE_INFO(pci_info[num], 2);
+	pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+	printf("    PCIE2 connected as %s (base addr %lx)\n",
+			pcie_ep ? "Endpoint" : "Root Complex",
+			pci_info[num].regs);
+	first_free_busno = fsl_pci_init_port(&pci_info[num++],
+				&pcie2_hose, first_free_busno);
 #else
-	puts("PCI-EXPRESS 2: Disabled\n");
+	puts("    PCIE2: disabled\n");
 #endif /* CONFIG_PCIE2 */
-
 }
 
 
-- 
1.7.0.4

[U-Boot] [PATCH 3/3] tqm85xx: Update PCI code

[Peter Tyser]

Update to use the recent, common FSL PCI initialization code.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: sr at denx.de
---
 board/tqc/tqm85xx/law.c     |    4 +-
 board/tqc/tqm85xx/tlb.c     |   10 ++--
 board/tqc/tqm85xx/tqm85xx.c |  151 ++++++++++++-------------------------------
 include/configs/TQM85xx.h   |   20 +++---
 4 files changed, 59 insertions(+), 126 deletions(-)

diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
index 7e9a2c7..e684ba2 100644
--- a/board/tqc/tqm85xx/law.c
+++ b/board/tqc/tqm85xx/law.c
@@ -71,7 +71,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 #ifdef CONFIG_PCIE1
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_BUS, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
 #else /* !CONFIG_PCIE1 */
 	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
 #endif /* CONFIG_PCIE1 */
@@ -79,7 +79,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
 #ifdef CONFIG_PCIE1
-	SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_BUS, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
 #endif /* CONFIG_PCIE */
 };
 
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 71fe3ab..75dd348 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	PCI express MEM First half
 	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -88,8 +88,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 5:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	PCI express MEM Second half
 	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
-		       CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
+		       CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 5, BOOKE_PAGESZ_256M, 1),
 #else /* !CONFIG_PCIE */
@@ -155,7 +155,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 9:	 16M	Non-cacheable, guarded
 	 * 0xef000000	 16M	PCI express IO
 	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 9, BOOKE_PAGESZ_16M, 1),
 #endif /* CONFIG_PCIE */
@@ -205,7 +205,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	 * TLB 6:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	PCI express MEM First half
 	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 6, BOOKE_PAGESZ_256M, 1),
 #else /* !CONFIG_PCIE */
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index dda2cb6..2c3885f 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -38,6 +38,7 @@
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
 #include <asm/io.h>
+#include <linux/compiler.h>
 #include <ioports.h>
 #include <flash.h>
 #include <libfdt.h>
@@ -534,7 +535,6 @@ void local_bus_init (void)
 /*
  * Initialize PCI Devices, report devices found.
  */
-static int first_free_busno;
 
 #ifdef CONFIG_PCI1
 static struct pci_controller pci1_hose;
@@ -544,144 +544,77 @@ static struct pci_controller pci1_hose;
 static struct pci_controller pcie1_hose;
 #endif /* CONFIG_PCIE1 */
 
-static inline void init_pci1(void)
+void pci_init_board (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_PCI1
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
-	struct pci_controller *hose = &pci1_hose;
-	struct pci_region *r = hose->regions;
-
-	/* PORDEVSR[15] */
-	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
-	/* PORDEVSR[14] */
-	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
-	/* PORPLLSR[16] */
-	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+	struct fsl_pci_info pci_info[2];
+	int first_free_busno = 0;
+	int num = 0;
+	int pcie_ep;
+	__maybe_unused int pcie_configured;
 
-	int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 devdisr = in_be32(&gur->devdisr);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	__maybe_unused uint io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+			MPC85xx_PORDEVSR_IO_SEL_SHIFT;
 
+#ifdef CONFIG_PCI1
+	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
+	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
 	uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* PCI PSPEED in [4:5] */
+	uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
 
-	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
-		printf ("PCI1:  %d bit, %s MHz, %s, %s, %s\n",
+	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+		SET_STD_PCI_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+		printf ("\n   PCI1:  %d bit, %s MHz, %s, %s, %s\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333333) ? "33" :
 			(pci_speed == 66666666) ? "66" : "unknown",
 			pci_clk_sel ? "sync" : "async",
-			pci_agent ? "agent" : "host",
+			pcie_ep ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter");
-
-		/* outbound memory */
-		pci_set_region (r++,
-				CONFIG_SYS_PCI1_MEM_BASE,
-				CONFIG_SYS_PCI1_MEM_PHYS,
-				CONFIG_SYS_PCI1_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region (r++,
-				CONFIG_SYS_PCI1_IO_BASE,
-				CONFIG_SYS_PCI1_IO_PHYS,
-				CONFIG_SYS_PCI1_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
-		printf ("       PCI on bus %02x..%02x\n",
-			hose->first_busno, hose->last_busno);
-
-		first_free_busno = hose->last_busno + 1;
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pci1_hose, first_free_busno);
 #ifdef CONFIG_PCIX_CHECK
-		if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
+		if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
 			ushort reg16 =
 				PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
 				PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
-			uint dev = PCI_BDF(hose->first_busno, 0, 0);
+			uint dev = PCI_BDF(0, 0, 0);
 
 			/* PCI-X init */
 			if (CONFIG_SYS_CLK_FREQ < 66000000)
 				puts ("PCI-X will only work@66 MHz\n");
 
-			pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
-						    reg16);
+			pci_write_config_word(dev, PCIX_COMMAND, reg16);
 		}
 #endif
 	} else {
-		puts ("PCI1:  disabled\n");
+		printf("    PCI1: disabled\n");
 	}
-#else /* !CONFIG_PCI1 */
-	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
-#endif /* CONFIG_PCI1 */
-}
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
+#endif
 
-static inline void init_pcie1(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_PCIE1
-	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
-	struct pci_controller *hose = &pcie1_hose;
-	int pcie_ep;
-	struct pci_region *r = hose->regions;
-
-	int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
-	pcie_ep = fsl_setup_hose(hose, CONFIG_SYS_PCIE1_ADDR);
-
-	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
-		printf ("PCIe:  %s, base address %x",
-			pcie_ep ? "Endpoint" : "Root complex", (uint)pci);
-
-		if (pci->pme_msg_det) {
-			pci->pme_msg_det = 0xffffffff;
-			debug (", with errors. Clearing. Now 0x%08x",
-			       pci->pme_msg_det);
-		}
-		puts ("\n");
-
-		/* outbound memory */
-		pci_set_region (r++,
-				CONFIG_SYS_PCIE1_MEM_BASE,
-				CONFIG_SYS_PCIE1_MEM_PHYS,
-				CONFIG_SYS_PCIE1_MEM_SIZE,
-				PCI_REGION_MEM);
-
-		/* outbound io */
-		pci_set_region (r++,
-				CONFIG_SYS_PCIE1_IO_BASE,
-				CONFIG_SYS_PCIE1_IO_PHYS,
-				CONFIG_SYS_PCIE1_IO_SIZE,
-				PCI_REGION_IO);
-
-		hose->region_count = r - hose->regions;
-
-		hose->first_busno = first_free_busno;
-
-		fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-		printf ("       PCIe on bus %02x..%02x\n",
-			hose->first_busno, hose->last_busno);
-
-		first_free_busno = hose->last_busno + 1;
-
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+		printf("    PCIE1 connected as %s\n",
+			pcie_ep ? "Endpoint" : "Root Complex");
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
 	} else {
-		printf ("PCIe:  disabled\n");
+		printf("    PCIE1: disabled\n");
 	}
-#else /* !CONFIG_PCIE1 */
-	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
 #endif /* CONFIG_PCIE1 */
 }
 
-void pci_init_board (void)
-{
-	init_pci1();
-	init_pcie1();
-}
-
 #ifdef CONFIG_OF_BOARD_SETUP
 void ft_board_setup (void *blob, bd_t *bd)
 {
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index ccb339d..01e18f1 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -374,11 +374,11 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
-#define CONFIG_SYS_PCI1_IO_BASE	(CONFIG_SYS_CCSRBAR + 0x02000000)
-#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
+#define CONFIG_SYS_PCI1_IO_BUS	(CONFIG_SYS_CCSRBAR + 0x02000000)
+#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BUS
 #define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/*  16M			*/
 
 #ifdef CONFIG_PCIE1
@@ -387,16 +387,16 @@
  * Addresses are mapped 1-1.
  */
 #ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xb0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xb0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000      /* 512M                 */
-#define CONFIG_SYS_PCIE1_IO_BASE	0xaf000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0xaf000000
 #else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_BASE	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M                 */
-#define CONFIG_SYS_PCIE1_IO_BASE	0xef000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0xef000000
 #endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
-#define CONFIG_SYS_PCIE1_IO_PHYS	CONFIG_SYS_PCIE1_IO_BASE
+#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
+#define CONFIG_SYS_PCIE1_IO_PHYS	CONFIG_SYS_PCIE1_IO_BUS
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x1000000       /* 16M                  */
 #endif /* CONFIG_PCIE1 */
 
-- 
1.7.0.4

[U-Boot] [PATCH 1/3] mpc8641hpcn: Update PCI code

[Kumar Gala]

On Sep 29, 2010, at 1:37 PM, Peter Tyser wrote:

> Update to use the recent, common FSL PCI initialization code.
> 
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> ---
> I was making the same changes to X-ES code, so applied them to
> other users of the old PCI init code.  I only compile tested
> them on these boards.
> 
> board/freescale/mpc8641hpcn/mpc8641hpcn.c |   97 +++++++----------------------
> 1 files changed, 22 insertions(+), 75 deletions(-)

applied to 85xx.

- k

[U-Boot] [PATCH 2/3] sbc8641d: Update PCI code

[Kumar Gala]

On Sep 29, 2010, at 1:37 PM, Peter Tyser wrote:

> Update to use the recent, common FSL PCI initialization code.
> 
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> CC: joe.hamman at embeddedspecialties.com
> ---
> board/sbc8641d/sbc8641d.c |  103 ++++++++++----------------------------------
> 1 files changed, 24 insertions(+), 79 deletions(-)

applied to 85xx.

- k

[U-Boot] [PATCH 3/3] tqm85xx: Update PCI code

[Kumar Gala]

On Sep 29, 2010, at 1:37 PM, Peter Tyser wrote:

> Update to use the recent, common FSL PCI initialization code.
> 
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> CC: sr at denx.de
> ---
> board/tqc/tqm85xx/law.c     |    4 +-
> board/tqc/tqm85xx/tlb.c     |   10 ++--
> board/tqc/tqm85xx/tqm85xx.c |  151 ++++++++++++-------------------------------
> include/configs/TQM85xx.h   |   20 +++---
> 4 files changed, 59 insertions(+), 126 deletions(-)

applied to 85xx.

- k

[U-Boot] [PATCH 3/3] tqm85xx: Update PCI code

[Wolfgang Denk]

Dear Peter Tyser,

In message <1285785448-4703-3-git-send-email-ptyser@xes-inc.com> you wrote:
> Update to use the recent, common FSL PCI initialization code.
> 
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> CC: sr at denx.de
> ---
>  board/tqc/tqm85xx/law.c     |    4 +-
>  board/tqc/tqm85xx/tlb.c     |   10 ++--
>  board/tqc/tqm85xx/tqm85xx.c |  151 ++++++++++++-------------------------------
>  include/configs/TQM85xx.h   |   20 +++---
>  4 files changed, 59 insertions(+), 126 deletions(-)

This commit needs fixing.

First, it corrupts the output. Some patch like this should be added:

diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 2c3885f..027c429 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -567,7 +567,7 @@ void pci_init_board (void)
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 		SET_STD_PCI_INFO(pci_info[num], 1);
 		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
-		printf ("\n   PCI1:  %d bit, %s MHz, %s, %s, %s\n",
+		printf ("PCI1:  %d bit, %s MHz, %s, %s, %s\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333333) ? "33" :
 			(pci_speed == 66666666) ? "66" : "unknown",
@@ -591,7 +591,7 @@ void pci_init_board (void)
 		}
 #endif
 	} else {
-		printf("    PCI1: disabled\n");
+		printf("PCI1:  disabled\n");
 	}
 #else
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);


Even worse, we now see a (badly formatted, but this is just an added
"bonus")

	Scanning PCI bus 00
    PCIE1 on bus 00 - 00

which is completely bogus as there on these boards nor on these
processors.


Can you please provide a fix?

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"It's like deja vu all over again."                      - Yogi Berra

[U-Boot] [PATCH 3/3] tqm85xx: Update PCI code

[Peter Tyser]

On Tue, 2010-10-26 at 21:54 +0200, Wolfgang Denk wrote:
> Dear Peter Tyser,
> 
> In message <1285785448-4703-3-git-send-email-ptyser@xes-inc.com> you wrote:
> > Update to use the recent, common FSL PCI initialization code.
> > 
> > Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> > CC: sr at denx.de
> > ---
> >  board/tqc/tqm85xx/law.c     |    4 +-
> >  board/tqc/tqm85xx/tlb.c     |   10 ++--
> >  board/tqc/tqm85xx/tqm85xx.c |  151 ++++++++++++-------------------------------
> >  include/configs/TQM85xx.h   |   20 +++---
> >  4 files changed, 59 insertions(+), 126 deletions(-)
> 
> This commit needs fixing.
> 
> First, it corrupts the output. Some patch like this should be added:
> 
> diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
> index 2c3885f..027c429 100644
> --- a/board/tqc/tqm85xx/tqm85xx.c
> +++ b/board/tqc/tqm85xx/tqm85xx.c
> @@ -567,7 +567,7 @@ void pci_init_board (void)
>  	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
>  		SET_STD_PCI_INFO(pci_info[num], 1);
>  		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
> -		printf ("\n   PCI1:  %d bit, %s MHz, %s, %s, %s\n",
> +		printf ("PCI1:  %d bit, %s MHz, %s, %s, %s\n",
>  			(pci_32) ? 32 : 64,
>  			(pci_speed == 33333333) ? "33" :
>  			(pci_speed == 66666666) ? "66" : "unknown",
> @@ -591,7 +591,7 @@ void pci_init_board (void)
>  		}
>  #endif
>  	} else {
> -		printf("    PCI1: disabled\n");
> +		printf("PCI1:  disabled\n");
>  	}
>  #else
>  	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
> 
> 
> Even worse, we now see a (badly formatted, but this is just an added
> "bonus")
> 
> 	Scanning PCI bus 00
>     PCIE1 on bus 00 - 00
> 
> which is completely bogus as there on these boards nor on these
> processors.
> 
> 
> Can you please provide a fix?

Can you send the entire bootup output?  The code is based on Freescale
reference boards, eg the mpc8568mds, so I'd guess the problem is not
tqm85xx-specific.

Best,
Pete

[U-Boot] [PATCH 3/3] tqm85xx: Update PCI code

[Wolfgang Denk]

Dear Peter Tyser,

In message <1288156533.1971.6.camel@ptyser-laptop> you wrote:
>
> Can you send the entire bootup output?  The code is based on Freescale
> reference boards, eg the mpc8568mds, so I'd guess the problem is not
> tqm85xx-specific.

Sure. Here it is:

U-Boot 2010.09-00558-g79e6313 (Oct 26 2010 - 21:31:41)

CPU:   8555E, Version: 1.1, (0x80790011)
Core:  Unknown, Version: 2.0, (0x80200020)
Clock Configuration:
       CPU0:833.333 MHz, 
       CCB:333.333 MHz,
       DDR:166.667 MHz (333.333 MT/s data rate), LBC:41.667 MHz
CPM:   333.333 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: TQM8555, serial# ABC0555 casl=25
I2C:   ready
DRAM:  128 MiB
FLASH: 128 MiB
L2:    256 KB already enabled

   PCI1:  32 bit, 33 MHz, sync, host, arbiter
               Scanning PCI bus 00
    PCIE1 on bus 00 - 00
PCI-X will only work at 66 MHz
In:    serial
Out:   serial
Err:   serial
DTT:   1 is 41 C
Net:   FCC1, TSEC0 [PRIME], TSEC1
PS/2:  No device found
Kbd:   reset failed, no ACK

Type run flash_nfs to mount root filesystem over NFS

Hit any key to stop autoboot:  0 
=> 


Please also note the "Core:  Unknown" which is new.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Hiring experienced unix people is  like  a  built-in  filter  against
idiots. Hiring experienced NT people provides no such guarantee.
            -- Miguel Cruz in WgL96.349$CC.122704 at typhoon2.ba-dsg.net

[U-Boot] [PATCH] fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware

[Peter Tyser]

Previously fsl_pci_init_port() always assumed that a port was a PCIe
port and would incorrectly print messages for a PCI port such as the
following on bootup:
    PCI1:  32 bit, 33 MHz, sync, host, arbiter
                Scanning PCI bus 00
    PCIE1 on bus 00 - 00

This change corrects the output of fsl_pci_init_port():
    PCI1:  32 bit, 33 MHz, sync, host, arbiter
                Scanning PCI bus 00
    PCI1 on bus 00 - 00

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
Tested on a MPC8548 with PCI, and a MPC8640 with PCIe

 drivers/pci/fsl_pci_init.c |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 1f02103..45794da 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -441,6 +441,8 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 {
 	volatile ccsr_fsl_pci_t *pci;
 	struct pci_region *r;
+	pci_dev_t dev = PCI_BDF(busno,0,0);
+	u8 pcie_cap;
 
 	pci = (ccsr_fsl_pci_t *) pci_info->regs;
 
@@ -479,7 +481,9 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 		hose->last_busno = hose->first_busno;
 	}
 
-	printf("    PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
+	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
+	printf("    PCI%s%x on bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
+			"E" : "", pci_info->pci_num,
 			hose->first_busno, hose->last_busno);
 
 	return(hose->last_busno + 1);
-- 
1.7.0.4

[U-Boot] [PATCH 3/3] tqm85xx: Update PCI code

[Peter Tyser]

On Wed, 2010-10-27 at 08:47 +0200, Wolfgang Denk wrote:
> Dear Peter Tyser,
> 
> In message <1288156533.1971.6.camel@ptyser-laptop> you wrote:
> >
> > Can you send the entire bootup output?  The code is based on Freescale
> > reference boards, eg the mpc8568mds, so I'd guess the problem is not
> > tqm85xx-specific.
> 
> Sure. Here it is:

Thanks.

> U-Boot 2010.09-00558-g79e6313 (Oct 26 2010 - 21:31:41)
> 
> CPU:   8555E, Version: 1.1, (0x80790011)
> Core:  Unknown, Version: 2.0, (0x80200020)
> Clock Configuration:
>        CPU0:833.333 MHz, 
>        CCB:333.333 MHz,
>        DDR:166.667 MHz (333.333 MT/s data rate), LBC:41.667 MHz
> CPM:   333.333 MHz
> L1:    D-cache 32 kB enabled
>        I-cache 32 kB enabled
> Board: TQM8555, serial# ABC0555 casl=25
> I2C:   ready
> DRAM:  128 MiB
> FLASH: 128 MiB
> L2:    256 KB already enabled
> 
>    PCI1:  32 bit, 33 MHz, sync, host, arbiter

Its unclear what the correct behavior is here.  I just did a quick
sample of recent Freescale reference boards and generally see:
p1020ds/p2020dsmpc8572: printf("    PCIE%u connected to %s as %s (base addr %lx)\n",

Older boards with PCI often look like:
mpc8548/mpc8568mds: printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",

The TQM boards, socrates, and mpc8349 are/were:
printf ("PCI1:  %d bit, %s MHz, %s, %s, %s\n");

So the original behavior of the TQM board was out of sync with the
majority of other boards, and some boards have a newline.

I agree we should get rid of the newline on all these printfs, but the
indentation issue is murkier to me.  The common Freescale PCI code
currently assumes there is an indentation, so we should really sync
boards'/FSL indentation up to be consistent.  Anyone have a strong
preference for the indentation?  p2020 way, or socrates way above?

>                Scanning PCI bus 00
>     PCIE1 on bus 00 - 00

I just sent a patch to address this issue.

Best,
Peter

[U-Boot] [PATCH 3/3] tqm85xx: Update PCI code

[Wolfgang Denk]

Dear Peter Tyser,

In message <1288298646.8967.130.camel@petert> you wrote:
>
> So the original behavior of the TQM board was out of sync with the
> majority of other boards, and some boards have a newline.

Let's say a large number of board maintainers do not care about nice
formatting of the output.

So if we use common code for a certain set, please let's not use the
lowest common denominator.

> I agree we should get rid of the newline on all these printfs, but the
> indentation issue is murkier to me.  The common Freescale PCI code
> currently assumes there is an indentation, so we should really sync
> boards'/FSL indentation up to be consistent.  Anyone have a strong
> preference for the indentation?  p2020 way, or socrates way above?

Why should the PCI output be indented? It is not so on any other board
I ever had my fingers on.

Example - all APM boards look like that:

CPU:   AMCC PowerPC 460EX Rev. B at 1066.667 MHz (PLB=266 OPB=88 EBC=88)
       Security/Kasumi support
       Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Canyonlands - AMCC PPC460EX Evaluation Board, 1*PCIe/1*SATA, Rev. 16
I2C:   ready
DRAM:  512 MiB (ECC not enabled, 533 MHz, CL4)
FLASH: 64 MiB
NAND:  128 MiB
PCI:   Bus Dev VenId DevId Class Int
PCIE1: link is not up.
DTT:   1 is 27 C
Net:   ppc_4xx_eth0, ppc_4xx_eth1
...

Output starts in the first column, all nicely aligned.



> >                Scanning PCI bus 00
> >     PCIE1 on bus 00 - 00
> 
> I just sent a patch to address this issue.

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Boykottiert Microsoft - Kauft Eure Fenster bei OBI!

[U-Boot] [PATCH] fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware

[Wolfgang Denk]

Dear Kumar,

In message <1288297499-21417-1-git-send-email-ptyser@xes-inc.com> Peter Tyser wrote:
> Previously fsl_pci_init_port() always assumed that a port was a PCIe
> port and would incorrectly print messages for a PCI port such as the
> following on bootup:
>     PCI1:  32 bit, 33 MHz, sync, host, arbiter
>                 Scanning PCI bus 00
>     PCIE1 on bus 00 - 00
> 
> This change corrects the output of fsl_pci_init_port():
>     PCI1:  32 bit, 33 MHz, sync, host, arbiter
>                 Scanning PCI bus 00
>     PCI1 on bus 00 - 00
> 
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> ---
> Tested on a MPC8548 with PCI, and a MPC8640 with PCIe
> 
>  drivers/pci/fsl_pci_init.c |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)

I thought this should go through your tree, as it affects all the FSL
boards.  Or are you waiting for me to pull this in?


Also, there is still this other unresolved issue about indentation of
the PCI messages.  Would you agree to clean this up as I suggested?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
To be sure of hitting the target, shoot first and, whatever you  hit,
call it the target.

[U-Boot] [PATCH] fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware

[Peter Tyser]

On Sat, 2010-11-13 at 23:53 +0100, Wolfgang Denk wrote:
> Dear Kumar,
> 
> In message <1288297499-21417-1-git-send-email-ptyser@xes-inc.com> Peter Tyser wrote:
> > Previously fsl_pci_init_port() always assumed that a port was a PCIe
> > port and would incorrectly print messages for a PCI port such as the
> > following on bootup:
> >     PCI1:  32 bit, 33 MHz, sync, host, arbiter
> >                 Scanning PCI bus 00
> >     PCIE1 on bus 00 - 00
> > 
> > This change corrects the output of fsl_pci_init_port():
> >     PCI1:  32 bit, 33 MHz, sync, host, arbiter
> >                 Scanning PCI bus 00
> >     PCI1 on bus 00 - 00
> > 
> > Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> > ---
> > Tested on a MPC8548 with PCI, and a MPC8640 with PCIe
> > 
> >  drivers/pci/fsl_pci_init.c |    6 +++++-
> >  1 files changed, 5 insertions(+), 1 deletions(-)
> 
> I thought this should go through your tree, as it affects all the FSL
> boards.  Or are you waiting for me to pull this in?
> 
> 
> Also, there is still this other unresolved issue about indentation of
> the PCI messages.  Would you agree to clean this up as I suggested?

I submitted a 6-patch series starting with "fsl: Clean up printing of
PCI boot info" a while back which should address the indentation issue.
Ideally the fist 3 patches in that series would make it into the
upcoming release.  The last 3 are RFCs and could go in this release, or
the next.

Best,
Peter

[U-Boot] [PATCH] fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware

[Wolfgang Denk]

Dear Peter Tyser,

In message <1288297499-21417-1-git-send-email-ptyser@xes-inc.com> you wrote:
> Previously fsl_pci_init_port() always assumed that a port was a PCIe
> port and would incorrectly print messages for a PCI port such as the
> following on bootup:
>     PCI1:  32 bit, 33 MHz, sync, host, arbiter
>                 Scanning PCI bus 00
>     PCIE1 on bus 00 - 00
> 
> This change corrects the output of fsl_pci_init_port():
>     PCI1:  32 bit, 33 MHz, sync, host, arbiter
>                 Scanning PCI bus 00
>     PCI1 on bus 00 - 00
> 
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> ---
> Tested on a MPC8548 with PCI, and a MPC8640 with PCIe
> 
>  drivers/pci/fsl_pci_init.c |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)

Applied, thanks.

Kumar, I hope this is OK with you.

Best regards,

Wolfgang Denk

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