instruction cache flushing issues

instruction cache flushing issues

[James Bottomley]

While looking at all the other problems surrounding our coherency
issues:

http://wiki.parisc-linux.org/TestCases

I noticed that we have no nullifier naitlb (non access instruction tlb
miss interruption) handler (we do in the nadtlb handler).  What this
means is that an icache flush to any area always pulls in the tlb entry
(or generates a page fault).  Can anyone remember why we do this?  I
suspect it's because for data, we don't want to prefetch if we have no
TLB entry and the effect on flushing is just incidental.

What I don't like about this behaviour is that if we flush a user
instruction page, we actually cause a TLB entry to be placed there
(where none might have existed before).  This, in turn, causes the CPU
to think it's allowed to do cache movein.  Premature movein (say because
we flush before the data is present) could be one cause of our apparent
icache problems in threading.

James