* [PATCH v4 0/7] OMAP: idle path errata fixes
@ 2010-12-18 22:53 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
Hi,
as discussed in [1], here is step 2 - idle path errata fixes.
this is the next rev incorporating comments from V2 post
of this series.
Tested:
this series:
SDP3430
SDP3630
this series + ASM cleanup series[2]
SDP3430
SDP3630
Test Script:
http://elinux.org/OMAP_Power_Management#Quick_verification_of_suspend-idle_functionality
V3: http://marc.info/?t=129140247800030&r=1&w=2
V2: http://marc.info/?l=linux-omap&m=129106200408109&w=2
Major change in V3:
Erratas are now handled per silicon - it is much cleaner :)
no more redundant cpu_is_omap34xx check anymore
errata configure is __init as it should be
Eduardo Valentin (1):
OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
Nishanth Menon (3):
omap3: pm: introduce errata handling
OMAP3630: PM: Erratum i608: disable RTA
OMAP3: PM: make omap3_cpuidle_update_states independent of
enable_off_mode
Peter 'p2' De Schrijver (2):
OMAP3: PM: Erratum i581 support: dll kick strategy
OMAP3630: PM: Disable L2 cache while invalidating L2 cache
Richard Woodruff (1):
OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
arch/arm/mach-omap2/control.c | 13 +++-
arch/arm/mach-omap2/control.h | 7 +-
arch/arm/mach-omap2/cpuidle34xx.c | 29 ++++--
arch/arm/mach-omap2/pm.h | 15 +++-
arch/arm/mach-omap2/pm34xx.c | 46 +++++++++-
arch/arm/mach-omap2/sleep34xx.S | 187 +++++++++++++++++++++++--------------
6 files changed, 211 insertions(+), 86 deletions(-)
bloat-o-meter report Vs 2.6.37-rc6
add/remove: 2/0 grow/shrink: 7/0 up/down: 297/0 (297)
function old new delta
omap3_pm_off_mode_enable 80 160 +80
omap3_pm_init 1792 1872 +80
omap3630_ctrl_disable_rta - 44 +44
omap3_save_scratchpad_contents 732 760 +28
static.__func__ 13783 13808 +25
vermagic 45 60 +15
linux_banner 132 147 +15
prcm_interrupt_handler 268 276 +8
pm34xx_errata - 2 +2
[1] http://marc.info/?l=linux-omap&m=129045338806957&w=2
[2] http://marc.info/?l=linux-omap&m=129268746417556&w=2
Cc: Charulatha Varadarajan <charu@ti.com>
Cc: Jean Pihet <jean.pihet@newoldbits.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Tao Hu <tghk48@motorola.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Vishwanath Sripathy <vishwanath.bs@ti.com>
---
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 0/7] OMAP: idle path errata fixes
@ 2010-12-18 22:53 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
as discussed in [1], here is step 2 - idle path errata fixes.
this is the next rev incorporating comments from V2 post
of this series.
Tested:
this series:
SDP3430
SDP3630
this series + ASM cleanup series[2]
SDP3430
SDP3630
Test Script:
http://elinux.org/OMAP_Power_Management#Quick_verification_of_suspend-idle_functionality
V3: http://marc.info/?t=129140247800030&r=1&w=2
V2: http://marc.info/?l=linux-omap&m=129106200408109&w=2
Major change in V3:
Erratas are now handled per silicon - it is much cleaner :)
no more redundant cpu_is_omap34xx check anymore
errata configure is __init as it should be
Eduardo Valentin (1):
OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
Nishanth Menon (3):
omap3: pm: introduce errata handling
OMAP3630: PM: Erratum i608: disable RTA
OMAP3: PM: make omap3_cpuidle_update_states independent of
enable_off_mode
Peter 'p2' De Schrijver (2):
OMAP3: PM: Erratum i581 support: dll kick strategy
OMAP3630: PM: Disable L2 cache while invalidating L2 cache
Richard Woodruff (1):
OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
arch/arm/mach-omap2/control.c | 13 +++-
arch/arm/mach-omap2/control.h | 7 +-
arch/arm/mach-omap2/cpuidle34xx.c | 29 ++++--
arch/arm/mach-omap2/pm.h | 15 +++-
arch/arm/mach-omap2/pm34xx.c | 46 +++++++++-
arch/arm/mach-omap2/sleep34xx.S | 187 +++++++++++++++++++++++--------------
6 files changed, 211 insertions(+), 86 deletions(-)
bloat-o-meter report Vs 2.6.37-rc6
add/remove: 2/0 grow/shrink: 7/0 up/down: 297/0 (297)
function old new delta
omap3_pm_off_mode_enable 80 160 +80
omap3_pm_init 1792 1872 +80
omap3630_ctrl_disable_rta - 44 +44
omap3_save_scratchpad_contents 732 760 +28
static.__func__ 13783 13808 +25
vermagic 45 60 +15
linux_banner 132 147 +15
prcm_interrupt_handler 268 276 +8
pm34xx_errata - 2 +2
[1] http://marc.info/?l=linux-omap&m=129045338806957&w=2
[2] http://marc.info/?l=linux-omap&m=129268746417556&w=2
Cc: Charulatha Varadarajan <charu@ti.com>
Cc: Jean Pihet <jean.pihet@newoldbits.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Tao Hu <tghk48@motorola.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Vishwanath Sripathy <vishwanath.bs@ti.com>
---
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-18 22:53 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
From: Richard Woodruff <r-woodruff2@ti.com>
Analysis in TI kernel with ETM showed that using cache mapped flush
in kernel instead of SO mapped flush cost drops by 65% (3.39mS down
to 1.17mS) for clean_l2 which is used during sleep sequences.
Overall:
- speed up
- unfortunately there isn't a good alternative flush method today
- code reduction and less maintenance and potential bug in
unmaintained code
This also fixes the bug with the clean_l2 function usage.
Reported-by: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
[nm@ti.com: ported rkw's proposal to 2.6.37-rc2]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
---
(no change in this series, posted for completeness)
v2: https://patchwork.kernel.org/patch/365222/
v1: http://marc.info/?l=linux-omap&m=129013171325210&w=2
arch/arm/mach-omap2/sleep34xx.S | 79 ++++++--------------------------------
1 files changed, 13 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2fb205a..2c20fcf 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -520,72 +520,17 @@ clean_caches:
cmp r9, #1 /* Check whether L2 inval is required or not*/
bne skip_l2_inval
clean_l2:
- /* read clidr */
- mrc p15, 1, r0, c0, c0, 1
- /* extract loc from clidr */
- ands r3, r0, #0x7000000
- /* left align loc bit field */
- mov r3, r3, lsr #23
- /* if loc is 0, then no need to clean */
- beq finished
- /* start clean at cache level 0 */
- mov r10, #0
-loop1:
- /* work out 3x current cache level */
- add r2, r10, r10, lsr #1
- /* extract cache type bits from clidr*/
- mov r1, r0, lsr r2
- /* mask of the bits for current cache only */
- and r1, r1, #7
- /* see what cache we have at this level */
- cmp r1, #2
- /* skip if no cache, or just i-cache */
- blt skip
- /* select current cache level in cssr */
- mcr p15, 2, r10, c0, c0, 0
- /* isb to sych the new cssr&csidr */
- isb
- /* read the new csidr */
- mrc p15, 1, r1, c0, c0, 0
- /* extract the length of the cache lines */
- and r2, r1, #7
- /* add 4 (line length offset) */
- add r2, r2, #4
- ldr r4, assoc_mask
- /* find maximum number on the way size */
- ands r4, r4, r1, lsr #3
- /* find bit position of way size increment */
- clz r5, r4
- ldr r7, numset_mask
- /* extract max number of the index size*/
- ands r7, r7, r1, lsr #13
-loop2:
- mov r9, r4
- /* create working copy of max way size*/
-loop3:
- /* factor way and cache number into r11 */
- orr r11, r10, r9, lsl r5
- /* factor index number into r11 */
- orr r11, r11, r7, lsl r2
- /*clean & invalidate by set/way */
- mcr p15, 0, r11, c7, c10, 2
- /* decrement the way*/
- subs r9, r9, #1
- bge loop3
- /*decrement the index */
- subs r7, r7, #1
- bge loop2
-skip:
- add r10, r10, #2
- /* increment cache number */
- cmp r3, r10
- bgt loop1
-finished:
- /*swith back to cache level 0 */
- mov r10, #0
- /* select current cache level in cssr */
- mcr p15, 2, r10, c0, c0, 0
- isb
+ /*
+ * Jump out to kernel flush routine
+ * - reuse that code is better
+ * - it executes in a cached space so is faster than refetch per-block
+ * - should be faster and will change with kernel
+ * - 'might' have to copy address, load and jump to it
+ */
+ ldr r1, kernel_flush
+ mov lr, pc
+ bx r1
+
skip_l2_inval:
/* Data memory barrier and Data sync barrier */
mov r1, #0
@@ -668,5 +613,7 @@ cache_pred_disable_mask:
.word 0xFFFFE7FB
control_stat:
.word CONTROL_STAT
+kernel_flush:
+ .word v7_flush_dcache_all
ENTRY(omap34xx_cpu_suspend_sz)
.word . - omap34xx_cpu_suspend
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
@ 2010-12-18 22:53 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Richard Woodruff <r-woodruff2@ti.com>
Analysis in TI kernel with ETM showed that using cache mapped flush
in kernel instead of SO mapped flush cost drops by 65% (3.39mS down
to 1.17mS) for clean_l2 which is used during sleep sequences.
Overall:
- speed up
- unfortunately there isn't a good alternative flush method today
- code reduction and less maintenance and potential bug in
unmaintained code
This also fixes the bug with the clean_l2 function usage.
Reported-by: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
[nm at ti.com: ported rkw's proposal to 2.6.37-rc2]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
---
(no change in this series, posted for completeness)
v2: https://patchwork.kernel.org/patch/365222/
v1: http://marc.info/?l=linux-omap&m=129013171325210&w=2
arch/arm/mach-omap2/sleep34xx.S | 79 ++++++--------------------------------
1 files changed, 13 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2fb205a..2c20fcf 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -520,72 +520,17 @@ clean_caches:
cmp r9, #1 /* Check whether L2 inval is required or not*/
bne skip_l2_inval
clean_l2:
- /* read clidr */
- mrc p15, 1, r0, c0, c0, 1
- /* extract loc from clidr */
- ands r3, r0, #0x7000000
- /* left align loc bit field */
- mov r3, r3, lsr #23
- /* if loc is 0, then no need to clean */
- beq finished
- /* start clean at cache level 0 */
- mov r10, #0
-loop1:
- /* work out 3x current cache level */
- add r2, r10, r10, lsr #1
- /* extract cache type bits from clidr*/
- mov r1, r0, lsr r2
- /* mask of the bits for current cache only */
- and r1, r1, #7
- /* see what cache we have at this level */
- cmp r1, #2
- /* skip if no cache, or just i-cache */
- blt skip
- /* select current cache level in cssr */
- mcr p15, 2, r10, c0, c0, 0
- /* isb to sych the new cssr&csidr */
- isb
- /* read the new csidr */
- mrc p15, 1, r1, c0, c0, 0
- /* extract the length of the cache lines */
- and r2, r1, #7
- /* add 4 (line length offset) */
- add r2, r2, #4
- ldr r4, assoc_mask
- /* find maximum number on the way size */
- ands r4, r4, r1, lsr #3
- /* find bit position of way size increment */
- clz r5, r4
- ldr r7, numset_mask
- /* extract max number of the index size*/
- ands r7, r7, r1, lsr #13
-loop2:
- mov r9, r4
- /* create working copy of max way size*/
-loop3:
- /* factor way and cache number into r11 */
- orr r11, r10, r9, lsl r5
- /* factor index number into r11 */
- orr r11, r11, r7, lsl r2
- /*clean & invalidate by set/way */
- mcr p15, 0, r11, c7, c10, 2
- /* decrement the way*/
- subs r9, r9, #1
- bge loop3
- /*decrement the index */
- subs r7, r7, #1
- bge loop2
-skip:
- add r10, r10, #2
- /* increment cache number */
- cmp r3, r10
- bgt loop1
-finished:
- /*swith back to cache level 0 */
- mov r10, #0
- /* select current cache level in cssr */
- mcr p15, 2, r10, c0, c0, 0
- isb
+ /*
+ * Jump out to kernel flush routine
+ * - reuse that code is better
+ * - it executes in a cached space so is faster than refetch per-block
+ * - should be faster and will change with kernel
+ * - 'might' have to copy address, load and jump to it
+ */
+ ldr r1, kernel_flush
+ mov lr, pc
+ bx r1
+
skip_l2_inval:
/* Data memory barrier and Data sync barrier */
mov r1, #0
@@ -668,5 +613,7 @@ cache_pred_disable_mask:
.word 0xFFFFE7FB
control_stat:
.word CONTROL_STAT
+kernel_flush:
+ .word v7_flush_dcache_all
ENTRY(omap34xx_cpu_suspend_sz)
.word . - omap34xx_cpu_suspend
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-18 22:53 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Erratum i581 impacts OMAP3 platforms.
PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing
the DPLL not to be locked at times.
IMPORTANT:
*) This is not a complete workaround implementation as recommended
by the silicon erratum. this is a support logic for detecting lockups and
attempting to recover where possible and is known to provide stability
in multiple platforms.
*) This code is mostly important for inactive and retention. The ROM code
waits for the maximum dll lock time when resuming from off mode. So for
off mode this code isn't really needed.
This should eventually get refactored as part of cleanups to sleep34xx.S
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
(no change done, posting for completeness of the series)
v2: https://patchwork.kernel.org/patch/365252/
typo correction- erratum, support, added comment from Peter from the
thread to commit message
v1: http://marc.info/?l=linux-omap&m=129013172525234&w=2
arch/arm/mach-omap2/sleep34xx.S | 52 +++++++++++++++++++++++++++++++++++---
1 files changed, 47 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2c20fcf..3fbd1e5 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -42,6 +42,7 @@
OMAP3430_PM_PREPWSTST)
#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
+#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
#define SRAM_BASE_P 0x40200000
#define CONTROL_STAT 0x480022F0
#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
@@ -554,31 +555,67 @@ skip_l2_inval:
/* Make sure SDRC accesses are ok */
wait_sdrc_ok:
+
+/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */
+ ldr r4, cm_idlest_ckgen
+wait_dpll3_lock:
+ ldr r5, [r4]
+ tst r5, #1
+ beq wait_dpll3_lock
+
ldr r4, cm_idlest1_core
+wait_sdrc_ready:
ldr r5, [r4]
- and r5, r5, #0x2
- cmp r5, #0
- bne wait_sdrc_ok
+ tst r5, #0x2
+ bne wait_sdrc_ready
+ /* allow DLL powerdown upon hw idle req */
ldr r4, sdrc_power
ldr r5, [r4]
bic r5, r5, #0x40
str r5, [r4]
-wait_dll_lock:
+is_dll_in_lock_mode:
+
/* Is dll in lock mode? */
ldr r4, sdrc_dlla_ctrl
ldr r5, [r4]
tst r5, #0x4
bxne lr
/* wait till dll locks */
- ldr r4, sdrc_dlla_status
+wait_dll_lock_timed:
+ ldr r4, wait_dll_lock_counter
+ add r4, r4, #1
+ str r4, wait_dll_lock_counter
+ ldr r4, sdrc_dlla_status
+ mov r6, #8 /* Wait 20uS for lock */
+wait_dll_lock:
+ subs r6, r6, #0x1
+ beq kick_dll
ldr r5, [r4]
and r5, r5, #0x4
cmp r5, #0x4
bne wait_dll_lock
bx lr
+ /* disable/reenable DLL if not locked */
+kick_dll:
+ ldr r4, sdrc_dlla_ctrl
+ ldr r5, [r4]
+ mov r6, r5
+ bic r6, #(1<<3) /* disable dll */
+ str r6, [r4]
+ dsb
+ orr r6, r6, #(1<<3) /* enable dll */
+ str r6, [r4]
+ dsb
+ ldr r4, kick_counter
+ add r4, r4, #1
+ str r4, kick_counter
+ b wait_dll_lock_timed
+
cm_idlest1_core:
.word CM_IDLEST1_CORE_V
+cm_idlest_ckgen:
+ .word CM_IDLEST_CKGEN_V
sdrc_dlla_status:
.word SDRC_DLLA_STATUS_V
sdrc_dlla_ctrl:
@@ -615,5 +652,10 @@ control_stat:
.word CONTROL_STAT
kernel_flush:
.word v7_flush_dcache_all
+ /* these 2 words need to be at the end !!! */
+kick_counter:
+ .word 0
+wait_dll_lock_counter:
+ .word 0
ENTRY(omap34xx_cpu_suspend_sz)
.word . - omap34xx_cpu_suspend
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
@ 2010-12-18 22:53 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Erratum i581 impacts OMAP3 platforms.
PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing
the DPLL not to be locked at times.
IMPORTANT:
*) This is not a complete workaround implementation as recommended
by the silicon erratum. this is a support logic for detecting lockups and
attempting to recover where possible and is known to provide stability
in multiple platforms.
*) This code is mostly important for inactive and retention. The ROM code
waits for the maximum dll lock time when resuming from off mode. So for
off mode this code isn't really needed.
This should eventually get refactored as part of cleanups to sleep34xx.S
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
(no change done, posting for completeness of the series)
v2: https://patchwork.kernel.org/patch/365252/
typo correction- erratum, support, added comment from Peter from the
thread to commit message
v1: http://marc.info/?l=linux-omap&m=129013172525234&w=2
arch/arm/mach-omap2/sleep34xx.S | 52 +++++++++++++++++++++++++++++++++++---
1 files changed, 47 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 2c20fcf..3fbd1e5 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -42,6 +42,7 @@
OMAP3430_PM_PREPWSTST)
#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
+#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
#define SRAM_BASE_P 0x40200000
#define CONTROL_STAT 0x480022F0
#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
@@ -554,31 +555,67 @@ skip_l2_inval:
/* Make sure SDRC accesses are ok */
wait_sdrc_ok:
+
+/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */
+ ldr r4, cm_idlest_ckgen
+wait_dpll3_lock:
+ ldr r5, [r4]
+ tst r5, #1
+ beq wait_dpll3_lock
+
ldr r4, cm_idlest1_core
+wait_sdrc_ready:
ldr r5, [r4]
- and r5, r5, #0x2
- cmp r5, #0
- bne wait_sdrc_ok
+ tst r5, #0x2
+ bne wait_sdrc_ready
+ /* allow DLL powerdown upon hw idle req */
ldr r4, sdrc_power
ldr r5, [r4]
bic r5, r5, #0x40
str r5, [r4]
-wait_dll_lock:
+is_dll_in_lock_mode:
+
/* Is dll in lock mode? */
ldr r4, sdrc_dlla_ctrl
ldr r5, [r4]
tst r5, #0x4
bxne lr
/* wait till dll locks */
- ldr r4, sdrc_dlla_status
+wait_dll_lock_timed:
+ ldr r4, wait_dll_lock_counter
+ add r4, r4, #1
+ str r4, wait_dll_lock_counter
+ ldr r4, sdrc_dlla_status
+ mov r6, #8 /* Wait 20uS for lock */
+wait_dll_lock:
+ subs r6, r6, #0x1
+ beq kick_dll
ldr r5, [r4]
and r5, r5, #0x4
cmp r5, #0x4
bne wait_dll_lock
bx lr
+ /* disable/reenable DLL if not locked */
+kick_dll:
+ ldr r4, sdrc_dlla_ctrl
+ ldr r5, [r4]
+ mov r6, r5
+ bic r6, #(1<<3) /* disable dll */
+ str r6, [r4]
+ dsb
+ orr r6, r6, #(1<<3) /* enable dll */
+ str r6, [r4]
+ dsb
+ ldr r4, kick_counter
+ add r4, r4, #1
+ str r4, kick_counter
+ b wait_dll_lock_timed
+
cm_idlest1_core:
.word CM_IDLEST1_CORE_V
+cm_idlest_ckgen:
+ .word CM_IDLEST_CKGEN_V
sdrc_dlla_status:
.word SDRC_DLLA_STATUS_V
sdrc_dlla_ctrl:
@@ -615,5 +652,10 @@ control_stat:
.word CONTROL_STAT
kernel_flush:
.word v7_flush_dcache_all
+ /* these 2 words need to be@the end !!! */
+kick_counter:
+ .word 0
+wait_dll_lock_counter:
+ .word 0
ENTRY(omap34xx_cpu_suspend_sz)
.word . - omap34xx_cpu_suspend
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 3/7] omap3: pm: introduce errata handling
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-18 22:53 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
Introduce errata handling for omap3. This patch introduces
errata variable and and stub for initialization which will be
filled up by followon patches.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Splitting the errata introduction out into it's own separate patch
arch/arm/mach-omap2/pm.h | 7 +++++++
arch/arm/mach-omap2/pm34xx.c | 9 +++++++++
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0d75bfd..0348fd7 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -85,4 +85,11 @@ extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
+#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
+extern u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
+#else
+#define IS_PM34XX_ERRATUM(id) 0
+#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
+
#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 648b8c5..5702f41 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -68,6 +68,9 @@ static inline bool is_suspending(void)
#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
+/* pm34xx errata defined in pm.h */
+u16 pm34xx_errata;
+
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
@@ -1002,6 +1005,10 @@ void omap_push_sram_idle(void)
save_secure_ram_context_sz);
}
+static void __init pm_errata_configure(void)
+{
+}
+
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
@@ -1011,6 +1018,8 @@ static int __init omap3_pm_init(void)
if (!cpu_is_omap34xx())
return -ENODEV;
+ pm_errata_configure();
+
printk(KERN_ERR "Power Management for TI OMAP3.\n");
/* XXX prcm_setup_regs needs to be before enabling hw
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 3/7] omap3: pm: introduce errata handling
@ 2010-12-18 22:53 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-arm-kernel
Introduce errata handling for omap3. This patch introduces
errata variable and and stub for initialization which will be
filled up by followon patches.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
Splitting the errata introduction out into it's own separate patch
arch/arm/mach-omap2/pm.h | 7 +++++++
arch/arm/mach-omap2/pm34xx.c | 9 +++++++++
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0d75bfd..0348fd7 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -85,4 +85,11 @@ extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
+#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
+extern u16 pm34xx_errata;
+#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
+#else
+#define IS_PM34XX_ERRATUM(id) 0
+#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
+
#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 648b8c5..5702f41 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -68,6 +68,9 @@ static inline bool is_suspending(void)
#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
+/* pm34xx errata defined in pm.h */
+u16 pm34xx_errata;
+
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
@@ -1002,6 +1005,10 @@ void omap_push_sram_idle(void)
save_secure_ram_context_sz);
}
+static void __init pm_errata_configure(void)
+{
+}
+
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
@@ -1011,6 +1018,8 @@ static int __init omap3_pm_init(void)
if (!cpu_is_omap34xx())
return -ENODEV;
+ pm_errata_configure();
+
printk(KERN_ERR "Power Management for TI OMAP3.\n");
/* XXX prcm_setup_regs needs to be before enabling hw
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-18 22:53 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
Erratum id: i608
RTA (Retention Till Access) feature is not supported and leads to device
stability issues when enabled. This impacts modules with embedded memories
on OMAP3630
Workaround is to disable RTA on boot and coming out of core off.
For disabling rta coming out of off mode, we do this by overriding the
restore pointer for 3630 to allow us restore handler as the first point of
entry before caches are touched and is common for GP and HS devices.
to disable earlier than this could be possible by modifying the ppa for HS
devices, but not for GP devices.
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
[ambresh@ti.com: co-developer]
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
v4:
control register handling moved to control.c
errata handling framework introduction split out
into a separate patch
v3: http://marc.info/?t=129140247800026&r=1&w=2
additional comment to explain Ambresh's contrib
removed the redundant check for cpu_is34xx - it is already
done by pm_init
pm_errata_configure is __init
v2: https://patchwork.kernel.org/patch/365242/
fixed missing b restore for 3430 es3.1 code.
introduced erratum handling logic here splitting it out of uart errata
typo fixes for erratum
v1: http://marc.info/?l=linux-omap&m=129013172825240&w=2
arch/arm/mach-omap2/control.c | 13 ++++++++++++-
arch/arm/mach-omap2/control.h | 7 ++++++-
arch/arm/mach-omap2/pm.h | 2 ++
arch/arm/mach-omap2/pm34xx.c | 10 ++++++++++
arch/arm/mach-omap2/sleep34xx.S | 26 ++++++++++++++++++++++++++
5 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294..27ed558 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
/* Populate the Scratchpad contents */
scratchpad_contents.boot_config_ptr = 0x0;
- if (omap_rev() != OMAP3430_REV_ES3_0 &&
+ if (cpu_is_omap3630())
+ scratchpad_contents.public_restore_ptr =
+ virt_to_phys(get_omap3630_restore_pointer());
+ else if (omap_rev() != OMAP3430_REV_ES3_0 &&
omap_rev() != OMAP3430_REV_ES3_1)
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_restore_pointer());
@@ -474,4 +477,12 @@ void omap3_control_restore_context(void)
omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
return;
}
+
+void omap3630_ctrl_disable_rta(void)
+{
+ if (!cpu_is_omap3630())
+ return;
+ omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
+}
+
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c..ec98dd7 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -204,6 +204,10 @@
#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
+/* 36xx-only RTA - Retention till Accesss control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
+#define OMAP36XX_RTA_DISABLE 0x0
+
/* 34xx D2D idle-related pins, handled by PM core */
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
@@ -347,10 +351,11 @@ extern void omap3_save_scratchpad_contents(void);
extern void omap3_clear_scratchpad_contents(void);
extern u32 *get_restore_pointer(void);
extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
-
+extern void omap3630_ctrl_disable_rta(void);
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0348fd7..8d9aa3e 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -85,6 +85,8 @@ extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
+#define PM_RTA_ERRATUM_i608 (1 << 0)
+
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 5702f41..b32a2ed 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1007,6 +1007,8 @@ void omap_push_sram_idle(void)
static void __init pm_errata_configure(void)
{
+ if (cpu_is_omap3630())
+ pm34xx_errata |= PM_RTA_ERRATUM_i608;
}
static int __init omap3_pm_init(void)
@@ -1067,6 +1069,14 @@ static int __init omap3_pm_init(void)
pm_idle = omap3_pm_idle;
omap3_idle_init();
+ /*
+ * RTA is disabled during initialization as per erratum i608
+ * it is safer to disable rta by the bootloader, but we would like
+ * to be doubly sure here and prevent any mishaps.
+ */
+ if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
+ omap3630_ctrl_disable_rta();
+
clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
omap3_secure_ram_storage =
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 3fbd1e5..cc3507b 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -45,6 +45,8 @@
#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
#define SRAM_BASE_P 0x40200000
#define CONTROL_STAT 0x480022F0
+#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
+ + OMAP36XX_CONTROL_MEM_RTA_CTRL)
#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
* available */
#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
@@ -99,6 +101,14 @@ ENTRY(get_restore_pointer)
ldmfd sp!, {pc} @ restore regs and return
ENTRY(get_restore_pointer_sz)
.word . - get_restore_pointer
+ .text
+/* Function call to get the restore pointer for 3630 resume from OFF */
+ENTRY(get_omap3630_restore_pointer)
+ stmfd sp!, {lr} @ save registers on stack
+ adr r0, restore_3630
+ ldmfd sp!, {pc} @ restore regs and return
+ENTRY(get_omap3630_restore_pointer_sz)
+ .word . - get_omap3630_restore_pointer
.text
/* Function call to get the restore pointer for for ES3 to resume from OFF */
@@ -246,6 +256,20 @@ copy_to_sram:
bne copy_to_sram
ldr r1, sram_base
blx r1
+ b restore
+
+restore_3630:
+ /*b restore_es3630*/ @ Enable to debug restore code
+ ldr r1, pm_prepwstst_core_p
+ ldr r2, [r1]
+ and r2, r2, #0x3
+ cmp r2, #0x0 @ Check if previous power state of CORE is OFF
+ bne restore
+ /* Disable rta before giving control */
+ ldr r1, control_mem_rta
+ mov r2, #OMAP36XX_RTA_DISABLE
+ str r2, [r1]
+ /* Fall thru for the remaining logic */
restore:
/* b restore*/ @ Enable to debug restore code
/* Check what was the reason for mpu reset and store the reason in r9*/
@@ -650,6 +674,8 @@ cache_pred_disable_mask:
.word 0xFFFFE7FB
control_stat:
.word CONTROL_STAT
+control_mem_rta:
+ .word CONTROL_MEM_RTA_CTRL
kernel_flush:
.word v7_flush_dcache_all
/* these 2 words need to be at the end !!! */
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
@ 2010-12-18 22:53 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-arm-kernel
Erratum id: i608
RTA (Retention Till Access) feature is not supported and leads to device
stability issues when enabled. This impacts modules with embedded memories
on OMAP3630
Workaround is to disable RTA on boot and coming out of core off.
For disabling rta coming out of off mode, we do this by overriding the
restore pointer for 3630 to allow us restore handler as the first point of
entry before caches are touched and is common for GP and HS devices.
to disable earlier than this could be possible by modifying the ppa for HS
devices, but not for GP devices.
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
[ambresh at ti.com: co-developer]
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
v4:
control register handling moved to control.c
errata handling framework introduction split out
into a separate patch
v3: http://marc.info/?t=129140247800026&r=1&w=2
additional comment to explain Ambresh's contrib
removed the redundant check for cpu_is34xx - it is already
done by pm_init
pm_errata_configure is __init
v2: https://patchwork.kernel.org/patch/365242/
fixed missing b restore for 3430 es3.1 code.
introduced erratum handling logic here splitting it out of uart errata
typo fixes for erratum
v1: http://marc.info/?l=linux-omap&m=129013172825240&w=2
arch/arm/mach-omap2/control.c | 13 ++++++++++++-
arch/arm/mach-omap2/control.h | 7 ++++++-
arch/arm/mach-omap2/pm.h | 2 ++
arch/arm/mach-omap2/pm34xx.c | 10 ++++++++++
arch/arm/mach-omap2/sleep34xx.S | 26 ++++++++++++++++++++++++++
5 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 1fa3294..27ed558 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
/* Populate the Scratchpad contents */
scratchpad_contents.boot_config_ptr = 0x0;
- if (omap_rev() != OMAP3430_REV_ES3_0 &&
+ if (cpu_is_omap3630())
+ scratchpad_contents.public_restore_ptr =
+ virt_to_phys(get_omap3630_restore_pointer());
+ else if (omap_rev() != OMAP3430_REV_ES3_0 &&
omap_rev() != OMAP3430_REV_ES3_1)
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_restore_pointer());
@@ -474,4 +477,12 @@ void omap3_control_restore_context(void)
omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
return;
}
+
+void omap3630_ctrl_disable_rta(void)
+{
+ if (!cpu_is_omap3630())
+ return;
+ omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
+}
+
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index b6c6b7c..ec98dd7 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -204,6 +204,10 @@
#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
+/* 36xx-only RTA - Retention till Accesss control registers and bits */
+#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
+#define OMAP36XX_RTA_DISABLE 0x0
+
/* 34xx D2D idle-related pins, handled by PM core */
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
@@ -347,10 +351,11 @@ extern void omap3_save_scratchpad_contents(void);
extern void omap3_clear_scratchpad_contents(void);
extern u32 *get_restore_pointer(void);
extern u32 *get_es3_restore_pointer(void);
+extern u32 *get_omap3630_restore_pointer(void);
extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
-
+extern void omap3630_ctrl_disable_rta(void);
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 0348fd7..8d9aa3e 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -85,6 +85,8 @@ extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
+#define PM_RTA_ERRATUM_i608 (1 << 0)
+
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 5702f41..b32a2ed 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1007,6 +1007,8 @@ void omap_push_sram_idle(void)
static void __init pm_errata_configure(void)
{
+ if (cpu_is_omap3630())
+ pm34xx_errata |= PM_RTA_ERRATUM_i608;
}
static int __init omap3_pm_init(void)
@@ -1067,6 +1069,14 @@ static int __init omap3_pm_init(void)
pm_idle = omap3_pm_idle;
omap3_idle_init();
+ /*
+ * RTA is disabled during initialization as per erratum i608
+ * it is safer to disable rta by the bootloader, but we would like
+ * to be doubly sure here and prevent any mishaps.
+ */
+ if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
+ omap3630_ctrl_disable_rta();
+
clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
omap3_secure_ram_storage =
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 3fbd1e5..cc3507b 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -45,6 +45,8 @@
#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
#define SRAM_BASE_P 0x40200000
#define CONTROL_STAT 0x480022F0
+#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
+ + OMAP36XX_CONTROL_MEM_RTA_CTRL)
#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
* available */
#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
@@ -99,6 +101,14 @@ ENTRY(get_restore_pointer)
ldmfd sp!, {pc} @ restore regs and return
ENTRY(get_restore_pointer_sz)
.word . - get_restore_pointer
+ .text
+/* Function call to get the restore pointer for 3630 resume from OFF */
+ENTRY(get_omap3630_restore_pointer)
+ stmfd sp!, {lr} @ save registers on stack
+ adr r0, restore_3630
+ ldmfd sp!, {pc} @ restore regs and return
+ENTRY(get_omap3630_restore_pointer_sz)
+ .word . - get_omap3630_restore_pointer
.text
/* Function call to get the restore pointer for for ES3 to resume from OFF */
@@ -246,6 +256,20 @@ copy_to_sram:
bne copy_to_sram
ldr r1, sram_base
blx r1
+ b restore
+
+restore_3630:
+ /*b restore_es3630*/ @ Enable to debug restore code
+ ldr r1, pm_prepwstst_core_p
+ ldr r2, [r1]
+ and r2, r2, #0x3
+ cmp r2, #0x0 @ Check if previous power state of CORE is OFF
+ bne restore
+ /* Disable rta before giving control */
+ ldr r1, control_mem_rta
+ mov r2, #OMAP36XX_RTA_DISABLE
+ str r2, [r1]
+ /* Fall thru for the remaining logic */
restore:
/* b restore*/ @ Enable to debug restore code
/* Check what was the reason for mpu reset and store the reason in r9*/
@@ -650,6 +674,8 @@ cache_pred_disable_mask:
.word 0xFFFFE7FB
control_stat:
.word CONTROL_STAT
+control_mem_rta:
+ .word CONTROL_MEM_RTA_CTRL
kernel_flush:
.word v7_flush_dcache_all
/* these 2 words need to be@the end !!! */
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-18 22:53 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
This disables L2 cache before invalidating it and reenables it afterwards.
This is be done according to ARM documentation. Currently this is identified
as being needed on OMAP3630 as the disable/enable is done from "public side"
while, on OMAP3430, this is done in the "secure side".
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
[nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
v4: rebased only. no functional change
v3: http://marc.info/?l=linux-omap&m=129139583519221&w=2
collate all silicon specific errata under a single cpu detection code
making it elegant and more maintainable.
v2: https://patchwork.kernel.org/patch/365232/
rebased out to this series independent of HS bugfixes
v1: http://marc.info/?l=linux-omap&m=129013171125204&w=2
arch/arm/mach-omap2/pm.h | 2 ++
arch/arm/mach-omap2/pm34xx.c | 5 ++++-
arch/arm/mach-omap2/sleep34xx.S | 30 ++++++++++++++++++++++++++++++
3 files changed, 36 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8d9aa3e..5e0bee9 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz;
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
+extern void enable_omap3630_toggle_l2_on_restore(void);
#else
#define IS_PM34XX_ERRATUM(id) 0
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b32a2ed..4ba7a06 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1007,8 +1007,11 @@ void omap_push_sram_idle(void)
static void __init pm_errata_configure(void)
{
- if (cpu_is_omap3630())
+ if (cpu_is_omap3630()) {
pm34xx_errata |= PM_RTA_ERRATUM_i608;
+ /* Enable the l2 cache toggling in sleep logic */
+ enable_omap3630_toggle_l2_on_restore();
+ }
}
static int __init omap3_pm_init(void)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index cc3507b..d2eda01 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
.word . - get_omap3630_restore_pointer
.text
+/*
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
+ * This function sets up a fflag that will allow for this toggling to take
+ * place on 3630. Hopefully some version in the future maynot need this
+ */
+ENTRY(enable_omap3630_toggle_l2_on_restore)
+ stmfd sp!, {lr} @ save registers on stack
+ /* Setup so that we will disable and enable l2 */
+ mov r1, #0x1
+ str r1, l2dis_3630
+ ldmfd sp!, {pc} @ restore regs and return
+
+ .text
/* Function call to get the restore pointer for for ES3 to resume from OFF */
ENTRY(get_es3_restore_pointer)
stmfd sp!, {lr} @ save registers on stack
@@ -283,6 +296,14 @@ restore:
moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
bne logic_l1_restore
+
+ ldr r0, l2dis_3630
+ cmp r0, #0x1 @ should we disable L2 on 3630?
+ bne skipl2dis
+ mrc p15, 0, r0, c1, c0, 1
+ bic r0, r0, #2 @ disable L2 cache
+ mcr p15, 0, r0, c1, c0, 1
+skipl2dis:
ldr r0, control_stat
ldr r1, [r0]
and r1, #0x700
@@ -343,6 +364,13 @@ smi: .word 0xE1600070 @ Call SMI monitor (smieq)
mov r12, #0x2
.word 0xE1600070 @ Call SMI monitor (smieq)
logic_l1_restore:
+ ldr r1, l2dis_3630
+ cmp r1, #0x1 @ Do we need to re-enable L2 on 3630?
+ bne skipl2reen
+ mrc p15, 0, r1, c1, c0, 1
+ orr r1, r1, #2 @ re-enable L2 cache
+ mcr p15, 0, r1, c1, c0, 1
+skipl2reen:
mov r1, #0
/* Invalidate all instruction caches to PoU
* and flush branch target cache */
@@ -678,6 +706,8 @@ control_mem_rta:
.word CONTROL_MEM_RTA_CTRL
kernel_flush:
.word v7_flush_dcache_all
+l2dis_3630:
+ .word 0
/* these 2 words need to be at the end !!! */
kick_counter:
.word 0
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
@ 2010-12-18 22:53 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
This disables L2 cache before invalidating it and reenables it afterwards.
This is be done according to ARM documentation. Currently this is identified
as being needed on OMAP3630 as the disable/enable is done from "public side"
while, on OMAP3430, this is done in the "secure side".
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
[nm at ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
---
v4: rebased only. no functional change
v3: http://marc.info/?l=linux-omap&m=129139583519221&w=2
collate all silicon specific errata under a single cpu detection code
making it elegant and more maintainable.
v2: https://patchwork.kernel.org/patch/365232/
rebased out to this series independent of HS bugfixes
v1: http://marc.info/?l=linux-omap&m=129013171125204&w=2
arch/arm/mach-omap2/pm.h | 2 ++
arch/arm/mach-omap2/pm34xx.c | 5 ++++-
arch/arm/mach-omap2/sleep34xx.S | 30 ++++++++++++++++++++++++++++++
3 files changed, 36 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 8d9aa3e..5e0bee9 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz;
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
+extern void enable_omap3630_toggle_l2_on_restore(void);
#else
#define IS_PM34XX_ERRATUM(id) 0
+static inline void enable_omap3630_toggle_l2_on_restore(void) { }
#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b32a2ed..4ba7a06 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -1007,8 +1007,11 @@ void omap_push_sram_idle(void)
static void __init pm_errata_configure(void)
{
- if (cpu_is_omap3630())
+ if (cpu_is_omap3630()) {
pm34xx_errata |= PM_RTA_ERRATUM_i608;
+ /* Enable the l2 cache toggling in sleep logic */
+ enable_omap3630_toggle_l2_on_restore();
+ }
}
static int __init omap3_pm_init(void)
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index cc3507b..d2eda01 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
.word . - get_omap3630_restore_pointer
.text
+/*
+ * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
+ * This function sets up a fflag that will allow for this toggling to take
+ * place on 3630. Hopefully some version in the future maynot need this
+ */
+ENTRY(enable_omap3630_toggle_l2_on_restore)
+ stmfd sp!, {lr} @ save registers on stack
+ /* Setup so that we will disable and enable l2 */
+ mov r1, #0x1
+ str r1, l2dis_3630
+ ldmfd sp!, {pc} @ restore regs and return
+
+ .text
/* Function call to get the restore pointer for for ES3 to resume from OFF */
ENTRY(get_es3_restore_pointer)
stmfd sp!, {lr} @ save registers on stack
@@ -283,6 +296,14 @@ restore:
moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
bne logic_l1_restore
+
+ ldr r0, l2dis_3630
+ cmp r0, #0x1 @ should we disable L2 on 3630?
+ bne skipl2dis
+ mrc p15, 0, r0, c1, c0, 1
+ bic r0, r0, #2 @ disable L2 cache
+ mcr p15, 0, r0, c1, c0, 1
+skipl2dis:
ldr r0, control_stat
ldr r1, [r0]
and r1, #0x700
@@ -343,6 +364,13 @@ smi: .word 0xE1600070 @ Call SMI monitor (smieq)
mov r12, #0x2
.word 0xE1600070 @ Call SMI monitor (smieq)
logic_l1_restore:
+ ldr r1, l2dis_3630
+ cmp r1, #0x1 @ Do we need to re-enable L2 on 3630?
+ bne skipl2reen
+ mrc p15, 0, r1, c1, c0, 1
+ orr r1, r1, #2 @ re-enable L2 cache
+ mcr p15, 0, r1, c1, c0, 1
+skipl2reen:
mov r1, #0
/* Invalidate all instruction caches to PoU
* and flush branch target cache */
@@ -678,6 +706,8 @@ control_mem_rta:
.word CONTROL_MEM_RTA_CTRL
kernel_flush:
.word v7_flush_dcache_all
+l2dis_3630:
+ .word 0
/* these 2 words need to be at the end !!! */
kick_counter:
.word 0
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-18 22:53 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
Currently omap3_cpuidle_update_states makes whole sale decision
on which C states to update based on enable_off_mode variable
Instead, achieve the same functionality by independently providing
mpu and core deepest states the system is allowed to achieve and
update the idle states accordingly.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/cpuidle34xx.c | 19 ++++++++++---------
arch/arm/mach-omap2/pm.h | 3 ++-
arch/arm/mach-omap2/pm34xx.c | 2 +-
3 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 0d50b45..f80d3f6 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -293,25 +293,26 @@ select_state:
DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
/**
- * omap3_cpuidle_update_states - Update the cpuidle states.
+ * omap3_cpuidle_update_states() - Update the cpuidle states
+ * @mpu_deepest_state: Enable states upto and including this for mpu domain
+ * @core_deepest_state: Enable states upto and including this for core domain
*
- * Currently, this function toggles the validity of idle states based upon
- * the flag 'enable_off_mode'. When the flag is set all states are valid.
- * Else, states leading to OFF state set to be invalid.
+ * This goes through the list of states available and enables and disables the
+ * validity of C states based on deepest state that can be achieved for the
+ * variable domain
*/
-void omap3_cpuidle_update_states(void)
+void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
{
int i;
for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
struct omap3_processor_cx *cx = &omap3_power_states[i];
- if (enable_off_mode) {
+ if ((cx->mpu_state >= mpu_deepest_state) &&
+ (cx->core_state >= core_deepest_state)) {
cx->valid = 1;
} else {
- if ((cx->mpu_state == PWRDM_POWER_OFF) ||
- (cx->core_state == PWRDM_POWER_OFF))
- cx->valid = 0;
+ cx->valid = 0;
}
}
}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 5e0bee9..92ef400 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -58,7 +58,8 @@ extern u32 sleep_while_idle;
#endif
#if defined(CONFIG_CPU_IDLE)
-extern void omap3_cpuidle_update_states(void);
+extern void omap3_cpuidle_update_states(u32 core_deepest_state,
+ u32 core_deepest_state);
#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 4ba7a06..21cd36e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,7 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states();
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, &pwrst_list, node) {
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
@ 2010-12-18 22:53 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-arm-kernel
Currently omap3_cpuidle_update_states makes whole sale decision
on which C states to update based on enable_off_mode variable
Instead, achieve the same functionality by independently providing
mpu and core deepest states the system is allowed to achieve and
update the idle states accordingly.
Signed-off-by: Nishanth Menon <nm@ti.com>
---
arch/arm/mach-omap2/cpuidle34xx.c | 19 ++++++++++---------
arch/arm/mach-omap2/pm.h | 3 ++-
arch/arm/mach-omap2/pm34xx.c | 2 +-
3 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 0d50b45..f80d3f6 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -293,25 +293,26 @@ select_state:
DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
/**
- * omap3_cpuidle_update_states - Update the cpuidle states.
+ * omap3_cpuidle_update_states() - Update the cpuidle states
+ * @mpu_deepest_state: Enable states upto and including this for mpu domain
+ * @core_deepest_state: Enable states upto and including this for core domain
*
- * Currently, this function toggles the validity of idle states based upon
- * the flag 'enable_off_mode'. When the flag is set all states are valid.
- * Else, states leading to OFF state set to be invalid.
+ * This goes through the list of states available and enables and disables the
+ * validity of C states based on deepest state that can be achieved for the
+ * variable domain
*/
-void omap3_cpuidle_update_states(void)
+void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
{
int i;
for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
struct omap3_processor_cx *cx = &omap3_power_states[i];
- if (enable_off_mode) {
+ if ((cx->mpu_state >= mpu_deepest_state) &&
+ (cx->core_state >= core_deepest_state)) {
cx->valid = 1;
} else {
- if ((cx->mpu_state == PWRDM_POWER_OFF) ||
- (cx->core_state == PWRDM_POWER_OFF))
- cx->valid = 0;
+ cx->valid = 0;
}
}
}
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 5e0bee9..92ef400 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -58,7 +58,8 @@ extern u32 sleep_while_idle;
#endif
#if defined(CONFIG_CPU_IDLE)
-extern void omap3_cpuidle_update_states(void);
+extern void omap3_cpuidle_update_states(u32 core_deepest_state,
+ u32 core_deepest_state);
#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 4ba7a06..21cd36e 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,7 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states();
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, &pwrst_list, node) {
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-18 22:53 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
From: Eduardo Valentin <eduardo.valentin@nokia.com>
Limitation i583: Self_Refresh Exit issue after OFF mode
Issue:
When device is waking up from OFF mode, then SDRC state machine sends
inappropriate sequence violating JEDEC standards.
Impact:
OMAP3630 < ES1.2 is impacted as follows depending on the platform:
CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable, while
for all other sysclk frequencies, varied levels of instability
seen based on varied parameters.
CS1: impacted
This patch takes option #3 as recommended by the Silicon erratum:
Avoid core power domain transitioning to OFF mode. Power consumption
impact is expected in this case.
To do this, we route core OFF requests to RET request on the impacted
revisions of silicon.
[nm@ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a bit]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
---
v4: idle state control changed a bit -we wont register or enable
the states which cannot be enabled.
v3: http://marc.info/?t=129140247800027&r=1&w=2
no functional change in erratum wa implementation, just registration of
erratum is collated to a single cpu detection and version check
v2: https://patchwork.kernel.org/patch/365262/
rebased to this patch series instead of depending on hs changes
fix typo for macro definition
v1: http://marc.info/?l=linux-omap&m=129013173425266&w=2
arch/arm/mach-omap2/cpuidle34xx.c | 10 ++++++++++
arch/arm/mach-omap2/pm.h | 1 +
arch/arm/mach-omap2/pm34xx.c | 24 +++++++++++++++++++++---
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f80d3f6..1b32e98 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -453,6 +453,16 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
+
+ /*
+ * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+ * enable OFF mode in a stable form for previous revisions.
+ * we disable C7 state as a result.
+ */
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+ omap3_power_states[OMAP3_STATE_C7].valid = 0;
+ cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
+ }
}
struct cpuidle_driver omap3_idle_driver = {
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 92ef400..9032d09 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
#define PM_RTA_ERRATUM_i608 (1 << 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 21cd36e..7faea55 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states(state, state);
+ /*
+ * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+ * enable OFF mode in a stable form for previous revisions, restrict
+ * instead to RET
+ */
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+ omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
+ else
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, &pwrst_list, node) {
- pwrst->next_state = state;
- omap_set_pwrdm_state(pwrst->pwrdm, state);
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
+ pwrst->pwrdm == core_pwrdm &&
+ state == PWRDM_POWER_OFF) {
+ pwrst->next_state = PWRDM_POWER_RET;
+ pr_err("%s: Core OFF disabled due to errata i583\n",
+ __func__);
+ } else {
+ pwrst->next_state = state;
+ }
+ omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}
}
@@ -1011,6 +1027,8 @@ static void __init pm_errata_configure(void)
pm34xx_errata |= PM_RTA_ERRATUM_i608;
/* Enable the l2 cache toggling in sleep logic */
enable_omap3630_toggle_l2_on_restore();
+ if (omap_rev() < OMAP3630_REV_ES1_2)
+ pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
}
}
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
@ 2010-12-18 22:53 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-18 22:53 UTC (permalink / raw)
To: linux-arm-kernel
From: Eduardo Valentin <eduardo.valentin@nokia.com>
Limitation i583: Self_Refresh Exit issue after OFF mode
Issue:
When device is waking up from OFF mode, then SDRC state machine sends
inappropriate sequence violating JEDEC standards.
Impact:
OMAP3630 < ES1.2 is impacted as follows depending on the platform:
CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable, while
for all other sysclk frequencies, varied levels of instability
seen based on varied parameters.
CS1: impacted
This patch takes option #3 as recommended by the Silicon erratum:
Avoid core power domain transitioning to OFF mode. Power consumption
impact is expected in this case.
To do this, we route core OFF requests to RET request on the impacted
revisions of silicon.
[nm at ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a bit]
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
---
v4: idle state control changed a bit -we wont register or enable
the states which cannot be enabled.
v3: http://marc.info/?t=129140247800027&r=1&w=2
no functional change in erratum wa implementation, just registration of
erratum is collated to a single cpu detection and version check
v2: https://patchwork.kernel.org/patch/365262/
rebased to this patch series instead of depending on hs changes
fix typo for macro definition
v1: http://marc.info/?l=linux-omap&m=129013173425266&w=2
arch/arm/mach-omap2/cpuidle34xx.c | 10 ++++++++++
arch/arm/mach-omap2/pm.h | 1 +
arch/arm/mach-omap2/pm34xx.c | 24 +++++++++++++++++++++---
3 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index f80d3f6..1b32e98 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -453,6 +453,16 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
+
+ /*
+ * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+ * enable OFF mode in a stable form for previous revisions.
+ * we disable C7 state as a result.
+ */
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+ omap3_power_states[OMAP3_STATE_C7].valid = 0;
+ cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
+ }
}
struct cpuidle_driver omap3_idle_driver = {
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 92ef400..9032d09 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
#define PM_RTA_ERRATUM_i608 (1 << 0)
+#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 21cd36e..7faea55 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
- omap3_cpuidle_update_states(state, state);
+ /*
+ * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+ * enable OFF mode in a stable form for previous revisions, restrict
+ * instead to RET
+ */
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+ omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
+ else
+ omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, &pwrst_list, node) {
- pwrst->next_state = state;
- omap_set_pwrdm_state(pwrst->pwrdm, state);
+ if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
+ pwrst->pwrdm == core_pwrdm &&
+ state == PWRDM_POWER_OFF) {
+ pwrst->next_state = PWRDM_POWER_RET;
+ pr_err("%s: Core OFF disabled due to errata i583\n",
+ __func__);
+ } else {
+ pwrst->next_state = state;
+ }
+ omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}
}
@@ -1011,6 +1027,8 @@ static void __init pm_errata_configure(void)
pm34xx_errata |= PM_RTA_ERRATUM_i608;
/* Enable the l2 cache toggling in sleep logic */
enable_omap3630_toggle_l2_on_restore();
+ if (omap_rev() < OMAP3630_REV_ES1_2)
+ pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
}
}
--
1.6.3.3
^ permalink raw reply related [flat|nested] 75+ messages in thread
* RE: [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 6:43 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 6:43 UTC (permalink / raw)
To: Nishanth Menon, linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use
> v7_flush_dcache_all
>
> From: Richard Woodruff <r-woodruff2@ti.com>
>
> Analysis in TI kernel with ETM showed that using cache mapped flush
> in kernel instead of SO mapped flush cost drops by 65% (3.39mS down
> to 1.17mS) for clean_l2 which is used during sleep sequences.
> Overall:
> - speed up
> - unfortunately there isn't a good alternative flush method today
> - code reduction and less maintenance and potential bug in
> unmaintained code
>
> This also fixes the bug with the clean_l2 function usage.
>
> Reported-by: Tony Lindgren <tony@atomide.com>
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [nm@ti.com: ported rkw's proposal to 2.6.37-rc2]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
> ---
> (no change in this series, posted for completeness)
> v2: https://patchwork.kernel.org/patch/365222/
> v1: http://marc.info/?l=linux-omap&m=129013171325210&w=2
> arch/arm/mach-omap2/sleep34xx.S | 79
++++++----------------------------
> ----
> 1 files changed, 13 insertions(+), 66 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index 2fb205a..2c20fcf 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -520,72 +520,17 @@ clean_caches:
> cmp r9, #1 /* Check whether L2 inval is required or not*/
> bne skip_l2_inval
> clean_l2:
> - /* read clidr */
> - mrc p15, 1, r0, c0, c0, 1
> - /* extract loc from clidr */
> - ands r3, r0, #0x7000000
> - /* left align loc bit field */
> - mov r3, r3, lsr #23
> - /* if loc is 0, then no need to clean */
> - beq finished
> - /* start clean at cache level 0 */
> - mov r10, #0
> -loop1:
> - /* work out 3x current cache level */
> - add r2, r10, r10, lsr #1
> - /* extract cache type bits from clidr*/
> - mov r1, r0, lsr r2
> - /* mask of the bits for current cache only */
> - and r1, r1, #7
> - /* see what cache we have at this level */
> - cmp r1, #2
> - /* skip if no cache, or just i-cache */
> - blt skip
> - /* select current cache level in cssr */
> - mcr p15, 2, r10, c0, c0, 0
> - /* isb to sych the new cssr&csidr */
> - isb
> - /* read the new csidr */
> - mrc p15, 1, r1, c0, c0, 0
> - /* extract the length of the cache lines */
> - and r2, r1, #7
> - /* add 4 (line length offset) */
> - add r2, r2, #4
> - ldr r4, assoc_mask
> - /* find maximum number on the way size */
> - ands r4, r4, r1, lsr #3
> - /* find bit position of way size increment */
> - clz r5, r4
> - ldr r7, numset_mask
> - /* extract max number of the index size*/
> - ands r7, r7, r1, lsr #13
> -loop2:
> - mov r9, r4
> - /* create working copy of max way size*/
> -loop3:
> - /* factor way and cache number into r11 */
> - orr r11, r10, r9, lsl r5
> - /* factor index number into r11 */
> - orr r11, r11, r7, lsl r2
> - /*clean & invalidate by set/way */
> - mcr p15, 0, r11, c7, c10, 2
> - /* decrement the way*/
> - subs r9, r9, #1
> - bge loop3
> - /*decrement the index */
> - subs r7, r7, #1
> - bge loop2
> -skip:
> - add r10, r10, #2
> - /* increment cache number */
> - cmp r3, r10
> - bgt loop1
> -finished:
> - /*swith back to cache level 0 */
> - mov r10, #0
> - /* select current cache level in cssr */
> - mcr p15, 2, r10, c0, c0, 0
> - isb
> + /*
> + * Jump out to kernel flush routine
> + * - reuse that code is better
> + * - it executes in a cached space so is faster than refetch per-
> block
> + * - should be faster and will change with kernel
> + * - 'might' have to copy address, load and jump to it
Would be good to clarify that this is needed to maintain the 'lr'
when code is executed from SRAM
> + */
> + ldr r1, kernel_flush
> + mov lr, pc
> + bx r1
> +
> skip_l2_inval:
> /* Data memory barrier and Data sync barrier */
> mov r1, #0
> @@ -668,5 +613,7 @@ cache_pred_disable_mask:
> .word 0xFFFFE7FB
> control_stat:
> .word CONTROL_STAT
> +kernel_flush:
> + .word v7_flush_dcache_all
> ENTRY(omap34xx_cpu_suspend_sz)
> .word . - omap34xx_cpu_suspend
O.w
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
@ 2010-12-20 6:43 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 6:43 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use
> v7_flush_dcache_all
>
> From: Richard Woodruff <r-woodruff2@ti.com>
>
> Analysis in TI kernel with ETM showed that using cache mapped flush
> in kernel instead of SO mapped flush cost drops by 65% (3.39mS down
> to 1.17mS) for clean_l2 which is used during sleep sequences.
> Overall:
> - speed up
> - unfortunately there isn't a good alternative flush method today
> - code reduction and less maintenance and potential bug in
> unmaintained code
>
> This also fixes the bug with the clean_l2 function usage.
>
> Reported-by: Tony Lindgren <tony@atomide.com>
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [nm at ti.com: ported rkw's proposal to 2.6.37-rc2]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
> ---
> (no change in this series, posted for completeness)
> v2: https://patchwork.kernel.org/patch/365222/
> v1: http://marc.info/?l=linux-omap&m=129013171325210&w=2
> arch/arm/mach-omap2/sleep34xx.S | 79
++++++----------------------------
> ----
> 1 files changed, 13 insertions(+), 66 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index 2fb205a..2c20fcf 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -520,72 +520,17 @@ clean_caches:
> cmp r9, #1 /* Check whether L2 inval is required or not*/
> bne skip_l2_inval
> clean_l2:
> - /* read clidr */
> - mrc p15, 1, r0, c0, c0, 1
> - /* extract loc from clidr */
> - ands r3, r0, #0x7000000
> - /* left align loc bit field */
> - mov r3, r3, lsr #23
> - /* if loc is 0, then no need to clean */
> - beq finished
> - /* start clean at cache level 0 */
> - mov r10, #0
> -loop1:
> - /* work out 3x current cache level */
> - add r2, r10, r10, lsr #1
> - /* extract cache type bits from clidr*/
> - mov r1, r0, lsr r2
> - /* mask of the bits for current cache only */
> - and r1, r1, #7
> - /* see what cache we have at this level */
> - cmp r1, #2
> - /* skip if no cache, or just i-cache */
> - blt skip
> - /* select current cache level in cssr */
> - mcr p15, 2, r10, c0, c0, 0
> - /* isb to sych the new cssr&csidr */
> - isb
> - /* read the new csidr */
> - mrc p15, 1, r1, c0, c0, 0
> - /* extract the length of the cache lines */
> - and r2, r1, #7
> - /* add 4 (line length offset) */
> - add r2, r2, #4
> - ldr r4, assoc_mask
> - /* find maximum number on the way size */
> - ands r4, r4, r1, lsr #3
> - /* find bit position of way size increment */
> - clz r5, r4
> - ldr r7, numset_mask
> - /* extract max number of the index size*/
> - ands r7, r7, r1, lsr #13
> -loop2:
> - mov r9, r4
> - /* create working copy of max way size*/
> -loop3:
> - /* factor way and cache number into r11 */
> - orr r11, r10, r9, lsl r5
> - /* factor index number into r11 */
> - orr r11, r11, r7, lsl r2
> - /*clean & invalidate by set/way */
> - mcr p15, 0, r11, c7, c10, 2
> - /* decrement the way*/
> - subs r9, r9, #1
> - bge loop3
> - /*decrement the index */
> - subs r7, r7, #1
> - bge loop2
> -skip:
> - add r10, r10, #2
> - /* increment cache number */
> - cmp r3, r10
> - bgt loop1
> -finished:
> - /*swith back to cache level 0 */
> - mov r10, #0
> - /* select current cache level in cssr */
> - mcr p15, 2, r10, c0, c0, 0
> - isb
> + /*
> + * Jump out to kernel flush routine
> + * - reuse that code is better
> + * - it executes in a cached space so is faster than refetch per-
> block
> + * - should be faster and will change with kernel
> + * - 'might' have to copy address, load and jump to it
Would be good to clarify that this is needed to maintain the 'lr'
when code is executed from SRAM
> + */
> + ldr r1, kernel_flush
> + mov lr, pc
> + bx r1
> +
> skip_l2_inval:
> /* Data memory barrier and Data sync barrier */
> mov r1, #0
> @@ -668,5 +613,7 @@ cache_pred_disable_mask:
> .word 0xFFFFE7FB
> control_stat:
> .word CONTROL_STAT
> +kernel_flush:
> + .word v7_flush_dcache_all
> ENTRY(omap34xx_cpu_suspend_sz)
> .word . - omap34xx_cpu_suspend
O.w
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 6:47 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 6:47 UTC (permalink / raw)
To: Nishanth Menon, linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick
strategy
>
> From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>
> Erratum i581 impacts OMAP3 platforms.
> PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing
> the DPLL not to be locked at times.
>
> IMPORTANT:
> *) This is not a complete workaround implementation as recommended
> by the silicon erratum. this is a support logic for detecting lockups
and
> attempting to recover where possible and is known to provide stability
> in multiple platforms.
> *) This code is mostly important for inactive and retention. The ROM
code
> waits for the maximum dll lock time when resuming from off mode. So for
> off mode this code isn't really needed.
>
> This should eventually get refactored as part of cleanups to sleep34xx.S
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> ---
> (no change done, posting for completeness of the series)
> v2: https://patchwork.kernel.org/patch/365252/
> typo correction- erratum, support, added comment from Peter from
the
> thread to commit message
> v1: http://marc.info/?l=linux-omap&m=129013172525234&w=2
> arch/arm/mach-omap2/sleep34xx.S | 52
> +++++++++++++++++++++++++++++++++++---
> 1 files changed, 47 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index 2c20fcf..3fbd1e5 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -42,6 +42,7 @@
> OMAP3430_PM_PREPWSTST)
> #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD +
> OMAP2_PM_PWSTCTRL
> #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
> +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
We need to avoid these macro's calculating VA directly. But I guess
it needs to be done more than just this line and hence can be done
in a separate patch.
> #define SRAM_BASE_P 0x40200000
> #define CONTROL_STAT 0x480022F0
> #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
> @@ -554,31 +555,67 @@ skip_l2_inval:
>
> /* Make sure SDRC accesses are ok */
> wait_sdrc_ok:
> +
> +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures
> this. */
> + ldr r4, cm_idlest_ckgen
> +wait_dpll3_lock:
> + ldr r5, [r4]
> + tst r5, #1
> + beq wait_dpll3_lock
> +
> ldr r4, cm_idlest1_core
> +wait_sdrc_ready:
> ldr r5, [r4]
> - and r5, r5, #0x2
> - cmp r5, #0
> - bne wait_sdrc_ok
> + tst r5, #0x2
> + bne wait_sdrc_ready
> + /* allow DLL powerdown upon hw idle req */
> ldr r4, sdrc_power
> ldr r5, [r4]
> bic r5, r5, #0x40
> str r5, [r4]
> -wait_dll_lock:
> +is_dll_in_lock_mode:
> +
> /* Is dll in lock mode? */
> ldr r4, sdrc_dlla_ctrl
> ldr r5, [r4]
> tst r5, #0x4
> bxne lr
> /* wait till dll locks */
> - ldr r4, sdrc_dlla_status
> +wait_dll_lock_timed:
> + ldr r4, wait_dll_lock_counter
> + add r4, r4, #1
> + str r4, wait_dll_lock_counter
> + ldr r4, sdrc_dlla_status
> + mov r6, #8 /* Wait 20uS for lock */
> +wait_dll_lock:
> + subs r6, r6, #0x1
> + beq kick_dll
> ldr r5, [r4]
> and r5, r5, #0x4
> cmp r5, #0x4
> bne wait_dll_lock
> bx lr
>
> + /* disable/reenable DLL if not locked */
> +kick_dll:
> + ldr r4, sdrc_dlla_ctrl
> + ldr r5, [r4]
> + mov r6, r5
> + bic r6, #(1<<3) /* disable dll */
> + str r6, [r4]
> + dsb
> + orr r6, r6, #(1<<3) /* enable dll */
> + str r6, [r4]
> + dsb
> + ldr r4, kick_counter
> + add r4, r4, #1
> + str r4, kick_counter
> + b wait_dll_lock_timed
> +
> cm_idlest1_core:
> .word CM_IDLEST1_CORE_V
> +cm_idlest_ckgen:
> + .word CM_IDLEST_CKGEN_V
> sdrc_dlla_status:
> .word SDRC_DLLA_STATUS_V
> sdrc_dlla_ctrl:
> @@ -615,5 +652,10 @@ control_stat:
> .word CONTROL_STAT
> kernel_flush:
> .word v7_flush_dcache_all
> + /* these 2 words need to be at the end !!! */
> +kick_counter:
> + .word 0
> +wait_dll_lock_counter:
> + .word 0
> ENTRY(omap34xx_cpu_suspend_sz)
> .word . - omap34xx_cpu_suspend
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
@ 2010-12-20 6:47 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 6:47 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick
strategy
>
> From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>
> Erratum i581 impacts OMAP3 platforms.
> PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing
> the DPLL not to be locked at times.
>
> IMPORTANT:
> *) This is not a complete workaround implementation as recommended
> by the silicon erratum. this is a support logic for detecting lockups
and
> attempting to recover where possible and is known to provide stability
> in multiple platforms.
> *) This code is mostly important for inactive and retention. The ROM
code
> waits for the maximum dll lock time when resuming from off mode. So for
> off mode this code isn't really needed.
>
> This should eventually get refactored as part of cleanups to sleep34xx.S
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> ---
> (no change done, posting for completeness of the series)
> v2: https://patchwork.kernel.org/patch/365252/
> typo correction- erratum, support, added comment from Peter from
the
> thread to commit message
> v1: http://marc.info/?l=linux-omap&m=129013172525234&w=2
> arch/arm/mach-omap2/sleep34xx.S | 52
> +++++++++++++++++++++++++++++++++++---
> 1 files changed, 47 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index 2c20fcf..3fbd1e5 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -42,6 +42,7 @@
> OMAP3430_PM_PREPWSTST)
> #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD +
> OMAP2_PM_PWSTCTRL
> #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
> +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
We need to avoid these macro's calculating VA directly. But I guess
it needs to be done more than just this line and hence can be done
in a separate patch.
> #define SRAM_BASE_P 0x40200000
> #define CONTROL_STAT 0x480022F0
> #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
> @@ -554,31 +555,67 @@ skip_l2_inval:
>
> /* Make sure SDRC accesses are ok */
> wait_sdrc_ok:
> +
> +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures
> this. */
> + ldr r4, cm_idlest_ckgen
> +wait_dpll3_lock:
> + ldr r5, [r4]
> + tst r5, #1
> + beq wait_dpll3_lock
> +
> ldr r4, cm_idlest1_core
> +wait_sdrc_ready:
> ldr r5, [r4]
> - and r5, r5, #0x2
> - cmp r5, #0
> - bne wait_sdrc_ok
> + tst r5, #0x2
> + bne wait_sdrc_ready
> + /* allow DLL powerdown upon hw idle req */
> ldr r4, sdrc_power
> ldr r5, [r4]
> bic r5, r5, #0x40
> str r5, [r4]
> -wait_dll_lock:
> +is_dll_in_lock_mode:
> +
> /* Is dll in lock mode? */
> ldr r4, sdrc_dlla_ctrl
> ldr r5, [r4]
> tst r5, #0x4
> bxne lr
> /* wait till dll locks */
> - ldr r4, sdrc_dlla_status
> +wait_dll_lock_timed:
> + ldr r4, wait_dll_lock_counter
> + add r4, r4, #1
> + str r4, wait_dll_lock_counter
> + ldr r4, sdrc_dlla_status
> + mov r6, #8 /* Wait 20uS for lock */
> +wait_dll_lock:
> + subs r6, r6, #0x1
> + beq kick_dll
> ldr r5, [r4]
> and r5, r5, #0x4
> cmp r5, #0x4
> bne wait_dll_lock
> bx lr
>
> + /* disable/reenable DLL if not locked */
> +kick_dll:
> + ldr r4, sdrc_dlla_ctrl
> + ldr r5, [r4]
> + mov r6, r5
> + bic r6, #(1<<3) /* disable dll */
> + str r6, [r4]
> + dsb
> + orr r6, r6, #(1<<3) /* enable dll */
> + str r6, [r4]
> + dsb
> + ldr r4, kick_counter
> + add r4, r4, #1
> + str r4, kick_counter
> + b wait_dll_lock_timed
> +
> cm_idlest1_core:
> .word CM_IDLEST1_CORE_V
> +cm_idlest_ckgen:
> + .word CM_IDLEST_CKGEN_V
> sdrc_dlla_status:
> .word SDRC_DLLA_STATUS_V
> sdrc_dlla_ctrl:
> @@ -615,5 +652,10 @@ control_stat:
> .word CONTROL_STAT
> kernel_flush:
> .word v7_flush_dcache_all
> + /* these 2 words need to be at the end !!! */
> +kick_counter:
> + .word 0
> +wait_dll_lock_counter:
> + .word 0
> ENTRY(omap34xx_cpu_suspend_sz)
> .word . - omap34xx_cpu_suspend
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 6:51 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 6:51 UTC (permalink / raw)
To: Nishanth Menon, linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if <
> ES1.2
>
> From: Eduardo Valentin <eduardo.valentin@nokia.com>
>
> Limitation i583: Self_Refresh Exit issue after OFF mode
>
> Issue:
> When device is waking up from OFF mode, then SDRC state machine sends
> inappropriate sequence violating JEDEC standards.
>
> Impact:
> OMAP3630 < ES1.2 is impacted as follows depending on the platform:
> CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable,
while
> for all other sysclk frequencies, varied levels of instability
> seen based on varied parameters.
> CS1: impacted
>
> This patch takes option #3 as recommended by the Silicon erratum:
> Avoid core power domain transitioning to OFF mode. Power consumption
> impact is expected in this case.
> To do this, we route core OFF requests to RET request on the impacted
> revisions of silicon.
>
> [nm@ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a
> bit]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
> ---
> v4: idle state control changed a bit -we wont register or enable
> the states which cannot be enabled.
> v3: http://marc.info/?t=129140247800027&r=1&w=2
> no functional change in erratum wa implementation, just registration
> of
> erratum is collated to a single cpu detection and version check
> v2: https://patchwork.kernel.org/patch/365262/
> rebased to this patch series instead of depending on hs changes
> fix typo for macro definition
> v1: http://marc.info/?l=linux-omap&m=129013173425266&w=2
> arch/arm/mach-omap2/cpuidle34xx.c | 10 ++++++++++
> arch/arm/mach-omap2/pm.h | 1 +
> arch/arm/mach-omap2/pm34xx.c | 24 +++++++++++++++++++++---
> 3 files changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-
> omap2/cpuidle34xx.c
> index f80d3f6..1b32e98 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -453,6 +453,16 @@ void omap_init_power_states(void)
> omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
> omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID
|
> CPUIDLE_FLAG_CHECK_BM;
> +
> + /*
> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We
> cannot
> + * enable OFF mode in a stable form for previous revisions.
> + * we disable C7 state as a result.
> + */
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
> + omap3_power_states[OMAP3_STATE_C7].valid = 0;
> + cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
WARN_ONCE in IDLE also would be good.
> + }
> }
>
> struct cpuidle_driver omap3_idle_driver = {
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 92ef400..9032d09 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
> extern unsigned int omap34xx_cpu_suspend_sz;
>
> #define PM_RTA_ERRATUM_i608 (1 << 0)
> +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
>
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 21cd36e..7faea55 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
> state = PWRDM_POWER_RET;
>
> #ifdef CONFIG_CPU_IDLE
> - omap3_cpuidle_update_states(state, state);
> + /*
> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We
> cannot
> + * enable OFF mode in a stable form for previous revisions,
restrict
> + * instead to RET
> + */
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
> + omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
> + else
> + omap3_cpuidle_update_states(state, state);
> #endif
>
> list_for_each_entry(pwrst, &pwrst_list, node) {
> - pwrst->next_state = state;
> - omap_set_pwrdm_state(pwrst->pwrdm, state);
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
> + pwrst->pwrdm == core_pwrdm &&
> + state == PWRDM_POWER_OFF) {
> + pwrst->next_state = PWRDM_POWER_RET;
> + pr_err("%s: Core OFF disabled due to errata
i583\n",
Shoud we do this in every iteration or just WARN_ONCE do ??
> + __func__);
> + } else {
> + pwrst->next_state = state;
> + }
> + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
> }
> }
>
> @@ -1011,6 +1027,8 @@ static void __init pm_errata_configure(void)
> pm34xx_errata |= PM_RTA_ERRATUM_i608;
> /* Enable the l2 cache toggling in sleep logic */
> enable_omap3630_toggle_l2_on_restore();
> + if (omap_rev() < OMAP3630_REV_ES1_2)
> + pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
> }
> }
>
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
@ 2010-12-20 6:51 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 6:51 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if <
> ES1.2
>
> From: Eduardo Valentin <eduardo.valentin@nokia.com>
>
> Limitation i583: Self_Refresh Exit issue after OFF mode
>
> Issue:
> When device is waking up from OFF mode, then SDRC state machine sends
> inappropriate sequence violating JEDEC standards.
>
> Impact:
> OMAP3630 < ES1.2 is impacted as follows depending on the platform:
> CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable,
while
> for all other sysclk frequencies, varied levels of instability
> seen based on varied parameters.
> CS1: impacted
>
> This patch takes option #3 as recommended by the Silicon erratum:
> Avoid core power domain transitioning to OFF mode. Power consumption
> impact is expected in this case.
> To do this, we route core OFF requests to RET request on the impacted
> revisions of silicon.
>
> [nm at ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a
> bit]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
> ---
> v4: idle state control changed a bit -we wont register or enable
> the states which cannot be enabled.
> v3: http://marc.info/?t=129140247800027&r=1&w=2
> no functional change in erratum wa implementation, just registration
> of
> erratum is collated to a single cpu detection and version check
> v2: https://patchwork.kernel.org/patch/365262/
> rebased to this patch series instead of depending on hs changes
> fix typo for macro definition
> v1: http://marc.info/?l=linux-omap&m=129013173425266&w=2
> arch/arm/mach-omap2/cpuidle34xx.c | 10 ++++++++++
> arch/arm/mach-omap2/pm.h | 1 +
> arch/arm/mach-omap2/pm34xx.c | 24 +++++++++++++++++++++---
> 3 files changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-
> omap2/cpuidle34xx.c
> index f80d3f6..1b32e98 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -453,6 +453,16 @@ void omap_init_power_states(void)
> omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
> omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID
|
> CPUIDLE_FLAG_CHECK_BM;
> +
> + /*
> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We
> cannot
> + * enable OFF mode in a stable form for previous revisions.
> + * we disable C7 state as a result.
> + */
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
> + omap3_power_states[OMAP3_STATE_C7].valid = 0;
> + cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
WARN_ONCE in IDLE also would be good.
> + }
> }
>
> struct cpuidle_driver omap3_idle_driver = {
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 92ef400..9032d09 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
> extern unsigned int omap34xx_cpu_suspend_sz;
>
> #define PM_RTA_ERRATUM_i608 (1 << 0)
> +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
>
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 21cd36e..7faea55 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
> state = PWRDM_POWER_RET;
>
> #ifdef CONFIG_CPU_IDLE
> - omap3_cpuidle_update_states(state, state);
> + /*
> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We
> cannot
> + * enable OFF mode in a stable form for previous revisions,
restrict
> + * instead to RET
> + */
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
> + omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
> + else
> + omap3_cpuidle_update_states(state, state);
> #endif
>
> list_for_each_entry(pwrst, &pwrst_list, node) {
> - pwrst->next_state = state;
> - omap_set_pwrdm_state(pwrst->pwrdm, state);
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
> + pwrst->pwrdm == core_pwrdm &&
> + state == PWRDM_POWER_OFF) {
> + pwrst->next_state = PWRDM_POWER_RET;
> + pr_err("%s: Core OFF disabled due to errata
i583\n",
Shoud we do this in every iteration or just WARN_ONCE do ??
> + __func__);
> + } else {
> + pwrst->next_state = state;
> + }
> + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
> }
> }
>
> @@ -1011,6 +1027,8 @@ static void __init pm_errata_configure(void)
> pm34xx_errata |= PM_RTA_ERRATUM_i608;
> /* Enable the l2 cache toggling in sleep logic */
> enable_omap3630_toggle_l2_on_restore();
> + if (omap_rev() < OMAP3630_REV_ES1_2)
> + pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
> }
> }
>
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 6:59 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 6:59 UTC (permalink / raw)
To: Nishanth Menon, linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
Nishant
> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
>
> Erratum id: i608
> RTA (Retention Till Access) feature is not supported and leads to device
> stability issues when enabled. This impacts modules with embedded
memories
> on OMAP3630
>
> Workaround is to disable RTA on boot and coming out of core off.
> For disabling rta coming out of off mode, we do this by overriding the
> restore pointer for 3630 to allow us restore handler as the first point
of
> entry before caches are touched and is common for GP and HS devices.
> to disable earlier than this could be possible by modifying the ppa for
HS
> devices, but not for GP devices.
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [ambresh@ti.com: co-developer]
> Signed-off-by: Ambresh K <ambresh@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
> v4:
> control register handling moved to control.c
> errata handling framework introduction split out
> into a separate patch
> v3: http://marc.info/?t=129140247800026&r=1&w=2
> additional comment to explain Ambresh's contrib
> removed the redundant check for cpu_is34xx - it is already
> done by pm_init
> pm_errata_configure is __init
> v2: https://patchwork.kernel.org/patch/365242/
> fixed missing b restore for 3430 es3.1 code.
> introduced erratum handling logic here splitting it out of uart
> errata
> typo fixes for erratum
> v1: http://marc.info/?l=linux-omap&m=129013172825240&w=2
>
> arch/arm/mach-omap2/control.c | 13 ++++++++++++-
> arch/arm/mach-omap2/control.h | 7 ++++++-
> arch/arm/mach-omap2/pm.h | 2 ++
> arch/arm/mach-omap2/pm34xx.c | 10 ++++++++++
> arch/arm/mach-omap2/sleep34xx.S | 26 ++++++++++++++++++++++++++
> 5 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c
b/arch/arm/mach-omap2/control.c
> index 1fa3294..27ed558 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
>
> /* Populate the Scratchpad contents */
> scratchpad_contents.boot_config_ptr = 0x0;
> - if (omap_rev() != OMAP3430_REV_ES3_0 &&
> + if (cpu_is_omap3630())
> + scratchpad_contents.public_restore_ptr =
> + virt_to_phys(get_omap3630_restore_pointer());
> + else if (omap_rev() != OMAP3430_REV_ES3_0 &&
> omap_rev() != OMAP3430_REV_ES3_1)
> scratchpad_contents.public_restore_ptr =
> virt_to_phys(get_restore_pointer());
> @@ -474,4 +477,12 @@ void omap3_control_restore_context(void)
> omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
> return;
> }
> +
> +void omap3630_ctrl_disable_rta(void)
> +{
> + if (!cpu_is_omap3630())
> + return;
> + omap_ctrl_writel(OMAP36XX_RTA_DISABLE,
> OMAP36XX_CONTROL_MEM_RTA_CTRL);
> +}
> +
> #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
> diff --git a/arch/arm/mach-omap2/control.h
b/arch/arm/mach-omap2/control.h
> index b6c6b7c..ec98dd7 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -204,6 +204,10 @@
> #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP +
> 0x014)
> #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP +
> 0x018)
>
> +/* 36xx-only RTA - Retention till Accesss control registers and bits */
> +#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
> +#define OMAP36XX_RTA_DISABLE 0x0
> +
> /* 34xx D2D idle-related pins, handled by PM core */
> #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
> #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
> @@ -347,10 +351,11 @@ extern void omap3_save_scratchpad_contents(void);
> extern void omap3_clear_scratchpad_contents(void);
> extern u32 *get_restore_pointer(void);
> extern u32 *get_es3_restore_pointer(void);
> +extern u32 *get_omap3630_restore_pointer(void);
> extern u32 omap3_arm_context[128];
> extern void omap3_control_save_context(void);
> extern void omap3_control_restore_context(void);
> -
> +extern void omap3630_ctrl_disable_rta(void);
> #else
> #define omap_ctrl_base_get() 0
> #define omap_ctrl_readb(x) 0
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 0348fd7..8d9aa3e 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -85,6 +85,8 @@ extern unsigned int save_secure_ram_context_sz;
> extern unsigned int omap24xx_cpu_suspend_sz;
> extern unsigned int omap34xx_cpu_suspend_sz;
>
> +#define PM_RTA_ERRATUM_i608 (1 << 0)
> +
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 5702f41..b32a2ed 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -1007,6 +1007,8 @@ void omap_push_sram_idle(void)
>
> static void __init pm_errata_configure(void)
> {
> + if (cpu_is_omap3630())
> + pm34xx_errata |= PM_RTA_ERRATUM_i608;
> }
>
> static int __init omap3_pm_init(void)
> @@ -1067,6 +1069,14 @@ static int __init omap3_pm_init(void)
> pm_idle = omap3_pm_idle;
> omap3_idle_init();
>
> + /*
> + * RTA is disabled during initialization as per erratum i608
> + * it is safer to disable rta by the bootloader, but we would like
> + * to be doubly sure here and prevent any mishaps.
> + */
> + if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
> + omap3630_ctrl_disable_rta();
> +
> clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
> if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
> omap3_secure_ram_storage =
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index 3fbd1e5..cc3507b 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -45,6 +45,8 @@
> #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
> #define SRAM_BASE_P 0x40200000
> #define CONTROL_STAT 0x480022F0
> +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
> + + OMAP36XX_CONTROL_MEM_RTA_CTRL)
Just a clarification. This register is not part of HW SAR SCM
Registers, right ?
> #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
> * available */
> #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +
> OMAP343X_CONTROL_MEM_WKUP\
> @@ -99,6 +101,14 @@ ENTRY(get_restore_pointer)
> ldmfd sp!, {pc} @ restore regs and return
> ENTRY(get_restore_pointer_sz)
> .word . - get_restore_pointer
> + .text
> +/* Function call to get the restore pointer for 3630 resume from OFF */
> +ENTRY(get_omap3630_restore_pointer)
> + stmfd sp!, {lr} @ save registers on stack
> + adr r0, restore_3630
> + ldmfd sp!, {pc} @ restore regs and return
> +ENTRY(get_omap3630_restore_pointer_sz)
> + .word . - get_omap3630_restore_pointer
>
> .text
> /* Function call to get the restore pointer for for ES3 to resume from
> OFF */
> @@ -246,6 +256,20 @@ copy_to_sram:
> bne copy_to_sram
> ldr r1, sram_base
> blx r1
> + b restore
> +
> +restore_3630:
> + /*b restore_es3630*/ @ Enable to debug restore code
> + ldr r1, pm_prepwstst_core_p
> + ldr r2, [r1]
> + and r2, r2, #0x3
> + cmp r2, #0x0 @ Check if previous power state of CORE is
OFF
> + bne restore
> + /* Disable rta before giving control */
> + ldr r1, control_mem_rta
> + mov r2, #OMAP36XX_RTA_DISABLE
> + str r2, [r1]
> + /* Fall thru for the remaining logic */
> restore:
> /* b restore*/ @ Enable to debug restore code
> /* Check what was the reason for mpu reset and store the reason
> in r9*/
> @@ -650,6 +674,8 @@ cache_pred_disable_mask:
> .word 0xFFFFE7FB
> control_stat:
> .word CONTROL_STAT
> +control_mem_rta:
> + .word CONTROL_MEM_RTA_CTRL
> kernel_flush:
> .word v7_flush_dcache_all
> /* these 2 words need to be at the end !!! */
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
@ 2010-12-20 6:59 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 6:59 UTC (permalink / raw)
To: linux-arm-kernel
Nishant
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
>
> Erratum id: i608
> RTA (Retention Till Access) feature is not supported and leads to device
> stability issues when enabled. This impacts modules with embedded
memories
> on OMAP3630
>
> Workaround is to disable RTA on boot and coming out of core off.
> For disabling rta coming out of off mode, we do this by overriding the
> restore pointer for 3630 to allow us restore handler as the first point
of
> entry before caches are touched and is common for GP and HS devices.
> to disable earlier than this could be possible by modifying the ppa for
HS
> devices, but not for GP devices.
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [ambresh at ti.com: co-developer]
> Signed-off-by: Ambresh K <ambresh@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
> v4:
> control register handling moved to control.c
> errata handling framework introduction split out
> into a separate patch
> v3: http://marc.info/?t=129140247800026&r=1&w=2
> additional comment to explain Ambresh's contrib
> removed the redundant check for cpu_is34xx - it is already
> done by pm_init
> pm_errata_configure is __init
> v2: https://patchwork.kernel.org/patch/365242/
> fixed missing b restore for 3430 es3.1 code.
> introduced erratum handling logic here splitting it out of uart
> errata
> typo fixes for erratum
> v1: http://marc.info/?l=linux-omap&m=129013172825240&w=2
>
> arch/arm/mach-omap2/control.c | 13 ++++++++++++-
> arch/arm/mach-omap2/control.h | 7 ++++++-
> arch/arm/mach-omap2/pm.h | 2 ++
> arch/arm/mach-omap2/pm34xx.c | 10 ++++++++++
> arch/arm/mach-omap2/sleep34xx.S | 26 ++++++++++++++++++++++++++
> 5 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c
b/arch/arm/mach-omap2/control.c
> index 1fa3294..27ed558 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
>
> /* Populate the Scratchpad contents */
> scratchpad_contents.boot_config_ptr = 0x0;
> - if (omap_rev() != OMAP3430_REV_ES3_0 &&
> + if (cpu_is_omap3630())
> + scratchpad_contents.public_restore_ptr =
> + virt_to_phys(get_omap3630_restore_pointer());
> + else if (omap_rev() != OMAP3430_REV_ES3_0 &&
> omap_rev() != OMAP3430_REV_ES3_1)
> scratchpad_contents.public_restore_ptr =
> virt_to_phys(get_restore_pointer());
> @@ -474,4 +477,12 @@ void omap3_control_restore_context(void)
> omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
> return;
> }
> +
> +void omap3630_ctrl_disable_rta(void)
> +{
> + if (!cpu_is_omap3630())
> + return;
> + omap_ctrl_writel(OMAP36XX_RTA_DISABLE,
> OMAP36XX_CONTROL_MEM_RTA_CTRL);
> +}
> +
> #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
> diff --git a/arch/arm/mach-omap2/control.h
b/arch/arm/mach-omap2/control.h
> index b6c6b7c..ec98dd7 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -204,6 +204,10 @@
> #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP +
> 0x014)
> #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP +
> 0x018)
>
> +/* 36xx-only RTA - Retention till Accesss control registers and bits */
> +#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
> +#define OMAP36XX_RTA_DISABLE 0x0
> +
> /* 34xx D2D idle-related pins, handled by PM core */
> #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
> #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
> @@ -347,10 +351,11 @@ extern void omap3_save_scratchpad_contents(void);
> extern void omap3_clear_scratchpad_contents(void);
> extern u32 *get_restore_pointer(void);
> extern u32 *get_es3_restore_pointer(void);
> +extern u32 *get_omap3630_restore_pointer(void);
> extern u32 omap3_arm_context[128];
> extern void omap3_control_save_context(void);
> extern void omap3_control_restore_context(void);
> -
> +extern void omap3630_ctrl_disable_rta(void);
> #else
> #define omap_ctrl_base_get() 0
> #define omap_ctrl_readb(x) 0
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 0348fd7..8d9aa3e 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -85,6 +85,8 @@ extern unsigned int save_secure_ram_context_sz;
> extern unsigned int omap24xx_cpu_suspend_sz;
> extern unsigned int omap34xx_cpu_suspend_sz;
>
> +#define PM_RTA_ERRATUM_i608 (1 << 0)
> +
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 5702f41..b32a2ed 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -1007,6 +1007,8 @@ void omap_push_sram_idle(void)
>
> static void __init pm_errata_configure(void)
> {
> + if (cpu_is_omap3630())
> + pm34xx_errata |= PM_RTA_ERRATUM_i608;
> }
>
> static int __init omap3_pm_init(void)
> @@ -1067,6 +1069,14 @@ static int __init omap3_pm_init(void)
> pm_idle = omap3_pm_idle;
> omap3_idle_init();
>
> + /*
> + * RTA is disabled during initialization as per erratum i608
> + * it is safer to disable rta by the bootloader, but we would like
> + * to be doubly sure here and prevent any mishaps.
> + */
> + if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
> + omap3630_ctrl_disable_rta();
> +
> clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
> if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
> omap3_secure_ram_storage =
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index 3fbd1e5..cc3507b 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -45,6 +45,8 @@
> #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
> #define SRAM_BASE_P 0x40200000
> #define CONTROL_STAT 0x480022F0
> +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
> + + OMAP36XX_CONTROL_MEM_RTA_CTRL)
Just a clarification. This register is not part of HW SAR SCM
Registers, right ?
> #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
> * available */
> #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +
> OMAP343X_CONTROL_MEM_WKUP\
> @@ -99,6 +101,14 @@ ENTRY(get_restore_pointer)
> ldmfd sp!, {pc} @ restore regs and return
> ENTRY(get_restore_pointer_sz)
> .word . - get_restore_pointer
> + .text
> +/* Function call to get the restore pointer for 3630 resume from OFF */
> +ENTRY(get_omap3630_restore_pointer)
> + stmfd sp!, {lr} @ save registers on stack
> + adr r0, restore_3630
> + ldmfd sp!, {pc} @ restore regs and return
> +ENTRY(get_omap3630_restore_pointer_sz)
> + .word . - get_omap3630_restore_pointer
>
> .text
> /* Function call to get the restore pointer for for ES3 to resume from
> OFF */
> @@ -246,6 +256,20 @@ copy_to_sram:
> bne copy_to_sram
> ldr r1, sram_base
> blx r1
> + b restore
> +
> +restore_3630:
> + /*b restore_es3630*/ @ Enable to debug restore code
> + ldr r1, pm_prepwstst_core_p
> + ldr r2, [r1]
> + and r2, r2, #0x3
> + cmp r2, #0x0 @ Check if previous power state of CORE is
OFF
> + bne restore
> + /* Disable rta before giving control */
> + ldr r1, control_mem_rta
> + mov r2, #OMAP36XX_RTA_DISABLE
> + str r2, [r1]
> + /* Fall thru for the remaining logic */
> restore:
> /* b restore*/ @ Enable to debug restore code
> /* Check what was the reason for mpu reset and store the reason
> in r9*/
> @@ -650,6 +674,8 @@ cache_pred_disable_mask:
> .word 0xFFFFE7FB
> control_stat:
> .word CONTROL_STAT
> +control_mem_rta:
> + .word CONTROL_MEM_RTA_CTRL
> kernel_flush:
> .word v7_flush_dcache_all
> /* these 2 words need to be at the end !!! */
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 7:13 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 7:13 UTC (permalink / raw)
To: Nishanth Menon, linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
invalidating
> L2 cache
>
> From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>
> This disables L2 cache before invalidating it and reenables it
afterwards.
> This is be done according to ARM documentation. Currently this is
> identified
> as being needed on OMAP3630 as the disable/enable is done from "public
> side"
> while, on OMAP3430, this is done in the "secure side".
Can you point me to ARM doc which says " for L2 invalidation, the
controller
needs to be disabled" ?
L2 invalidation can be done with L2 enabled or disabled. Infact if I look
at
below code, effective $L2 will get enabled only when 'C' bit is enabled
it shouldn't matter really.
After looking further I guess it might be needed because L2AUXCTRL
Configuration is getting changed. In that case for sure the sequence
used here is right.
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only
on
> 3630]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> ---
As such patch is fine with me.
> v4: rebased only. no functional change
> v3: http://marc.info/?l=linux-omap&m=129139583519221&w=2
> collate all silicon specific errata under a single cpu detection code
> making it elegant and more maintainable.
> v2: https://patchwork.kernel.org/patch/365232/
> rebased out to this series independent of HS bugfixes
> v1: http://marc.info/?l=linux-omap&m=129013171125204&w=2
>
> arch/arm/mach-omap2/pm.h | 2 ++
> arch/arm/mach-omap2/pm34xx.c | 5 ++++-
> arch/arm/mach-omap2/sleep34xx.S | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 36 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 8d9aa3e..5e0bee9 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz;
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
> +extern void enable_omap3630_toggle_l2_on_restore(void);
> #else
> #define IS_PM34XX_ERRATUM(id) 0
> +static inline void enable_omap3630_toggle_l2_on_restore(void) { }
> #endif /* defined(CONFIG_PM) &&
defined(CONFIG_ARCH_OMAP3) */
>
> #endif
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index b32a2ed..4ba7a06 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -1007,8 +1007,11 @@ void omap_push_sram_idle(void)
>
> static void __init pm_errata_configure(void)
> {
> - if (cpu_is_omap3630())
> + if (cpu_is_omap3630()) {
> pm34xx_errata |= PM_RTA_ERRATUM_i608;
> + /* Enable the l2 cache toggling in sleep logic */
> + enable_omap3630_toggle_l2_on_restore();
> + }
> }
>
> static int __init omap3_pm_init(void)
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index cc3507b..d2eda01 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
> .word . - get_omap3630_restore_pointer
>
> .text
> +/*
> + * L2 cache needs to be toggled for stable OFF mode functionality on
3630.
> + * This function sets up a fflag that will allow for this toggling to
> take
> + * place on 3630. Hopefully some version in the future maynot need this
> + */
> +ENTRY(enable_omap3630_toggle_l2_on_restore)
> + stmfd sp!, {lr} @ save registers on stack
> + /* Setup so that we will disable and enable l2 */
> + mov r1, #0x1
> + str r1, l2dis_3630
> + ldmfd sp!, {pc} @ restore regs and return
> +
> + .text
> /* Function call to get the restore pointer for for ES3 to resume from
> OFF */
> ENTRY(get_es3_restore_pointer)
> stmfd sp!, {lr} @ save registers on stack
> @@ -283,6 +296,14 @@ restore:
> moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
> movne r9, #0x1 @ Only L1 and L2 lost => avoid L2
invalidation
> bne logic_l1_restore
> +
> + ldr r0, l2dis_3630
> + cmp r0, #0x1 @ should we disable L2 on 3630?
> + bne skipl2dis
> + mrc p15, 0, r0, c1, c0, 1
> + bic r0, r0, #2 @ disable L2 cache
> + mcr p15, 0, r0, c1, c0, 1
> +skipl2dis:
> ldr r0, control_stat
> ldr r1, [r0]
> and r1, #0x700
> @@ -343,6 +364,13 @@ smi: .word 0xE1600070 @ Call SMI monitor
> (smieq)
> mov r12, #0x2
> .word 0xE1600070 @ Call SMI monitor (smieq)
> logic_l1_restore:
> + ldr r1, l2dis_3630
> + cmp r1, #0x1 @ Do we need to re-enable L2 on 3630?
> + bne skipl2reen
> + mrc p15, 0, r1, c1, c0, 1
> + orr r1, r1, #2 @ re-enable L2 cache
> + mcr p15, 0, r1, c1, c0, 1
> +skipl2reen:
> mov r1, #0
> /* Invalidate all instruction caches to PoU
> * and flush branch target cache */
> @@ -678,6 +706,8 @@ control_mem_rta:
> .word CONTROL_MEM_RTA_CTRL
> kernel_flush:
> .word v7_flush_dcache_all
> +l2dis_3630:
> + .word 0
> /* these 2 words need to be at the end !!! */
> kick_counter:
> .word 0
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
@ 2010-12-20 7:13 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 7:13 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
invalidating
> L2 cache
>
> From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>
> This disables L2 cache before invalidating it and reenables it
afterwards.
> This is be done according to ARM documentation. Currently this is
> identified
> as being needed on OMAP3630 as the disable/enable is done from "public
> side"
> while, on OMAP3430, this is done in the "secure side".
Can you point me to ARM doc which says " for L2 invalidation, the
controller
needs to be disabled" ?
L2 invalidation can be done with L2 enabled or disabled. Infact if I look
at
below code, effective $L2 will get enabled only when 'C' bit is enabled
it shouldn't matter really.
After looking further I guess it might be needed because L2AUXCTRL
Configuration is getting changed. In that case for sure the sequence
used here is right.
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [nm at ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only
on
> 3630]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> ---
As such patch is fine with me.
> v4: rebased only. no functional change
> v3: http://marc.info/?l=linux-omap&m=129139583519221&w=2
> collate all silicon specific errata under a single cpu detection code
> making it elegant and more maintainable.
> v2: https://patchwork.kernel.org/patch/365232/
> rebased out to this series independent of HS bugfixes
> v1: http://marc.info/?l=linux-omap&m=129013171125204&w=2
>
> arch/arm/mach-omap2/pm.h | 2 ++
> arch/arm/mach-omap2/pm34xx.c | 5 ++++-
> arch/arm/mach-omap2/sleep34xx.S | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 36 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 8d9aa3e..5e0bee9 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz;
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
> +extern void enable_omap3630_toggle_l2_on_restore(void);
> #else
> #define IS_PM34XX_ERRATUM(id) 0
> +static inline void enable_omap3630_toggle_l2_on_restore(void) { }
> #endif /* defined(CONFIG_PM) &&
defined(CONFIG_ARCH_OMAP3) */
>
> #endif
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index b32a2ed..4ba7a06 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -1007,8 +1007,11 @@ void omap_push_sram_idle(void)
>
> static void __init pm_errata_configure(void)
> {
> - if (cpu_is_omap3630())
> + if (cpu_is_omap3630()) {
> pm34xx_errata |= PM_RTA_ERRATUM_i608;
> + /* Enable the l2 cache toggling in sleep logic */
> + enable_omap3630_toggle_l2_on_restore();
> + }
> }
>
> static int __init omap3_pm_init(void)
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
> omap2/sleep34xx.S
> index cc3507b..d2eda01 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
> .word . - get_omap3630_restore_pointer
>
> .text
> +/*
> + * L2 cache needs to be toggled for stable OFF mode functionality on
3630.
> + * This function sets up a fflag that will allow for this toggling to
> take
> + * place on 3630. Hopefully some version in the future maynot need this
> + */
> +ENTRY(enable_omap3630_toggle_l2_on_restore)
> + stmfd sp!, {lr} @ save registers on stack
> + /* Setup so that we will disable and enable l2 */
> + mov r1, #0x1
> + str r1, l2dis_3630
> + ldmfd sp!, {pc} @ restore regs and return
> +
> + .text
> /* Function call to get the restore pointer for for ES3 to resume from
> OFF */
> ENTRY(get_es3_restore_pointer)
> stmfd sp!, {lr} @ save registers on stack
> @@ -283,6 +296,14 @@ restore:
> moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
> movne r9, #0x1 @ Only L1 and L2 lost => avoid L2
invalidation
> bne logic_l1_restore
> +
> + ldr r0, l2dis_3630
> + cmp r0, #0x1 @ should we disable L2 on 3630?
> + bne skipl2dis
> + mrc p15, 0, r0, c1, c0, 1
> + bic r0, r0, #2 @ disable L2 cache
> + mcr p15, 0, r0, c1, c0, 1
> +skipl2dis:
> ldr r0, control_stat
> ldr r1, [r0]
> and r1, #0x700
> @@ -343,6 +364,13 @@ smi: .word 0xE1600070 @ Call SMI monitor
> (smieq)
> mov r12, #0x2
> .word 0xE1600070 @ Call SMI monitor (smieq)
> logic_l1_restore:
> + ldr r1, l2dis_3630
> + cmp r1, #0x1 @ Do we need to re-enable L2 on 3630?
> + bne skipl2reen
> + mrc p15, 0, r1, c1, c0, 1
> + orr r1, r1, #2 @ re-enable L2 cache
> + mcr p15, 0, r1, c1, c0, 1
> +skipl2reen:
> mov r1, #0
> /* Invalidate all instruction caches to PoU
> * and flush branch target cache */
> @@ -678,6 +706,8 @@ control_mem_rta:
> .word CONTROL_MEM_RTA_CTRL
> kernel_flush:
> .word v7_flush_dcache_all
> +l2dis_3630:
> + .word 0
> /* these 2 words need to be at the end !!! */
> kick_counter:
> .word 0
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 7:16 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 7:16 UTC (permalink / raw)
To: Nishanth Menon, linux-omap, linux-arm; +Cc: Jean Pihet, Kevin, Tony
> -----Original Message-----
> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
> owner@vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states
> independent of enable_off_mode
>
> Currently omap3_cpuidle_update_states makes whole sale decision
> on which C states to update based on enable_off_mode variable
> Instead, achieve the same functionality by independently providing
> mpu and core deepest states the system is allowed to achieve and
> update the idle states accordingly.
>
Thanks Nishant for this change. Indeed it's better than using the debug
related flag.
> Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/cpuidle34xx.c | 19 ++++++++++---------
> arch/arm/mach-omap2/pm.h | 3 ++-
> arch/arm/mach-omap2/pm34xx.c | 2 +-
> 3 files changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-
> omap2/cpuidle34xx.c
> index 0d50b45..f80d3f6 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -293,25 +293,26 @@ select_state:
> DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
>
> /**
> - * omap3_cpuidle_update_states - Update the cpuidle states.
> + * omap3_cpuidle_update_states() - Update the cpuidle states
> + * @mpu_deepest_state: Enable states upto and including this for
mpu
> domain
> + * @core_deepest_state: Enable states upto and including this for
> core domain
> *
> - * Currently, this function toggles the validity of idle states based
> upon
> - * the flag 'enable_off_mode'. When the flag is set all states are
valid.
> - * Else, states leading to OFF state set to be invalid.
> + * This goes through the list of states available and enables and
> disables the
> + * validity of C states based on deepest state that can be achieved for
> the
> + * variable domain
> */
> -void omap3_cpuidle_update_states(void)
> +void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32
> core_deepest_state)
> {
> int i;
>
> for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
> struct omap3_processor_cx *cx = &omap3_power_states[i];
>
> - if (enable_off_mode) {
> + if ((cx->mpu_state >= mpu_deepest_state) &&
> + (cx->core_state >= core_deepest_state)) {
> cx->valid = 1;
> } else {
> - if ((cx->mpu_state == PWRDM_POWER_OFF) ||
> - (cx->core_state == PWRDM_POWER_OFF))
> - cx->valid = 0;
> + cx->valid = 0;
> }
> }
> }
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 5e0bee9..92ef400 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -58,7 +58,8 @@ extern u32 sleep_while_idle;
> #endif
>
> #if defined(CONFIG_CPU_IDLE)
> -extern void omap3_cpuidle_update_states(void);
> +extern void omap3_cpuidle_update_states(u32 core_deepest_state,
> + u32 core_deepest_state);
> #endif
>
> #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 4ba7a06..21cd36e 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -928,7 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
> state = PWRDM_POWER_RET;
>
> #ifdef CONFIG_CPU_IDLE
> - omap3_cpuidle_update_states();
> + omap3_cpuidle_update_states(state, state);
> #endif
>
> list_for_each_entry(pwrst, &pwrst_list, node) {
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
@ 2010-12-20 7:16 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 7:16 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Nishanth Menon
> Sent: Sunday, December 19, 2010 4:24 AM
> To: linux-omap; linux-arm
> Cc: Jean Pihet; Kevin; Tony
> Subject: [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states
> independent of enable_off_mode
>
> Currently omap3_cpuidle_update_states makes whole sale decision
> on which C states to update based on enable_off_mode variable
> Instead, achieve the same functionality by independently providing
> mpu and core deepest states the system is allowed to achieve and
> update the idle states accordingly.
>
Thanks Nishant for this change. Indeed it's better than using the debug
related flag.
> Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> ---
> arch/arm/mach-omap2/cpuidle34xx.c | 19 ++++++++++---------
> arch/arm/mach-omap2/pm.h | 3 ++-
> arch/arm/mach-omap2/pm34xx.c | 2 +-
> 3 files changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-
> omap2/cpuidle34xx.c
> index 0d50b45..f80d3f6 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -293,25 +293,26 @@ select_state:
> DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
>
> /**
> - * omap3_cpuidle_update_states - Update the cpuidle states.
> + * omap3_cpuidle_update_states() - Update the cpuidle states
> + * @mpu_deepest_state: Enable states upto and including this for
mpu
> domain
> + * @core_deepest_state: Enable states upto and including this for
> core domain
> *
> - * Currently, this function toggles the validity of idle states based
> upon
> - * the flag 'enable_off_mode'. When the flag is set all states are
valid.
> - * Else, states leading to OFF state set to be invalid.
> + * This goes through the list of states available and enables and
> disables the
> + * validity of C states based on deepest state that can be achieved for
> the
> + * variable domain
> */
> -void omap3_cpuidle_update_states(void)
> +void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32
> core_deepest_state)
> {
> int i;
>
> for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
> struct omap3_processor_cx *cx = &omap3_power_states[i];
>
> - if (enable_off_mode) {
> + if ((cx->mpu_state >= mpu_deepest_state) &&
> + (cx->core_state >= core_deepest_state)) {
> cx->valid = 1;
> } else {
> - if ((cx->mpu_state == PWRDM_POWER_OFF) ||
> - (cx->core_state == PWRDM_POWER_OFF))
> - cx->valid = 0;
> + cx->valid = 0;
> }
> }
> }
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 5e0bee9..92ef400 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -58,7 +58,8 @@ extern u32 sleep_while_idle;
> #endif
>
> #if defined(CONFIG_CPU_IDLE)
> -extern void omap3_cpuidle_update_states(void);
> +extern void omap3_cpuidle_update_states(u32 core_deepest_state,
> + u32 core_deepest_state);
> #endif
>
> #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 4ba7a06..21cd36e 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -928,7 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
> state = PWRDM_POWER_RET;
>
> #ifdef CONFIG_CPU_IDLE
> - omap3_cpuidle_update_states();
> + omap3_cpuidle_update_states(state, state);
> #endif
>
> list_for_each_entry(pwrst, &pwrst_list, node) {
> --
> 1.6.3.3
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 0/7] OMAP: idle path errata fixes
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 10:17 ` Jean Pihet
-1 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:17 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Kevin, Tony
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> Hi,
> as discussed in [1], here is step 2 - idle path errata fixes.
> this is the next rev incorporating comments from V2 post
> of this series.
>
> Tested:
> this series:
> SDP3430
> SDP3630
> this series + ASM cleanup series[2]
> SDP3430
> SDP3630
> Test Script:
> http://elinux.org/OMAP_Power_Management#Quick_verification_of_suspend-idle_functionality
This series + ASM cleanup series[2]:
Tested OK on Beagleboard with full RET and OFF modes,
using cpuidle.
Tested-by: Jean Pihet <j-pihet@ti.com>
>
> V3: http://marc.info/?t=129140247800030&r=1&w=2
>
> V2: http://marc.info/?l=linux-omap&m=129106200408109&w=2
>
> Major change in V3:
> Erratas are now handled per silicon - it is much cleaner :)
> no more redundant cpu_is_omap34xx check anymore
> errata configure is __init as it should be
>
> Eduardo Valentin (1):
> OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
>
> Nishanth Menon (3):
> omap3: pm: introduce errata handling
> OMAP3630: PM: Erratum i608: disable RTA
> OMAP3: PM: make omap3_cpuidle_update_states independent of
> enable_off_mode
>
> Peter 'p2' De Schrijver (2):
> OMAP3: PM: Erratum i581 support: dll kick strategy
> OMAP3630: PM: Disable L2 cache while invalidating L2 cache
>
> Richard Woodruff (1):
> OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
>
> arch/arm/mach-omap2/control.c | 13 +++-
> arch/arm/mach-omap2/control.h | 7 +-
> arch/arm/mach-omap2/cpuidle34xx.c | 29 ++++--
> arch/arm/mach-omap2/pm.h | 15 +++-
> arch/arm/mach-omap2/pm34xx.c | 46 +++++++++-
> arch/arm/mach-omap2/sleep34xx.S | 187 +++++++++++++++++++++++--------------
> 6 files changed, 211 insertions(+), 86 deletions(-)
>
> bloat-o-meter report Vs 2.6.37-rc6
> add/remove: 2/0 grow/shrink: 7/0 up/down: 297/0 (297)
> function old new delta
> omap3_pm_off_mode_enable 80 160 +80
> omap3_pm_init 1792 1872 +80
> omap3630_ctrl_disable_rta - 44 +44
> omap3_save_scratchpad_contents 732 760 +28
> static.__func__ 13783 13808 +25
> vermagic 45 60 +15
> linux_banner 132 147 +15
> prcm_interrupt_handler 268 276 +8
> pm34xx_errata - 2 +2
>
> [1] http://marc.info/?l=linux-omap&m=129045338806957&w=2
> [2] http://marc.info/?l=linux-omap&m=129268746417556&w=2
>
> Cc: Charulatha Varadarajan <charu@ti.com>
> Cc: Jean Pihet <jean.pihet@newoldbits.com>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Tao Hu <tghk48@motorola.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Vishwanath Sripathy <vishwanath.bs@ti.com>
>
> ---
> Regards,
> Nishanth Menon
>
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 0/7] OMAP: idle path errata fixes
@ 2010-12-20 10:17 ` Jean Pihet
0 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:17 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> Hi,
> as discussed in [1], here is step 2 - idle path errata fixes.
> this is the next rev incorporating comments from V2 post
> of this series.
>
> Tested:
> this series:
> ? ? ? ?SDP3430
> ? ? ? ?SDP3630
> this series + ASM cleanup series[2]
> ? ? ? ?SDP3430
> ? ? ? ?SDP3630
> Test Script:
> http://elinux.org/OMAP_Power_Management#Quick_verification_of_suspend-idle_functionality
This series + ASM cleanup series[2]:
Tested OK on Beagleboard with full RET and OFF modes,
using cpuidle.
Tested-by: Jean Pihet <j-pihet@ti.com>
>
> V3: http://marc.info/?t=129140247800030&r=1&w=2
>
> V2: http://marc.info/?l=linux-omap&m=129106200408109&w=2
>
> Major change in V3:
> ? ? ? ?Erratas are now handled per silicon - it is much cleaner :)
> ? ? ? ?no more redundant cpu_is_omap34xx check anymore
> ? ? ? ?errata configure is __init as it should be
>
> Eduardo Valentin (1):
> ?OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
>
> Nishanth Menon (3):
> ?omap3: pm: introduce errata handling
> ?OMAP3630: PM: Erratum i608: disable RTA
> ?OMAP3: PM: make omap3_cpuidle_update_states independent of
> ? ?enable_off_mode
>
> Peter 'p2' De Schrijver (2):
> ?OMAP3: PM: Erratum i581 support: dll kick strategy
> ?OMAP3630: PM: Disable L2 cache while invalidating L2 cache
>
> Richard Woodruff (1):
> ?OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
>
> ?arch/arm/mach-omap2/control.c ? ? | ? 13 +++-
> ?arch/arm/mach-omap2/control.h ? ? | ? ?7 +-
> ?arch/arm/mach-omap2/cpuidle34xx.c | ? 29 ++++--
> ?arch/arm/mach-omap2/pm.h ? ? ? ? ?| ? 15 +++-
> ?arch/arm/mach-omap2/pm34xx.c ? ? ?| ? 46 +++++++++-
> ?arch/arm/mach-omap2/sleep34xx.S ? | ?187 +++++++++++++++++++++++--------------
> ?6 files changed, 211 insertions(+), 86 deletions(-)
>
> bloat-o-meter report Vs 2.6.37-rc6
> add/remove: 2/0 grow/shrink: 7/0 up/down: 297/0 (297)
> function ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? old ? ? new ? delta
> omap3_pm_off_mode_enable ? ? ? ? ? ? ? ? ? ? ?80 ? ? 160 ? ? +80
> omap3_pm_init ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1792 ? ?1872 ? ? +80
> omap3630_ctrl_disable_rta ? ? ? ? ? ? ? ? ? ? ?- ? ? ?44 ? ? +44
> omap3_save_scratchpad_contents ? ? ? ? ? ? ? 732 ? ? 760 ? ? +28
> static.__func__ ? ? ? ? ? ? ? ? ? ? ? ? ? ?13783 ? 13808 ? ? +25
> vermagic ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?45 ? ? ?60 ? ? +15
> linux_banner ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 132 ? ? 147 ? ? +15
> prcm_interrupt_handler ? ? ? ? ? ? ? ? ? ? ? 268 ? ? 276 ? ? ?+8
> pm34xx_errata ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?- ? ? ? 2 ? ? ?+2
>
> [1] http://marc.info/?l=linux-omap&m=129045338806957&w=2
> [2] http://marc.info/?l=linux-omap&m=129268746417556&w=2
>
> Cc: Charulatha Varadarajan <charu@ti.com>
> Cc: Jean Pihet <jean.pihet@newoldbits.com>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Tao Hu <tghk48@motorola.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Vishwanath Sripathy <vishwanath.bs@ti.com>
>
> ---
> Regards,
> Nishanth Menon
>
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 3/7] omap3: pm: introduce errata handling
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 10:18 ` Jean Pihet
-1 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:18 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Kevin, Tony
Hi Nishant,
Here a few minor remarks about typos:
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> Introduce errata handling for omap3. This patch introduces
Use caps for OMAP3
> errata variable and and stub for initialization which will be
and and -> and
> filled up by followon patches.
followon -> follow-on?
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
> Splitting the errata introduction out into it's own separate patch
>
> arch/arm/mach-omap2/pm.h | 7 +++++++
> arch/arm/mach-omap2/pm34xx.c | 9 +++++++++
> 2 files changed, 16 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 0d75bfd..0348fd7 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -85,4 +85,11 @@ extern unsigned int save_secure_ram_context_sz;
> extern unsigned int omap24xx_cpu_suspend_sz;
> extern unsigned int omap34xx_cpu_suspend_sz;
>
> +#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> +extern u16 pm34xx_errata;
> +#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
> +#else
> +#define IS_PM34XX_ERRATUM(id) 0
> +#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
> +
> #endif
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 648b8c5..5702f41 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -68,6 +68,9 @@ static inline bool is_suspending(void)
> #define OMAP343X_TABLE_VALUE_OFFSET 0xc0
> #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
>
> +/* pm34xx errata defined in pm.h */
> +u16 pm34xx_errata;
> +
> struct power_state {
> struct powerdomain *pwrdm;
> u32 next_state;
> @@ -1002,6 +1005,10 @@ void omap_push_sram_idle(void)
> save_secure_ram_context_sz);
> }
>
> +static void __init pm_errata_configure(void)
> +{
> +}
> +
> static int __init omap3_pm_init(void)
> {
> struct power_state *pwrst, *tmp;
> @@ -1011,6 +1018,8 @@ static int __init omap3_pm_init(void)
> if (!cpu_is_omap34xx())
> return -ENODEV;
>
> + pm_errata_configure();
> +
> printk(KERN_ERR "Power Management for TI OMAP3.\n");
>
> /* XXX prcm_setup_regs needs to be before enabling hw
> --
> 1.6.3.3
>
>
Jean
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To unsubscribe from this list: send the line "unsubscribe linux-omap" in
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 3/7] omap3: pm: introduce errata handling
@ 2010-12-20 10:18 ` Jean Pihet
0 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi Nishant,
Here a few minor remarks about typos:
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> Introduce errata handling for omap3. This patch introduces
Use caps for OMAP3
> errata variable and and stub for initialization which will be
and and -> and
> filled up by followon patches.
followon -> follow-on?
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
> Splitting the errata introduction out into it's own separate patch
>
> ?arch/arm/mach-omap2/pm.h ? ? | ? ?7 +++++++
> ?arch/arm/mach-omap2/pm34xx.c | ? ?9 +++++++++
> ?2 files changed, 16 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 0d75bfd..0348fd7 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -85,4 +85,11 @@ extern unsigned int save_secure_ram_context_sz;
> ?extern unsigned int omap24xx_cpu_suspend_sz;
> ?extern unsigned int omap34xx_cpu_suspend_sz;
>
> +#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> +extern u16 pm34xx_errata;
> +#define IS_PM34XX_ERRATUM(id) ? ? ? ? ?(pm34xx_errata & (id))
> +#else
> +#define IS_PM34XX_ERRATUM(id) ? ? ? ? ?0
> +#endif ? ? ? ? /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
> +
> ?#endif
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 648b8c5..5702f41 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -68,6 +68,9 @@ static inline bool is_suspending(void)
> ?#define OMAP343X_TABLE_VALUE_OFFSET ? ? ? 0xc0
> ?#define OMAP343X_CONTROL_REG_VALUE_OFFSET ?0xc8
>
> +/* pm34xx errata defined in pm.h */
> +u16 pm34xx_errata;
> +
> ?struct power_state {
> ? ? ? ?struct powerdomain *pwrdm;
> ? ? ? ?u32 next_state;
> @@ -1002,6 +1005,10 @@ void omap_push_sram_idle(void)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?save_secure_ram_context_sz);
> ?}
>
> +static void __init pm_errata_configure(void)
> +{
> +}
> +
> ?static int __init omap3_pm_init(void)
> ?{
> ? ? ? ?struct power_state *pwrst, *tmp;
> @@ -1011,6 +1018,8 @@ static int __init omap3_pm_init(void)
> ? ? ? ?if (!cpu_is_omap34xx())
> ? ? ? ? ? ? ? ?return -ENODEV;
>
> + ? ? ? pm_errata_configure();
> +
> ? ? ? ?printk(KERN_ERR "Power Management for TI OMAP3.\n");
>
> ? ? ? ?/* XXX prcm_setup_regs needs to be before enabling hw
> --
> 1.6.3.3
>
>
Jean
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
2010-12-20 6:43 ` Santosh Shilimkar
@ 2010-12-20 10:19 ` Jean Pihet
-1 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:19 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: Nishanth Menon, linux-omap, linux-arm, Kevin, Tony
On Mon, Dec 20, 2010 at 7:43 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
>> owner@vger.kernel.org] On Behalf Of Nishanth Menon
>> Sent: Sunday, December 19, 2010 4:24 AM
>> To: linux-omap; linux-arm
>> Cc: Jean Pihet; Kevin; Tony
>> Subject: [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use
>> v7_flush_dcache_all
>>
>> From: Richard Woodruff <r-woodruff2@ti.com>
>>
>> Analysis in TI kernel with ETM showed that using cache mapped flush
>> in kernel instead of SO mapped flush cost drops by 65% (3.39mS down
>> to 1.17mS) for clean_l2 which is used during sleep sequences.
>> Overall:
>> - speed up
>> - unfortunately there isn't a good alternative flush method today
>> - code reduction and less maintenance and potential bug in
>> unmaintained code
>>
>> This also fixes the bug with the clean_l2 function usage.
>>
>> Reported-by: Tony Lindgren <tony@atomide.com>
>>
>> Cc: Kevin Hilman <khilman@deeprootsystems.com>
>> Cc: Tony Lindgren <tony@atomide.com>
>>
>> [nm@ti.com: ported rkw's proposal to 2.6.37-rc2]
>> Signed-off-by: Nishanth Menon <nm@ti.com>
>> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
>> ---
>> (no change in this series, posted for completeness)
>> v2: https://patchwork.kernel.org/patch/365222/
>> v1: http://marc.info/?l=linux-omap&m=129013171325210&w=2
>> arch/arm/mach-omap2/sleep34xx.S | 79
> ++++++----------------------------
>> ----
>> 1 files changed, 13 insertions(+), 66 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
>> omap2/sleep34xx.S
>> index 2fb205a..2c20fcf 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -520,72 +520,17 @@ clean_caches:
>> cmp r9, #1 /* Check whether L2 inval is required or not*/
>> bne skip_l2_inval
>> clean_l2:
>> - /* read clidr */
>> - mrc p15, 1, r0, c0, c0, 1
>> - /* extract loc from clidr */
>> - ands r3, r0, #0x7000000
>> - /* left align loc bit field */
>> - mov r3, r3, lsr #23
>> - /* if loc is 0, then no need to clean */
>> - beq finished
>> - /* start clean at cache level 0 */
>> - mov r10, #0
>> -loop1:
>> - /* work out 3x current cache level */
>> - add r2, r10, r10, lsr #1
>> - /* extract cache type bits from clidr*/
>> - mov r1, r0, lsr r2
>> - /* mask of the bits for current cache only */
>> - and r1, r1, #7
>> - /* see what cache we have at this level */
>> - cmp r1, #2
>> - /* skip if no cache, or just i-cache */
>> - blt skip
>> - /* select current cache level in cssr */
>> - mcr p15, 2, r10, c0, c0, 0
>> - /* isb to sych the new cssr&csidr */
>> - isb
>> - /* read the new csidr */
>> - mrc p15, 1, r1, c0, c0, 0
>> - /* extract the length of the cache lines */
>> - and r2, r1, #7
>> - /* add 4 (line length offset) */
>> - add r2, r2, #4
>> - ldr r4, assoc_mask
>> - /* find maximum number on the way size */
>> - ands r4, r4, r1, lsr #3
>> - /* find bit position of way size increment */
>> - clz r5, r4
>> - ldr r7, numset_mask
>> - /* extract max number of the index size*/
>> - ands r7, r7, r1, lsr #13
>> -loop2:
>> - mov r9, r4
>> - /* create working copy of max way size*/
>> -loop3:
>> - /* factor way and cache number into r11 */
>> - orr r11, r10, r9, lsl r5
>> - /* factor index number into r11 */
>> - orr r11, r11, r7, lsl r2
>> - /*clean & invalidate by set/way */
>> - mcr p15, 0, r11, c7, c10, 2
>> - /* decrement the way*/
>> - subs r9, r9, #1
>> - bge loop3
>> - /*decrement the index */
>> - subs r7, r7, #1
>> - bge loop2
>> -skip:
>> - add r10, r10, #2
>> - /* increment cache number */
>> - cmp r3, r10
>> - bgt loop1
>> -finished:
>> - /*swith back to cache level 0 */
>> - mov r10, #0
>> - /* select current cache level in cssr */
>> - mcr p15, 2, r10, c0, c0, 0
>> - isb
>> + /*
>> + * Jump out to kernel flush routine
>> + * - reuse that code is better
>> + * - it executes in a cached space so is faster than refetch per-
>> block
>> + * - should be faster and will change with kernel
>> + * - 'might' have to copy address, load and jump to it
> Would be good to clarify that this is needed to maintain the 'lr'
> when code is executed from SRAM
>
Agree on that. Some comments have been posted at
http://marc.info/?l=linux-omap&m=129016170719489&w=2.
>> + */
>> + ldr r1, kernel_flush
>> + mov lr, pc
>> + bx r1
>> +
>> skip_l2_inval:
>> /* Data memory barrier and Data sync barrier */
>> mov r1, #0
>> @@ -668,5 +613,7 @@ cache_pred_disable_mask:
>> .word 0xFFFFE7FB
>> control_stat:
>> .word CONTROL_STAT
>> +kernel_flush:
>> + .word v7_flush_dcache_all
>> ENTRY(omap34xx_cpu_suspend_sz)
>> .word . - omap34xx_cpu_suspend
>
> O.w
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
>
>> --
>> 1.6.3.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
Jean
--
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all
@ 2010-12-20 10:19 ` Jean Pihet
0 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:19 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Dec 20, 2010 at 7:43 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
>> owner at vger.kernel.org] On Behalf Of Nishanth Menon
>> Sent: Sunday, December 19, 2010 4:24 AM
>> To: linux-omap; linux-arm
>> Cc: Jean Pihet; Kevin; Tony
>> Subject: [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use
>> v7_flush_dcache_all
>>
>> From: Richard Woodruff <r-woodruff2@ti.com>
>>
>> Analysis in TI kernel with ETM showed that using cache mapped flush
>> in kernel instead of SO mapped flush cost drops by 65% (3.39mS down
>> to 1.17mS) for clean_l2 which is used during sleep sequences.
>> Overall:
>> ? ? ? - speed up
>> ? ? ? - unfortunately there isn't a good alternative flush method today
>> ? ? ? - code reduction and less maintenance and potential bug in
>> ? ? ? ? unmaintained code
>>
>> This also fixes the bug with the clean_l2 function usage.
>>
>> Reported-by: Tony Lindgren <tony@atomide.com>
>>
>> Cc: Kevin Hilman <khilman@deeprootsystems.com>
>> Cc: Tony Lindgren <tony@atomide.com>
>>
>> [nm at ti.com: ported rkw's proposal to 2.6.37-rc2]
>> Signed-off-by: Nishanth Menon <nm@ti.com>
>> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
>> ---
>> (no change in this series, posted for completeness)
>> v2: https://patchwork.kernel.org/patch/365222/
>> v1: http://marc.info/?l=linux-omap&m=129013171325210&w=2
>> ?arch/arm/mach-omap2/sleep34xx.S | ? 79
> ++++++----------------------------
>> ----
>> ?1 files changed, 13 insertions(+), 66 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
>> omap2/sleep34xx.S
>> index 2fb205a..2c20fcf 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -520,72 +520,17 @@ clean_caches:
>> ? ? ? cmp ? ? r9, #1 /* Check whether L2 inval is required or not*/
>> ? ? ? bne ? ? skip_l2_inval
>> ?clean_l2:
>> - ? ? /* read clidr */
>> - ? ? mrc ? ? p15, 1, r0, c0, c0, 1
>> - ? ? /* extract loc from clidr */
>> - ? ? ands ? ?r3, r0, #0x7000000
>> - ? ? /* left align loc bit field */
>> - ? ? mov ? ? r3, r3, lsr #23
>> - ? ? /* if loc is 0, then no need to clean */
>> - ? ? beq ? ? finished
>> - ? ? /* start clean at cache level 0 */
>> - ? ? mov ? ? r10, #0
>> -loop1:
>> - ? ? /* work out 3x current cache level */
>> - ? ? add ? ? r2, r10, r10, lsr #1
>> - ? ? /* extract cache type bits from clidr*/
>> - ? ? mov ? ? r1, r0, lsr r2
>> - ? ? /* mask of the bits for current cache only */
>> - ? ? and ? ? r1, r1, #7
>> - ? ? /* see what cache we have at this level */
>> - ? ? cmp ? ? r1, #2
>> - ? ? /* skip if no cache, or just i-cache */
>> - ? ? blt ? ? skip
>> - ? ? /* select current cache level in cssr */
>> - ? ? mcr ? ? p15, 2, r10, c0, c0, 0
>> - ? ? /* isb to sych the new cssr&csidr */
>> - ? ? isb
>> - ? ? /* read the new csidr */
>> - ? ? mrc ? ? p15, 1, r1, c0, c0, 0
>> - ? ? /* extract the length of the cache lines */
>> - ? ? and ? ? r2, r1, #7
>> - ? ? /* add 4 (line length offset) */
>> - ? ? add ? ? r2, r2, #4
>> - ? ? ldr ? ? r4, assoc_mask
>> - ? ? /* find maximum number on the way size */
>> - ? ? ands ? ?r4, r4, r1, lsr #3
>> - ? ? /* find bit position of way size increment */
>> - ? ? clz ? ? r5, r4
>> - ? ? ldr ? ? r7, numset_mask
>> - ? ? /* extract max number of the index size*/
>> - ? ? ands ? ?r7, r7, r1, lsr #13
>> -loop2:
>> - ? ? mov ? ? r9, r4
>> - ? ? /* create working copy of max way size*/
>> -loop3:
>> - ? ? /* factor way and cache number into r11 */
>> - ? ? orr ? ? r11, r10, r9, lsl r5
>> - ? ? /* factor index number into r11 */
>> - ? ? orr ? ? r11, r11, r7, lsl r2
>> - ? ? /*clean & invalidate by set/way */
>> - ? ? mcr ? ? p15, 0, r11, c7, c10, 2
>> - ? ? /* decrement the way*/
>> - ? ? subs ? ?r9, r9, #1
>> - ? ? bge ? ? loop3
>> - ? ? /*decrement the index */
>> - ? ? subs ? ?r7, r7, #1
>> - ? ? bge ? ? loop2
>> -skip:
>> - ? ? add ? ? r10, r10, #2
>> - ? ? /* increment cache number */
>> - ? ? cmp ? ? r3, r10
>> - ? ? bgt ? ? loop1
>> -finished:
>> - ? ? /*swith back to cache level 0 */
>> - ? ? mov ? ? r10, #0
>> - ? ? /* select current cache level in cssr */
>> - ? ? mcr ? ? p15, 2, r10, c0, c0, 0
>> - ? ? isb
>> + ? ? /*
>> + ? ? ?* Jump out to kernel flush routine
>> + ? ? ?* ?- reuse that code is better
>> + ? ? ?* ?- it executes in a cached space so is faster than refetch per-
>> block
>> + ? ? ?* ?- should be faster and will change with kernel
>> + ? ? ?* ?- 'might' have to copy address, load and jump to it
> Would be good to clarify that this is needed to maintain the 'lr'
> when code is executed from SRAM
>
Agree on that. Some comments have been posted at
http://marc.info/?l=linux-omap&m=129016170719489&w=2.
>> + ? ? ?*/
>> + ? ? ldr r1, kernel_flush
>> + ? ? mov lr, pc
>> + ? ? bx ?r1
>> +
>> ?skip_l2_inval:
>> ? ? ? /* Data memory barrier and Data sync barrier */
>> ? ? ? mov ? ? r1, #0
>> @@ -668,5 +613,7 @@ cache_pred_disable_mask:
>> ? ? ? .word ? 0xFFFFE7FB
>> ?control_stat:
>> ? ? ? .word ? CONTROL_STAT
>> +kernel_flush:
>> + ? ? .word v7_flush_dcache_all
>> ?ENTRY(omap34xx_cpu_suspend_sz)
>> ? ? ? .word ? . - omap34xx_cpu_suspend
>
> O.w
> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
>
>> --
>> 1.6.3.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
Jean
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 10:23 ` Jean Pihet
-1 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:23 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Kevin, Tony
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>
> Erratum i581 impacts OMAP3 platforms.
> PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing
> the DPLL not to be locked at times.
>
> IMPORTANT:
> *) This is not a complete workaround implementation as recommended
> by the silicon erratum. this is a support logic for detecting lockups and
> attempting to recover where possible and is known to provide stability
> in multiple platforms.
> *) This code is mostly important for inactive and retention. The ROM code
> waits for the maximum dll lock time when resuming from off mode. So for
> off mode this code isn't really needed.
>
> This should eventually get refactored as part of cleanups to sleep34xx.S
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> ---
> (no change done, posting for completeness of the series)
> v2: https://patchwork.kernel.org/patch/365252/
> typo correction- erratum, support, added comment from Peter from the
> thread to commit message
> v1: http://marc.info/?l=linux-omap&m=129013172525234&w=2
> arch/arm/mach-omap2/sleep34xx.S | 52 +++++++++++++++++++++++++++++++++++---
> 1 files changed, 47 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 2c20fcf..3fbd1e5 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -42,6 +42,7 @@
> OMAP3430_PM_PREPWSTST)
> #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
> #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
> +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
> #define SRAM_BASE_P 0x40200000
> #define CONTROL_STAT 0x480022F0
> #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
> @@ -554,31 +555,67 @@ skip_l2_inval:
>
> /* Make sure SDRC accesses are ok */
> wait_sdrc_ok:
> +
> +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */
> + ldr r4, cm_idlest_ckgen
> +wait_dpll3_lock:
> + ldr r5, [r4]
> + tst r5, #1
> + beq wait_dpll3_lock
> +
> ldr r4, cm_idlest1_core
> +wait_sdrc_ready:
> ldr r5, [r4]
> - and r5, r5, #0x2
> - cmp r5, #0
> - bne wait_sdrc_ok
> + tst r5, #0x2
> + bne wait_sdrc_ready
> + /* allow DLL powerdown upon hw idle req */
> ldr r4, sdrc_power
> ldr r5, [r4]
> bic r5, r5, #0x40
> str r5, [r4]
> -wait_dll_lock:
> +is_dll_in_lock_mode:
> +
> /* Is dll in lock mode? */
> ldr r4, sdrc_dlla_ctrl
> ldr r5, [r4]
> tst r5, #0x4
> bxne lr
> /* wait till dll locks */
> - ldr r4, sdrc_dlla_status
> +wait_dll_lock_timed:
> + ldr r4, wait_dll_lock_counter
> + add r4, r4, #1
> + str r4, wait_dll_lock_counter
> + ldr r4, sdrc_dlla_status
> + mov r6, #8 /* Wait 20uS for lock */
> +wait_dll_lock:
> + subs r6, r6, #0x1
> + beq kick_dll
It would be good to have more comments on the code flow here:
- what are wait_dll_lock_counter and kick_counter used for?
- what is the timing based on? Why 20uS for the wait time?
- jumping back and forth to kick_dll and wait_dll_lock_timed is confusing.
> ldr r5, [r4]
> and r5, r5, #0x4
> cmp r5, #0x4
> bne wait_dll_lock
> bx lr
>
> + /* disable/reenable DLL if not locked */
> +kick_dll:
> + ldr r4, sdrc_dlla_ctrl
> + ldr r5, [r4]
> + mov r6, r5
> + bic r6, #(1<<3) /* disable dll */
> + str r6, [r4]
> + dsb
> + orr r6, r6, #(1<<3) /* enable dll */
> + str r6, [r4]
> + dsb
> + ldr r4, kick_counter
> + add r4, r4, #1
> + str r4, kick_counter
> + b wait_dll_lock_timed
> +
> cm_idlest1_core:
> .word CM_IDLEST1_CORE_V
> +cm_idlest_ckgen:
> + .word CM_IDLEST_CKGEN_V
> sdrc_dlla_status:
> .word SDRC_DLLA_STATUS_V
> sdrc_dlla_ctrl:
> @@ -615,5 +652,10 @@ control_stat:
> .word CONTROL_STAT
> kernel_flush:
> .word v7_flush_dcache_all
> + /* these 2 words need to be at the end !!! */
> +kick_counter:
> + .word 0
> +wait_dll_lock_counter:
> + .word 0
Why do they need to be at the end? Also, at the end of what do they need to be?
> ENTRY(omap34xx_cpu_suspend_sz)
> .word . - omap34xx_cpu_suspend
> --
> 1.6.3.3
>
>
Regards,
Jean
--
To unsubscribe from this list: send the line "unsubscribe linux-omap" in
the body of a message to majordomo@vger.kernel.org
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
@ 2010-12-20 10:23 ` Jean Pihet
0 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:23 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>
> Erratum i581 impacts OMAP3 platforms.
> PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing
> the DPLL not to be locked at times.
>
> IMPORTANT:
> *) This is not a complete workaround implementation as recommended
> by the silicon erratum. this is a support logic for detecting lockups and
> attempting to recover where possible and is known to provide stability
> in multiple platforms.
> *) This code is mostly important for inactive and retention. The ROM code
> waits for the maximum dll lock time when resuming from off mode. So for
> off mode this code isn't really needed.
>
> This should eventually get refactored as part of cleanups to sleep34xx.S
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> ---
> (no change done, posting for completeness of the series)
> v2: https://patchwork.kernel.org/patch/365252/
> ? ? ? ?typo correction- erratum, support, added comment from Peter from the
> ? ? ? ?thread to commit message
> v1: http://marc.info/?l=linux-omap&m=129013172525234&w=2
> ?arch/arm/mach-omap2/sleep34xx.S | ? 52 +++++++++++++++++++++++++++++++++++---
> ?1 files changed, 47 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 2c20fcf..3fbd1e5 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -42,6 +42,7 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?OMAP3430_PM_PREPWSTST)
> ?#define PM_PWSTCTRL_MPU_P ? ? ?OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
> ?#define CM_IDLEST1_CORE_V ? ? ?OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
> +#define CM_IDLEST_CKGEN_V ? ? ?OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
> ?#define SRAM_BASE_P ? ? ? ? ? ?0x40200000
> ?#define CONTROL_STAT ? ? ? ? ? 0x480022F0
> ?#define SCRATCHPAD_MEM_OFFS ? ?0x310 /* Move this as correct place is
> @@ -554,31 +555,67 @@ skip_l2_inval:
>
> ?/* Make sure SDRC accesses are ok */
> ?wait_sdrc_ok:
> +
> +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */
> + ? ? ? ldr ? ? r4, cm_idlest_ckgen
> +wait_dpll3_lock:
> + ? ? ? ldr ? ? r5, [r4]
> + ? ? ? tst ? ? r5, #1
> + ? ? ? beq ? ? wait_dpll3_lock
> +
> ? ? ? ? ldr ? ? r4, cm_idlest1_core
> +wait_sdrc_ready:
> ? ? ? ? ldr ? ? r5, [r4]
> - ? ? ? ?and ? ? r5, r5, #0x2
> - ? ? ? ?cmp ? ? r5, #0
> - ? ? ? ?bne ? ? wait_sdrc_ok
> + ? ? ? ?tst ? ? r5, #0x2
> + ? ? ? ?bne ? ? wait_sdrc_ready
> + ? ? ? /* allow DLL powerdown upon hw idle req */
> ? ? ? ? ldr ? ? r4, sdrc_power
> ? ? ? ? ldr ? ? r5, [r4]
> ? ? ? ? bic ? ? r5, r5, #0x40
> ? ? ? ? str ? ? r5, [r4]
> -wait_dll_lock:
> +is_dll_in_lock_mode:
> +
> ? ? ? ? /* Is dll in lock mode? */
> ? ? ? ? ldr ? ? r4, sdrc_dlla_ctrl
> ? ? ? ? ldr ? ? r5, [r4]
> ? ? ? ? tst ? ? r5, #0x4
> ? ? ? ? bxne ? ?lr
> ? ? ? ? /* wait till dll locks */
> - ? ? ? ?ldr ? ? r4, sdrc_dlla_status
> +wait_dll_lock_timed:
> + ? ? ? ldr ? ? r4, wait_dll_lock_counter
> + ? ? ? add ? ? r4, r4, #1
> + ? ? ? str ? ? r4, wait_dll_lock_counter
> + ? ? ? ldr ? ? r4, sdrc_dlla_status
> + ? ? ? ?mov ? ?r6, #8 ? ? ? ? ?/* Wait 20uS for lock */
> +wait_dll_lock:
> + ? ? ? subs ? ?r6, r6, #0x1
> + ? ? ? beq ? ? kick_dll
It would be good to have more comments on the code flow here:
- what are wait_dll_lock_counter and kick_counter used for?
- what is the timing based on? Why 20uS for the wait time?
- jumping back and forth to kick_dll and wait_dll_lock_timed is confusing.
> ? ? ? ? ldr ? ? r5, [r4]
> ? ? ? ? and ? ? r5, r5, #0x4
> ? ? ? ? cmp ? ? r5, #0x4
> ? ? ? ? bne ? ? wait_dll_lock
> ? ? ? ? bx ? ? ?lr
>
> + ? ? ? /* disable/reenable DLL if not locked */
> +kick_dll:
> + ? ? ? ldr ? ? r4, sdrc_dlla_ctrl
> + ? ? ? ldr ? ? r5, [r4]
> + ? ? ? mov ? ? r6, r5
> + ? ? ? bic ? ? r6, #(1<<3) ? ? /* disable dll */
> + ? ? ? str ? ? r6, [r4]
> + ? ? ? dsb
> + ? ? ? orr ? ? r6, r6, #(1<<3) /* enable dll */
> + ? ? ? str ? ? r6, [r4]
> + ? ? ? dsb
> + ? ? ? ldr ? ? r4, kick_counter
> + ? ? ? add ? ? r4, r4, #1
> + ? ? ? str ? ? r4, kick_counter
> + ? ? ? b ? ? ? wait_dll_lock_timed
> +
> ?cm_idlest1_core:
> ? ? ? ?.word ? CM_IDLEST1_CORE_V
> +cm_idlest_ckgen:
> + ? ? ? .word ? CM_IDLEST_CKGEN_V
> ?sdrc_dlla_status:
> ? ? ? ?.word ? SDRC_DLLA_STATUS_V
> ?sdrc_dlla_ctrl:
> @@ -615,5 +652,10 @@ control_stat:
> ? ? ? ?.word ? CONTROL_STAT
> ?kernel_flush:
> ? ? ? ?.word v7_flush_dcache_all
> + ? ? ? /* these 2 words need to be at the end !!! */
> +kick_counter:
> + ? ? ? .word ? 0
> +wait_dll_lock_counter:
> + ? ? ? .word ? 0
Why do they need to be at the end? Also, at the end of what do they need to be?
> ?ENTRY(omap34xx_cpu_suspend_sz)
> ? ? ? ?.word ? . - omap34xx_cpu_suspend
> --
> 1.6.3.3
>
>
Regards,
Jean
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
2010-12-20 6:51 ` Santosh Shilimkar
@ 2010-12-20 10:26 ` Jean Pihet
-1 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:26 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: Nishanth Menon, linux-omap, linux-arm, Kevin, Tony
On Mon, Dec 20, 2010 at 7:51 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: linux-omap-owner@vger.kernel.org [mailto:linux-omap-
>> owner@vger.kernel.org] On Behalf Of Nishanth Menon
>> Sent: Sunday, December 19, 2010 4:24 AM
>> To: linux-omap; linux-arm
>> Cc: Jean Pihet; Kevin; Tony
>> Subject: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if <
>> ES1.2
>>
>> From: Eduardo Valentin <eduardo.valentin@nokia.com>
>>
>> Limitation i583: Self_Refresh Exit issue after OFF mode
>>
>> Issue:
>> When device is waking up from OFF mode, then SDRC state machine sends
>> inappropriate sequence violating JEDEC standards.
>>
>> Impact:
>> OMAP3630 < ES1.2 is impacted as follows depending on the platform:
>> CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable,
> while
>> for all other sysclk frequencies, varied levels of instability
>> seen based on varied parameters.
>> CS1: impacted
>>
>> This patch takes option #3 as recommended by the Silicon erratum:
>> Avoid core power domain transitioning to OFF mode. Power consumption
>> impact is expected in this case.
>> To do this, we route core OFF requests to RET request on the impacted
>> revisions of silicon.
>>
>> [nm@ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a
>> bit]
>> Signed-off-by: Nishanth Menon <nm@ti.com>
>> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
>> ---
>> v4: idle state control changed a bit -we wont register or enable
>> the states which cannot be enabled.
>> v3: http://marc.info/?t=129140247800027&r=1&w=2
>> no functional change in erratum wa implementation, just registration
>> of
>> erratum is collated to a single cpu detection and version check
>> v2: https://patchwork.kernel.org/patch/365262/
>> rebased to this patch series instead of depending on hs changes
>> fix typo for macro definition
>> v1: http://marc.info/?l=linux-omap&m=129013173425266&w=2
>> arch/arm/mach-omap2/cpuidle34xx.c | 10 ++++++++++
>> arch/arm/mach-omap2/pm.h | 1 +
>> arch/arm/mach-omap2/pm34xx.c | 24 +++++++++++++++++++++---
>> 3 files changed, 32 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-
>> omap2/cpuidle34xx.c
>> index f80d3f6..1b32e98 100644
>> --- a/arch/arm/mach-omap2/cpuidle34xx.c
>> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
>> @@ -453,6 +453,16 @@ void omap_init_power_states(void)
>> omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
>> omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID
> |
>> CPUIDLE_FLAG_CHECK_BM;
>> +
>> + /*
>> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We
>> cannot
>> + * enable OFF mode in a stable form for previous revisions.
>> + * we disable C7 state as a result.
>> + */
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
>> + omap3_power_states[OMAP3_STATE_C7].valid = 0;
>> + cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
> WARN_ONCE in IDLE also would be good.
Agree on the WARN_ONCE remarks.
Other than that:
Acked-by: Jean Pihet <j-pihet@ti.com>
>> + }
>> }
>>
>> struct cpuidle_driver omap3_idle_driver = {
>> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
>> index 92ef400..9032d09 100644
>> --- a/arch/arm/mach-omap2/pm.h
>> +++ b/arch/arm/mach-omap2/pm.h
>> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
>> extern unsigned int omap34xx_cpu_suspend_sz;
>>
>> #define PM_RTA_ERRATUM_i608 (1 << 0)
>> +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
>>
>> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
>> extern u16 pm34xx_errata;
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index 21cd36e..7faea55 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
>> state = PWRDM_POWER_RET;
>>
>> #ifdef CONFIG_CPU_IDLE
>> - omap3_cpuidle_update_states(state, state);
>> + /*
>> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We
>> cannot
>> + * enable OFF mode in a stable form for previous revisions,
> restrict
>> + * instead to RET
>> + */
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
>> + omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
>> + else
>> + omap3_cpuidle_update_states(state, state);
>> #endif
>>
>> list_for_each_entry(pwrst, &pwrst_list, node) {
>> - pwrst->next_state = state;
>> - omap_set_pwrdm_state(pwrst->pwrdm, state);
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
>> + pwrst->pwrdm == core_pwrdm &&
>> + state == PWRDM_POWER_OFF) {
>> + pwrst->next_state = PWRDM_POWER_RET;
>> + pr_err("%s: Core OFF disabled due to errata
> i583\n",
> Shoud we do this in every iteration or just WARN_ONCE do ??
>> + __func__);
>> + } else {
>> + pwrst->next_state = state;
>> + }
>> + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
>> }
>> }
>>
>> @@ -1011,6 +1027,8 @@ static void __init pm_errata_configure(void)
>> pm34xx_errata |= PM_RTA_ERRATUM_i608;
>> /* Enable the l2 cache toggling in sleep logic */
>> enable_omap3630_toggle_l2_on_restore();
>> + if (omap_rev() < OMAP3630_REV_ES1_2)
>> + pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
>> }
>> }
>>
>> --
>> 1.6.3.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
--
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
@ 2010-12-20 10:26 ` Jean Pihet
0 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:26 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Dec 20, 2010 at 7:51 AM, Santosh Shilimkar
<santosh.shilimkar@ti.com> wrote:
>> -----Original Message-----
>> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
>> owner at vger.kernel.org] On Behalf Of Nishanth Menon
>> Sent: Sunday, December 19, 2010 4:24 AM
>> To: linux-omap; linux-arm
>> Cc: Jean Pihet; Kevin; Tony
>> Subject: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if <
>> ES1.2
>>
>> From: Eduardo Valentin <eduardo.valentin@nokia.com>
>>
>> Limitation i583: Self_Refresh Exit issue after OFF mode
>>
>> Issue:
>> When device is waking up from OFF mode, then SDRC state machine sends
>> inappropriate sequence violating JEDEC standards.
>>
>> Impact:
>> OMAP3630 < ES1.2 is impacted as follows depending on the platform:
>> CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable,
> while
>> ? ? ? for all other sysclk frequencies, varied levels of instability
>> ? ? ? seen based on varied parameters.
>> CS1: impacted
>>
>> This patch takes option #3 as recommended by the Silicon erratum:
>> Avoid core power domain transitioning to OFF mode. Power consumption
>> impact is expected in this case.
>> To do this, we route core OFF requests to RET request on the impacted
>> revisions of silicon.
>>
>> [nm at ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a
>> bit]
>> Signed-off-by: Nishanth Menon <nm@ti.com>
>> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
>> ---
>> v4: idle state control changed a bit -we wont register or enable
>> ? ? the states which cannot be enabled.
>> v3: http://marc.info/?t=129140247800027&r=1&w=2
>> ? ? no functional change in erratum wa implementation, just registration
>> of
>> ? ? ? erratum is collated to a single cpu detection and version check
>> v2: https://patchwork.kernel.org/patch/365262/
>> ? ? rebased to this patch series instead of depending on hs changes
>> ? ? fix typo for macro definition
>> v1: http://marc.info/?l=linux-omap&m=129013173425266&w=2
>> ?arch/arm/mach-omap2/cpuidle34xx.c | ? 10 ++++++++++
>> ?arch/arm/mach-omap2/pm.h ? ? ? ? ?| ? ?1 +
>> ?arch/arm/mach-omap2/pm34xx.c ? ? ?| ? 24 +++++++++++++++++++++---
>> ?3 files changed, 32 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-
>> omap2/cpuidle34xx.c
>> index f80d3f6..1b32e98 100644
>> --- a/arch/arm/mach-omap2/cpuidle34xx.c
>> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
>> @@ -453,6 +453,16 @@ void omap_init_power_states(void)
>> ? ? ? omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
>> ? ? ? omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID
> |
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CPUIDLE_FLAG_CHECK_BM;
>> +
>> + ? ? /*
>> + ? ? ?* Erratum i583: implementation for ES rev < Es1.2 on 3630. We
>> cannot
>> + ? ? ?* enable OFF mode in a stable form for previous revisions.
>> + ? ? ?* we disable C7 state as a result.
>> + ? ? ?*/
>> + ? ? if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
>> + ? ? ? ? ? ? omap3_power_states[OMAP3_STATE_C7].valid = 0;
>> + ? ? ? ? ? ? cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
> WARN_ONCE in IDLE also would be good.
Agree on the WARN_ONCE remarks.
Other than that:
Acked-by: Jean Pihet <j-pihet@ti.com>
>> + ? ? }
>> ?}
>>
>> ?struct cpuidle_driver omap3_idle_driver = {
>> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
>> index 92ef400..9032d09 100644
>> --- a/arch/arm/mach-omap2/pm.h
>> +++ b/arch/arm/mach-omap2/pm.h
>> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
>> ?extern unsigned int omap34xx_cpu_suspend_sz;
>>
>> ?#define PM_RTA_ERRATUM_i608 ? ? ? ? ?(1 << 0)
>> +#define PM_SDRC_WAKEUP_ERRATUM_i583 ?(1 << 1)
>>
>> ?#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
>> ?extern u16 pm34xx_errata;
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index 21cd36e..7faea55 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
>> ? ? ? ? ? ? ? state = PWRDM_POWER_RET;
>>
>> ?#ifdef CONFIG_CPU_IDLE
>> - ? ? omap3_cpuidle_update_states(state, state);
>> + ? ? /*
>> + ? ? ?* Erratum i583: implementation for ES rev < Es1.2 on 3630. We
>> cannot
>> + ? ? ?* enable OFF mode in a stable form for previous revisions,
> restrict
>> + ? ? ?* instead to RET
>> + ? ? ?*/
>> + ? ? if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
>> + ? ? ? ? ? ? omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
>> + ? ? else
>> + ? ? ? ? ? ? omap3_cpuidle_update_states(state, state);
>> ?#endif
>>
>> ? ? ? list_for_each_entry(pwrst, &pwrst_list, node) {
>> - ? ? ? ? ? ? pwrst->next_state = state;
>> - ? ? ? ? ? ? omap_set_pwrdm_state(pwrst->pwrdm, state);
>> + ? ? ? ? ? ? if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? pwrst->pwrdm == core_pwrdm &&
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? state == PWRDM_POWER_OFF) {
>> + ? ? ? ? ? ? ? ? ? ? pwrst->next_state = PWRDM_POWER_RET;
>> + ? ? ? ? ? ? ? ? ? ? pr_err("%s: Core OFF disabled due to errata
> i583\n",
> Shoud we do this in every iteration or just WARN_ONCE do ??
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? __func__);
>> + ? ? ? ? ? ? } else {
>> + ? ? ? ? ? ? ? ? ? ? pwrst->next_state = state;
>> + ? ? ? ? ? ? }
>> + ? ? ? ? ? ? omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
>> ? ? ? }
>> ?}
>>
>> @@ -1011,6 +1027,8 @@ static void __init pm_errata_configure(void)
>> ? ? ? ? ? ? ? pm34xx_errata |= PM_RTA_ERRATUM_i608;
>> ? ? ? ? ? ? ? /* Enable the l2 cache toggling in sleep logic */
>> ? ? ? ? ? ? ? enable_omap3630_toggle_l2_on_restore();
>> + ? ? ? ? ? ? if (omap_rev() < OMAP3630_REV_ES1_2)
>> + ? ? ? ? ? ? ? ? ? ? pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
>> ? ? ? }
>> ?}
>>
>> --
>> 1.6.3.3
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 10:27 ` Jean Pihet
-1 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:27 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Kevin, Tony
Nishant,
Here are minor remarks about comments formatting.
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> Erratum id: i608
> RTA (Retention Till Access) feature is not supported and leads to device
> stability issues when enabled. This impacts modules with embedded memories
> on OMAP3630
>
> Workaround is to disable RTA on boot and coming out of core off.
> For disabling rta coming out of off mode, we do this by overriding the
Use caps for RTA
> restore pointer for 3630 to allow us restore handler as the first point of
This is not clear, maybe 'to allow us to restore handler' needs to be removed.
> entry before caches are touched and is common for GP and HS devices.
> to disable earlier than this could be possible by modifying the ppa for HS
Same here, it looks like the original sentence has been cut in pieces.
Use caps for PPA.
> devices, but not for GP devices.
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [ambresh@ti.com: co-developer]
> Signed-off-by: Ambresh K <ambresh@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
Otherwise:
Acked-by: Jean Pihet <j-pihet@ti.com>
> ---
> v4:
> control register handling moved to control.c
> errata handling framework introduction split out
> into a separate patch
> v3: http://marc.info/?t=129140247800026&r=1&w=2
> additional comment to explain Ambresh's contrib
> removed the redundant check for cpu_is34xx - it is already
> done by pm_init
> pm_errata_configure is __init
> v2: https://patchwork.kernel.org/patch/365242/
> fixed missing b restore for 3430 es3.1 code.
> introduced erratum handling logic here splitting it out of uart errata
> typo fixes for erratum
> v1: http://marc.info/?l=linux-omap&m=129013172825240&w=2
>
> arch/arm/mach-omap2/control.c | 13 ++++++++++++-
> arch/arm/mach-omap2/control.h | 7 ++++++-
> arch/arm/mach-omap2/pm.h | 2 ++
> arch/arm/mach-omap2/pm34xx.c | 10 ++++++++++
> arch/arm/mach-omap2/sleep34xx.S | 26 ++++++++++++++++++++++++++
> 5 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index 1fa3294..27ed558 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
>
> /* Populate the Scratchpad contents */
> scratchpad_contents.boot_config_ptr = 0x0;
> - if (omap_rev() != OMAP3430_REV_ES3_0 &&
> + if (cpu_is_omap3630())
> + scratchpad_contents.public_restore_ptr =
> + virt_to_phys(get_omap3630_restore_pointer());
> + else if (omap_rev() != OMAP3430_REV_ES3_0 &&
> omap_rev() != OMAP3430_REV_ES3_1)
> scratchpad_contents.public_restore_ptr =
> virt_to_phys(get_restore_pointer());
> @@ -474,4 +477,12 @@ void omap3_control_restore_context(void)
> omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
> return;
> }
> +
> +void omap3630_ctrl_disable_rta(void)
> +{
> + if (!cpu_is_omap3630())
> + return;
> + omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
> +}
> +
> #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index b6c6b7c..ec98dd7 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -204,6 +204,10 @@
> #define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
> #define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
>
> +/* 36xx-only RTA - Retention till Accesss control registers and bits */
> +#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
> +#define OMAP36XX_RTA_DISABLE 0x0
> +
> /* 34xx D2D idle-related pins, handled by PM core */
> #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
> #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
> @@ -347,10 +351,11 @@ extern void omap3_save_scratchpad_contents(void);
> extern void omap3_clear_scratchpad_contents(void);
> extern u32 *get_restore_pointer(void);
> extern u32 *get_es3_restore_pointer(void);
> +extern u32 *get_omap3630_restore_pointer(void);
> extern u32 omap3_arm_context[128];
> extern void omap3_control_save_context(void);
> extern void omap3_control_restore_context(void);
> -
> +extern void omap3630_ctrl_disable_rta(void);
> #else
> #define omap_ctrl_base_get() 0
> #define omap_ctrl_readb(x) 0
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 0348fd7..8d9aa3e 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -85,6 +85,8 @@ extern unsigned int save_secure_ram_context_sz;
> extern unsigned int omap24xx_cpu_suspend_sz;
> extern unsigned int omap34xx_cpu_suspend_sz;
>
> +#define PM_RTA_ERRATUM_i608 (1 << 0)
> +
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 5702f41..b32a2ed 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -1007,6 +1007,8 @@ void omap_push_sram_idle(void)
>
> static void __init pm_errata_configure(void)
> {
> + if (cpu_is_omap3630())
> + pm34xx_errata |= PM_RTA_ERRATUM_i608;
> }
>
> static int __init omap3_pm_init(void)
> @@ -1067,6 +1069,14 @@ static int __init omap3_pm_init(void)
> pm_idle = omap3_pm_idle;
> omap3_idle_init();
>
> + /*
> + * RTA is disabled during initialization as per erratum i608
> + * it is safer to disable rta by the bootloader, but we would like
Use caps for RTA
> + * to be doubly sure here and prevent any mishaps.
> + */
> + if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
> + omap3630_ctrl_disable_rta();
> +
> clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
> if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
> omap3_secure_ram_storage =
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 3fbd1e5..cc3507b 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -45,6 +45,8 @@
> #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
> #define SRAM_BASE_P 0x40200000
> #define CONTROL_STAT 0x480022F0
> +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
> + + OMAP36XX_CONTROL_MEM_RTA_CTRL)
> #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
> * available */
> #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
> @@ -99,6 +101,14 @@ ENTRY(get_restore_pointer)
> ldmfd sp!, {pc} @ restore regs and return
> ENTRY(get_restore_pointer_sz)
> .word . - get_restore_pointer
> + .text
> +/* Function call to get the restore pointer for 3630 resume from OFF */
> +ENTRY(get_omap3630_restore_pointer)
> + stmfd sp!, {lr} @ save registers on stack
> + adr r0, restore_3630
> + ldmfd sp!, {pc} @ restore regs and return
> +ENTRY(get_omap3630_restore_pointer_sz)
> + .word . - get_omap3630_restore_pointer
>
> .text
> /* Function call to get the restore pointer for for ES3 to resume from OFF */
> @@ -246,6 +256,20 @@ copy_to_sram:
> bne copy_to_sram
> ldr r1, sram_base
> blx r1
> + b restore
> +
> +restore_3630:
> + /*b restore_es3630*/ @ Enable to debug restore code
> + ldr r1, pm_prepwstst_core_p
> + ldr r2, [r1]
> + and r2, r2, #0x3
> + cmp r2, #0x0 @ Check if previous power state of CORE is OFF
> + bne restore
> + /* Disable rta before giving control */
Use caps for RTA
> + ldr r1, control_mem_rta
> + mov r2, #OMAP36XX_RTA_DISABLE
> + str r2, [r1]
> + /* Fall thru for the remaining logic */
> restore:
> /* b restore*/ @ Enable to debug restore code
> /* Check what was the reason for mpu reset and store the reason in r9*/
> @@ -650,6 +674,8 @@ cache_pred_disable_mask:
> .word 0xFFFFE7FB
> control_stat:
> .word CONTROL_STAT
> +control_mem_rta:
> + .word CONTROL_MEM_RTA_CTRL
> kernel_flush:
> .word v7_flush_dcache_all
> /* these 2 words need to be at the end !!! */
> --
> 1.6.3.3
>
>
--
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
@ 2010-12-20 10:27 ` Jean Pihet
0 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:27 UTC (permalink / raw)
To: linux-arm-kernel
Nishant,
Here are minor remarks about comments formatting.
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> Erratum id: i608
> RTA (Retention Till Access) feature is not supported and leads to device
> stability issues when enabled. This impacts modules with embedded memories
> on OMAP3630
>
> Workaround is to disable RTA on boot and coming out of core off.
> For disabling rta coming out of off mode, we do this by overriding the
Use caps for RTA
> restore pointer for 3630 to allow us restore handler as the first point of
This is not clear, maybe 'to allow us to restore handler' needs to be removed.
> entry before caches are touched and is common for GP and HS devices.
> to disable earlier than this could be possible by modifying the ppa for HS
Same here, it looks like the original sentence has been cut in pieces.
Use caps for PPA.
> devices, but not for GP devices.
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [ambresh at ti.com: co-developer]
> Signed-off-by: Ambresh K <ambresh@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
Otherwise:
Acked-by: Jean Pihet <j-pihet@ti.com>
> ---
> v4:
> ? ? ? ?control register handling moved to control.c
> ? ? ? ?errata handling framework introduction split out
> ? ? ? ?into a separate patch
> v3: http://marc.info/?t=129140247800026&r=1&w=2
> ? ? ? ?additional comment to explain Ambresh's contrib
> ? ? ? ?removed the redundant check for cpu_is34xx - it is already
> ? ? ? ? ? ? ? ?done by pm_init
> ? ? ? ?pm_errata_configure is __init
> v2: https://patchwork.kernel.org/patch/365242/
> ? ? ? ?fixed missing b restore for 3430 es3.1 code.
> ? ? ? ?introduced erratum handling logic here splitting it out of uart errata
> ? ? ? ?typo fixes for erratum
> v1: http://marc.info/?l=linux-omap&m=129013172825240&w=2
>
> ?arch/arm/mach-omap2/control.c ? | ? 13 ++++++++++++-
> ?arch/arm/mach-omap2/control.h ? | ? ?7 ++++++-
> ?arch/arm/mach-omap2/pm.h ? ? ? ?| ? ?2 ++
> ?arch/arm/mach-omap2/pm34xx.c ? ?| ? 10 ++++++++++
> ?arch/arm/mach-omap2/sleep34xx.S | ? 26 ++++++++++++++++++++++++++
> ?5 files changed, 56 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
> index 1fa3294..27ed558 100644
> --- a/arch/arm/mach-omap2/control.c
> +++ b/arch/arm/mach-omap2/control.c
> @@ -241,7 +241,10 @@ void omap3_save_scratchpad_contents(void)
>
> ? ? ? ?/* Populate the Scratchpad contents */
> ? ? ? ?scratchpad_contents.boot_config_ptr = 0x0;
> - ? ? ? if (omap_rev() != OMAP3430_REV_ES3_0 &&
> + ? ? ? if (cpu_is_omap3630())
> + ? ? ? ? ? ? ? scratchpad_contents.public_restore_ptr =
> + ? ? ? ? ? ? ? ? ? ? ? virt_to_phys(get_omap3630_restore_pointer());
> + ? ? ? else if (omap_rev() != OMAP3430_REV_ES3_0 &&
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?omap_rev() != OMAP3430_REV_ES3_1)
> ? ? ? ? ? ? ? ?scratchpad_contents.public_restore_ptr =
> ? ? ? ? ? ? ? ? ? ? ? ?virt_to_phys(get_restore_pointer());
> @@ -474,4 +477,12 @@ void omap3_control_restore_context(void)
> ? ? ? ?omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
> ? ? ? ?return;
> ?}
> +
> +void omap3630_ctrl_disable_rta(void)
> +{
> + ? ? ? if (!cpu_is_omap3630())
> + ? ? ? ? ? ? ? return;
> + ? ? ? omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
> +}
> +
> ?#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
> diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
> index b6c6b7c..ec98dd7 100644
> --- a/arch/arm/mach-omap2/control.h
> +++ b/arch/arm/mach-omap2/control.h
> @@ -204,6 +204,10 @@
> ?#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
> ?#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
>
> +/* 36xx-only RTA - Retention till Accesss control registers and bits */
> +#define OMAP36XX_CONTROL_MEM_RTA_CTRL ?0x40C
> +#define OMAP36XX_RTA_DISABLE ? ? ? ? ? 0x0
> +
> ?/* 34xx D2D idle-related pins, handled by PM core */
> ?#define OMAP3_PADCONF_SAD2D_MSTANDBY ? 0x250
> ?#define OMAP3_PADCONF_SAD2D_IDLEACK ? ?0x254
> @@ -347,10 +351,11 @@ extern void omap3_save_scratchpad_contents(void);
> ?extern void omap3_clear_scratchpad_contents(void);
> ?extern u32 *get_restore_pointer(void);
> ?extern u32 *get_es3_restore_pointer(void);
> +extern u32 *get_omap3630_restore_pointer(void);
> ?extern u32 omap3_arm_context[128];
> ?extern void omap3_control_save_context(void);
> ?extern void omap3_control_restore_context(void);
> -
> +extern void omap3630_ctrl_disable_rta(void);
> ?#else
> ?#define omap_ctrl_base_get() ? ? ? ? ? 0
> ?#define omap_ctrl_readb(x) ? ? ? ? ? ? 0
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 0348fd7..8d9aa3e 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -85,6 +85,8 @@ extern unsigned int save_secure_ram_context_sz;
> ?extern unsigned int omap24xx_cpu_suspend_sz;
> ?extern unsigned int omap34xx_cpu_suspend_sz;
>
> +#define PM_RTA_ERRATUM_i608 ? ? ? ? ? ?(1 << 0)
> +
> ?#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> ?extern u16 pm34xx_errata;
> ?#define IS_PM34XX_ERRATUM(id) ? ? ? ? ?(pm34xx_errata & (id))
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 5702f41..b32a2ed 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -1007,6 +1007,8 @@ void omap_push_sram_idle(void)
>
> ?static void __init pm_errata_configure(void)
> ?{
> + ? ? ? if (cpu_is_omap3630())
> + ? ? ? ? ? ? ? pm34xx_errata |= PM_RTA_ERRATUM_i608;
> ?}
>
> ?static int __init omap3_pm_init(void)
> @@ -1067,6 +1069,14 @@ static int __init omap3_pm_init(void)
> ? ? ? ?pm_idle = omap3_pm_idle;
> ? ? ? ?omap3_idle_init();
>
> + ? ? ? /*
> + ? ? ? ?* RTA is disabled during initialization as per erratum i608
> + ? ? ? ?* it is safer to disable rta by the bootloader, but we would like
Use caps for RTA
> + ? ? ? ?* to be doubly sure here and prevent any mishaps.
> + ? ? ? ?*/
> + ? ? ? if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
> + ? ? ? ? ? ? ? omap3630_ctrl_disable_rta();
> +
> ? ? ? ?clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
> ? ? ? ?if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
> ? ? ? ? ? ? ? ?omap3_secure_ram_storage =
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index 3fbd1e5..cc3507b 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -45,6 +45,8 @@
> ?#define CM_IDLEST_CKGEN_V ? ? ?OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
> ?#define SRAM_BASE_P ? ? ? ? ? ?0x40200000
> ?#define CONTROL_STAT ? ? ? ? ? 0x480022F0
> +#define CONTROL_MEM_RTA_CTRL ? (OMAP343X_CTRL_BASE\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + OMAP36XX_CONTROL_MEM_RTA_CTRL)
> ?#define SCRATCHPAD_MEM_OFFS ? ?0x310 /* Move this as correct place is
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * available */
> ?#define SCRATCHPAD_BASE_P ? ? ?(OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\
> @@ -99,6 +101,14 @@ ENTRY(get_restore_pointer)
> ? ? ? ? ldmfd ? sp!, {pc} ? ? @ restore regs and return
> ?ENTRY(get_restore_pointer_sz)
> ? ? ? ? .word ? . - get_restore_pointer
> + ? ? ? .text
> +/* Function call to get the restore pointer for 3630 resume from OFF */
> +ENTRY(get_omap3630_restore_pointer)
> + ? ? ? ?stmfd ? sp!, {lr} ? ? @ save registers on stack
> + ? ? ? adr ? ? r0, restore_3630
> + ? ? ? ?ldmfd ? sp!, {pc} ? ? @ restore regs and return
> +ENTRY(get_omap3630_restore_pointer_sz)
> + ? ? ? ?.word ? . - get_omap3630_restore_pointer
>
> ? ? ? ?.text
> ?/* Function call to get the restore pointer for for ES3 to resume from OFF */
> @@ -246,6 +256,20 @@ copy_to_sram:
> ? ? ? ?bne ? ? copy_to_sram
> ? ? ? ?ldr ? ? r1, sram_base
> ? ? ? ?blx ? ? r1
> + ? ? ? b ? ? ? restore
> +
> +restore_3630:
> + ? ? ? /*b restore_es3630*/ ? ? ? ? ? ?@ Enable to debug restore code
> + ? ? ? ldr ? ? r1, pm_prepwstst_core_p
> + ? ? ? ldr ? ? r2, [r1]
> + ? ? ? and ? ? r2, r2, #0x3
> + ? ? ? cmp ? ? r2, #0x0 ? ? ? ?@ Check if previous power state of CORE is OFF
> + ? ? ? bne ? ? restore
> + ? ? ? /* Disable rta before giving control */
Use caps for RTA
> + ? ? ? ldr ? ? r1, control_mem_rta
> + ? ? ? mov ? ? r2, #OMAP36XX_RTA_DISABLE
> + ? ? ? str ? ? r2, [r1]
> + ? ? ? /* Fall thru for the remaining logic */
> ?restore:
> ? ? ? ?/* b restore*/ ?@ Enable to debug restore code
> ? ? ? ? /* Check what was the reason for mpu reset and store the reason in r9*/
> @@ -650,6 +674,8 @@ cache_pred_disable_mask:
> ? ? ? ?.word ? 0xFFFFE7FB
> ?control_stat:
> ? ? ? ?.word ? CONTROL_STAT
> +control_mem_rta:
> + ? ? ? .word ? CONTROL_MEM_RTA_CTRL
> ?kernel_flush:
> ? ? ? ?.word v7_flush_dcache_all
> ? ? ? ?/* these 2 words need to be at the end !!! */
> --
> 1.6.3.3
>
>
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 10:28 ` Jean Pihet
-1 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:28 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Kevin, Tony
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>
> This disables L2 cache before invalidating it and reenables it afterwards.
> This is be done according to ARM documentation. Currently this is identified
> as being needed on OMAP3630 as the disable/enable is done from "public side"
> while, on OMAP3430, this is done in the "secure side".
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [nm@ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
> ---
> v4: rebased only. no functional change
> v3: http://marc.info/?l=linux-omap&m=129139583519221&w=2
> collate all silicon specific errata under a single cpu detection code
> making it elegant and more maintainable.
> v2: https://patchwork.kernel.org/patch/365232/
> rebased out to this series independent of HS bugfixes
> v1: http://marc.info/?l=linux-omap&m=129013171125204&w=2
>
> arch/arm/mach-omap2/pm.h | 2 ++
> arch/arm/mach-omap2/pm34xx.c | 5 ++++-
> arch/arm/mach-omap2/sleep34xx.S | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 36 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 8d9aa3e..5e0bee9 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz;
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> #define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
> +extern void enable_omap3630_toggle_l2_on_restore(void);
> #else
> #define IS_PM34XX_ERRATUM(id) 0
> +static inline void enable_omap3630_toggle_l2_on_restore(void) { }
> #endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
>
> #endif
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index b32a2ed..4ba7a06 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -1007,8 +1007,11 @@ void omap_push_sram_idle(void)
>
> static void __init pm_errata_configure(void)
> {
> - if (cpu_is_omap3630())
> + if (cpu_is_omap3630()) {
> pm34xx_errata |= PM_RTA_ERRATUM_i608;
> + /* Enable the l2 cache toggling in sleep logic */
> + enable_omap3630_toggle_l2_on_restore();
> + }
> }
>
> static int __init omap3_pm_init(void)
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index cc3507b..d2eda01 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
> .word . - get_omap3630_restore_pointer
>
> .text
> +/*
> + * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
> + * This function sets up a fflag that will allow for this toggling to take
> + * place on 3630. Hopefully some version in the future maynot need this
> + */
> +ENTRY(enable_omap3630_toggle_l2_on_restore)
> + stmfd sp!, {lr} @ save registers on stack
> + /* Setup so that we will disable and enable l2 */
> + mov r1, #0x1
> + str r1, l2dis_3630
> + ldmfd sp!, {pc} @ restore regs and return
> +
> + .text
> /* Function call to get the restore pointer for for ES3 to resume from OFF */
> ENTRY(get_es3_restore_pointer)
> stmfd sp!, {lr} @ save registers on stack
> @@ -283,6 +296,14 @@ restore:
> moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
> movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
> bne logic_l1_restore
> +
> + ldr r0, l2dis_3630
> + cmp r0, #0x1 @ should we disable L2 on 3630?
> + bne skipl2dis
> + mrc p15, 0, r0, c1, c0, 1
> + bic r0, r0, #2 @ disable L2 cache
> + mcr p15, 0, r0, c1, c0, 1
> +skipl2dis:
> ldr r0, control_stat
> ldr r1, [r0]
> and r1, #0x700
> @@ -343,6 +364,13 @@ smi: .word 0xE1600070 @ Call SMI monitor (smieq)
> mov r12, #0x2
> .word 0xE1600070 @ Call SMI monitor (smieq)
> logic_l1_restore:
> + ldr r1, l2dis_3630
> + cmp r1, #0x1 @ Do we need to re-enable L2 on 3630?
> + bne skipl2reen
> + mrc p15, 0, r1, c1, c0, 1
> + orr r1, r1, #2 @ re-enable L2 cache
> + mcr p15, 0, r1, c1, c0, 1
> +skipl2reen:
> mov r1, #0
> /* Invalidate all instruction caches to PoU
> * and flush branch target cache */
> @@ -678,6 +706,8 @@ control_mem_rta:
> .word CONTROL_MEM_RTA_CTRL
> kernel_flush:
> .word v7_flush_dcache_all
> +l2dis_3630:
> + .word 0
> /* these 2 words need to be at the end !!! */
> kick_counter:
> .word 0
> --
> 1.6.3.3
>
>
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
@ 2010-12-20 10:28 ` Jean Pihet
0 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:28 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
>
> This disables L2 cache before invalidating it and reenables it afterwards.
> This is be done according to ARM documentation. Currently this is identified
> as being needed on OMAP3630 as the disable/enable is done from "public side"
> while, on OMAP3430, this is done in the "secure side".
>
> Cc: Kevin Hilman <khilman@deeprootsystems.com>
> Cc: Tony Lindgren <tony@atomide.com>
>
> [nm at ti.com: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
> Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
> ---
> v4: rebased only. no functional change
> v3: http://marc.info/?l=linux-omap&m=129139583519221&w=2
> collate all silicon specific errata under a single cpu detection code
> ? ? ? ?making it elegant and more maintainable.
> v2: https://patchwork.kernel.org/patch/365232/
> ? ? ? ?rebased out to this series independent of HS bugfixes
> v1: http://marc.info/?l=linux-omap&m=129013171125204&w=2
>
> ?arch/arm/mach-omap2/pm.h ? ? ? ?| ? ?2 ++
> ?arch/arm/mach-omap2/pm34xx.c ? ?| ? ?5 ++++-
> ?arch/arm/mach-omap2/sleep34xx.S | ? 30 ++++++++++++++++++++++++++++++
> ?3 files changed, 36 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 8d9aa3e..5e0bee9 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -90,8 +90,10 @@ extern unsigned int omap34xx_cpu_suspend_sz;
> ?#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> ?extern u16 pm34xx_errata;
> ?#define IS_PM34XX_ERRATUM(id) ? ? ? ? ?(pm34xx_errata & (id))
> +extern void enable_omap3630_toggle_l2_on_restore(void);
> ?#else
> ?#define IS_PM34XX_ERRATUM(id) ? ? ? ? ?0
> +static inline void enable_omap3630_toggle_l2_on_restore(void) { }
> ?#endif ? ? ? ? /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
>
> ?#endif
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index b32a2ed..4ba7a06 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -1007,8 +1007,11 @@ void omap_push_sram_idle(void)
>
> ?static void __init pm_errata_configure(void)
> ?{
> - ? ? ? if (cpu_is_omap3630())
> + ? ? ? if (cpu_is_omap3630()) {
> ? ? ? ? ? ? ? ?pm34xx_errata |= PM_RTA_ERRATUM_i608;
> + ? ? ? ? ? ? ? /* Enable the l2 cache toggling in sleep logic */
> + ? ? ? ? ? ? ? enable_omap3630_toggle_l2_on_restore();
> + ? ? ? }
> ?}
>
> ?static int __init omap3_pm_init(void)
> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> index cc3507b..d2eda01 100644
> --- a/arch/arm/mach-omap2/sleep34xx.S
> +++ b/arch/arm/mach-omap2/sleep34xx.S
> @@ -111,6 +111,19 @@ ENTRY(get_omap3630_restore_pointer_sz)
> ? ? ? ? .word ? . - get_omap3630_restore_pointer
>
> ? ? ? ?.text
> +/*
> + * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
> + * This function sets up a fflag that will allow for this toggling to take
> + * place on 3630. Hopefully some version in the future maynot need this
> + */
> +ENTRY(enable_omap3630_toggle_l2_on_restore)
> + ? ? ? ?stmfd ? sp!, {lr} ? ? @ save registers on stack
> + ? ? ? /* Setup so that we will disable and enable l2 */
> + ? ? ? mov ? ? r1, #0x1
> + ? ? ? str ? ? r1, l2dis_3630
> + ? ? ? ?ldmfd ? sp!, {pc} ? ? @ restore regs and return
> +
> + ? ? ? .text
> ?/* Function call to get the restore pointer for for ES3 to resume from OFF */
> ?ENTRY(get_es3_restore_pointer)
> ? ? ? ?stmfd ? sp!, {lr} ? ? ? @ save registers on stack
> @@ -283,6 +296,14 @@ restore:
> ? ? ? ? moveq ? r9, #0x3 ? ? ? ?@ MPU OFF => L1 and L2 lost
> ? ? ? ?movne ? r9, #0x1 ? ? ? ?@ Only L1 and L2 lost => avoid L2 invalidation
> ? ? ? ?bne ? ? logic_l1_restore
> +
> + ? ? ? ldr ? ? r0, l2dis_3630
> + ? ? ? cmp ? ? r0, #0x1 ? ? ? ?@ should we disable L2 on 3630?
> + ? ? ? bne ? ? skipl2dis
> + ? ? ? mrc ? ? p15, 0, r0, c1, c0, 1
> + ? ? ? bic ? ? r0, r0, #2 ? ? ?@ disable L2 cache
> + ? ? ? mcr ? ? p15, 0, r0, c1, c0, 1
> +skipl2dis:
> ? ? ? ?ldr ? ? r0, control_stat
> ? ? ? ?ldr ? ? r1, [r0]
> ? ? ? ?and ? ? r1, #0x700
> @@ -343,6 +364,13 @@ smi: ? ?.word 0xE1600070 ? ? ? ? ? @ Call SMI monitor (smieq)
> ? ? ? ?mov ? ? r12, #0x2
> ? ? ? ?.word 0xE1600070 ? ? ? ?@ Call SMI monitor (smieq)
> ?logic_l1_restore:
> + ? ? ? ldr ? ? r1, l2dis_3630
> + ? ? ? cmp ? ? r1, #0x1 ? ? ? ?@ Do we need to re-enable L2 on 3630?
> + ? ? ? bne ? ? skipl2reen
> + ? ? ? mrc ? ? p15, 0, r1, c1, c0, 1
> + ? ? ? orr ? ? r1, r1, #2 ? ? ?@ re-enable L2 cache
> + ? ? ? mcr ? ? p15, 0, r1, c1, c0, 1
> +skipl2reen:
> ? ? ? ?mov ? ? r1, #0
> ? ? ? ?/* Invalidate all instruction caches to PoU
> ? ? ? ? * and flush branch target cache */
> @@ -678,6 +706,8 @@ control_mem_rta:
> ? ? ? ?.word ? CONTROL_MEM_RTA_CTRL
> ?kernel_flush:
> ? ? ? ?.word v7_flush_dcache_all
> +l2dis_3630:
> + ? ? ? .word 0
> ? ? ? ?/* these 2 words need to be at the end !!! */
> ?kick_counter:
> ? ? ? ?.word ? 0
> --
> 1.6.3.3
>
>
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 10:28 ` Jean Pihet
-1 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:28 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Kevin, Tony
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> Currently omap3_cpuidle_update_states makes whole sale decision
> on which C states to update based on enable_off_mode variable
> Instead, achieve the same functionality by independently providing
> mpu and core deepest states the system is allowed to achieve and
> update the idle states accordingly.
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
> ---
> arch/arm/mach-omap2/cpuidle34xx.c | 19 ++++++++++---------
> arch/arm/mach-omap2/pm.h | 3 ++-
> arch/arm/mach-omap2/pm34xx.c | 2 +-
> 3 files changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index 0d50b45..f80d3f6 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -293,25 +293,26 @@ select_state:
> DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
>
> /**
> - * omap3_cpuidle_update_states - Update the cpuidle states.
> + * omap3_cpuidle_update_states() - Update the cpuidle states
> + * @mpu_deepest_state: Enable states upto and including this for mpu domain
> + * @core_deepest_state: Enable states upto and including this for core domain
> *
> - * Currently, this function toggles the validity of idle states based upon
> - * the flag 'enable_off_mode'. When the flag is set all states are valid.
> - * Else, states leading to OFF state set to be invalid.
> + * This goes through the list of states available and enables and disables the
> + * validity of C states based on deepest state that can be achieved for the
> + * variable domain
> */
> -void omap3_cpuidle_update_states(void)
> +void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
> {
> int i;
>
> for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
> struct omap3_processor_cx *cx = &omap3_power_states[i];
>
> - if (enable_off_mode) {
> + if ((cx->mpu_state >= mpu_deepest_state) &&
> + (cx->core_state >= core_deepest_state)) {
> cx->valid = 1;
> } else {
> - if ((cx->mpu_state == PWRDM_POWER_OFF) ||
> - (cx->core_state == PWRDM_POWER_OFF))
> - cx->valid = 0;
> + cx->valid = 0;
> }
> }
> }
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 5e0bee9..92ef400 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -58,7 +58,8 @@ extern u32 sleep_while_idle;
> #endif
>
> #if defined(CONFIG_CPU_IDLE)
> -extern void omap3_cpuidle_update_states(void);
> +extern void omap3_cpuidle_update_states(u32 core_deepest_state,
> + u32 core_deepest_state);
> #endif
>
> #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 4ba7a06..21cd36e 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -928,7 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
> state = PWRDM_POWER_RET;
>
> #ifdef CONFIG_CPU_IDLE
> - omap3_cpuidle_update_states();
> + omap3_cpuidle_update_states(state, state);
> #endif
>
> list_for_each_entry(pwrst, &pwrst_list, node) {
> --
> 1.6.3.3
>
>
--
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^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode
@ 2010-12-20 10:28 ` Jean Pihet
0 siblings, 0 replies; 75+ messages in thread
From: Jean Pihet @ 2010-12-20 10:28 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> Currently omap3_cpuidle_update_states makes whole sale decision
> on which C states to update based on enable_off_mode variable
> Instead, achieve the same functionality by independently providing
> mpu and core deepest states the system is allowed to achieve and
> update the idle states accordingly.
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
> ---
> ?arch/arm/mach-omap2/cpuidle34xx.c | ? 19 ++++++++++---------
> ?arch/arm/mach-omap2/pm.h ? ? ? ? ?| ? ?3 ++-
> ?arch/arm/mach-omap2/pm34xx.c ? ? ?| ? ?2 +-
> ?3 files changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index 0d50b45..f80d3f6 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -293,25 +293,26 @@ select_state:
> ?DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
>
> ?/**
> - * omap3_cpuidle_update_states - Update the cpuidle states.
> + * omap3_cpuidle_update_states() - Update the cpuidle states
> + * @mpu_deepest_state: Enable states upto and including this for mpu domain
> + * @core_deepest_state: ? ? ? ?Enable states upto and including this for core domain
> ?*
> - * Currently, this function toggles the validity of idle states based upon
> - * the flag 'enable_off_mode'. When the flag is set all states are valid.
> - * Else, states leading to OFF state set to be invalid.
> + * This goes through the list of states available and enables and disables the
> + * validity of C states based on deepest state that can be achieved for the
> + * variable domain
> ?*/
> -void omap3_cpuidle_update_states(void)
> +void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
> ?{
> ? ? ? ?int i;
>
> ? ? ? ?for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
> ? ? ? ? ? ? ? ?struct omap3_processor_cx *cx = &omap3_power_states[i];
>
> - ? ? ? ? ? ? ? if (enable_off_mode) {
> + ? ? ? ? ? ? ? if ((cx->mpu_state >= mpu_deepest_state) &&
> + ? ? ? ? ? ? ? ? ? (cx->core_state >= core_deepest_state)) {
> ? ? ? ? ? ? ? ? ? ? ? ?cx->valid = 1;
> ? ? ? ? ? ? ? ?} else {
> - ? ? ? ? ? ? ? ? ? ? ? if ((cx->mpu_state == PWRDM_POWER_OFF) ||
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (cx->core_state == PWRDM_POWER_OFF))
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cx->valid = 0;
> + ? ? ? ? ? ? ? ? ? ? ? cx->valid = 0;
> ? ? ? ? ? ? ? ?}
> ? ? ? ?}
> ?}
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 5e0bee9..92ef400 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -58,7 +58,8 @@ extern u32 sleep_while_idle;
> ?#endif
>
> ?#if defined(CONFIG_CPU_IDLE)
> -extern void omap3_cpuidle_update_states(void);
> +extern void omap3_cpuidle_update_states(u32 core_deepest_state,
> + ? ? ? ? ? ? ? u32 core_deepest_state);
> ?#endif
>
> ?#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 4ba7a06..21cd36e 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -928,7 +928,7 @@ void omap3_pm_off_mode_enable(int enable)
> ? ? ? ? ? ? ? ?state = PWRDM_POWER_RET;
>
> ?#ifdef CONFIG_CPU_IDLE
> - ? ? ? omap3_cpuidle_update_states();
> + ? ? ? omap3_cpuidle_update_states(state, state);
> ?#endif
>
> ? ? ? ?list_for_each_entry(pwrst, &pwrst_list, node) {
> --
> 1.6.3.3
>
>
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
2010-12-20 6:51 ` Santosh Shilimkar
@ 2010-12-20 11:22 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 11:22 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
Santosh Shilimkar wrote, on 12/20/2010 12:51 AM:
[...]
>> +
>> + /*
>> + * Erratum i583: implementation for ES rev< Es1.2 on 3630. We
>> cannot
>> + * enable OFF mode in a stable form for previous revisions.
>> + * we disable C7 state as a result.
>> + */
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
>> + omap3_power_states[OMAP3_STATE_C7].valid = 0;
>> + cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
> WARN_ONCE in IDLE also would be good.
>> + }
this state will not be active anyways as enable_off_mode is 0 by default.
>> }
>>
>> struct cpuidle_driver omap3_idle_driver = {
>> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
>> index 92ef400..9032d09 100644
>> --- a/arch/arm/mach-omap2/pm.h
>> +++ b/arch/arm/mach-omap2/pm.h
>> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
>> extern unsigned int omap34xx_cpu_suspend_sz;
>>
>> #define PM_RTA_ERRATUM_i608 (1<< 0)
>> +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1<< 1)
>>
>> #if defined(CONFIG_PM)&& defined(CONFIG_ARCH_OMAP3)
>> extern u16 pm34xx_errata;
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index 21cd36e..7faea55 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
>> state = PWRDM_POWER_RET;
>>
>> #ifdef CONFIG_CPU_IDLE
>> - omap3_cpuidle_update_states(state, state);
>> + /*
>> + * Erratum i583: implementation for ES rev< Es1.2 on 3630. We
>> cannot
>> + * enable OFF mode in a stable form for previous revisions,
> restrict
>> + * instead to RET
>> + */
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
>> + omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
>> + else
>> + omap3_cpuidle_update_states(state, state);
>> #endif
>>
>> list_for_each_entry(pwrst,&pwrst_list, node) {
>> - pwrst->next_state = state;
>> - omap_set_pwrdm_state(pwrst->pwrdm, state);
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)&&
>> + pwrst->pwrdm == core_pwrdm&&
>> + state == PWRDM_POWER_OFF) {
>> + pwrst->next_state = PWRDM_POWER_RET;
>> + pr_err("%s: Core OFF disabled due to errata
> i583\n",
> Shoud we do this in every iteration or just WARN_ONCE do ??
every time off mode is enabled? this path is not exercised for every cpu
idle/suspend iteration.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
@ 2010-12-20 11:22 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 11:22 UTC (permalink / raw)
To: linux-arm-kernel
Santosh Shilimkar wrote, on 12/20/2010 12:51 AM:
[...]
>> +
>> + /*
>> + * Erratum i583: implementation for ES rev< Es1.2 on 3630. We
>> cannot
>> + * enable OFF mode in a stable form for previous revisions.
>> + * we disable C7 state as a result.
>> + */
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
>> + omap3_power_states[OMAP3_STATE_C7].valid = 0;
>> + cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
> WARN_ONCE in IDLE also would be good.
>> + }
this state will not be active anyways as enable_off_mode is 0 by default.
>> }
>>
>> struct cpuidle_driver omap3_idle_driver = {
>> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
>> index 92ef400..9032d09 100644
>> --- a/arch/arm/mach-omap2/pm.h
>> +++ b/arch/arm/mach-omap2/pm.h
>> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
>> extern unsigned int omap34xx_cpu_suspend_sz;
>>
>> #define PM_RTA_ERRATUM_i608 (1<< 0)
>> +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1<< 1)
>>
>> #if defined(CONFIG_PM)&& defined(CONFIG_ARCH_OMAP3)
>> extern u16 pm34xx_errata;
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index 21cd36e..7faea55 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
>> state = PWRDM_POWER_RET;
>>
>> #ifdef CONFIG_CPU_IDLE
>> - omap3_cpuidle_update_states(state, state);
>> + /*
>> + * Erratum i583: implementation for ES rev< Es1.2 on 3630. We
>> cannot
>> + * enable OFF mode in a stable form for previous revisions,
> restrict
>> + * instead to RET
>> + */
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
>> + omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
>> + else
>> + omap3_cpuidle_update_states(state, state);
>> #endif
>>
>> list_for_each_entry(pwrst,&pwrst_list, node) {
>> - pwrst->next_state = state;
>> - omap_set_pwrdm_state(pwrst->pwrdm, state);
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)&&
>> + pwrst->pwrdm == core_pwrdm&&
>> + state == PWRDM_POWER_OFF) {
>> + pwrst->next_state = PWRDM_POWER_RET;
>> + pr_err("%s: Core OFF disabled due to errata
> i583\n",
> Shoud we do this in every iteration or just WARN_ONCE do ??
every time off mode is enabled? this path is not exercised for every cpu
idle/suspend iteration.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
2010-12-20 6:59 ` Santosh Shilimkar
@ 2010-12-20 11:23 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 11:23 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
Santosh Shilimkar wrote, on 12/20/2010 12:59 AM:
[..]
>> index 3fbd1e5..cc3507b 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -45,6 +45,8 @@
>> #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
>> #define SRAM_BASE_P 0x40200000
>> #define CONTROL_STAT 0x480022F0
>> +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
>> + + OMAP36XX_CONTROL_MEM_RTA_CTRL)
> Just a clarification. This register is not part of HW SAR SCM
> Registers, right ?
Right.
[..]
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
@ 2010-12-20 11:23 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 11:23 UTC (permalink / raw)
To: linux-arm-kernel
Santosh Shilimkar wrote, on 12/20/2010 12:59 AM:
[..]
>> index 3fbd1e5..cc3507b 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -45,6 +45,8 @@
>> #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
>> #define SRAM_BASE_P 0x40200000
>> #define CONTROL_STAT 0x480022F0
>> +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
>> + + OMAP36XX_CONTROL_MEM_RTA_CTRL)
> Just a clarification. This register is not part of HW SAR SCM
> Registers, right ?
Right.
[..]
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
2010-12-20 10:23 ` Jean Pihet
(?)
@ 2010-12-20 11:33 ` Peter 'p2' De Schrijver
2010-12-20 14:21 ` Nishanth Menon
-1 siblings, 1 reply; 75+ messages in thread
From: Peter 'p2' De Schrijver @ 2010-12-20 11:33 UTC (permalink / raw)
To: ext Jean Pihet; +Cc: Nishanth Menon, linux-omap, linux-arm, Kevin, Tony
On Mon, Dec 20, 2010 at 11:23:27AM +0100, ext Jean Pihet wrote:
> On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
> > From: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> >
> > Erratum i581 impacts OMAP3 platforms.
> > PRCM DPLL control FSM removes SDRC_IDLEREQ before DPLL3 locks causing
> > the DPLL not to be locked at times.
> >
> > IMPORTANT:
> > *) This is not a complete workaround implementation as recommended
> > by the silicon erratum. this is a support logic for detecting lockups and
> > attempting to recover where possible and is known to provide stability
> > in multiple platforms.
> > *) This code is mostly important for inactive and retention. The ROM code
> > waits for the maximum dll lock time when resuming from off mode. So for
> > off mode this code isn't really needed.
> >
> > This should eventually get refactored as part of cleanups to sleep34xx.S
> >
> > Cc: Kevin Hilman <khilman@deeprootsystems.com>
> > Cc: Tony Lindgren <tony@atomide.com>
> >
> > Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
> > ---
> > (no change done, posting for completeness of the series)
> > v2: https://patchwork.kernel.org/patch/365252/
> > typo correction- erratum, support, added comment from Peter from the
> > thread to commit message
> > v1: http://marc.info/?l=linux-omap&m=129013172525234&w=2
> > arch/arm/mach-omap2/sleep34xx.S | 52 +++++++++++++++++++++++++++++++++++---
> > 1 files changed, 47 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
> > index 2c20fcf..3fbd1e5 100644
> > --- a/arch/arm/mach-omap2/sleep34xx.S
> > +++ b/arch/arm/mach-omap2/sleep34xx.S
> > @@ -42,6 +42,7 @@
> > OMAP3430_PM_PREPWSTST)
> > #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
> > #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
> > +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
> > #define SRAM_BASE_P 0x40200000
> > #define CONTROL_STAT 0x480022F0
> > #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
> > @@ -554,31 +555,67 @@ skip_l2_inval:
> >
> > /* Make sure SDRC accesses are ok */
> > wait_sdrc_ok:
> > +
> > +/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this. */
> > + ldr r4, cm_idlest_ckgen
> > +wait_dpll3_lock:
> > + ldr r5, [r4]
> > + tst r5, #1
> > + beq wait_dpll3_lock
> > +
> > ldr r4, cm_idlest1_core
> > +wait_sdrc_ready:
> > ldr r5, [r4]
> > - and r5, r5, #0x2
> > - cmp r5, #0
> > - bne wait_sdrc_ok
> > + tst r5, #0x2
> > + bne wait_sdrc_ready
> > + /* allow DLL powerdown upon hw idle req */
> > ldr r4, sdrc_power
> > ldr r5, [r4]
> > bic r5, r5, #0x40
> > str r5, [r4]
> > -wait_dll_lock:
> > +is_dll_in_lock_mode:
> > +
> > /* Is dll in lock mode? */
> > ldr r4, sdrc_dlla_ctrl
> > ldr r5, [r4]
> > tst r5, #0x4
> > bxne lr
> > /* wait till dll locks */
> > - ldr r4, sdrc_dlla_status
> > +wait_dll_lock_timed:
> > + ldr r4, wait_dll_lock_counter
> > + add r4, r4, #1
> > + str r4, wait_dll_lock_counter
> > + ldr r4, sdrc_dlla_status
> > + mov r6, #8 /* Wait 20uS for lock */
> > +wait_dll_lock:
> > + subs r6, r6, #0x1
> > + beq kick_dll
>
> It would be good to have more comments on the code flow here:
> - what are wait_dll_lock_counter and kick_counter used for?
For debugging and statistics. So you can find out how many times a
'kick' was needed.
> - what is the timing based on? Why 20uS for the wait time?
This is the maximum lock time of the dll according to TI for OMAP3430.
> - jumping back and forth to kick_dll and wait_dll_lock_timed is confusing.
>
> > ldr r5, [r4]
> > and r5, r5, #0x4
> > cmp r5, #0x4
> > bne wait_dll_lock
> > bx lr
> >
> > + /* disable/reenable DLL if not locked */
> > +kick_dll:
> > + ldr r4, sdrc_dlla_ctrl
> > + ldr r5, [r4]
> > + mov r6, r5
> > + bic r6, #(1<<3) /* disable dll */
> > + str r6, [r4]
> > + dsb
> > + orr r6, r6, #(1<<3) /* enable dll */
> > + str r6, [r4]
> > + dsb
> > + ldr r4, kick_counter
> > + add r4, r4, #1
> > + str r4, kick_counter
> > + b wait_dll_lock_timed
> > +
> > cm_idlest1_core:
> > .word CM_IDLEST1_CORE_V
> > +cm_idlest_ckgen:
> > + .word CM_IDLEST_CKGEN_V
> > sdrc_dlla_status:
> > .word SDRC_DLLA_STATUS_V
> > sdrc_dlla_ctrl:
> > @@ -615,5 +652,10 @@ control_stat:
> > .word CONTROL_STAT
> > kernel_flush:
> > .word v7_flush_dcache_all
> > + /* these 2 words need to be at the end !!! */
> > +kick_counter:
> > + .word 0
> > +wait_dll_lock_counter:
> > + .word 0
> Why do they need to be at the end? Also, at the end of what do they need to be?
>
At the end of omap34xx_cpu_suspend. As we don't know where in SRAM the
counters will be, the code accessing those counters addresses them
relative from (_omap_sram_idle + omap34xx_cpu_suspend_sz). Not sure if
this part of the code made it to linux-omap though.
Cheers,
Peter.
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^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
2010-12-20 7:13 ` Santosh Shilimkar
@ 2010-12-20 11:44 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 11:44 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
Santosh Shilimkar wrote, on 12/20/2010 01:13 AM:
[..]
>> This is be done according to ARM documentation. Currently this is
>> identified
>> as being needed on OMAP3630 as the disable/enable is done from "public
>> side"
>> while, on OMAP3430, this is done in the "secure side".
> Can you point me to ARM doc which says " for L2 invalidation, the
> controller
> needs to be disabled" ?
please see section 8.3 of the Cortex-A8 TRM
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
@ 2010-12-20 11:44 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 11:44 UTC (permalink / raw)
To: linux-arm-kernel
Santosh Shilimkar wrote, on 12/20/2010 01:13 AM:
[..]
>> This is be done according to ARM documentation. Currently this is
>> identified
>> as being needed on OMAP3630 as the disable/enable is done from "public
>> side"
>> while, on OMAP3430, this is done in the "secure side".
> Can you point me to ARM doc which says " for L2 invalidation, the
> controller
> needs to be disabled" ?
please see section 8.3 of the Cortex-A8 TRM
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
2010-12-20 11:44 ` Nishanth Menon
@ 2010-12-20 12:14 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 12:14 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
> -----Original Message-----
> From: Nishanth Menon [mailto:nm@ti.com]
> Sent: Monday, December 20, 2010 5:15 PM
> To: Santosh Shilimkar
> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
> invalidating L2 cache
>
> Santosh Shilimkar wrote, on 12/20/2010 01:13 AM:
> [..]
> >> This is be done according to ARM documentation. Currently this is
> >> identified
> >> as being needed on OMAP3630 as the disable/enable is done from
"public
> >> side"
> >> while, on OMAP3430, this is done in the "secure side".
> > Can you point me to ARM doc which says " for L2 invalidation, the
> > controller
> > needs to be disabled" ?
> please see section 8.3 of the Cortex-A8 TRM
>
Yes. Have seen it and it doesn't say at least what your patch
description is saying.
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
@ 2010-12-20 12:14 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 12:14 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Nishanth Menon [mailto:nm at ti.com]
> Sent: Monday, December 20, 2010 5:15 PM
> To: Santosh Shilimkar
> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
> invalidating L2 cache
>
> Santosh Shilimkar wrote, on 12/20/2010 01:13 AM:
> [..]
> >> This is be done according to ARM documentation. Currently this is
> >> identified
> >> as being needed on OMAP3630 as the disable/enable is done from
"public
> >> side"
> >> while, on OMAP3430, this is done in the "secure side".
> > Can you point me to ARM doc which says " for L2 invalidation, the
> > controller
> > needs to be disabled" ?
> please see section 8.3 of the Cortex-A8 TRM
>
Yes. Have seen it and it doesn't say at least what your patch
description is saying.
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
2010-12-20 11:23 ` Nishanth Menon
@ 2010-12-20 12:15 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 12:15 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
> -----Original Message-----
> From: Nishanth Menon [mailto:nm@ti.com]
> Sent: Monday, December 20, 2010 4:54 PM
> To: Santosh Shilimkar
> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> Subject: Re: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
>
> Santosh Shilimkar wrote, on 12/20/2010 12:59 AM:
> [..]
> >> index 3fbd1e5..cc3507b 100644
> >> --- a/arch/arm/mach-omap2/sleep34xx.S
> >> +++ b/arch/arm/mach-omap2/sleep34xx.S
> >> @@ -45,6 +45,8 @@
> >> #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD,
> CM_IDLEST)
> >> #define SRAM_BASE_P 0x40200000
> >> #define CONTROL_STAT 0x480022F0
> >> +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
> >> + + OMAP36XX_CONTROL_MEM_RTA_CTRL)
> > Just a clarification. This register is not part of HW SAR SCM
> > Registers, right ?
> Right.
>
> [..]
Thanks.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
@ 2010-12-20 12:15 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 12:15 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Nishanth Menon [mailto:nm at ti.com]
> Sent: Monday, December 20, 2010 4:54 PM
> To: Santosh Shilimkar
> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> Subject: Re: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
>
> Santosh Shilimkar wrote, on 12/20/2010 12:59 AM:
> [..]
> >> index 3fbd1e5..cc3507b 100644
> >> --- a/arch/arm/mach-omap2/sleep34xx.S
> >> +++ b/arch/arm/mach-omap2/sleep34xx.S
> >> @@ -45,6 +45,8 @@
> >> #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD,
> CM_IDLEST)
> >> #define SRAM_BASE_P 0x40200000
> >> #define CONTROL_STAT 0x480022F0
> >> +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\
> >> + + OMAP36XX_CONTROL_MEM_RTA_CTRL)
> > Just a clarification. This register is not part of HW SAR SCM
> > Registers, right ?
> Right.
>
> [..]
Thanks.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
2010-12-20 12:14 ` Santosh Shilimkar
@ 2010-12-20 13:08 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 13:08 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
Santosh Shilimkar had written, on 12/20/2010 06:14 AM, the following:
>> -----Original Message-----
>> From: Nishanth Menon [mailto:nm@ti.com]
>> Sent: Monday, December 20, 2010 5:15 PM
>> To: Santosh Shilimkar
>> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
>> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
>> invalidating L2 cache
>>
>> Santosh Shilimkar wrote, on 12/20/2010 01:13 AM:
>> [..]
>>>> This is be done according to ARM documentation. Currently this is
>>>> identified
>>>> as being needed on OMAP3630 as the disable/enable is done from
> "public
>>>> side"
>>>> while, on OMAP3430, this is done in the "secure side".
>>> Can you point me to ARM doc which says " for L2 invalidation, the
>>> controller
>>> needs to be disabled" ?
>> please see section 8.3 of the Cortex-A8 TRM
>>
> Yes. Have seen it and it doesn't say at least what your patch
> description is saying.
See [1]
To disable the L2 cache, but leave the L1 data cache enabled, use the
following sequence:
1. Disable the C bit.
for details on C bit: see [2]
2. Clean and invalidate the L1 and L2 caches.
[...]
Does this help or do you have a suggestion on how the commit message
could be improved?
Ref:
[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Babigfeh.html
[2]
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Bgbciiaf.html
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
@ 2010-12-20 13:08 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 13:08 UTC (permalink / raw)
To: linux-arm-kernel
Santosh Shilimkar had written, on 12/20/2010 06:14 AM, the following:
>> -----Original Message-----
>> From: Nishanth Menon [mailto:nm at ti.com]
>> Sent: Monday, December 20, 2010 5:15 PM
>> To: Santosh Shilimkar
>> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
>> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
>> invalidating L2 cache
>>
>> Santosh Shilimkar wrote, on 12/20/2010 01:13 AM:
>> [..]
>>>> This is be done according to ARM documentation. Currently this is
>>>> identified
>>>> as being needed on OMAP3630 as the disable/enable is done from
> "public
>>>> side"
>>>> while, on OMAP3430, this is done in the "secure side".
>>> Can you point me to ARM doc which says " for L2 invalidation, the
>>> controller
>>> needs to be disabled" ?
>> please see section 8.3 of the Cortex-A8 TRM
>>
> Yes. Have seen it and it doesn't say at least what your patch
> description is saying.
See [1]
To disable the L2 cache, but leave the L1 data cache enabled, use the
following sequence:
1. Disable the C bit.
for details on C bit: see [2]
2. Clean and invalidate the L1 and L2 caches.
[...]
Does this help or do you have a suggestion on how the commit message
could be improved?
Ref:
[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Babigfeh.html
[2]
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Bgbciiaf.html
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
2010-12-20 13:08 ` Nishanth Menon
@ 2010-12-20 13:29 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 13:29 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
> -----Original Message-----
> From: Nishanth Menon [mailto:nm@ti.com]
> Sent: Monday, December 20, 2010 6:38 PM
> To: Santosh Shilimkar
> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
> invalidating L2 cache
>
> Santosh Shilimkar had written, on 12/20/2010 06:14 AM, the following:
> >> -----Original Message-----
> >> From: Nishanth Menon [mailto:nm@ti.com]
> >> Sent: Monday, December 20, 2010 5:15 PM
> >> To: Santosh Shilimkar
> >> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> >> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
> >> invalidating L2 cache
> >>
> >> Santosh Shilimkar wrote, on 12/20/2010 01:13 AM:
> >> [..]
> >>>> This is be done according to ARM documentation. Currently this is
> >>>> identified
> >>>> as being needed on OMAP3630 as the disable/enable is done from
> > "public
> >>>> side"
> >>>> while, on OMAP3430, this is done in the "secure side".
> >>> Can you point me to ARM doc which says " for L2 invalidation, the
> >>> controller
> >>> needs to be disabled" ?
> >> please see section 8.3 of the Cortex-A8 TRM
> >>
> > Yes. Have seen it and it doesn't say at least what your patch
> > description is saying.
> See [1]
> To disable the L2 cache, but leave the L1 data cache enabled, use the
> following sequence:
But it's not applicable to this piece of code. Your L1D is
not ON here either.
> 1. Disable the C bit.
> for details on C bit: see [2]
> 2. Clean and invalidate the L1 and L2 caches.
> [...]
> Does this help or do you have a suggestion on how the commit message
> could be improved?
>
Actually it doesn't. My worry is we might be trying to work-around some
OMAP specific issue. But as I said initially we do change the AUXCTRL
configuration and in that case the sequence is correct as per ARM TRM.
So may be you could update the change log something like below.
While coming out of MPU OSWR/OFF states, L2 controller is reseted.
The reset behavior is implementation specific as per ARMv7 TRM and
hence $L2 needs to be invalidated before it's use. Since the
AUXCTRL register is also reconfigured, disable L2 cache before
invalidating it and re-enables it afterwards. This is as per
Cortex-A8 ARM documentation.
Currently this is identified as being needed on OMAP3630 as the
disable/enable is done from "public side" while, on OMAP3430, this
is done in the "secure side".
Regards,
Santosh
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
@ 2010-12-20 13:29 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 13:29 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Nishanth Menon [mailto:nm at ti.com]
> Sent: Monday, December 20, 2010 6:38 PM
> To: Santosh Shilimkar
> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
> invalidating L2 cache
>
> Santosh Shilimkar had written, on 12/20/2010 06:14 AM, the following:
> >> -----Original Message-----
> >> From: Nishanth Menon [mailto:nm at ti.com]
> >> Sent: Monday, December 20, 2010 5:15 PM
> >> To: Santosh Shilimkar
> >> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> >> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
> >> invalidating L2 cache
> >>
> >> Santosh Shilimkar wrote, on 12/20/2010 01:13 AM:
> >> [..]
> >>>> This is be done according to ARM documentation. Currently this is
> >>>> identified
> >>>> as being needed on OMAP3630 as the disable/enable is done from
> > "public
> >>>> side"
> >>>> while, on OMAP3430, this is done in the "secure side".
> >>> Can you point me to ARM doc which says " for L2 invalidation, the
> >>> controller
> >>> needs to be disabled" ?
> >> please see section 8.3 of the Cortex-A8 TRM
> >>
> > Yes. Have seen it and it doesn't say at least what your patch
> > description is saying.
> See [1]
> To disable the L2 cache, but leave the L1 data cache enabled, use the
> following sequence:
But it's not applicable to this piece of code. Your L1D is
not ON here either.
> 1. Disable the C bit.
> for details on C bit: see [2]
> 2. Clean and invalidate the L1 and L2 caches.
> [...]
> Does this help or do you have a suggestion on how the commit message
> could be improved?
>
Actually it doesn't. My worry is we might be trying to work-around some
OMAP specific issue. But as I said initially we do change the AUXCTRL
configuration and in that case the sequence is correct as per ARM TRM.
So may be you could update the change log something like below.
While coming out of MPU OSWR/OFF states, L2 controller is reseted.
The reset behavior is implementation specific as per ARMv7 TRM and
hence $L2 needs to be invalidated before it's use. Since the
AUXCTRL register is also reconfigured, disable L2 cache before
invalidating it and re-enables it afterwards. This is as per
Cortex-A8 ARM documentation.
Currently this is identified as being needed on OMAP3630 as the
disable/enable is done from "public side" while, on OMAP3430, this
is done in the "secure side".
Regards,
Santosh
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
2010-12-20 13:29 ` Santosh Shilimkar
@ 2010-12-20 13:33 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 13:33 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
Santosh Shilimkar had written, on 12/20/2010 07:29 AM, the following:
[..]
> So may be you could update the change log something like below.
>
> While coming out of MPU OSWR/OFF states, L2 controller is reseted.
> The reset behavior is implementation specific as per ARMv7 TRM and
> hence $L2 needs to be invalidated before it's use. Since the
> AUXCTRL register is also reconfigured, disable L2 cache before
> invalidating it and re-enables it afterwards. This is as per
> Cortex-A8 ARM documentation.
> Currently this is identified as being needed on OMAP3630 as the
> disable/enable is done from "public side" while, on OMAP3430, this
> is done in the "secure side".
Thanks, will update the rev5 patch with this commit log.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
@ 2010-12-20 13:33 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 13:33 UTC (permalink / raw)
To: linux-arm-kernel
Santosh Shilimkar had written, on 12/20/2010 07:29 AM, the following:
[..]
> So may be you could update the change log something like below.
>
> While coming out of MPU OSWR/OFF states, L2 controller is reseted.
> The reset behavior is implementation specific as per ARMv7 TRM and
> hence $L2 needs to be invalidated before it's use. Since the
> AUXCTRL register is also reconfigured, disable L2 cache before
> invalidating it and re-enables it afterwards. This is as per
> Cortex-A8 ARM documentation.
> Currently this is identified as being needed on OMAP3630 as the
> disable/enable is done from "public side" while, on OMAP3430, this
> is done in the "secure side".
Thanks, will update the rev5 patch with this commit log.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* RE: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
2010-12-20 13:33 ` Nishanth Menon
@ 2010-12-20 13:37 ` Santosh Shilimkar
-1 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 13:37 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
> -----Original Message-----
> From: Nishanth Menon [mailto:nm@ti.com]
> Sent: Monday, December 20, 2010 7:03 PM
> To: Santosh Shilimkar
> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
> invalidating L2 cache
>
> Santosh Shilimkar had written, on 12/20/2010 07:29 AM, the following:
> [..]
> > So may be you could update the change log something like below.
> >
> > While coming out of MPU OSWR/OFF states, L2 controller is reseted.
> > The reset behavior is implementation specific as per ARMv7 TRM and
> > hence $L2 needs to be invalidated before it's use. Since the
> > AUXCTRL register is also reconfigured, disable L2 cache before
> > invalidating it and re-enables it afterwards. This is as per
> > Cortex-A8 ARM documentation.
> > Currently this is identified as being needed on OMAP3630 as the
> > disable/enable is done from "public side" while, on OMAP3430, this
> > is done in the "secure side".
> Thanks, will update the rev5 patch with this commit log.
>
Sure. With that change you could add,
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache
@ 2010-12-20 13:37 ` Santosh Shilimkar
0 siblings, 0 replies; 75+ messages in thread
From: Santosh Shilimkar @ 2010-12-20 13:37 UTC (permalink / raw)
To: linux-arm-kernel
> -----Original Message-----
> From: Nishanth Menon [mailto:nm at ti.com]
> Sent: Monday, December 20, 2010 7:03 PM
> To: Santosh Shilimkar
> Cc: linux-omap; linux-arm; Jean Pihet; Kevin; Tony
> Subject: Re: [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while
> invalidating L2 cache
>
> Santosh Shilimkar had written, on 12/20/2010 07:29 AM, the following:
> [..]
> > So may be you could update the change log something like below.
> >
> > While coming out of MPU OSWR/OFF states, L2 controller is reseted.
> > The reset behavior is implementation specific as per ARMv7 TRM and
> > hence $L2 needs to be invalidated before it's use. Since the
> > AUXCTRL register is also reconfigured, disable L2 cache before
> > invalidating it and re-enables it afterwards. This is as per
> > Cortex-A8 ARM documentation.
> > Currently this is identified as being needed on OMAP3630 as the
> > disable/enable is done from "public side" while, on OMAP3430, this
> > is done in the "secure side".
> Thanks, will update the rev5 patch with this commit log.
>
Sure. With that change you could add,
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
2010-12-20 6:47 ` Santosh Shilimkar
@ 2010-12-20 14:16 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 14:16 UTC (permalink / raw)
To: Santosh Shilimkar; +Cc: linux-omap, linux-arm, Jean Pihet, Kevin, Tony
Santosh Shilimkar had written, on 12/20/2010 12:47 AM, the following:
[..]
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
>> omap2/sleep34xx.S
>> index 2c20fcf..3fbd1e5 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -42,6 +42,7 @@
>> OMAP3430_PM_PREPWSTST)
>> #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD +
>> OMAP2_PM_PWSTCTRL
>> #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
>> +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
> We need to avoid these macro's calculating VA directly. But I guess
> it needs to be done more than just this line and hence can be done
> in a separate patch.
yes - with the cleanups planned for this file, we could probably add it
to that set I guess.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
@ 2010-12-20 14:16 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 14:16 UTC (permalink / raw)
To: linux-arm-kernel
Santosh Shilimkar had written, on 12/20/2010 12:47 AM, the following:
[..]
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-
>> omap2/sleep34xx.S
>> index 2c20fcf..3fbd1e5 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
>> @@ -42,6 +42,7 @@
>> OMAP3430_PM_PREPWSTST)
>> #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD +
>> OMAP2_PM_PWSTCTRL
>> #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
>> +#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
> We need to avoid these macro's calculating VA directly. But I guess
> it needs to be done more than just this line and hence can be done
> in a separate patch.
yes - with the cleanups planned for this file, we could probably add it
to that set I guess.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
2010-12-20 11:33 ` Peter 'p2' De Schrijver
@ 2010-12-20 14:21 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 14:21 UTC (permalink / raw)
To: Peter 'p2' De Schrijver
Cc: ext Jean Pihet, linux-omap, linux-arm, Kevin, Tony
Peter 'p2' De Schrijver had written, on 12/20/2010 05:33 AM, the following:
[..]
>>> + /* these 2 words need to be at the end !!! */
>>> +kick_counter:
>>> + .word 0
>>> +wait_dll_lock_counter:
>>> + .word 0
>> Why do they need to be at the end? Also, at the end of what do they need to be?
>>
>
> At the end of omap34xx_cpu_suspend. As we don't know where in SRAM the
> counters will be, the code accessing those counters addresses them
> relative from (_omap_sram_idle + omap34xx_cpu_suspend_sz). Not sure if
> this part of the code made it to linux-omap though.
I have not posted the change needed to expose these counters to
userspace waiting for the churn in sleep34xx.S to settle down.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy
@ 2010-12-20 14:21 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 14:21 UTC (permalink / raw)
To: linux-arm-kernel
Peter 'p2' De Schrijver had written, on 12/20/2010 05:33 AM, the following:
[..]
>>> + /* these 2 words need to be at the end !!! */
>>> +kick_counter:
>>> + .word 0
>>> +wait_dll_lock_counter:
>>> + .word 0
>> Why do they need to be at the end? Also, at the end of what do they need to be?
>>
>
> At the end of omap34xx_cpu_suspend. As we don't know where in SRAM the
> counters will be, the code accessing those counters addresses them
> relative from (_omap_sram_idle + omap34xx_cpu_suspend_sz). Not sure if
> this part of the code made it to linux-omap though.
I have not posted the change needed to expose these counters to
userspace waiting for the churn in sleep34xx.S to settle down.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 3/7] omap3: pm: introduce errata handling
2010-12-20 10:18 ` Jean Pihet
@ 2010-12-20 14:39 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 14:39 UTC (permalink / raw)
To: Jean Pihet; +Cc: linux-omap, linux-arm, Kevin, Tony
Jean Pihet had written, on 12/20/2010 04:18 AM, the following:
> Here a few minor remarks about typos:
>
> On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
>> Introduce errata handling for omap3. This patch introduces
> Use caps for OMAP3
>
>> errata variable and and stub for initialization which will be
> and and -> and
>
>> filled up by followon patches.
> followon -> follow-on?
Thanks. Updated for v5 of the patch.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 3/7] omap3: pm: introduce errata handling
@ 2010-12-20 14:39 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 14:39 UTC (permalink / raw)
To: linux-arm-kernel
Jean Pihet had written, on 12/20/2010 04:18 AM, the following:
> Here a few minor remarks about typos:
>
> On Sat, Dec 18, 2010 at 11:53 PM, Nishanth Menon <nm@ti.com> wrote:
>> Introduce errata handling for omap3. This patch introduces
> Use caps for OMAP3
>
>> errata variable and and stub for initialization which will be
> and and -> and
>
>> filled up by followon patches.
> followon -> follow-on?
Thanks. Updated for v5 of the patch.
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
2010-12-20 10:27 ` Jean Pihet
@ 2010-12-20 14:45 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 14:45 UTC (permalink / raw)
To: Jean Pihet; +Cc: linux-omap, linux-arm, Kevin, Tony
Jean Pihet had written, on 12/20/2010 04:27 AM, the following:
[..]
>> Workaround is to disable RTA on boot and coming out of core off.
>> For disabling rta coming out of off mode, we do this by overriding the
> Use caps for RTA
Thanks. done.
>
>> restore pointer for 3630 to allow us restore handler as the first point of
> This is not clear, maybe 'to allow us to restore handler' needs to be removed.
Thanks. done.
>
>> entry before caches are touched and is common for GP and HS devices.
>> to disable earlier than this could be possible by modifying the ppa for HS
> Same here, it looks like the original sentence has been cut in pieces.
> Use caps for PPA.
Thanks. done.
[..]
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index 5702f41..b32a2ed 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
[..]
>> @@ -1067,6 +1069,14 @@ static int __init omap3_pm_init(void)
>> pm_idle = omap3_pm_idle;
>> omap3_idle_init();
>>
>> + /*
>> + * RTA is disabled during initialization as per erratum i608
>> + * it is safer to disable rta by the bootloader, but we would like
> Use caps for RTA
thanks. Done.
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
>> index 3fbd1e5..cc3507b 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
[..]
>> +restore_3630:
>> + /*b restore_es3630*/ @ Enable to debug restore code
>> + ldr r1, pm_prepwstst_core_p
>> + ldr r2, [r1]
>> + and r2, r2, #0x3
>> + cmp r2, #0x0 @ Check if previous power state of CORE is OFF
>> + bne restore
>> + /* Disable rta before giving control */
> Use caps for RTA
Thanks. Done.
[..]
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA
@ 2010-12-20 14:45 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 14:45 UTC (permalink / raw)
To: linux-arm-kernel
Jean Pihet had written, on 12/20/2010 04:27 AM, the following:
[..]
>> Workaround is to disable RTA on boot and coming out of core off.
>> For disabling rta coming out of off mode, we do this by overriding the
> Use caps for RTA
Thanks. done.
>
>> restore pointer for 3630 to allow us restore handler as the first point of
> This is not clear, maybe 'to allow us to restore handler' needs to be removed.
Thanks. done.
>
>> entry before caches are touched and is common for GP and HS devices.
>> to disable earlier than this could be possible by modifying the ppa for HS
> Same here, it looks like the original sentence has been cut in pieces.
> Use caps for PPA.
Thanks. done.
[..]
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index 5702f41..b32a2ed 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
[..]
>> @@ -1067,6 +1069,14 @@ static int __init omap3_pm_init(void)
>> pm_idle = omap3_pm_idle;
>> omap3_idle_init();
>>
>> + /*
>> + * RTA is disabled during initialization as per erratum i608
>> + * it is safer to disable rta by the bootloader, but we would like
> Use caps for RTA
thanks. Done.
>> diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
>> index 3fbd1e5..cc3507b 100644
>> --- a/arch/arm/mach-omap2/sleep34xx.S
>> +++ b/arch/arm/mach-omap2/sleep34xx.S
[..]
>> +restore_3630:
>> + /*b restore_es3630*/ @ Enable to debug restore code
>> + ldr r1, pm_prepwstst_core_p
>> + ldr r2, [r1]
>> + and r2, r2, #0x3
>> + cmp r2, #0x0 @ Check if previous power state of CORE is OFF
>> + bne restore
>> + /* Disable rta before giving control */
> Use caps for RTA
Thanks. Done.
[..]
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
2010-12-18 22:53 ` Nishanth Menon
@ 2010-12-20 19:05 ` Kevin Hilman
-1 siblings, 0 replies; 75+ messages in thread
From: Kevin Hilman @ 2010-12-20 19:05 UTC (permalink / raw)
To: Nishanth Menon; +Cc: linux-omap, linux-arm, Jean Pihet, Tony
Nishanth Menon <nm@ti.com> writes:
> From: Eduardo Valentin <eduardo.valentin@nokia.com>
>
> Limitation i583: Self_Refresh Exit issue after OFF mode
>
> Issue:
> When device is waking up from OFF mode, then SDRC state machine sends
> inappropriate sequence violating JEDEC standards.
>
> Impact:
> OMAP3630 < ES1.2 is impacted as follows depending on the platform:
> CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable, while
> for all other sysclk frequencies, varied levels of instability
> seen based on varied parameters.
> CS1: impacted
>
> This patch takes option #3 as recommended by the Silicon erratum:
> Avoid core power domain transitioning to OFF mode. Power consumption
> impact is expected in this case.
> To do this, we route core OFF requests to RET request on the impacted
> revisions of silicon.
>
> [nm@ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a bit]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
> ---
> v4: idle state control changed a bit -we wont register or enable
> the states which cannot be enabled.
I like this version. Thanks.
> v3: http://marc.info/?t=129140247800027&r=1&w=2
> no functional change in erratum wa implementation, just registration of
> erratum is collated to a single cpu detection and version check
> v2: https://patchwork.kernel.org/patch/365262/
> rebased to this patch series instead of depending on hs changes
> fix typo for macro definition
> v1: http://marc.info/?l=linux-omap&m=129013173425266&w=2
> arch/arm/mach-omap2/cpuidle34xx.c | 10 ++++++++++
> arch/arm/mach-omap2/pm.h | 1 +
> arch/arm/mach-omap2/pm34xx.c | 24 +++++++++++++++++++++---
> 3 files changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index f80d3f6..1b32e98 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -453,6 +453,16 @@ void omap_init_power_states(void)
> omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
> omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
> CPUIDLE_FLAG_CHECK_BM;
> +
> + /*
> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
> + * enable OFF mode in a stable form for previous revisions.
> + * we disable C7 state as a result.
> + */
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
> + omap3_power_states[OMAP3_STATE_C7].valid = 0;
> + cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
> + }
> }
>
> struct cpuidle_driver omap3_idle_driver = {
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 92ef400..9032d09 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
> extern unsigned int omap34xx_cpu_suspend_sz;
>
> #define PM_RTA_ERRATUM_i608 (1 << 0)
> +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
>
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 21cd36e..7faea55 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
> state = PWRDM_POWER_RET;
>
> #ifdef CONFIG_CPU_IDLE
> - omap3_cpuidle_update_states(state, state);
> + /*
> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
> + * enable OFF mode in a stable form for previous revisions, restrict
> + * instead to RET
> + */
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
> + omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
> + else
> + omap3_cpuidle_update_states(state, state);
> #endif
>
> list_for_each_entry(pwrst, &pwrst_list, node) {
> - pwrst->next_state = state;
> - omap_set_pwrdm_state(pwrst->pwrdm, state);
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
> + pwrst->pwrdm == core_pwrdm &&
> + state == PWRDM_POWER_OFF) {
> + pwrst->next_state = PWRDM_POWER_RET;
> + pr_err("%s: Core OFF disabled due to errata i583\n",
> + __func__);
This is a warning, not an error condition, so should probably be
pr_warning().
That being said, this could be noisy if enable_off_mode is being toggled
repeatedly, so using WARN_ONCE() might be more appropriate as suggested
by others.
Kevin
> + } else {
> + pwrst->next_state = state;
> + }
> + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
> }
> }
>
> @@ -1011,6 +1027,8 @@ static void __init pm_errata_configure(void)
> pm34xx_errata |= PM_RTA_ERRATUM_i608;
> /* Enable the l2 cache toggling in sleep logic */
> enable_omap3630_toggle_l2_on_restore();
> + if (omap_rev() < OMAP3630_REV_ES1_2)
> + pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
> }
> }
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
@ 2010-12-20 19:05 ` Kevin Hilman
0 siblings, 0 replies; 75+ messages in thread
From: Kevin Hilman @ 2010-12-20 19:05 UTC (permalink / raw)
To: linux-arm-kernel
Nishanth Menon <nm@ti.com> writes:
> From: Eduardo Valentin <eduardo.valentin@nokia.com>
>
> Limitation i583: Self_Refresh Exit issue after OFF mode
>
> Issue:
> When device is waking up from OFF mode, then SDRC state machine sends
> inappropriate sequence violating JEDEC standards.
>
> Impact:
> OMAP3630 < ES1.2 is impacted as follows depending on the platform:
> CS0: for 38.4MHz as internal sysclk, DDR content seen to be stable, while
> for all other sysclk frequencies, varied levels of instability
> seen based on varied parameters.
> CS1: impacted
>
> This patch takes option #3 as recommended by the Silicon erratum:
> Avoid core power domain transitioning to OFF mode. Power consumption
> impact is expected in this case.
> To do this, we route core OFF requests to RET request on the impacted
> revisions of silicon.
>
> [nm at ti.com: rebased the code to 2.6.37-rc2- short circuit code changed a bit]
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com>
> ---
> v4: idle state control changed a bit -we wont register or enable
> the states which cannot be enabled.
I like this version. Thanks.
> v3: http://marc.info/?t=129140247800027&r=1&w=2
> no functional change in erratum wa implementation, just registration of
> erratum is collated to a single cpu detection and version check
> v2: https://patchwork.kernel.org/patch/365262/
> rebased to this patch series instead of depending on hs changes
> fix typo for macro definition
> v1: http://marc.info/?l=linux-omap&m=129013173425266&w=2
> arch/arm/mach-omap2/cpuidle34xx.c | 10 ++++++++++
> arch/arm/mach-omap2/pm.h | 1 +
> arch/arm/mach-omap2/pm34xx.c | 24 +++++++++++++++++++++---
> 3 files changed, 32 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
> index f80d3f6..1b32e98 100644
> --- a/arch/arm/mach-omap2/cpuidle34xx.c
> +++ b/arch/arm/mach-omap2/cpuidle34xx.c
> @@ -453,6 +453,16 @@ void omap_init_power_states(void)
> omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
> omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
> CPUIDLE_FLAG_CHECK_BM;
> +
> + /*
> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
> + * enable OFF mode in a stable form for previous revisions.
> + * we disable C7 state as a result.
> + */
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
> + omap3_power_states[OMAP3_STATE_C7].valid = 0;
> + cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
> + }
> }
>
> struct cpuidle_driver omap3_idle_driver = {
> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
> index 92ef400..9032d09 100644
> --- a/arch/arm/mach-omap2/pm.h
> +++ b/arch/arm/mach-omap2/pm.h
> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
> extern unsigned int omap34xx_cpu_suspend_sz;
>
> #define PM_RTA_ERRATUM_i608 (1 << 0)
> +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
>
> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
> extern u16 pm34xx_errata;
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 21cd36e..7faea55 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
> state = PWRDM_POWER_RET;
>
> #ifdef CONFIG_CPU_IDLE
> - omap3_cpuidle_update_states(state, state);
> + /*
> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
> + * enable OFF mode in a stable form for previous revisions, restrict
> + * instead to RET
> + */
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
> + omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
> + else
> + omap3_cpuidle_update_states(state, state);
> #endif
>
> list_for_each_entry(pwrst, &pwrst_list, node) {
> - pwrst->next_state = state;
> - omap_set_pwrdm_state(pwrst->pwrdm, state);
> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
> + pwrst->pwrdm == core_pwrdm &&
> + state == PWRDM_POWER_OFF) {
> + pwrst->next_state = PWRDM_POWER_RET;
> + pr_err("%s: Core OFF disabled due to errata i583\n",
> + __func__);
This is a warning, not an error condition, so should probably be
pr_warning().
That being said, this could be noisy if enable_off_mode is being toggled
repeatedly, so using WARN_ONCE() might be more appropriate as suggested
by others.
Kevin
> + } else {
> + pwrst->next_state = state;
> + }
> + omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
> }
> }
>
> @@ -1011,6 +1027,8 @@ static void __init pm_errata_configure(void)
> pm34xx_errata |= PM_RTA_ERRATUM_i608;
> /* Enable the l2 cache toggling in sleep logic */
> enable_omap3630_toggle_l2_on_restore();
> + if (omap_rev() < OMAP3630_REV_ES1_2)
> + pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
> }
> }
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
2010-12-20 19:05 ` Kevin Hilman
@ 2010-12-20 19:07 ` Nishanth Menon
-1 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 19:07 UTC (permalink / raw)
To: Kevin Hilman; +Cc: linux-omap, linux-arm, Jean Pihet, Tony
Kevin Hilman had written, on 12/20/2010 01:05 PM, the following:
[..]
>> struct cpuidle_driver omap3_idle_driver = {
>> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
>> index 92ef400..9032d09 100644
>> --- a/arch/arm/mach-omap2/pm.h
>> +++ b/arch/arm/mach-omap2/pm.h
>> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
>> extern unsigned int omap34xx_cpu_suspend_sz;
>>
>> #define PM_RTA_ERRATUM_i608 (1 << 0)
>> +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
>>
>> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
>> extern u16 pm34xx_errata;
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index 21cd36e..7faea55 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
>> state = PWRDM_POWER_RET;
>>
>> #ifdef CONFIG_CPU_IDLE
>> - omap3_cpuidle_update_states(state, state);
>> + /*
>> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
>> + * enable OFF mode in a stable form for previous revisions, restrict
>> + * instead to RET
>> + */
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
>> + omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
>> + else
>> + omap3_cpuidle_update_states(state, state);
>> #endif
>>
>> list_for_each_entry(pwrst, &pwrst_list, node) {
>> - pwrst->next_state = state;
>> - omap_set_pwrdm_state(pwrst->pwrdm, state);
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
>> + pwrst->pwrdm == core_pwrdm &&
>> + state == PWRDM_POWER_OFF) {
>> + pwrst->next_state = PWRDM_POWER_RET;
>> + pr_err("%s: Core OFF disabled due to errata i583\n",
>> + __func__);
>
> This is a warning, not an error condition, so should probably be
> pr_warning().
>
> That being said, this could be noisy if enable_off_mode is being toggled
> repeatedly, so using WARN_ONCE() might be more appropriate as suggested
> by others.
ok WARN_ONCE it is then.. :) next rev coming right up in a few more mins..
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
* [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2
@ 2010-12-20 19:07 ` Nishanth Menon
0 siblings, 0 replies; 75+ messages in thread
From: Nishanth Menon @ 2010-12-20 19:07 UTC (permalink / raw)
To: linux-arm-kernel
Kevin Hilman had written, on 12/20/2010 01:05 PM, the following:
[..]
>> struct cpuidle_driver omap3_idle_driver = {
>> diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
>> index 92ef400..9032d09 100644
>> --- a/arch/arm/mach-omap2/pm.h
>> +++ b/arch/arm/mach-omap2/pm.h
>> @@ -87,6 +87,7 @@ extern unsigned int omap24xx_cpu_suspend_sz;
>> extern unsigned int omap34xx_cpu_suspend_sz;
>>
>> #define PM_RTA_ERRATUM_i608 (1 << 0)
>> +#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
>>
>> #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
>> extern u16 pm34xx_errata;
>> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
>> index 21cd36e..7faea55 100644
>> --- a/arch/arm/mach-omap2/pm34xx.c
>> +++ b/arch/arm/mach-omap2/pm34xx.c
>> @@ -928,12 +928,28 @@ void omap3_pm_off_mode_enable(int enable)
>> state = PWRDM_POWER_RET;
>>
>> #ifdef CONFIG_CPU_IDLE
>> - omap3_cpuidle_update_states(state, state);
>> + /*
>> + * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
>> + * enable OFF mode in a stable form for previous revisions, restrict
>> + * instead to RET
>> + */
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
>> + omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
>> + else
>> + omap3_cpuidle_update_states(state, state);
>> #endif
>>
>> list_for_each_entry(pwrst, &pwrst_list, node) {
>> - pwrst->next_state = state;
>> - omap_set_pwrdm_state(pwrst->pwrdm, state);
>> + if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
>> + pwrst->pwrdm == core_pwrdm &&
>> + state == PWRDM_POWER_OFF) {
>> + pwrst->next_state = PWRDM_POWER_RET;
>> + pr_err("%s: Core OFF disabled due to errata i583\n",
>> + __func__);
>
> This is a warning, not an error condition, so should probably be
> pr_warning().
>
> That being said, this could be noisy if enable_off_mode is being toggled
> repeatedly, so using WARN_ONCE() might be more appropriate as suggested
> by others.
ok WARN_ONCE it is then.. :) next rev coming right up in a few more mins..
--
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 75+ messages in thread
end of thread, other threads:[~2010-12-20 19:07 UTC | newest]
Thread overview: 75+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-12-18 22:53 [PATCH v4 0/7] OMAP: idle path errata fixes Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-18 22:53 ` [PATCH v4 1/7] OMAP3: PM: Update clean_l2 to use v7_flush_dcache_all Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 6:43 ` Santosh Shilimkar
2010-12-20 6:43 ` Santosh Shilimkar
2010-12-20 10:19 ` Jean Pihet
2010-12-20 10:19 ` Jean Pihet
2010-12-18 22:53 ` [PATCH v4 2/7] OMAP3: PM: Erratum i581 support: dll kick strategy Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 6:47 ` Santosh Shilimkar
2010-12-20 6:47 ` Santosh Shilimkar
2010-12-20 14:16 ` Nishanth Menon
2010-12-20 14:16 ` Nishanth Menon
2010-12-20 10:23 ` Jean Pihet
2010-12-20 10:23 ` Jean Pihet
2010-12-20 11:33 ` Peter 'p2' De Schrijver
2010-12-20 14:21 ` Nishanth Menon
2010-12-20 14:21 ` Nishanth Menon
2010-12-18 22:53 ` [PATCH v4 3/7] omap3: pm: introduce errata handling Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 10:18 ` Jean Pihet
2010-12-20 10:18 ` Jean Pihet
2010-12-20 14:39 ` Nishanth Menon
2010-12-20 14:39 ` Nishanth Menon
2010-12-18 22:53 ` [PATCH v4 4/7] OMAP3630: PM: Erratum i608: disable RTA Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 6:59 ` Santosh Shilimkar
2010-12-20 6:59 ` Santosh Shilimkar
2010-12-20 11:23 ` Nishanth Menon
2010-12-20 11:23 ` Nishanth Menon
2010-12-20 12:15 ` Santosh Shilimkar
2010-12-20 12:15 ` Santosh Shilimkar
2010-12-20 10:27 ` Jean Pihet
2010-12-20 10:27 ` Jean Pihet
2010-12-20 14:45 ` Nishanth Menon
2010-12-20 14:45 ` Nishanth Menon
2010-12-18 22:53 ` [PATCH v4 5/7] OMAP3630: PM: Disable L2 cache while invalidating L2 cache Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 7:13 ` Santosh Shilimkar
2010-12-20 7:13 ` Santosh Shilimkar
2010-12-20 11:44 ` Nishanth Menon
2010-12-20 11:44 ` Nishanth Menon
2010-12-20 12:14 ` Santosh Shilimkar
2010-12-20 12:14 ` Santosh Shilimkar
2010-12-20 13:08 ` Nishanth Menon
2010-12-20 13:08 ` Nishanth Menon
2010-12-20 13:29 ` Santosh Shilimkar
2010-12-20 13:29 ` Santosh Shilimkar
2010-12-20 13:33 ` Nishanth Menon
2010-12-20 13:33 ` Nishanth Menon
2010-12-20 13:37 ` Santosh Shilimkar
2010-12-20 13:37 ` Santosh Shilimkar
2010-12-20 10:28 ` Jean Pihet
2010-12-20 10:28 ` Jean Pihet
2010-12-18 22:53 ` [PATCH v4 6/7] OMAP3: PM: make omap3_cpuidle_update_states independent of enable_off_mode Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 7:16 ` Santosh Shilimkar
2010-12-20 7:16 ` Santosh Shilimkar
2010-12-20 10:28 ` Jean Pihet
2010-12-20 10:28 ` Jean Pihet
2010-12-18 22:53 ` [PATCH v4 7/7] OMAP3630: PM: Erratum i583: disable coreoff if < ES1.2 Nishanth Menon
2010-12-18 22:53 ` Nishanth Menon
2010-12-20 6:51 ` Santosh Shilimkar
2010-12-20 6:51 ` Santosh Shilimkar
2010-12-20 10:26 ` Jean Pihet
2010-12-20 10:26 ` Jean Pihet
2010-12-20 11:22 ` Nishanth Menon
2010-12-20 11:22 ` Nishanth Menon
2010-12-20 19:05 ` Kevin Hilman
2010-12-20 19:05 ` Kevin Hilman
2010-12-20 19:07 ` Nishanth Menon
2010-12-20 19:07 ` Nishanth Menon
2010-12-20 10:17 ` [PATCH v4 0/7] OMAP: idle path errata fixes Jean Pihet
2010-12-20 10:17 ` Jean Pihet
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