[PATCH] cortex-m3: adjusted target cflags

[PATCH] cortex-m3: adjusted target cflags

[Enrico Scholz]

Explicit '-mthumb' is required because Cortex-M3 does not support ARM
instructions and actual flags cause gcc to fail with 'error: target CPU
does not support ARM mode'.

The '-mcpu=cortex-m3' is shorter than '-march=armv7-m -mtune=cortex-m3'
and enables workarounds like '-mfix-cortex-m3-ldrd'.

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
---
 conf/machine/include/tune-cortexm3.inc |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/conf/machine/include/tune-cortexm3.inc b/conf/machine/include/tune-cortexm3.inc
index 6da9aee..a66a33c 100644
--- a/conf/machine/include/tune-cortexm3.inc
+++ b/conf/machine/include/tune-cortexm3.inc
@@ -1,4 +1,4 @@
 # valid options for -march: `armv7', `armv7-m'
-TARGET_CC_ARCH = "-march=armv7-m -mtune=cortex-m3 -mfpu=vfp -mfloat-abi=softfp"
+TARGET_CC_ARCH = "-mthumb -mcpu=cortex-m3 -mfpu=vfp -mfloat-abi=softfp"
 FEED_ARCH = "armv7"
 BASE_PACKAGE_ARCH = "armv7"
-- 
1.7.4

[PATCH] gcc-4.5: added thumb2 build patch

[Enrico Scholz]

Fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43999 and is
required to build gcc for Thumb2 only architectures (e.g. Cortex-M3).

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
---
 recipes/gcc/gcc-4.5.inc                |    3 ++-
 recipes/gcc/gcc-4.5/thumb2-build.patch |   11 +++++++++++
 2 files changed, 13 insertions(+), 1 deletions(-)
 create mode 100644 recipes/gcc/gcc-4.5/thumb2-build.patch

diff --git a/recipes/gcc/gcc-4.5.inc b/recipes/gcc/gcc-4.5.inc
index b630528..9ba2e22 100644
--- a/recipes/gcc/gcc-4.5.inc
+++ b/recipes/gcc/gcc-4.5.inc
@@ -8,7 +8,7 @@ DEPENDS = "mpfr gmp libmpc libelf"
 NATIVEDEPS = "mpfr-native gmp-native libmpc-native"
 
 
-INC_PR = "r31"
+INC_PR = "r32"
 
 SRCREV = "168622"
 PV = "4.5"
@@ -166,6 +166,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH} \
 #	   file://linaro/gcc-4.5-linaro-r99457.patch \
 	   file://gcc-scalar-widening-pr45847.patch \
 	   file://gcc-arm-volatile-bitfield-fix.patch \
+	   file://thumb2-build.patch \
 	  "
 
 SRC_URI_append_mips64 = " file://mips64-nomultilib.patch "
diff --git a/recipes/gcc/gcc-4.5/thumb2-build.patch b/recipes/gcc/gcc-4.5/thumb2-build.patch
new file mode 100644
index 0000000..8fefbfa
--- /dev/null
+++ b/recipes/gcc/gcc-4.5/thumb2-build.patch
@@ -0,0 +1,11 @@
+Index: gcc/config/arm/lib1funcs.asm
+===================================================================
+--- a/gcc/config/arm/lib1funcs.asm	(revision 163231)
++++ b/gcc/config/arm/lib1funcs.asm	(working copy)
+@@ -642,5 +642,5 @@
+ 	cmp	\dividend, #0			@ Early termination?
+-	do_it	hs, t
++	do_it	ne, t
+ 	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
+ 	movne	\divisor,  \divisor, lsr #4
+ 	bne	1b
-- 
1.7.4

Re: [PATCH] gcc-4.5: added thumb2 build patch

[Koen Kooi]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 07-02-11 16:53, Enrico Scholz wrote:
> Fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43999 and is
> required to build gcc for Thumb2 only architectures (e.g. Cortex-M3).
> 
> Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
> ---
>  recipes/gcc/gcc-4.5.inc                |    3 ++-
>  recipes/gcc/gcc-4.5/thumb2-build.patch |   11 +++++++++++
>  2 files changed, 13 insertions(+), 1 deletions(-)
>  create mode 100644 recipes/gcc/gcc-4.5/thumb2-build.patch
> 
> diff --git a/recipes/gcc/gcc-4.5.inc b/recipes/gcc/gcc-4.5.inc
> index b630528..9ba2e22 100644
> --- a/recipes/gcc/gcc-4.5.inc
> +++ b/recipes/gcc/gcc-4.5.inc
> @@ -8,7 +8,7 @@ DEPENDS = "mpfr gmp libmpc libelf"
>  NATIVEDEPS = "mpfr-native gmp-native libmpc-native"
>  
>  
> -INC_PR = "r31"
> +INC_PR = "r32"
>  
>  SRCREV = "168622"
>  PV = "4.5"
> @@ -166,6 +166,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH} \
>  #	   file://linaro/gcc-4.5-linaro-r99457.patch \
>  	   file://gcc-scalar-widening-pr45847.patch \
>  	   file://gcc-arm-volatile-bitfield-fix.patch \
> +	   file://thumb2-build.patch \
>  	  "
>  
>  SRC_URI_append_mips64 = " file://mips64-nomultilib.patch "
> diff --git a/recipes/gcc/gcc-4.5/thumb2-build.patch b/recipes/gcc/gcc-4.5/thumb2-build.patch
> new file mode 100644
> index 0000000..8fefbfa
> --- /dev/null
> +++ b/recipes/gcc/gcc-4.5/thumb2-build.patch
> @@ -0,0 +1,11 @@
> +Index: gcc/config/arm/lib1funcs.asm
> +===================================================================
> +--- a/gcc/config/arm/lib1funcs.asm	(revision 163231)
> ++++ b/gcc/config/arm/lib1funcs.asm	(working copy)
> +@@ -642,5 +642,5 @@
> + 	cmp	\dividend, #0			@ Early termination?
> +-	do_it	hs, t
> ++	do_it	ne, t
> + 	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
> + 	movne	\divisor,  \divisor, lsr #4
> + 	bne	1b

COuld you please add some more information to the thumb2-build.patch
file? The author and bugzilla link should be enough.
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Version: GnuPG v1.4.5 (Darwin)

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[PATCH, v2] gcc-4.5: added thumb2 build patch

[Enrico Scholz]

Fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43999 and is
required to build gcc for Thumb2 only architectures (e.g. Cortex-M3).

Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
---
 recipes/gcc/gcc-4.5.inc                |    3 ++-
 recipes/gcc/gcc-4.5/thumb2-build.patch |   16 ++++++++++++++++
 2 files changed, 18 insertions(+), 1 deletions(-)
 create mode 100644 recipes/gcc/gcc-4.5/thumb2-build.patch

diff --git a/recipes/gcc/gcc-4.5.inc b/recipes/gcc/gcc-4.5.inc
index b630528..9ba2e22 100644
--- a/recipes/gcc/gcc-4.5.inc
+++ b/recipes/gcc/gcc-4.5.inc
@@ -8,7 +8,7 @@ DEPENDS = "mpfr gmp libmpc libelf"
 NATIVEDEPS = "mpfr-native gmp-native libmpc-native"
 
 
-INC_PR = "r31"
+INC_PR = "r32"
 
 SRCREV = "168622"
 PV = "4.5"
@@ -166,6 +166,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH} \
 #	   file://linaro/gcc-4.5-linaro-r99457.patch \
 	   file://gcc-scalar-widening-pr45847.patch \
 	   file://gcc-arm-volatile-bitfield-fix.patch \
+	   file://thumb2-build.patch \
 	  "
 
 SRC_URI_append_mips64 = " file://mips64-nomultilib.patch "
diff --git a/recipes/gcc/gcc-4.5/thumb2-build.patch b/recipes/gcc/gcc-4.5/thumb2-build.patch
new file mode 100644
index 0000000..75e765e
--- /dev/null
+++ b/recipes/gcc/gcc-4.5/thumb2-build.patch
@@ -0,0 +1,16 @@
+Fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43999
+
+Patch was taken from comment #3 (Jing Yu) there; the patch attached
+to the named bugreport is wrong.
+
+Index: gcc/config/arm/lib1funcs.asm
+===================================================================
+--- a/gcc/config/arm/lib1funcs.asm	(revision 163231)
++++ b/gcc/config/arm/lib1funcs.asm	(working copy)
+@@ -642,5 +642,5 @@
+ 	cmp	\dividend, #0			@ Early termination?
+-	do_it	hs, t
++	do_it	ne, t
+ 	movnes	\curbit,   \curbit,  lsr #4	@ No, any more bits to do?
+ 	movne	\divisor,  \divisor, lsr #4
+ 	bne	1b
-- 
1.7.4

Re: [PATCH, v2] gcc-4.5: added thumb2 build patch

[Khem Raj]

On Mon, Feb 7, 2011 at 9:25 AM, Enrico Scholz
<enrico.scholz@sigma-chemnitz.de> wrote:
> Fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43999 and is
> required to build gcc for Thumb2 only architectures (e.g. Cortex-M3).
>
> Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
> ---
>  recipes/gcc/gcc-4.5.inc                |    3 ++-
>  recipes/gcc/gcc-4.5/thumb2-build.patch |   16 ++++++++++++++++
>  2 files changed, 18 insertions(+), 1 deletions(-)
>  create mode 100644 recipes/gcc/gcc-4.5/thumb2-build.patch
>
> diff --git a/recipes/gcc/gcc-4.5.inc b/recipes/gcc/gcc-4.5.inc
> index b630528..9ba2e22 100644
> --- a/recipes/gcc/gcc-4.5.inc
> +++ b/recipes/gcc/gcc-4.5.inc
> @@ -8,7 +8,7 @@ DEPENDS = "mpfr gmp libmpc libelf"
>  NATIVEDEPS = "mpfr-native gmp-native libmpc-native"
>
>
> -INC_PR = "r31"
> +INC_PR = "r32"
>
>  SRCREV = "168622"
>  PV = "4.5"
> @@ -166,6 +166,7 @@ SRC_URI = "svn://gcc.gnu.org/svn/gcc/branches;module=${BRANCH} \
>  #         file://linaro/gcc-4.5-linaro-r99457.patch \
>           file://gcc-scalar-widening-pr45847.patch \
>           file://gcc-arm-volatile-bitfield-fix.patch \
> +          file://thumb2-build.patch \
>          "
>
>  SRC_URI_append_mips64 = " file://mips64-nomultilib.patch "
> diff --git a/recipes/gcc/gcc-4.5/thumb2-build.patch b/recipes/gcc/gcc-4.5/thumb2-build.patch
> new file mode 100644
> index 0000000..75e765e
> --- /dev/null
> +++ b/recipes/gcc/gcc-4.5/thumb2-build.patch
> @@ -0,0 +1,16 @@
> +Fix for http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43999
> +
> +Patch was taken from comment #3 (Jing Yu) there; the patch attached
> +to the named bugreport is wrong.
> +
> +Index: gcc/config/arm/lib1funcs.asm
> +===================================================================
> +--- a/gcc/config/arm/lib1funcs.asm     (revision 163231)
> ++++ b/gcc/config/arm/lib1funcs.asm     (working copy)
> +@@ -642,5 +642,5 @@
> +       cmp     \dividend, #0                   @ Early termination?
> +-      do_it   hs, t
> ++      do_it   ne, t

This needs to be tested on all arms before being taken in. I would
suggest test it
on beagleboard and qemuarm that will cover other two case arm/thumb1
if gcc testsuites
show no new regressions then we can consider it.

> +       movnes  \curbit,   \curbit,  lsr #4     @ No, any more bits to do?
> +       movne   \divisor,  \divisor, lsr #4
> +       bne     1b
> --
> 1.7.4
>
>
> _______________________________________________
> Openembedded-devel mailing list
> Openembedded-devel@lists.openembedded.org
> http://lists.linuxtogo.org/cgi-bin/mailman/listinfo/openembedded-devel
>

Re: [PATCH] cortex-m3: adjusted target cflags

[Khem Raj]

On Mon, Feb 7, 2011 at 7:53 AM, Enrico Scholz
<enrico.scholz@sigma-chemnitz.de> wrote:
> Explicit '-mthumb' is required because Cortex-M3 does not support ARM
> instructions and actual flags cause gcc to fail with 'error: target CPU
> does not support ARM mode'.
>
> The '-mcpu=cortex-m3' is shorter than '-march=armv7-m -mtune=cortex-m3'
> and enables workarounds like '-mfix-cortex-m3-ldrd'.

Does -mcpu=cortex-m3 also cause gcc to tune for cortex-m3 ?

>
> Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
> ---
>  conf/machine/include/tune-cortexm3.inc |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/conf/machine/include/tune-cortexm3.inc b/conf/machine/include/tune-cortexm3.inc
> index 6da9aee..a66a33c 100644
> --- a/conf/machine/include/tune-cortexm3.inc
> +++ b/conf/machine/include/tune-cortexm3.inc
> @@ -1,4 +1,4 @@
>  # valid options for -march: `armv7', `armv7-m'
> -TARGET_CC_ARCH = "-march=armv7-m -mtune=cortex-m3 -mfpu=vfp -mfloat-abi=softfp"
> +TARGET_CC_ARCH = "-mthumb -mcpu=cortex-m3 -mfpu=vfp -mfloat-abi=softfp"
>  FEED_ARCH = "armv7"
>  BASE_PACKAGE_ARCH = "armv7"
> --
> 1.7.4
>
>
> _______________________________________________
> Openembedded-devel mailing list
> Openembedded-devel@lists.openembedded.org
> http://lists.linuxtogo.org/cgi-bin/mailman/listinfo/openembedded-devel
>

Re: [PATCH] cortex-m3: adjusted target cflags

[Mark Hatle]

On 2/7/11 1:33 PM, Khem Raj wrote:
> On Mon, Feb 7, 2011 at 7:53 AM, Enrico Scholz
> <enrico.scholz@sigma-chemnitz.de> wrote:
>> Explicit '-mthumb' is required because Cortex-M3 does not support ARM
>> instructions and actual flags cause gcc to fail with 'error: target CPU
>> does not support ARM mode'.
>>
>> The '-mcpu=cortex-m3' is shorter than '-march=armv7-m -mtune=cortex-m3'
>> and enables workarounds like '-mfix-cortex-m3-ldrd'.
> 
> Does -mcpu=cortex-m3 also cause gcc to tune for cortex-m3 ?

-mcpu=cortex-m3 is equivalent to -march=cortex-m3 -mtune=cortex-m3

So in this instance, it will have a side effect of potentially changing the
available set of instructions.. The existing command says the only available
instructions are those defined as "armv7-m", but I want to tune the instruction
scheduler for execution on "cortex-m3".

(I'm not an ARM expert, so I'm not sure what is reasonable in this case.. but
the arguments do have slightly different meanings.)

--Mark

>>
>> Signed-off-by: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
>> ---
>>  conf/machine/include/tune-cortexm3.inc |    2 +-
>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/conf/machine/include/tune-cortexm3.inc b/conf/machine/include/tune-cortexm3.inc
>> index 6da9aee..a66a33c 100644
>> --- a/conf/machine/include/tune-cortexm3.inc
>> +++ b/conf/machine/include/tune-cortexm3.inc
>> @@ -1,4 +1,4 @@
>>  # valid options for -march: `armv7', `armv7-m'
>> -TARGET_CC_ARCH = "-march=armv7-m -mtune=cortex-m3 -mfpu=vfp -mfloat-abi=softfp"
>> +TARGET_CC_ARCH = "-mthumb -mcpu=cortex-m3 -mfpu=vfp -mfloat-abi=softfp"
>>  FEED_ARCH = "armv7"
>>  BASE_PACKAGE_ARCH = "armv7"
>> --
>> 1.7.4
>>
>>
>> _______________________________________________
>> Openembedded-devel mailing list
>> Openembedded-devel@lists.openembedded.org
>> http://lists.linuxtogo.org/cgi-bin/mailman/listinfo/openembedded-devel
>>
> 
> _______________________________________________
> Openembedded-devel mailing list
> Openembedded-devel@lists.openembedded.org
> http://lists.linuxtogo.org/cgi-bin/mailman/listinfo/openembedded-devel

Re: [PATCH] cortex-m3: adjusted target cflags

[Khem Raj]

On Mon, Feb 7, 2011 at 11:39 AM, Mark Hatle <mark.hatle@windriver.com> wrote:
> On 2/7/11 1:33 PM, Khem Raj wrote:
>> On Mon, Feb 7, 2011 at 7:53 AM, Enrico Scholz
>> <enrico.scholz@sigma-chemnitz.de> wrote:
>>> Explicit '-mthumb' is required because Cortex-M3 does not support ARM
>>> instructions and actual flags cause gcc to fail with 'error: target CPU
>>> does not support ARM mode'.
>>>
>>> The '-mcpu=cortex-m3' is shorter than '-march=armv7-m -mtune=cortex-m3'
>>> and enables workarounds like '-mfix-cortex-m3-ldrd'.
>>
>> Does -mcpu=cortex-m3 also cause gcc to tune for cortex-m3 ?
>
> -mcpu=cortex-m3 is equivalent to -march=cortex-m3 -mtune=cortex-m3

is -march=cortex-m3 valid even ? my question was if we select armv7-m
using -march
then gcc knows stuff like oh this arch has a hardware div instruction
but now if we
use -mcpu will it still do it.

Re: [PATCH] cortex-m3: adjusted target cflags

[Mark Hatle]

On 2/7/11 2:19 PM, Khem Raj wrote:
> On Mon, Feb 7, 2011 at 11:39 AM, Mark Hatle <mark.hatle@windriver.com> wrote:
>> On 2/7/11 1:33 PM, Khem Raj wrote:
>>> On Mon, Feb 7, 2011 at 7:53 AM, Enrico Scholz
>>> <enrico.scholz@sigma-chemnitz.de> wrote:
>>>> Explicit '-mthumb' is required because Cortex-M3 does not support ARM
>>>> instructions and actual flags cause gcc to fail with 'error: target CPU
>>>> does not support ARM mode'.
>>>>
>>>> The '-mcpu=cortex-m3' is shorter than '-march=armv7-m -mtune=cortex-m3'
>>>> and enables workarounds like '-mfix-cortex-m3-ldrd'.
>>>
>>> Does -mcpu=cortex-m3 also cause gcc to tune for cortex-m3 ?
>>
>> -mcpu=cortex-m3 is equivalent to -march=cortex-m3 -mtune=cortex-m3
> 
> is -march=cortex-m3 valid even ? my question was if we select armv7-m
> using -march
> then gcc knows stuff like oh this arch has a hardware div instruction
> but now if we
> use -mcpu will it still do it.

You would have to look in the source and see if -mcpu=cortex-m3 is an "alias"
for anything or simply uses the default logic of cpu == march && mtune..

(FYI, last time I looked at how this worked was a year or so ago.. so if the way
GCC processes options has changed, then I'm wrong..  but it's worth looking at..
 I was scolded many times by GCC developers that -mcpu= is not the same as
specifically setting the arch and tune.)

Usually you use march & mtune when you are trying to make a set of binaries that
is capable of running on multiple cores in the same family.  I see it used the
most of IA and Power systems myself.

--Mark

Re: [PATCH] cortex-m3: adjusted target cflags

[Enrico Scholz]

Khem Raj <raj.khem@gmail.com> writes:

>> The '-mcpu=cortex-m3' is shorter than '-march=armv7-m -mtune=cortex-m3'
>> and enables workarounds like '-mfix-cortex-m3-ldrd'.
>
> Does -mcpu=cortex-m3 also cause gcc to tune for cortex-m3 ?

Yes; logic in gcc/config/arm/arm.c is:

|    if (i == ARM_OPT_SET_CPU || i == ARM_OPT_SET_TUNE)
|      arm_tune = (enum processor_type) (sel - ptr->processors);
|
|    if (i == ARM_OPT_SET_ARCH)
|      target_arch_cpu = sel->core;
|
|    if (i == ARM_OPT_SET_CPU)
|      selected_cpu = (enum processor_type) (sel - ptr->processors);

'-mcpu' causes the highest optimization level (both for the used instruction
set (--> '-march') and the "soft" optimizations (--> '-mcpu')).



Enrico

Re: [PATCH] cortex-m3: adjusted target cflags

[Khem Raj]

On Mon, Feb 7, 2011 at 12:59 PM, Enrico Scholz
<enrico.scholz@sigma-chemnitz.de> wrote:
> Khem Raj <raj.khem@gmail.com> writes:
>
>>> The '-mcpu=cortex-m3' is shorter than '-march=armv7-m -mtune=cortex-m3'
>>> and enables workarounds like '-mfix-cortex-m3-ldrd'.
>>
>> Does -mcpu=cortex-m3 also cause gcc to tune for cortex-m3 ?
>
> Yes; logic in gcc/config/arm/arm.c is:
>
> |    if (i == ARM_OPT_SET_CPU || i == ARM_OPT_SET_TUNE)
> |      arm_tune = (enum processor_type) (sel - ptr->processors);
> |
> |    if (i == ARM_OPT_SET_ARCH)
> |      target_arch_cpu = sel->core;
> |
> |    if (i == ARM_OPT_SET_CPU)
> |      selected_cpu = (enum processor_type) (sel - ptr->processors);
>
> '-mcpu' causes the highest optimization level (both for the used instruction
> set (--> '-march') and the "soft" optimizations (--> '-mcpu')).

OK that seems better. Can you check what does gcc emits in an assembly file
when using -mcpu=cortex-m3 in your case. If it emits sdiv instruction or not

int foo (long a, long b)
{
        return a/b;
}


Acked-by: Khem Raj <raj.khem@gmail.com>

>
>
>
> Enrico
>
> _______________________________________________
> Openembedded-devel mailing list
> Openembedded-devel@lists.openembedded.org
> http://lists.linuxtogo.org/cgi-bin/mailman/listinfo/openembedded-devel
>

Re: [PATCH] cortex-m3: adjusted target cflags

[Enrico Scholz]

Khem Raj <raj.khem@gmail.com> writes:

> Can you check what does gcc emits in an assembly file when using
> -mcpu=cortex-m3 in your case. If it emits sdiv instruction or not
>
> int foo (long a, long b)
> {
>         return a/b;
> }

$ arm-linux-uclibceabi-gcc -mthumb -mcpu=cortex-m3 -mfpu=vfp -mfloat-abi=softfp -O1 -c x.c
$ arm-linux-uclibceabi-objdump -d x.o
00000000 <foo>:
   0:   fb90 f0f1       sdiv    r0, r0, r1
   4:   4770            bx      lr
   6:   bf00            nop



Enrico

Re: [PATCH] cortex-m3: adjusted target cflags

[Khem Raj]

On Mon, Feb 7, 2011 at 2:27 PM, Enrico Scholz
<enrico.scholz@sigma-chemnitz.de> wrote:
> Khem Raj <raj.khem@gmail.com> writes:
>
>> Can you check what does gcc emits in an assembly file when using
>> -mcpu=cortex-m3 in your case. If it emits sdiv instruction or not
>>
>> int foo (long a, long b)
>> {
>>         return a/b;
>> }
>
> $ arm-linux-uclibceabi-gcc -mthumb -mcpu=cortex-m3 -mfpu=vfp -mfloat-abi=softfp -O1 -c x.c
> $ arm-linux-uclibceabi-objdump -d x.o
> 00000000 <foo>:
>   0:   fb90 f0f1       sdiv    r0, r0, r1
>   4:   4770            bx      lr
>   6:   bf00            nop
>
>

thx

>
> Enrico
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