All of lore.kernel.org
 help / color / mirror / Atom feed
* Re: [PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider
       [not found] <1299152316.2615.91.camel@deskari>
@ 2011-03-03 13:16 ` Tomi Valkeinen
  2011-03-03 15:34   ` Raghuveer Murthy
  0 siblings, 1 reply; 3+ messages in thread
From: Tomi Valkeinen @ 2011-03-03 13:16 UTC (permalink / raw)
  To: Raghuveer Murthy; +Cc: linux-omap

On Thu, 2011-03-03 at 15:25 +0530, Raghuveer Murthy wrote:
> OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
> registers to configure the pixel clock frequency, for the respective LCD 
> displays.
> 
> There is also DISPC_DIVISOR register, which by default has the ENABLE bit 
> set to zero, for backward compatibility mode. Hence the logical clock divider of
> DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
> of DISPC_DIVISOR1.LCD is 4.
> 
> If only the secondary LCD is enabled, at high pixel resolutions the core clk 
> lags behind the pixel clock, causing stair-step effect (diagonal lines with
> tearing) on the display.
> 
> Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set 
> independently and exclusively in DISPC_DIVISOR.LCD.

I think this patch set is ok. However, it doesn't apply with the latest
master branch from DSS tree, some quite trivial conflicts with dss
features. Can you rebase and post it?

Also, please send patches to my ti.com address, not iki.fi address.

 Tomi



^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider
  2011-03-03 13:16 ` [PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider Tomi Valkeinen
@ 2011-03-03 15:34   ` Raghuveer Murthy
  0 siblings, 0 replies; 3+ messages in thread
From: Raghuveer Murthy @ 2011-03-03 15:34 UTC (permalink / raw)
  To: Valkeinen, Tomi; +Cc: Murthy, Raghuveer, linux-omap

On Thursday 03 March 2011 06:46 PM, Valkeinen, Tomi wrote:
> On Thu, 2011-03-03 at 15:25 +0530, Raghuveer Murthy wrote:
>> OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
>> registers to configure the pixel clock frequency, for the respective LCD
>> displays.
>>
>> There is also DISPC_DIVISOR register, which by default has the ENABLE bit
>> set to zero, for backward compatibility mode. Hence the logical clock divider of
>> DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
>> of DISPC_DIVISOR1.LCD is 4.
>>
>> If only the secondary LCD is enabled, at high pixel resolutions the core clk
>> lags behind the pixel clock, causing stair-step effect (diagonal lines with
>> tearing) on the display.
>>
>> Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set
>> independently and exclusively in DISPC_DIVISOR.LCD.
>
> I think this patch set is ok. However, it doesn't apply with the latest
> master branch from DSS tree, some quite trivial conflicts with dss
> features. Can you rebase and post it?
>
> Also, please send patches to my ti.com address, not iki.fi address.
>
>   Tomi
>
>
Hi Tomi,

Resent the after re-basing.

Regards,
Raghuveer


^ permalink raw reply	[flat|nested] 3+ messages in thread

* [PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider
@ 2011-03-03  9:55 Raghuveer Murthy
  0 siblings, 0 replies; 3+ messages in thread
From: Raghuveer Murthy @ 2011-03-03  9:55 UTC (permalink / raw)
  To: tomba; +Cc: linux-omap

OMAP4 has 2 LCD channels and corresponding DISPC_DIVISOR1 and DISPC_DIVISOR2
registers to configure the pixel clock frequency, for the respective LCD 
displays.

There is also DISPC_DIVISOR register, which by default has the ENABLE bit 
set to zero, for backward compatibility mode. Hence the logical clock divider of
DISPC_DIVISOR1.LCD, gets used for core func clk configuration. The default value
of DISPC_DIVISOR1.LCD is 4.

If only the secondary LCD is enabled, at high pixel resolutions the core clk 
lags behind the pixel clock, causing stair-step effect (diagonal lines with
tearing) on the display.

Hence DISPC_DIVISOR.ENABLE is set to 1, and the core functional clock is set 
independently and exclusively in DISPC_DIVISOR.LCD.

- Added the above as dss_features

-----------------------------------------------------
History
-------
Changes from previous version (v1)
- Fixed comments from Tomi Valkeinen <tomi.valkeinen@ti.com>

Base
----
url = git://gitorious.org/linux-omap-dss2/linux.git
branch "master"
commit 1e0f79f1066aba3cfcaa45a0298bb24ba7bf864d 

-----------------------------------------------------
Raghuveer Murthy (3):
  OMAP: DSS2: Adding dss_features for independent core clk divider
  OMAP: DSS2: Renaming register macro DISPC_DIVISOR(ch)
  OMAP4: DSS2: Using dss_features to set independent core clock divider

 drivers/video/omap2/dss/dispc.c        |   51 +++++++++++++++++++++++--------
 drivers/video/omap2/dss/dss_features.c |    2 +-
 drivers/video/omap2/dss/dss_features.h |    2 +
 3 files changed, 41 insertions(+), 14 deletions(-)


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2011-03-03 15:34 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <1299152316.2615.91.camel@deskari>
2011-03-03 13:16 ` [PATCH v1 0/3] OMAP: DSS2: Fix for DISPC core functional clock divider Tomi Valkeinen
2011-03-03 15:34   ` Raghuveer Murthy
2011-03-03  9:55 Raghuveer Murthy

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.