* [PATCH 2/2] powerpc: Remove Xilinx PPC405/PPC440 support
@ 2020-03-27 12:12 ` Michal Simek
0 siblings, 0 replies; 104+ messages in thread
From: Michal Simek @ 2020-03-27 12:12 UTC (permalink / raw)
To: linux-kernel, monstr, michal.simek, git, sfr, marc.zyngier
Cc: Kate Stewart, Mark Rutland, Desnes A. Nunes do Rosario,
Geert Uytterhoeven, linux-doc, linux-fbdev, dri-devel,
Richard Fontana, Paul Mackerras, Miquel Raynal,
Mauro Carvalho Chehab, Sasha Levin, Jonathan Corbet,
Michael Ellerman, Masahiro Yamada, YueHaibing,
Krzysztof Kozlowski, linux-arm-kernel, Leonardo Bras,
Matt Porter, devicetree, Andrew Donnellan, Arnd Bergmann,
Bartlomiej Zolnierkiewicz, Alistair Popple, linuxppc-dev,
Nicholas Piggin, Alexios Zavras, Rob Herring, Jonathan Cameron,
Thomas Gleixner, Andy Shevchenko, Allison Randal,
Christophe Leroy, Wei Hu, Greg Kroah-Hartman, Nick Desaulniers,
Armijn Hemel, Enrico Weigelt, David S. Miller,
Thiago Jung Bauermann
The latest Xilinx design tools called ISE and EDK has been released in
October 2013. New tool doesn't support any PPC405/PPC440 new designs.
These platforms are no longer supported and tested.
PowerPC 405/440 port is orphan from 2013 by
commit cdeb89943bfc ("MAINTAINERS: Fix incorrect status tag") and
commit 19624236cce1 ("MAINTAINERS: Update Grant's email address and maintainership")
that's why it is time to remove the support fot these platforms.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Documentation/devicetree/bindings/xilinx.txt | 143 ------
Documentation/powerpc/bootwrapper.rst | 28 +-
MAINTAINERS | 6 -
arch/powerpc/Kconfig.debug | 2 +-
arch/powerpc/boot/Makefile | 7 +-
arch/powerpc/boot/dts/Makefile | 1 -
arch/powerpc/boot/dts/virtex440-ml507.dts | 406 ----------------
arch/powerpc/boot/dts/virtex440-ml510.dts | 466 -------------------
arch/powerpc/boot/ops.h | 1 -
arch/powerpc/boot/serial.c | 5 -
arch/powerpc/boot/uartlite.c | 79 ----
arch/powerpc/boot/virtex.c | 97 ----
arch/powerpc/boot/virtex405-head.S | 31 --
arch/powerpc/boot/wrapper | 8 -
arch/powerpc/configs/40x/virtex_defconfig | 75 ---
arch/powerpc/configs/44x/virtex5_defconfig | 74 ---
arch/powerpc/configs/ppc40x_defconfig | 8 -
arch/powerpc/configs/ppc44x_defconfig | 8 -
arch/powerpc/include/asm/xilinx_intc.h | 16 -
arch/powerpc/include/asm/xilinx_pci.h | 21 -
arch/powerpc/kernel/cputable.c | 39 --
arch/powerpc/platforms/40x/Kconfig | 31 --
arch/powerpc/platforms/40x/Makefile | 1 -
arch/powerpc/platforms/40x/virtex.c | 54 ---
arch/powerpc/platforms/44x/Kconfig | 37 --
arch/powerpc/platforms/44x/Makefile | 2 -
arch/powerpc/platforms/44x/virtex.c | 60 ---
arch/powerpc/platforms/44x/virtex_ml510.c | 30 --
arch/powerpc/platforms/Kconfig | 4 -
arch/powerpc/sysdev/Makefile | 2 -
arch/powerpc/sysdev/xilinx_intc.c | 88 ----
arch/powerpc/sysdev/xilinx_pci.c | 132 ------
arch/powerpc/xmon/ppc-dis.c | 6 -
arch/powerpc/xmon/ppc-opc.c | 23 -
arch/powerpc/xmon/ppc.h | 5 -
drivers/char/Kconfig | 2 +-
drivers/video/fbdev/Kconfig | 2 +-
37 files changed, 7 insertions(+), 1993 deletions(-)
delete mode 100644 arch/powerpc/boot/dts/virtex440-ml507.dts
delete mode 100644 arch/powerpc/boot/dts/virtex440-ml510.dts
delete mode 100644 arch/powerpc/boot/uartlite.c
delete mode 100644 arch/powerpc/boot/virtex.c
delete mode 100644 arch/powerpc/boot/virtex405-head.S
delete mode 100644 arch/powerpc/configs/40x/virtex_defconfig
delete mode 100644 arch/powerpc/configs/44x/virtex5_defconfig
delete mode 100644 arch/powerpc/include/asm/xilinx_intc.h
delete mode 100644 arch/powerpc/include/asm/xilinx_pci.h
delete mode 100644 arch/powerpc/platforms/40x/virtex.c
delete mode 100644 arch/powerpc/platforms/44x/virtex.c
delete mode 100644 arch/powerpc/platforms/44x/virtex_ml510.c
delete mode 100644 arch/powerpc/sysdev/xilinx_intc.c
delete mode 100644 arch/powerpc/sysdev/xilinx_pci.c
diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt
index d058ace29345..28199b31fe5e 100644
--- a/Documentation/devicetree/bindings/xilinx.txt
+++ b/Documentation/devicetree/bindings/xilinx.txt
@@ -86,149 +86,6 @@
xlnx,use-parity = <0>;
};
- Some IP cores actually implement 2 or more logical devices. In
- this case, the device should still describe the whole IP core with
- a single node and add a child node for each logical device. The
- ranges property can be used to translate from parent IP-core to the
- registers of each device. In addition, the parent node should be
- compatible with the bus type 'xlnx,compound', and should contain
- #address-cells and #size-cells, as with any other bus. (Note: this
- makes the assumption that both logical devices have the same bus
- binding. If this is not true, then separate nodes should be used
- for each logical device). The 'cell-index' property can be used to
- enumerate logical devices within an IP core. For example, the
- following is the system.mhs entry for the dual ps2 controller found
- on the ml403 reference design.
-
- BEGIN opb_ps2_dual_ref
- PARAMETER INSTANCE = opb_ps2_dual_ref_0
- PARAMETER HW_VER = 1.00.a
- PARAMETER C_BASEADDR = 0xA9000000
- PARAMETER C_HIGHADDR = 0xA9001FFF
- BUS_INTERFACE SOPB = opb_v20_0
- PORT Sys_Intr1 = ps2_1_intr
- PORT Sys_Intr2 = ps2_2_intr
- PORT Clkin1 = ps2_clk_rx_1
- PORT Clkin2 = ps2_clk_rx_2
- PORT Clkpd1 = ps2_clk_tx_1
- PORT Clkpd2 = ps2_clk_tx_2
- PORT Rx1 = ps2_d_rx_1
- PORT Rx2 = ps2_d_rx_2
- PORT Txpd1 = ps2_d_tx_1
- PORT Txpd2 = ps2_d_tx_2
- END
-
- It would result in the following device tree nodes:
-
- opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ranges = <0 a9000000 2000>;
- // If this device had extra parameters, then they would
- // go here.
- ps2@0 {
- compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
- reg = <0 40>;
- interrupt-parent = <&opb_intc_0>;
- interrupts = <3 0>;
- cell-index = <0>;
- };
- ps2@1000 {
- compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
- reg = <1000 40>;
- interrupt-parent = <&opb_intc_0>;
- interrupts = <3 0>;
- cell-index = <0>;
- };
- };
-
- Also, the system.mhs file defines bus attachments from the processor
- to the devices. The device tree structure should reflect the bus
- attachments. Again an example; this system.mhs fragment:
-
- BEGIN ppc405_virtex4
- PARAMETER INSTANCE = ppc405_0
- PARAMETER HW_VER = 1.01.a
- BUS_INTERFACE DPLB = plb_v34_0
- BUS_INTERFACE IPLB = plb_v34_0
- END
-
- BEGIN opb_intc
- PARAMETER INSTANCE = opb_intc_0
- PARAMETER HW_VER = 1.00.c
- PARAMETER C_BASEADDR = 0xD1000FC0
- PARAMETER C_HIGHADDR = 0xD1000FDF
- BUS_INTERFACE SOPB = opb_v20_0
- END
-
- BEGIN opb_uart16550
- PARAMETER INSTANCE = opb_uart16550_0
- PARAMETER HW_VER = 1.00.d
- PARAMETER C_BASEADDR = 0xa0000000
- PARAMETER C_HIGHADDR = 0xa0001FFF
- BUS_INTERFACE SOPB = opb_v20_0
- END
-
- BEGIN plb_v34
- PARAMETER INSTANCE = plb_v34_0
- PARAMETER HW_VER = 1.02.a
- END
-
- BEGIN plb_bram_if_cntlr
- PARAMETER INSTANCE = plb_bram_if_cntlr_0
- PARAMETER HW_VER = 1.00.b
- PARAMETER C_BASEADDR = 0xFFFF0000
- PARAMETER C_HIGHADDR = 0xFFFFFFFF
- BUS_INTERFACE SPLB = plb_v34_0
- END
-
- BEGIN plb2opb_bridge
- PARAMETER INSTANCE = plb2opb_bridge_0
- PARAMETER HW_VER = 1.01.a
- PARAMETER C_RNG0_BASEADDR = 0x20000000
- PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
- PARAMETER C_RNG1_BASEADDR = 0x60000000
- PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
- PARAMETER C_RNG2_BASEADDR = 0x80000000
- PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
- PARAMETER C_RNG3_BASEADDR = 0xC0000000
- PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
- BUS_INTERFACE SPLB = plb_v34_0
- BUS_INTERFACE MOPB = opb_v20_0
- END
-
- Gives this device tree (some properties removed for clarity):
-
- plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v34-1.02.a";
- device_type = "ibm,plb";
- ranges; // 1:1 translation
-
- plb_bram_if_cntrl_0: bram@ffff0000 {
- reg = <ffff0000 10000>;
- }
-
- opb@20000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <20000000 20000000 20000000
- 60000000 60000000 20000000
- 80000000 80000000 40000000
- c0000000 c0000000 20000000>;
-
- opb_uart16550_0: serial@a0000000 {
- reg = <a00000000 2000>;
- };
-
- opb_intc_0: interrupt-controller@d1000fc0 {
- reg = <d1000fc0 20>;
- };
- };
- };
-
That covers the general approach to binding xilinx IP cores into the
device tree. The following are bindings for specific devices:
diff --git a/Documentation/powerpc/bootwrapper.rst b/Documentation/powerpc/bootwrapper.rst
index a6292afba573..cdfa2bc8425f 100644
--- a/Documentation/powerpc/bootwrapper.rst
+++ b/Documentation/powerpc/bootwrapper.rst
@@ -70,28 +70,6 @@ Currently, the following image format targets exist:
kernel with this image type and it depends entirely on
the embedded device tree for all information.
- The simpleImage is useful for booting systems with
- an unknown firmware interface or for booting from
- a debugger when no firmware is present (such as on
- the Xilinx Virtex platform). The only assumption that
- simpleImage makes is that RAM is correctly initialized
- and that the MMU is either off or has RAM mapped to
- base address 0.
-
- simpleImage also supports inserting special platform
- specific initialization code to the start of the bootup
- sequence. The virtex405 platform uses this feature to
- ensure that the cache is invalidated before caching
- is enabled. Platform specific initialization code is
- added as part of the wrapper script and is keyed on
- the image target name. For example, all
- simpleImage.virtex405-* targets will add the
- virtex405-head.S initialization code (This also means
- that the dts file for virtex405 targets should be
- named (virtex405-<board>.dts). Search the wrapper
- script for 'virtex405' and see the file
- arch/powerpc/boot/virtex405-head.S for details.
-
treeImage.%; Image format for used with OpenBIOS firmware found
on some ppc4xx hardware. This image embeds a device
tree blob inside the image.
@@ -116,10 +94,8 @@ Image types which embed a device tree blob (simpleImage, dtbImage, treeImage,
and cuImage) all generate the device tree blob from a file in the
arch/powerpc/boot/dts/ directory. The Makefile selects the correct device
tree source based on the name of the target. Therefore, if the kernel is
-built with 'make treeImage.walnut simpleImage.virtex405-ml403', then the
-build system will use arch/powerpc/boot/dts/walnut.dts to build
-treeImage.walnut and arch/powerpc/boot/dts/virtex405-ml403.dts to build
-the simpleImage.virtex405-ml403.
+built with 'make treeImage.walnut', then the build system will use
+arch/powerpc/boot/dts/walnut.dts to build treeImage.walnut.
Two special targets called 'zImage' and 'zImage.initrd' also exist. These
targets build all the default images as selected by the kernel configuration.
diff --git a/MAINTAINERS b/MAINTAINERS
index a0d86490c2c6..842a9bbc2013 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9668,12 +9668,6 @@ L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: arch/powerpc/platforms/8xx/
-LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
-L: linuxppc-dev@lists.ozlabs.org
-S: Orphan
-F: arch/powerpc/*/*virtex*
-F: arch/powerpc/*/*/*virtex*
-
LINUX FOR POWERPC PA SEMI PWRFICIENT
L: linuxppc-dev@lists.ozlabs.org
S: Orphan
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 0b063830eea8..b88900f4832f 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -230,7 +230,7 @@ config PPC_EARLY_DEBUG_40x
help
Select this to enable early debugging for IBM 40x chips via the
inbuilt serial port. This works on chips with a 16550 compatible
- UART. Xilinx chips with uartlite cannot use this option.
+ UART.
config PPC_EARLY_DEBUG_CPM
bool "Early serial debugging for Freescale CPM-based serial ports"
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index c53a1b8bba8b..d8077b7071dd 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -79,7 +79,6 @@ $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
-$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
# The pre-boot decompressors pull in a lot of kernel headers and other source
# files. This creates a bit of a dependency headache since we need to copy
@@ -129,14 +128,12 @@ src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
-src-wlib-$(CONFIG_XILINX_VIRTEX) += uartlite.c
src-wlib-$(CONFIG_CPM) += cpm-serial.c
src-plat-y := of.c epapr.c
src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
treeboot-walnut.c cuboot-acadia.c \
- cuboot-kilauea.c simpleboot.c \
- virtex405-head.S virtex.c
+ cuboot-kilauea.c simpleboot.c
src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
cuboot-bamboo.c cuboot-sam440ep.c \
cuboot-sequoia.c cuboot-rainier.c \
@@ -144,7 +141,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
cuboot-warp.c cuboot-yosemite.c \
treeboot-iss4xx.c treeboot-currituck.c \
treeboot-akebono.c \
- simpleboot.c fixed-head.S virtex.c
+ simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
diff --git a/arch/powerpc/boot/dts/Makefile b/arch/powerpc/boot/dts/Makefile
index 1cbc0e4ce857..fb335d05aae8 100644
--- a/arch/powerpc/boot/dts/Makefile
+++ b/arch/powerpc/boot/dts/Makefile
@@ -4,4 +4,3 @@ subdir-y += fsl
dtstree := $(srctree)/$(src)
dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
-dtb-$(CONFIG_XILINX_VIRTEX440_GENERIC_BOARD) += virtex440-ml507.dtb virtex440-ml510.dtb
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
deleted file mode 100644
index 66f1c6312de6..000000000000
--- a/arch/powerpc/boot/dts/virtex440-ml507.dts
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * This file supports the Xilinx ML507 board with the 440 processor.
- * A reference design for the FPGA is provided at http://git.xilinx.com.
- *
- * (C) Copyright 2008 Xilinx, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
- * ---
- *
- * Device Tree Generator version: 1.1
- *
- * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
- *
- * XPS project directory: ml507_ppc440_emb_ref
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,virtex440";
- dcr-parent = <&ppc440_0>;
- model = "testing";
- DDR2_SDRAM: memory@0 {
- device_type = "memory";
- reg = < 0 0x10000000 >;
- } ;
- chosen {
- bootargs = "console=ttyS0 root=/dev/ram";
- stdout-path = &RS232_Uart_1;
- } ;
- cpus {
- #address-cells = <1>;
- #cpus = <1>;
- #size-cells = <0>;
- ppc440_0: cpu@0 {
- clock-frequency = <400000000>;
- compatible = "PowerPC,440", "ibm,ppc440";
- d-cache-line-size = <0x20>;
- d-cache-size = <0x8000>;
- dcr-access-method = "native";
- dcr-controller ;
- device_type = "cpu";
- i-cache-line-size = <0x20>;
- i-cache-size = <0x8000>;
- model = "PowerPC,440";
- reg = <0>;
- timebase-frequency = <400000000>;
- xlnx,apu-control = <1>;
- xlnx,apu-udi-0 = <0>;
- xlnx,apu-udi-1 = <0>;
- xlnx,apu-udi-10 = <0>;
- xlnx,apu-udi-11 = <0>;
- xlnx,apu-udi-12 = <0>;
- xlnx,apu-udi-13 = <0>;
- xlnx,apu-udi-14 = <0>;
- xlnx,apu-udi-15 = <0>;
- xlnx,apu-udi-2 = <0>;
- xlnx,apu-udi-3 = <0>;
- xlnx,apu-udi-4 = <0>;
- xlnx,apu-udi-5 = <0>;
- xlnx,apu-udi-6 = <0>;
- xlnx,apu-udi-7 = <0>;
- xlnx,apu-udi-8 = <0>;
- xlnx,apu-udi-9 = <0>;
- xlnx,dcr-autolock-enable = <1>;
- xlnx,dcu-rd-ld-cache-plb-prio = <0>;
- xlnx,dcu-rd-noncache-plb-prio = <0>;
- xlnx,dcu-rd-touch-plb-prio = <0>;
- xlnx,dcu-rd-urgent-plb-prio = <0>;
- xlnx,dcu-wr-flush-plb-prio = <0>;
- xlnx,dcu-wr-store-plb-prio = <0>;
- xlnx,dcu-wr-urgent-plb-prio = <0>;
- xlnx,dma0-control = <0>;
- xlnx,dma0-plb-prio = <0>;
- xlnx,dma0-rxchannelctrl = <0x1010000>;
- xlnx,dma0-rxirqtimer = <0x3ff>;
- xlnx,dma0-txchannelctrl = <0x1010000>;
- xlnx,dma0-txirqtimer = <0x3ff>;
- xlnx,dma1-control = <0>;
- xlnx,dma1-plb-prio = <0>;
- xlnx,dma1-rxchannelctrl = <0x1010000>;
- xlnx,dma1-rxirqtimer = <0x3ff>;
- xlnx,dma1-txchannelctrl = <0x1010000>;
- xlnx,dma1-txirqtimer = <0x3ff>;
- xlnx,dma2-control = <0>;
- xlnx,dma2-plb-prio = <0>;
- xlnx,dma2-rxchannelctrl = <0x1010000>;
- xlnx,dma2-rxirqtimer = <0x3ff>;
- xlnx,dma2-txchannelctrl = <0x1010000>;
- xlnx,dma2-txirqtimer = <0x3ff>;
- xlnx,dma3-control = <0>;
- xlnx,dma3-plb-prio = <0>;
- xlnx,dma3-rxchannelctrl = <0x1010000>;
- xlnx,dma3-rxirqtimer = <0x3ff>;
- xlnx,dma3-txchannelctrl = <0x1010000>;
- xlnx,dma3-txirqtimer = <0x3ff>;
- xlnx,endian-reset = <0>;
- xlnx,generate-plb-timespecs = <1>;
- xlnx,icu-rd-fetch-plb-prio = <0>;
- xlnx,icu-rd-spec-plb-prio = <0>;
- xlnx,icu-rd-touch-plb-prio = <0>;
- xlnx,interconnect-imask = <0xffffffff>;
- xlnx,mplb-allow-lock-xfer = <1>;
- xlnx,mplb-arb-mode = <0>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-counter = <0x500>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-max-burst = <8>;
- xlnx,mplb-native-dwidth = <0x80>;
- xlnx,mplb-p2p = <0>;
- xlnx,mplb-prio-dcur = <2>;
- xlnx,mplb-prio-dcuw = <3>;
- xlnx,mplb-prio-icu = <4>;
- xlnx,mplb-prio-splb0 = <1>;
- xlnx,mplb-prio-splb1 = <0>;
- xlnx,mplb-read-pipe-enable = <1>;
- xlnx,mplb-sync-tattribute = <0>;
- xlnx,mplb-wdog-enable = <1>;
- xlnx,mplb-write-pipe-enable = <1>;
- xlnx,mplb-write-post-enable = <1>;
- xlnx,num-dma = <1>;
- xlnx,pir = <0xf>;
- xlnx,ppc440mc-addr-base = <0>;
- xlnx,ppc440mc-addr-high = <0xfffffff>;
- xlnx,ppc440mc-arb-mode = <0>;
- xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
- xlnx,ppc440mc-control = <0xf810008f>;
- xlnx,ppc440mc-max-burst = <8>;
- xlnx,ppc440mc-prio-dcur = <2>;
- xlnx,ppc440mc-prio-dcuw = <3>;
- xlnx,ppc440mc-prio-icu = <4>;
- xlnx,ppc440mc-prio-splb0 = <1>;
- xlnx,ppc440mc-prio-splb1 = <0>;
- xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
- xlnx,ppcdm-asyncmode = <0>;
- xlnx,ppcds-asyncmode = <0>;
- xlnx,user-reset = <0>;
- DMA0: sdma@80 {
- compatible = "xlnx,ll-dma-1.00.a";
- dcr-reg = < 0x80 0x11 >;
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 10 2 11 2 >;
- } ;
- } ;
- } ;
- plb_v46_0: plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
- ranges ;
- DIP_Switches_8Bit: gpio@81460000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 7 2 >;
- reg = < 0x81460000 0x10000 >;
- xlnx,all-inputs = <1>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <8>;
- xlnx,interrupt-present = <1>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- FLASH: flash@fc000000 {
- bank-width = <2>;
- compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
- reg = < 0xfc000000 0x2000000 >;
- xlnx,family = "virtex5";
- xlnx,include-datawidth-matching-0 = <0x1>;
- xlnx,include-datawidth-matching-1 = <0x0>;
- xlnx,include-datawidth-matching-2 = <0x0>;
- xlnx,include-datawidth-matching-3 = <0x0>;
- xlnx,include-negedge-ioregs = <0x0>;
- xlnx,include-plb-ipif = <0x1>;
- xlnx,include-wrbuf = <0x1>;
- xlnx,max-mem-width = <0x10>;
- xlnx,mch-native-dwidth = <0x20>;
- xlnx,mch-plb-clk-period-ps = <0x2710>;
- xlnx,mch-splb-awidth = <0x20>;
- xlnx,mch0-accessbuf-depth = <0x10>;
- xlnx,mch0-protocol = <0x0>;
- xlnx,mch0-rddatabuf-depth = <0x10>;
- xlnx,mch1-accessbuf-depth = <0x10>;
- xlnx,mch1-protocol = <0x0>;
- xlnx,mch1-rddatabuf-depth = <0x10>;
- xlnx,mch2-accessbuf-depth = <0x10>;
- xlnx,mch2-protocol = <0x0>;
- xlnx,mch2-rddatabuf-depth = <0x10>;
- xlnx,mch3-accessbuf-depth = <0x10>;
- xlnx,mch3-protocol = <0x0>;
- xlnx,mch3-rddatabuf-depth = <0x10>;
- xlnx,mem0-width = <0x10>;
- xlnx,mem1-width = <0x20>;
- xlnx,mem2-width = <0x20>;
- xlnx,mem3-width = <0x20>;
- xlnx,num-banks-mem = <0x1>;
- xlnx,num-channels = <0x2>;
- xlnx,priority-mode = <0x0>;
- xlnx,synch-mem-0 = <0x0>;
- xlnx,synch-mem-1 = <0x0>;
- xlnx,synch-mem-2 = <0x0>;
- xlnx,synch-mem-3 = <0x0>;
- xlnx,synch-pipedelay-0 = <0x2>;
- xlnx,synch-pipedelay-1 = <0x2>;
- xlnx,synch-pipedelay-2 = <0x2>;
- xlnx,synch-pipedelay-3 = <0x2>;
- xlnx,tavdv-ps-mem-0 = <0x1adb0>;
- xlnx,tavdv-ps-mem-1 = <0x3a98>;
- xlnx,tavdv-ps-mem-2 = <0x3a98>;
- xlnx,tavdv-ps-mem-3 = <0x3a98>;
- xlnx,tcedv-ps-mem-0 = <0x1adb0>;
- xlnx,tcedv-ps-mem-1 = <0x3a98>;
- xlnx,tcedv-ps-mem-2 = <0x3a98>;
- xlnx,tcedv-ps-mem-3 = <0x3a98>;
- xlnx,thzce-ps-mem-0 = <0x88b8>;
- xlnx,thzce-ps-mem-1 = <0x1b58>;
- xlnx,thzce-ps-mem-2 = <0x1b58>;
- xlnx,thzce-ps-mem-3 = <0x1b58>;
- xlnx,thzoe-ps-mem-0 = <0x1b58>;
- xlnx,thzoe-ps-mem-1 = <0x1b58>;
- xlnx,thzoe-ps-mem-2 = <0x1b58>;
- xlnx,thzoe-ps-mem-3 = <0x1b58>;
- xlnx,tlzwe-ps-mem-0 = <0x88b8>;
- xlnx,tlzwe-ps-mem-1 = <0x0>;
- xlnx,tlzwe-ps-mem-2 = <0x0>;
- xlnx,tlzwe-ps-mem-3 = <0x0>;
- xlnx,twc-ps-mem-0 = <0x2af8>;
- xlnx,twc-ps-mem-1 = <0x3a98>;
- xlnx,twc-ps-mem-2 = <0x3a98>;
- xlnx,twc-ps-mem-3 = <0x3a98>;
- xlnx,twp-ps-mem-0 = <0x11170>;
- xlnx,twp-ps-mem-1 = <0x2ee0>;
- xlnx,twp-ps-mem-2 = <0x2ee0>;
- xlnx,twp-ps-mem-3 = <0x2ee0>;
- xlnx,xcl0-linesize = <0x4>;
- xlnx,xcl0-writexfer = <0x1>;
- xlnx,xcl1-linesize = <0x4>;
- xlnx,xcl1-writexfer = <0x1>;
- xlnx,xcl2-linesize = <0x4>;
- xlnx,xcl2-writexfer = <0x1>;
- xlnx,xcl3-linesize = <0x4>;
- xlnx,xcl3-writexfer = <0x1>;
- } ;
- Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ethernet@81c00000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "xlnx,xps-ll-temac-1.01.b";
- device_type = "network";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 5 2 >;
- llink-connected = <&DMA0>;
- local-mac-address = [ 02 00 00 00 00 00 ];
- reg = < 0x81c00000 0x40 >;
- xlnx,bus2core-clk-ratio = <1>;
- xlnx,phy-type = <1>;
- xlnx,phyaddr = <1>;
- xlnx,rxcsum = <1>;
- xlnx,rxfifo = <0x1000>;
- xlnx,temac-type = <0>;
- xlnx,txcsum = <1>;
- xlnx,txfifo = <0x1000>;
- phy-handle = <&phy7>;
- clock-frequency = <100000000>;
- phy7: phy@7 {
- compatible = "marvell,88e1111";
- reg = <7>;
- } ;
- } ;
- } ;
- IIC_EEPROM: i2c@81600000 {
- compatible = "xlnx,xps-iic-2.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 6 2 >;
- reg = < 0x81600000 0x10000 >;
- xlnx,clk-freq = <0x5f5e100>;
- xlnx,family = "virtex5";
- xlnx,gpo-width = <0x1>;
- xlnx,iic-freq = <0x186a0>;
- xlnx,scl-inertial-delay = <0x0>;
- xlnx,sda-inertial-delay = <0x0>;
- xlnx,ten-bit-adr = <0x0>;
- } ;
- LEDs_8Bit: gpio@81400000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81400000 0x10000 >;
- xlnx,all-inputs = <0>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <8>;
- xlnx,interrupt-present = <0>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- LEDs_Positions: gpio@81420000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81420000 0x10000 >;
- xlnx,all-inputs = <0>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <5>;
- xlnx,interrupt-present = <0>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- Push_Buttons_5Bit: gpio@81440000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 8 2 >;
- reg = < 0x81440000 0x10000 >;
- xlnx,all-inputs = <1>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <5>;
- xlnx,interrupt-present = <1>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- RS232_Uart_1: serial@83e00000 {
- clock-frequency = <100000000>;
- compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
- current-speed = <9600>;
- device_type = "serial";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 9 2 >;
- reg = < 0x83e00000 0x10000 >;
- reg-offset = <0x1003>;
- reg-shift = <2>;
- xlnx,family = "virtex5";
- xlnx,has-external-rclk = <0>;
- xlnx,has-external-xin = <0>;
- xlnx,is-a-16550 = <1>;
- } ;
- SysACE_CompactFlash: sysace@83600000 {
- compatible = "xlnx,xps-sysace-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 4 2 >;
- reg = < 0x83600000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,mem-width = <0x10>;
- } ;
- xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
- compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
- reg = < 0xffff0000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- xps_intc_0: interrupt-controller@81800000 {
- #interrupt-cells = <2>;
- compatible = "xlnx,xps-intc-1.00.a";
- interrupt-controller ;
- reg = < 0x81800000 0x10000 >;
- xlnx,num-intr-inputs = <0xc>;
- } ;
- xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
- compatible = "xlnx,xps-timebase-wdt-1.00.b";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 2 0 1 2 >;
- reg = < 0x83a00000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,wdt-enable-once = <0>;
- xlnx,wdt-interval = <0x1e>;
- } ;
- xps_timer_1: timer@83c00000 {
- compatible = "xlnx,xps-timer-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 3 2 >;
- reg = < 0x83c00000 0x10000 >;
- xlnx,count-width = <0x20>;
- xlnx,family = "virtex5";
- xlnx,gen0-assert = <1>;
- xlnx,gen1-assert = <1>;
- xlnx,one-timer-only = <1>;
- xlnx,trig0-assert = <1>;
- xlnx,trig1-assert = <1>;
- } ;
- } ;
-} ;
diff --git a/arch/powerpc/boot/dts/virtex440-ml510.dts b/arch/powerpc/boot/dts/virtex440-ml510.dts
deleted file mode 100644
index 3b736ca26ddc..000000000000
--- a/arch/powerpc/boot/dts/virtex440-ml510.dts
+++ /dev/null
@@ -1,466 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Xilinx ML510 Reference Design support
- *
- * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design.
- * The reference design contains a bug which prevent PCI DMA from working
- * properly. A description of the bug is given in the plbv46_pci section. It
- * needs to be fixed by the user until Xilinx updates their reference design.
- *
- * Copyright 2009, Roderick Colenbrander
- */
-
-/dts-v1/;
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
- dcr-parent = <&ppc440_0>;
- DDR2_SDRAM_DIMM0: memory@0 {
- device_type = "memory";
- reg = < 0x0 0x20000000 >;
- } ;
- alias {
- ethernet0 = &Hard_Ethernet_MAC;
- serial0 = &RS232_Uart_1;
- } ;
- chosen {
- bootargs = "console=ttyS0 root=/dev/ram";
- stdout-path = "/plb@0/serial@83e00000";
- } ;
- cpus {
- #address-cells = <1>;
- #cpus = <0x1>;
- #size-cells = <0>;
- ppc440_0: cpu@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- clock-frequency = <300000000>;
- compatible = "PowerPC,440", "ibm,ppc440";
- d-cache-line-size = <0x20>;
- d-cache-size = <0x8000>;
- dcr-access-method = "native";
- dcr-controller ;
- device_type = "cpu";
- i-cache-line-size = <0x20>;
- i-cache-size = <0x8000>;
- model = "PowerPC,440";
- reg = <0>;
- timebase-frequency = <300000000>;
- xlnx,apu-control = <0x2000>;
- xlnx,apu-udi-0 = <0x0>;
- xlnx,apu-udi-1 = <0x0>;
- xlnx,apu-udi-10 = <0x0>;
- xlnx,apu-udi-11 = <0x0>;
- xlnx,apu-udi-12 = <0x0>;
- xlnx,apu-udi-13 = <0x0>;
- xlnx,apu-udi-14 = <0x0>;
- xlnx,apu-udi-15 = <0x0>;
- xlnx,apu-udi-2 = <0x0>;
- xlnx,apu-udi-3 = <0x0>;
- xlnx,apu-udi-4 = <0x0>;
- xlnx,apu-udi-5 = <0x0>;
- xlnx,apu-udi-6 = <0x0>;
- xlnx,apu-udi-7 = <0x0>;
- xlnx,apu-udi-8 = <0x0>;
- xlnx,apu-udi-9 = <0x0>;
- xlnx,dcr-autolock-enable = <0x1>;
- xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
- xlnx,dcu-rd-noncache-plb-prio = <0x0>;
- xlnx,dcu-rd-touch-plb-prio = <0x0>;
- xlnx,dcu-rd-urgent-plb-prio = <0x0>;
- xlnx,dcu-wr-flush-plb-prio = <0x0>;
- xlnx,dcu-wr-store-plb-prio = <0x0>;
- xlnx,dcu-wr-urgent-plb-prio = <0x0>;
- xlnx,dma0-control = <0x0>;
- xlnx,dma0-plb-prio = <0x0>;
- xlnx,dma0-rxchannelctrl = <0x1010000>;
- xlnx,dma0-rxirqtimer = <0x3ff>;
- xlnx,dma0-txchannelctrl = <0x1010000>;
- xlnx,dma0-txirqtimer = <0x3ff>;
- xlnx,dma1-control = <0x0>;
- xlnx,dma1-plb-prio = <0x0>;
- xlnx,dma1-rxchannelctrl = <0x1010000>;
- xlnx,dma1-rxirqtimer = <0x3ff>;
- xlnx,dma1-txchannelctrl = <0x1010000>;
- xlnx,dma1-txirqtimer = <0x3ff>;
- xlnx,dma2-control = <0x0>;
- xlnx,dma2-plb-prio = <0x0>;
- xlnx,dma2-rxchannelctrl = <0x1010000>;
- xlnx,dma2-rxirqtimer = <0x3ff>;
- xlnx,dma2-txchannelctrl = <0x1010000>;
- xlnx,dma2-txirqtimer = <0x3ff>;
- xlnx,dma3-control = <0x0>;
- xlnx,dma3-plb-prio = <0x0>;
- xlnx,dma3-rxchannelctrl = <0x1010000>;
- xlnx,dma3-rxirqtimer = <0x3ff>;
- xlnx,dma3-txchannelctrl = <0x1010000>;
- xlnx,dma3-txirqtimer = <0x3ff>;
- xlnx,endian-reset = <0x0>;
- xlnx,generate-plb-timespecs = <0x1>;
- xlnx,icu-rd-fetch-plb-prio = <0x0>;
- xlnx,icu-rd-spec-plb-prio = <0x0>;
- xlnx,icu-rd-touch-plb-prio = <0x0>;
- xlnx,interconnect-imask = <0xffffffff>;
- xlnx,mplb-allow-lock-xfer = <0x1>;
- xlnx,mplb-arb-mode = <0x0>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-counter = <0x500>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-max-burst = <0x8>;
- xlnx,mplb-native-dwidth = <0x80>;
- xlnx,mplb-p2p = <0x0>;
- xlnx,mplb-prio-dcur = <0x2>;
- xlnx,mplb-prio-dcuw = <0x3>;
- xlnx,mplb-prio-icu = <0x4>;
- xlnx,mplb-prio-splb0 = <0x1>;
- xlnx,mplb-prio-splb1 = <0x0>;
- xlnx,mplb-read-pipe-enable = <0x1>;
- xlnx,mplb-sync-tattribute = <0x0>;
- xlnx,mplb-wdog-enable = <0x1>;
- xlnx,mplb-write-pipe-enable = <0x1>;
- xlnx,mplb-write-post-enable = <0x1>;
- xlnx,num-dma = <0x0>;
- xlnx,pir = <0xf>;
- xlnx,ppc440mc-addr-base = <0x0>;
- xlnx,ppc440mc-addr-high = <0x1fffffff>;
- xlnx,ppc440mc-arb-mode = <0x0>;
- xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
- xlnx,ppc440mc-control = <0xf810008f>;
- xlnx,ppc440mc-max-burst = <0x8>;
- xlnx,ppc440mc-prio-dcur = <0x2>;
- xlnx,ppc440mc-prio-dcuw = <0x3>;
- xlnx,ppc440mc-prio-icu = <0x4>;
- xlnx,ppc440mc-prio-splb0 = <0x1>;
- xlnx,ppc440mc-prio-splb1 = <0x0>;
- xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
- xlnx,ppcdm-asyncmode = <0x0>;
- xlnx,ppcds-asyncmode = <0x0>;
- xlnx,user-reset = <0x0>;
- } ;
- } ;
- plb_v46_0: plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
- ranges ;
- FLASH: flash@fc000000 {
- bank-width = <2>;
- compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
- reg = < 0xfc000000 0x2000000 >;
- xlnx,family = "virtex5";
- xlnx,include-datawidth-matching-0 = <0x1>;
- xlnx,include-datawidth-matching-1 = <0x0>;
- xlnx,include-datawidth-matching-2 = <0x0>;
- xlnx,include-datawidth-matching-3 = <0x0>;
- xlnx,include-negedge-ioregs = <0x0>;
- xlnx,include-plb-ipif = <0x1>;
- xlnx,include-wrbuf = <0x1>;
- xlnx,max-mem-width = <0x10>;
- xlnx,mch-native-dwidth = <0x20>;
- xlnx,mch-plb-clk-period-ps = <0x2710>;
- xlnx,mch-splb-awidth = <0x20>;
- xlnx,mch0-accessbuf-depth = <0x10>;
- xlnx,mch0-protocol = <0x0>;
- xlnx,mch0-rddatabuf-depth = <0x10>;
- xlnx,mch1-accessbuf-depth = <0x10>;
- xlnx,mch1-protocol = <0x0>;
- xlnx,mch1-rddatabuf-depth = <0x10>;
- xlnx,mch2-accessbuf-depth = <0x10>;
- xlnx,mch2-protocol = <0x0>;
- xlnx,mch2-rddatabuf-depth = <0x10>;
- xlnx,mch3-accessbuf-depth = <0x10>;
- xlnx,mch3-protocol = <0x0>;
- xlnx,mch3-rddatabuf-depth = <0x10>;
- xlnx,mem0-width = <0x10>;
- xlnx,mem1-width = <0x20>;
- xlnx,mem2-width = <0x20>;
- xlnx,mem3-width = <0x20>;
- xlnx,num-banks-mem = <0x1>;
- xlnx,num-channels = <0x2>;
- xlnx,priority-mode = <0x0>;
- xlnx,synch-mem-0 = <0x0>;
- xlnx,synch-mem-1 = <0x0>;
- xlnx,synch-mem-2 = <0x0>;
- xlnx,synch-mem-3 = <0x0>;
- xlnx,synch-pipedelay-0 = <0x2>;
- xlnx,synch-pipedelay-1 = <0x2>;
- xlnx,synch-pipedelay-2 = <0x2>;
- xlnx,synch-pipedelay-3 = <0x2>;
- xlnx,tavdv-ps-mem-0 = <0x1adb0>;
- xlnx,tavdv-ps-mem-1 = <0x3a98>;
- xlnx,tavdv-ps-mem-2 = <0x3a98>;
- xlnx,tavdv-ps-mem-3 = <0x3a98>;
- xlnx,tcedv-ps-mem-0 = <0x1adb0>;
- xlnx,tcedv-ps-mem-1 = <0x3a98>;
- xlnx,tcedv-ps-mem-2 = <0x3a98>;
- xlnx,tcedv-ps-mem-3 = <0x3a98>;
- xlnx,thzce-ps-mem-0 = <0x88b8>;
- xlnx,thzce-ps-mem-1 = <0x1b58>;
- xlnx,thzce-ps-mem-2 = <0x1b58>;
- xlnx,thzce-ps-mem-3 = <0x1b58>;
- xlnx,thzoe-ps-mem-0 = <0x1b58>;
- xlnx,thzoe-ps-mem-1 = <0x1b58>;
- xlnx,thzoe-ps-mem-2 = <0x1b58>;
- xlnx,thzoe-ps-mem-3 = <0x1b58>;
- xlnx,tlzwe-ps-mem-0 = <0x88b8>;
- xlnx,tlzwe-ps-mem-1 = <0x0>;
- xlnx,tlzwe-ps-mem-2 = <0x0>;
- xlnx,tlzwe-ps-mem-3 = <0x0>;
- xlnx,twc-ps-mem-0 = <0x1adb0>;
- xlnx,twc-ps-mem-1 = <0x3a98>;
- xlnx,twc-ps-mem-2 = <0x3a98>;
- xlnx,twc-ps-mem-3 = <0x3a98>;
- xlnx,twp-ps-mem-0 = <0x11170>;
- xlnx,twp-ps-mem-1 = <0x2ee0>;
- xlnx,twp-ps-mem-2 = <0x2ee0>;
- xlnx,twp-ps-mem-3 = <0x2ee0>;
- xlnx,xcl0-linesize = <0x4>;
- xlnx,xcl0-writexfer = <0x1>;
- xlnx,xcl1-linesize = <0x4>;
- xlnx,xcl1-writexfer = <0x1>;
- xlnx,xcl2-linesize = <0x4>;
- xlnx,xcl2-writexfer = <0x1>;
- xlnx,xcl3-linesize = <0x4>;
- xlnx,xcl3-writexfer = <0x1>;
- } ;
- Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ethernet@81c00000 {
- compatible = "xlnx,xps-ll-temac-1.01.b";
- device_type = "network";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 8 2 >;
- llink-connected = <&Hard_Ethernet_MAC_fifo>;
- local-mac-address = [ 02 00 00 00 00 00 ];
- reg = < 0x81c00000 0x40 >;
- xlnx,bus2core-clk-ratio = <0x1>;
- xlnx,phy-type = <0x3>;
- xlnx,phyaddr = <0x1>;
- xlnx,rxcsum = <0x0>;
- xlnx,rxfifo = <0x8000>;
- xlnx,temac-type = <0x0>;
- xlnx,txcsum = <0x0>;
- xlnx,txfifo = <0x8000>;
- } ;
- } ;
- Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
- compatible = "xlnx,xps-ll-fifo-1.01.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 6 2 >;
- reg = < 0x81a00000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- IIC_EEPROM: i2c@81600000 {
- compatible = "xlnx,xps-iic-2.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 9 2 >;
- reg = < 0x81600000 0x10000 >;
- xlnx,clk-freq = <0x5f5e100>;
- xlnx,family = "virtex5";
- xlnx,gpo-width = <0x1>;
- xlnx,iic-freq = <0x186a0>;
- xlnx,scl-inertial-delay = <0x5>;
- xlnx,sda-inertial-delay = <0x5>;
- xlnx,ten-bit-adr = <0x0>;
- } ;
- LCD_OPTIONAL: gpio@81420000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81420000 0x10000 >;
- xlnx,all-inputs = <0x0>;
- xlnx,all-inputs-2 = <0x0>;
- xlnx,dout-default = <0x0>;
- xlnx,dout-default-2 = <0x0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <0xb>;
- xlnx,interrupt-present = <0x0>;
- xlnx,is-bidir = <0x1>;
- xlnx,is-bidir-2 = <0x1>;
- xlnx,is-dual = <0x0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- LEDs_4Bit: gpio@81400000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81400000 0x10000 >;
- xlnx,all-inputs = <0x0>;
- xlnx,all-inputs-2 = <0x0>;
- xlnx,dout-default = <0x0>;
- xlnx,dout-default-2 = <0x0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <0x4>;
- xlnx,interrupt-present = <0x0>;
- xlnx,is-bidir = <0x1>;
- xlnx,is-bidir-2 = <0x1>;
- xlnx,is-dual = <0x0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- RS232_Uart_1: serial@83e00000 {
- clock-frequency = <100000000>;
- compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
- current-speed = <9600>;
- device_type = "serial";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 11 2 >;
- reg = < 0x83e00000 0x10000 >;
- reg-offset = <0x1003>;
- reg-shift = <2>;
- xlnx,family = "virtex5";
- xlnx,has-external-rclk = <0x0>;
- xlnx,has-external-xin = <0x0>;
- xlnx,is-a-16550 = <0x1>;
- } ;
- SPI_EEPROM: xps-spi@feff8000 {
- compatible = "xlnx,xps-spi-2.00.b";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 10 2 >;
- reg = < 0xfeff8000 0x80 >;
- xlnx,family = "virtex5";
- xlnx,fifo-exist = <0x1>;
- xlnx,num-ss-bits = <0x1>;
- xlnx,num-transfer-bits = <0x8>;
- xlnx,sck-ratio = <0x80>;
- } ;
- SysACE_CompactFlash: sysace@83600000 {
- compatible = "xlnx,xps-sysace-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 7 2 >;
- reg = < 0x83600000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,mem-width = <0x10>;
- } ;
- plbv46_pci_0: plbv46-pci@85e00000 {
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "xlnx,plbv46-pci-1.03.a";
- device_type = "pci";
- reg = < 0x85e00000 0x10000 >;
-
- /*
- * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to
- * 0 which means that a read/write to the memory mapped
- * i/o region (which starts at 0xa0000000) for pci
- * bar 0 on the plb side translates to 0.
- * It is important to set this value to 0xa0000000, so
- * that inbound and outbound pci transactions work
- * properly including DMA.
- */
- ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
- 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>;
-
- #interrupt-cells = <1>;
- interrupt-parent = <&xps_intc_0>;
- interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
- interrupt-map = <
- /* IRQ mapping for pci slots and ALI M1533
- * periperhals. In total there are 5 interrupt
- * lines connected to a xps_intc controller.
- * Four of them are PCI IRQ A, B, C, D and
- * which correspond to respectively xpx_intc
- * 5, 4, 3 and 2. The fifth interrupt line is
- * connected to the south bridge and this one
- * uses irq 1 and is active high instead of
- * active low.
- *
- * The M1533 contains various peripherals
- * including AC97 audio, a modem, USB, IDE and
- * some power management stuff. The modem
- * isn't connected on the ML510 and the power
- * management core also isn't used.
- */
-
- /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
- 0x3000 0 0 1 &xps_intc_0 3 2
- 0x3000 0 0 2 &xps_intc_0 2 2
- 0x3000 0 0 3 &xps_intc_0 5 2
- 0x3000 0 0 4 &xps_intc_0 4 2
-
- /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
- /*
- 0x11800 0 0 1 &xps_intc_0 5 0 2
- 0x11800 0 0 2 &xps_intc_0 4 0 2
- 0x11800 0 0 3 &xps_intc_0 3 0 2
- 0x11800 0 0 4 &xps_intc_0 2 0 2
- */
-
- /* According to the datasheet + schematic
- * ABCD [FPGA] of slot 5 is mapped to DABC.
- * Testing showed that at least A maps to B,
- * the mapping of the other pins is a guess
- * and for that reason the lines have been
- * commented out.
- */
- /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
- 0x2800 0 0 1 &xps_intc_0 4 2
- /*
- 0x2800 0 0 2 &xps_intc_0 3 2
- 0x2800 0 0 3 &xps_intc_0 2 2
- 0x2800 0 0 4 &xps_intc_0 5 2
- */
-
- /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
- /*
- 0x11000 0 0 1 &xps_intc_0 4 0 2
- 0x11000 0 0 2 &xps_intc_0 3 0 2
- 0x11000 0 0 3 &xps_intc_0 2 0 2
- 0x11000 0 0 4 &xps_intc_0 5 0 2
- */
-
- /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
- 0x0800 0 0 1 &i8259 7 2
-
- /* IDSEL 0x1b / dev=11, bus=0 / IDE */
- 0x5800 0 0 1 &i8259 14 2
-
- /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
- 0x7800 0 0 1 &i8259 7 2
- >;
- ali_m1533 {
- #size-cells = <1>;
- #address-cells = <2>;
- i8259: interrupt-controller@20 {
- reg = <1 0x20 2
- 1 0xa0 2
- 1 0x4d0 2>;
- interrupt-controller;
- device_type = "interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- compatible = "chrp,iic";
-
- /* south bridge irq is active high */
- interrupts = <1 3>;
- interrupt-parent = <&xps_intc_0>;
- };
- };
- } ;
- xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
- compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
- reg = < 0xffff0000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- xps_intc_0: interrupt-controller@81800000 {
- #interrupt-cells = <0x2>;
- compatible = "xlnx,xps-intc-1.00.a";
- interrupt-controller ;
- reg = < 0x81800000 0x10000 >;
- xlnx,num-intr-inputs = <0xc>;
- } ;
- xps_tft_0: tft@86e00000 {
- compatible = "xlnx,xps-tft-1.00.a";
- reg = < 0x86e00000 0x10000 >;
- xlnx,dcr-splb-slave-if = <0x1>;
- xlnx,default-tft-base-addr = <0x0>;
- xlnx,family = "virtex5";
- xlnx,i2c-slave-addr = <0x76>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-native-dwidth = <0x40>;
- xlnx,mplb-smallest-slave = <0x20>;
- xlnx,tft-interface = <0x1>;
- } ;
- } ;
-} ;
diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h
index e0606766480f..6455fc9a244f 100644
--- a/arch/powerpc/boot/ops.h
+++ b/arch/powerpc/boot/ops.h
@@ -88,7 +88,6 @@ int serial_console_init(void);
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
int cpm_console_init(void *devp, struct serial_console_data *scdp);
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp);
-int uartlite_console_init(void *devp, struct serial_console_data *scdp);
int opal_console_init(void *devp, struct serial_console_data *scdp);
void *simple_alloc_init(char *base, unsigned long heap_size,
unsigned long granularity, unsigned long max_allocs);
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index 9457863147f9..0bfa7e87e546 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -132,11 +132,6 @@ int serial_console_init(void)
else if (dt_is_compatible(devp, "fsl,mpc5200-psc-uart"))
rc = mpc5200_psc_console_init(devp, &serial_cd);
#endif
-#ifdef CONFIG_XILINX_VIRTEX
- else if (dt_is_compatible(devp, "xlnx,opb-uartlite-1.00.b") ||
- dt_is_compatible(devp, "xlnx,xps-uartlite-1.00.a"))
- rc = uartlite_console_init(devp, &serial_cd);
-#endif
#ifdef CONFIG_PPC64_BOOT_WRAPPER
else if (dt_is_compatible(devp, "ibm,opal-console-raw"))
rc = opal_console_init(devp, &serial_cd);
diff --git a/arch/powerpc/boot/uartlite.c b/arch/powerpc/boot/uartlite.c
deleted file mode 100644
index 46bed69b4169..000000000000
--- a/arch/powerpc/boot/uartlite.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Xilinx UARTLITE bootloader driver
- *
- * Copyright (C) 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include "types.h"
-#include "string.h"
-#include "stdio.h"
-#include "io.h"
-#include "ops.h"
-
-#define ULITE_RX 0x00
-#define ULITE_TX 0x04
-#define ULITE_STATUS 0x08
-#define ULITE_CONTROL 0x0c
-
-#define ULITE_STATUS_RXVALID 0x01
-#define ULITE_STATUS_TXFULL 0x08
-
-#define ULITE_CONTROL_RST_RX 0x02
-
-static void * reg_base;
-
-static int uartlite_open(void)
-{
- /* Clear the RX FIFO */
- out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX);
- return 0;
-}
-
-static void uartlite_putc(unsigned char c)
-{
- u32 reg = ULITE_STATUS_TXFULL;
- while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */
- reg = in_be32(reg_base + ULITE_STATUS);
- out_be32(reg_base + ULITE_TX, c);
-}
-
-static unsigned char uartlite_getc(void)
-{
- u32 reg = 0;
- while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */
- reg = in_be32(reg_base + ULITE_STATUS);
- return in_be32(reg_base + ULITE_RX);
-}
-
-static u8 uartlite_tstc(void)
-{
- u32 reg = in_be32(reg_base + ULITE_STATUS);
- return reg & ULITE_STATUS_RXVALID;
-}
-
-int uartlite_console_init(void *devp, struct serial_console_data *scdp)
-{
- int n;
- unsigned long reg_phys;
-
- n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base));
- if (n != sizeof(reg_base)) {
- if (!dt_xlate_reg(devp, 0, ®_phys, NULL))
- return -1;
-
- reg_base = (void *)reg_phys;
- }
-
- scdp->open = uartlite_open;
- scdp->putc = uartlite_putc;
- scdp->getc = uartlite_getc;
- scdp->tstc = uartlite_tstc;
- scdp->close = NULL;
- return 0;
-}
diff --git a/arch/powerpc/boot/virtex.c b/arch/powerpc/boot/virtex.c
deleted file mode 100644
index f731cbb4bff0..000000000000
--- a/arch/powerpc/boot/virtex.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * The platform specific code for virtex devices since a boot loader is not
- * always used.
- *
- * (C) Copyright 2008 Xilinx, Inc.
- */
-
-#include "ops.h"
-#include "io.h"
-#include "stdio.h"
-
-#define UART_DLL 0 /* Out: Divisor Latch Low */
-#define UART_DLM 1 /* Out: Divisor Latch High */
-#define UART_FCR 2 /* Out: FIFO Control Register */
-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define UART_LCR 3 /* Out: Line Control Register */
-#define UART_MCR 4 /* Out: Modem Control Register */
-#define UART_MCR_RTS 0x02 /* RTS complement */
-#define UART_MCR_DTR 0x01 /* DTR complement */
-#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-
-static int virtex_ns16550_console_init(void *devp)
-{
- unsigned char *reg_base;
- u32 reg_shift, reg_offset, clk, spd;
- u16 divisor;
- int n;
-
- if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1)
- return -1;
-
- n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset));
- if (n == sizeof(reg_offset))
- reg_base += reg_offset;
-
- n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift));
- if (n != sizeof(reg_shift))
- reg_shift = 0;
-
- n = getprop(devp, "current-speed", (void *)&spd, sizeof(spd));
- if (n != sizeof(spd))
- spd = 9600;
-
- /* should there be a default clock rate?*/
- n = getprop(devp, "clock-frequency", (void *)&clk, sizeof(clk));
- if (n != sizeof(clk))
- return -1;
-
- divisor = clk / (16 * spd);
-
- /* Access baud rate */
- out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB);
-
- /* Baud rate based on input clock */
- out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF);
- out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8);
-
- /* 8 data, 1 stop, no parity */
- out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8);
-
- /* RTS/DTR */
- out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR);
-
- /* Clear transmitter and receiver */
- out_8(reg_base + (UART_FCR << reg_shift),
- UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
- return 0;
-}
-
-/* For virtex, the kernel may be loaded without using a bootloader and if so
- some UARTs need more setup than is provided in the normal console init
-*/
-int platform_specific_init(void)
-{
- void *devp;
- char devtype[MAX_PROP_LEN];
- char path[MAX_PATH_LEN];
-
- devp = finddevice("/chosen");
- if (devp == NULL)
- return -1;
-
- if (getprop(devp, "linux,stdout-path", path, MAX_PATH_LEN) > 0) {
- devp = finddevice(path);
- if (devp == NULL)
- return -1;
-
- if ((getprop(devp, "device_type", devtype, sizeof(devtype)) > 0)
- && !strcmp(devtype, "serial")
- && (dt_is_compatible(devp, "ns16550")))
- virtex_ns16550_console_init(devp);
- }
- return 0;
-}
diff --git a/arch/powerpc/boot/virtex405-head.S b/arch/powerpc/boot/virtex405-head.S
deleted file mode 100644
index 00bab7d7c48c..000000000000
--- a/arch/powerpc/boot/virtex405-head.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include "ppc_asm.h"
-
- .text
- .global _zimage_start
-_zimage_start:
-
- /* PPC errata 213: needed by Virtex-4 FX */
- mfccr0 0
- oris 0,0,0x50000000@h
- mtccr0 0
-
- /*
- * Invalidate the data cache if the data cache is turned off.
- * - The 405 core does not invalidate the data cache on power-up
- * or reset but does turn off the data cache. We cannot assume
- * that the cache contents are valid.
- * - If the data cache is turned on this must have been done by
- * a bootloader and we assume that the cache contents are
- * valid.
- */
- mfdccr r9
- cmplwi r9,0
- bne 2f
- lis r9,0
- li r8,256
- mtctr r8
-1: dccci r0,r9
- addi r9,r9,0x20
- bdnz 1b
-2: b _zimage_start_lib
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index ed6266367bc0..de5fd5a047e8 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -323,14 +323,6 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
-simpleboot-virtex405-*)
- platformo="$object/virtex405-head.o $object/simpleboot.o $object/virtex.o"
- binary=y
- ;;
-simpleboot-virtex440-*)
- platformo="$object/fixed-head.o $object/simpleboot.o $object/virtex.o"
- binary=y
- ;;
simpleboot-*)
platformo="$object/fixed-head.o $object/simpleboot.o"
binary=y
diff --git a/arch/powerpc/configs/40x/virtex_defconfig b/arch/powerpc/configs/40x/virtex_defconfig
deleted file mode 100644
index 5e7c61d1d7d0..000000000000
--- a/arch/powerpc/configs/40x/virtex_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_40x=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_WALNUT is not set
-CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
-CONFIG_PREEMPT=y
-CONFIG_MATH_EMULATION=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE=""
-CONFIG_PCI=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_XILINX_SYSACE=y
-CONFIG_NETDEVICES=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
-CONFIG_XILINX_HWICAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_XILINX=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRC_CCITT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/powerpc/configs/44x/virtex5_defconfig b/arch/powerpc/configs/44x/virtex5_defconfig
deleted file mode 100644
index 1f74079e1703..000000000000
--- a/arch/powerpc/configs/44x/virtex5_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_44x=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_EBONY is not set
-CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y
-CONFIG_PREEMPT=y
-CONFIG_MATH_EMULATION=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE=""
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_XILINX_SYSACE=y
-CONFIG_NETDEVICES=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
-CONFIG_XILINX_HWICAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_XILINX=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRC_CCITT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/powerpc/configs/ppc40x_defconfig b/arch/powerpc/configs/ppc40x_defconfig
index a5f683aed328..88960a72b525 100644
--- a/arch/powerpc/configs/ppc40x_defconfig
+++ b/arch/powerpc/configs/ppc40x_defconfig
@@ -14,7 +14,6 @@ CONFIG_EP405=y
CONFIG_HOTFOOT=y
CONFIG_KILAUEA=y
CONFIG_MAKALU=y
-CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -37,33 +36,26 @@ CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
-CONFIG_XILINX_SYSACE=m
CONFIG_NETDEVICES=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=m
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
# CONFIG_HW_RANDOM is not set
-CONFIG_XILINX_HWICAP=m
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_IBM_IIC=m
-CONFIG_GPIO_XILINX=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=y
CONFIG_FB=m
-CONFIG_FB_XILINX=m
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=m
CONFIG_VFAT_FS=m
diff --git a/arch/powerpc/configs/ppc44x_defconfig b/arch/powerpc/configs/ppc44x_defconfig
index a41eedfe0a5f..8b595f67068c 100644
--- a/arch/powerpc/configs/ppc44x_defconfig
+++ b/arch/powerpc/configs/ppc44x_defconfig
@@ -22,7 +22,6 @@ CONFIG_GLACIER=y
CONFIG_REDWOOD=y
CONFIG_EIGER=y
CONFIG_YOSEMITE=y
-CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y
CONFIG_PPC4xx_GPIO=y
CONFIG_MATH_EMULATION=y
CONFIG_NET=y
@@ -46,7 +45,6 @@ CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
-CONFIG_XILINX_SYSACE=m
CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m
# CONFIG_SCSI_LOWLEVEL is not set
@@ -57,7 +55,6 @@ CONFIG_IBM_EMAC=y
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=m
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
@@ -65,18 +62,13 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
# CONFIG_HW_RANDOM is not set
-CONFIG_XILINX_HWICAP=m
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_IBM_IIC=m
-CONFIG_GPIO_XILINX=y
# CONFIG_HWMON is not set
CONFIG_FB=m
-CONFIG_FB_XILINX=m
CONFIG_USB=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_OHCI_HCD=m
diff --git a/arch/powerpc/include/asm/xilinx_intc.h b/arch/powerpc/include/asm/xilinx_intc.h
deleted file mode 100644
index ca9aa162fb09..000000000000
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Xilinx intc external definitions
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- */
-#ifndef _ASM_POWERPC_XILINX_INTC_H
-#define _ASM_POWERPC_XILINX_INTC_H
-
-#ifdef __KERNEL__
-
-extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xintc_get_irq(void);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/include/asm/xilinx_pci.h b/arch/powerpc/include/asm/xilinx_pci.h
deleted file mode 100644
index 7a8275caf6af..000000000000
--- a/arch/powerpc/include/asm/xilinx_pci.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Xilinx pci external definitions
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef INCLUDE_XILINX_PCI
-#define INCLUDE_XILINX_PCI
-
-#ifdef CONFIG_XILINX_PCI
-extern void __init xilinx_pci_init(void);
-#else
-static inline void __init xilinx_pci_init(void) { return; }
-#endif
-
-#endif /* INCLUDE_XILINX_PCI */
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 245be4fafe13..2dff9041bcdc 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1385,32 +1385,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
- { /* Xilinx Virtex-II Pro */
- .pvr_mask = 0xfffff000,
- .pvr_value = 0x20010000,
- .cpu_name = "Virtex-II Pro",
- .cpu_features = CPU_FTRS_40X,
- .cpu_user_features = PPC_FEATURE_32 |
- PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
- .mmu_features = MMU_FTR_TYPE_40x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .machine_check = machine_check_4xx,
- .platform = "ppc405",
- },
- { /* Xilinx Virtex-4 FX */
- .pvr_mask = 0xfffff000,
- .pvr_value = 0x20011000,
- .cpu_name = "Virtex-4 FX",
- .cpu_features = CPU_FTRS_40X,
- .cpu_user_features = PPC_FEATURE_32 |
- PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
- .mmu_features = MMU_FTR_TYPE_40x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .machine_check = machine_check_4xx,
- .platform = "ppc405",
- },
{ /* 405EP */
.pvr_mask = 0xffff0000,
.pvr_value = 0x51210000,
@@ -1800,19 +1774,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = "ppc440",
},
- { /* 440 in Xilinx Virtex-5 FXT */
- .pvr_mask = 0xfffffff0,
- .pvr_value = 0x7ff21910,
- .cpu_name = "440 in Virtex-5 FXT",
- .cpu_features = CPU_FTRS_44X,
- .cpu_user_features = COMMON_USER_BOOKE,
- .mmu_features = MMU_FTR_TYPE_44x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .cpu_setup = __setup_cpu_440x5,
- .machine_check = machine_check_440A,
- .platform = "ppc440",
- },
{ /* 460EX */
.pvr_mask = 0xffff0006,
.pvr_value = 0x13020002,
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index 6da813b65b42..d06ca51e8443 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -55,23 +55,6 @@ config WALNUT
help
This option enables support for the IBM PPC405GP evaluation board.
-config XILINX_VIRTEX_GENERIC_BOARD
- bool "Generic Xilinx Virtex board"
- depends on 40x
- select XILINX_VIRTEX_II_PRO
- select XILINX_VIRTEX_4_FX
- select XILINX_INTC
- help
- This option enables generic support for Xilinx Virtex based boards.
-
- The generic virtex board support matches any device tree which
- specifies 'xilinx,virtex' in its compatible field. This includes
- the Xilinx ML3xx and ML4xx reference designs using the powerpc
- core.
-
- Most Virtex designs should use this unless it needs to do some
- special configuration at board probe time.
-
config OBS600
bool "OpenBlockS 600"
depends on 40x
@@ -109,20 +92,6 @@ config 405EZ
select IBM_EMAC_MAL_CLR_ICINTSTAT if IBM_EMAC
select IBM_EMAC_MAL_COMMON_ERR if IBM_EMAC
-config XILINX_VIRTEX
- bool
- select DEFAULT_UIMAGE
-
-config XILINX_VIRTEX_II_PRO
- bool
- select XILINX_VIRTEX
- select IBM405_ERR77
- select IBM405_ERR51
-
-config XILINX_VIRTEX_4_FX
- bool
- select XILINX_VIRTEX
-
config STB03xxx
bool
select IBM405_ERR77
diff --git a/arch/powerpc/platforms/40x/Makefile b/arch/powerpc/platforms/40x/Makefile
index 828d78340dd9..e9386deed505 100644
--- a/arch/powerpc/platforms/40x/Makefile
+++ b/arch/powerpc/platforms/40x/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_WALNUT) += walnut.o
-obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD) += virtex.o
obj-$(CONFIG_EP405) += ep405.o
obj-$(CONFIG_PPC40x_SIMPLE) += ppc40x_simple.o
diff --git a/arch/powerpc/platforms/40x/virtex.c b/arch/powerpc/platforms/40x/virtex.c
deleted file mode 100644
index e3d5e095846b..000000000000
--- a/arch/powerpc/platforms/40x/virtex.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Xilinx Virtex (IIpro & 4FX) based board support
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <asm/xilinx_intc.h>
-#include <asm/xilinx_pci.h>
-#include <asm/ppc4xx.h>
-
-static const struct of_device_id xilinx_of_bus_ids[] __initconst = {
- { .compatible = "xlnx,plb-v46-1.00.a", },
- { .compatible = "xlnx,plb-v34-1.01.a", },
- { .compatible = "xlnx,plb-v34-1.02.a", },
- { .compatible = "xlnx,opb-v20-1.10.c", },
- { .compatible = "xlnx,dcr-v29-1.00.a", },
- { .compatible = "xlnx,compound", },
- {}
-};
-
-static int __init virtex_device_probe(void)
-{
- of_platform_bus_probe(NULL, xilinx_of_bus_ids, NULL);
-
- return 0;
-}
-machine_device_initcall(virtex, virtex_device_probe);
-
-static int __init virtex_probe(void)
-{
- if (!of_machine_is_compatible("xlnx,virtex"))
- return 0;
-
- return 1;
-}
-
-define_machine(virtex) {
- .name = "Xilinx Virtex",
- .probe = virtex_probe,
- .setup_arch = xilinx_pci_init,
- .init_IRQ = xilinx_intc_init_tree,
- .get_irq = xintc_get_irq,
- .restart = ppc4xx_reset_system,
- .calibrate_decr = generic_calibrate_decr,
-};
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 25ebe634a661..39e93d23fb38 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -232,33 +232,6 @@ config ICON
help
This option enables support for the AMCC PPC440SPe evaluation board.
-config XILINX_VIRTEX440_GENERIC_BOARD
- bool "Generic Xilinx Virtex 5 FXT board support"
- depends on 44x
- select XILINX_VIRTEX_5_FXT
- select XILINX_INTC
- help
- This option enables generic support for Xilinx Virtex based boards
- that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
-
- The generic virtex board support matches any device tree which
- specifies 'xlnx,virtex440' in its compatible field. This includes
- the Xilinx ML5xx reference designs using the powerpc core.
-
- Most Virtex 5 designs should use this unless it needs to do some
- special configuration at board probe time.
-
-config XILINX_ML510
- bool "Xilinx ML510 extra support"
- depends on XILINX_VIRTEX440_GENERIC_BOARD
- select HAVE_PCI
- select XILINX_PCI if PCI
- select PPC_INDIRECT_PCI if PCI
- select PPC_I8259 if PCI
- help
- This option enables extra support for features on the Xilinx ML510
- board. The ML510 has a PCI bus with ALI south bridge.
-
config PPC44x_SIMPLE
bool "Simple PowerPC 44x board support"
depends on 44x
@@ -354,13 +327,3 @@ config 476FPE_ERR46
config IBM440EP_ERR42
bool
-# Xilinx specific config options.
-config XILINX_VIRTEX
- bool
- select DEFAULT_UIMAGE
-
-# Xilinx Virtex 5 FXT FPGA architecture, selected by a Xilinx board above
-config XILINX_VIRTEX_5_FXT
- bool
- select XILINX_VIRTEX
-
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 1b78c6af821a..5ba031f57652 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -7,8 +7,6 @@ obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_SAM440EP) += sam440ep.o
obj-$(CONFIG_WARP) += warp.o
-obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
-obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
obj-$(CONFIG_ISS4xx) += iss4xx.o
obj-$(CONFIG_CANYONLANDS)+= canyonlands.o
obj-$(CONFIG_CURRITUCK) += ppc476.o
diff --git a/arch/powerpc/platforms/44x/virtex.c b/arch/powerpc/platforms/44x/virtex.c
deleted file mode 100644
index 3eb13ed926ee..000000000000
--- a/arch/powerpc/platforms/44x/virtex.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Xilinx Virtex 5FXT based board support, derived from
- * the Xilinx Virtex (IIpro & 4FX) based board support
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- * Copyright 2008 Xilinx, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <asm/xilinx_intc.h>
-#include <asm/xilinx_pci.h>
-#include <asm/reg.h>
-#include <asm/ppc4xx.h>
-#include "44x.h"
-
-static const struct of_device_id xilinx_of_bus_ids[] __initconst = {
- { .compatible = "simple-bus", },
- { .compatible = "xlnx,plb-v46-1.00.a", },
- { .compatible = "xlnx,plb-v46-1.02.a", },
- { .compatible = "xlnx,plb-v34-1.01.a", },
- { .compatible = "xlnx,plb-v34-1.02.a", },
- { .compatible = "xlnx,opb-v20-1.10.c", },
- { .compatible = "xlnx,dcr-v29-1.00.a", },
- { .compatible = "xlnx,compound", },
- {}
-};
-
-static int __init virtex_device_probe(void)
-{
- of_platform_bus_probe(NULL, xilinx_of_bus_ids, NULL);
-
- return 0;
-}
-machine_device_initcall(virtex, virtex_device_probe);
-
-static int __init virtex_probe(void)
-{
- if (!of_machine_is_compatible("xlnx,virtex440"))
- return 0;
-
- return 1;
-}
-
-define_machine(virtex) {
- .name = "Xilinx Virtex440",
- .probe = virtex_probe,
- .setup_arch = xilinx_pci_init,
- .init_IRQ = xilinx_intc_init_tree,
- .get_irq = xintc_get_irq,
- .calibrate_decr = generic_calibrate_decr,
- .restart = ppc4xx_reset_system,
-};
diff --git a/arch/powerpc/platforms/44x/virtex_ml510.c b/arch/powerpc/platforms/44x/virtex_ml510.c
deleted file mode 100644
index 349f218b335c..000000000000
--- a/arch/powerpc/platforms/44x/virtex_ml510.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <asm/i8259.h>
-#include <linux/pci.h>
-#include "44x.h"
-
-/**
- * ml510_ail_quirk
- */
-static void ml510_ali_quirk(struct pci_dev *dev)
-{
- /* Enable the IDE controller */
- pci_write_config_byte(dev, 0x58, 0x4c);
- /* Assign irq 14 to the primary ide channel */
- pci_write_config_byte(dev, 0x44, 0x0d);
- /* Assign irq 15 to the secondary ide channel */
- pci_write_config_byte(dev, 0x75, 0x0f);
- /* Set the ide controller in native mode */
- pci_write_config_byte(dev, 0x09, 0xff);
-
- /* INTB = disabled, INTA = disabled */
- pci_write_config_byte(dev, 0x48, 0x00);
- /* INTD = disabled, INTC = disabled */
- pci_write_config_byte(dev, 0x4a, 0x00);
- /* Audio = INT7, Modem = disabled. */
- pci_write_config_byte(dev, 0x4b, 0x60);
- /* USB = INT7 */
- pci_write_config_byte(dev, 0x74, 0x06);
-}
-DECLARE_PCI_FIXUP_EARLY(0x10b9, 0x1533, ml510_ali_quirk);
-
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 1f8025383caa..5e6479d409a0 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -317,8 +317,4 @@ config MCU_MPC8349EMITX
also register MCU GPIOs with the generic GPIO API, so you'll able
to use MCU pins as GPIOs.
-config XILINX_PCI
- bool "Xilinx PCI host bridge support"
- depends on PCI && XILINX_VIRTEX
-
endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cb5a5bd2cef5..026b3f01a991 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -31,8 +31,6 @@ obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_IPIC) += ipic.o
-obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
-obj-$(CONFIG_XILINX_PCI) += xilinx_pci.o
obj-$(CONFIG_OF_RTC) += of_rtc.o
obj-$(CONFIG_CPM) += cpm_common.o
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
deleted file mode 100644
index 4a86dcff3fcd..000000000000
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Interrupt controller driver for Xilinx Virtex FPGAs
- *
- * Copyright (C) 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
- */
-
-/*
- * This is a driver for the interrupt controller typically found in
- * Xilinx Virtex FPGA designs.
- *
- * The interrupt sense levels are hard coded into the FPGA design with
- * typically a 1:1 relationship between irq lines and devices (no shared
- * irq lines). Therefore, this driver does not attempt to handle edge
- * and level interrupts differently.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/i8259.h>
-#include <asm/irq.h>
-#include <linux/irqchip.h>
-
-#if defined(CONFIG_PPC_I8259)
-/*
- * Support code for cascading to 8259 interrupt controllers
- */
-static void xilinx_i8259_cascade(struct irq_desc *desc)
-{
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned int cascade_irq = i8259_irq();
-
- if (cascade_irq)
- generic_handle_irq(cascade_irq);
-
- /* Let xilinx_intc end the interrupt */
- chip->irq_unmask(&desc->irq_data);
-}
-
-static void __init xilinx_i8259_setup_cascade(void)
-{
- struct device_node *cascade_node;
- int cascade_irq;
-
- /* Initialize i8259 controller */
- cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
- if (!cascade_node)
- return;
-
- cascade_irq = irq_of_parse_and_map(cascade_node, 0);
- if (!cascade_irq) {
- pr_err("virtex_ml510: Failed to map cascade interrupt\n");
- goto out;
- }
-
- i8259_init(cascade_node, 0);
- irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
-
- /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
- /* This looks like a dirty hack to me --gcl */
- outb(0xc0, 0x4d0);
- outb(0xc0, 0x4d1);
-
- out:
- of_node_put(cascade_node);
-}
-#else
-static inline void xilinx_i8259_setup_cascade(void) { return; }
-#endif /* defined(CONFIG_PPC_I8259) */
-
-/*
- * Initialize master Xilinx interrupt controller
- */
-void __init xilinx_intc_init_tree(void)
-{
- irqchip_init();
- xilinx_i8259_setup_cascade();
-}
diff --git a/arch/powerpc/sysdev/xilinx_pci.c b/arch/powerpc/sysdev/xilinx_pci.c
deleted file mode 100644
index fea5667699ed..000000000000
--- a/arch/powerpc/sysdev/xilinx_pci.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * PCI support for Xilinx plbv46_pci soft-core which can be used on
- * Xilinx Virtex ML410 / ML510 boards.
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
- * by Benjamin Herrenschmidt.
- * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/ioport.h>
-#include <linux/of.h>
-#include <linux/pci.h>
-#include <mm/mmu_decl.h>
-#include <asm/io.h>
-#include <asm/xilinx_pci.h>
-
-#define XPLB_PCI_ADDR 0x10c
-#define XPLB_PCI_DATA 0x110
-#define XPLB_PCI_BUS 0x114
-
-#define PCI_HOST_ENABLE_CMD PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
-
-static const struct of_device_id xilinx_pci_match[] = {
- { .compatible = "xlnx,plbv46-pci-1.03.a", },
- {}
-};
-
-/**
- * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
- */
-static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
-{
- struct pci_controller *hose;
- int i;
-
- if (dev->devfn || dev->bus->self)
- return;
-
- hose = pci_bus_to_host(dev->bus);
- if (!hose)
- return;
-
- if (!of_match_node(xilinx_pci_match, hose->dn))
- return;
-
- /* Hide the PCI host BARs from the kernel as their content doesn't
- * fit well in the resource management
- */
- for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
- }
-
- dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
- pci_name(dev));
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
-
-/**
- * xilinx_pci_exclude_device - Don't do config access for non-root bus
- *
- * This is a hack. Config access to any bus other than bus 0 does not
- * currently work on the ML510 so we prevent it here.
- */
-static int
-xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
-{
- return (bus != 0);
-}
-
-/**
- * xilinx_pci_init - Find and register a Xilinx PCI host bridge
- */
-void __init xilinx_pci_init(void)
-{
- struct pci_controller *hose;
- struct resource r;
- void __iomem *pci_reg;
- struct device_node *pci_node;
-
- pci_node = of_find_matching_node(NULL, xilinx_pci_match);
- if(!pci_node)
- return;
-
- if (of_address_to_resource(pci_node, 0, &r)) {
- pr_err("xilinx-pci: cannot resolve base address\n");
- return;
- }
-
- hose = pcibios_alloc_controller(pci_node);
- if (!hose) {
- pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
- return;
- }
-
- /* Setup config space */
- setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
- r.start + XPLB_PCI_DATA,
- PPC_INDIRECT_TYPE_SET_CFG_TYPE);
-
- /* According to the xilinx plbv46_pci documentation the soft-core starts
- * a self-init when the bus master enable bit is set. Without this bit
- * set the pci bus can't be scanned.
- */
- early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
-
- /* Set the max latency timer to 255 */
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
-
- /* Set the max bus number to 255 */
- pci_reg = of_iomap(pci_node, 0);
- out_8(pci_reg + XPLB_PCI_BUS, 0xff);
- iounmap(pci_reg);
-
- /* Nothing past the root bridge is working right now. By default
- * exclude config access to anything except bus 0 */
- if (!ppc_md.pci_exclude_device)
- ppc_md.pci_exclude_device = xilinx_pci_exclude_device;
-
- /* Register the host bridge with the linux kernel! */
- pci_process_bridge_OF_ranges(hose, pci_node, 1);
-
- pr_info("xilinx-pci: Registered PCI host bridge\n");
-}
diff --git a/arch/powerpc/xmon/ppc-dis.c b/arch/powerpc/xmon/ppc-dis.c
index 75fa98221d48..a91ac589b401 100644
--- a/arch/powerpc/xmon/ppc-dis.c
+++ b/arch/powerpc/xmon/ppc-dis.c
@@ -224,12 +224,6 @@ int print_insn_powerpc (unsigned long insn, unsigned long memaddr)
print_address(memaddr + value);
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
print_address(value & 0xffffffff);
- else if ((operand->flags & PPC_OPERAND_FSL) != 0)
- printf("fsl%ld", value);
- else if ((operand->flags & PPC_OPERAND_FCR) != 0)
- printf("fcr%ld", value);
- else if ((operand->flags & PPC_OPERAND_UDI) != 0)
- printf("%ld", value);
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
index dfb80810b16c..918845e777fd 100644
--- a/arch/powerpc/xmon/ppc-opc.c
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -857,29 +857,6 @@ const struct powerpc_operand powerpc_operands[] =
#define HTM_A XFL_L
{ 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
- /* Xilinx APU related masks and macros */
-#define FCRT XFL_L + 1
-#define FCRT_MASK (0x1f << 21)
- { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
-
- /* Xilinx FSL related masks and macros */
-#define FSL FCRT + 1
-#define FSL_MASK (0x1f << 11)
- { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
-
- /* Xilinx UDI related masks and macros */
-#define URT FSL + 1
- { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
-
-#define URA URT + 1
- { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
-
-#define URB URA + 1
- { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
-
-#define URC URB + 1
- { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
-
/* The VLESIMM field in a D form instruction. */
#define VLESIMM URC + 1
{ 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
diff --git a/arch/powerpc/xmon/ppc.h b/arch/powerpc/xmon/ppc.h
index d00f33dcf192..37717b1f7bd7 100644
--- a/arch/powerpc/xmon/ppc.h
+++ b/arch/powerpc/xmon/ppc.h
@@ -388,11 +388,6 @@ extern const unsigned int num_powerpc_operands;
/* Valid range of operand is 0..n rather than 0..n-1. */
#define PPC_OPERAND_PLUS1 (0x10000)
-/* Xilinx APU and FSL related operands */
-#define PPC_OPERAND_FSL (0x20000)
-#define PPC_OPERAND_FCR (0x40000)
-#define PPC_OPERAND_UDI (0x80000)
-
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 26956c006987..0ccbd6fd6de1 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -316,7 +316,7 @@ config DTLK
config XILINX_HWICAP
tristate "Xilinx HWICAP Support"
- depends on XILINX_VIRTEX || MICROBLAZE
+ depends on MICROBLAZE
help
This option enables support for Xilinx Internal Configuration
Access Port (ICAP) driver. The ICAP is used on Xilinx Virtex
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index f65991a67af2..b174650e0f09 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -2007,7 +2007,7 @@ config FB_PS3_DEFAULT_SIZE_M
config FB_XILINX
tristate "Xilinx frame buffer support"
- depends on FB && (XILINX_VIRTEX || MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ depends on FB && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
--
2.26.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 2/2] powerpc: Remove Xilinx PPC405/PPC440 support
@ 2020-03-27 12:12 ` Michal Simek
0 siblings, 0 replies; 104+ messages in thread
From: Michal Simek @ 2020-03-27 12:12 UTC (permalink / raw)
To: linux-kernel, monstr, michal.simek, git, sfr, marc.zyngier
Cc: Kate Stewart, Mark Rutland, Desnes A. Nunes do Rosario,
Geert Uytterhoeven, linux-doc, Benjamin Herrenschmidt,
linux-fbdev, dri-devel, Richard Fontana, Paul Mackerras,
Miquel Raynal, Mauro Carvalho Chehab, Fabio Estevam, Sasha Levin,
Jonathan Corbet, Michael Ellerman, Masahiro Yamada, YueHaibing,
Krzysztof Kozlowski, linux-arm-kernel, Leonardo Bras,
Matt Porter, devicetree, Andrew Donnellan, Arnd Bergmann,
Bartlomiej Zolnierkiewicz, Alistair Popple, linuxppc-dev,
Nicholas Piggin, Alexios Zavras, Rob Herring, Jonathan Cameron,
Thomas Gleixner, Andy Shevchenko, Allison Randal,
Christophe Leroy, Wei Hu, Greg Kroah-Hartman, Nick Desaulniers,
Armijn Hemel, Enrico Weigelt, David S. Miller,
Thiago Jung Bauermann
The latest Xilinx design tools called ISE and EDK has been released in
October 2013. New tool doesn't support any PPC405/PPC440 new designs.
These platforms are no longer supported and tested.
PowerPC 405/440 port is orphan from 2013 by
commit cdeb89943bfc ("MAINTAINERS: Fix incorrect status tag") and
commit 19624236cce1 ("MAINTAINERS: Update Grant's email address and maintainership")
that's why it is time to remove the support fot these platforms.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Documentation/devicetree/bindings/xilinx.txt | 143 ------
Documentation/powerpc/bootwrapper.rst | 28 +-
MAINTAINERS | 6 -
arch/powerpc/Kconfig.debug | 2 +-
arch/powerpc/boot/Makefile | 7 +-
arch/powerpc/boot/dts/Makefile | 1 -
arch/powerpc/boot/dts/virtex440-ml507.dts | 406 ----------------
arch/powerpc/boot/dts/virtex440-ml510.dts | 466 -------------------
arch/powerpc/boot/ops.h | 1 -
arch/powerpc/boot/serial.c | 5 -
arch/powerpc/boot/uartlite.c | 79 ----
arch/powerpc/boot/virtex.c | 97 ----
arch/powerpc/boot/virtex405-head.S | 31 --
arch/powerpc/boot/wrapper | 8 -
arch/powerpc/configs/40x/virtex_defconfig | 75 ---
arch/powerpc/configs/44x/virtex5_defconfig | 74 ---
arch/powerpc/configs/ppc40x_defconfig | 8 -
arch/powerpc/configs/ppc44x_defconfig | 8 -
arch/powerpc/include/asm/xilinx_intc.h | 16 -
arch/powerpc/include/asm/xilinx_pci.h | 21 -
arch/powerpc/kernel/cputable.c | 39 --
arch/powerpc/platforms/40x/Kconfig | 31 --
arch/powerpc/platforms/40x/Makefile | 1 -
arch/powerpc/platforms/40x/virtex.c | 54 ---
arch/powerpc/platforms/44x/Kconfig | 37 --
arch/powerpc/platforms/44x/Makefile | 2 -
arch/powerpc/platforms/44x/virtex.c | 60 ---
arch/powerpc/platforms/44x/virtex_ml510.c | 30 --
arch/powerpc/platforms/Kconfig | 4 -
arch/powerpc/sysdev/Makefile | 2 -
arch/powerpc/sysdev/xilinx_intc.c | 88 ----
arch/powerpc/sysdev/xilinx_pci.c | 132 ------
arch/powerpc/xmon/ppc-dis.c | 6 -
arch/powerpc/xmon/ppc-opc.c | 23 -
arch/powerpc/xmon/ppc.h | 5 -
drivers/char/Kconfig | 2 +-
drivers/video/fbdev/Kconfig | 2 +-
37 files changed, 7 insertions(+), 1993 deletions(-)
delete mode 100644 arch/powerpc/boot/dts/virtex440-ml507.dts
delete mode 100644 arch/powerpc/boot/dts/virtex440-ml510.dts
delete mode 100644 arch/powerpc/boot/uartlite.c
delete mode 100644 arch/powerpc/boot/virtex.c
delete mode 100644 arch/powerpc/boot/virtex405-head.S
delete mode 100644 arch/powerpc/configs/40x/virtex_defconfig
delete mode 100644 arch/powerpc/configs/44x/virtex5_defconfig
delete mode 100644 arch/powerpc/include/asm/xilinx_intc.h
delete mode 100644 arch/powerpc/include/asm/xilinx_pci.h
delete mode 100644 arch/powerpc/platforms/40x/virtex.c
delete mode 100644 arch/powerpc/platforms/44x/virtex.c
delete mode 100644 arch/powerpc/platforms/44x/virtex_ml510.c
delete mode 100644 arch/powerpc/sysdev/xilinx_intc.c
delete mode 100644 arch/powerpc/sysdev/xilinx_pci.c
diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt
index d058ace29345..28199b31fe5e 100644
--- a/Documentation/devicetree/bindings/xilinx.txt
+++ b/Documentation/devicetree/bindings/xilinx.txt
@@ -86,149 +86,6 @@
xlnx,use-parity = <0>;
};
- Some IP cores actually implement 2 or more logical devices. In
- this case, the device should still describe the whole IP core with
- a single node and add a child node for each logical device. The
- ranges property can be used to translate from parent IP-core to the
- registers of each device. In addition, the parent node should be
- compatible with the bus type 'xlnx,compound', and should contain
- #address-cells and #size-cells, as with any other bus. (Note: this
- makes the assumption that both logical devices have the same bus
- binding. If this is not true, then separate nodes should be used
- for each logical device). The 'cell-index' property can be used to
- enumerate logical devices within an IP core. For example, the
- following is the system.mhs entry for the dual ps2 controller found
- on the ml403 reference design.
-
- BEGIN opb_ps2_dual_ref
- PARAMETER INSTANCE = opb_ps2_dual_ref_0
- PARAMETER HW_VER = 1.00.a
- PARAMETER C_BASEADDR = 0xA9000000
- PARAMETER C_HIGHADDR = 0xA9001FFF
- BUS_INTERFACE SOPB = opb_v20_0
- PORT Sys_Intr1 = ps2_1_intr
- PORT Sys_Intr2 = ps2_2_intr
- PORT Clkin1 = ps2_clk_rx_1
- PORT Clkin2 = ps2_clk_rx_2
- PORT Clkpd1 = ps2_clk_tx_1
- PORT Clkpd2 = ps2_clk_tx_2
- PORT Rx1 = ps2_d_rx_1
- PORT Rx2 = ps2_d_rx_2
- PORT Txpd1 = ps2_d_tx_1
- PORT Txpd2 = ps2_d_tx_2
- END
-
- It would result in the following device tree nodes:
-
- opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ranges = <0 a9000000 2000>;
- // If this device had extra parameters, then they would
- // go here.
- ps2@0 {
- compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
- reg = <0 40>;
- interrupt-parent = <&opb_intc_0>;
- interrupts = <3 0>;
- cell-index = <0>;
- };
- ps2@1000 {
- compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
- reg = <1000 40>;
- interrupt-parent = <&opb_intc_0>;
- interrupts = <3 0>;
- cell-index = <0>;
- };
- };
-
- Also, the system.mhs file defines bus attachments from the processor
- to the devices. The device tree structure should reflect the bus
- attachments. Again an example; this system.mhs fragment:
-
- BEGIN ppc405_virtex4
- PARAMETER INSTANCE = ppc405_0
- PARAMETER HW_VER = 1.01.a
- BUS_INTERFACE DPLB = plb_v34_0
- BUS_INTERFACE IPLB = plb_v34_0
- END
-
- BEGIN opb_intc
- PARAMETER INSTANCE = opb_intc_0
- PARAMETER HW_VER = 1.00.c
- PARAMETER C_BASEADDR = 0xD1000FC0
- PARAMETER C_HIGHADDR = 0xD1000FDF
- BUS_INTERFACE SOPB = opb_v20_0
- END
-
- BEGIN opb_uart16550
- PARAMETER INSTANCE = opb_uart16550_0
- PARAMETER HW_VER = 1.00.d
- PARAMETER C_BASEADDR = 0xa0000000
- PARAMETER C_HIGHADDR = 0xa0001FFF
- BUS_INTERFACE SOPB = opb_v20_0
- END
-
- BEGIN plb_v34
- PARAMETER INSTANCE = plb_v34_0
- PARAMETER HW_VER = 1.02.a
- END
-
- BEGIN plb_bram_if_cntlr
- PARAMETER INSTANCE = plb_bram_if_cntlr_0
- PARAMETER HW_VER = 1.00.b
- PARAMETER C_BASEADDR = 0xFFFF0000
- PARAMETER C_HIGHADDR = 0xFFFFFFFF
- BUS_INTERFACE SPLB = plb_v34_0
- END
-
- BEGIN plb2opb_bridge
- PARAMETER INSTANCE = plb2opb_bridge_0
- PARAMETER HW_VER = 1.01.a
- PARAMETER C_RNG0_BASEADDR = 0x20000000
- PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
- PARAMETER C_RNG1_BASEADDR = 0x60000000
- PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
- PARAMETER C_RNG2_BASEADDR = 0x80000000
- PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
- PARAMETER C_RNG3_BASEADDR = 0xC0000000
- PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
- BUS_INTERFACE SPLB = plb_v34_0
- BUS_INTERFACE MOPB = opb_v20_0
- END
-
- Gives this device tree (some properties removed for clarity):
-
- plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v34-1.02.a";
- device_type = "ibm,plb";
- ranges; // 1:1 translation
-
- plb_bram_if_cntrl_0: bram@ffff0000 {
- reg = <ffff0000 10000>;
- }
-
- opb@20000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <20000000 20000000 20000000
- 60000000 60000000 20000000
- 80000000 80000000 40000000
- c0000000 c0000000 20000000>;
-
- opb_uart16550_0: serial@a0000000 {
- reg = <a00000000 2000>;
- };
-
- opb_intc_0: interrupt-controller@d1000fc0 {
- reg = <d1000fc0 20>;
- };
- };
- };
-
That covers the general approach to binding xilinx IP cores into the
device tree. The following are bindings for specific devices:
diff --git a/Documentation/powerpc/bootwrapper.rst b/Documentation/powerpc/bootwrapper.rst
index a6292afba573..cdfa2bc8425f 100644
--- a/Documentation/powerpc/bootwrapper.rst
+++ b/Documentation/powerpc/bootwrapper.rst
@@ -70,28 +70,6 @@ Currently, the following image format targets exist:
kernel with this image type and it depends entirely on
the embedded device tree for all information.
- The simpleImage is useful for booting systems with
- an unknown firmware interface or for booting from
- a debugger when no firmware is present (such as on
- the Xilinx Virtex platform). The only assumption that
- simpleImage makes is that RAM is correctly initialized
- and that the MMU is either off or has RAM mapped to
- base address 0.
-
- simpleImage also supports inserting special platform
- specific initialization code to the start of the bootup
- sequence. The virtex405 platform uses this feature to
- ensure that the cache is invalidated before caching
- is enabled. Platform specific initialization code is
- added as part of the wrapper script and is keyed on
- the image target name. For example, all
- simpleImage.virtex405-* targets will add the
- virtex405-head.S initialization code (This also means
- that the dts file for virtex405 targets should be
- named (virtex405-<board>.dts). Search the wrapper
- script for 'virtex405' and see the file
- arch/powerpc/boot/virtex405-head.S for details.
-
treeImage.%; Image format for used with OpenBIOS firmware found
on some ppc4xx hardware. This image embeds a device
tree blob inside the image.
@@ -116,10 +94,8 @@ Image types which embed a device tree blob (simpleImage, dtbImage, treeImage,
and cuImage) all generate the device tree blob from a file in the
arch/powerpc/boot/dts/ directory. The Makefile selects the correct device
tree source based on the name of the target. Therefore, if the kernel is
-built with 'make treeImage.walnut simpleImage.virtex405-ml403', then the
-build system will use arch/powerpc/boot/dts/walnut.dts to build
-treeImage.walnut and arch/powerpc/boot/dts/virtex405-ml403.dts to build
-the simpleImage.virtex405-ml403.
+built with 'make treeImage.walnut', then the build system will use
+arch/powerpc/boot/dts/walnut.dts to build treeImage.walnut.
Two special targets called 'zImage' and 'zImage.initrd' also exist. These
targets build all the default images as selected by the kernel configuration.
diff --git a/MAINTAINERS b/MAINTAINERS
index a0d86490c2c6..842a9bbc2013 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9668,12 +9668,6 @@ L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: arch/powerpc/platforms/8xx/
-LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
-L: linuxppc-dev@lists.ozlabs.org
-S: Orphan
-F: arch/powerpc/*/*virtex*
-F: arch/powerpc/*/*/*virtex*
-
LINUX FOR POWERPC PA SEMI PWRFICIENT
L: linuxppc-dev@lists.ozlabs.org
S: Orphan
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 0b063830eea8..b88900f4832f 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -230,7 +230,7 @@ config PPC_EARLY_DEBUG_40x
help
Select this to enable early debugging for IBM 40x chips via the
inbuilt serial port. This works on chips with a 16550 compatible
- UART. Xilinx chips with uartlite cannot use this option.
+ UART.
config PPC_EARLY_DEBUG_CPM
bool "Early serial debugging for Freescale CPM-based serial ports"
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index c53a1b8bba8b..d8077b7071dd 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -79,7 +79,6 @@ $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
-$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
# The pre-boot decompressors pull in a lot of kernel headers and other source
# files. This creates a bit of a dependency headache since we need to copy
@@ -129,14 +128,12 @@ src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
-src-wlib-$(CONFIG_XILINX_VIRTEX) += uartlite.c
src-wlib-$(CONFIG_CPM) += cpm-serial.c
src-plat-y := of.c epapr.c
src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
treeboot-walnut.c cuboot-acadia.c \
- cuboot-kilauea.c simpleboot.c \
- virtex405-head.S virtex.c
+ cuboot-kilauea.c simpleboot.c
src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
cuboot-bamboo.c cuboot-sam440ep.c \
cuboot-sequoia.c cuboot-rainier.c \
@@ -144,7 +141,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
cuboot-warp.c cuboot-yosemite.c \
treeboot-iss4xx.c treeboot-currituck.c \
treeboot-akebono.c \
- simpleboot.c fixed-head.S virtex.c
+ simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
diff --git a/arch/powerpc/boot/dts/Makefile b/arch/powerpc/boot/dts/Makefile
index 1cbc0e4ce857..fb335d05aae8 100644
--- a/arch/powerpc/boot/dts/Makefile
+++ b/arch/powerpc/boot/dts/Makefile
@@ -4,4 +4,3 @@ subdir-y += fsl
dtstree := $(srctree)/$(src)
dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
-dtb-$(CONFIG_XILINX_VIRTEX440_GENERIC_BOARD) += virtex440-ml507.dtb virtex440-ml510.dtb
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
deleted file mode 100644
index 66f1c6312de6..000000000000
--- a/arch/powerpc/boot/dts/virtex440-ml507.dts
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * This file supports the Xilinx ML507 board with the 440 processor.
- * A reference design for the FPGA is provided at http://git.xilinx.com.
- *
- * (C) Copyright 2008 Xilinx, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
- * ---
- *
- * Device Tree Generator version: 1.1
- *
- * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
- *
- * XPS project directory: ml507_ppc440_emb_ref
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,virtex440";
- dcr-parent = <&ppc440_0>;
- model = "testing";
- DDR2_SDRAM: memory@0 {
- device_type = "memory";
- reg = < 0 0x10000000 >;
- } ;
- chosen {
- bootargs = "console=ttyS0 root=/dev/ram";
- stdout-path = &RS232_Uart_1;
- } ;
- cpus {
- #address-cells = <1>;
- #cpus = <1>;
- #size-cells = <0>;
- ppc440_0: cpu@0 {
- clock-frequency = <400000000>;
- compatible = "PowerPC,440", "ibm,ppc440";
- d-cache-line-size = <0x20>;
- d-cache-size = <0x8000>;
- dcr-access-method = "native";
- dcr-controller ;
- device_type = "cpu";
- i-cache-line-size = <0x20>;
- i-cache-size = <0x8000>;
- model = "PowerPC,440";
- reg = <0>;
- timebase-frequency = <400000000>;
- xlnx,apu-control = <1>;
- xlnx,apu-udi-0 = <0>;
- xlnx,apu-udi-1 = <0>;
- xlnx,apu-udi-10 = <0>;
- xlnx,apu-udi-11 = <0>;
- xlnx,apu-udi-12 = <0>;
- xlnx,apu-udi-13 = <0>;
- xlnx,apu-udi-14 = <0>;
- xlnx,apu-udi-15 = <0>;
- xlnx,apu-udi-2 = <0>;
- xlnx,apu-udi-3 = <0>;
- xlnx,apu-udi-4 = <0>;
- xlnx,apu-udi-5 = <0>;
- xlnx,apu-udi-6 = <0>;
- xlnx,apu-udi-7 = <0>;
- xlnx,apu-udi-8 = <0>;
- xlnx,apu-udi-9 = <0>;
- xlnx,dcr-autolock-enable = <1>;
- xlnx,dcu-rd-ld-cache-plb-prio = <0>;
- xlnx,dcu-rd-noncache-plb-prio = <0>;
- xlnx,dcu-rd-touch-plb-prio = <0>;
- xlnx,dcu-rd-urgent-plb-prio = <0>;
- xlnx,dcu-wr-flush-plb-prio = <0>;
- xlnx,dcu-wr-store-plb-prio = <0>;
- xlnx,dcu-wr-urgent-plb-prio = <0>;
- xlnx,dma0-control = <0>;
- xlnx,dma0-plb-prio = <0>;
- xlnx,dma0-rxchannelctrl = <0x1010000>;
- xlnx,dma0-rxirqtimer = <0x3ff>;
- xlnx,dma0-txchannelctrl = <0x1010000>;
- xlnx,dma0-txirqtimer = <0x3ff>;
- xlnx,dma1-control = <0>;
- xlnx,dma1-plb-prio = <0>;
- xlnx,dma1-rxchannelctrl = <0x1010000>;
- xlnx,dma1-rxirqtimer = <0x3ff>;
- xlnx,dma1-txchannelctrl = <0x1010000>;
- xlnx,dma1-txirqtimer = <0x3ff>;
- xlnx,dma2-control = <0>;
- xlnx,dma2-plb-prio = <0>;
- xlnx,dma2-rxchannelctrl = <0x1010000>;
- xlnx,dma2-rxirqtimer = <0x3ff>;
- xlnx,dma2-txchannelctrl = <0x1010000>;
- xlnx,dma2-txirqtimer = <0x3ff>;
- xlnx,dma3-control = <0>;
- xlnx,dma3-plb-prio = <0>;
- xlnx,dma3-rxchannelctrl = <0x1010000>;
- xlnx,dma3-rxirqtimer = <0x3ff>;
- xlnx,dma3-txchannelctrl = <0x1010000>;
- xlnx,dma3-txirqtimer = <0x3ff>;
- xlnx,endian-reset = <0>;
- xlnx,generate-plb-timespecs = <1>;
- xlnx,icu-rd-fetch-plb-prio = <0>;
- xlnx,icu-rd-spec-plb-prio = <0>;
- xlnx,icu-rd-touch-plb-prio = <0>;
- xlnx,interconnect-imask = <0xffffffff>;
- xlnx,mplb-allow-lock-xfer = <1>;
- xlnx,mplb-arb-mode = <0>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-counter = <0x500>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-max-burst = <8>;
- xlnx,mplb-native-dwidth = <0x80>;
- xlnx,mplb-p2p = <0>;
- xlnx,mplb-prio-dcur = <2>;
- xlnx,mplb-prio-dcuw = <3>;
- xlnx,mplb-prio-icu = <4>;
- xlnx,mplb-prio-splb0 = <1>;
- xlnx,mplb-prio-splb1 = <0>;
- xlnx,mplb-read-pipe-enable = <1>;
- xlnx,mplb-sync-tattribute = <0>;
- xlnx,mplb-wdog-enable = <1>;
- xlnx,mplb-write-pipe-enable = <1>;
- xlnx,mplb-write-post-enable = <1>;
- xlnx,num-dma = <1>;
- xlnx,pir = <0xf>;
- xlnx,ppc440mc-addr-base = <0>;
- xlnx,ppc440mc-addr-high = <0xfffffff>;
- xlnx,ppc440mc-arb-mode = <0>;
- xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
- xlnx,ppc440mc-control = <0xf810008f>;
- xlnx,ppc440mc-max-burst = <8>;
- xlnx,ppc440mc-prio-dcur = <2>;
- xlnx,ppc440mc-prio-dcuw = <3>;
- xlnx,ppc440mc-prio-icu = <4>;
- xlnx,ppc440mc-prio-splb0 = <1>;
- xlnx,ppc440mc-prio-splb1 = <0>;
- xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
- xlnx,ppcdm-asyncmode = <0>;
- xlnx,ppcds-asyncmode = <0>;
- xlnx,user-reset = <0>;
- DMA0: sdma@80 {
- compatible = "xlnx,ll-dma-1.00.a";
- dcr-reg = < 0x80 0x11 >;
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 10 2 11 2 >;
- } ;
- } ;
- } ;
- plb_v46_0: plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
- ranges ;
- DIP_Switches_8Bit: gpio@81460000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 7 2 >;
- reg = < 0x81460000 0x10000 >;
- xlnx,all-inputs = <1>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <8>;
- xlnx,interrupt-present = <1>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- FLASH: flash@fc000000 {
- bank-width = <2>;
- compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
- reg = < 0xfc000000 0x2000000 >;
- xlnx,family = "virtex5";
- xlnx,include-datawidth-matching-0 = <0x1>;
- xlnx,include-datawidth-matching-1 = <0x0>;
- xlnx,include-datawidth-matching-2 = <0x0>;
- xlnx,include-datawidth-matching-3 = <0x0>;
- xlnx,include-negedge-ioregs = <0x0>;
- xlnx,include-plb-ipif = <0x1>;
- xlnx,include-wrbuf = <0x1>;
- xlnx,max-mem-width = <0x10>;
- xlnx,mch-native-dwidth = <0x20>;
- xlnx,mch-plb-clk-period-ps = <0x2710>;
- xlnx,mch-splb-awidth = <0x20>;
- xlnx,mch0-accessbuf-depth = <0x10>;
- xlnx,mch0-protocol = <0x0>;
- xlnx,mch0-rddatabuf-depth = <0x10>;
- xlnx,mch1-accessbuf-depth = <0x10>;
- xlnx,mch1-protocol = <0x0>;
- xlnx,mch1-rddatabuf-depth = <0x10>;
- xlnx,mch2-accessbuf-depth = <0x10>;
- xlnx,mch2-protocol = <0x0>;
- xlnx,mch2-rddatabuf-depth = <0x10>;
- xlnx,mch3-accessbuf-depth = <0x10>;
- xlnx,mch3-protocol = <0x0>;
- xlnx,mch3-rddatabuf-depth = <0x10>;
- xlnx,mem0-width = <0x10>;
- xlnx,mem1-width = <0x20>;
- xlnx,mem2-width = <0x20>;
- xlnx,mem3-width = <0x20>;
- xlnx,num-banks-mem = <0x1>;
- xlnx,num-channels = <0x2>;
- xlnx,priority-mode = <0x0>;
- xlnx,synch-mem-0 = <0x0>;
- xlnx,synch-mem-1 = <0x0>;
- xlnx,synch-mem-2 = <0x0>;
- xlnx,synch-mem-3 = <0x0>;
- xlnx,synch-pipedelay-0 = <0x2>;
- xlnx,synch-pipedelay-1 = <0x2>;
- xlnx,synch-pipedelay-2 = <0x2>;
- xlnx,synch-pipedelay-3 = <0x2>;
- xlnx,tavdv-ps-mem-0 = <0x1adb0>;
- xlnx,tavdv-ps-mem-1 = <0x3a98>;
- xlnx,tavdv-ps-mem-2 = <0x3a98>;
- xlnx,tavdv-ps-mem-3 = <0x3a98>;
- xlnx,tcedv-ps-mem-0 = <0x1adb0>;
- xlnx,tcedv-ps-mem-1 = <0x3a98>;
- xlnx,tcedv-ps-mem-2 = <0x3a98>;
- xlnx,tcedv-ps-mem-3 = <0x3a98>;
- xlnx,thzce-ps-mem-0 = <0x88b8>;
- xlnx,thzce-ps-mem-1 = <0x1b58>;
- xlnx,thzce-ps-mem-2 = <0x1b58>;
- xlnx,thzce-ps-mem-3 = <0x1b58>;
- xlnx,thzoe-ps-mem-0 = <0x1b58>;
- xlnx,thzoe-ps-mem-1 = <0x1b58>;
- xlnx,thzoe-ps-mem-2 = <0x1b58>;
- xlnx,thzoe-ps-mem-3 = <0x1b58>;
- xlnx,tlzwe-ps-mem-0 = <0x88b8>;
- xlnx,tlzwe-ps-mem-1 = <0x0>;
- xlnx,tlzwe-ps-mem-2 = <0x0>;
- xlnx,tlzwe-ps-mem-3 = <0x0>;
- xlnx,twc-ps-mem-0 = <0x2af8>;
- xlnx,twc-ps-mem-1 = <0x3a98>;
- xlnx,twc-ps-mem-2 = <0x3a98>;
- xlnx,twc-ps-mem-3 = <0x3a98>;
- xlnx,twp-ps-mem-0 = <0x11170>;
- xlnx,twp-ps-mem-1 = <0x2ee0>;
- xlnx,twp-ps-mem-2 = <0x2ee0>;
- xlnx,twp-ps-mem-3 = <0x2ee0>;
- xlnx,xcl0-linesize = <0x4>;
- xlnx,xcl0-writexfer = <0x1>;
- xlnx,xcl1-linesize = <0x4>;
- xlnx,xcl1-writexfer = <0x1>;
- xlnx,xcl2-linesize = <0x4>;
- xlnx,xcl2-writexfer = <0x1>;
- xlnx,xcl3-linesize = <0x4>;
- xlnx,xcl3-writexfer = <0x1>;
- } ;
- Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ethernet@81c00000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "xlnx,xps-ll-temac-1.01.b";
- device_type = "network";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 5 2 >;
- llink-connected = <&DMA0>;
- local-mac-address = [ 02 00 00 00 00 00 ];
- reg = < 0x81c00000 0x40 >;
- xlnx,bus2core-clk-ratio = <1>;
- xlnx,phy-type = <1>;
- xlnx,phyaddr = <1>;
- xlnx,rxcsum = <1>;
- xlnx,rxfifo = <0x1000>;
- xlnx,temac-type = <0>;
- xlnx,txcsum = <1>;
- xlnx,txfifo = <0x1000>;
- phy-handle = <&phy7>;
- clock-frequency = <100000000>;
- phy7: phy@7 {
- compatible = "marvell,88e1111";
- reg = <7>;
- } ;
- } ;
- } ;
- IIC_EEPROM: i2c@81600000 {
- compatible = "xlnx,xps-iic-2.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 6 2 >;
- reg = < 0x81600000 0x10000 >;
- xlnx,clk-freq = <0x5f5e100>;
- xlnx,family = "virtex5";
- xlnx,gpo-width = <0x1>;
- xlnx,iic-freq = <0x186a0>;
- xlnx,scl-inertial-delay = <0x0>;
- xlnx,sda-inertial-delay = <0x0>;
- xlnx,ten-bit-adr = <0x0>;
- } ;
- LEDs_8Bit: gpio@81400000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81400000 0x10000 >;
- xlnx,all-inputs = <0>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <8>;
- xlnx,interrupt-present = <0>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- LEDs_Positions: gpio@81420000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81420000 0x10000 >;
- xlnx,all-inputs = <0>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <5>;
- xlnx,interrupt-present = <0>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- Push_Buttons_5Bit: gpio@81440000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 8 2 >;
- reg = < 0x81440000 0x10000 >;
- xlnx,all-inputs = <1>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <5>;
- xlnx,interrupt-present = <1>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- RS232_Uart_1: serial@83e00000 {
- clock-frequency = <100000000>;
- compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
- current-speed = <9600>;
- device_type = "serial";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 9 2 >;
- reg = < 0x83e00000 0x10000 >;
- reg-offset = <0x1003>;
- reg-shift = <2>;
- xlnx,family = "virtex5";
- xlnx,has-external-rclk = <0>;
- xlnx,has-external-xin = <0>;
- xlnx,is-a-16550 = <1>;
- } ;
- SysACE_CompactFlash: sysace@83600000 {
- compatible = "xlnx,xps-sysace-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 4 2 >;
- reg = < 0x83600000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,mem-width = <0x10>;
- } ;
- xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
- compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
- reg = < 0xffff0000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- xps_intc_0: interrupt-controller@81800000 {
- #interrupt-cells = <2>;
- compatible = "xlnx,xps-intc-1.00.a";
- interrupt-controller ;
- reg = < 0x81800000 0x10000 >;
- xlnx,num-intr-inputs = <0xc>;
- } ;
- xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
- compatible = "xlnx,xps-timebase-wdt-1.00.b";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 2 0 1 2 >;
- reg = < 0x83a00000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,wdt-enable-once = <0>;
- xlnx,wdt-interval = <0x1e>;
- } ;
- xps_timer_1: timer@83c00000 {
- compatible = "xlnx,xps-timer-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 3 2 >;
- reg = < 0x83c00000 0x10000 >;
- xlnx,count-width = <0x20>;
- xlnx,family = "virtex5";
- xlnx,gen0-assert = <1>;
- xlnx,gen1-assert = <1>;
- xlnx,one-timer-only = <1>;
- xlnx,trig0-assert = <1>;
- xlnx,trig1-assert = <1>;
- } ;
- } ;
-} ;
diff --git a/arch/powerpc/boot/dts/virtex440-ml510.dts b/arch/powerpc/boot/dts/virtex440-ml510.dts
deleted file mode 100644
index 3b736ca26ddc..000000000000
--- a/arch/powerpc/boot/dts/virtex440-ml510.dts
+++ /dev/null
@@ -1,466 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Xilinx ML510 Reference Design support
- *
- * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design.
- * The reference design contains a bug which prevent PCI DMA from working
- * properly. A description of the bug is given in the plbv46_pci section. It
- * needs to be fixed by the user until Xilinx updates their reference design.
- *
- * Copyright 2009, Roderick Colenbrander
- */
-
-/dts-v1/;
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
- dcr-parent = <&ppc440_0>;
- DDR2_SDRAM_DIMM0: memory@0 {
- device_type = "memory";
- reg = < 0x0 0x20000000 >;
- } ;
- alias {
- ethernet0 = &Hard_Ethernet_MAC;
- serial0 = &RS232_Uart_1;
- } ;
- chosen {
- bootargs = "console=ttyS0 root=/dev/ram";
- stdout-path = "/plb@0/serial@83e00000";
- } ;
- cpus {
- #address-cells = <1>;
- #cpus = <0x1>;
- #size-cells = <0>;
- ppc440_0: cpu@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- clock-frequency = <300000000>;
- compatible = "PowerPC,440", "ibm,ppc440";
- d-cache-line-size = <0x20>;
- d-cache-size = <0x8000>;
- dcr-access-method = "native";
- dcr-controller ;
- device_type = "cpu";
- i-cache-line-size = <0x20>;
- i-cache-size = <0x8000>;
- model = "PowerPC,440";
- reg = <0>;
- timebase-frequency = <300000000>;
- xlnx,apu-control = <0x2000>;
- xlnx,apu-udi-0 = <0x0>;
- xlnx,apu-udi-1 = <0x0>;
- xlnx,apu-udi-10 = <0x0>;
- xlnx,apu-udi-11 = <0x0>;
- xlnx,apu-udi-12 = <0x0>;
- xlnx,apu-udi-13 = <0x0>;
- xlnx,apu-udi-14 = <0x0>;
- xlnx,apu-udi-15 = <0x0>;
- xlnx,apu-udi-2 = <0x0>;
- xlnx,apu-udi-3 = <0x0>;
- xlnx,apu-udi-4 = <0x0>;
- xlnx,apu-udi-5 = <0x0>;
- xlnx,apu-udi-6 = <0x0>;
- xlnx,apu-udi-7 = <0x0>;
- xlnx,apu-udi-8 = <0x0>;
- xlnx,apu-udi-9 = <0x0>;
- xlnx,dcr-autolock-enable = <0x1>;
- xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
- xlnx,dcu-rd-noncache-plb-prio = <0x0>;
- xlnx,dcu-rd-touch-plb-prio = <0x0>;
- xlnx,dcu-rd-urgent-plb-prio = <0x0>;
- xlnx,dcu-wr-flush-plb-prio = <0x0>;
- xlnx,dcu-wr-store-plb-prio = <0x0>;
- xlnx,dcu-wr-urgent-plb-prio = <0x0>;
- xlnx,dma0-control = <0x0>;
- xlnx,dma0-plb-prio = <0x0>;
- xlnx,dma0-rxchannelctrl = <0x1010000>;
- xlnx,dma0-rxirqtimer = <0x3ff>;
- xlnx,dma0-txchannelctrl = <0x1010000>;
- xlnx,dma0-txirqtimer = <0x3ff>;
- xlnx,dma1-control = <0x0>;
- xlnx,dma1-plb-prio = <0x0>;
- xlnx,dma1-rxchannelctrl = <0x1010000>;
- xlnx,dma1-rxirqtimer = <0x3ff>;
- xlnx,dma1-txchannelctrl = <0x1010000>;
- xlnx,dma1-txirqtimer = <0x3ff>;
- xlnx,dma2-control = <0x0>;
- xlnx,dma2-plb-prio = <0x0>;
- xlnx,dma2-rxchannelctrl = <0x1010000>;
- xlnx,dma2-rxirqtimer = <0x3ff>;
- xlnx,dma2-txchannelctrl = <0x1010000>;
- xlnx,dma2-txirqtimer = <0x3ff>;
- xlnx,dma3-control = <0x0>;
- xlnx,dma3-plb-prio = <0x0>;
- xlnx,dma3-rxchannelctrl = <0x1010000>;
- xlnx,dma3-rxirqtimer = <0x3ff>;
- xlnx,dma3-txchannelctrl = <0x1010000>;
- xlnx,dma3-txirqtimer = <0x3ff>;
- xlnx,endian-reset = <0x0>;
- xlnx,generate-plb-timespecs = <0x1>;
- xlnx,icu-rd-fetch-plb-prio = <0x0>;
- xlnx,icu-rd-spec-plb-prio = <0x0>;
- xlnx,icu-rd-touch-plb-prio = <0x0>;
- xlnx,interconnect-imask = <0xffffffff>;
- xlnx,mplb-allow-lock-xfer = <0x1>;
- xlnx,mplb-arb-mode = <0x0>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-counter = <0x500>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-max-burst = <0x8>;
- xlnx,mplb-native-dwidth = <0x80>;
- xlnx,mplb-p2p = <0x0>;
- xlnx,mplb-prio-dcur = <0x2>;
- xlnx,mplb-prio-dcuw = <0x3>;
- xlnx,mplb-prio-icu = <0x4>;
- xlnx,mplb-prio-splb0 = <0x1>;
- xlnx,mplb-prio-splb1 = <0x0>;
- xlnx,mplb-read-pipe-enable = <0x1>;
- xlnx,mplb-sync-tattribute = <0x0>;
- xlnx,mplb-wdog-enable = <0x1>;
- xlnx,mplb-write-pipe-enable = <0x1>;
- xlnx,mplb-write-post-enable = <0x1>;
- xlnx,num-dma = <0x0>;
- xlnx,pir = <0xf>;
- xlnx,ppc440mc-addr-base = <0x0>;
- xlnx,ppc440mc-addr-high = <0x1fffffff>;
- xlnx,ppc440mc-arb-mode = <0x0>;
- xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
- xlnx,ppc440mc-control = <0xf810008f>;
- xlnx,ppc440mc-max-burst = <0x8>;
- xlnx,ppc440mc-prio-dcur = <0x2>;
- xlnx,ppc440mc-prio-dcuw = <0x3>;
- xlnx,ppc440mc-prio-icu = <0x4>;
- xlnx,ppc440mc-prio-splb0 = <0x1>;
- xlnx,ppc440mc-prio-splb1 = <0x0>;
- xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
- xlnx,ppcdm-asyncmode = <0x0>;
- xlnx,ppcds-asyncmode = <0x0>;
- xlnx,user-reset = <0x0>;
- } ;
- } ;
- plb_v46_0: plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
- ranges ;
- FLASH: flash@fc000000 {
- bank-width = <2>;
- compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
- reg = < 0xfc000000 0x2000000 >;
- xlnx,family = "virtex5";
- xlnx,include-datawidth-matching-0 = <0x1>;
- xlnx,include-datawidth-matching-1 = <0x0>;
- xlnx,include-datawidth-matching-2 = <0x0>;
- xlnx,include-datawidth-matching-3 = <0x0>;
- xlnx,include-negedge-ioregs = <0x0>;
- xlnx,include-plb-ipif = <0x1>;
- xlnx,include-wrbuf = <0x1>;
- xlnx,max-mem-width = <0x10>;
- xlnx,mch-native-dwidth = <0x20>;
- xlnx,mch-plb-clk-period-ps = <0x2710>;
- xlnx,mch-splb-awidth = <0x20>;
- xlnx,mch0-accessbuf-depth = <0x10>;
- xlnx,mch0-protocol = <0x0>;
- xlnx,mch0-rddatabuf-depth = <0x10>;
- xlnx,mch1-accessbuf-depth = <0x10>;
- xlnx,mch1-protocol = <0x0>;
- xlnx,mch1-rddatabuf-depth = <0x10>;
- xlnx,mch2-accessbuf-depth = <0x10>;
- xlnx,mch2-protocol = <0x0>;
- xlnx,mch2-rddatabuf-depth = <0x10>;
- xlnx,mch3-accessbuf-depth = <0x10>;
- xlnx,mch3-protocol = <0x0>;
- xlnx,mch3-rddatabuf-depth = <0x10>;
- xlnx,mem0-width = <0x10>;
- xlnx,mem1-width = <0x20>;
- xlnx,mem2-width = <0x20>;
- xlnx,mem3-width = <0x20>;
- xlnx,num-banks-mem = <0x1>;
- xlnx,num-channels = <0x2>;
- xlnx,priority-mode = <0x0>;
- xlnx,synch-mem-0 = <0x0>;
- xlnx,synch-mem-1 = <0x0>;
- xlnx,synch-mem-2 = <0x0>;
- xlnx,synch-mem-3 = <0x0>;
- xlnx,synch-pipedelay-0 = <0x2>;
- xlnx,synch-pipedelay-1 = <0x2>;
- xlnx,synch-pipedelay-2 = <0x2>;
- xlnx,synch-pipedelay-3 = <0x2>;
- xlnx,tavdv-ps-mem-0 = <0x1adb0>;
- xlnx,tavdv-ps-mem-1 = <0x3a98>;
- xlnx,tavdv-ps-mem-2 = <0x3a98>;
- xlnx,tavdv-ps-mem-3 = <0x3a98>;
- xlnx,tcedv-ps-mem-0 = <0x1adb0>;
- xlnx,tcedv-ps-mem-1 = <0x3a98>;
- xlnx,tcedv-ps-mem-2 = <0x3a98>;
- xlnx,tcedv-ps-mem-3 = <0x3a98>;
- xlnx,thzce-ps-mem-0 = <0x88b8>;
- xlnx,thzce-ps-mem-1 = <0x1b58>;
- xlnx,thzce-ps-mem-2 = <0x1b58>;
- xlnx,thzce-ps-mem-3 = <0x1b58>;
- xlnx,thzoe-ps-mem-0 = <0x1b58>;
- xlnx,thzoe-ps-mem-1 = <0x1b58>;
- xlnx,thzoe-ps-mem-2 = <0x1b58>;
- xlnx,thzoe-ps-mem-3 = <0x1b58>;
- xlnx,tlzwe-ps-mem-0 = <0x88b8>;
- xlnx,tlzwe-ps-mem-1 = <0x0>;
- xlnx,tlzwe-ps-mem-2 = <0x0>;
- xlnx,tlzwe-ps-mem-3 = <0x0>;
- xlnx,twc-ps-mem-0 = <0x1adb0>;
- xlnx,twc-ps-mem-1 = <0x3a98>;
- xlnx,twc-ps-mem-2 = <0x3a98>;
- xlnx,twc-ps-mem-3 = <0x3a98>;
- xlnx,twp-ps-mem-0 = <0x11170>;
- xlnx,twp-ps-mem-1 = <0x2ee0>;
- xlnx,twp-ps-mem-2 = <0x2ee0>;
- xlnx,twp-ps-mem-3 = <0x2ee0>;
- xlnx,xcl0-linesize = <0x4>;
- xlnx,xcl0-writexfer = <0x1>;
- xlnx,xcl1-linesize = <0x4>;
- xlnx,xcl1-writexfer = <0x1>;
- xlnx,xcl2-linesize = <0x4>;
- xlnx,xcl2-writexfer = <0x1>;
- xlnx,xcl3-linesize = <0x4>;
- xlnx,xcl3-writexfer = <0x1>;
- } ;
- Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ethernet@81c00000 {
- compatible = "xlnx,xps-ll-temac-1.01.b";
- device_type = "network";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 8 2 >;
- llink-connected = <&Hard_Ethernet_MAC_fifo>;
- local-mac-address = [ 02 00 00 00 00 00 ];
- reg = < 0x81c00000 0x40 >;
- xlnx,bus2core-clk-ratio = <0x1>;
- xlnx,phy-type = <0x3>;
- xlnx,phyaddr = <0x1>;
- xlnx,rxcsum = <0x0>;
- xlnx,rxfifo = <0x8000>;
- xlnx,temac-type = <0x0>;
- xlnx,txcsum = <0x0>;
- xlnx,txfifo = <0x8000>;
- } ;
- } ;
- Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
- compatible = "xlnx,xps-ll-fifo-1.01.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 6 2 >;
- reg = < 0x81a00000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- IIC_EEPROM: i2c@81600000 {
- compatible = "xlnx,xps-iic-2.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 9 2 >;
- reg = < 0x81600000 0x10000 >;
- xlnx,clk-freq = <0x5f5e100>;
- xlnx,family = "virtex5";
- xlnx,gpo-width = <0x1>;
- xlnx,iic-freq = <0x186a0>;
- xlnx,scl-inertial-delay = <0x5>;
- xlnx,sda-inertial-delay = <0x5>;
- xlnx,ten-bit-adr = <0x0>;
- } ;
- LCD_OPTIONAL: gpio@81420000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81420000 0x10000 >;
- xlnx,all-inputs = <0x0>;
- xlnx,all-inputs-2 = <0x0>;
- xlnx,dout-default = <0x0>;
- xlnx,dout-default-2 = <0x0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <0xb>;
- xlnx,interrupt-present = <0x0>;
- xlnx,is-bidir = <0x1>;
- xlnx,is-bidir-2 = <0x1>;
- xlnx,is-dual = <0x0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- LEDs_4Bit: gpio@81400000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81400000 0x10000 >;
- xlnx,all-inputs = <0x0>;
- xlnx,all-inputs-2 = <0x0>;
- xlnx,dout-default = <0x0>;
- xlnx,dout-default-2 = <0x0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <0x4>;
- xlnx,interrupt-present = <0x0>;
- xlnx,is-bidir = <0x1>;
- xlnx,is-bidir-2 = <0x1>;
- xlnx,is-dual = <0x0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- RS232_Uart_1: serial@83e00000 {
- clock-frequency = <100000000>;
- compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
- current-speed = <9600>;
- device_type = "serial";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 11 2 >;
- reg = < 0x83e00000 0x10000 >;
- reg-offset = <0x1003>;
- reg-shift = <2>;
- xlnx,family = "virtex5";
- xlnx,has-external-rclk = <0x0>;
- xlnx,has-external-xin = <0x0>;
- xlnx,is-a-16550 = <0x1>;
- } ;
- SPI_EEPROM: xps-spi@feff8000 {
- compatible = "xlnx,xps-spi-2.00.b";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 10 2 >;
- reg = < 0xfeff8000 0x80 >;
- xlnx,family = "virtex5";
- xlnx,fifo-exist = <0x1>;
- xlnx,num-ss-bits = <0x1>;
- xlnx,num-transfer-bits = <0x8>;
- xlnx,sck-ratio = <0x80>;
- } ;
- SysACE_CompactFlash: sysace@83600000 {
- compatible = "xlnx,xps-sysace-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 7 2 >;
- reg = < 0x83600000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,mem-width = <0x10>;
- } ;
- plbv46_pci_0: plbv46-pci@85e00000 {
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "xlnx,plbv46-pci-1.03.a";
- device_type = "pci";
- reg = < 0x85e00000 0x10000 >;
-
- /*
- * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to
- * 0 which means that a read/write to the memory mapped
- * i/o region (which starts at 0xa0000000) for pci
- * bar 0 on the plb side translates to 0.
- * It is important to set this value to 0xa0000000, so
- * that inbound and outbound pci transactions work
- * properly including DMA.
- */
- ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
- 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>;
-
- #interrupt-cells = <1>;
- interrupt-parent = <&xps_intc_0>;
- interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
- interrupt-map = <
- /* IRQ mapping for pci slots and ALI M1533
- * periperhals. In total there are 5 interrupt
- * lines connected to a xps_intc controller.
- * Four of them are PCI IRQ A, B, C, D and
- * which correspond to respectively xpx_intc
- * 5, 4, 3 and 2. The fifth interrupt line is
- * connected to the south bridge and this one
- * uses irq 1 and is active high instead of
- * active low.
- *
- * The M1533 contains various peripherals
- * including AC97 audio, a modem, USB, IDE and
- * some power management stuff. The modem
- * isn't connected on the ML510 and the power
- * management core also isn't used.
- */
-
- /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
- 0x3000 0 0 1 &xps_intc_0 3 2
- 0x3000 0 0 2 &xps_intc_0 2 2
- 0x3000 0 0 3 &xps_intc_0 5 2
- 0x3000 0 0 4 &xps_intc_0 4 2
-
- /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
- /*
- 0x11800 0 0 1 &xps_intc_0 5 0 2
- 0x11800 0 0 2 &xps_intc_0 4 0 2
- 0x11800 0 0 3 &xps_intc_0 3 0 2
- 0x11800 0 0 4 &xps_intc_0 2 0 2
- */
-
- /* According to the datasheet + schematic
- * ABCD [FPGA] of slot 5 is mapped to DABC.
- * Testing showed that at least A maps to B,
- * the mapping of the other pins is a guess
- * and for that reason the lines have been
- * commented out.
- */
- /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
- 0x2800 0 0 1 &xps_intc_0 4 2
- /*
- 0x2800 0 0 2 &xps_intc_0 3 2
- 0x2800 0 0 3 &xps_intc_0 2 2
- 0x2800 0 0 4 &xps_intc_0 5 2
- */
-
- /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
- /*
- 0x11000 0 0 1 &xps_intc_0 4 0 2
- 0x11000 0 0 2 &xps_intc_0 3 0 2
- 0x11000 0 0 3 &xps_intc_0 2 0 2
- 0x11000 0 0 4 &xps_intc_0 5 0 2
- */
-
- /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
- 0x0800 0 0 1 &i8259 7 2
-
- /* IDSEL 0x1b / dev=11, bus=0 / IDE */
- 0x5800 0 0 1 &i8259 14 2
-
- /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
- 0x7800 0 0 1 &i8259 7 2
- >;
- ali_m1533 {
- #size-cells = <1>;
- #address-cells = <2>;
- i8259: interrupt-controller@20 {
- reg = <1 0x20 2
- 1 0xa0 2
- 1 0x4d0 2>;
- interrupt-controller;
- device_type = "interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- compatible = "chrp,iic";
-
- /* south bridge irq is active high */
- interrupts = <1 3>;
- interrupt-parent = <&xps_intc_0>;
- };
- };
- } ;
- xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
- compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
- reg = < 0xffff0000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- xps_intc_0: interrupt-controller@81800000 {
- #interrupt-cells = <0x2>;
- compatible = "xlnx,xps-intc-1.00.a";
- interrupt-controller ;
- reg = < 0x81800000 0x10000 >;
- xlnx,num-intr-inputs = <0xc>;
- } ;
- xps_tft_0: tft@86e00000 {
- compatible = "xlnx,xps-tft-1.00.a";
- reg = < 0x86e00000 0x10000 >;
- xlnx,dcr-splb-slave-if = <0x1>;
- xlnx,default-tft-base-addr = <0x0>;
- xlnx,family = "virtex5";
- xlnx,i2c-slave-addr = <0x76>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-native-dwidth = <0x40>;
- xlnx,mplb-smallest-slave = <0x20>;
- xlnx,tft-interface = <0x1>;
- } ;
- } ;
-} ;
diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h
index e0606766480f..6455fc9a244f 100644
--- a/arch/powerpc/boot/ops.h
+++ b/arch/powerpc/boot/ops.h
@@ -88,7 +88,6 @@ int serial_console_init(void);
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
int cpm_console_init(void *devp, struct serial_console_data *scdp);
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp);
-int uartlite_console_init(void *devp, struct serial_console_data *scdp);
int opal_console_init(void *devp, struct serial_console_data *scdp);
void *simple_alloc_init(char *base, unsigned long heap_size,
unsigned long granularity, unsigned long max_allocs);
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index 9457863147f9..0bfa7e87e546 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -132,11 +132,6 @@ int serial_console_init(void)
else if (dt_is_compatible(devp, "fsl,mpc5200-psc-uart"))
rc = mpc5200_psc_console_init(devp, &serial_cd);
#endif
-#ifdef CONFIG_XILINX_VIRTEX
- else if (dt_is_compatible(devp, "xlnx,opb-uartlite-1.00.b") ||
- dt_is_compatible(devp, "xlnx,xps-uartlite-1.00.a"))
- rc = uartlite_console_init(devp, &serial_cd);
-#endif
#ifdef CONFIG_PPC64_BOOT_WRAPPER
else if (dt_is_compatible(devp, "ibm,opal-console-raw"))
rc = opal_console_init(devp, &serial_cd);
diff --git a/arch/powerpc/boot/uartlite.c b/arch/powerpc/boot/uartlite.c
deleted file mode 100644
index 46bed69b4169..000000000000
--- a/arch/powerpc/boot/uartlite.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Xilinx UARTLITE bootloader driver
- *
- * Copyright (C) 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include "types.h"
-#include "string.h"
-#include "stdio.h"
-#include "io.h"
-#include "ops.h"
-
-#define ULITE_RX 0x00
-#define ULITE_TX 0x04
-#define ULITE_STATUS 0x08
-#define ULITE_CONTROL 0x0c
-
-#define ULITE_STATUS_RXVALID 0x01
-#define ULITE_STATUS_TXFULL 0x08
-
-#define ULITE_CONTROL_RST_RX 0x02
-
-static void * reg_base;
-
-static int uartlite_open(void)
-{
- /* Clear the RX FIFO */
- out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX);
- return 0;
-}
-
-static void uartlite_putc(unsigned char c)
-{
- u32 reg = ULITE_STATUS_TXFULL;
- while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */
- reg = in_be32(reg_base + ULITE_STATUS);
- out_be32(reg_base + ULITE_TX, c);
-}
-
-static unsigned char uartlite_getc(void)
-{
- u32 reg = 0;
- while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */
- reg = in_be32(reg_base + ULITE_STATUS);
- return in_be32(reg_base + ULITE_RX);
-}
-
-static u8 uartlite_tstc(void)
-{
- u32 reg = in_be32(reg_base + ULITE_STATUS);
- return reg & ULITE_STATUS_RXVALID;
-}
-
-int uartlite_console_init(void *devp, struct serial_console_data *scdp)
-{
- int n;
- unsigned long reg_phys;
-
- n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base));
- if (n != sizeof(reg_base)) {
- if (!dt_xlate_reg(devp, 0, ®_phys, NULL))
- return -1;
-
- reg_base = (void *)reg_phys;
- }
-
- scdp->open = uartlite_open;
- scdp->putc = uartlite_putc;
- scdp->getc = uartlite_getc;
- scdp->tstc = uartlite_tstc;
- scdp->close = NULL;
- return 0;
-}
diff --git a/arch/powerpc/boot/virtex.c b/arch/powerpc/boot/virtex.c
deleted file mode 100644
index f731cbb4bff0..000000000000
--- a/arch/powerpc/boot/virtex.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * The platform specific code for virtex devices since a boot loader is not
- * always used.
- *
- * (C) Copyright 2008 Xilinx, Inc.
- */
-
-#include "ops.h"
-#include "io.h"
-#include "stdio.h"
-
-#define UART_DLL 0 /* Out: Divisor Latch Low */
-#define UART_DLM 1 /* Out: Divisor Latch High */
-#define UART_FCR 2 /* Out: FIFO Control Register */
-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define UART_LCR 3 /* Out: Line Control Register */
-#define UART_MCR 4 /* Out: Modem Control Register */
-#define UART_MCR_RTS 0x02 /* RTS complement */
-#define UART_MCR_DTR 0x01 /* DTR complement */
-#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-
-static int virtex_ns16550_console_init(void *devp)
-{
- unsigned char *reg_base;
- u32 reg_shift, reg_offset, clk, spd;
- u16 divisor;
- int n;
-
- if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1)
- return -1;
-
- n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset));
- if (n == sizeof(reg_offset))
- reg_base += reg_offset;
-
- n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift));
- if (n != sizeof(reg_shift))
- reg_shift = 0;
-
- n = getprop(devp, "current-speed", (void *)&spd, sizeof(spd));
- if (n != sizeof(spd))
- spd = 9600;
-
- /* should there be a default clock rate?*/
- n = getprop(devp, "clock-frequency", (void *)&clk, sizeof(clk));
- if (n != sizeof(clk))
- return -1;
-
- divisor = clk / (16 * spd);
-
- /* Access baud rate */
- out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB);
-
- /* Baud rate based on input clock */
- out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF);
- out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8);
-
- /* 8 data, 1 stop, no parity */
- out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8);
-
- /* RTS/DTR */
- out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR);
-
- /* Clear transmitter and receiver */
- out_8(reg_base + (UART_FCR << reg_shift),
- UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
- return 0;
-}
-
-/* For virtex, the kernel may be loaded without using a bootloader and if so
- some UARTs need more setup than is provided in the normal console init
-*/
-int platform_specific_init(void)
-{
- void *devp;
- char devtype[MAX_PROP_LEN];
- char path[MAX_PATH_LEN];
-
- devp = finddevice("/chosen");
- if (devp == NULL)
- return -1;
-
- if (getprop(devp, "linux,stdout-path", path, MAX_PATH_LEN) > 0) {
- devp = finddevice(path);
- if (devp == NULL)
- return -1;
-
- if ((getprop(devp, "device_type", devtype, sizeof(devtype)) > 0)
- && !strcmp(devtype, "serial")
- && (dt_is_compatible(devp, "ns16550")))
- virtex_ns16550_console_init(devp);
- }
- return 0;
-}
diff --git a/arch/powerpc/boot/virtex405-head.S b/arch/powerpc/boot/virtex405-head.S
deleted file mode 100644
index 00bab7d7c48c..000000000000
--- a/arch/powerpc/boot/virtex405-head.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include "ppc_asm.h"
-
- .text
- .global _zimage_start
-_zimage_start:
-
- /* PPC errata 213: needed by Virtex-4 FX */
- mfccr0 0
- oris 0,0,0x50000000@h
- mtccr0 0
-
- /*
- * Invalidate the data cache if the data cache is turned off.
- * - The 405 core does not invalidate the data cache on power-up
- * or reset but does turn off the data cache. We cannot assume
- * that the cache contents are valid.
- * - If the data cache is turned on this must have been done by
- * a bootloader and we assume that the cache contents are
- * valid.
- */
- mfdccr r9
- cmplwi r9,0
- bne 2f
- lis r9,0
- li r8,256
- mtctr r8
-1: dccci r0,r9
- addi r9,r9,0x20
- bdnz 1b
-2: b _zimage_start_lib
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index ed6266367bc0..de5fd5a047e8 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -323,14 +323,6 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
-simpleboot-virtex405-*)
- platformo="$object/virtex405-head.o $object/simpleboot.o $object/virtex.o"
- binary=y
- ;;
-simpleboot-virtex440-*)
- platformo="$object/fixed-head.o $object/simpleboot.o $object/virtex.o"
- binary=y
- ;;
simpleboot-*)
platformo="$object/fixed-head.o $object/simpleboot.o"
binary=y
diff --git a/arch/powerpc/configs/40x/virtex_defconfig b/arch/powerpc/configs/40x/virtex_defconfig
deleted file mode 100644
index 5e7c61d1d7d0..000000000000
--- a/arch/powerpc/configs/40x/virtex_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_40x=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_WALNUT is not set
-CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
-CONFIG_PREEMPT=y
-CONFIG_MATH_EMULATION=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE=""
-CONFIG_PCI=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_XILINX_SYSACE=y
-CONFIG_NETDEVICES=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
-CONFIG_XILINX_HWICAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_XILINX=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRC_CCITT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/powerpc/configs/44x/virtex5_defconfig b/arch/powerpc/configs/44x/virtex5_defconfig
deleted file mode 100644
index 1f74079e1703..000000000000
--- a/arch/powerpc/configs/44x/virtex5_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_44x=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_EBONY is not set
-CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y
-CONFIG_PREEMPT=y
-CONFIG_MATH_EMULATION=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE=""
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_XILINX_SYSACE=y
-CONFIG_NETDEVICES=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
-CONFIG_XILINX_HWICAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_XILINX=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRC_CCITT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/powerpc/configs/ppc40x_defconfig b/arch/powerpc/configs/ppc40x_defconfig
index a5f683aed328..88960a72b525 100644
--- a/arch/powerpc/configs/ppc40x_defconfig
+++ b/arch/powerpc/configs/ppc40x_defconfig
@@ -14,7 +14,6 @@ CONFIG_EP405=y
CONFIG_HOTFOOT=y
CONFIG_KILAUEA=y
CONFIG_MAKALU=y
-CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -37,33 +36,26 @@ CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
-CONFIG_XILINX_SYSACE=m
CONFIG_NETDEVICES=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=m
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
# CONFIG_HW_RANDOM is not set
-CONFIG_XILINX_HWICAP=m
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_IBM_IIC=m
-CONFIG_GPIO_XILINX=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=y
CONFIG_FB=m
-CONFIG_FB_XILINX=m
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=m
CONFIG_VFAT_FS=m
diff --git a/arch/powerpc/configs/ppc44x_defconfig b/arch/powerpc/configs/ppc44x_defconfig
index a41eedfe0a5f..8b595f67068c 100644
--- a/arch/powerpc/configs/ppc44x_defconfig
+++ b/arch/powerpc/configs/ppc44x_defconfig
@@ -22,7 +22,6 @@ CONFIG_GLACIER=y
CONFIG_REDWOOD=y
CONFIG_EIGER=y
CONFIG_YOSEMITE=y
-CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y
CONFIG_PPC4xx_GPIO=y
CONFIG_MATH_EMULATION=y
CONFIG_NET=y
@@ -46,7 +45,6 @@ CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
-CONFIG_XILINX_SYSACE=m
CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m
# CONFIG_SCSI_LOWLEVEL is not set
@@ -57,7 +55,6 @@ CONFIG_IBM_EMAC=y
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=m
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
@@ -65,18 +62,13 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
# CONFIG_HW_RANDOM is not set
-CONFIG_XILINX_HWICAP=m
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_IBM_IIC=m
-CONFIG_GPIO_XILINX=y
# CONFIG_HWMON is not set
CONFIG_FB=m
-CONFIG_FB_XILINX=m
CONFIG_USB=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_OHCI_HCD=m
diff --git a/arch/powerpc/include/asm/xilinx_intc.h b/arch/powerpc/include/asm/xilinx_intc.h
deleted file mode 100644
index ca9aa162fb09..000000000000
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Xilinx intc external definitions
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- */
-#ifndef _ASM_POWERPC_XILINX_INTC_H
-#define _ASM_POWERPC_XILINX_INTC_H
-
-#ifdef __KERNEL__
-
-extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xintc_get_irq(void);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/include/asm/xilinx_pci.h b/arch/powerpc/include/asm/xilinx_pci.h
deleted file mode 100644
index 7a8275caf6af..000000000000
--- a/arch/powerpc/include/asm/xilinx_pci.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Xilinx pci external definitions
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef INCLUDE_XILINX_PCI
-#define INCLUDE_XILINX_PCI
-
-#ifdef CONFIG_XILINX_PCI
-extern void __init xilinx_pci_init(void);
-#else
-static inline void __init xilinx_pci_init(void) { return; }
-#endif
-
-#endif /* INCLUDE_XILINX_PCI */
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 245be4fafe13..2dff9041bcdc 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1385,32 +1385,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
- { /* Xilinx Virtex-II Pro */
- .pvr_mask = 0xfffff000,
- .pvr_value = 0x20010000,
- .cpu_name = "Virtex-II Pro",
- .cpu_features = CPU_FTRS_40X,
- .cpu_user_features = PPC_FEATURE_32 |
- PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
- .mmu_features = MMU_FTR_TYPE_40x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .machine_check = machine_check_4xx,
- .platform = "ppc405",
- },
- { /* Xilinx Virtex-4 FX */
- .pvr_mask = 0xfffff000,
- .pvr_value = 0x20011000,
- .cpu_name = "Virtex-4 FX",
- .cpu_features = CPU_FTRS_40X,
- .cpu_user_features = PPC_FEATURE_32 |
- PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
- .mmu_features = MMU_FTR_TYPE_40x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .machine_check = machine_check_4xx,
- .platform = "ppc405",
- },
{ /* 405EP */
.pvr_mask = 0xffff0000,
.pvr_value = 0x51210000,
@@ -1800,19 +1774,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = "ppc440",
},
- { /* 440 in Xilinx Virtex-5 FXT */
- .pvr_mask = 0xfffffff0,
- .pvr_value = 0x7ff21910,
- .cpu_name = "440 in Virtex-5 FXT",
- .cpu_features = CPU_FTRS_44X,
- .cpu_user_features = COMMON_USER_BOOKE,
- .mmu_features = MMU_FTR_TYPE_44x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .cpu_setup = __setup_cpu_440x5,
- .machine_check = machine_check_440A,
- .platform = "ppc440",
- },
{ /* 460EX */
.pvr_mask = 0xffff0006,
.pvr_value = 0x13020002,
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index 6da813b65b42..d06ca51e8443 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -55,23 +55,6 @@ config WALNUT
help
This option enables support for the IBM PPC405GP evaluation board.
-config XILINX_VIRTEX_GENERIC_BOARD
- bool "Generic Xilinx Virtex board"
- depends on 40x
- select XILINX_VIRTEX_II_PRO
- select XILINX_VIRTEX_4_FX
- select XILINX_INTC
- help
- This option enables generic support for Xilinx Virtex based boards.
-
- The generic virtex board support matches any device tree which
- specifies 'xilinx,virtex' in its compatible field. This includes
- the Xilinx ML3xx and ML4xx reference designs using the powerpc
- core.
-
- Most Virtex designs should use this unless it needs to do some
- special configuration at board probe time.
-
config OBS600
bool "OpenBlockS 600"
depends on 40x
@@ -109,20 +92,6 @@ config 405EZ
select IBM_EMAC_MAL_CLR_ICINTSTAT if IBM_EMAC
select IBM_EMAC_MAL_COMMON_ERR if IBM_EMAC
-config XILINX_VIRTEX
- bool
- select DEFAULT_UIMAGE
-
-config XILINX_VIRTEX_II_PRO
- bool
- select XILINX_VIRTEX
- select IBM405_ERR77
- select IBM405_ERR51
-
-config XILINX_VIRTEX_4_FX
- bool
- select XILINX_VIRTEX
-
config STB03xxx
bool
select IBM405_ERR77
diff --git a/arch/powerpc/platforms/40x/Makefile b/arch/powerpc/platforms/40x/Makefile
index 828d78340dd9..e9386deed505 100644
--- a/arch/powerpc/platforms/40x/Makefile
+++ b/arch/powerpc/platforms/40x/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_WALNUT) += walnut.o
-obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD) += virtex.o
obj-$(CONFIG_EP405) += ep405.o
obj-$(CONFIG_PPC40x_SIMPLE) += ppc40x_simple.o
diff --git a/arch/powerpc/platforms/40x/virtex.c b/arch/powerpc/platforms/40x/virtex.c
deleted file mode 100644
index e3d5e095846b..000000000000
--- a/arch/powerpc/platforms/40x/virtex.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Xilinx Virtex (IIpro & 4FX) based board support
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <asm/xilinx_intc.h>
-#include <asm/xilinx_pci.h>
-#include <asm/ppc4xx.h>
-
-static const struct of_device_id xilinx_of_bus_ids[] __initconst = {
- { .compatible = "xlnx,plb-v46-1.00.a", },
- { .compatible = "xlnx,plb-v34-1.01.a", },
- { .compatible = "xlnx,plb-v34-1.02.a", },
- { .compatible = "xlnx,opb-v20-1.10.c", },
- { .compatible = "xlnx,dcr-v29-1.00.a", },
- { .compatible = "xlnx,compound", },
- {}
-};
-
-static int __init virtex_device_probe(void)
-{
- of_platform_bus_probe(NULL, xilinx_of_bus_ids, NULL);
-
- return 0;
-}
-machine_device_initcall(virtex, virtex_device_probe);
-
-static int __init virtex_probe(void)
-{
- if (!of_machine_is_compatible("xlnx,virtex"))
- return 0;
-
- return 1;
-}
-
-define_machine(virtex) {
- .name = "Xilinx Virtex",
- .probe = virtex_probe,
- .setup_arch = xilinx_pci_init,
- .init_IRQ = xilinx_intc_init_tree,
- .get_irq = xintc_get_irq,
- .restart = ppc4xx_reset_system,
- .calibrate_decr = generic_calibrate_decr,
-};
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 25ebe634a661..39e93d23fb38 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -232,33 +232,6 @@ config ICON
help
This option enables support for the AMCC PPC440SPe evaluation board.
-config XILINX_VIRTEX440_GENERIC_BOARD
- bool "Generic Xilinx Virtex 5 FXT board support"
- depends on 44x
- select XILINX_VIRTEX_5_FXT
- select XILINX_INTC
- help
- This option enables generic support for Xilinx Virtex based boards
- that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
-
- The generic virtex board support matches any device tree which
- specifies 'xlnx,virtex440' in its compatible field. This includes
- the Xilinx ML5xx reference designs using the powerpc core.
-
- Most Virtex 5 designs should use this unless it needs to do some
- special configuration at board probe time.
-
-config XILINX_ML510
- bool "Xilinx ML510 extra support"
- depends on XILINX_VIRTEX440_GENERIC_BOARD
- select HAVE_PCI
- select XILINX_PCI if PCI
- select PPC_INDIRECT_PCI if PCI
- select PPC_I8259 if PCI
- help
- This option enables extra support for features on the Xilinx ML510
- board. The ML510 has a PCI bus with ALI south bridge.
-
config PPC44x_SIMPLE
bool "Simple PowerPC 44x board support"
depends on 44x
@@ -354,13 +327,3 @@ config 476FPE_ERR46
config IBM440EP_ERR42
bool
-# Xilinx specific config options.
-config XILINX_VIRTEX
- bool
- select DEFAULT_UIMAGE
-
-# Xilinx Virtex 5 FXT FPGA architecture, selected by a Xilinx board above
-config XILINX_VIRTEX_5_FXT
- bool
- select XILINX_VIRTEX
-
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 1b78c6af821a..5ba031f57652 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -7,8 +7,6 @@ obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_SAM440EP) += sam440ep.o
obj-$(CONFIG_WARP) += warp.o
-obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
-obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
obj-$(CONFIG_ISS4xx) += iss4xx.o
obj-$(CONFIG_CANYONLANDS)+= canyonlands.o
obj-$(CONFIG_CURRITUCK) += ppc476.o
diff --git a/arch/powerpc/platforms/44x/virtex.c b/arch/powerpc/platforms/44x/virtex.c
deleted file mode 100644
index 3eb13ed926ee..000000000000
--- a/arch/powerpc/platforms/44x/virtex.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Xilinx Virtex 5FXT based board support, derived from
- * the Xilinx Virtex (IIpro & 4FX) based board support
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- * Copyright 2008 Xilinx, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <asm/xilinx_intc.h>
-#include <asm/xilinx_pci.h>
-#include <asm/reg.h>
-#include <asm/ppc4xx.h>
-#include "44x.h"
-
-static const struct of_device_id xilinx_of_bus_ids[] __initconst = {
- { .compatible = "simple-bus", },
- { .compatible = "xlnx,plb-v46-1.00.a", },
- { .compatible = "xlnx,plb-v46-1.02.a", },
- { .compatible = "xlnx,plb-v34-1.01.a", },
- { .compatible = "xlnx,plb-v34-1.02.a", },
- { .compatible = "xlnx,opb-v20-1.10.c", },
- { .compatible = "xlnx,dcr-v29-1.00.a", },
- { .compatible = "xlnx,compound", },
- {}
-};
-
-static int __init virtex_device_probe(void)
-{
- of_platform_bus_probe(NULL, xilinx_of_bus_ids, NULL);
-
- return 0;
-}
-machine_device_initcall(virtex, virtex_device_probe);
-
-static int __init virtex_probe(void)
-{
- if (!of_machine_is_compatible("xlnx,virtex440"))
- return 0;
-
- return 1;
-}
-
-define_machine(virtex) {
- .name = "Xilinx Virtex440",
- .probe = virtex_probe,
- .setup_arch = xilinx_pci_init,
- .init_IRQ = xilinx_intc_init_tree,
- .get_irq = xintc_get_irq,
- .calibrate_decr = generic_calibrate_decr,
- .restart = ppc4xx_reset_system,
-};
diff --git a/arch/powerpc/platforms/44x/virtex_ml510.c b/arch/powerpc/platforms/44x/virtex_ml510.c
deleted file mode 100644
index 349f218b335c..000000000000
--- a/arch/powerpc/platforms/44x/virtex_ml510.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <asm/i8259.h>
-#include <linux/pci.h>
-#include "44x.h"
-
-/**
- * ml510_ail_quirk
- */
-static void ml510_ali_quirk(struct pci_dev *dev)
-{
- /* Enable the IDE controller */
- pci_write_config_byte(dev, 0x58, 0x4c);
- /* Assign irq 14 to the primary ide channel */
- pci_write_config_byte(dev, 0x44, 0x0d);
- /* Assign irq 15 to the secondary ide channel */
- pci_write_config_byte(dev, 0x75, 0x0f);
- /* Set the ide controller in native mode */
- pci_write_config_byte(dev, 0x09, 0xff);
-
- /* INTB = disabled, INTA = disabled */
- pci_write_config_byte(dev, 0x48, 0x00);
- /* INTD = disabled, INTC = disabled */
- pci_write_config_byte(dev, 0x4a, 0x00);
- /* Audio = INT7, Modem = disabled. */
- pci_write_config_byte(dev, 0x4b, 0x60);
- /* USB = INT7 */
- pci_write_config_byte(dev, 0x74, 0x06);
-}
-DECLARE_PCI_FIXUP_EARLY(0x10b9, 0x1533, ml510_ali_quirk);
-
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 1f8025383caa..5e6479d409a0 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -317,8 +317,4 @@ config MCU_MPC8349EMITX
also register MCU GPIOs with the generic GPIO API, so you'll able
to use MCU pins as GPIOs.
-config XILINX_PCI
- bool "Xilinx PCI host bridge support"
- depends on PCI && XILINX_VIRTEX
-
endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cb5a5bd2cef5..026b3f01a991 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -31,8 +31,6 @@ obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_IPIC) += ipic.o
-obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
-obj-$(CONFIG_XILINX_PCI) += xilinx_pci.o
obj-$(CONFIG_OF_RTC) += of_rtc.o
obj-$(CONFIG_CPM) += cpm_common.o
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
deleted file mode 100644
index 4a86dcff3fcd..000000000000
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Interrupt controller driver for Xilinx Virtex FPGAs
- *
- * Copyright (C) 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
- */
-
-/*
- * This is a driver for the interrupt controller typically found in
- * Xilinx Virtex FPGA designs.
- *
- * The interrupt sense levels are hard coded into the FPGA design with
- * typically a 1:1 relationship between irq lines and devices (no shared
- * irq lines). Therefore, this driver does not attempt to handle edge
- * and level interrupts differently.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/i8259.h>
-#include <asm/irq.h>
-#include <linux/irqchip.h>
-
-#if defined(CONFIG_PPC_I8259)
-/*
- * Support code for cascading to 8259 interrupt controllers
- */
-static void xilinx_i8259_cascade(struct irq_desc *desc)
-{
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned int cascade_irq = i8259_irq();
-
- if (cascade_irq)
- generic_handle_irq(cascade_irq);
-
- /* Let xilinx_intc end the interrupt */
- chip->irq_unmask(&desc->irq_data);
-}
-
-static void __init xilinx_i8259_setup_cascade(void)
-{
- struct device_node *cascade_node;
- int cascade_irq;
-
- /* Initialize i8259 controller */
- cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
- if (!cascade_node)
- return;
-
- cascade_irq = irq_of_parse_and_map(cascade_node, 0);
- if (!cascade_irq) {
- pr_err("virtex_ml510: Failed to map cascade interrupt\n");
- goto out;
- }
-
- i8259_init(cascade_node, 0);
- irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
-
- /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
- /* This looks like a dirty hack to me --gcl */
- outb(0xc0, 0x4d0);
- outb(0xc0, 0x4d1);
-
- out:
- of_node_put(cascade_node);
-}
-#else
-static inline void xilinx_i8259_setup_cascade(void) { return; }
-#endif /* defined(CONFIG_PPC_I8259) */
-
-/*
- * Initialize master Xilinx interrupt controller
- */
-void __init xilinx_intc_init_tree(void)
-{
- irqchip_init();
- xilinx_i8259_setup_cascade();
-}
diff --git a/arch/powerpc/sysdev/xilinx_pci.c b/arch/powerpc/sysdev/xilinx_pci.c
deleted file mode 100644
index fea5667699ed..000000000000
--- a/arch/powerpc/sysdev/xilinx_pci.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * PCI support for Xilinx plbv46_pci soft-core which can be used on
- * Xilinx Virtex ML410 / ML510 boards.
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
- * by Benjamin Herrenschmidt.
- * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/ioport.h>
-#include <linux/of.h>
-#include <linux/pci.h>
-#include <mm/mmu_decl.h>
-#include <asm/io.h>
-#include <asm/xilinx_pci.h>
-
-#define XPLB_PCI_ADDR 0x10c
-#define XPLB_PCI_DATA 0x110
-#define XPLB_PCI_BUS 0x114
-
-#define PCI_HOST_ENABLE_CMD PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
-
-static const struct of_device_id xilinx_pci_match[] = {
- { .compatible = "xlnx,plbv46-pci-1.03.a", },
- {}
-};
-
-/**
- * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
- */
-static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
-{
- struct pci_controller *hose;
- int i;
-
- if (dev->devfn || dev->bus->self)
- return;
-
- hose = pci_bus_to_host(dev->bus);
- if (!hose)
- return;
-
- if (!of_match_node(xilinx_pci_match, hose->dn))
- return;
-
- /* Hide the PCI host BARs from the kernel as their content doesn't
- * fit well in the resource management
- */
- for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
- }
-
- dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
- pci_name(dev));
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
-
-/**
- * xilinx_pci_exclude_device - Don't do config access for non-root bus
- *
- * This is a hack. Config access to any bus other than bus 0 does not
- * currently work on the ML510 so we prevent it here.
- */
-static int
-xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
-{
- return (bus != 0);
-}
-
-/**
- * xilinx_pci_init - Find and register a Xilinx PCI host bridge
- */
-void __init xilinx_pci_init(void)
-{
- struct pci_controller *hose;
- struct resource r;
- void __iomem *pci_reg;
- struct device_node *pci_node;
-
- pci_node = of_find_matching_node(NULL, xilinx_pci_match);
- if(!pci_node)
- return;
-
- if (of_address_to_resource(pci_node, 0, &r)) {
- pr_err("xilinx-pci: cannot resolve base address\n");
- return;
- }
-
- hose = pcibios_alloc_controller(pci_node);
- if (!hose) {
- pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
- return;
- }
-
- /* Setup config space */
- setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
- r.start + XPLB_PCI_DATA,
- PPC_INDIRECT_TYPE_SET_CFG_TYPE);
-
- /* According to the xilinx plbv46_pci documentation the soft-core starts
- * a self-init when the bus master enable bit is set. Without this bit
- * set the pci bus can't be scanned.
- */
- early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
-
- /* Set the max latency timer to 255 */
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
-
- /* Set the max bus number to 255 */
- pci_reg = of_iomap(pci_node, 0);
- out_8(pci_reg + XPLB_PCI_BUS, 0xff);
- iounmap(pci_reg);
-
- /* Nothing past the root bridge is working right now. By default
- * exclude config access to anything except bus 0 */
- if (!ppc_md.pci_exclude_device)
- ppc_md.pci_exclude_device = xilinx_pci_exclude_device;
-
- /* Register the host bridge with the linux kernel! */
- pci_process_bridge_OF_ranges(hose, pci_node, 1);
-
- pr_info("xilinx-pci: Registered PCI host bridge\n");
-}
diff --git a/arch/powerpc/xmon/ppc-dis.c b/arch/powerpc/xmon/ppc-dis.c
index 75fa98221d48..a91ac589b401 100644
--- a/arch/powerpc/xmon/ppc-dis.c
+++ b/arch/powerpc/xmon/ppc-dis.c
@@ -224,12 +224,6 @@ int print_insn_powerpc (unsigned long insn, unsigned long memaddr)
print_address(memaddr + value);
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
print_address(value & 0xffffffff);
- else if ((operand->flags & PPC_OPERAND_FSL) != 0)
- printf("fsl%ld", value);
- else if ((operand->flags & PPC_OPERAND_FCR) != 0)
- printf("fcr%ld", value);
- else if ((operand->flags & PPC_OPERAND_UDI) != 0)
- printf("%ld", value);
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
index dfb80810b16c..918845e777fd 100644
--- a/arch/powerpc/xmon/ppc-opc.c
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -857,29 +857,6 @@ const struct powerpc_operand powerpc_operands[] =
#define HTM_A XFL_L
{ 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
- /* Xilinx APU related masks and macros */
-#define FCRT XFL_L + 1
-#define FCRT_MASK (0x1f << 21)
- { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
-
- /* Xilinx FSL related masks and macros */
-#define FSL FCRT + 1
-#define FSL_MASK (0x1f << 11)
- { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
-
- /* Xilinx UDI related masks and macros */
-#define URT FSL + 1
- { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
-
-#define URA URT + 1
- { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
-
-#define URB URA + 1
- { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
-
-#define URC URB + 1
- { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
-
/* The VLESIMM field in a D form instruction. */
#define VLESIMM URC + 1
{ 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
diff --git a/arch/powerpc/xmon/ppc.h b/arch/powerpc/xmon/ppc.h
index d00f33dcf192..37717b1f7bd7 100644
--- a/arch/powerpc/xmon/ppc.h
+++ b/arch/powerpc/xmon/ppc.h
@@ -388,11 +388,6 @@ extern const unsigned int num_powerpc_operands;
/* Valid range of operand is 0..n rather than 0..n-1. */
#define PPC_OPERAND_PLUS1 (0x10000)
-/* Xilinx APU and FSL related operands */
-#define PPC_OPERAND_FSL (0x20000)
-#define PPC_OPERAND_FCR (0x40000)
-#define PPC_OPERAND_UDI (0x80000)
-
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 26956c006987..0ccbd6fd6de1 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -316,7 +316,7 @@ config DTLK
config XILINX_HWICAP
tristate "Xilinx HWICAP Support"
- depends on XILINX_VIRTEX || MICROBLAZE
+ depends on MICROBLAZE
help
This option enables support for Xilinx Internal Configuration
Access Port (ICAP) driver. The ICAP is used on Xilinx Virtex
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index f65991a67af2..b174650e0f09 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -2007,7 +2007,7 @@ config FB_PS3_DEFAULT_SIZE_M
config FB_XILINX
tristate "Xilinx frame buffer support"
- depends on FB && (XILINX_VIRTEX || MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ depends on FB && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
--
2.26.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 2/2] powerpc: Remove Xilinx PPC405/PPC440 support
@ 2020-03-27 12:12 ` Michal Simek
0 siblings, 0 replies; 104+ messages in thread
From: Michal Simek @ 2020-03-27 12:12 UTC (permalink / raw)
To: linux-kernel, monstr, michal.simek, git, sfr, marc.zyngier
Cc: Kate Stewart, Mark Rutland, Desnes A. Nunes do Rosario,
Geert Uytterhoeven, linux-doc, linux-fbdev, dri-devel,
Richard Fontana, Paul Mackerras, Miquel Raynal,
Mauro Carvalho Chehab, Fabio Estevam, Sasha Levin,
Jonathan Corbet, Masahiro Yamada, YueHaibing,
Krzysztof Kozlowski, linux-arm-kernel, Leonardo Bras, devicetree,
Andrew Donnellan, Arnd Bergmann, Bartlomiej Zolnierkiewicz,
Alistair Popple, linuxppc-dev, Nicholas Piggin, Alexios Zavras,
Rob Herring, Jonathan Cameron, Thomas Gleixner, Andy Shevchenko,
Allison Randal, Wei Hu, Greg Kroah-Hartman, Nick Desaulniers,
Armijn Hemel, Enrico Weigelt, David S. Miller,
Thiago Jung Bauermann
The latest Xilinx design tools called ISE and EDK has been released in
October 2013. New tool doesn't support any PPC405/PPC440 new designs.
These platforms are no longer supported and tested.
PowerPC 405/440 port is orphan from 2013 by
commit cdeb89943bfc ("MAINTAINERS: Fix incorrect status tag") and
commit 19624236cce1 ("MAINTAINERS: Update Grant's email address and maintainership")
that's why it is time to remove the support fot these platforms.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Documentation/devicetree/bindings/xilinx.txt | 143 ------
Documentation/powerpc/bootwrapper.rst | 28 +-
MAINTAINERS | 6 -
arch/powerpc/Kconfig.debug | 2 +-
arch/powerpc/boot/Makefile | 7 +-
arch/powerpc/boot/dts/Makefile | 1 -
arch/powerpc/boot/dts/virtex440-ml507.dts | 406 ----------------
arch/powerpc/boot/dts/virtex440-ml510.dts | 466 -------------------
arch/powerpc/boot/ops.h | 1 -
arch/powerpc/boot/serial.c | 5 -
arch/powerpc/boot/uartlite.c | 79 ----
arch/powerpc/boot/virtex.c | 97 ----
arch/powerpc/boot/virtex405-head.S | 31 --
arch/powerpc/boot/wrapper | 8 -
arch/powerpc/configs/40x/virtex_defconfig | 75 ---
arch/powerpc/configs/44x/virtex5_defconfig | 74 ---
arch/powerpc/configs/ppc40x_defconfig | 8 -
arch/powerpc/configs/ppc44x_defconfig | 8 -
arch/powerpc/include/asm/xilinx_intc.h | 16 -
arch/powerpc/include/asm/xilinx_pci.h | 21 -
arch/powerpc/kernel/cputable.c | 39 --
arch/powerpc/platforms/40x/Kconfig | 31 --
arch/powerpc/platforms/40x/Makefile | 1 -
arch/powerpc/platforms/40x/virtex.c | 54 ---
arch/powerpc/platforms/44x/Kconfig | 37 --
arch/powerpc/platforms/44x/Makefile | 2 -
arch/powerpc/platforms/44x/virtex.c | 60 ---
arch/powerpc/platforms/44x/virtex_ml510.c | 30 --
arch/powerpc/platforms/Kconfig | 4 -
arch/powerpc/sysdev/Makefile | 2 -
arch/powerpc/sysdev/xilinx_intc.c | 88 ----
arch/powerpc/sysdev/xilinx_pci.c | 132 ------
arch/powerpc/xmon/ppc-dis.c | 6 -
arch/powerpc/xmon/ppc-opc.c | 23 -
arch/powerpc/xmon/ppc.h | 5 -
drivers/char/Kconfig | 2 +-
drivers/video/fbdev/Kconfig | 2 +-
37 files changed, 7 insertions(+), 1993 deletions(-)
delete mode 100644 arch/powerpc/boot/dts/virtex440-ml507.dts
delete mode 100644 arch/powerpc/boot/dts/virtex440-ml510.dts
delete mode 100644 arch/powerpc/boot/uartlite.c
delete mode 100644 arch/powerpc/boot/virtex.c
delete mode 100644 arch/powerpc/boot/virtex405-head.S
delete mode 100644 arch/powerpc/configs/40x/virtex_defconfig
delete mode 100644 arch/powerpc/configs/44x/virtex5_defconfig
delete mode 100644 arch/powerpc/include/asm/xilinx_intc.h
delete mode 100644 arch/powerpc/include/asm/xilinx_pci.h
delete mode 100644 arch/powerpc/platforms/40x/virtex.c
delete mode 100644 arch/powerpc/platforms/44x/virtex.c
delete mode 100644 arch/powerpc/platforms/44x/virtex_ml510.c
delete mode 100644 arch/powerpc/sysdev/xilinx_intc.c
delete mode 100644 arch/powerpc/sysdev/xilinx_pci.c
diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt
index d058ace29345..28199b31fe5e 100644
--- a/Documentation/devicetree/bindings/xilinx.txt
+++ b/Documentation/devicetree/bindings/xilinx.txt
@@ -86,149 +86,6 @@
xlnx,use-parity = <0>;
};
- Some IP cores actually implement 2 or more logical devices. In
- this case, the device should still describe the whole IP core with
- a single node and add a child node for each logical device. The
- ranges property can be used to translate from parent IP-core to the
- registers of each device. In addition, the parent node should be
- compatible with the bus type 'xlnx,compound', and should contain
- #address-cells and #size-cells, as with any other bus. (Note: this
- makes the assumption that both logical devices have the same bus
- binding. If this is not true, then separate nodes should be used
- for each logical device). The 'cell-index' property can be used to
- enumerate logical devices within an IP core. For example, the
- following is the system.mhs entry for the dual ps2 controller found
- on the ml403 reference design.
-
- BEGIN opb_ps2_dual_ref
- PARAMETER INSTANCE = opb_ps2_dual_ref_0
- PARAMETER HW_VER = 1.00.a
- PARAMETER C_BASEADDR = 0xA9000000
- PARAMETER C_HIGHADDR = 0xA9001FFF
- BUS_INTERFACE SOPB = opb_v20_0
- PORT Sys_Intr1 = ps2_1_intr
- PORT Sys_Intr2 = ps2_2_intr
- PORT Clkin1 = ps2_clk_rx_1
- PORT Clkin2 = ps2_clk_rx_2
- PORT Clkpd1 = ps2_clk_tx_1
- PORT Clkpd2 = ps2_clk_tx_2
- PORT Rx1 = ps2_d_rx_1
- PORT Rx2 = ps2_d_rx_2
- PORT Txpd1 = ps2_d_tx_1
- PORT Txpd2 = ps2_d_tx_2
- END
-
- It would result in the following device tree nodes:
-
- opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ranges = <0 a9000000 2000>;
- // If this device had extra parameters, then they would
- // go here.
- ps2@0 {
- compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
- reg = <0 40>;
- interrupt-parent = <&opb_intc_0>;
- interrupts = <3 0>;
- cell-index = <0>;
- };
- ps2@1000 {
- compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
- reg = <1000 40>;
- interrupt-parent = <&opb_intc_0>;
- interrupts = <3 0>;
- cell-index = <0>;
- };
- };
-
- Also, the system.mhs file defines bus attachments from the processor
- to the devices. The device tree structure should reflect the bus
- attachments. Again an example; this system.mhs fragment:
-
- BEGIN ppc405_virtex4
- PARAMETER INSTANCE = ppc405_0
- PARAMETER HW_VER = 1.01.a
- BUS_INTERFACE DPLB = plb_v34_0
- BUS_INTERFACE IPLB = plb_v34_0
- END
-
- BEGIN opb_intc
- PARAMETER INSTANCE = opb_intc_0
- PARAMETER HW_VER = 1.00.c
- PARAMETER C_BASEADDR = 0xD1000FC0
- PARAMETER C_HIGHADDR = 0xD1000FDF
- BUS_INTERFACE SOPB = opb_v20_0
- END
-
- BEGIN opb_uart16550
- PARAMETER INSTANCE = opb_uart16550_0
- PARAMETER HW_VER = 1.00.d
- PARAMETER C_BASEADDR = 0xa0000000
- PARAMETER C_HIGHADDR = 0xa0001FFF
- BUS_INTERFACE SOPB = opb_v20_0
- END
-
- BEGIN plb_v34
- PARAMETER INSTANCE = plb_v34_0
- PARAMETER HW_VER = 1.02.a
- END
-
- BEGIN plb_bram_if_cntlr
- PARAMETER INSTANCE = plb_bram_if_cntlr_0
- PARAMETER HW_VER = 1.00.b
- PARAMETER C_BASEADDR = 0xFFFF0000
- PARAMETER C_HIGHADDR = 0xFFFFFFFF
- BUS_INTERFACE SPLB = plb_v34_0
- END
-
- BEGIN plb2opb_bridge
- PARAMETER INSTANCE = plb2opb_bridge_0
- PARAMETER HW_VER = 1.01.a
- PARAMETER C_RNG0_BASEADDR = 0x20000000
- PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
- PARAMETER C_RNG1_BASEADDR = 0x60000000
- PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
- PARAMETER C_RNG2_BASEADDR = 0x80000000
- PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
- PARAMETER C_RNG3_BASEADDR = 0xC0000000
- PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
- BUS_INTERFACE SPLB = plb_v34_0
- BUS_INTERFACE MOPB = opb_v20_0
- END
-
- Gives this device tree (some properties removed for clarity):
-
- plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v34-1.02.a";
- device_type = "ibm,plb";
- ranges; // 1:1 translation
-
- plb_bram_if_cntrl_0: bram@ffff0000 {
- reg = <ffff0000 10000>;
- }
-
- opb@20000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <20000000 20000000 20000000
- 60000000 60000000 20000000
- 80000000 80000000 40000000
- c0000000 c0000000 20000000>;
-
- opb_uart16550_0: serial@a0000000 {
- reg = <a00000000 2000>;
- };
-
- opb_intc_0: interrupt-controller@d1000fc0 {
- reg = <d1000fc0 20>;
- };
- };
- };
-
That covers the general approach to binding xilinx IP cores into the
device tree. The following are bindings for specific devices:
diff --git a/Documentation/powerpc/bootwrapper.rst b/Documentation/powerpc/bootwrapper.rst
index a6292afba573..cdfa2bc8425f 100644
--- a/Documentation/powerpc/bootwrapper.rst
+++ b/Documentation/powerpc/bootwrapper.rst
@@ -70,28 +70,6 @@ Currently, the following image format targets exist:
kernel with this image type and it depends entirely on
the embedded device tree for all information.
- The simpleImage is useful for booting systems with
- an unknown firmware interface or for booting from
- a debugger when no firmware is present (such as on
- the Xilinx Virtex platform). The only assumption that
- simpleImage makes is that RAM is correctly initialized
- and that the MMU is either off or has RAM mapped to
- base address 0.
-
- simpleImage also supports inserting special platform
- specific initialization code to the start of the bootup
- sequence. The virtex405 platform uses this feature to
- ensure that the cache is invalidated before caching
- is enabled. Platform specific initialization code is
- added as part of the wrapper script and is keyed on
- the image target name. For example, all
- simpleImage.virtex405-* targets will add the
- virtex405-head.S initialization code (This also means
- that the dts file for virtex405 targets should be
- named (virtex405-<board>.dts). Search the wrapper
- script for 'virtex405' and see the file
- arch/powerpc/boot/virtex405-head.S for details.
-
treeImage.%; Image format for used with OpenBIOS firmware found
on some ppc4xx hardware. This image embeds a device
tree blob inside the image.
@@ -116,10 +94,8 @@ Image types which embed a device tree blob (simpleImage, dtbImage, treeImage,
and cuImage) all generate the device tree blob from a file in the
arch/powerpc/boot/dts/ directory. The Makefile selects the correct device
tree source based on the name of the target. Therefore, if the kernel is
-built with 'make treeImage.walnut simpleImage.virtex405-ml403', then the
-build system will use arch/powerpc/boot/dts/walnut.dts to build
-treeImage.walnut and arch/powerpc/boot/dts/virtex405-ml403.dts to build
-the simpleImage.virtex405-ml403.
+built with 'make treeImage.walnut', then the build system will use
+arch/powerpc/boot/dts/walnut.dts to build treeImage.walnut.
Two special targets called 'zImage' and 'zImage.initrd' also exist. These
targets build all the default images as selected by the kernel configuration.
diff --git a/MAINTAINERS b/MAINTAINERS
index a0d86490c2c6..842a9bbc2013 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9668,12 +9668,6 @@ L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: arch/powerpc/platforms/8xx/
-LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
-L: linuxppc-dev@lists.ozlabs.org
-S: Orphan
-F: arch/powerpc/*/*virtex*
-F: arch/powerpc/*/*/*virtex*
-
LINUX FOR POWERPC PA SEMI PWRFICIENT
L: linuxppc-dev@lists.ozlabs.org
S: Orphan
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 0b063830eea8..b88900f4832f 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -230,7 +230,7 @@ config PPC_EARLY_DEBUG_40x
help
Select this to enable early debugging for IBM 40x chips via the
inbuilt serial port. This works on chips with a 16550 compatible
- UART. Xilinx chips with uartlite cannot use this option.
+ UART.
config PPC_EARLY_DEBUG_CPM
bool "Early serial debugging for Freescale CPM-based serial ports"
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index c53a1b8bba8b..d8077b7071dd 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -79,7 +79,6 @@ $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu=405
$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu=405
-$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
# The pre-boot decompressors pull in a lot of kernel headers and other source
# files. This creates a bit of a dependency headache since we need to copy
@@ -129,14 +128,12 @@ src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
-src-wlib-$(CONFIG_XILINX_VIRTEX) += uartlite.c
src-wlib-$(CONFIG_CPM) += cpm-serial.c
src-plat-y := of.c epapr.c
src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
treeboot-walnut.c cuboot-acadia.c \
- cuboot-kilauea.c simpleboot.c \
- virtex405-head.S virtex.c
+ cuboot-kilauea.c simpleboot.c
src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
cuboot-bamboo.c cuboot-sam440ep.c \
cuboot-sequoia.c cuboot-rainier.c \
@@ -144,7 +141,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
cuboot-warp.c cuboot-yosemite.c \
treeboot-iss4xx.c treeboot-currituck.c \
treeboot-akebono.c \
- simpleboot.c fixed-head.S virtex.c
+ simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
diff --git a/arch/powerpc/boot/dts/Makefile b/arch/powerpc/boot/dts/Makefile
index 1cbc0e4ce857..fb335d05aae8 100644
--- a/arch/powerpc/boot/dts/Makefile
+++ b/arch/powerpc/boot/dts/Makefile
@@ -4,4 +4,3 @@ subdir-y += fsl
dtstree := $(srctree)/$(src)
dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
-dtb-$(CONFIG_XILINX_VIRTEX440_GENERIC_BOARD) += virtex440-ml507.dtb virtex440-ml510.dtb
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
deleted file mode 100644
index 66f1c6312de6..000000000000
--- a/arch/powerpc/boot/dts/virtex440-ml507.dts
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * This file supports the Xilinx ML507 board with the 440 processor.
- * A reference design for the FPGA is provided at http://git.xilinx.com.
- *
- * (C) Copyright 2008 Xilinx, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
- * ---
- *
- * Device Tree Generator version: 1.1
- *
- * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
- *
- * XPS project directory: ml507_ppc440_emb_ref
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,virtex440";
- dcr-parent = <&ppc440_0>;
- model = "testing";
- DDR2_SDRAM: memory@0 {
- device_type = "memory";
- reg = < 0 0x10000000 >;
- } ;
- chosen {
- bootargs = "console=ttyS0 root=/dev/ram";
- stdout-path = &RS232_Uart_1;
- } ;
- cpus {
- #address-cells = <1>;
- #cpus = <1>;
- #size-cells = <0>;
- ppc440_0: cpu@0 {
- clock-frequency = <400000000>;
- compatible = "PowerPC,440", "ibm,ppc440";
- d-cache-line-size = <0x20>;
- d-cache-size = <0x8000>;
- dcr-access-method = "native";
- dcr-controller ;
- device_type = "cpu";
- i-cache-line-size = <0x20>;
- i-cache-size = <0x8000>;
- model = "PowerPC,440";
- reg = <0>;
- timebase-frequency = <400000000>;
- xlnx,apu-control = <1>;
- xlnx,apu-udi-0 = <0>;
- xlnx,apu-udi-1 = <0>;
- xlnx,apu-udi-10 = <0>;
- xlnx,apu-udi-11 = <0>;
- xlnx,apu-udi-12 = <0>;
- xlnx,apu-udi-13 = <0>;
- xlnx,apu-udi-14 = <0>;
- xlnx,apu-udi-15 = <0>;
- xlnx,apu-udi-2 = <0>;
- xlnx,apu-udi-3 = <0>;
- xlnx,apu-udi-4 = <0>;
- xlnx,apu-udi-5 = <0>;
- xlnx,apu-udi-6 = <0>;
- xlnx,apu-udi-7 = <0>;
- xlnx,apu-udi-8 = <0>;
- xlnx,apu-udi-9 = <0>;
- xlnx,dcr-autolock-enable = <1>;
- xlnx,dcu-rd-ld-cache-plb-prio = <0>;
- xlnx,dcu-rd-noncache-plb-prio = <0>;
- xlnx,dcu-rd-touch-plb-prio = <0>;
- xlnx,dcu-rd-urgent-plb-prio = <0>;
- xlnx,dcu-wr-flush-plb-prio = <0>;
- xlnx,dcu-wr-store-plb-prio = <0>;
- xlnx,dcu-wr-urgent-plb-prio = <0>;
- xlnx,dma0-control = <0>;
- xlnx,dma0-plb-prio = <0>;
- xlnx,dma0-rxchannelctrl = <0x1010000>;
- xlnx,dma0-rxirqtimer = <0x3ff>;
- xlnx,dma0-txchannelctrl = <0x1010000>;
- xlnx,dma0-txirqtimer = <0x3ff>;
- xlnx,dma1-control = <0>;
- xlnx,dma1-plb-prio = <0>;
- xlnx,dma1-rxchannelctrl = <0x1010000>;
- xlnx,dma1-rxirqtimer = <0x3ff>;
- xlnx,dma1-txchannelctrl = <0x1010000>;
- xlnx,dma1-txirqtimer = <0x3ff>;
- xlnx,dma2-control = <0>;
- xlnx,dma2-plb-prio = <0>;
- xlnx,dma2-rxchannelctrl = <0x1010000>;
- xlnx,dma2-rxirqtimer = <0x3ff>;
- xlnx,dma2-txchannelctrl = <0x1010000>;
- xlnx,dma2-txirqtimer = <0x3ff>;
- xlnx,dma3-control = <0>;
- xlnx,dma3-plb-prio = <0>;
- xlnx,dma3-rxchannelctrl = <0x1010000>;
- xlnx,dma3-rxirqtimer = <0x3ff>;
- xlnx,dma3-txchannelctrl = <0x1010000>;
- xlnx,dma3-txirqtimer = <0x3ff>;
- xlnx,endian-reset = <0>;
- xlnx,generate-plb-timespecs = <1>;
- xlnx,icu-rd-fetch-plb-prio = <0>;
- xlnx,icu-rd-spec-plb-prio = <0>;
- xlnx,icu-rd-touch-plb-prio = <0>;
- xlnx,interconnect-imask = <0xffffffff>;
- xlnx,mplb-allow-lock-xfer = <1>;
- xlnx,mplb-arb-mode = <0>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-counter = <0x500>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-max-burst = <8>;
- xlnx,mplb-native-dwidth = <0x80>;
- xlnx,mplb-p2p = <0>;
- xlnx,mplb-prio-dcur = <2>;
- xlnx,mplb-prio-dcuw = <3>;
- xlnx,mplb-prio-icu = <4>;
- xlnx,mplb-prio-splb0 = <1>;
- xlnx,mplb-prio-splb1 = <0>;
- xlnx,mplb-read-pipe-enable = <1>;
- xlnx,mplb-sync-tattribute = <0>;
- xlnx,mplb-wdog-enable = <1>;
- xlnx,mplb-write-pipe-enable = <1>;
- xlnx,mplb-write-post-enable = <1>;
- xlnx,num-dma = <1>;
- xlnx,pir = <0xf>;
- xlnx,ppc440mc-addr-base = <0>;
- xlnx,ppc440mc-addr-high = <0xfffffff>;
- xlnx,ppc440mc-arb-mode = <0>;
- xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
- xlnx,ppc440mc-control = <0xf810008f>;
- xlnx,ppc440mc-max-burst = <8>;
- xlnx,ppc440mc-prio-dcur = <2>;
- xlnx,ppc440mc-prio-dcuw = <3>;
- xlnx,ppc440mc-prio-icu = <4>;
- xlnx,ppc440mc-prio-splb0 = <1>;
- xlnx,ppc440mc-prio-splb1 = <0>;
- xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
- xlnx,ppcdm-asyncmode = <0>;
- xlnx,ppcds-asyncmode = <0>;
- xlnx,user-reset = <0>;
- DMA0: sdma@80 {
- compatible = "xlnx,ll-dma-1.00.a";
- dcr-reg = < 0x80 0x11 >;
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 10 2 11 2 >;
- } ;
- } ;
- } ;
- plb_v46_0: plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
- ranges ;
- DIP_Switches_8Bit: gpio@81460000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 7 2 >;
- reg = < 0x81460000 0x10000 >;
- xlnx,all-inputs = <1>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <8>;
- xlnx,interrupt-present = <1>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- FLASH: flash@fc000000 {
- bank-width = <2>;
- compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
- reg = < 0xfc000000 0x2000000 >;
- xlnx,family = "virtex5";
- xlnx,include-datawidth-matching-0 = <0x1>;
- xlnx,include-datawidth-matching-1 = <0x0>;
- xlnx,include-datawidth-matching-2 = <0x0>;
- xlnx,include-datawidth-matching-3 = <0x0>;
- xlnx,include-negedge-ioregs = <0x0>;
- xlnx,include-plb-ipif = <0x1>;
- xlnx,include-wrbuf = <0x1>;
- xlnx,max-mem-width = <0x10>;
- xlnx,mch-native-dwidth = <0x20>;
- xlnx,mch-plb-clk-period-ps = <0x2710>;
- xlnx,mch-splb-awidth = <0x20>;
- xlnx,mch0-accessbuf-depth = <0x10>;
- xlnx,mch0-protocol = <0x0>;
- xlnx,mch0-rddatabuf-depth = <0x10>;
- xlnx,mch1-accessbuf-depth = <0x10>;
- xlnx,mch1-protocol = <0x0>;
- xlnx,mch1-rddatabuf-depth = <0x10>;
- xlnx,mch2-accessbuf-depth = <0x10>;
- xlnx,mch2-protocol = <0x0>;
- xlnx,mch2-rddatabuf-depth = <0x10>;
- xlnx,mch3-accessbuf-depth = <0x10>;
- xlnx,mch3-protocol = <0x0>;
- xlnx,mch3-rddatabuf-depth = <0x10>;
- xlnx,mem0-width = <0x10>;
- xlnx,mem1-width = <0x20>;
- xlnx,mem2-width = <0x20>;
- xlnx,mem3-width = <0x20>;
- xlnx,num-banks-mem = <0x1>;
- xlnx,num-channels = <0x2>;
- xlnx,priority-mode = <0x0>;
- xlnx,synch-mem-0 = <0x0>;
- xlnx,synch-mem-1 = <0x0>;
- xlnx,synch-mem-2 = <0x0>;
- xlnx,synch-mem-3 = <0x0>;
- xlnx,synch-pipedelay-0 = <0x2>;
- xlnx,synch-pipedelay-1 = <0x2>;
- xlnx,synch-pipedelay-2 = <0x2>;
- xlnx,synch-pipedelay-3 = <0x2>;
- xlnx,tavdv-ps-mem-0 = <0x1adb0>;
- xlnx,tavdv-ps-mem-1 = <0x3a98>;
- xlnx,tavdv-ps-mem-2 = <0x3a98>;
- xlnx,tavdv-ps-mem-3 = <0x3a98>;
- xlnx,tcedv-ps-mem-0 = <0x1adb0>;
- xlnx,tcedv-ps-mem-1 = <0x3a98>;
- xlnx,tcedv-ps-mem-2 = <0x3a98>;
- xlnx,tcedv-ps-mem-3 = <0x3a98>;
- xlnx,thzce-ps-mem-0 = <0x88b8>;
- xlnx,thzce-ps-mem-1 = <0x1b58>;
- xlnx,thzce-ps-mem-2 = <0x1b58>;
- xlnx,thzce-ps-mem-3 = <0x1b58>;
- xlnx,thzoe-ps-mem-0 = <0x1b58>;
- xlnx,thzoe-ps-mem-1 = <0x1b58>;
- xlnx,thzoe-ps-mem-2 = <0x1b58>;
- xlnx,thzoe-ps-mem-3 = <0x1b58>;
- xlnx,tlzwe-ps-mem-0 = <0x88b8>;
- xlnx,tlzwe-ps-mem-1 = <0x0>;
- xlnx,tlzwe-ps-mem-2 = <0x0>;
- xlnx,tlzwe-ps-mem-3 = <0x0>;
- xlnx,twc-ps-mem-0 = <0x2af8>;
- xlnx,twc-ps-mem-1 = <0x3a98>;
- xlnx,twc-ps-mem-2 = <0x3a98>;
- xlnx,twc-ps-mem-3 = <0x3a98>;
- xlnx,twp-ps-mem-0 = <0x11170>;
- xlnx,twp-ps-mem-1 = <0x2ee0>;
- xlnx,twp-ps-mem-2 = <0x2ee0>;
- xlnx,twp-ps-mem-3 = <0x2ee0>;
- xlnx,xcl0-linesize = <0x4>;
- xlnx,xcl0-writexfer = <0x1>;
- xlnx,xcl1-linesize = <0x4>;
- xlnx,xcl1-writexfer = <0x1>;
- xlnx,xcl2-linesize = <0x4>;
- xlnx,xcl2-writexfer = <0x1>;
- xlnx,xcl3-linesize = <0x4>;
- xlnx,xcl3-writexfer = <0x1>;
- } ;
- Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ethernet@81c00000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "xlnx,xps-ll-temac-1.01.b";
- device_type = "network";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 5 2 >;
- llink-connected = <&DMA0>;
- local-mac-address = [ 02 00 00 00 00 00 ];
- reg = < 0x81c00000 0x40 >;
- xlnx,bus2core-clk-ratio = <1>;
- xlnx,phy-type = <1>;
- xlnx,phyaddr = <1>;
- xlnx,rxcsum = <1>;
- xlnx,rxfifo = <0x1000>;
- xlnx,temac-type = <0>;
- xlnx,txcsum = <1>;
- xlnx,txfifo = <0x1000>;
- phy-handle = <&phy7>;
- clock-frequency = <100000000>;
- phy7: phy@7 {
- compatible = "marvell,88e1111";
- reg = <7>;
- } ;
- } ;
- } ;
- IIC_EEPROM: i2c@81600000 {
- compatible = "xlnx,xps-iic-2.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 6 2 >;
- reg = < 0x81600000 0x10000 >;
- xlnx,clk-freq = <0x5f5e100>;
- xlnx,family = "virtex5";
- xlnx,gpo-width = <0x1>;
- xlnx,iic-freq = <0x186a0>;
- xlnx,scl-inertial-delay = <0x0>;
- xlnx,sda-inertial-delay = <0x0>;
- xlnx,ten-bit-adr = <0x0>;
- } ;
- LEDs_8Bit: gpio@81400000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81400000 0x10000 >;
- xlnx,all-inputs = <0>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <8>;
- xlnx,interrupt-present = <0>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- LEDs_Positions: gpio@81420000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81420000 0x10000 >;
- xlnx,all-inputs = <0>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <5>;
- xlnx,interrupt-present = <0>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- Push_Buttons_5Bit: gpio@81440000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 8 2 >;
- reg = < 0x81440000 0x10000 >;
- xlnx,all-inputs = <1>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <5>;
- xlnx,interrupt-present = <1>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- RS232_Uart_1: serial@83e00000 {
- clock-frequency = <100000000>;
- compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
- current-speed = <9600>;
- device_type = "serial";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 9 2 >;
- reg = < 0x83e00000 0x10000 >;
- reg-offset = <0x1003>;
- reg-shift = <2>;
- xlnx,family = "virtex5";
- xlnx,has-external-rclk = <0>;
- xlnx,has-external-xin = <0>;
- xlnx,is-a-16550 = <1>;
- } ;
- SysACE_CompactFlash: sysace@83600000 {
- compatible = "xlnx,xps-sysace-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 4 2 >;
- reg = < 0x83600000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,mem-width = <0x10>;
- } ;
- xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
- compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
- reg = < 0xffff0000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- xps_intc_0: interrupt-controller@81800000 {
- #interrupt-cells = <2>;
- compatible = "xlnx,xps-intc-1.00.a";
- interrupt-controller ;
- reg = < 0x81800000 0x10000 >;
- xlnx,num-intr-inputs = <0xc>;
- } ;
- xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
- compatible = "xlnx,xps-timebase-wdt-1.00.b";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 2 0 1 2 >;
- reg = < 0x83a00000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,wdt-enable-once = <0>;
- xlnx,wdt-interval = <0x1e>;
- } ;
- xps_timer_1: timer@83c00000 {
- compatible = "xlnx,xps-timer-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 3 2 >;
- reg = < 0x83c00000 0x10000 >;
- xlnx,count-width = <0x20>;
- xlnx,family = "virtex5";
- xlnx,gen0-assert = <1>;
- xlnx,gen1-assert = <1>;
- xlnx,one-timer-only = <1>;
- xlnx,trig0-assert = <1>;
- xlnx,trig1-assert = <1>;
- } ;
- } ;
-} ;
diff --git a/arch/powerpc/boot/dts/virtex440-ml510.dts b/arch/powerpc/boot/dts/virtex440-ml510.dts
deleted file mode 100644
index 3b736ca26ddc..000000000000
--- a/arch/powerpc/boot/dts/virtex440-ml510.dts
+++ /dev/null
@@ -1,466 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Xilinx ML510 Reference Design support
- *
- * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design.
- * The reference design contains a bug which prevent PCI DMA from working
- * properly. A description of the bug is given in the plbv46_pci section. It
- * needs to be fixed by the user until Xilinx updates their reference design.
- *
- * Copyright 2009, Roderick Colenbrander
- */
-
-/dts-v1/;
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
- dcr-parent = <&ppc440_0>;
- DDR2_SDRAM_DIMM0: memory@0 {
- device_type = "memory";
- reg = < 0x0 0x20000000 >;
- } ;
- alias {
- ethernet0 = &Hard_Ethernet_MAC;
- serial0 = &RS232_Uart_1;
- } ;
- chosen {
- bootargs = "console=ttyS0 root=/dev/ram";
- stdout-path = "/plb@0/serial@83e00000";
- } ;
- cpus {
- #address-cells = <1>;
- #cpus = <0x1>;
- #size-cells = <0>;
- ppc440_0: cpu@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- clock-frequency = <300000000>;
- compatible = "PowerPC,440", "ibm,ppc440";
- d-cache-line-size = <0x20>;
- d-cache-size = <0x8000>;
- dcr-access-method = "native";
- dcr-controller ;
- device_type = "cpu";
- i-cache-line-size = <0x20>;
- i-cache-size = <0x8000>;
- model = "PowerPC,440";
- reg = <0>;
- timebase-frequency = <300000000>;
- xlnx,apu-control = <0x2000>;
- xlnx,apu-udi-0 = <0x0>;
- xlnx,apu-udi-1 = <0x0>;
- xlnx,apu-udi-10 = <0x0>;
- xlnx,apu-udi-11 = <0x0>;
- xlnx,apu-udi-12 = <0x0>;
- xlnx,apu-udi-13 = <0x0>;
- xlnx,apu-udi-14 = <0x0>;
- xlnx,apu-udi-15 = <0x0>;
- xlnx,apu-udi-2 = <0x0>;
- xlnx,apu-udi-3 = <0x0>;
- xlnx,apu-udi-4 = <0x0>;
- xlnx,apu-udi-5 = <0x0>;
- xlnx,apu-udi-6 = <0x0>;
- xlnx,apu-udi-7 = <0x0>;
- xlnx,apu-udi-8 = <0x0>;
- xlnx,apu-udi-9 = <0x0>;
- xlnx,dcr-autolock-enable = <0x1>;
- xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
- xlnx,dcu-rd-noncache-plb-prio = <0x0>;
- xlnx,dcu-rd-touch-plb-prio = <0x0>;
- xlnx,dcu-rd-urgent-plb-prio = <0x0>;
- xlnx,dcu-wr-flush-plb-prio = <0x0>;
- xlnx,dcu-wr-store-plb-prio = <0x0>;
- xlnx,dcu-wr-urgent-plb-prio = <0x0>;
- xlnx,dma0-control = <0x0>;
- xlnx,dma0-plb-prio = <0x0>;
- xlnx,dma0-rxchannelctrl = <0x1010000>;
- xlnx,dma0-rxirqtimer = <0x3ff>;
- xlnx,dma0-txchannelctrl = <0x1010000>;
- xlnx,dma0-txirqtimer = <0x3ff>;
- xlnx,dma1-control = <0x0>;
- xlnx,dma1-plb-prio = <0x0>;
- xlnx,dma1-rxchannelctrl = <0x1010000>;
- xlnx,dma1-rxirqtimer = <0x3ff>;
- xlnx,dma1-txchannelctrl = <0x1010000>;
- xlnx,dma1-txirqtimer = <0x3ff>;
- xlnx,dma2-control = <0x0>;
- xlnx,dma2-plb-prio = <0x0>;
- xlnx,dma2-rxchannelctrl = <0x1010000>;
- xlnx,dma2-rxirqtimer = <0x3ff>;
- xlnx,dma2-txchannelctrl = <0x1010000>;
- xlnx,dma2-txirqtimer = <0x3ff>;
- xlnx,dma3-control = <0x0>;
- xlnx,dma3-plb-prio = <0x0>;
- xlnx,dma3-rxchannelctrl = <0x1010000>;
- xlnx,dma3-rxirqtimer = <0x3ff>;
- xlnx,dma3-txchannelctrl = <0x1010000>;
- xlnx,dma3-txirqtimer = <0x3ff>;
- xlnx,endian-reset = <0x0>;
- xlnx,generate-plb-timespecs = <0x1>;
- xlnx,icu-rd-fetch-plb-prio = <0x0>;
- xlnx,icu-rd-spec-plb-prio = <0x0>;
- xlnx,icu-rd-touch-plb-prio = <0x0>;
- xlnx,interconnect-imask = <0xffffffff>;
- xlnx,mplb-allow-lock-xfer = <0x1>;
- xlnx,mplb-arb-mode = <0x0>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-counter = <0x500>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-max-burst = <0x8>;
- xlnx,mplb-native-dwidth = <0x80>;
- xlnx,mplb-p2p = <0x0>;
- xlnx,mplb-prio-dcur = <0x2>;
- xlnx,mplb-prio-dcuw = <0x3>;
- xlnx,mplb-prio-icu = <0x4>;
- xlnx,mplb-prio-splb0 = <0x1>;
- xlnx,mplb-prio-splb1 = <0x0>;
- xlnx,mplb-read-pipe-enable = <0x1>;
- xlnx,mplb-sync-tattribute = <0x0>;
- xlnx,mplb-wdog-enable = <0x1>;
- xlnx,mplb-write-pipe-enable = <0x1>;
- xlnx,mplb-write-post-enable = <0x1>;
- xlnx,num-dma = <0x0>;
- xlnx,pir = <0xf>;
- xlnx,ppc440mc-addr-base = <0x0>;
- xlnx,ppc440mc-addr-high = <0x1fffffff>;
- xlnx,ppc440mc-arb-mode = <0x0>;
- xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
- xlnx,ppc440mc-control = <0xf810008f>;
- xlnx,ppc440mc-max-burst = <0x8>;
- xlnx,ppc440mc-prio-dcur = <0x2>;
- xlnx,ppc440mc-prio-dcuw = <0x3>;
- xlnx,ppc440mc-prio-icu = <0x4>;
- xlnx,ppc440mc-prio-splb0 = <0x1>;
- xlnx,ppc440mc-prio-splb1 = <0x0>;
- xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
- xlnx,ppcdm-asyncmode = <0x0>;
- xlnx,ppcds-asyncmode = <0x0>;
- xlnx,user-reset = <0x0>;
- } ;
- } ;
- plb_v46_0: plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
- ranges ;
- FLASH: flash@fc000000 {
- bank-width = <2>;
- compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
- reg = < 0xfc000000 0x2000000 >;
- xlnx,family = "virtex5";
- xlnx,include-datawidth-matching-0 = <0x1>;
- xlnx,include-datawidth-matching-1 = <0x0>;
- xlnx,include-datawidth-matching-2 = <0x0>;
- xlnx,include-datawidth-matching-3 = <0x0>;
- xlnx,include-negedge-ioregs = <0x0>;
- xlnx,include-plb-ipif = <0x1>;
- xlnx,include-wrbuf = <0x1>;
- xlnx,max-mem-width = <0x10>;
- xlnx,mch-native-dwidth = <0x20>;
- xlnx,mch-plb-clk-period-ps = <0x2710>;
- xlnx,mch-splb-awidth = <0x20>;
- xlnx,mch0-accessbuf-depth = <0x10>;
- xlnx,mch0-protocol = <0x0>;
- xlnx,mch0-rddatabuf-depth = <0x10>;
- xlnx,mch1-accessbuf-depth = <0x10>;
- xlnx,mch1-protocol = <0x0>;
- xlnx,mch1-rddatabuf-depth = <0x10>;
- xlnx,mch2-accessbuf-depth = <0x10>;
- xlnx,mch2-protocol = <0x0>;
- xlnx,mch2-rddatabuf-depth = <0x10>;
- xlnx,mch3-accessbuf-depth = <0x10>;
- xlnx,mch3-protocol = <0x0>;
- xlnx,mch3-rddatabuf-depth = <0x10>;
- xlnx,mem0-width = <0x10>;
- xlnx,mem1-width = <0x20>;
- xlnx,mem2-width = <0x20>;
- xlnx,mem3-width = <0x20>;
- xlnx,num-banks-mem = <0x1>;
- xlnx,num-channels = <0x2>;
- xlnx,priority-mode = <0x0>;
- xlnx,synch-mem-0 = <0x0>;
- xlnx,synch-mem-1 = <0x0>;
- xlnx,synch-mem-2 = <0x0>;
- xlnx,synch-mem-3 = <0x0>;
- xlnx,synch-pipedelay-0 = <0x2>;
- xlnx,synch-pipedelay-1 = <0x2>;
- xlnx,synch-pipedelay-2 = <0x2>;
- xlnx,synch-pipedelay-3 = <0x2>;
- xlnx,tavdv-ps-mem-0 = <0x1adb0>;
- xlnx,tavdv-ps-mem-1 = <0x3a98>;
- xlnx,tavdv-ps-mem-2 = <0x3a98>;
- xlnx,tavdv-ps-mem-3 = <0x3a98>;
- xlnx,tcedv-ps-mem-0 = <0x1adb0>;
- xlnx,tcedv-ps-mem-1 = <0x3a98>;
- xlnx,tcedv-ps-mem-2 = <0x3a98>;
- xlnx,tcedv-ps-mem-3 = <0x3a98>;
- xlnx,thzce-ps-mem-0 = <0x88b8>;
- xlnx,thzce-ps-mem-1 = <0x1b58>;
- xlnx,thzce-ps-mem-2 = <0x1b58>;
- xlnx,thzce-ps-mem-3 = <0x1b58>;
- xlnx,thzoe-ps-mem-0 = <0x1b58>;
- xlnx,thzoe-ps-mem-1 = <0x1b58>;
- xlnx,thzoe-ps-mem-2 = <0x1b58>;
- xlnx,thzoe-ps-mem-3 = <0x1b58>;
- xlnx,tlzwe-ps-mem-0 = <0x88b8>;
- xlnx,tlzwe-ps-mem-1 = <0x0>;
- xlnx,tlzwe-ps-mem-2 = <0x0>;
- xlnx,tlzwe-ps-mem-3 = <0x0>;
- xlnx,twc-ps-mem-0 = <0x1adb0>;
- xlnx,twc-ps-mem-1 = <0x3a98>;
- xlnx,twc-ps-mem-2 = <0x3a98>;
- xlnx,twc-ps-mem-3 = <0x3a98>;
- xlnx,twp-ps-mem-0 = <0x11170>;
- xlnx,twp-ps-mem-1 = <0x2ee0>;
- xlnx,twp-ps-mem-2 = <0x2ee0>;
- xlnx,twp-ps-mem-3 = <0x2ee0>;
- xlnx,xcl0-linesize = <0x4>;
- xlnx,xcl0-writexfer = <0x1>;
- xlnx,xcl1-linesize = <0x4>;
- xlnx,xcl1-writexfer = <0x1>;
- xlnx,xcl2-linesize = <0x4>;
- xlnx,xcl2-writexfer = <0x1>;
- xlnx,xcl3-linesize = <0x4>;
- xlnx,xcl3-writexfer = <0x1>;
- } ;
- Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ethernet@81c00000 {
- compatible = "xlnx,xps-ll-temac-1.01.b";
- device_type = "network";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 8 2 >;
- llink-connected = <&Hard_Ethernet_MAC_fifo>;
- local-mac-address = [ 02 00 00 00 00 00 ];
- reg = < 0x81c00000 0x40 >;
- xlnx,bus2core-clk-ratio = <0x1>;
- xlnx,phy-type = <0x3>;
- xlnx,phyaddr = <0x1>;
- xlnx,rxcsum = <0x0>;
- xlnx,rxfifo = <0x8000>;
- xlnx,temac-type = <0x0>;
- xlnx,txcsum = <0x0>;
- xlnx,txfifo = <0x8000>;
- } ;
- } ;
- Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
- compatible = "xlnx,xps-ll-fifo-1.01.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 6 2 >;
- reg = < 0x81a00000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- IIC_EEPROM: i2c@81600000 {
- compatible = "xlnx,xps-iic-2.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 9 2 >;
- reg = < 0x81600000 0x10000 >;
- xlnx,clk-freq = <0x5f5e100>;
- xlnx,family = "virtex5";
- xlnx,gpo-width = <0x1>;
- xlnx,iic-freq = <0x186a0>;
- xlnx,scl-inertial-delay = <0x5>;
- xlnx,sda-inertial-delay = <0x5>;
- xlnx,ten-bit-adr = <0x0>;
- } ;
- LCD_OPTIONAL: gpio@81420000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81420000 0x10000 >;
- xlnx,all-inputs = <0x0>;
- xlnx,all-inputs-2 = <0x0>;
- xlnx,dout-default = <0x0>;
- xlnx,dout-default-2 = <0x0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <0xb>;
- xlnx,interrupt-present = <0x0>;
- xlnx,is-bidir = <0x1>;
- xlnx,is-bidir-2 = <0x1>;
- xlnx,is-dual = <0x0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- LEDs_4Bit: gpio@81400000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81400000 0x10000 >;
- xlnx,all-inputs = <0x0>;
- xlnx,all-inputs-2 = <0x0>;
- xlnx,dout-default = <0x0>;
- xlnx,dout-default-2 = <0x0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <0x4>;
- xlnx,interrupt-present = <0x0>;
- xlnx,is-bidir = <0x1>;
- xlnx,is-bidir-2 = <0x1>;
- xlnx,is-dual = <0x0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- RS232_Uart_1: serial@83e00000 {
- clock-frequency = <100000000>;
- compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
- current-speed = <9600>;
- device_type = "serial";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 11 2 >;
- reg = < 0x83e00000 0x10000 >;
- reg-offset = <0x1003>;
- reg-shift = <2>;
- xlnx,family = "virtex5";
- xlnx,has-external-rclk = <0x0>;
- xlnx,has-external-xin = <0x0>;
- xlnx,is-a-16550 = <0x1>;
- } ;
- SPI_EEPROM: xps-spi@feff8000 {
- compatible = "xlnx,xps-spi-2.00.b";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 10 2 >;
- reg = < 0xfeff8000 0x80 >;
- xlnx,family = "virtex5";
- xlnx,fifo-exist = <0x1>;
- xlnx,num-ss-bits = <0x1>;
- xlnx,num-transfer-bits = <0x8>;
- xlnx,sck-ratio = <0x80>;
- } ;
- SysACE_CompactFlash: sysace@83600000 {
- compatible = "xlnx,xps-sysace-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 7 2 >;
- reg = < 0x83600000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,mem-width = <0x10>;
- } ;
- plbv46_pci_0: plbv46-pci@85e00000 {
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "xlnx,plbv46-pci-1.03.a";
- device_type = "pci";
- reg = < 0x85e00000 0x10000 >;
-
- /*
- * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to
- * 0 which means that a read/write to the memory mapped
- * i/o region (which starts at 0xa0000000) for pci
- * bar 0 on the plb side translates to 0.
- * It is important to set this value to 0xa0000000, so
- * that inbound and outbound pci transactions work
- * properly including DMA.
- */
- ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
- 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>;
-
- #interrupt-cells = <1>;
- interrupt-parent = <&xps_intc_0>;
- interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
- interrupt-map = <
- /* IRQ mapping for pci slots and ALI M1533
- * periperhals. In total there are 5 interrupt
- * lines connected to a xps_intc controller.
- * Four of them are PCI IRQ A, B, C, D and
- * which correspond to respectively xpx_intc
- * 5, 4, 3 and 2. The fifth interrupt line is
- * connected to the south bridge and this one
- * uses irq 1 and is active high instead of
- * active low.
- *
- * The M1533 contains various peripherals
- * including AC97 audio, a modem, USB, IDE and
- * some power management stuff. The modem
- * isn't connected on the ML510 and the power
- * management core also isn't used.
- */
-
- /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
- 0x3000 0 0 1 &xps_intc_0 3 2
- 0x3000 0 0 2 &xps_intc_0 2 2
- 0x3000 0 0 3 &xps_intc_0 5 2
- 0x3000 0 0 4 &xps_intc_0 4 2
-
- /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
- /*
- 0x11800 0 0 1 &xps_intc_0 5 0 2
- 0x11800 0 0 2 &xps_intc_0 4 0 2
- 0x11800 0 0 3 &xps_intc_0 3 0 2
- 0x11800 0 0 4 &xps_intc_0 2 0 2
- */
-
- /* According to the datasheet + schematic
- * ABCD [FPGA] of slot 5 is mapped to DABC.
- * Testing showed that at least A maps to B,
- * the mapping of the other pins is a guess
- * and for that reason the lines have been
- * commented out.
- */
- /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
- 0x2800 0 0 1 &xps_intc_0 4 2
- /*
- 0x2800 0 0 2 &xps_intc_0 3 2
- 0x2800 0 0 3 &xps_intc_0 2 2
- 0x2800 0 0 4 &xps_intc_0 5 2
- */
-
- /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
- /*
- 0x11000 0 0 1 &xps_intc_0 4 0 2
- 0x11000 0 0 2 &xps_intc_0 3 0 2
- 0x11000 0 0 3 &xps_intc_0 2 0 2
- 0x11000 0 0 4 &xps_intc_0 5 0 2
- */
-
- /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
- 0x0800 0 0 1 &i8259 7 2
-
- /* IDSEL 0x1b / dev=11, bus=0 / IDE */
- 0x5800 0 0 1 &i8259 14 2
-
- /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
- 0x7800 0 0 1 &i8259 7 2
- >;
- ali_m1533 {
- #size-cells = <1>;
- #address-cells = <2>;
- i8259: interrupt-controller@20 {
- reg = <1 0x20 2
- 1 0xa0 2
- 1 0x4d0 2>;
- interrupt-controller;
- device_type = "interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- compatible = "chrp,iic";
-
- /* south bridge irq is active high */
- interrupts = <1 3>;
- interrupt-parent = <&xps_intc_0>;
- };
- };
- } ;
- xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
- compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
- reg = < 0xffff0000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- xps_intc_0: interrupt-controller@81800000 {
- #interrupt-cells = <0x2>;
- compatible = "xlnx,xps-intc-1.00.a";
- interrupt-controller ;
- reg = < 0x81800000 0x10000 >;
- xlnx,num-intr-inputs = <0xc>;
- } ;
- xps_tft_0: tft@86e00000 {
- compatible = "xlnx,xps-tft-1.00.a";
- reg = < 0x86e00000 0x10000 >;
- xlnx,dcr-splb-slave-if = <0x1>;
- xlnx,default-tft-base-addr = <0x0>;
- xlnx,family = "virtex5";
- xlnx,i2c-slave-addr = <0x76>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-native-dwidth = <0x40>;
- xlnx,mplb-smallest-slave = <0x20>;
- xlnx,tft-interface = <0x1>;
- } ;
- } ;
-} ;
diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h
index e0606766480f..6455fc9a244f 100644
--- a/arch/powerpc/boot/ops.h
+++ b/arch/powerpc/boot/ops.h
@@ -88,7 +88,6 @@ int serial_console_init(void);
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
int cpm_console_init(void *devp, struct serial_console_data *scdp);
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp);
-int uartlite_console_init(void *devp, struct serial_console_data *scdp);
int opal_console_init(void *devp, struct serial_console_data *scdp);
void *simple_alloc_init(char *base, unsigned long heap_size,
unsigned long granularity, unsigned long max_allocs);
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index 9457863147f9..0bfa7e87e546 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -132,11 +132,6 @@ int serial_console_init(void)
else if (dt_is_compatible(devp, "fsl,mpc5200-psc-uart"))
rc = mpc5200_psc_console_init(devp, &serial_cd);
#endif
-#ifdef CONFIG_XILINX_VIRTEX
- else if (dt_is_compatible(devp, "xlnx,opb-uartlite-1.00.b") ||
- dt_is_compatible(devp, "xlnx,xps-uartlite-1.00.a"))
- rc = uartlite_console_init(devp, &serial_cd);
-#endif
#ifdef CONFIG_PPC64_BOOT_WRAPPER
else if (dt_is_compatible(devp, "ibm,opal-console-raw"))
rc = opal_console_init(devp, &serial_cd);
diff --git a/arch/powerpc/boot/uartlite.c b/arch/powerpc/boot/uartlite.c
deleted file mode 100644
index 46bed69b4169..000000000000
--- a/arch/powerpc/boot/uartlite.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Xilinx UARTLITE bootloader driver
- *
- * Copyright (C) 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include "types.h"
-#include "string.h"
-#include "stdio.h"
-#include "io.h"
-#include "ops.h"
-
-#define ULITE_RX 0x00
-#define ULITE_TX 0x04
-#define ULITE_STATUS 0x08
-#define ULITE_CONTROL 0x0c
-
-#define ULITE_STATUS_RXVALID 0x01
-#define ULITE_STATUS_TXFULL 0x08
-
-#define ULITE_CONTROL_RST_RX 0x02
-
-static void * reg_base;
-
-static int uartlite_open(void)
-{
- /* Clear the RX FIFO */
- out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX);
- return 0;
-}
-
-static void uartlite_putc(unsigned char c)
-{
- u32 reg = ULITE_STATUS_TXFULL;
- while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */
- reg = in_be32(reg_base + ULITE_STATUS);
- out_be32(reg_base + ULITE_TX, c);
-}
-
-static unsigned char uartlite_getc(void)
-{
- u32 reg = 0;
- while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */
- reg = in_be32(reg_base + ULITE_STATUS);
- return in_be32(reg_base + ULITE_RX);
-}
-
-static u8 uartlite_tstc(void)
-{
- u32 reg = in_be32(reg_base + ULITE_STATUS);
- return reg & ULITE_STATUS_RXVALID;
-}
-
-int uartlite_console_init(void *devp, struct serial_console_data *scdp)
-{
- int n;
- unsigned long reg_phys;
-
- n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base));
- if (n != sizeof(reg_base)) {
- if (!dt_xlate_reg(devp, 0, ®_phys, NULL))
- return -1;
-
- reg_base = (void *)reg_phys;
- }
-
- scdp->open = uartlite_open;
- scdp->putc = uartlite_putc;
- scdp->getc = uartlite_getc;
- scdp->tstc = uartlite_tstc;
- scdp->close = NULL;
- return 0;
-}
diff --git a/arch/powerpc/boot/virtex.c b/arch/powerpc/boot/virtex.c
deleted file mode 100644
index f731cbb4bff0..000000000000
--- a/arch/powerpc/boot/virtex.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * The platform specific code for virtex devices since a boot loader is not
- * always used.
- *
- * (C) Copyright 2008 Xilinx, Inc.
- */
-
-#include "ops.h"
-#include "io.h"
-#include "stdio.h"
-
-#define UART_DLL 0 /* Out: Divisor Latch Low */
-#define UART_DLM 1 /* Out: Divisor Latch High */
-#define UART_FCR 2 /* Out: FIFO Control Register */
-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define UART_LCR 3 /* Out: Line Control Register */
-#define UART_MCR 4 /* Out: Modem Control Register */
-#define UART_MCR_RTS 0x02 /* RTS complement */
-#define UART_MCR_DTR 0x01 /* DTR complement */
-#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-
-static int virtex_ns16550_console_init(void *devp)
-{
- unsigned char *reg_base;
- u32 reg_shift, reg_offset, clk, spd;
- u16 divisor;
- int n;
-
- if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1)
- return -1;
-
- n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset));
- if (n == sizeof(reg_offset))
- reg_base += reg_offset;
-
- n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift));
- if (n != sizeof(reg_shift))
- reg_shift = 0;
-
- n = getprop(devp, "current-speed", (void *)&spd, sizeof(spd));
- if (n != sizeof(spd))
- spd = 9600;
-
- /* should there be a default clock rate?*/
- n = getprop(devp, "clock-frequency", (void *)&clk, sizeof(clk));
- if (n != sizeof(clk))
- return -1;
-
- divisor = clk / (16 * spd);
-
- /* Access baud rate */
- out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB);
-
- /* Baud rate based on input clock */
- out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF);
- out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8);
-
- /* 8 data, 1 stop, no parity */
- out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8);
-
- /* RTS/DTR */
- out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR);
-
- /* Clear transmitter and receiver */
- out_8(reg_base + (UART_FCR << reg_shift),
- UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
- return 0;
-}
-
-/* For virtex, the kernel may be loaded without using a bootloader and if so
- some UARTs need more setup than is provided in the normal console init
-*/
-int platform_specific_init(void)
-{
- void *devp;
- char devtype[MAX_PROP_LEN];
- char path[MAX_PATH_LEN];
-
- devp = finddevice("/chosen");
- if (devp == NULL)
- return -1;
-
- if (getprop(devp, "linux,stdout-path", path, MAX_PATH_LEN) > 0) {
- devp = finddevice(path);
- if (devp == NULL)
- return -1;
-
- if ((getprop(devp, "device_type", devtype, sizeof(devtype)) > 0)
- && !strcmp(devtype, "serial")
- && (dt_is_compatible(devp, "ns16550")))
- virtex_ns16550_console_init(devp);
- }
- return 0;
-}
diff --git a/arch/powerpc/boot/virtex405-head.S b/arch/powerpc/boot/virtex405-head.S
deleted file mode 100644
index 00bab7d7c48c..000000000000
--- a/arch/powerpc/boot/virtex405-head.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include "ppc_asm.h"
-
- .text
- .global _zimage_start
-_zimage_start:
-
- /* PPC errata 213: needed by Virtex-4 FX */
- mfccr0 0
- oris 0,0,0x50000000@h
- mtccr0 0
-
- /*
- * Invalidate the data cache if the data cache is turned off.
- * - The 405 core does not invalidate the data cache on power-up
- * or reset but does turn off the data cache. We cannot assume
- * that the cache contents are valid.
- * - If the data cache is turned on this must have been done by
- * a bootloader and we assume that the cache contents are
- * valid.
- */
- mfdccr r9
- cmplwi r9,0
- bne 2f
- lis r9,0
- li r8,256
- mtctr r8
-1: dccci r0,r9
- addi r9,r9,0x20
- bdnz 1b
-2: b _zimage_start_lib
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index ed6266367bc0..de5fd5a047e8 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -323,14 +323,6 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
-simpleboot-virtex405-*)
- platformo="$object/virtex405-head.o $object/simpleboot.o $object/virtex.o"
- binary=y
- ;;
-simpleboot-virtex440-*)
- platformo="$object/fixed-head.o $object/simpleboot.o $object/virtex.o"
- binary=y
- ;;
simpleboot-*)
platformo="$object/fixed-head.o $object/simpleboot.o"
binary=y
diff --git a/arch/powerpc/configs/40x/virtex_defconfig b/arch/powerpc/configs/40x/virtex_defconfig
deleted file mode 100644
index 5e7c61d1d7d0..000000000000
--- a/arch/powerpc/configs/40x/virtex_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_40x=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_WALNUT is not set
-CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
-CONFIG_PREEMPT=y
-CONFIG_MATH_EMULATION=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE=""
-CONFIG_PCI=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_XILINX_SYSACE=y
-CONFIG_NETDEVICES=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
-CONFIG_XILINX_HWICAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_XILINX=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRC_CCITT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/powerpc/configs/44x/virtex5_defconfig b/arch/powerpc/configs/44x/virtex5_defconfig
deleted file mode 100644
index 1f74079e1703..000000000000
--- a/arch/powerpc/configs/44x/virtex5_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_44x=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_EBONY is not set
-CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y
-CONFIG_PREEMPT=y
-CONFIG_MATH_EMULATION=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE=""
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_XILINX_SYSACE=y
-CONFIG_NETDEVICES=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
-CONFIG_XILINX_HWICAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_XILINX=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRC_CCITT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/powerpc/configs/ppc40x_defconfig b/arch/powerpc/configs/ppc40x_defconfig
index a5f683aed328..88960a72b525 100644
--- a/arch/powerpc/configs/ppc40x_defconfig
+++ b/arch/powerpc/configs/ppc40x_defconfig
@@ -14,7 +14,6 @@ CONFIG_EP405=y
CONFIG_HOTFOOT=y
CONFIG_KILAUEA=y
CONFIG_MAKALU=y
-CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -37,33 +36,26 @@ CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
-CONFIG_XILINX_SYSACE=m
CONFIG_NETDEVICES=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=m
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
# CONFIG_HW_RANDOM is not set
-CONFIG_XILINX_HWICAP=m
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_IBM_IIC=m
-CONFIG_GPIO_XILINX=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=y
CONFIG_FB=m
-CONFIG_FB_XILINX=m
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=m
CONFIG_VFAT_FS=m
diff --git a/arch/powerpc/configs/ppc44x_defconfig b/arch/powerpc/configs/ppc44x_defconfig
index a41eedfe0a5f..8b595f67068c 100644
--- a/arch/powerpc/configs/ppc44x_defconfig
+++ b/arch/powerpc/configs/ppc44x_defconfig
@@ -22,7 +22,6 @@ CONFIG_GLACIER=y
CONFIG_REDWOOD=y
CONFIG_EIGER=y
CONFIG_YOSEMITE=y
-CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y
CONFIG_PPC4xx_GPIO=y
CONFIG_MATH_EMULATION=y
CONFIG_NET=y
@@ -46,7 +45,6 @@ CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=35000
-CONFIG_XILINX_SYSACE=m
CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m
# CONFIG_SCSI_LOWLEVEL is not set
@@ -57,7 +55,6 @@ CONFIG_IBM_EMAC=y
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=m
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
@@ -65,18 +62,13 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
# CONFIG_HW_RANDOM is not set
-CONFIG_XILINX_HWICAP=m
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_IBM_IIC=m
-CONFIG_GPIO_XILINX=y
# CONFIG_HWMON is not set
CONFIG_FB=m
-CONFIG_FB_XILINX=m
CONFIG_USB=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_OHCI_HCD=m
diff --git a/arch/powerpc/include/asm/xilinx_intc.h b/arch/powerpc/include/asm/xilinx_intc.h
deleted file mode 100644
index ca9aa162fb09..000000000000
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Xilinx intc external definitions
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- */
-#ifndef _ASM_POWERPC_XILINX_INTC_H
-#define _ASM_POWERPC_XILINX_INTC_H
-
-#ifdef __KERNEL__
-
-extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xintc_get_irq(void);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/include/asm/xilinx_pci.h b/arch/powerpc/include/asm/xilinx_pci.h
deleted file mode 100644
index 7a8275caf6af..000000000000
--- a/arch/powerpc/include/asm/xilinx_pci.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Xilinx pci external definitions
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef INCLUDE_XILINX_PCI
-#define INCLUDE_XILINX_PCI
-
-#ifdef CONFIG_XILINX_PCI
-extern void __init xilinx_pci_init(void);
-#else
-static inline void __init xilinx_pci_init(void) { return; }
-#endif
-
-#endif /* INCLUDE_XILINX_PCI */
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 245be4fafe13..2dff9041bcdc 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1385,32 +1385,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
- { /* Xilinx Virtex-II Pro */
- .pvr_mask = 0xfffff000,
- .pvr_value = 0x20010000,
- .cpu_name = "Virtex-II Pro",
- .cpu_features = CPU_FTRS_40X,
- .cpu_user_features = PPC_FEATURE_32 |
- PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
- .mmu_features = MMU_FTR_TYPE_40x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .machine_check = machine_check_4xx,
- .platform = "ppc405",
- },
- { /* Xilinx Virtex-4 FX */
- .pvr_mask = 0xfffff000,
- .pvr_value = 0x20011000,
- .cpu_name = "Virtex-4 FX",
- .cpu_features = CPU_FTRS_40X,
- .cpu_user_features = PPC_FEATURE_32 |
- PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
- .mmu_features = MMU_FTR_TYPE_40x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .machine_check = machine_check_4xx,
- .platform = "ppc405",
- },
{ /* 405EP */
.pvr_mask = 0xffff0000,
.pvr_value = 0x51210000,
@@ -1800,19 +1774,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = "ppc440",
},
- { /* 440 in Xilinx Virtex-5 FXT */
- .pvr_mask = 0xfffffff0,
- .pvr_value = 0x7ff21910,
- .cpu_name = "440 in Virtex-5 FXT",
- .cpu_features = CPU_FTRS_44X,
- .cpu_user_features = COMMON_USER_BOOKE,
- .mmu_features = MMU_FTR_TYPE_44x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .cpu_setup = __setup_cpu_440x5,
- .machine_check = machine_check_440A,
- .platform = "ppc440",
- },
{ /* 460EX */
.pvr_mask = 0xffff0006,
.pvr_value = 0x13020002,
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index 6da813b65b42..d06ca51e8443 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -55,23 +55,6 @@ config WALNUT
help
This option enables support for the IBM PPC405GP evaluation board.
-config XILINX_VIRTEX_GENERIC_BOARD
- bool "Generic Xilinx Virtex board"
- depends on 40x
- select XILINX_VIRTEX_II_PRO
- select XILINX_VIRTEX_4_FX
- select XILINX_INTC
- help
- This option enables generic support for Xilinx Virtex based boards.
-
- The generic virtex board support matches any device tree which
- specifies 'xilinx,virtex' in its compatible field. This includes
- the Xilinx ML3xx and ML4xx reference designs using the powerpc
- core.
-
- Most Virtex designs should use this unless it needs to do some
- special configuration at board probe time.
-
config OBS600
bool "OpenBlockS 600"
depends on 40x
@@ -109,20 +92,6 @@ config 405EZ
select IBM_EMAC_MAL_CLR_ICINTSTAT if IBM_EMAC
select IBM_EMAC_MAL_COMMON_ERR if IBM_EMAC
-config XILINX_VIRTEX
- bool
- select DEFAULT_UIMAGE
-
-config XILINX_VIRTEX_II_PRO
- bool
- select XILINX_VIRTEX
- select IBM405_ERR77
- select IBM405_ERR51
-
-config XILINX_VIRTEX_4_FX
- bool
- select XILINX_VIRTEX
-
config STB03xxx
bool
select IBM405_ERR77
diff --git a/arch/powerpc/platforms/40x/Makefile b/arch/powerpc/platforms/40x/Makefile
index 828d78340dd9..e9386deed505 100644
--- a/arch/powerpc/platforms/40x/Makefile
+++ b/arch/powerpc/platforms/40x/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_WALNUT) += walnut.o
-obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD) += virtex.o
obj-$(CONFIG_EP405) += ep405.o
obj-$(CONFIG_PPC40x_SIMPLE) += ppc40x_simple.o
diff --git a/arch/powerpc/platforms/40x/virtex.c b/arch/powerpc/platforms/40x/virtex.c
deleted file mode 100644
index e3d5e095846b..000000000000
--- a/arch/powerpc/platforms/40x/virtex.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Xilinx Virtex (IIpro & 4FX) based board support
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <asm/xilinx_intc.h>
-#include <asm/xilinx_pci.h>
-#include <asm/ppc4xx.h>
-
-static const struct of_device_id xilinx_of_bus_ids[] __initconst = {
- { .compatible = "xlnx,plb-v46-1.00.a", },
- { .compatible = "xlnx,plb-v34-1.01.a", },
- { .compatible = "xlnx,plb-v34-1.02.a", },
- { .compatible = "xlnx,opb-v20-1.10.c", },
- { .compatible = "xlnx,dcr-v29-1.00.a", },
- { .compatible = "xlnx,compound", },
- {}
-};
-
-static int __init virtex_device_probe(void)
-{
- of_platform_bus_probe(NULL, xilinx_of_bus_ids, NULL);
-
- return 0;
-}
-machine_device_initcall(virtex, virtex_device_probe);
-
-static int __init virtex_probe(void)
-{
- if (!of_machine_is_compatible("xlnx,virtex"))
- return 0;
-
- return 1;
-}
-
-define_machine(virtex) {
- .name = "Xilinx Virtex",
- .probe = virtex_probe,
- .setup_arch = xilinx_pci_init,
- .init_IRQ = xilinx_intc_init_tree,
- .get_irq = xintc_get_irq,
- .restart = ppc4xx_reset_system,
- .calibrate_decr = generic_calibrate_decr,
-};
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 25ebe634a661..39e93d23fb38 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -232,33 +232,6 @@ config ICON
help
This option enables support for the AMCC PPC440SPe evaluation board.
-config XILINX_VIRTEX440_GENERIC_BOARD
- bool "Generic Xilinx Virtex 5 FXT board support"
- depends on 44x
- select XILINX_VIRTEX_5_FXT
- select XILINX_INTC
- help
- This option enables generic support for Xilinx Virtex based boards
- that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
-
- The generic virtex board support matches any device tree which
- specifies 'xlnx,virtex440' in its compatible field. This includes
- the Xilinx ML5xx reference designs using the powerpc core.
-
- Most Virtex 5 designs should use this unless it needs to do some
- special configuration at board probe time.
-
-config XILINX_ML510
- bool "Xilinx ML510 extra support"
- depends on XILINX_VIRTEX440_GENERIC_BOARD
- select HAVE_PCI
- select XILINX_PCI if PCI
- select PPC_INDIRECT_PCI if PCI
- select PPC_I8259 if PCI
- help
- This option enables extra support for features on the Xilinx ML510
- board. The ML510 has a PCI bus with ALI south bridge.
-
config PPC44x_SIMPLE
bool "Simple PowerPC 44x board support"
depends on 44x
@@ -354,13 +327,3 @@ config 476FPE_ERR46
config IBM440EP_ERR42
bool
-# Xilinx specific config options.
-config XILINX_VIRTEX
- bool
- select DEFAULT_UIMAGE
-
-# Xilinx Virtex 5 FXT FPGA architecture, selected by a Xilinx board above
-config XILINX_VIRTEX_5_FXT
- bool
- select XILINX_VIRTEX
-
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 1b78c6af821a..5ba031f57652 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -7,8 +7,6 @@ obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_SAM440EP) += sam440ep.o
obj-$(CONFIG_WARP) += warp.o
-obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
-obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
obj-$(CONFIG_ISS4xx) += iss4xx.o
obj-$(CONFIG_CANYONLANDS)+= canyonlands.o
obj-$(CONFIG_CURRITUCK) += ppc476.o
diff --git a/arch/powerpc/platforms/44x/virtex.c b/arch/powerpc/platforms/44x/virtex.c
deleted file mode 100644
index 3eb13ed926ee..000000000000
--- a/arch/powerpc/platforms/44x/virtex.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Xilinx Virtex 5FXT based board support, derived from
- * the Xilinx Virtex (IIpro & 4FX) based board support
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- * Copyright 2008 Xilinx, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <asm/xilinx_intc.h>
-#include <asm/xilinx_pci.h>
-#include <asm/reg.h>
-#include <asm/ppc4xx.h>
-#include "44x.h"
-
-static const struct of_device_id xilinx_of_bus_ids[] __initconst = {
- { .compatible = "simple-bus", },
- { .compatible = "xlnx,plb-v46-1.00.a", },
- { .compatible = "xlnx,plb-v46-1.02.a", },
- { .compatible = "xlnx,plb-v34-1.01.a", },
- { .compatible = "xlnx,plb-v34-1.02.a", },
- { .compatible = "xlnx,opb-v20-1.10.c", },
- { .compatible = "xlnx,dcr-v29-1.00.a", },
- { .compatible = "xlnx,compound", },
- {}
-};
-
-static int __init virtex_device_probe(void)
-{
- of_platform_bus_probe(NULL, xilinx_of_bus_ids, NULL);
-
- return 0;
-}
-machine_device_initcall(virtex, virtex_device_probe);
-
-static int __init virtex_probe(void)
-{
- if (!of_machine_is_compatible("xlnx,virtex440"))
- return 0;
-
- return 1;
-}
-
-define_machine(virtex) {
- .name = "Xilinx Virtex440",
- .probe = virtex_probe,
- .setup_arch = xilinx_pci_init,
- .init_IRQ = xilinx_intc_init_tree,
- .get_irq = xintc_get_irq,
- .calibrate_decr = generic_calibrate_decr,
- .restart = ppc4xx_reset_system,
-};
diff --git a/arch/powerpc/platforms/44x/virtex_ml510.c b/arch/powerpc/platforms/44x/virtex_ml510.c
deleted file mode 100644
index 349f218b335c..000000000000
--- a/arch/powerpc/platforms/44x/virtex_ml510.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <asm/i8259.h>
-#include <linux/pci.h>
-#include "44x.h"
-
-/**
- * ml510_ail_quirk
- */
-static void ml510_ali_quirk(struct pci_dev *dev)
-{
- /* Enable the IDE controller */
- pci_write_config_byte(dev, 0x58, 0x4c);
- /* Assign irq 14 to the primary ide channel */
- pci_write_config_byte(dev, 0x44, 0x0d);
- /* Assign irq 15 to the secondary ide channel */
- pci_write_config_byte(dev, 0x75, 0x0f);
- /* Set the ide controller in native mode */
- pci_write_config_byte(dev, 0x09, 0xff);
-
- /* INTB = disabled, INTA = disabled */
- pci_write_config_byte(dev, 0x48, 0x00);
- /* INTD = disabled, INTC = disabled */
- pci_write_config_byte(dev, 0x4a, 0x00);
- /* Audio = INT7, Modem = disabled. */
- pci_write_config_byte(dev, 0x4b, 0x60);
- /* USB = INT7 */
- pci_write_config_byte(dev, 0x74, 0x06);
-}
-DECLARE_PCI_FIXUP_EARLY(0x10b9, 0x1533, ml510_ali_quirk);
-
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 1f8025383caa..5e6479d409a0 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -317,8 +317,4 @@ config MCU_MPC8349EMITX
also register MCU GPIOs with the generic GPIO API, so you'll able
to use MCU pins as GPIOs.
-config XILINX_PCI
- bool "Xilinx PCI host bridge support"
- depends on PCI && XILINX_VIRTEX
-
endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cb5a5bd2cef5..026b3f01a991 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -31,8 +31,6 @@ obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_IPIC) += ipic.o
-obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
-obj-$(CONFIG_XILINX_PCI) += xilinx_pci.o
obj-$(CONFIG_OF_RTC) += of_rtc.o
obj-$(CONFIG_CPM) += cpm_common.o
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
deleted file mode 100644
index 4a86dcff3fcd..000000000000
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Interrupt controller driver for Xilinx Virtex FPGAs
- *
- * Copyright (C) 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
- */
-
-/*
- * This is a driver for the interrupt controller typically found in
- * Xilinx Virtex FPGA designs.
- *
- * The interrupt sense levels are hard coded into the FPGA design with
- * typically a 1:1 relationship between irq lines and devices (no shared
- * irq lines). Therefore, this driver does not attempt to handle edge
- * and level interrupts differently.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/i8259.h>
-#include <asm/irq.h>
-#include <linux/irqchip.h>
-
-#if defined(CONFIG_PPC_I8259)
-/*
- * Support code for cascading to 8259 interrupt controllers
- */
-static void xilinx_i8259_cascade(struct irq_desc *desc)
-{
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned int cascade_irq = i8259_irq();
-
- if (cascade_irq)
- generic_handle_irq(cascade_irq);
-
- /* Let xilinx_intc end the interrupt */
- chip->irq_unmask(&desc->irq_data);
-}
-
-static void __init xilinx_i8259_setup_cascade(void)
-{
- struct device_node *cascade_node;
- int cascade_irq;
-
- /* Initialize i8259 controller */
- cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
- if (!cascade_node)
- return;
-
- cascade_irq = irq_of_parse_and_map(cascade_node, 0);
- if (!cascade_irq) {
- pr_err("virtex_ml510: Failed to map cascade interrupt\n");
- goto out;
- }
-
- i8259_init(cascade_node, 0);
- irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
-
- /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
- /* This looks like a dirty hack to me --gcl */
- outb(0xc0, 0x4d0);
- outb(0xc0, 0x4d1);
-
- out:
- of_node_put(cascade_node);
-}
-#else
-static inline void xilinx_i8259_setup_cascade(void) { return; }
-#endif /* defined(CONFIG_PPC_I8259) */
-
-/*
- * Initialize master Xilinx interrupt controller
- */
-void __init xilinx_intc_init_tree(void)
-{
- irqchip_init();
- xilinx_i8259_setup_cascade();
-}
diff --git a/arch/powerpc/sysdev/xilinx_pci.c b/arch/powerpc/sysdev/xilinx_pci.c
deleted file mode 100644
index fea5667699ed..000000000000
--- a/arch/powerpc/sysdev/xilinx_pci.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * PCI support for Xilinx plbv46_pci soft-core which can be used on
- * Xilinx Virtex ML410 / ML510 boards.
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
- * by Benjamin Herrenschmidt.
- * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/ioport.h>
-#include <linux/of.h>
-#include <linux/pci.h>
-#include <mm/mmu_decl.h>
-#include <asm/io.h>
-#include <asm/xilinx_pci.h>
-
-#define XPLB_PCI_ADDR 0x10c
-#define XPLB_PCI_DATA 0x110
-#define XPLB_PCI_BUS 0x114
-
-#define PCI_HOST_ENABLE_CMD PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
-
-static const struct of_device_id xilinx_pci_match[] = {
- { .compatible = "xlnx,plbv46-pci-1.03.a", },
- {}
-};
-
-/**
- * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
- */
-static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
-{
- struct pci_controller *hose;
- int i;
-
- if (dev->devfn || dev->bus->self)
- return;
-
- hose = pci_bus_to_host(dev->bus);
- if (!hose)
- return;
-
- if (!of_match_node(xilinx_pci_match, hose->dn))
- return;
-
- /* Hide the PCI host BARs from the kernel as their content doesn't
- * fit well in the resource management
- */
- for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
- }
-
- dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
- pci_name(dev));
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
-
-/**
- * xilinx_pci_exclude_device - Don't do config access for non-root bus
- *
- * This is a hack. Config access to any bus other than bus 0 does not
- * currently work on the ML510 so we prevent it here.
- */
-static int
-xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
-{
- return (bus != 0);
-}
-
-/**
- * xilinx_pci_init - Find and register a Xilinx PCI host bridge
- */
-void __init xilinx_pci_init(void)
-{
- struct pci_controller *hose;
- struct resource r;
- void __iomem *pci_reg;
- struct device_node *pci_node;
-
- pci_node = of_find_matching_node(NULL, xilinx_pci_match);
- if(!pci_node)
- return;
-
- if (of_address_to_resource(pci_node, 0, &r)) {
- pr_err("xilinx-pci: cannot resolve base address\n");
- return;
- }
-
- hose = pcibios_alloc_controller(pci_node);
- if (!hose) {
- pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
- return;
- }
-
- /* Setup config space */
- setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
- r.start + XPLB_PCI_DATA,
- PPC_INDIRECT_TYPE_SET_CFG_TYPE);
-
- /* According to the xilinx plbv46_pci documentation the soft-core starts
- * a self-init when the bus master enable bit is set. Without this bit
- * set the pci bus can't be scanned.
- */
- early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
-
- /* Set the max latency timer to 255 */
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
-
- /* Set the max bus number to 255 */
- pci_reg = of_iomap(pci_node, 0);
- out_8(pci_reg + XPLB_PCI_BUS, 0xff);
- iounmap(pci_reg);
-
- /* Nothing past the root bridge is working right now. By default
- * exclude config access to anything except bus 0 */
- if (!ppc_md.pci_exclude_device)
- ppc_md.pci_exclude_device = xilinx_pci_exclude_device;
-
- /* Register the host bridge with the linux kernel! */
- pci_process_bridge_OF_ranges(hose, pci_node, 1);
-
- pr_info("xilinx-pci: Registered PCI host bridge\n");
-}
diff --git a/arch/powerpc/xmon/ppc-dis.c b/arch/powerpc/xmon/ppc-dis.c
index 75fa98221d48..a91ac589b401 100644
--- a/arch/powerpc/xmon/ppc-dis.c
+++ b/arch/powerpc/xmon/ppc-dis.c
@@ -224,12 +224,6 @@ int print_insn_powerpc (unsigned long insn, unsigned long memaddr)
print_address(memaddr + value);
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
print_address(value & 0xffffffff);
- else if ((operand->flags & PPC_OPERAND_FSL) != 0)
- printf("fsl%ld", value);
- else if ((operand->flags & PPC_OPERAND_FCR) != 0)
- printf("fcr%ld", value);
- else if ((operand->flags & PPC_OPERAND_UDI) != 0)
- printf("%ld", value);
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
index dfb80810b16c..918845e777fd 100644
--- a/arch/powerpc/xmon/ppc-opc.c
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -857,29 +857,6 @@ const struct powerpc_operand powerpc_operands[] =
#define HTM_A XFL_L
{ 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
- /* Xilinx APU related masks and macros */
-#define FCRT XFL_L + 1
-#define FCRT_MASK (0x1f << 21)
- { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
-
- /* Xilinx FSL related masks and macros */
-#define FSL FCRT + 1
-#define FSL_MASK (0x1f << 11)
- { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
-
- /* Xilinx UDI related masks and macros */
-#define URT FSL + 1
- { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
-
-#define URA URT + 1
- { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
-
-#define URB URA + 1
- { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
-
-#define URC URB + 1
- { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
-
/* The VLESIMM field in a D form instruction. */
#define VLESIMM URC + 1
{ 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
diff --git a/arch/powerpc/xmon/ppc.h b/arch/powerpc/xmon/ppc.h
index d00f33dcf192..37717b1f7bd7 100644
--- a/arch/powerpc/xmon/ppc.h
+++ b/arch/powerpc/xmon/ppc.h
@@ -388,11 +388,6 @@ extern const unsigned int num_powerpc_operands;
/* Valid range of operand is 0..n rather than 0..n-1. */
#define PPC_OPERAND_PLUS1 (0x10000)
-/* Xilinx APU and FSL related operands */
-#define PPC_OPERAND_FSL (0x20000)
-#define PPC_OPERAND_FCR (0x40000)
-#define PPC_OPERAND_UDI (0x80000)
-
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 26956c006987..0ccbd6fd6de1 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -316,7 +316,7 @@ config DTLK
config XILINX_HWICAP
tristate "Xilinx HWICAP Support"
- depends on XILINX_VIRTEX || MICROBLAZE
+ depends on MICROBLAZE
help
This option enables support for Xilinx Internal Configuration
Access Port (ICAP) driver. The ICAP is used on Xilinx Virtex
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index f65991a67af2..b174650e0f09 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -2007,7 +2007,7 @@ config FB_PS3_DEFAULT_SIZE_M
config FB_XILINX
tristate "Xilinx frame buffer support"
- depends on FB && (XILINX_VIRTEX || MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ depends on FB && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
--
2.26.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* [PATCH 2/2] powerpc: Remove Xilinx PPC405/PPC440 support
@ 2020-03-27 12:12 ` Michal Simek
0 siblings, 0 replies; 104+ messages in thread
From: Michal Simek @ 2020-03-27 12:12 UTC (permalink / raw)
To: linux-kernel, monstr, michal.simek, git, sfr, marc.zyngier
Cc: Kate Stewart, Mark Rutland, Desnes A. Nunes do Rosario,
Geert Uytterhoeven, linux-doc, linux-fbdev, dri-devel,
Richard Fontana, Paul Mackerras, Miquel Raynal,
Mauro Carvalho Chehab, Sasha Levin, Jonathan Corbet,
Michael Ellerman, Masahiro Yamada, YueHaibing,
Krzysztof Kozlowski, linux-arm-kernel, Leonardo Bras,
Matt Porter, devicetree, Andrew Donnellan, Arnd Bergmann,
Bartlomiej Zolnierkiewicz, Alistair Popple, linuxppc-dev,
Nicholas Piggin, Alexios Zavras, Rob Herring, Jonathan Cameron,
Thomas Gleixner, Andy Shevchenko, Allison Randal,
Christophe Leroy, Wei Hu, Greg Kroah-Hartman, Nick Desaulniers,
Armijn Hemel, Enrico Weigelt, David S. Miller,
Thiago Jung Bauermann
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="windows-1254", Size: 79478 bytes --]
The latest Xilinx design tools called ISE and EDK has been released in
October 2013. New tool doesn't support any PPC405/PPC440 new designs.
These platforms are no longer supported and tested.
PowerPC 405/440 port is orphan from 2013 by
commit cdeb89943bfc ("MAINTAINERS: Fix incorrect status tag") and
commit 19624236cce1 ("MAINTAINERS: Update Grant's email address and maintainership")
that's why it is time to remove the support fot these platforms.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Documentation/devicetree/bindings/xilinx.txt | 143 ------
Documentation/powerpc/bootwrapper.rst | 28 +-
MAINTAINERS | 6 -
arch/powerpc/Kconfig.debug | 2 +-
arch/powerpc/boot/Makefile | 7 +-
arch/powerpc/boot/dts/Makefile | 1 -
arch/powerpc/boot/dts/virtex440-ml507.dts | 406 ----------------
arch/powerpc/boot/dts/virtex440-ml510.dts | 466 -------------------
arch/powerpc/boot/ops.h | 1 -
arch/powerpc/boot/serial.c | 5 -
arch/powerpc/boot/uartlite.c | 79 ----
arch/powerpc/boot/virtex.c | 97 ----
arch/powerpc/boot/virtex405-head.S | 31 --
arch/powerpc/boot/wrapper | 8 -
arch/powerpc/configs/40x/virtex_defconfig | 75 ---
arch/powerpc/configs/44x/virtex5_defconfig | 74 ---
arch/powerpc/configs/ppc40x_defconfig | 8 -
arch/powerpc/configs/ppc44x_defconfig | 8 -
arch/powerpc/include/asm/xilinx_intc.h | 16 -
arch/powerpc/include/asm/xilinx_pci.h | 21 -
arch/powerpc/kernel/cputable.c | 39 --
arch/powerpc/platforms/40x/Kconfig | 31 --
arch/powerpc/platforms/40x/Makefile | 1 -
arch/powerpc/platforms/40x/virtex.c | 54 ---
arch/powerpc/platforms/44x/Kconfig | 37 --
arch/powerpc/platforms/44x/Makefile | 2 -
arch/powerpc/platforms/44x/virtex.c | 60 ---
arch/powerpc/platforms/44x/virtex_ml510.c | 30 --
arch/powerpc/platforms/Kconfig | 4 -
arch/powerpc/sysdev/Makefile | 2 -
arch/powerpc/sysdev/xilinx_intc.c | 88 ----
arch/powerpc/sysdev/xilinx_pci.c | 132 ------
arch/powerpc/xmon/ppc-dis.c | 6 -
arch/powerpc/xmon/ppc-opc.c | 23 -
arch/powerpc/xmon/ppc.h | 5 -
drivers/char/Kconfig | 2 +-
drivers/video/fbdev/Kconfig | 2 +-
37 files changed, 7 insertions(+), 1993 deletions(-)
delete mode 100644 arch/powerpc/boot/dts/virtex440-ml507.dts
delete mode 100644 arch/powerpc/boot/dts/virtex440-ml510.dts
delete mode 100644 arch/powerpc/boot/uartlite.c
delete mode 100644 arch/powerpc/boot/virtex.c
delete mode 100644 arch/powerpc/boot/virtex405-head.S
delete mode 100644 arch/powerpc/configs/40x/virtex_defconfig
delete mode 100644 arch/powerpc/configs/44x/virtex5_defconfig
delete mode 100644 arch/powerpc/include/asm/xilinx_intc.h
delete mode 100644 arch/powerpc/include/asm/xilinx_pci.h
delete mode 100644 arch/powerpc/platforms/40x/virtex.c
delete mode 100644 arch/powerpc/platforms/44x/virtex.c
delete mode 100644 arch/powerpc/platforms/44x/virtex_ml510.c
delete mode 100644 arch/powerpc/sysdev/xilinx_intc.c
delete mode 100644 arch/powerpc/sysdev/xilinx_pci.c
diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt
index d058ace29345..28199b31fe5e 100644
--- a/Documentation/devicetree/bindings/xilinx.txt
+++ b/Documentation/devicetree/bindings/xilinx.txt
@@ -86,149 +86,6 @@
xlnx,use-parity = <0>;
};
- Some IP cores actually implement 2 or more logical devices. In
- this case, the device should still describe the whole IP core with
- a single node and add a child node for each logical device. The
- ranges property can be used to translate from parent IP-core to the
- registers of each device. In addition, the parent node should be
- compatible with the bus type 'xlnx,compound', and should contain
- #address-cells and #size-cells, as with any other bus. (Note: this
- makes the assumption that both logical devices have the same bus
- binding. If this is not true, then separate nodes should be used
- for each logical device). The 'cell-index' property can be used to
- enumerate logical devices within an IP core. For example, the
- following is the system.mhs entry for the dual ps2 controller found
- on the ml403 reference design.
-
- BEGIN opb_ps2_dual_ref
- PARAMETER INSTANCE = opb_ps2_dual_ref_0
- PARAMETER HW_VER = 1.00.a
- PARAMETER C_BASEADDR = 0xA9000000
- PARAMETER C_HIGHADDR = 0xA9001FFF
- BUS_INTERFACE SOPB = opb_v20_0
- PORT Sys_Intr1 = ps2_1_intr
- PORT Sys_Intr2 = ps2_2_intr
- PORT Clkin1 = ps2_clk_rx_1
- PORT Clkin2 = ps2_clk_rx_2
- PORT Clkpd1 = ps2_clk_tx_1
- PORT Clkpd2 = ps2_clk_tx_2
- PORT Rx1 = ps2_d_rx_1
- PORT Rx2 = ps2_d_rx_2
- PORT Txpd1 = ps2_d_tx_1
- PORT Txpd2 = ps2_d_tx_2
- END
-
- It would result in the following device tree nodes:
-
- opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ranges = <0 a9000000 2000>;
- // If this device had extra parameters, then they would
- // go here.
- ps2@0 {
- compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
- reg = <0 40>;
- interrupt-parent = <&opb_intc_0>;
- interrupts = <3 0>;
- cell-index = <0>;
- };
- ps2@1000 {
- compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
- reg = <1000 40>;
- interrupt-parent = <&opb_intc_0>;
- interrupts = <3 0>;
- cell-index = <0>;
- };
- };
-
- Also, the system.mhs file defines bus attachments from the processor
- to the devices. The device tree structure should reflect the bus
- attachments. Again an example; this system.mhs fragment:
-
- BEGIN ppc405_virtex4
- PARAMETER INSTANCE = ppc405_0
- PARAMETER HW_VER = 1.01.a
- BUS_INTERFACE DPLB = plb_v34_0
- BUS_INTERFACE IPLB = plb_v34_0
- END
-
- BEGIN opb_intc
- PARAMETER INSTANCE = opb_intc_0
- PARAMETER HW_VER = 1.00.c
- PARAMETER C_BASEADDR = 0xD1000FC0
- PARAMETER C_HIGHADDR = 0xD1000FDF
- BUS_INTERFACE SOPB = opb_v20_0
- END
-
- BEGIN opb_uart16550
- PARAMETER INSTANCE = opb_uart16550_0
- PARAMETER HW_VER = 1.00.d
- PARAMETER C_BASEADDR = 0xa0000000
- PARAMETER C_HIGHADDR = 0xa0001FFF
- BUS_INTERFACE SOPB = opb_v20_0
- END
-
- BEGIN plb_v34
- PARAMETER INSTANCE = plb_v34_0
- PARAMETER HW_VER = 1.02.a
- END
-
- BEGIN plb_bram_if_cntlr
- PARAMETER INSTANCE = plb_bram_if_cntlr_0
- PARAMETER HW_VER = 1.00.b
- PARAMETER C_BASEADDR = 0xFFFF0000
- PARAMETER C_HIGHADDR = 0xFFFFFFFF
- BUS_INTERFACE SPLB = plb_v34_0
- END
-
- BEGIN plb2opb_bridge
- PARAMETER INSTANCE = plb2opb_bridge_0
- PARAMETER HW_VER = 1.01.a
- PARAMETER C_RNG0_BASEADDR = 0x20000000
- PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
- PARAMETER C_RNG1_BASEADDR = 0x60000000
- PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
- PARAMETER C_RNG2_BASEADDR = 0x80000000
- PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
- PARAMETER C_RNG3_BASEADDR = 0xC0000000
- PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
- BUS_INTERFACE SPLB = plb_v34_0
- BUS_INTERFACE MOPB = opb_v20_0
- END
-
- Gives this device tree (some properties removed for clarity):
-
- plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v34-1.02.a";
- device_type = "ibm,plb";
- ranges; // 1:1 translation
-
- plb_bram_if_cntrl_0: bram@ffff0000 {
- reg = <ffff0000 10000>;
- }
-
- opb@20000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <20000000 20000000 20000000
- 60000000 60000000 20000000
- 80000000 80000000 40000000
- c0000000 c0000000 20000000>;
-
- opb_uart16550_0: serial@a0000000 {
- reg = <a00000000 2000>;
- };
-
- opb_intc_0: interrupt-controller@d1000fc0 {
- reg = <d1000fc0 20>;
- };
- };
- };
-
That covers the general approach to binding xilinx IP cores into the
device tree. The following are bindings for specific devices:
diff --git a/Documentation/powerpc/bootwrapper.rst b/Documentation/powerpc/bootwrapper.rst
index a6292afba573..cdfa2bc8425f 100644
--- a/Documentation/powerpc/bootwrapper.rst
+++ b/Documentation/powerpc/bootwrapper.rst
@@ -70,28 +70,6 @@ Currently, the following image format targets exist:
kernel with this image type and it depends entirely on
the embedded device tree for all information.
- The simpleImage is useful for booting systems with
- an unknown firmware interface or for booting from
- a debugger when no firmware is present (such as on
- the Xilinx Virtex platform). The only assumption that
- simpleImage makes is that RAM is correctly initialized
- and that the MMU is either off or has RAM mapped to
- base address 0.
-
- simpleImage also supports inserting special platform
- specific initialization code to the start of the bootup
- sequence. The virtex405 platform uses this feature to
- ensure that the cache is invalidated before caching
- is enabled. Platform specific initialization code is
- added as part of the wrapper script and is keyed on
- the image target name. For example, all
- simpleImage.virtex405-* targets will add the
- virtex405-head.S initialization code (This also means
- that the dts file for virtex405 targets should be
- named (virtex405-<board>.dts). Search the wrapper
- script for 'virtex405' and see the file
- arch/powerpc/boot/virtex405-head.S for details.
-
treeImage.%; Image format for used with OpenBIOS firmware found
on some ppc4xx hardware. This image embeds a device
tree blob inside the image.
@@ -116,10 +94,8 @@ Image types which embed a device tree blob (simpleImage, dtbImage, treeImage,
and cuImage) all generate the device tree blob from a file in the
arch/powerpc/boot/dts/ directory. The Makefile selects the correct device
tree source based on the name of the target. Therefore, if the kernel is
-built with 'make treeImage.walnut simpleImage.virtex405-ml403', then the
-build system will use arch/powerpc/boot/dts/walnut.dts to build
-treeImage.walnut and arch/powerpc/boot/dts/virtex405-ml403.dts to build
-the simpleImage.virtex405-ml403.
+built with 'make treeImage.walnut', then the build system will use
+arch/powerpc/boot/dts/walnut.dts to build treeImage.walnut.
Two special targets called 'zImage' and 'zImage.initrd' also exist. These
targets build all the default images as selected by the kernel configuration.
diff --git a/MAINTAINERS b/MAINTAINERS
index a0d86490c2c6..842a9bbc2013 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9668,12 +9668,6 @@ L: linuxppc-dev@lists.ozlabs.org
S: Maintained
F: arch/powerpc/platforms/8xx/
-LINUX FOR POWERPC EMBEDDED XILINX VIRTEX
-L: linuxppc-dev@lists.ozlabs.org
-S: Orphan
-F: arch/powerpc/*/*virtex*
-F: arch/powerpc/*/*/*virtex*
-
LINUX FOR POWERPC PA SEMI PWRFICIENT
L: linuxppc-dev@lists.ozlabs.org
S: Orphan
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 0b063830eea8..b88900f4832f 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -230,7 +230,7 @@ config PPC_EARLY_DEBUG_40x
help
Select this to enable early debugging for IBM 40x chips via the
inbuilt serial port. This works on chips with a 16550 compatible
- UART. Xilinx chips with uartlite cannot use this option.
+ UART.
config PPC_EARLY_DEBUG_CPM
bool "Early serial debugging for Freescale CPM-based serial ports"
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index c53a1b8bba8b..d8077b7071dd 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -79,7 +79,6 @@ $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu@5
$(obj)/treeboot-iss4xx.o: BOOTCFLAGS += -mcpu@5
$(obj)/treeboot-currituck.o: BOOTCFLAGS += -mcpu@5
$(obj)/treeboot-akebono.o: BOOTCFLAGS += -mcpu@5
-$(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu@5
# The pre-boot decompressors pull in a lot of kernel headers and other source
# files. This creates a bit of a dependency headache since we need to copy
@@ -129,14 +128,12 @@ src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
-src-wlib-$(CONFIG_XILINX_VIRTEX) += uartlite.c
src-wlib-$(CONFIG_CPM) += cpm-serial.c
src-plat-y := of.c epapr.c
src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
treeboot-walnut.c cuboot-acadia.c \
- cuboot-kilauea.c simpleboot.c \
- virtex405-head.S virtex.c
+ cuboot-kilauea.c simpleboot.c
src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
cuboot-bamboo.c cuboot-sam440ep.c \
cuboot-sequoia.c cuboot-rainier.c \
@@ -144,7 +141,7 @@ src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
cuboot-warp.c cuboot-yosemite.c \
treeboot-iss4xx.c treeboot-currituck.c \
treeboot-akebono.c \
- simpleboot.c fixed-head.S virtex.c
+ simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
diff --git a/arch/powerpc/boot/dts/Makefile b/arch/powerpc/boot/dts/Makefile
index 1cbc0e4ce857..fb335d05aae8 100644
--- a/arch/powerpc/boot/dts/Makefile
+++ b/arch/powerpc/boot/dts/Makefile
@@ -4,4 +4,3 @@ subdir-y += fsl
dtstree := $(srctree)/$(src)
dtb-$(CONFIG_OF_ALL_DTBS) := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
-dtb-$(CONFIG_XILINX_VIRTEX440_GENERIC_BOARD) += virtex440-ml507.dtb virtex440-ml510.dtb
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
deleted file mode 100644
index 66f1c6312de6..000000000000
--- a/arch/powerpc/boot/dts/virtex440-ml507.dts
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * This file supports the Xilinx ML507 board with the 440 processor.
- * A reference design for the FPGA is provided at http://git.xilinx.com.
- *
- * (C) Copyright 2008 Xilinx, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
- * ---
- *
- * Device Tree Generator version: 1.1
- *
- * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
- *
- * XPS project directory: ml507_ppc440_emb_ref
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,virtex440";
- dcr-parent = <&ppc440_0>;
- model = "testing";
- DDR2_SDRAM: memory@0 {
- device_type = "memory";
- reg = < 0 0x10000000 >;
- } ;
- chosen {
- bootargs = "console=ttyS0 root=/dev/ram";
- stdout-path = &RS232_Uart_1;
- } ;
- cpus {
- #address-cells = <1>;
- #cpus = <1>;
- #size-cells = <0>;
- ppc440_0: cpu@0 {
- clock-frequency = <400000000>;
- compatible = "PowerPC,440", "ibm,ppc440";
- d-cache-line-size = <0x20>;
- d-cache-size = <0x8000>;
- dcr-access-method = "native";
- dcr-controller ;
- device_type = "cpu";
- i-cache-line-size = <0x20>;
- i-cache-size = <0x8000>;
- model = "PowerPC,440";
- reg = <0>;
- timebase-frequency = <400000000>;
- xlnx,apu-control = <1>;
- xlnx,apu-udi-0 = <0>;
- xlnx,apu-udi-1 = <0>;
- xlnx,apu-udi-10 = <0>;
- xlnx,apu-udi-11 = <0>;
- xlnx,apu-udi-12 = <0>;
- xlnx,apu-udi-13 = <0>;
- xlnx,apu-udi-14 = <0>;
- xlnx,apu-udi-15 = <0>;
- xlnx,apu-udi-2 = <0>;
- xlnx,apu-udi-3 = <0>;
- xlnx,apu-udi-4 = <0>;
- xlnx,apu-udi-5 = <0>;
- xlnx,apu-udi-6 = <0>;
- xlnx,apu-udi-7 = <0>;
- xlnx,apu-udi-8 = <0>;
- xlnx,apu-udi-9 = <0>;
- xlnx,dcr-autolock-enable = <1>;
- xlnx,dcu-rd-ld-cache-plb-prio = <0>;
- xlnx,dcu-rd-noncache-plb-prio = <0>;
- xlnx,dcu-rd-touch-plb-prio = <0>;
- xlnx,dcu-rd-urgent-plb-prio = <0>;
- xlnx,dcu-wr-flush-plb-prio = <0>;
- xlnx,dcu-wr-store-plb-prio = <0>;
- xlnx,dcu-wr-urgent-plb-prio = <0>;
- xlnx,dma0-control = <0>;
- xlnx,dma0-plb-prio = <0>;
- xlnx,dma0-rxchannelctrl = <0x1010000>;
- xlnx,dma0-rxirqtimer = <0x3ff>;
- xlnx,dma0-txchannelctrl = <0x1010000>;
- xlnx,dma0-txirqtimer = <0x3ff>;
- xlnx,dma1-control = <0>;
- xlnx,dma1-plb-prio = <0>;
- xlnx,dma1-rxchannelctrl = <0x1010000>;
- xlnx,dma1-rxirqtimer = <0x3ff>;
- xlnx,dma1-txchannelctrl = <0x1010000>;
- xlnx,dma1-txirqtimer = <0x3ff>;
- xlnx,dma2-control = <0>;
- xlnx,dma2-plb-prio = <0>;
- xlnx,dma2-rxchannelctrl = <0x1010000>;
- xlnx,dma2-rxirqtimer = <0x3ff>;
- xlnx,dma2-txchannelctrl = <0x1010000>;
- xlnx,dma2-txirqtimer = <0x3ff>;
- xlnx,dma3-control = <0>;
- xlnx,dma3-plb-prio = <0>;
- xlnx,dma3-rxchannelctrl = <0x1010000>;
- xlnx,dma3-rxirqtimer = <0x3ff>;
- xlnx,dma3-txchannelctrl = <0x1010000>;
- xlnx,dma3-txirqtimer = <0x3ff>;
- xlnx,endian-reset = <0>;
- xlnx,generate-plb-timespecs = <1>;
- xlnx,icu-rd-fetch-plb-prio = <0>;
- xlnx,icu-rd-spec-plb-prio = <0>;
- xlnx,icu-rd-touch-plb-prio = <0>;
- xlnx,interconnect-imask = <0xffffffff>;
- xlnx,mplb-allow-lock-xfer = <1>;
- xlnx,mplb-arb-mode = <0>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-counter = <0x500>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-max-burst = <8>;
- xlnx,mplb-native-dwidth = <0x80>;
- xlnx,mplb-p2p = <0>;
- xlnx,mplb-prio-dcur = <2>;
- xlnx,mplb-prio-dcuw = <3>;
- xlnx,mplb-prio-icu = <4>;
- xlnx,mplb-prio-splb0 = <1>;
- xlnx,mplb-prio-splb1 = <0>;
- xlnx,mplb-read-pipe-enable = <1>;
- xlnx,mplb-sync-tattribute = <0>;
- xlnx,mplb-wdog-enable = <1>;
- xlnx,mplb-write-pipe-enable = <1>;
- xlnx,mplb-write-post-enable = <1>;
- xlnx,num-dma = <1>;
- xlnx,pir = <0xf>;
- xlnx,ppc440mc-addr-base = <0>;
- xlnx,ppc440mc-addr-high = <0xfffffff>;
- xlnx,ppc440mc-arb-mode = <0>;
- xlnx,ppc440mc-bank-conflict-mask = <0xc00000>;
- xlnx,ppc440mc-control = <0xf810008f>;
- xlnx,ppc440mc-max-burst = <8>;
- xlnx,ppc440mc-prio-dcur = <2>;
- xlnx,ppc440mc-prio-dcuw = <3>;
- xlnx,ppc440mc-prio-icu = <4>;
- xlnx,ppc440mc-prio-splb0 = <1>;
- xlnx,ppc440mc-prio-splb1 = <0>;
- xlnx,ppc440mc-row-conflict-mask = <0x3ffe00>;
- xlnx,ppcdm-asyncmode = <0>;
- xlnx,ppcds-asyncmode = <0>;
- xlnx,user-reset = <0>;
- DMA0: sdma@80 {
- compatible = "xlnx,ll-dma-1.00.a";
- dcr-reg = < 0x80 0x11 >;
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 10 2 11 2 >;
- } ;
- } ;
- } ;
- plb_v46_0: plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
- ranges ;
- DIP_Switches_8Bit: gpio@81460000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 7 2 >;
- reg = < 0x81460000 0x10000 >;
- xlnx,all-inputs = <1>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <8>;
- xlnx,interrupt-present = <1>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- FLASH: flash@fc000000 {
- bank-width = <2>;
- compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
- reg = < 0xfc000000 0x2000000 >;
- xlnx,family = "virtex5";
- xlnx,include-datawidth-matching-0 = <0x1>;
- xlnx,include-datawidth-matching-1 = <0x0>;
- xlnx,include-datawidth-matching-2 = <0x0>;
- xlnx,include-datawidth-matching-3 = <0x0>;
- xlnx,include-negedge-ioregs = <0x0>;
- xlnx,include-plb-ipif = <0x1>;
- xlnx,include-wrbuf = <0x1>;
- xlnx,max-mem-width = <0x10>;
- xlnx,mch-native-dwidth = <0x20>;
- xlnx,mch-plb-clk-period-ps = <0x2710>;
- xlnx,mch-splb-awidth = <0x20>;
- xlnx,mch0-accessbuf-depth = <0x10>;
- xlnx,mch0-protocol = <0x0>;
- xlnx,mch0-rddatabuf-depth = <0x10>;
- xlnx,mch1-accessbuf-depth = <0x10>;
- xlnx,mch1-protocol = <0x0>;
- xlnx,mch1-rddatabuf-depth = <0x10>;
- xlnx,mch2-accessbuf-depth = <0x10>;
- xlnx,mch2-protocol = <0x0>;
- xlnx,mch2-rddatabuf-depth = <0x10>;
- xlnx,mch3-accessbuf-depth = <0x10>;
- xlnx,mch3-protocol = <0x0>;
- xlnx,mch3-rddatabuf-depth = <0x10>;
- xlnx,mem0-width = <0x10>;
- xlnx,mem1-width = <0x20>;
- xlnx,mem2-width = <0x20>;
- xlnx,mem3-width = <0x20>;
- xlnx,num-banks-mem = <0x1>;
- xlnx,num-channels = <0x2>;
- xlnx,priority-mode = <0x0>;
- xlnx,synch-mem-0 = <0x0>;
- xlnx,synch-mem-1 = <0x0>;
- xlnx,synch-mem-2 = <0x0>;
- xlnx,synch-mem-3 = <0x0>;
- xlnx,synch-pipedelay-0 = <0x2>;
- xlnx,synch-pipedelay-1 = <0x2>;
- xlnx,synch-pipedelay-2 = <0x2>;
- xlnx,synch-pipedelay-3 = <0x2>;
- xlnx,tavdv-ps-mem-0 = <0x1adb0>;
- xlnx,tavdv-ps-mem-1 = <0x3a98>;
- xlnx,tavdv-ps-mem-2 = <0x3a98>;
- xlnx,tavdv-ps-mem-3 = <0x3a98>;
- xlnx,tcedv-ps-mem-0 = <0x1adb0>;
- xlnx,tcedv-ps-mem-1 = <0x3a98>;
- xlnx,tcedv-ps-mem-2 = <0x3a98>;
- xlnx,tcedv-ps-mem-3 = <0x3a98>;
- xlnx,thzce-ps-mem-0 = <0x88b8>;
- xlnx,thzce-ps-mem-1 = <0x1b58>;
- xlnx,thzce-ps-mem-2 = <0x1b58>;
- xlnx,thzce-ps-mem-3 = <0x1b58>;
- xlnx,thzoe-ps-mem-0 = <0x1b58>;
- xlnx,thzoe-ps-mem-1 = <0x1b58>;
- xlnx,thzoe-ps-mem-2 = <0x1b58>;
- xlnx,thzoe-ps-mem-3 = <0x1b58>;
- xlnx,tlzwe-ps-mem-0 = <0x88b8>;
- xlnx,tlzwe-ps-mem-1 = <0x0>;
- xlnx,tlzwe-ps-mem-2 = <0x0>;
- xlnx,tlzwe-ps-mem-3 = <0x0>;
- xlnx,twc-ps-mem-0 = <0x2af8>;
- xlnx,twc-ps-mem-1 = <0x3a98>;
- xlnx,twc-ps-mem-2 = <0x3a98>;
- xlnx,twc-ps-mem-3 = <0x3a98>;
- xlnx,twp-ps-mem-0 = <0x11170>;
- xlnx,twp-ps-mem-1 = <0x2ee0>;
- xlnx,twp-ps-mem-2 = <0x2ee0>;
- xlnx,twp-ps-mem-3 = <0x2ee0>;
- xlnx,xcl0-linesize = <0x4>;
- xlnx,xcl0-writexfer = <0x1>;
- xlnx,xcl1-linesize = <0x4>;
- xlnx,xcl1-writexfer = <0x1>;
- xlnx,xcl2-linesize = <0x4>;
- xlnx,xcl2-writexfer = <0x1>;
- xlnx,xcl3-linesize = <0x4>;
- xlnx,xcl3-writexfer = <0x1>;
- } ;
- Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ethernet@81c00000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "xlnx,xps-ll-temac-1.01.b";
- device_type = "network";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 5 2 >;
- llink-connected = <&DMA0>;
- local-mac-address = [ 02 00 00 00 00 00 ];
- reg = < 0x81c00000 0x40 >;
- xlnx,bus2core-clk-ratio = <1>;
- xlnx,phy-type = <1>;
- xlnx,phyaddr = <1>;
- xlnx,rxcsum = <1>;
- xlnx,rxfifo = <0x1000>;
- xlnx,temac-type = <0>;
- xlnx,txcsum = <1>;
- xlnx,txfifo = <0x1000>;
- phy-handle = <&phy7>;
- clock-frequency = <100000000>;
- phy7: phy@7 {
- compatible = "marvell,88e1111";
- reg = <7>;
- } ;
- } ;
- } ;
- IIC_EEPROM: i2c@81600000 {
- compatible = "xlnx,xps-iic-2.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 6 2 >;
- reg = < 0x81600000 0x10000 >;
- xlnx,clk-freq = <0x5f5e100>;
- xlnx,family = "virtex5";
- xlnx,gpo-width = <0x1>;
- xlnx,iic-freq = <0x186a0>;
- xlnx,scl-inertial-delay = <0x0>;
- xlnx,sda-inertial-delay = <0x0>;
- xlnx,ten-bit-adr = <0x0>;
- } ;
- LEDs_8Bit: gpio@81400000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81400000 0x10000 >;
- xlnx,all-inputs = <0>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <8>;
- xlnx,interrupt-present = <0>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- LEDs_Positions: gpio@81420000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81420000 0x10000 >;
- xlnx,all-inputs = <0>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <5>;
- xlnx,interrupt-present = <0>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- Push_Buttons_5Bit: gpio@81440000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 8 2 >;
- reg = < 0x81440000 0x10000 >;
- xlnx,all-inputs = <1>;
- xlnx,all-inputs-2 = <0>;
- xlnx,dout-default = <0>;
- xlnx,dout-default-2 = <0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <5>;
- xlnx,interrupt-present = <1>;
- xlnx,is-bidir = <1>;
- xlnx,is-bidir-2 = <1>;
- xlnx,is-dual = <0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- RS232_Uart_1: serial@83e00000 {
- clock-frequency = <100000000>;
- compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
- current-speed = <9600>;
- device_type = "serial";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 9 2 >;
- reg = < 0x83e00000 0x10000 >;
- reg-offset = <0x1003>;
- reg-shift = <2>;
- xlnx,family = "virtex5";
- xlnx,has-external-rclk = <0>;
- xlnx,has-external-xin = <0>;
- xlnx,is-a-16550 = <1>;
- } ;
- SysACE_CompactFlash: sysace@83600000 {
- compatible = "xlnx,xps-sysace-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 4 2 >;
- reg = < 0x83600000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,mem-width = <0x10>;
- } ;
- xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
- compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
- reg = < 0xffff0000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- xps_intc_0: interrupt-controller@81800000 {
- #interrupt-cells = <2>;
- compatible = "xlnx,xps-intc-1.00.a";
- interrupt-controller ;
- reg = < 0x81800000 0x10000 >;
- xlnx,num-intr-inputs = <0xc>;
- } ;
- xps_timebase_wdt_1: xps-timebase-wdt@83a00000 {
- compatible = "xlnx,xps-timebase-wdt-1.00.b";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 2 0 1 2 >;
- reg = < 0x83a00000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,wdt-enable-once = <0>;
- xlnx,wdt-interval = <0x1e>;
- } ;
- xps_timer_1: timer@83c00000 {
- compatible = "xlnx,xps-timer-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 3 2 >;
- reg = < 0x83c00000 0x10000 >;
- xlnx,count-width = <0x20>;
- xlnx,family = "virtex5";
- xlnx,gen0-assert = <1>;
- xlnx,gen1-assert = <1>;
- xlnx,one-timer-only = <1>;
- xlnx,trig0-assert = <1>;
- xlnx,trig1-assert = <1>;
- } ;
- } ;
-} ;
diff --git a/arch/powerpc/boot/dts/virtex440-ml510.dts b/arch/powerpc/boot/dts/virtex440-ml510.dts
deleted file mode 100644
index 3b736ca26ddc..000000000000
--- a/arch/powerpc/boot/dts/virtex440-ml510.dts
+++ /dev/null
@@ -1,466 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Xilinx ML510 Reference Design support
- *
- * This DTS file was created for the ml510_bsb1_pcores_ppc440 reference design.
- * The reference design contains a bug which prevent PCI DMA from working
- * properly. A description of the bug is given in the plbv46_pci section. It
- * needs to be fixed by the user until Xilinx updates their reference design.
- *
- * Copyright 2009, Roderick Colenbrander
- */
-
-/dts-v1/;
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,ml510-ref-design", "xlnx,virtex440";
- dcr-parent = <&ppc440_0>;
- DDR2_SDRAM_DIMM0: memory@0 {
- device_type = "memory";
- reg = < 0x0 0x20000000 >;
- } ;
- alias {
- ethernet0 = &Hard_Ethernet_MAC;
- serial0 = &RS232_Uart_1;
- } ;
- chosen {
- bootargs = "console=ttyS0 root=/dev/ram";
- stdout-path = "/plb@0/serial@83e00000";
- } ;
- cpus {
- #address-cells = <1>;
- #cpus = <0x1>;
- #size-cells = <0>;
- ppc440_0: cpu@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- clock-frequency = <300000000>;
- compatible = "PowerPC,440", "ibm,ppc440";
- d-cache-line-size = <0x20>;
- d-cache-size = <0x8000>;
- dcr-access-method = "native";
- dcr-controller ;
- device_type = "cpu";
- i-cache-line-size = <0x20>;
- i-cache-size = <0x8000>;
- model = "PowerPC,440";
- reg = <0>;
- timebase-frequency = <300000000>;
- xlnx,apu-control = <0x2000>;
- xlnx,apu-udi-0 = <0x0>;
- xlnx,apu-udi-1 = <0x0>;
- xlnx,apu-udi-10 = <0x0>;
- xlnx,apu-udi-11 = <0x0>;
- xlnx,apu-udi-12 = <0x0>;
- xlnx,apu-udi-13 = <0x0>;
- xlnx,apu-udi-14 = <0x0>;
- xlnx,apu-udi-15 = <0x0>;
- xlnx,apu-udi-2 = <0x0>;
- xlnx,apu-udi-3 = <0x0>;
- xlnx,apu-udi-4 = <0x0>;
- xlnx,apu-udi-5 = <0x0>;
- xlnx,apu-udi-6 = <0x0>;
- xlnx,apu-udi-7 = <0x0>;
- xlnx,apu-udi-8 = <0x0>;
- xlnx,apu-udi-9 = <0x0>;
- xlnx,dcr-autolock-enable = <0x1>;
- xlnx,dcu-rd-ld-cache-plb-prio = <0x0>;
- xlnx,dcu-rd-noncache-plb-prio = <0x0>;
- xlnx,dcu-rd-touch-plb-prio = <0x0>;
- xlnx,dcu-rd-urgent-plb-prio = <0x0>;
- xlnx,dcu-wr-flush-plb-prio = <0x0>;
- xlnx,dcu-wr-store-plb-prio = <0x0>;
- xlnx,dcu-wr-urgent-plb-prio = <0x0>;
- xlnx,dma0-control = <0x0>;
- xlnx,dma0-plb-prio = <0x0>;
- xlnx,dma0-rxchannelctrl = <0x1010000>;
- xlnx,dma0-rxirqtimer = <0x3ff>;
- xlnx,dma0-txchannelctrl = <0x1010000>;
- xlnx,dma0-txirqtimer = <0x3ff>;
- xlnx,dma1-control = <0x0>;
- xlnx,dma1-plb-prio = <0x0>;
- xlnx,dma1-rxchannelctrl = <0x1010000>;
- xlnx,dma1-rxirqtimer = <0x3ff>;
- xlnx,dma1-txchannelctrl = <0x1010000>;
- xlnx,dma1-txirqtimer = <0x3ff>;
- xlnx,dma2-control = <0x0>;
- xlnx,dma2-plb-prio = <0x0>;
- xlnx,dma2-rxchannelctrl = <0x1010000>;
- xlnx,dma2-rxirqtimer = <0x3ff>;
- xlnx,dma2-txchannelctrl = <0x1010000>;
- xlnx,dma2-txirqtimer = <0x3ff>;
- xlnx,dma3-control = <0x0>;
- xlnx,dma3-plb-prio = <0x0>;
- xlnx,dma3-rxchannelctrl = <0x1010000>;
- xlnx,dma3-rxirqtimer = <0x3ff>;
- xlnx,dma3-txchannelctrl = <0x1010000>;
- xlnx,dma3-txirqtimer = <0x3ff>;
- xlnx,endian-reset = <0x0>;
- xlnx,generate-plb-timespecs = <0x1>;
- xlnx,icu-rd-fetch-plb-prio = <0x0>;
- xlnx,icu-rd-spec-plb-prio = <0x0>;
- xlnx,icu-rd-touch-plb-prio = <0x0>;
- xlnx,interconnect-imask = <0xffffffff>;
- xlnx,mplb-allow-lock-xfer = <0x1>;
- xlnx,mplb-arb-mode = <0x0>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-counter = <0x500>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-max-burst = <0x8>;
- xlnx,mplb-native-dwidth = <0x80>;
- xlnx,mplb-p2p = <0x0>;
- xlnx,mplb-prio-dcur = <0x2>;
- xlnx,mplb-prio-dcuw = <0x3>;
- xlnx,mplb-prio-icu = <0x4>;
- xlnx,mplb-prio-splb0 = <0x1>;
- xlnx,mplb-prio-splb1 = <0x0>;
- xlnx,mplb-read-pipe-enable = <0x1>;
- xlnx,mplb-sync-tattribute = <0x0>;
- xlnx,mplb-wdog-enable = <0x1>;
- xlnx,mplb-write-pipe-enable = <0x1>;
- xlnx,mplb-write-post-enable = <0x1>;
- xlnx,num-dma = <0x0>;
- xlnx,pir = <0xf>;
- xlnx,ppc440mc-addr-base = <0x0>;
- xlnx,ppc440mc-addr-high = <0x1fffffff>;
- xlnx,ppc440mc-arb-mode = <0x0>;
- xlnx,ppc440mc-bank-conflict-mask = <0x1800000>;
- xlnx,ppc440mc-control = <0xf810008f>;
- xlnx,ppc440mc-max-burst = <0x8>;
- xlnx,ppc440mc-prio-dcur = <0x2>;
- xlnx,ppc440mc-prio-dcuw = <0x3>;
- xlnx,ppc440mc-prio-icu = <0x4>;
- xlnx,ppc440mc-prio-splb0 = <0x1>;
- xlnx,ppc440mc-prio-splb1 = <0x0>;
- xlnx,ppc440mc-row-conflict-mask = <0x7ffe00>;
- xlnx,ppcdm-asyncmode = <0x0>;
- xlnx,ppcds-asyncmode = <0x0>;
- xlnx,user-reset = <0x0>;
- } ;
- } ;
- plb_v46_0: plb@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
- ranges ;
- FLASH: flash@fc000000 {
- bank-width = <2>;
- compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
- reg = < 0xfc000000 0x2000000 >;
- xlnx,family = "virtex5";
- xlnx,include-datawidth-matching-0 = <0x1>;
- xlnx,include-datawidth-matching-1 = <0x0>;
- xlnx,include-datawidth-matching-2 = <0x0>;
- xlnx,include-datawidth-matching-3 = <0x0>;
- xlnx,include-negedge-ioregs = <0x0>;
- xlnx,include-plb-ipif = <0x1>;
- xlnx,include-wrbuf = <0x1>;
- xlnx,max-mem-width = <0x10>;
- xlnx,mch-native-dwidth = <0x20>;
- xlnx,mch-plb-clk-period-ps = <0x2710>;
- xlnx,mch-splb-awidth = <0x20>;
- xlnx,mch0-accessbuf-depth = <0x10>;
- xlnx,mch0-protocol = <0x0>;
- xlnx,mch0-rddatabuf-depth = <0x10>;
- xlnx,mch1-accessbuf-depth = <0x10>;
- xlnx,mch1-protocol = <0x0>;
- xlnx,mch1-rddatabuf-depth = <0x10>;
- xlnx,mch2-accessbuf-depth = <0x10>;
- xlnx,mch2-protocol = <0x0>;
- xlnx,mch2-rddatabuf-depth = <0x10>;
- xlnx,mch3-accessbuf-depth = <0x10>;
- xlnx,mch3-protocol = <0x0>;
- xlnx,mch3-rddatabuf-depth = <0x10>;
- xlnx,mem0-width = <0x10>;
- xlnx,mem1-width = <0x20>;
- xlnx,mem2-width = <0x20>;
- xlnx,mem3-width = <0x20>;
- xlnx,num-banks-mem = <0x1>;
- xlnx,num-channels = <0x2>;
- xlnx,priority-mode = <0x0>;
- xlnx,synch-mem-0 = <0x0>;
- xlnx,synch-mem-1 = <0x0>;
- xlnx,synch-mem-2 = <0x0>;
- xlnx,synch-mem-3 = <0x0>;
- xlnx,synch-pipedelay-0 = <0x2>;
- xlnx,synch-pipedelay-1 = <0x2>;
- xlnx,synch-pipedelay-2 = <0x2>;
- xlnx,synch-pipedelay-3 = <0x2>;
- xlnx,tavdv-ps-mem-0 = <0x1adb0>;
- xlnx,tavdv-ps-mem-1 = <0x3a98>;
- xlnx,tavdv-ps-mem-2 = <0x3a98>;
- xlnx,tavdv-ps-mem-3 = <0x3a98>;
- xlnx,tcedv-ps-mem-0 = <0x1adb0>;
- xlnx,tcedv-ps-mem-1 = <0x3a98>;
- xlnx,tcedv-ps-mem-2 = <0x3a98>;
- xlnx,tcedv-ps-mem-3 = <0x3a98>;
- xlnx,thzce-ps-mem-0 = <0x88b8>;
- xlnx,thzce-ps-mem-1 = <0x1b58>;
- xlnx,thzce-ps-mem-2 = <0x1b58>;
- xlnx,thzce-ps-mem-3 = <0x1b58>;
- xlnx,thzoe-ps-mem-0 = <0x1b58>;
- xlnx,thzoe-ps-mem-1 = <0x1b58>;
- xlnx,thzoe-ps-mem-2 = <0x1b58>;
- xlnx,thzoe-ps-mem-3 = <0x1b58>;
- xlnx,tlzwe-ps-mem-0 = <0x88b8>;
- xlnx,tlzwe-ps-mem-1 = <0x0>;
- xlnx,tlzwe-ps-mem-2 = <0x0>;
- xlnx,tlzwe-ps-mem-3 = <0x0>;
- xlnx,twc-ps-mem-0 = <0x1adb0>;
- xlnx,twc-ps-mem-1 = <0x3a98>;
- xlnx,twc-ps-mem-2 = <0x3a98>;
- xlnx,twc-ps-mem-3 = <0x3a98>;
- xlnx,twp-ps-mem-0 = <0x11170>;
- xlnx,twp-ps-mem-1 = <0x2ee0>;
- xlnx,twp-ps-mem-2 = <0x2ee0>;
- xlnx,twp-ps-mem-3 = <0x2ee0>;
- xlnx,xcl0-linesize = <0x4>;
- xlnx,xcl0-writexfer = <0x1>;
- xlnx,xcl1-linesize = <0x4>;
- xlnx,xcl1-writexfer = <0x1>;
- xlnx,xcl2-linesize = <0x4>;
- xlnx,xcl2-writexfer = <0x1>;
- xlnx,xcl3-linesize = <0x4>;
- xlnx,xcl3-writexfer = <0x1>;
- } ;
- Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "xlnx,compound";
- ethernet@81c00000 {
- compatible = "xlnx,xps-ll-temac-1.01.b";
- device_type = "network";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 8 2 >;
- llink-connected = <&Hard_Ethernet_MAC_fifo>;
- local-mac-address = [ 02 00 00 00 00 00 ];
- reg = < 0x81c00000 0x40 >;
- xlnx,bus2core-clk-ratio = <0x1>;
- xlnx,phy-type = <0x3>;
- xlnx,phyaddr = <0x1>;
- xlnx,rxcsum = <0x0>;
- xlnx,rxfifo = <0x8000>;
- xlnx,temac-type = <0x0>;
- xlnx,txcsum = <0x0>;
- xlnx,txfifo = <0x8000>;
- } ;
- } ;
- Hard_Ethernet_MAC_fifo: xps-ll-fifo@81a00000 {
- compatible = "xlnx,xps-ll-fifo-1.01.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 6 2 >;
- reg = < 0x81a00000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- IIC_EEPROM: i2c@81600000 {
- compatible = "xlnx,xps-iic-2.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 9 2 >;
- reg = < 0x81600000 0x10000 >;
- xlnx,clk-freq = <0x5f5e100>;
- xlnx,family = "virtex5";
- xlnx,gpo-width = <0x1>;
- xlnx,iic-freq = <0x186a0>;
- xlnx,scl-inertial-delay = <0x5>;
- xlnx,sda-inertial-delay = <0x5>;
- xlnx,ten-bit-adr = <0x0>;
- } ;
- LCD_OPTIONAL: gpio@81420000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81420000 0x10000 >;
- xlnx,all-inputs = <0x0>;
- xlnx,all-inputs-2 = <0x0>;
- xlnx,dout-default = <0x0>;
- xlnx,dout-default-2 = <0x0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <0xb>;
- xlnx,interrupt-present = <0x0>;
- xlnx,is-bidir = <0x1>;
- xlnx,is-bidir-2 = <0x1>;
- xlnx,is-dual = <0x0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- LEDs_4Bit: gpio@81400000 {
- compatible = "xlnx,xps-gpio-1.00.a";
- reg = < 0x81400000 0x10000 >;
- xlnx,all-inputs = <0x0>;
- xlnx,all-inputs-2 = <0x0>;
- xlnx,dout-default = <0x0>;
- xlnx,dout-default-2 = <0x0>;
- xlnx,family = "virtex5";
- xlnx,gpio-width = <0x4>;
- xlnx,interrupt-present = <0x0>;
- xlnx,is-bidir = <0x1>;
- xlnx,is-bidir-2 = <0x1>;
- xlnx,is-dual = <0x0>;
- xlnx,tri-default = <0xffffffff>;
- xlnx,tri-default-2 = <0xffffffff>;
- } ;
- RS232_Uart_1: serial@83e00000 {
- clock-frequency = <100000000>;
- compatible = "xlnx,xps-uart16550-2.00.b", "ns16550";
- current-speed = <9600>;
- device_type = "serial";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 11 2 >;
- reg = < 0x83e00000 0x10000 >;
- reg-offset = <0x1003>;
- reg-shift = <2>;
- xlnx,family = "virtex5";
- xlnx,has-external-rclk = <0x0>;
- xlnx,has-external-xin = <0x0>;
- xlnx,is-a-16550 = <0x1>;
- } ;
- SPI_EEPROM: xps-spi@feff8000 {
- compatible = "xlnx,xps-spi-2.00.b";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 10 2 >;
- reg = < 0xfeff8000 0x80 >;
- xlnx,family = "virtex5";
- xlnx,fifo-exist = <0x1>;
- xlnx,num-ss-bits = <0x1>;
- xlnx,num-transfer-bits = <0x8>;
- xlnx,sck-ratio = <0x80>;
- } ;
- SysACE_CompactFlash: sysace@83600000 {
- compatible = "xlnx,xps-sysace-1.00.a";
- interrupt-parent = <&xps_intc_0>;
- interrupts = < 7 2 >;
- reg = < 0x83600000 0x10000 >;
- xlnx,family = "virtex5";
- xlnx,mem-width = <0x10>;
- } ;
- plbv46_pci_0: plbv46-pci@85e00000 {
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "xlnx,plbv46-pci-1.03.a";
- device_type = "pci";
- reg = < 0x85e00000 0x10000 >;
-
- /*
- * The default ML510 BSB has C_IPIFBAR2PCIBAR_0 set to
- * 0 which means that a read/write to the memory mapped
- * i/o region (which starts at 0xa0000000) for pci
- * bar 0 on the plb side translates to 0.
- * It is important to set this value to 0xa0000000, so
- * that inbound and outbound pci transactions work
- * properly including DMA.
- */
- ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
- 0x01000000 0 0x00000000 0xf0000000 0 0x00010000>;
-
- #interrupt-cells = <1>;
- interrupt-parent = <&xps_intc_0>;
- interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
- interrupt-map = <
- /* IRQ mapping for pci slots and ALI M1533
- * periperhals. In total there are 5 interrupt
- * lines connected to a xps_intc controller.
- * Four of them are PCI IRQ A, B, C, D and
- * which correspond to respectively xpx_intc
- * 5, 4, 3 and 2. The fifth interrupt line is
- * connected to the south bridge and this one
- * uses irq 1 and is active high instead of
- * active low.
- *
- * The M1533 contains various peripherals
- * including AC97 audio, a modem, USB, IDE and
- * some power management stuff. The modem
- * isn't connected on the ML510 and the power
- * management core also isn't used.
- */
-
- /* IDSEL 0x16 / dev=6, bus=0 / PCI slot 3 */
- 0x3000 0 0 1 &xps_intc_0 3 2
- 0x3000 0 0 2 &xps_intc_0 2 2
- 0x3000 0 0 3 &xps_intc_0 5 2
- 0x3000 0 0 4 &xps_intc_0 4 2
-
- /* IDSEL 0x13 / dev=3, bus=1 / PCI slot 4 */
- /*
- 0x11800 0 0 1 &xps_intc_0 5 0 2
- 0x11800 0 0 2 &xps_intc_0 4 0 2
- 0x11800 0 0 3 &xps_intc_0 3 0 2
- 0x11800 0 0 4 &xps_intc_0 2 0 2
- */
-
- /* According to the datasheet + schematic
- * ABCD [FPGA] of slot 5 is mapped to DABC.
- * Testing showed that at least A maps to B,
- * the mapping of the other pins is a guess
- * and for that reason the lines have been
- * commented out.
- */
- /* IDSEL 0x15 / dev=5, bus=0 / PCI slot 5 */
- 0x2800 0 0 1 &xps_intc_0 4 2
- /*
- 0x2800 0 0 2 &xps_intc_0 3 2
- 0x2800 0 0 3 &xps_intc_0 2 2
- 0x2800 0 0 4 &xps_intc_0 5 2
- */
-
- /* IDSEL 0x12 / dev=2, bus=1 / PCI slot 6 */
- /*
- 0x11000 0 0 1 &xps_intc_0 4 0 2
- 0x11000 0 0 2 &xps_intc_0 3 0 2
- 0x11000 0 0 3 &xps_intc_0 2 0 2
- 0x11000 0 0 4 &xps_intc_0 5 0 2
- */
-
- /* IDSEL 0x11 / dev=1, bus=0 / AC97 audio */
- 0x0800 0 0 1 &i8259 7 2
-
- /* IDSEL 0x1b / dev\x11, bus=0 / IDE */
- 0x5800 0 0 1 &i8259 14 2
-
- /* IDSEL 0x1f / dev 15, bus=0 / 2x USB 1.1 */
- 0x7800 0 0 1 &i8259 7 2
- >;
- ali_m1533 {
- #size-cells = <1>;
- #address-cells = <2>;
- i8259: interrupt-controller@20 {
- reg = <1 0x20 2
- 1 0xa0 2
- 1 0x4d0 2>;
- interrupt-controller;
- device_type = "interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- compatible = "chrp,iic";
-
- /* south bridge irq is active high */
- interrupts = <1 3>;
- interrupt-parent = <&xps_intc_0>;
- };
- };
- } ;
- xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffff0000 {
- compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
- reg = < 0xffff0000 0x10000 >;
- xlnx,family = "virtex5";
- } ;
- xps_intc_0: interrupt-controller@81800000 {
- #interrupt-cells = <0x2>;
- compatible = "xlnx,xps-intc-1.00.a";
- interrupt-controller ;
- reg = < 0x81800000 0x10000 >;
- xlnx,num-intr-inputs = <0xc>;
- } ;
- xps_tft_0: tft@86e00000 {
- compatible = "xlnx,xps-tft-1.00.a";
- reg = < 0x86e00000 0x10000 >;
- xlnx,dcr-splb-slave-if = <0x1>;
- xlnx,default-tft-base-addr = <0x0>;
- xlnx,family = "virtex5";
- xlnx,i2c-slave-addr = <0x76>;
- xlnx,mplb-awidth = <0x20>;
- xlnx,mplb-dwidth = <0x80>;
- xlnx,mplb-native-dwidth = <0x40>;
- xlnx,mplb-smallest-slave = <0x20>;
- xlnx,tft-interface = <0x1>;
- } ;
- } ;
-} ;
diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h
index e0606766480f..6455fc9a244f 100644
--- a/arch/powerpc/boot/ops.h
+++ b/arch/powerpc/boot/ops.h
@@ -88,7 +88,6 @@ int serial_console_init(void);
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
int cpm_console_init(void *devp, struct serial_console_data *scdp);
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp);
-int uartlite_console_init(void *devp, struct serial_console_data *scdp);
int opal_console_init(void *devp, struct serial_console_data *scdp);
void *simple_alloc_init(char *base, unsigned long heap_size,
unsigned long granularity, unsigned long max_allocs);
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index 9457863147f9..0bfa7e87e546 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -132,11 +132,6 @@ int serial_console_init(void)
else if (dt_is_compatible(devp, "fsl,mpc5200-psc-uart"))
rc = mpc5200_psc_console_init(devp, &serial_cd);
#endif
-#ifdef CONFIG_XILINX_VIRTEX
- else if (dt_is_compatible(devp, "xlnx,opb-uartlite-1.00.b") ||
- dt_is_compatible(devp, "xlnx,xps-uartlite-1.00.a"))
- rc = uartlite_console_init(devp, &serial_cd);
-#endif
#ifdef CONFIG_PPC64_BOOT_WRAPPER
else if (dt_is_compatible(devp, "ibm,opal-console-raw"))
rc = opal_console_init(devp, &serial_cd);
diff --git a/arch/powerpc/boot/uartlite.c b/arch/powerpc/boot/uartlite.c
deleted file mode 100644
index 46bed69b4169..000000000000
--- a/arch/powerpc/boot/uartlite.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Xilinx UARTLITE bootloader driver
- *
- * Copyright (C) 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include "types.h"
-#include "string.h"
-#include "stdio.h"
-#include "io.h"
-#include "ops.h"
-
-#define ULITE_RX 0x00
-#define ULITE_TX 0x04
-#define ULITE_STATUS 0x08
-#define ULITE_CONTROL 0x0c
-
-#define ULITE_STATUS_RXVALID 0x01
-#define ULITE_STATUS_TXFULL 0x08
-
-#define ULITE_CONTROL_RST_RX 0x02
-
-static void * reg_base;
-
-static int uartlite_open(void)
-{
- /* Clear the RX FIFO */
- out_be32(reg_base + ULITE_CONTROL, ULITE_CONTROL_RST_RX);
- return 0;
-}
-
-static void uartlite_putc(unsigned char c)
-{
- u32 reg = ULITE_STATUS_TXFULL;
- while (reg & ULITE_STATUS_TXFULL) /* spin on TXFULL bit */
- reg = in_be32(reg_base + ULITE_STATUS);
- out_be32(reg_base + ULITE_TX, c);
-}
-
-static unsigned char uartlite_getc(void)
-{
- u32 reg = 0;
- while (!(reg & ULITE_STATUS_RXVALID)) /* spin waiting for RXVALID bit */
- reg = in_be32(reg_base + ULITE_STATUS);
- return in_be32(reg_base + ULITE_RX);
-}
-
-static u8 uartlite_tstc(void)
-{
- u32 reg = in_be32(reg_base + ULITE_STATUS);
- return reg & ULITE_STATUS_RXVALID;
-}
-
-int uartlite_console_init(void *devp, struct serial_console_data *scdp)
-{
- int n;
- unsigned long reg_phys;
-
- n = getprop(devp, "virtual-reg", ®_base, sizeof(reg_base));
- if (n != sizeof(reg_base)) {
- if (!dt_xlate_reg(devp, 0, ®_phys, NULL))
- return -1;
-
- reg_base = (void *)reg_phys;
- }
-
- scdp->open = uartlite_open;
- scdp->putc = uartlite_putc;
- scdp->getc = uartlite_getc;
- scdp->tstc = uartlite_tstc;
- scdp->close = NULL;
- return 0;
-}
diff --git a/arch/powerpc/boot/virtex.c b/arch/powerpc/boot/virtex.c
deleted file mode 100644
index f731cbb4bff0..000000000000
--- a/arch/powerpc/boot/virtex.c
+++ /dev/null
@@ -1,97 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * The platform specific code for virtex devices since a boot loader is not
- * always used.
- *
- * (C) Copyright 2008 Xilinx, Inc.
- */
-
-#include "ops.h"
-#include "io.h"
-#include "stdio.h"
-
-#define UART_DLL 0 /* Out: Divisor Latch Low */
-#define UART_DLM 1 /* Out: Divisor Latch High */
-#define UART_FCR 2 /* Out: FIFO Control Register */
-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define UART_LCR 3 /* Out: Line Control Register */
-#define UART_MCR 4 /* Out: Modem Control Register */
-#define UART_MCR_RTS 0x02 /* RTS complement */
-#define UART_MCR_DTR 0x01 /* DTR complement */
-#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-
-static int virtex_ns16550_console_init(void *devp)
-{
- unsigned char *reg_base;
- u32 reg_shift, reg_offset, clk, spd;
- u16 divisor;
- int n;
-
- if (dt_get_virtual_reg(devp, (void **)®_base, 1) < 1)
- return -1;
-
- n = getprop(devp, "reg-offset", ®_offset, sizeof(reg_offset));
- if (n = sizeof(reg_offset))
- reg_base += reg_offset;
-
- n = getprop(devp, "reg-shift", ®_shift, sizeof(reg_shift));
- if (n != sizeof(reg_shift))
- reg_shift = 0;
-
- n = getprop(devp, "current-speed", (void *)&spd, sizeof(spd));
- if (n != sizeof(spd))
- spd = 9600;
-
- /* should there be a default clock rate?*/
- n = getprop(devp, "clock-frequency", (void *)&clk, sizeof(clk));
- if (n != sizeof(clk))
- return -1;
-
- divisor = clk / (16 * spd);
-
- /* Access baud rate */
- out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_DLAB);
-
- /* Baud rate based on input clock */
- out_8(reg_base + (UART_DLL << reg_shift), divisor & 0xFF);
- out_8(reg_base + (UART_DLM << reg_shift), divisor >> 8);
-
- /* 8 data, 1 stop, no parity */
- out_8(reg_base + (UART_LCR << reg_shift), UART_LCR_WLEN8);
-
- /* RTS/DTR */
- out_8(reg_base + (UART_MCR << reg_shift), UART_MCR_RTS | UART_MCR_DTR);
-
- /* Clear transmitter and receiver */
- out_8(reg_base + (UART_FCR << reg_shift),
- UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
- return 0;
-}
-
-/* For virtex, the kernel may be loaded without using a bootloader and if so
- some UARTs need more setup than is provided in the normal console init
-*/
-int platform_specific_init(void)
-{
- void *devp;
- char devtype[MAX_PROP_LEN];
- char path[MAX_PATH_LEN];
-
- devp = finddevice("/chosen");
- if (devp = NULL)
- return -1;
-
- if (getprop(devp, "linux,stdout-path", path, MAX_PATH_LEN) > 0) {
- devp = finddevice(path);
- if (devp = NULL)
- return -1;
-
- if ((getprop(devp, "device_type", devtype, sizeof(devtype)) > 0)
- && !strcmp(devtype, "serial")
- && (dt_is_compatible(devp, "ns16550")))
- virtex_ns16550_console_init(devp);
- }
- return 0;
-}
diff --git a/arch/powerpc/boot/virtex405-head.S b/arch/powerpc/boot/virtex405-head.S
deleted file mode 100644
index 00bab7d7c48c..000000000000
--- a/arch/powerpc/boot/virtex405-head.S
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#include "ppc_asm.h"
-
- .text
- .global _zimage_start
-_zimage_start:
-
- /* PPC errata 213: needed by Virtex-4 FX */
- mfccr0 0
- oris 0,0,0x50000000@h
- mtccr0 0
-
- /*
- * Invalidate the data cache if the data cache is turned off.
- * - The 405 core does not invalidate the data cache on power-up
- * or reset but does turn off the data cache. We cannot assume
- * that the cache contents are valid.
- * - If the data cache is turned on this must have been done by
- * a bootloader and we assume that the cache contents are
- * valid.
- */
- mfdccr r9
- cmplwi r9,0
- bne 2f
- lis r9,0
- li r8,256
- mtctr r8
-1: dccci r0,r9
- addi r9,r9,0x20
- bdnz 1b
-2: b _zimage_start_lib
diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper
index ed6266367bc0..de5fd5a047e8 100755
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -323,14 +323,6 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
-simpleboot-virtex405-*)
- platformo="$object/virtex405-head.o $object/simpleboot.o $object/virtex.o"
- binary=y
- ;;
-simpleboot-virtex440-*)
- platformo="$object/fixed-head.o $object/simpleboot.o $object/virtex.o"
- binary=y
- ;;
simpleboot-*)
platformo="$object/fixed-head.o $object/simpleboot.o"
binary=y
diff --git a/arch/powerpc/configs/40x/virtex_defconfig b/arch/powerpc/configs/40x/virtex_defconfig
deleted file mode 100644
index 5e7c61d1d7d0..000000000000
--- a/arch/powerpc/configs/40x/virtex_defconfig
+++ /dev/null
@@ -1,75 +0,0 @@
-CONFIG_40x=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT\x14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_WALNUT is not set
-CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
-CONFIG_PREEMPT=y
-CONFIG_MATH_EMULATION=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE=""
-CONFIG_PCI=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE92
-CONFIG_XILINX_SYSACE=y
-CONFIG_NETDEVICES=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
-CONFIG_XILINX_HWICAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_XILINX=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRC_CCITT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/powerpc/configs/44x/virtex5_defconfig b/arch/powerpc/configs/44x/virtex5_defconfig
deleted file mode 100644
index 1f74079e1703..000000000000
--- a/arch/powerpc/configs/44x/virtex5_defconfig
+++ /dev/null
@@ -1,74 +0,0 @@
-CONFIG_44x=y
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT\x14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_EBONY is not set
-CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y
-CONFIG_PREEMPT=y
-CONFIG_MATH_EMULATION=y
-CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE=""
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_NETFILTER=y
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE92
-CONFIG_XILINX_SYSACE=y
-CONFIG_NETDEVICES=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
-CONFIG_XILINX_HWICAP=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_XILINX=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_FB_XILINX=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_UTF8=m
-CONFIG_CRC_CCITT=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_KERNEL=y
diff --git a/arch/powerpc/configs/ppc40x_defconfig b/arch/powerpc/configs/ppc40x_defconfig
index a5f683aed328..88960a72b525 100644
--- a/arch/powerpc/configs/ppc40x_defconfig
+++ b/arch/powerpc/configs/ppc40x_defconfig
@@ -14,7 +14,6 @@ CONFIG_EP405=y
CONFIG_HOTFOOT=y
CONFIG_KILAUEA=y
CONFIG_MAKALU=y
-CONFIG_XILINX_VIRTEX_GENERIC_BOARD=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
@@ -37,33 +36,26 @@ CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE5000
-CONFIG_XILINX_SYSACE=m
CONFIG_NETDEVICES=y
CONFIG_IBM_EMAC=y
# CONFIG_INPUT is not set
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=m
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
# CONFIG_HW_RANDOM is not set
-CONFIG_XILINX_HWICAP=m
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_IBM_IIC=m
-CONFIG_GPIO_XILINX=y
# CONFIG_HWMON is not set
CONFIG_THERMAL=y
CONFIG_FB=m
-CONFIG_FB_XILINX=m
CONFIG_EXT2_FS=y
CONFIG_EXT4_FS=m
CONFIG_VFAT_FS=m
diff --git a/arch/powerpc/configs/ppc44x_defconfig b/arch/powerpc/configs/ppc44x_defconfig
index a41eedfe0a5f..8b595f67068c 100644
--- a/arch/powerpc/configs/ppc44x_defconfig
+++ b/arch/powerpc/configs/ppc44x_defconfig
@@ -22,7 +22,6 @@ CONFIG_GLACIER=y
CONFIG_REDWOOD=y
CONFIG_EIGER=y
CONFIG_YOSEMITE=y
-CONFIG_XILINX_VIRTEX440_GENERIC_BOARD=y
CONFIG_PPC4xx_GPIO=y
CONFIG_MATH_EMULATION=y
CONFIG_NET=y
@@ -46,7 +45,6 @@ CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_GLUEBI=m
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE5000
-CONFIG_XILINX_SYSACE=m
CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m
# CONFIG_SCSI_LOWLEVEL is not set
@@ -57,7 +55,6 @@ CONFIG_IBM_EMAC=y
CONFIG_SERIO=m
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_XILINX_XPS_PS2=m
# CONFIG_VT is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
@@ -65,18 +62,13 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_UARTLITE=y
-CONFIG_SERIAL_UARTLITE_CONSOLE=y
# CONFIG_HW_RANDOM is not set
-CONFIG_XILINX_HWICAP=m
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
CONFIG_I2C_IBM_IIC=m
-CONFIG_GPIO_XILINX=y
# CONFIG_HWMON is not set
CONFIG_FB=m
-CONFIG_FB_XILINX=m
CONFIG_USB=m
CONFIG_USB_EHCI_HCD=m
CONFIG_USB_OHCI_HCD=m
diff --git a/arch/powerpc/include/asm/xilinx_intc.h b/arch/powerpc/include/asm/xilinx_intc.h
deleted file mode 100644
index ca9aa162fb09..000000000000
--- a/arch/powerpc/include/asm/xilinx_intc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Xilinx intc external definitions
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- */
-#ifndef _ASM_POWERPC_XILINX_INTC_H
-#define _ASM_POWERPC_XILINX_INTC_H
-
-#ifdef __KERNEL__
-
-extern void __init xilinx_intc_init_tree(void);
-extern unsigned int xintc_get_irq(void);
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_POWERPC_XILINX_INTC_H */
diff --git a/arch/powerpc/include/asm/xilinx_pci.h b/arch/powerpc/include/asm/xilinx_pci.h
deleted file mode 100644
index 7a8275caf6af..000000000000
--- a/arch/powerpc/include/asm/xilinx_pci.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Xilinx pci external definitions
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef INCLUDE_XILINX_PCI
-#define INCLUDE_XILINX_PCI
-
-#ifdef CONFIG_XILINX_PCI
-extern void __init xilinx_pci_init(void);
-#else
-static inline void __init xilinx_pci_init(void) { return; }
-#endif
-
-#endif /* INCLUDE_XILINX_PCI */
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 245be4fafe13..2dff9041bcdc 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1385,32 +1385,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_4xx,
.platform = "ppc405",
},
- { /* Xilinx Virtex-II Pro */
- .pvr_mask = 0xfffff000,
- .pvr_value = 0x20010000,
- .cpu_name = "Virtex-II Pro",
- .cpu_features = CPU_FTRS_40X,
- .cpu_user_features = PPC_FEATURE_32 |
- PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
- .mmu_features = MMU_FTR_TYPE_40x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .machine_check = machine_check_4xx,
- .platform = "ppc405",
- },
- { /* Xilinx Virtex-4 FX */
- .pvr_mask = 0xfffff000,
- .pvr_value = 0x20011000,
- .cpu_name = "Virtex-4 FX",
- .cpu_features = CPU_FTRS_40X,
- .cpu_user_features = PPC_FEATURE_32 |
- PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
- .mmu_features = MMU_FTR_TYPE_40x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .machine_check = machine_check_4xx,
- .platform = "ppc405",
- },
{ /* 405EP */
.pvr_mask = 0xffff0000,
.pvr_value = 0x51210000,
@@ -1800,19 +1774,6 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_440A,
.platform = "ppc440",
},
- { /* 440 in Xilinx Virtex-5 FXT */
- .pvr_mask = 0xfffffff0,
- .pvr_value = 0x7ff21910,
- .cpu_name = "440 in Virtex-5 FXT",
- .cpu_features = CPU_FTRS_44X,
- .cpu_user_features = COMMON_USER_BOOKE,
- .mmu_features = MMU_FTR_TYPE_44x,
- .icache_bsize = 32,
- .dcache_bsize = 32,
- .cpu_setup = __setup_cpu_440x5,
- .machine_check = machine_check_440A,
- .platform = "ppc440",
- },
{ /* 460EX */
.pvr_mask = 0xffff0006,
.pvr_value = 0x13020002,
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index 6da813b65b42..d06ca51e8443 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -55,23 +55,6 @@ config WALNUT
help
This option enables support for the IBM PPC405GP evaluation board.
-config XILINX_VIRTEX_GENERIC_BOARD
- bool "Generic Xilinx Virtex board"
- depends on 40x
- select XILINX_VIRTEX_II_PRO
- select XILINX_VIRTEX_4_FX
- select XILINX_INTC
- help
- This option enables generic support for Xilinx Virtex based boards.
-
- The generic virtex board support matches any device tree which
- specifies 'xilinx,virtex' in its compatible field. This includes
- the Xilinx ML3xx and ML4xx reference designs using the powerpc
- core.
-
- Most Virtex designs should use this unless it needs to do some
- special configuration at board probe time.
-
config OBS600
bool "OpenBlockS 600"
depends on 40x
@@ -109,20 +92,6 @@ config 405EZ
select IBM_EMAC_MAL_CLR_ICINTSTAT if IBM_EMAC
select IBM_EMAC_MAL_COMMON_ERR if IBM_EMAC
-config XILINX_VIRTEX
- bool
- select DEFAULT_UIMAGE
-
-config XILINX_VIRTEX_II_PRO
- bool
- select XILINX_VIRTEX
- select IBM405_ERR77
- select IBM405_ERR51
-
-config XILINX_VIRTEX_4_FX
- bool
- select XILINX_VIRTEX
-
config STB03xxx
bool
select IBM405_ERR77
diff --git a/arch/powerpc/platforms/40x/Makefile b/arch/powerpc/platforms/40x/Makefile
index 828d78340dd9..e9386deed505 100644
--- a/arch/powerpc/platforms/40x/Makefile
+++ b/arch/powerpc/platforms/40x/Makefile
@@ -1,5 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_WALNUT) += walnut.o
-obj-$(CONFIG_XILINX_VIRTEX_GENERIC_BOARD) += virtex.o
obj-$(CONFIG_EP405) += ep405.o
obj-$(CONFIG_PPC40x_SIMPLE) += ppc40x_simple.o
diff --git a/arch/powerpc/platforms/40x/virtex.c b/arch/powerpc/platforms/40x/virtex.c
deleted file mode 100644
index e3d5e095846b..000000000000
--- a/arch/powerpc/platforms/40x/virtex.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Xilinx Virtex (IIpro & 4FX) based board support
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <asm/xilinx_intc.h>
-#include <asm/xilinx_pci.h>
-#include <asm/ppc4xx.h>
-
-static const struct of_device_id xilinx_of_bus_ids[] __initconst = {
- { .compatible = "xlnx,plb-v46-1.00.a", },
- { .compatible = "xlnx,plb-v34-1.01.a", },
- { .compatible = "xlnx,plb-v34-1.02.a", },
- { .compatible = "xlnx,opb-v20-1.10.c", },
- { .compatible = "xlnx,dcr-v29-1.00.a", },
- { .compatible = "xlnx,compound", },
- {}
-};
-
-static int __init virtex_device_probe(void)
-{
- of_platform_bus_probe(NULL, xilinx_of_bus_ids, NULL);
-
- return 0;
-}
-machine_device_initcall(virtex, virtex_device_probe);
-
-static int __init virtex_probe(void)
-{
- if (!of_machine_is_compatible("xlnx,virtex"))
- return 0;
-
- return 1;
-}
-
-define_machine(virtex) {
- .name = "Xilinx Virtex",
- .probe = virtex_probe,
- .setup_arch = xilinx_pci_init,
- .init_IRQ = xilinx_intc_init_tree,
- .get_irq = xintc_get_irq,
- .restart = ppc4xx_reset_system,
- .calibrate_decr = generic_calibrate_decr,
-};
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 25ebe634a661..39e93d23fb38 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -232,33 +232,6 @@ config ICON
help
This option enables support for the AMCC PPC440SPe evaluation board.
-config XILINX_VIRTEX440_GENERIC_BOARD
- bool "Generic Xilinx Virtex 5 FXT board support"
- depends on 44x
- select XILINX_VIRTEX_5_FXT
- select XILINX_INTC
- help
- This option enables generic support for Xilinx Virtex based boards
- that use a 440 based processor in the Virtex 5 FXT FPGA architecture.
-
- The generic virtex board support matches any device tree which
- specifies 'xlnx,virtex440' in its compatible field. This includes
- the Xilinx ML5xx reference designs using the powerpc core.
-
- Most Virtex 5 designs should use this unless it needs to do some
- special configuration at board probe time.
-
-config XILINX_ML510
- bool "Xilinx ML510 extra support"
- depends on XILINX_VIRTEX440_GENERIC_BOARD
- select HAVE_PCI
- select XILINX_PCI if PCI
- select PPC_INDIRECT_PCI if PCI
- select PPC_I8259 if PCI
- help
- This option enables extra support for features on the Xilinx ML510
- board. The ML510 has a PCI bus with ALI south bridge.
-
config PPC44x_SIMPLE
bool "Simple PowerPC 44x board support"
depends on 44x
@@ -354,13 +327,3 @@ config 476FPE_ERR46
config IBM440EP_ERR42
bool
-# Xilinx specific config options.
-config XILINX_VIRTEX
- bool
- select DEFAULT_UIMAGE
-
-# Xilinx Virtex 5 FXT FPGA architecture, selected by a Xilinx board above
-config XILINX_VIRTEX_5_FXT
- bool
- select XILINX_VIRTEX
-
diff --git a/arch/powerpc/platforms/44x/Makefile b/arch/powerpc/platforms/44x/Makefile
index 1b78c6af821a..5ba031f57652 100644
--- a/arch/powerpc/platforms/44x/Makefile
+++ b/arch/powerpc/platforms/44x/Makefile
@@ -7,8 +7,6 @@ obj-$(CONFIG_PPC44x_SIMPLE) += ppc44x_simple.o
obj-$(CONFIG_EBONY) += ebony.o
obj-$(CONFIG_SAM440EP) += sam440ep.o
obj-$(CONFIG_WARP) += warp.o
-obj-$(CONFIG_XILINX_VIRTEX_5_FXT) += virtex.o
-obj-$(CONFIG_XILINX_ML510) += virtex_ml510.o
obj-$(CONFIG_ISS4xx) += iss4xx.o
obj-$(CONFIG_CANYONLANDS)+= canyonlands.o
obj-$(CONFIG_CURRITUCK) += ppc476.o
diff --git a/arch/powerpc/platforms/44x/virtex.c b/arch/powerpc/platforms/44x/virtex.c
deleted file mode 100644
index 3eb13ed926ee..000000000000
--- a/arch/powerpc/platforms/44x/virtex.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Xilinx Virtex 5FXT based board support, derived from
- * the Xilinx Virtex (IIpro & 4FX) based board support
- *
- * Copyright 2007 Secret Lab Technologies Ltd.
- * Copyright 2008 Xilinx, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/of_platform.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <asm/xilinx_intc.h>
-#include <asm/xilinx_pci.h>
-#include <asm/reg.h>
-#include <asm/ppc4xx.h>
-#include "44x.h"
-
-static const struct of_device_id xilinx_of_bus_ids[] __initconst = {
- { .compatible = "simple-bus", },
- { .compatible = "xlnx,plb-v46-1.00.a", },
- { .compatible = "xlnx,plb-v46-1.02.a", },
- { .compatible = "xlnx,plb-v34-1.01.a", },
- { .compatible = "xlnx,plb-v34-1.02.a", },
- { .compatible = "xlnx,opb-v20-1.10.c", },
- { .compatible = "xlnx,dcr-v29-1.00.a", },
- { .compatible = "xlnx,compound", },
- {}
-};
-
-static int __init virtex_device_probe(void)
-{
- of_platform_bus_probe(NULL, xilinx_of_bus_ids, NULL);
-
- return 0;
-}
-machine_device_initcall(virtex, virtex_device_probe);
-
-static int __init virtex_probe(void)
-{
- if (!of_machine_is_compatible("xlnx,virtex440"))
- return 0;
-
- return 1;
-}
-
-define_machine(virtex) {
- .name = "Xilinx Virtex440",
- .probe = virtex_probe,
- .setup_arch = xilinx_pci_init,
- .init_IRQ = xilinx_intc_init_tree,
- .get_irq = xintc_get_irq,
- .calibrate_decr = generic_calibrate_decr,
- .restart = ppc4xx_reset_system,
-};
diff --git a/arch/powerpc/platforms/44x/virtex_ml510.c b/arch/powerpc/platforms/44x/virtex_ml510.c
deleted file mode 100644
index 349f218b335c..000000000000
--- a/arch/powerpc/platforms/44x/virtex_ml510.c
+++ /dev/null
@@ -1,30 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <asm/i8259.h>
-#include <linux/pci.h>
-#include "44x.h"
-
-/**
- * ml510_ail_quirk
- */
-static void ml510_ali_quirk(struct pci_dev *dev)
-{
- /* Enable the IDE controller */
- pci_write_config_byte(dev, 0x58, 0x4c);
- /* Assign irq 14 to the primary ide channel */
- pci_write_config_byte(dev, 0x44, 0x0d);
- /* Assign irq 15 to the secondary ide channel */
- pci_write_config_byte(dev, 0x75, 0x0f);
- /* Set the ide controller in native mode */
- pci_write_config_byte(dev, 0x09, 0xff);
-
- /* INTB = disabled, INTA = disabled */
- pci_write_config_byte(dev, 0x48, 0x00);
- /* INTD = disabled, INTC = disabled */
- pci_write_config_byte(dev, 0x4a, 0x00);
- /* Audio = INT7, Modem = disabled. */
- pci_write_config_byte(dev, 0x4b, 0x60);
- /* USB = INT7 */
- pci_write_config_byte(dev, 0x74, 0x06);
-}
-DECLARE_PCI_FIXUP_EARLY(0x10b9, 0x1533, ml510_ali_quirk);
-
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 1f8025383caa..5e6479d409a0 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -317,8 +317,4 @@ config MCU_MPC8349EMITX
also register MCU GPIOs with the generic GPIO API, so you'll able
to use MCU pins as GPIOs.
-config XILINX_PCI
- bool "Xilinx PCI host bridge support"
- depends on PCI && XILINX_VIRTEX
-
endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cb5a5bd2cef5..026b3f01a991 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -31,8 +31,6 @@ obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_IPIC) += ipic.o
-obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
-obj-$(CONFIG_XILINX_PCI) += xilinx_pci.o
obj-$(CONFIG_OF_RTC) += of_rtc.o
obj-$(CONFIG_CPM) += cpm_common.o
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
deleted file mode 100644
index 4a86dcff3fcd..000000000000
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Interrupt controller driver for Xilinx Virtex FPGAs
- *
- * Copyright (C) 2007 Secret Lab Technologies Ltd.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- *
- */
-
-/*
- * This is a driver for the interrupt controller typically found in
- * Xilinx Virtex FPGA designs.
- *
- * The interrupt sense levels are hard coded into the FPGA design with
- * typically a 1:1 relationship between irq lines and devices (no shared
- * irq lines). Therefore, this driver does not attempt to handle edge
- * and level interrupts differently.
- */
-#undef DEBUG
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/i8259.h>
-#include <asm/irq.h>
-#include <linux/irqchip.h>
-
-#if defined(CONFIG_PPC_I8259)
-/*
- * Support code for cascading to 8259 interrupt controllers
- */
-static void xilinx_i8259_cascade(struct irq_desc *desc)
-{
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned int cascade_irq = i8259_irq();
-
- if (cascade_irq)
- generic_handle_irq(cascade_irq);
-
- /* Let xilinx_intc end the interrupt */
- chip->irq_unmask(&desc->irq_data);
-}
-
-static void __init xilinx_i8259_setup_cascade(void)
-{
- struct device_node *cascade_node;
- int cascade_irq;
-
- /* Initialize i8259 controller */
- cascade_node = of_find_compatible_node(NULL, NULL, "chrp,iic");
- if (!cascade_node)
- return;
-
- cascade_irq = irq_of_parse_and_map(cascade_node, 0);
- if (!cascade_irq) {
- pr_err("virtex_ml510: Failed to map cascade interrupt\n");
- goto out;
- }
-
- i8259_init(cascade_node, 0);
- irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
-
- /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
- /* This looks like a dirty hack to me --gcl */
- outb(0xc0, 0x4d0);
- outb(0xc0, 0x4d1);
-
- out:
- of_node_put(cascade_node);
-}
-#else
-static inline void xilinx_i8259_setup_cascade(void) { return; }
-#endif /* defined(CONFIG_PPC_I8259) */
-
-/*
- * Initialize master Xilinx interrupt controller
- */
-void __init xilinx_intc_init_tree(void)
-{
- irqchip_init();
- xilinx_i8259_setup_cascade();
-}
diff --git a/arch/powerpc/sysdev/xilinx_pci.c b/arch/powerpc/sysdev/xilinx_pci.c
deleted file mode 100644
index fea5667699ed..000000000000
--- a/arch/powerpc/sysdev/xilinx_pci.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * PCI support for Xilinx plbv46_pci soft-core which can be used on
- * Xilinx Virtex ML410 / ML510 boards.
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
- * by Benjamin Herrenschmidt.
- * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/ioport.h>
-#include <linux/of.h>
-#include <linux/pci.h>
-#include <mm/mmu_decl.h>
-#include <asm/io.h>
-#include <asm/xilinx_pci.h>
-
-#define XPLB_PCI_ADDR 0x10c
-#define XPLB_PCI_DATA 0x110
-#define XPLB_PCI_BUS 0x114
-
-#define PCI_HOST_ENABLE_CMD PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
-
-static const struct of_device_id xilinx_pci_match[] = {
- { .compatible = "xlnx,plbv46-pci-1.03.a", },
- {}
-};
-
-/**
- * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
- */
-static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
-{
- struct pci_controller *hose;
- int i;
-
- if (dev->devfn || dev->bus->self)
- return;
-
- hose = pci_bus_to_host(dev->bus);
- if (!hose)
- return;
-
- if (!of_match_node(xilinx_pci_match, hose->dn))
- return;
-
- /* Hide the PCI host BARs from the kernel as their content doesn't
- * fit well in the resource management
- */
- for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
- }
-
- dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
- pci_name(dev));
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
-
-/**
- * xilinx_pci_exclude_device - Don't do config access for non-root bus
- *
- * This is a hack. Config access to any bus other than bus 0 does not
- * currently work on the ML510 so we prevent it here.
- */
-static int
-xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
-{
- return (bus != 0);
-}
-
-/**
- * xilinx_pci_init - Find and register a Xilinx PCI host bridge
- */
-void __init xilinx_pci_init(void)
-{
- struct pci_controller *hose;
- struct resource r;
- void __iomem *pci_reg;
- struct device_node *pci_node;
-
- pci_node = of_find_matching_node(NULL, xilinx_pci_match);
- if(!pci_node)
- return;
-
- if (of_address_to_resource(pci_node, 0, &r)) {
- pr_err("xilinx-pci: cannot resolve base address\n");
- return;
- }
-
- hose = pcibios_alloc_controller(pci_node);
- if (!hose) {
- pr_err("xilinx-pci: pcibios_alloc_controller() failed\n");
- return;
- }
-
- /* Setup config space */
- setup_indirect_pci(hose, r.start + XPLB_PCI_ADDR,
- r.start + XPLB_PCI_DATA,
- PPC_INDIRECT_TYPE_SET_CFG_TYPE);
-
- /* According to the xilinx plbv46_pci documentation the soft-core starts
- * a self-init when the bus master enable bit is set. Without this bit
- * set the pci bus can't be scanned.
- */
- early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
-
- /* Set the max latency timer to 255 */
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
-
- /* Set the max bus number to 255 */
- pci_reg = of_iomap(pci_node, 0);
- out_8(pci_reg + XPLB_PCI_BUS, 0xff);
- iounmap(pci_reg);
-
- /* Nothing past the root bridge is working right now. By default
- * exclude config access to anything except bus 0 */
- if (!ppc_md.pci_exclude_device)
- ppc_md.pci_exclude_device = xilinx_pci_exclude_device;
-
- /* Register the host bridge with the linux kernel! */
- pci_process_bridge_OF_ranges(hose, pci_node, 1);
-
- pr_info("xilinx-pci: Registered PCI host bridge\n");
-}
diff --git a/arch/powerpc/xmon/ppc-dis.c b/arch/powerpc/xmon/ppc-dis.c
index 75fa98221d48..a91ac589b401 100644
--- a/arch/powerpc/xmon/ppc-dis.c
+++ b/arch/powerpc/xmon/ppc-dis.c
@@ -224,12 +224,6 @@ int print_insn_powerpc (unsigned long insn, unsigned long memaddr)
print_address(memaddr + value);
else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0)
print_address(value & 0xffffffff);
- else if ((operand->flags & PPC_OPERAND_FSL) != 0)
- printf("fsl%ld", value);
- else if ((operand->flags & PPC_OPERAND_FCR) != 0)
- printf("fcr%ld", value);
- else if ((operand->flags & PPC_OPERAND_UDI) != 0)
- printf("%ld", value);
else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
&& (((dialect & PPC_OPCODE_PPC) != 0)
|| ((dialect & PPC_OPCODE_VLE) != 0)))
diff --git a/arch/powerpc/xmon/ppc-opc.c b/arch/powerpc/xmon/ppc-opc.c
index dfb80810b16c..918845e777fd 100644
--- a/arch/powerpc/xmon/ppc-opc.c
+++ b/arch/powerpc/xmon/ppc-opc.c
@@ -857,29 +857,6 @@ const struct powerpc_operand powerpc_operands[] #define HTM_A XFL_L
{ 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
- /* Xilinx APU related masks and macros */
-#define FCRT XFL_L + 1
-#define FCRT_MASK (0x1f << 21)
- { 0x1f, 21, 0, 0, PPC_OPERAND_FCR },
-
- /* Xilinx FSL related masks and macros */
-#define FSL FCRT + 1
-#define FSL_MASK (0x1f << 11)
- { 0x1f, 11, 0, 0, PPC_OPERAND_FSL },
-
- /* Xilinx UDI related masks and macros */
-#define URT FSL + 1
- { 0x1f, 21, 0, 0, PPC_OPERAND_UDI },
-
-#define URA URT + 1
- { 0x1f, 16, 0, 0, PPC_OPERAND_UDI },
-
-#define URB URA + 1
- { 0x1f, 11, 0, 0, PPC_OPERAND_UDI },
-
-#define URC URB + 1
- { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
-
/* The VLESIMM field in a D form instruction. */
#define VLESIMM URC + 1
{ 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
diff --git a/arch/powerpc/xmon/ppc.h b/arch/powerpc/xmon/ppc.h
index d00f33dcf192..37717b1f7bd7 100644
--- a/arch/powerpc/xmon/ppc.h
+++ b/arch/powerpc/xmon/ppc.h
@@ -388,11 +388,6 @@ extern const unsigned int num_powerpc_operands;
/* Valid range of operand is 0..n rather than 0..n-1. */
#define PPC_OPERAND_PLUS1 (0x10000)
-/* Xilinx APU and FSL related operands */
-#define PPC_OPERAND_FSL (0x20000)
-#define PPC_OPERAND_FCR (0x40000)
-#define PPC_OPERAND_UDI (0x80000)
-
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
index 26956c006987..0ccbd6fd6de1 100644
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -316,7 +316,7 @@ config DTLK
config XILINX_HWICAP
tristate "Xilinx HWICAP Support"
- depends on XILINX_VIRTEX || MICROBLAZE
+ depends on MICROBLAZE
help
This option enables support for Xilinx Internal Configuration
Access Port (ICAP) driver. The ICAP is used on Xilinx Virtex
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index f65991a67af2..b174650e0f09 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -2007,7 +2007,7 @@ config FB_PS3_DEFAULT_SIZE_M
config FB_XILINX
tristate "Xilinx frame buffer support"
- depends on FB && (XILINX_VIRTEX || MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
+ depends on FB && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
--
2.26.0
^ permalink raw reply related [flat|nested] 104+ messages in thread* Re: [PATCH 2/2] powerpc: Remove Xilinx PPC405/PPC440 support
2020-03-27 12:12 ` Michal Simek
@ 2020-03-28 1:08 ` kbuild test robot
-1 siblings, 0 replies; 104+ messages in thread
From: kbuild test robot @ 2020-03-28 1:08 UTC (permalink / raw)
To: Michal Simek
Cc: kbuild-all, linux-kernel, monstr, michal.simek, git, sfr, marc.zyngier
[-- Attachment #1: Type: text/plain, Size: 93983 bytes --]
Hi Michal,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on sound/for-next robh/for-next linus/master v5.6-rc7 next-20200327]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Michal-Simek/powerpc-Remove-support-for-ppc405-440-Xilinx-platforms/20200328-034921
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=9.2.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
>> arch/powerpc/xmon/ppc-opc.c:3270:55: error: 'FSL' undeclared here (not in a function)
3270 | {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: error: 'URC' undeclared here (not in a function); did you mean 'XRC'?
861 | #define VLESIMM URC + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:879:13: note: in expansion of macro 'VLEUIMML'
879 | #define XS6 VLEUIMML + 1
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:880:13: note: in expansion of macro 'XS6'
880 | #define XT6 XS6
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:884:14: note: in expansion of macro 'XT6'
884 | #define XSQ6 XT6 + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:885:14: note: in expansion of macro 'XSQ6'
885 | #define XTQ6 XSQ6
| ^~~~
>> arch/powerpc/xmon/ppc-opc.c:889:13: note: in expansion of macro 'XTQ6'
889 | #define XA6 XTQ6 + 1
| ^~~~
>> arch/powerpc/xmon/ppc-opc.c:893:13: note: in expansion of macro 'XA6'
893 | #define XB6 XA6 + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:899:14: note: in expansion of macro 'XB6'
899 | #define XB6S XB6 + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:903:13: note: in expansion of macro 'XB6S'
903 | #define XC6 XB6S + 1
| ^~~~
>> arch/powerpc/xmon/ppc-opc.c:907:12: note: in expansion of macro 'XC6'
907 | #define DM XC6 + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:912:14: note: in expansion of macro 'DM'
912 | #define DMEX DM + 1
| ^~
>> arch/powerpc/xmon/ppc-opc.c:916:13: note: in expansion of macro 'DMEX'
916 | #define UIM DMEX + 1
| ^~~~
>> arch/powerpc/xmon/ppc-opc.c:918:15: note: in expansion of macro 'UIM'
918 | #define UIMM2 UIM
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:3321:62: note: in expansion of macro 'UIMM2'
3321 | {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
| ^~~~~
>> arch/powerpc/xmon/ppc-opc.c:3500:63: error: 'URT' undeclared here (not in a function); did you mean 'XRT'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| XRT
>> arch/powerpc/xmon/ppc-opc.c:3500:68: error: 'URA' undeclared here (not in a function); did you mean 'FRA'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRA
arch/powerpc/xmon/ppc-opc.c:3500:73: error: 'URB' undeclared here (not in a function); did you mean 'FRB'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRB
arch/powerpc/xmon/ppc-opc.c:4674:51: error: 'FCRT' undeclared here (not in a function); did you mean 'FRT'?
4674 | {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
| ^~~~
| FRT
arch/powerpc/xmon/ppc-opc.c:861:17: error: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Werror=int-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Werror=int-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[106].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
vim +/FSL +3270 arch/powerpc/xmon/ppc-opc.c
08d96e0b127e07 Balbir Singh 2017-02-02 3064
08d96e0b127e07 Balbir Singh 2017-02-02 3065 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3066 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3067 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3068 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3069 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3070 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3071 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3072 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3073 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3074 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3075 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3076 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3077 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3078 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3079 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3080 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3081 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3082 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3083 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3084 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3085 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3086 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3087 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3088 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3089 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3090 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3091 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3092 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3093 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3094 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3095 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3096 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3097 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3098 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3099 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3100 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3101 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3102 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3103 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3104 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3105 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3106 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3107 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3108 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3109 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3110 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3111 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3112 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3113 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3114 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3115 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3116 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3117 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3118 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3119 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3120 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3121 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3122 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3123 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3124 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3125 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3126 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3127 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3128 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3129 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3130 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3131 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3132 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3133 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3134 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3135 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3136 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3137 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3138 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3139 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3140 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3141 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3142 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3143 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3144 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3145 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3146 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3147 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3148 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3149 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3150 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3151 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3152 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3153 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3154 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3155 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3156 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3157 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3158 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3159 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3160 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3161 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3162 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3163 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3164 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3165 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3166 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3167 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3168 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3169 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3170 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3171 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3172 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3173 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3174 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3175 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3176 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3177 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3178 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3179 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3180 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3181 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3182 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3183 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3184 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3185 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3186 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3187 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3188 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3189 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3190 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3191 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3192 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3193 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3194 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3195 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3196 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3197 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3198 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3199 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3200 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3201 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3202 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3203 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3204 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3205 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3206 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3207 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3208 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3209 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3210 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3211 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3212 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3213 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3214 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3215 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3216 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3217 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3218 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3219 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3220 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3221 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3222 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3223 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3224 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3225 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3226 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3227 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3228 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3229 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3230 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3231 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3232 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3233 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3234 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3235 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3236 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3237 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3238 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3239 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3240 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3241 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3242 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3243 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3244 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3245 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3246 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3247 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3248 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3249 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3250 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3251 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3252 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3253 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3254 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3255 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3256 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3257 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3258 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3259 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3260 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3261 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3262 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3263 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3264 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3265 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3266 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3267 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3268 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3269 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 @3270 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3271 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3272 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3273 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3274 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3275 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3276 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3277 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3278 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3279 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3280 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3281 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3282 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3283 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3284 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3285 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3286 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3287 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3288 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3289 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3290 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3291 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3292 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3293 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3294 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3295 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3296 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3297 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3298 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3299 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3300 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3301 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
08d96e0b127e07 Balbir Singh 2017-02-02 3302 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3303 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3304 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3305 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3306 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3307 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3308 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3309 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3310 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3311 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3312 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3313 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3314 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3315 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3316 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3317 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3318 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3319 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3320 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 @3321 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
08d96e0b127e07 Balbir Singh 2017-02-02 3322 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3323 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3324 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3325 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3326 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3327 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3328 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3329 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3330 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3331 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3332 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3333 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3334 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3335 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3336 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3337 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3338 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3339 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3340 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3341 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3342 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3343 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3344 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3345 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3346 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3347 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3348 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3349 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3350 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3351 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3352 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3353 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3354 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3355 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3356 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3357 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3358 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3359 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3360 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3361 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3362 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3363 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3364 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3365 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3366 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3367 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3368 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3369 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3370 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3371 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3372 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3373 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3374 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3375 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3376 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3377 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3378 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3379 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3380 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3381 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3382 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3383 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3384 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3385 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3386 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3387 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3388 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3389 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3390 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3391 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3392 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3393 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3394 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3395 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3396 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3397 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3398 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3399 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3400 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3401 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3402 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3403 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3404 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3405 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3406 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3407 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3408 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3409 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3410 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3411 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3412 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3413 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3414 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3415 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3416 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3417 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3418 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3419 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3420 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3421 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3422 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3423 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3424 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3425 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3426 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3427 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3428 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3429 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3430 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3431 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3432 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3433 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3434 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3435 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3436 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3437 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3438 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3439 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3440 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3441 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3442 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3443 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3444 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3445 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3446 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3447 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3448 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3449 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3450 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3451 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3452 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3453 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3454 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3455 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3456 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3457 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3458 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3459 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3460 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3461 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3462 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3463 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3464 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3465 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3466 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3467 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3468 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3469 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3470 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3471 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3472 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3473 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3474 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3475 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3476 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3477 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3478 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3479 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3480 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3481 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3482 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3483 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3484 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3485 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3486 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3487 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3488 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3489 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3490 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3491 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3492 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3493 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3494 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3495 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3496 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3497 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3498 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3499 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3500 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3501 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3502 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3503 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3504 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3505 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3506 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3507 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3508 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3509 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3510 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3511 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3512 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3513 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3514 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3515 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3516 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3517 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3518 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3519 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3520 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3521 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3522 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3523 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3524 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3525 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3526 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3527 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3528 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3529 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3530 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3531 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3532 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3533 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3534 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3535 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3536 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3537 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3538 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3539 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3540 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3541 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3542 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3543 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3544 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3545 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3546 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3547 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3548 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3549 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3550 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3551 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3552 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3553 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3554 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3555 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3556 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3557 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3558 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3559 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3560 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3561 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3562 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3563 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3564 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3565 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3566 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3567 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3568 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3569 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3570 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3571 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3572 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3573 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3574 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3575 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3576 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3577 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3578 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3579 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3580 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3581 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3582 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3583 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3584 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3585 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3586 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3587 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3588 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3589 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3590 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3591 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3592 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3593 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3594 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3595 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3596 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3597 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3598 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3599 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3600 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3601 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3602 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3603 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3604 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3605 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3606 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3607 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3608 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3609 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3610 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3611 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3612 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3613 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3614 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3615 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3616 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3617 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3618 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3619 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3620 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3621 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3622 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3623 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3624 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3625 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3626 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3627 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3628 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3629 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3630 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3631 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3632 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3633 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3634 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3635 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3636 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3637 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3638 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3639 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3640 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3641 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3642 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3643 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3644 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3645 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3646 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3647 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3648 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3649 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3650 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3651 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3652 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3653 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3654 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3655 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3656 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3657 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3658 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3659 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3660 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3661 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3662 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3663 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3664 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3665 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3666 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3667 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3668 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3669 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3670 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3671 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3672 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3673 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3674 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3675 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3676 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3677 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3678 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3679 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3680 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3681 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3682 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3683 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3684 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3685 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3686 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3687 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3688 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3689 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3690 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3691 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3692 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3693 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3694 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3695 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3696 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3697 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3698 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3699 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3700 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3701 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3702 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3703 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3704 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3705 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3706 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3707 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3708 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3709 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3710 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3711 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3712 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3713 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3714 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3715 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3716 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3717 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3718 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3719 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3720 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3721 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3722 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3723 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3724 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3725 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3726 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
08d96e0b127e07 Balbir Singh 2017-02-02 3727 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3728 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3729 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3730 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3731 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3732 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3733 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3734 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3735 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3736 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3737 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3738 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3739 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3740 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3741 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3742 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3743 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3744 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3745 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3746 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3747 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3748 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3749 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3750 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3751 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3752 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3753 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3754 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3755 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3756 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3757 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3758 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3759 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3760 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3761 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3762 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3763 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3764 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3765 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3766 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3767 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3768 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3769 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3770 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3771 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3772 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3773 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3774 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3775 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3776 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3777 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3778 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3779 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3780 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3781 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3782 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3783 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3784 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3785 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3786 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3787 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3788 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3789 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3790 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3791 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3792 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3793 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3794 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3795 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3796 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3797 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3798 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3799 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3800 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3801
:::::: The code at line 3270 was first introduced by commit
:::::: 08d96e0b127e07c3b90e10f1939caf70b456793e powerpc/xmon: Apply binutils changes to upgrade disassembly
:::::: TO: Balbir Singh <bsingharora@gmail.com>
:::::: CC: Michael Ellerman <mpe@ellerman.id.au>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 25778 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread* Re: [PATCH 2/2] powerpc: Remove Xilinx PPC405/PPC440 support
@ 2020-03-28 1:08 ` kbuild test robot
0 siblings, 0 replies; 104+ messages in thread
From: kbuild test robot @ 2020-03-28 1:08 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 94920 bytes --]
Hi Michal,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on sound/for-next robh/for-next linus/master v5.6-rc7 next-20200327]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Michal-Simek/powerpc-Remove-support-for-ppc405-440-Xilinx-platforms/20200328-034921
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=9.2.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
>> arch/powerpc/xmon/ppc-opc.c:3270:55: error: 'FSL' undeclared here (not in a function)
3270 | {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: error: 'URC' undeclared here (not in a function); did you mean 'XRC'?
861 | #define VLESIMM URC + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:879:13: note: in expansion of macro 'VLEUIMML'
879 | #define XS6 VLEUIMML + 1
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:880:13: note: in expansion of macro 'XS6'
880 | #define XT6 XS6
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:884:14: note: in expansion of macro 'XT6'
884 | #define XSQ6 XT6 + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:885:14: note: in expansion of macro 'XSQ6'
885 | #define XTQ6 XSQ6
| ^~~~
>> arch/powerpc/xmon/ppc-opc.c:889:13: note: in expansion of macro 'XTQ6'
889 | #define XA6 XTQ6 + 1
| ^~~~
>> arch/powerpc/xmon/ppc-opc.c:893:13: note: in expansion of macro 'XA6'
893 | #define XB6 XA6 + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:899:14: note: in expansion of macro 'XB6'
899 | #define XB6S XB6 + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:903:13: note: in expansion of macro 'XB6S'
903 | #define XC6 XB6S + 1
| ^~~~
>> arch/powerpc/xmon/ppc-opc.c:907:12: note: in expansion of macro 'XC6'
907 | #define DM XC6 + 1
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:912:14: note: in expansion of macro 'DM'
912 | #define DMEX DM + 1
| ^~
>> arch/powerpc/xmon/ppc-opc.c:916:13: note: in expansion of macro 'DMEX'
916 | #define UIM DMEX + 1
| ^~~~
>> arch/powerpc/xmon/ppc-opc.c:918:15: note: in expansion of macro 'UIM'
918 | #define UIMM2 UIM
| ^~~
>> arch/powerpc/xmon/ppc-opc.c:3321:62: note: in expansion of macro 'UIMM2'
3321 | {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
| ^~~~~
>> arch/powerpc/xmon/ppc-opc.c:3500:63: error: 'URT' undeclared here (not in a function); did you mean 'XRT'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| XRT
>> arch/powerpc/xmon/ppc-opc.c:3500:68: error: 'URA' undeclared here (not in a function); did you mean 'FRA'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRA
arch/powerpc/xmon/ppc-opc.c:3500:73: error: 'URB' undeclared here (not in a function); did you mean 'FRB'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRB
arch/powerpc/xmon/ppc-opc.c:4674:51: error: 'FCRT' undeclared here (not in a function); did you mean 'FRT'?
4674 | {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
| ^~~~
| FRT
arch/powerpc/xmon/ppc-opc.c:861:17: error: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Werror=int-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Werror=int-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[106].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
vim +/FSL +3270 arch/powerpc/xmon/ppc-opc.c
08d96e0b127e07 Balbir Singh 2017-02-02 3064
08d96e0b127e07 Balbir Singh 2017-02-02 3065 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3066 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3067 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3068 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3069 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3070 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3071 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3072 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3073 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3074 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3075 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3076 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3077 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3078 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3079 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3080 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3081 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3082 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3083 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3084 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3085 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3086 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3087 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3088 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3089 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3090 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3091 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3092 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3093 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3094 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3095 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3096 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3097 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3098 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3099 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3100 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3101 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3102 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3103 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3104 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3105 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3106 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3107 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3108 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3109 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3110 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3111 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3112 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3113 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3114 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3115 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3116 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3117 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3118 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3119 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3120 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3121 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3122 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3123 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3124 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3125 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3126 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3127 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3128 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3129 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3130 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3131 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3132 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3133 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3134 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3135 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3136 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3137 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3138 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3139 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3140 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3141 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3142 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3143 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3144 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3145 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3146 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3147 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3148 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3149 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3150 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3151 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3152 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3153 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3154 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3155 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3156 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3157 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3158 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3159 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3160 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3161 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3162 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3163 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3164 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3165 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3166 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3167 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3168 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3169 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3170 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3171 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3172 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3173 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3174 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3175 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3176 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3177 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3178 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3179 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3180 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3181 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3182 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3183 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3184 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3185 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3186 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3187 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3188 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3189 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3190 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3191 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3192 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3193 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3194 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3195 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3196 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3197 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3198 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3199 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3200 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3201 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3202 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3203 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3204 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3205 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3206 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3207 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3208 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3209 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3210 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3211 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3212 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3213 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3214 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3215 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3216 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3217 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3218 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3219 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3220 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3221 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3222 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3223 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3224 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3225 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3226 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3227 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3228 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3229 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3230 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3231 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3232 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3233 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3234 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3235 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3236 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3237 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3238 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3239 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3240 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3241 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3242 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3243 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3244 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3245 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3246 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3247 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3248 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3249 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3250 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3251 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3252 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3253 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3254 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3255 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3256 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3257 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3258 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3259 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3260 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3261 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3262 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3263 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3264 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3265 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3266 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3267 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3268 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3269 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 @3270 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3271 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3272 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3273 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3274 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3275 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3276 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3277 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3278 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3279 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3280 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3281 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3282 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3283 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3284 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3285 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3286 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3287 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3288 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3289 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3290 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3291 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3292 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3293 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3294 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3295 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3296 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3297 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3298 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3299 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3300 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3301 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
08d96e0b127e07 Balbir Singh 2017-02-02 3302 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3303 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3304 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3305 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3306 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3307 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3308 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3309 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3310 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3311 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3312 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3313 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3314 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3315 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3316 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3317 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3318 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3319 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3320 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 @3321 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
08d96e0b127e07 Balbir Singh 2017-02-02 3322 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3323 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3324 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3325 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3326 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3327 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3328 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3329 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3330 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3331 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3332 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3333 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3334 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3335 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3336 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3337 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3338 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3339 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3340 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3341 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3342 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3343 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3344 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3345 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3346 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3347 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3348 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3349 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3350 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3351 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3352 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3353 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3354 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3355 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3356 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3357 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3358 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3359 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3360 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3361 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3362 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3363 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3364 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3365 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3366 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3367 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3368 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3369 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3370 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3371 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3372 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3373 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3374 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3375 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3376 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3377 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3378 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3379 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3380 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3381 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3382 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3383 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3384 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3385 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3386 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3387 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3388 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3389 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3390 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3391 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3392 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3393 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3394 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3395 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3396 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3397 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3398 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3399 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3400 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3401 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3402 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3403 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3404 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3405 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3406 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3407 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3408 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3409 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3410 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3411 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3412 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3413 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3414 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3415 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3416 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3417 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3418 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3419 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3420 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3421 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3422 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3423 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3424 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3425 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3426 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3427 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3428 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3429 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3430 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3431 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3432 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3433 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3434 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3435 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3436 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3437 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3438 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3439 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3440 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3441 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3442 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3443 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3444 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3445 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3446 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3447 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3448 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3449 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3450 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3451 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3452 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3453 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3454 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3455 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3456 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3457 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3458 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3459 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3460 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3461 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3462 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3463 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3464 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3465 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3466 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3467 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3468 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3469 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3470 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3471 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3472 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3473 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3474 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3475 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3476 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3477 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3478 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3479 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3480 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3481 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3482 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3483 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3484 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3485 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3486 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3487 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3488 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3489 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3490 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3491 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3492 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3493 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3494 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3495 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3496 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3497 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3498 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3499 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3500 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3501 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3502 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3503 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3504 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3505 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3506 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3507 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3508 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3509 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3510 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3511 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3512 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3513 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3514 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3515 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3516 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3517 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3518 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3519 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3520 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3521 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3522 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3523 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3524 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3525 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3526 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3527 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3528 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3529 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3530 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3531 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3532 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3533 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3534 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3535 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3536 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3537 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3538 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3539 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3540 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3541 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3542 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3543 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3544 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3545 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3546 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3547 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3548 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3549 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3550 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3551 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3552 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3553 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3554 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3555 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3556 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3557 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3558 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3559 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3560 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3561 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3562 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3563 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3564 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3565 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3566 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3567 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3568 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3569 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3570 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3571 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3572 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3573 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3574 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3575 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3576 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3577 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3578 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3579 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3580 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3581 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3582 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3583 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3584 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3585 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3586 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3587 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3588 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3589 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3590 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3591 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3592 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3593 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3594 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3595 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3596 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3597 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3598 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3599 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3600 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3601 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3602 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3603 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3604 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3605 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3606 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3607 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3608 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3609 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3610 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3611 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3612 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3613 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3614 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3615 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3616 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3617 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3618 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3619 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3620 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3621 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3622 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3623 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3624 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3625 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3626 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3627 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3628 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3629 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3630 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3631 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3632 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3633 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3634 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3635 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3636 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3637 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3638 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3639 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3640 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3641 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3642 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3643 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3644 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3645 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3646 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3647 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3648 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3649 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3650 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3651 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3652 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3653 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3654 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3655 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3656 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3657 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3658 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3659 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3660 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3661 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3662 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3663 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3664 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3665 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3666 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3667 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3668 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3669 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3670 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3671 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3672 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3673 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3674 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3675 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3676 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3677 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3678 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3679 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3680 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3681 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3682 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3683 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3684 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3685 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3686 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3687 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3688 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3689 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3690 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3691 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3692 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3693 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3694 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3695 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3696 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3697 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3698 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3699 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3700 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3701 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3702 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3703 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3704 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3705 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3706 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3707 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3708 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3709 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3710 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3711 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3712 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3713 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3714 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3715 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3716 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3717 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3718 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3719 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3720 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3721 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3722 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3723 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3724 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3725 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3726 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
08d96e0b127e07 Balbir Singh 2017-02-02 3727 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3728 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3729 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3730 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3731 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3732 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3733 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3734 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3735 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3736 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3737 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3738 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3739 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3740 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3741 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3742 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3743 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3744 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3745 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3746 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3747 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3748 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3749 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3750 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3751 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3752 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3753 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3754 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3755 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3756 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3757 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3758 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3759 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3760 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3761 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3762 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3763 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3764 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3765 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3766 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3767 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3768 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3769 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3770 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3771 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3772 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3773 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3774 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3775 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3776 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3777 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3778 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3779 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3780 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3781 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3782 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3783 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3784 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3785 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3786 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3787 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3788 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3789 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3790 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3791 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3792 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3793 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3794 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3795 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3796 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3797 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3798 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3799 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3800 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3801
:::::: The code at line 3270 was first introduced by commit
:::::: 08d96e0b127e07c3b90e10f1939caf70b456793e powerpc/xmon: Apply binutils changes to upgrade disassembly
:::::: TO: Balbir Singh <bsingharora@gmail.com>
:::::: CC: Michael Ellerman <mpe@ellerman.id.au>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 25778 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread
* Re: [PATCH 2/2] powerpc: Remove Xilinx PPC405/PPC440 support
2020-03-27 12:12 ` Michal Simek
@ 2020-03-28 1:31 ` kbuild test robot
-1 siblings, 0 replies; 104+ messages in thread
From: kbuild test robot @ 2020-03-28 1:31 UTC (permalink / raw)
To: Michal Simek
Cc: kbuild-all, linux-kernel, monstr, michal.simek, git, sfr, marc.zyngier
[-- Attachment #1: Type: text/plain, Size: 124671 bytes --]
Hi Michal,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on sound/for-next robh/for-next linus/master v5.6-rc7 next-20200327]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Michal-Simek/powerpc-Remove-support-for-ppc405-440-Xilinx-platforms/20200328-034921
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=9.2.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
arch/powerpc/xmon/ppc-opc.c:3270:55: error: 'FSL' undeclared here (not in a function)
3270 | {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
| ^~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: 'URC' undeclared here (not in a function); did you mean 'XRC'?
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:879:13: note: in expansion of macro 'VLEUIMML'
879 | #define XS6 VLEUIMML + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:880:13: note: in expansion of macro 'XS6'
880 | #define XT6 XS6
| ^~~
arch/powerpc/xmon/ppc-opc.c:884:14: note: in expansion of macro 'XT6'
884 | #define XSQ6 XT6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:885:14: note: in expansion of macro 'XSQ6'
885 | #define XTQ6 XSQ6
| ^~~~
arch/powerpc/xmon/ppc-opc.c:889:13: note: in expansion of macro 'XTQ6'
889 | #define XA6 XTQ6 + 1
| ^~~~
arch/powerpc/xmon/ppc-opc.c:893:13: note: in expansion of macro 'XA6'
893 | #define XB6 XA6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:899:14: note: in expansion of macro 'XB6'
899 | #define XB6S XB6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:903:13: note: in expansion of macro 'XB6S'
903 | #define XC6 XB6S + 1
| ^~~~
arch/powerpc/xmon/ppc-opc.c:907:12: note: in expansion of macro 'XC6'
907 | #define DM XC6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:912:14: note: in expansion of macro 'DM'
912 | #define DMEX DM + 1
| ^~
arch/powerpc/xmon/ppc-opc.c:916:13: note: in expansion of macro 'DMEX'
916 | #define UIM DMEX + 1
| ^~~~
arch/powerpc/xmon/ppc-opc.c:918:15: note: in expansion of macro 'UIM'
918 | #define UIMM2 UIM
| ^~~
arch/powerpc/xmon/ppc-opc.c:3321:62: note: in expansion of macro 'UIMM2'
3321 | {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
| ^~~~~
>> arch/powerpc/xmon/ppc-opc.c:3500:63: error: 'URT' undeclared here (not in a function); did you mean 'FRT'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRT
arch/powerpc/xmon/ppc-opc.c:3500:68: error: 'URA' undeclared here (not in a function); did you mean 'FRA'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRA
arch/powerpc/xmon/ppc-opc.c:3500:73: error: 'URB' undeclared here (not in a function); did you mean 'FRB'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRB
arch/powerpc/xmon/ppc-opc.c:4674:51: error: 'FCRT' undeclared here (not in a function); did you mean 'FRT'?
4674 | {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
| ^~~~
| FRT
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[106].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[106].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[107].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[107].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[108].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[108].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[109].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[109].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[110].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[110].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[111].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[111].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[112].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[112].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[113].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[113].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[114].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[114].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[115].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[115].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[116].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[116].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[117].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[117].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[118].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[118].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
vim +3500 arch/powerpc/xmon/ppc-opc.c
08d96e0b127e07 Balbir Singh 2017-02-02 3064
08d96e0b127e07 Balbir Singh 2017-02-02 3065 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3066 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3067 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3068 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3069 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3070 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3071 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3072 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3073 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3074 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3075 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3076 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3077 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3078 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3079 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3080 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3081 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3082 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3083 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3084 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3085 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3086 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3087 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3088 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3089 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3090 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3091 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3092 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3093 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3094 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3095 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3096 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3097 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3098 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3099 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3100 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3101 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3102 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3103 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3104 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3105 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3106 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3107 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3108 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3109 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3110 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3111 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3112 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3113 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3114 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3115 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3116 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3117 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3118 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3119 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3120 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3121 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3122 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3123 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3124 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3125 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3126 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3127 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3128 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3129 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3130 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3131 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3132 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3133 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3134 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3135 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3136 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3137 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3138 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3139 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3140 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3141 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3142 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3143 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3144 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3145 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3146 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3147 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3148 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3149 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3150 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3151 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3152 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3153 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3154 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3155 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3156 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3157 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3158 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3159 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3160 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3161 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3162 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3163 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3164 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3165 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3166 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3167 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3168 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3169 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3170 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3171 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3172 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3173 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3174 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3175 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3176 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3177 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3178 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3179 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3180 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3181 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3182 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3183 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3184 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3185 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3186 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3187 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3188 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3189 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3190 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3191 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3192 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3193 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3194 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3195 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3196 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3197 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3198 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3199 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3200 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3201 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3202 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3203 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3204 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3205 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3206 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3207 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3208 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3209 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3210 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3211 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3212 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3213 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3214 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3215 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3216 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3217 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3218 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3219 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3220 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3221 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3222 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3223 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3224 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3225 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3226 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3227 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3228 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3229 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3230 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3231 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3232 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3233 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3234 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3235 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3236 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3237 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3238 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3239 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3240 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3241 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3242 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3243 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3244 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3245 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3246 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3247 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3248 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3249 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3250 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3251 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3252 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3253 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3254 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3255 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3256 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3257 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3258 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3259 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3260 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3261 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3262 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3263 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3264 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3265 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3266 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3267 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3268 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3269 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3270 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3271 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3272 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3273 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3274 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3275 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3276 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3277 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3278 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3279 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3280 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3281 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3282 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3283 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3284 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3285 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3286 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3287 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3288 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3289 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3290 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3291 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3292 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3293 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3294 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3295 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3296 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3297 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3298 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3299 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3300 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3301 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
08d96e0b127e07 Balbir Singh 2017-02-02 3302 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3303 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3304 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3305 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3306 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3307 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3308 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3309 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3310 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3311 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3312 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3313 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3314 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3315 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3316 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3317 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3318 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3319 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3320 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3321 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
08d96e0b127e07 Balbir Singh 2017-02-02 3322 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3323 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3324 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3325 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3326 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3327 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3328 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3329 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3330 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3331 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3332 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3333 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3334 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3335 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3336 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3337 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3338 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3339 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3340 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3341 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3342 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3343 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3344 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3345 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3346 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3347 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3348 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3349 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3350 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3351 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3352 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3353 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3354 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3355 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3356 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3357 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3358 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3359 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3360 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3361 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3362 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3363 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3364 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3365 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3366 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3367 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3368 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3369 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3370 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3371 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3372 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3373 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3374 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3375 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3376 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3377 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3378 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3379 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3380 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3381 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3382 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3383 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3384 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3385 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3386 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3387 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3388 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3389 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3390 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3391 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3392 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3393 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3394 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3395 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3396 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3397 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3398 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3399 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3400 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3401 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3402 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3403 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3404 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3405 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3406 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3407 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3408 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3409 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3410 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3411 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3412 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3413 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3414 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3415 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3416 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3417 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3418 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3419 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3420 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3421 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3422 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3423 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3424 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3425 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3426 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3427 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3428 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3429 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3430 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3431 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3432 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3433 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3434 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3435 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3436 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3437 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3438 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3439 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3440 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3441 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3442 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3443 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3444 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3445 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3446 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3447 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3448 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3449 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3450 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3451 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3452 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3453 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3454 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3455 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3456 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3457 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3458 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3459 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3460 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3461 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3462 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3463 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3464 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3465 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3466 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3467 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3468 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3469 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3470 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3471 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3472 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3473 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3474 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3475 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3476 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3477 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3478 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3479 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3480 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3481 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3482 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3483 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3484 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3485 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3486 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3487 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3488 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3489 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3490 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3491 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3492 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3493 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3494 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3495 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3496 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3497 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3498 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3499 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 @3500 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3501 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3502 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3503 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3504 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3505 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3506 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3507 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3508 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3509 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3510 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3511 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3512 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3513 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3514 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3515 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3516 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3517 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3518 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3519 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3520 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3521 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3522 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3523 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3524 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3525 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3526 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3527 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3528 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3529 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3530 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3531 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3532 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3533 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3534 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3535 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3536 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3537 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3538 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3539 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3540 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3541 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3542 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3543 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3544 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3545 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3546 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3547 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3548 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3549 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3550 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3551 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3552 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3553 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3554 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3555 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3556 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3557 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3558 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3559 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3560 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3561 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3562 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3563 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3564 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3565 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3566 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3567 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3568 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3569 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3570 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3571 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3572 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3573 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3574 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3575 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3576 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3577 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3578 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3579 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3580 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3581 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3582 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3583 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3584 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3585 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3586 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3587 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3588 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3589 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3590 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3591 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3592 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3593 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3594 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3595 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3596 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3597 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3598 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3599 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3600 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3601 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3602 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3603 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3604 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3605 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3606 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3607 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3608 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3609 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3610 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3611 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3612 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3613 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3614 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3615 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3616 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3617 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3618 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3619 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3620 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3621 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3622 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3623 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3624 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3625 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3626 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3627 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3628 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3629 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3630 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3631 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3632 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3633 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3634 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3635 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3636 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3637 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3638 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3639 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3640 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3641 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3642 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3643 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3644 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3645 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3646 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3647 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3648 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3649 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3650 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3651 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3652 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3653 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3654 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3655 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3656 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3657 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3658 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3659 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3660 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3661 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3662 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3663 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3664 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3665 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3666 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3667 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3668 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3669 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3670 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3671 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3672 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3673 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3674 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3675 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3676 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3677 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3678 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3679 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3680 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3681 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3682 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3683 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3684 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3685 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3686 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3687 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3688 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3689 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3690 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3691 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3692 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3693 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3694 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3695 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3696 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3697 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3698 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3699 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3700 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3701 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3702 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3703 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3704 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3705 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3706 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3707 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3708 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3709 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3710 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3711 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3712 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3713 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3714 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3715 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3716 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3717 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3718 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3719 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3720 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3721 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3722 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3723 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3724 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3725 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3726 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
08d96e0b127e07 Balbir Singh 2017-02-02 3727 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3728 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3729 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3730 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3731 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3732 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3733 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3734 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3735 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3736 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3737 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3738 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3739 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3740 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3741 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3742 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3743 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3744 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3745 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3746 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3747 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3748 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3749 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3750 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3751 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3752 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3753 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3754 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3755 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3756 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3757 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3758 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3759 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3760 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3761 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3762 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3763 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3764 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3765 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3766 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3767 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3768 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3769 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3770 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3771 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3772 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3773 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3774 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3775 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3776 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3777 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3778 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3779 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3780 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3781 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3782 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3783 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3784 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3785 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3786 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3787 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3788 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3789 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3790 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3791 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3792 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3793 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3794 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3795 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3796 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3797 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3798 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3799 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3800 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3801
:::::: The code at line 3500 was first introduced by commit
:::::: 08d96e0b127e07c3b90e10f1939caf70b456793e powerpc/xmon: Apply binutils changes to upgrade disassembly
:::::: TO: Balbir Singh <bsingharora@gmail.com>
:::::: CC: Michael Ellerman <mpe@ellerman.id.au>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 64772 bytes --]
^ permalink raw reply [flat|nested] 104+ messages in thread* Re: [PATCH 2/2] powerpc: Remove Xilinx PPC405/PPC440 support
@ 2020-03-28 1:31 ` kbuild test robot
0 siblings, 0 replies; 104+ messages in thread
From: kbuild test robot @ 2020-03-28 1:31 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 126107 bytes --]
Hi Michal,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on sound/for-next robh/for-next linus/master v5.6-rc7 next-20200327]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Michal-Simek/powerpc-Remove-support-for-ppc405-440-Xilinx-platforms/20200328-034921
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allyesconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=9.2.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
arch/powerpc/xmon/ppc-opc.c:3270:55: error: 'FSL' undeclared here (not in a function)
3270 | {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
| ^~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: 'URC' undeclared here (not in a function); did you mean 'XRC'?
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:879:13: note: in expansion of macro 'VLEUIMML'
879 | #define XS6 VLEUIMML + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:880:13: note: in expansion of macro 'XS6'
880 | #define XT6 XS6
| ^~~
arch/powerpc/xmon/ppc-opc.c:884:14: note: in expansion of macro 'XT6'
884 | #define XSQ6 XT6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:885:14: note: in expansion of macro 'XSQ6'
885 | #define XTQ6 XSQ6
| ^~~~
arch/powerpc/xmon/ppc-opc.c:889:13: note: in expansion of macro 'XTQ6'
889 | #define XA6 XTQ6 + 1
| ^~~~
arch/powerpc/xmon/ppc-opc.c:893:13: note: in expansion of macro 'XA6'
893 | #define XB6 XA6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:899:14: note: in expansion of macro 'XB6'
899 | #define XB6S XB6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:903:13: note: in expansion of macro 'XB6S'
903 | #define XC6 XB6S + 1
| ^~~~
arch/powerpc/xmon/ppc-opc.c:907:12: note: in expansion of macro 'XC6'
907 | #define DM XC6 + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:912:14: note: in expansion of macro 'DM'
912 | #define DMEX DM + 1
| ^~
arch/powerpc/xmon/ppc-opc.c:916:13: note: in expansion of macro 'DMEX'
916 | #define UIM DMEX + 1
| ^~~~
arch/powerpc/xmon/ppc-opc.c:918:15: note: in expansion of macro 'UIM'
918 | #define UIMM2 UIM
| ^~~
arch/powerpc/xmon/ppc-opc.c:3321:62: note: in expansion of macro 'UIMM2'
3321 | {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
| ^~~~~
>> arch/powerpc/xmon/ppc-opc.c:3500:63: error: 'URT' undeclared here (not in a function); did you mean 'FRT'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRT
arch/powerpc/xmon/ppc-opc.c:3500:68: error: 'URA' undeclared here (not in a function); did you mean 'FRA'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRA
arch/powerpc/xmon/ppc-opc.c:3500:73: error: 'URB' undeclared here (not in a function); did you mean 'FRB'?
3500 | {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
| ^~~
| FRB
arch/powerpc/xmon/ppc-opc.c:4674:51: error: 'FCRT' undeclared here (not in a function); did you mean 'FRT'?
4674 | {"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
| ^~~~
| FRT
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[105].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7068:52: note: in expansion of macro 'VLEUIMML'
7068 | {"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[106].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[106].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7069:56: note: in expansion of macro 'VLEUIMML'
7069 | {"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[107].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[107].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7070:54: note: in expansion of macro 'VLEUIMML'
7070 | {"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[108].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[108].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7071:55: note: in expansion of macro 'VLEUIMML'
7071 | {"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[109].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[109].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:875:18: note: in expansion of macro 'VLEUIMM'
875 | #define VLEUIMML VLEUIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7072:53: note: in expansion of macro 'VLEUIMML'
7072 | {"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[110].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[110].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7073:57: note: in expansion of macro 'VLEUIMM'
7073 | {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[111].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[111].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7074:56: note: in expansion of macro 'VLESIMM'
7074 | {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[112].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[112].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:871:17: note: in expansion of macro 'VLENSIMM'
871 | #define VLEUIMM VLENSIMM + 1
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:7075:56: note: in expansion of macro 'VLEUIMM'
7075 | {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[113].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[113].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7076:55: note: in expansion of macro 'VLESIMM'
7076 | {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[114].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[114].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7077:55: note: in expansion of macro 'VLESIMM'
7077 | {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[115].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[115].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7078:55: note: in expansion of macro 'VLENSIMM'
7078 | {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[116].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[116].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7079:55: note: in expansion of macro 'VLESIMM'
7079 | {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[117].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[117].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:866:18: note: in expansion of macro 'VLESIMM'
866 | #define VLENSIMM VLESIMM + 1
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:7080:55: note: in expansion of macro 'VLENSIMM'
7080 | {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
| ^~~~~~~~
>> arch/powerpc/xmon/ppc-opc.c:861:17: warning: initialization of 'unsigned char' from 'const struct powerpc_opcode *' makes integer from pointer without a cast [-Wint-conversion]
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[118].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: error: initializer element is not constant
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
arch/powerpc/xmon/ppc-opc.c:861:17: note: (near initialization for 'vle_opcodes[118].operands[1]')
861 | #define VLESIMM URC + 1
| ^~~
arch/powerpc/xmon/ppc-opc.c:7081:55: note: in expansion of macro 'VLESIMM'
7081 | {"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
| ^~~~~~~
vim +3500 arch/powerpc/xmon/ppc-opc.c
08d96e0b127e07 Balbir Singh 2017-02-02 3064
08d96e0b127e07 Balbir Singh 2017-02-02 3065 {"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3066 {"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3067 {"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3068 {"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3069 {"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3070 {"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3071 {"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3072 {"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3073 {"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3074 {"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3075 {"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3076 {"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3077 {"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3078 {"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3079 {"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3080 {"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3081 {"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3082 {"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3083 {"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3084 {"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3085 {"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3086 {"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3087 {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3088 {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3089 {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3090 {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3091 {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3092 {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3093 {"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3094 {"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3095 {"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3096 {"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3097 {"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3098 {"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3099 {"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3100 {"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3101 {"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3102 {"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3103 {"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3104 {"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3105 {"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3106 {"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3107 {"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3108 {"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3109 {"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3110 {"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3111 {"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3112 {"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3113 {"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3114 {"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3115 {"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3116 {"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3117 {"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3118 {"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3119 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3120 {"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3121 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3122 {"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3123 {"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3124 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3125 {"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3126 {"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3127 {"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3128 {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3129 {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3130 {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3131 {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3132 {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3133 {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3134 {"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3135 {"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3136 {"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3137 {"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3138 {"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3139 {"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
08d96e0b127e07 Balbir Singh 2017-02-02 3140 {"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3141 {"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3142 {"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3143 {"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3144 {"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3145 {"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3146 {"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3147 {"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3148 {"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3149 {"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3150 {"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3151 {"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3152 {"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3153 {"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3154 {"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3155 {"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3156 {"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3157 {"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3158 {"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3159 {"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3160 {"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3161 {"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3162 {"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3163 {"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3164 {"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3165 {"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3166 {"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3167 {"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3168 {"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3169 {"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3170 {"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3171 {"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3172 {"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3173 {"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3174 {"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3175 {"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3176 {"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3177 {"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3178 {"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3179 {"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3180 {"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3181 {"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3182 {"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3183 {"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3184 {"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3185 {"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3186 {"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3187 {"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3188 {"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3189 {"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3190 {"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3191 {"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3192 {"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3193 {"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3194 {"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3195 {"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3196 {"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3197 {"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3198 {"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3199 {"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3200 {"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3201 {"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3202 {"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3203 {"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3204 {"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3205 {"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3206 {"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3207 {"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3208 {"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3209 {"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3210 {"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3211 {"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3212 {"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3213 {"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3214 {"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3215 {"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3216 {"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3217 {"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3218 {"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3219 {"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3220 {"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3221 {"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3222 {"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3223 {"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3224 {"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3225 {"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3226 {"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3227 {"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3228 {"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3229 {"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3230 {"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3231 {"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3232 {"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3233 {"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3234 {"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3235 {"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3236 {"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3237 {"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3238 {"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3239 {"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3240 {"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3241 {"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3242 {"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3243 {"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3244 {"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3245 {"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3246 {"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3247 {"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3248 {"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3249 {"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3250 {"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3251 {"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3252 {"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3253 {"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3254 {"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3255 {"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3256 {"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3257 {"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3258 {"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3259 {"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3260 {"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3261 {"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3262 {"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3263 {"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3264 {"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3265 {"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3266 {"evmr", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3267 {"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3268 {"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3269 {"evnot", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, BBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3270 {"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3271 {"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3272 {"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3273 {"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3274 {"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3275 {"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3276 {"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3277 {"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3278 {"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3279 {"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3280 {"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3281 {"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3282 {"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3283 {"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3284 {"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3285 {"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3286 {"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3287 {"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3288 {"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3289 {"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3290 {"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3291 {"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3292 {"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3293 {"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3294 {"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3295 {"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3296 {"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3297 {"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3298 {"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3299 {"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3300 {"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3301 {"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}},
08d96e0b127e07 Balbir Singh 2017-02-02 3302 {"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3303 {"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3304 {"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3305 {"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3306 {"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3307 {"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3308 {"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3309 {"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3310 {"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3311 {"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3312 {"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3313 {"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3314 {"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3315 {"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3316 {"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3317 {"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3318 {"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3319 {"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3320 {"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3321 {"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}},
08d96e0b127e07 Balbir Singh 2017-02-02 3322 {"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3323 {"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3324 {"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3325 {"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3326 {"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3327 {"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3328 {"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3329 {"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3330 {"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3331 {"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3332 {"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3333 {"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3334 {"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3335 {"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3336 {"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3337 {"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3338 {"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3339 {"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3340 {"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3341 {"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3342 {"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3343 {"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3344 {"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3345 {"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3346 {"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3347 {"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3348 {"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3349 {"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3350 {"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3351 {"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3352 {"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3353 {"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3354 {"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3355 {"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3356 {"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3357 {"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3358 {"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3359 {"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3360 {"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3361 {"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3362 {"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3363 {"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3364 {"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3365 {"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3366 {"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3367 {"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3368 {"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3369 {"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3370 {"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3371 {"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3372 {"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3373 {"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3374 {"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3375 {"efdcfuid", VX (4, 738), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3376 {"efdcfsid", VX (4, 739), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3377 {"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3378 {"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3379 {"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3380 {"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3381 {"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3382 {"efdctuidz", VX (4, 746), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3383 {"efdctsidz", VX (4, 747), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3384 {"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3385 {"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3386 {"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3387 {"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3388 {"efdcfui", VX (4, 752), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3389 {"efdcfsi", VX (4, 753), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3390 {"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3391 {"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3392 {"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3393 {"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3394 {"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3395 {"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3396 {"efdctuiz", VX (4, 760), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3397 {"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}},
08d96e0b127e07 Balbir Singh 2017-02-02 3398 {"efdctsiz", VX (4, 762), VX_MASK, PPCEFS, 0, {RS, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3399 {"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3400 {"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3401 {"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3402 {"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3403 {"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3404 {"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3405 {"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3406 {"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3407 {"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3408 {"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3409 {"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3410 {"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3411 {"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3412 {"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3413 {"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3414 {"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3415 {"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3416 {"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3417 {"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3418 {"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3419 {"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3420 {"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3421 {"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3422 {"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3423 {"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3424 {"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3425 {"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3426 {"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3427 {"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3428 {"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3429 {"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3430 {"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3431 {"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3432 {"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3433 {"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3434 {"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3435 {"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3436 {"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3437 {"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3438 {"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3439 {"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3440 {"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3441 {"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3442 {"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3443 {"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3444 {"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3445 {"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3446 {"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3447 {"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3448 {"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3449 {"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3450 {"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3451 {"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3452 {"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3453 {"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3454 {"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3455 {"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3456 {"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3457 {"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3458 {"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3459 {"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3460 {"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3461 {"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3462 {"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3463 {"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3464 {"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3465 {"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3466 {"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3467 {"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3468 {"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3469 {"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3470 {"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3471 {"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3472 {"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3473 {"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3474 {"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3475 {"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3476 {"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3477 {"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3478 {"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3479 {"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3480 {"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3481 {"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3482 {"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3483 {"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3484 {"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3485 {"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}},
08d96e0b127e07 Balbir Singh 2017-02-02 3486 {"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}},
08d96e0b127e07 Balbir Singh 2017-02-02 3487 {"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3488 {"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3489 {"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3490 {"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3491 {"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3492 {"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3493 {"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3494 {"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3495 {"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3496 {"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3497 {"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3498 {"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3499 {"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 @3500 {"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3501 {"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3502 {"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3503 {"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3504 {"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3505 {"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3506 {"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3507 {"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3508 {"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3509 {"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3510 {"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3511 {"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3512 {"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3513 {"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3514 {"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3515 {"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3516 {"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3517 {"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3518 {"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3519 {"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3520 {"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3521 {"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3522 {"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3523 {"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3524 {"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3525 {"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3526 {"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3527 {"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3528 {"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3529 {"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3530 {"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3531 {"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3532 {"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3533 {"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3534 {"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3535 {"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3536 {"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3537 {"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3538 {"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3539 {"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3540 {"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3541 {"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3542 {"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3543 {"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3544 {"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3545 {"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3546 {"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3547 {"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3548 {"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3549 {"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3550 {"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3551 {"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3552 {"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3553 {"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3554 {"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3555 {"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3556 {"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3557 {"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3558 {"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3559 {"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3560 {"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3561 {"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3562 {"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3563 {"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3564 {"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3565 {"vmr", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3566 {"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3567 {"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3568 {"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3569 {"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3570 {"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3571 {"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3572 {"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3573 {"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3574 {"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3575 {"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3576 {"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3577 {"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3578 {"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3579 {"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3580 {"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3581 {"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3582 {"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3583 {"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3584 {"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3585 {"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3586 {"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3587 {"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3588 {"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3589 {"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3590 {"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3591 {"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3592 {"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3593 {"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3594 {"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3595 {"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3596 {"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3597 {"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3598 {"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3599 {"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3600 {"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3601 {"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3602 {"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3603 {"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3604 {"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3605 {"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3606 {"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3607 {"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3608 {"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3609 {"vnot", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VBA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3610 {"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3611 {"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3612 {"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3613 {"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3614 {"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3615 {"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3616 {"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3617 {"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3618 {"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3619 {"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3620 {"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3621 {"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3622 {"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3623 {"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3624 {"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3625 {"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3626 {"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3627 {"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3628 {"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3629 {"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3630 {"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3631 {"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3632 {"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3633 {"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3634 {"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3635 {"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3636 {"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3637 {"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3638 {"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3639 {"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3640 {"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3641 {"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3642 {"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3643 {"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3644 {"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3645 {"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3646 {"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3647 {"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3648 {"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3649 {"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3650 {"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3651 {"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3652 {"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3653 {"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3654 {"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3655 {"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3656 {"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3657 {"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3658 {"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3659 {"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3660 {"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3661 {"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3662 {"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3663 {"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3664 {"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3665 {"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3666 {"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3667 {"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3668 {"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3669 {"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3670 {"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3671 {"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3672 {"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3673 {"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3674 {"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3675 {"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3676 {"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3677 {"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3678 {"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3679 {"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3680 {"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3681 {"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3682 {"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3683 {"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3684 {"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3685 {"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3686 {"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3687 {"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3688 {"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3689 {"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3690 {"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}},
08d96e0b127e07 Balbir Singh 2017-02-02 3691 {"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3692 {"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3693 {"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3694 {"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3695 {"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3696 {"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}},
08d96e0b127e07 Balbir Singh 2017-02-02 3697 {"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3698 {"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3699 {"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3700 {"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3701 {"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3702 {"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3703 {"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3704 {"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3705 {"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3706 {"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3707 {"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3708 {"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3709 {"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3710 {"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3711 {"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3712 {"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3713 {"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3714 {"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3715 {"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3716 {"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3717 {"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3718 {"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3719 {"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3720 {"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3721 {"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3722 {"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3723 {"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3724 {"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3725 {"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3726 {"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}},
08d96e0b127e07 Balbir Singh 2017-02-02 3727 {"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3728 {"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3729 {"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3730 {"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3731 {"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3732 {"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3733 {"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3734 {"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3735 {"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3736 {"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3737 {"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3738 {"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3739 {"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3740 {"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3741 {"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3742 {"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3743 {"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3744 {"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3745 {"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3746 {"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3747 {"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3748 {"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3749 {"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}},
08d96e0b127e07 Balbir Singh 2017-02-02 3750 {"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3751 {"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3752 {"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3753 {"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3754 {"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3755 {"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3756 {"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3757 {"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3758 {"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3759 {"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3760 {"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3761 {"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3762 {"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3763 {"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3764 {"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3765 {"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3766 {"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3767 {"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3768 {"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3769 {"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3770 {"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3771 {"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3772 {"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3773 {"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3774 {"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3775 {"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3776 {"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3777 {"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3778 {"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3779 {"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3780 {"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3781 {"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3782 {"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3783 {"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3784 {"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3785 {"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3786 {"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3787 {"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3788 {"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3789 {"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3790 {"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3791 {"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3792 {"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3793 {"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3794 {"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3795 {"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, PPC476, {URT, URA, URB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3796 {"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3797 {"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3798 {"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3799 {"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3800 {"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}},
08d96e0b127e07 Balbir Singh 2017-02-02 3801
:::::: The code at line 3500 was first introduced by commit
:::::: 08d96e0b127e07c3b90e10f1939caf70b456793e powerpc/xmon: Apply binutils changes to upgrade disassembly
:::::: TO: Balbir Singh <bsingharora@gmail.com>
:::::: CC: Michael Ellerman <mpe@ellerman.id.au>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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