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From: Ramalingam C <ramalingam.c@intel.com>
To: "Shankar, Uma" <uma.shankar@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"seanpaul@chromium.org" <seanpaul@chromium.org>,
	"daniel@ffwll.ch" <daniel@ffwll.ch>,
	"chris@chris-wilson.co.uk" <chris@chris-wilson.co.uk>,
	"jani.nikula@linux.intel.com" <jani.nikula@linux.intel.com>,
	"Winkler, Tomas" <tomas.winkler@intel.com>,
	"Usyskin, Alexander" <alexander.usyskin@intel.com>
Cc: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>
Subject: Re: [PATCH v3 37/40] drm/i915: Implement the HDCP2.2 support for DP
Date: Mon, 21 May 2018 14:19:18 +0530	[thread overview]
Message-ID: <12e6dc0b-87ee-1a26-4e11-262ee212ba80@intel.com> (raw)
In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F7F1F5EDB@BGSMSX104.gar.corp.intel.com>



On Friday 18 May 2018 09:45 PM, Shankar, Uma wrote:
>
>> -----Original Message-----
>> From: dri-devel [mailto:dri-devel-bounces@lists.freedesktop.org] On Behalf Of
>> Ramalingam C
>> Sent: Tuesday, April 3, 2018 7:28 PM
>> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
>> seanpaul@chromium.org; daniel@ffwll.ch; chris@chris-wilson.co.uk;
>> jani.nikula@linux.intel.com; Winkler, Tomas <tomas.winkler@intel.com>;
>> Usyskin, Alexander <alexander.usyskin@intel.com>
>> Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>> Subject: [PATCH v3 37/40] drm/i915: Implement the HDCP2.2 support for DP
>>
>> Implements the DP adaptation specific HDCP2.2 functions.
>>
>> These functions perform the DPCD read and write for communicating the
>> HDCP2.2 auth message back and forth.
>>
>> Note: Chris Wilson suggested alternate method for waiting for CP_IRQ, than
>> completions concept. WIP to understand and implement that, if needed. Just to
>> unblock the review of other changes, v2 still continues with completions.
>>
>> v2:
>>   wait for cp_irq is merged with this patch. Rebased.
>> v3:
>>   wait_queue is used for wait for cp_irq [Chris Wilson]
>>
>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c   | 352
>> ++++++++++++++++++++++++++++++++++++++
>> drivers/gpu/drm/i915/intel_drv.h  |   7 +
>> drivers/gpu/drm/i915/intel_hdcp.c |   5 +
>> 3 files changed, 364 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index f92c0326fff5..e5cb54ceda38 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -31,6 +31,7 @@
>> #include <linux/types.h>
>> #include <linux/notifier.h>
>> #include <linux/reboot.h>
>> +#include <linux/mei_hdcp.h>
>> #include <asm/byteorder.h>
>> #include <drm/drmP.h>
>> #include <drm/drm_atomic_helper.h>
>> @@ -5070,6 +5071,28 @@ void intel_dp_encoder_suspend(struct intel_encoder
>> *intel_encoder)
>> 	pps_unlock(intel_dp);
>> }
>>
>> +static int intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp,
>> +					 int timeout)
>> +{
>> +	long ret;
>> +
>> +	/* Reinit */
>> +	atomic_set(&hdcp->cp_irq_recved, 0);
> I feel "received" would sound better instead of the current abbreviation.
>
>> +
>> +#define C (atomic_read(&hdcp->cp_irq_recved) > 0)
>> +	ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
>> +					       msecs_to_jiffies(timeout));
>> +
>> +	if (ret > 0) {
>> +		atomic_set(&hdcp->cp_irq_recved, 0);
>> +		return 0;
>> +	} else if (!ret) {
>> +		return -ETIMEDOUT;
>> +	}
>> +	return (int)ret;
>> +}
>> +
>> +
>> static
>> int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
>> 				u8 *an)
>> @@ -5288,6 +5311,329 @@ int intel_dp_hdcp_capable(struct intel_digital_port
>> *intel_dig_port,
>> 	return 0;
>> }
>>
>> +static inline
> Don’t make this inline.
>
>> +int intel_dpcd_offset_for_hdcp2_msgid(uint8_t byte, unsigned int
>> +*offset) {
>> +	switch (byte) {
>> +	case HDCP_2_2_AKE_INIT:
>> +		*offset = DP_HDCP_2_2_AKE_INIT_OFFSET;
>> +		break;
>> +	case HDCP_2_2_AKE_SEND_CERT:
>> +		*offset = DP_HDCP_2_2_AKE_SEND_CERT_OFFSET;
>> +		break;
>> +	case HDCP_2_2_AKE_NO_STORED_KM:
>> +		*offset = DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET;
>> +		break;
>> +	case HDCP_2_2_AKE_STORED_KM:
>> +		*offset = DP_HDCP_2_2_AKE_STORED_KM_OFFSET;
>> +		break;
>> +	case HDCP_2_2_AKE_SEND_HPRIME:
>> +		*offset = DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET;
>> +		break;
>> +	case HDCP_2_2_AKE_SEND_PARING_INFO:
>> +		*offset = DP_HDCP_2_2_AKE_SEND_PARING_INFO_OFFSET;
>> +		break;
>> +	case HDCP_2_2_LC_INIT:
>> +		*offset = DP_HDCP_2_2_LC_INIT_OFFSET;
>> +		break;
>> +	case HDCP_2_2_LC_SEND_LPRIME:
>> +		*offset = DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET;
>> +		break;
>> +	case HDCP_2_2_SKE_SEND_EKS:
>> +		*offset = DP_HDCP_2_2_SKE_SEND_EKS_OFFSET;
>> +		break;
>> +	case HDCP_2_2_REP_SEND_RECVID_LIST:
>> +		*offset = DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET;
>> +		break;
>> +	case HDCP_2_2_REP_SEND_ACK:
>> +		*offset = DP_HDCP_2_2_REP_SEND_ACK_OFFSET;
>> +		break;
>> +	case HDCP_2_2_REP_STREAM_MANAGE:
>> +		*offset = DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET;
>> +		break;
>> +	case HDCP_2_2_REP_STREAM_READY:
>> +		*offset = DP_HDCP_2_2_REP_STREAM_READY_OFFSET;
>> +		break;
>> +	case HDCP_2_2_ERRATA_DP_STREAM_TYPE:
>> +		*offset = DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET;
>> +		break;
>> +	default:
>> +		DRM_ERROR("Unrecognized Msg ID\n");
>> +		return -EINVAL;
>> +	}
> Leave a blank line.
>
>> +	return 0;
>> +}
>> +
>> +static inline
>> +int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
>> +				  uint8_t *rx_status)
>> +{
>> +	ssize_t ret;
>> +
>> +	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
>> +			       DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
>> +			       HDCP_2_2_DP_RXSTATUS_LEN);
>> +	if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
>> +		DRM_ERROR("Read bstatus from DP/AUX failed (%ld)\n", ret);
>> +		return ret >= 0 ? -EIO : ret;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static inline
>> +int intel_dp_hdcp2_timeout_for_msg(uint8_t msg_id, bool paired) {
>> +	int timeout = -EINVAL;
> Initializing with -EINVAL doesn't sound right. Make it more logical.
Moved the assignment under the default.
>
>> +
>> +	switch (msg_id) {
>> +	case HDCP_2_2_AKE_SEND_CERT:
>> +		timeout = HDCP_2_2_CERT_TIMEOUT;
>> +		break;
>> +	case HDCP_2_2_AKE_SEND_HPRIME:
>> +		if (paired)
>> +			timeout = HDCP_2_2_HPRIME_PAIRED_TIMEOUT;
>> +		else
>> +			timeout = HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT;
>> +		break;
>> +	case HDCP_2_2_AKE_SEND_PARING_INFO:
>> +		timeout = HDCP_2_2_PAIRING_TIMEOUT;
>> +		break;
>> +	case HDCP_2_2_LC_SEND_LPRIME:
>> +		timeout = HDCP_2_2_DP_LPRIME_TIMEOUT;
>> +		break;
>> +	case HDCP_2_2_REP_SEND_RECVID_LIST:
>> +		timeout = HDCP_2_2_RECVID_LIST_TIMEOUT;
>> +		break;
>> +	case HDCP_2_2_REP_STREAM_READY:
>> +		timeout = HDCP_2_2_STREAM_READY_TIMEOUT;
>> +		break;
>> +	default:
>> +		DRM_ERROR("Unsupported msg_id: %d\n", (int)msg_id);
>> +	}
> Leave a blank line.
>
>> +	return timeout;
>> +}
>> +
>> +static inline
> Don't make it inline.
>
>> +int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port,
>> +				  uint8_t msg_id, bool *msg_ready)
>> +{
>> +	uint8_t rx_status;
>> +	int ret;
>> +
>> +	*msg_ready = false;
>> +	ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	switch (msg_id) {
>> +	case HDCP_2_2_AKE_SEND_HPRIME:
>> +		if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
>> +			*msg_ready = true;
>> +		break;
>> +	case HDCP_2_2_AKE_SEND_PARING_INFO:
>> +		if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
>> +			*msg_ready = true;
>> +		break;
>> +	case HDCP_2_2_REP_SEND_RECVID_LIST:
>> +		if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
>> +			*msg_ready = true;
>> +		break;
>> +	default:
>> +		DRM_DEBUG_KMS("Unidentified msg_id: %d\n", (int)msg_id);
>> +		return -EINVAL;
>> +	}
>> +	return 0;
>> +}
>> +
>> +
>> +static inline ssize_t
> Don’t make it inline.
>
>> +intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
>> +			    uint8_t msg_id)
>> +{
>> +	struct intel_dp *dp = &intel_dig_port->dp;
>> +	struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
>> +	int ret, timeout;
>> +	bool msg_ready = false;
>> +
>> +	timeout = intel_dp_hdcp2_timeout_for_msg(msg_id, hdcp->is_paired);
>> +	switch (msg_id) {
>> +
>> +	/*
>> +	 * There is no way to detect the CERT, LPRIME and STREAM_READY
>> +	 * availability. So Wait for timeout and read the msg.
>> +	 */
>> +	case HDCP_2_2_AKE_SEND_CERT:
>> +	case HDCP_2_2_LC_SEND_LPRIME:
>> +	case HDCP_2_2_REP_STREAM_READY:
>> +		mdelay(timeout);
>> +		ret = 0;
>> +		break;
>> +	case HDCP_2_2_AKE_SEND_HPRIME:
>> +	case HDCP_2_2_AKE_SEND_PARING_INFO:
>> +	case HDCP_2_2_REP_SEND_RECVID_LIST:
>> +		intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
>> +		ret = hdcp2_detect_msg_availability(intel_dig_port, msg_id,
>> +						    &msg_ready);
>> +		if (!msg_ready)
>> +			ret = -ETIMEDOUT;
>> +		break;
>> +	default:
>> +		DRM_DEBUG_KMS("Unidentified msg_id: %d\n", (int)msg_id);
>> +		return -EINVAL;
>> +	}
> Leave a blank line here.
>
>> +	if (ret)
>> +		DRM_ERROR("msg_id %d, ret %d, timeout(mSec): %d\n",
>> msg_id, ret,
>> +			  timeout);
>> +	return ret;
>> +}
>> +
>> +static
>> +int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
>> +			     void *buf, size_t size)
>> +{
>> +	unsigned int offset;
>> +	uint8_t *byte = buf;
>> +	ssize_t ret, bytes_to_write, len;
>> +
>> +	if (intel_dpcd_offset_for_hdcp2_msgid(*byte, &offset) < 0)
>> +		return -EINVAL;
>> +
>> +	/* No msg_id in DP HDCP2.2 msgs */
>> +	bytes_to_write = size - 1;
>> +	byte++;
>> +
>> +	while (bytes_to_write) {
>> +		len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
>> +				DP_AUX_MAX_PAYLOAD_BYTES :
>> bytes_to_write;
>> +
>> +		ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, offset,
>> +					(void *)byte, len);
>> +		if (ret < 0)
>> +			return ret;
>> +
>> +		bytes_to_write -= ret;
>> +		byte += ret;
>> +		offset += ret;
>> +	}
> Leave a blank line.
>
>> +	return size;
>> +}
>> +
>> +static
>> +int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
>> +			    uint8_t msg_id, void *buf, size_t size) {
>> +	unsigned int offset, dev_cnt;
>> +	uint8_t *byte = buf;
>> +	uint8_t rx_info[HDCP_2_2_RXINFO_LEN];
>> +	ssize_t ret, bytes_to_recv, len;
>> +
>> +	if (intel_dpcd_offset_for_hdcp2_msgid(msg_id, &offset) < 0)
>> +		return -EINVAL;
>> +
>> +	ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, msg_id);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	/* Finding the ReceiverID List size */
>> +	if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
>> +		ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
>> +				       DP_HDCP_2_2_REG_RXINFO_OFFSET,
>> +				       (void *)rx_info, HDCP_2_2_RXINFO_LEN);
>> +		if (ret != HDCP_2_2_RXINFO_LEN)
>> +			return ret >= 0 ? -EIO : ret;
>> +
>> +		dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
>> +			   HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
>> +
>> +		if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
>> +			dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
>> +
>> +		size = sizeof(struct hdcp2_rep_send_receiverid_list) -
>> +		       HDCP_2_2_RECEIVER_IDS_MAX_LEN +
>> +		       (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
>> +	}
>> +
>> +	bytes_to_recv = size - 1;
>> +
>> +	/* To skip the msg_id, as msgs in DP adaptation has no msg_id */
>> +	byte++;
>> +
>> +	while (bytes_to_recv) {
>> +		len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
>> +		      DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
>> +
>> +		ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset,
>> +				       (void *)byte, len);
>> +		if (ret < 0) {
>> +			DRM_DEBUG_KMS("msg_id %d, ret %d\n", msg_id,
>> (int)ret);
>> +			return ret;
>> +		}
>> +
>> +		bytes_to_recv -= ret;
>> +		byte += ret;
>> +		offset += ret;
>> +	}
>> +	byte = buf;
>> +	*byte = msg_id;
>> +
>> +	return size;
>> +}
>> +
>> +static
> This can be made inline.
Since this is the function for the hdcp_shim ptr, I am not sure that 
making inline will be helpful.
So I am not making it as inline.

Ram
>
>> +int intel_dp_hdcp2_config_stream_type(struct intel_digital_port
>> *intel_dig_port,
>> +				      void *buf, size_t size)
>> +{
>> +	return intel_dp_hdcp2_write_msg(intel_dig_port, buf, size); }
>> +
>> +static
>> +int intel_dp_hdcp2_check_link(struct intel_digital_port
>> +*intel_dig_port) {
>> +	uint8_t rx_status;
>> +	int ret;
>> +
>> +	ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status);
>> +	if (ret)
>> +		return ret;
>> +
>> +	if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
>> +		ret = DRM_HDCP_REAUTH_REQUEST;
>> +	else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
>> +		ret = DRM_HDCP_LINK_INTEGRITY_FAILURE;
>> +	else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
>> +		ret = DRM_HDCP_TOPOLOGY_CHANGE;
>> +
>> +	return ret;
>> +}
>> +
>> +static
>> +int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port,
>> +			   bool *capable)
>> +{
>> +	uint8_t rx_caps[3];
>> +	int ret;
>> +
>> +	*capable = false;
>> +	ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
>> +			       DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
>> +			       rx_caps, HDCP_2_2_RXCAPS_LEN);
>> +	if (ret != HDCP_2_2_RXCAPS_LEN)
>> +		return ret >= 0 ? -EIO : ret;
>> +
>> +	if (rx_caps[0] == HDCP_2_2_RXCAPS_VERSION_VAL &&
>> +	    HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
>> +		*capable = true;
>> +
>> +	return 0;
>> +}
>> +
>> +static
>> +enum hdcp_protocol intel_dp_hdcp2_protocol(void) {
>> +	return HDCP_PROTOCOL_DP;
>> +}
>> +
>> static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
>> 	.write_an_aksv = intel_dp_hdcp_write_an_aksv,
>> 	.read_bksv = intel_dp_hdcp_read_bksv,
>> @@ -5300,6 +5646,12 @@ static const struct intel_hdcp_shim
>> intel_dp_hdcp_shim = {
>> 	.toggle_signalling = intel_dp_hdcp_toggle_signalling,
>> 	.check_link = intel_dp_hdcp_check_link,
>> 	.hdcp_capable = intel_dp_hdcp_capable,
>> +	.write_2_2_msg = intel_dp_hdcp2_write_msg,
>> +	.read_2_2_msg = intel_dp_hdcp2_read_msg,
>> +	.config_stream_type = intel_dp_hdcp2_config_stream_type,
>> +	.check_2_2_link = intel_dp_hdcp2_check_link,
>> +	.hdcp_2_2_capable = intel_dp_hdcp2_capable,
>> +	.hdcp_protocol = intel_dp_hdcp2_protocol,
>> };
>>
>> static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) diff --git
>> a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 8e60ccd0d368..37f9a0e2ea13 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -444,6 +444,13 @@ struct intel_hdcp {
>> 	struct mei_hdcp_data mei_data;
>> 	struct notifier_block mei_cldev_nb;
>> 	struct delayed_work hdcp2_check_work;
>> +
>> +	/*
>> +	 * Work queue to signal the CP_IRQ. Used for the waiters to read the
>> +	 * available information from HDCP DP sink.
>> +	 */
>> +	wait_queue_head_t cp_irq_queue;
>> +	atomic_t cp_irq_recved;
>> };
>>
>> struct intel_connector {
>> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c
>> b/drivers/gpu/drm/i915/intel_hdcp.c
>> index 8cf0eeb4b3f8..9386b451191e 100644
>> --- a/drivers/gpu/drm/i915/intel_hdcp.c
>> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
>> @@ -788,6 +788,8 @@ int intel_hdcp_init(struct intel_connector *connector,
>> 	if (hdcp2_supported)
>> 		intel_hdcp2_init(connector);
>>
>> +	init_waitqueue_head(&hdcp->cp_irq_queue);
>> +	atomic_set(&hdcp->cp_irq_recved, 0);
> Leave a blank line.
>
>> 	return 0;
>> }
>>
>> @@ -1762,4 +1764,7 @@ void intel_hdcp_handle_cp_irq(struct intel_connector
>> *connector)
>> 		intel_hdcp_check_link(connector);
>> 	else if (intel_hdcp2_in_force(connector))
>> 		intel_hdcp2_check_link(connector);
>> +
>> +	atomic_set(&connector->hdcp.cp_irq_recved, 1);
>> +	wake_up_all(&connector->hdcp.cp_irq_queue);
>> }
>> --
>> 2.7.4
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel

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  reply	other threads:[~2018-05-21  8:49 UTC|newest]

Thread overview: 130+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-03 13:57 [PATCH v3 00/40] drm/i915: Implement HDCP2.2 Ramalingam C
2018-04-03 13:57 ` [PATCH v3 01/40] drm: hdcp2.2 authentication msg definitions Ramalingam C
2018-05-09 10:01   ` Shankar, Uma
2018-05-14 15:23     ` [Intel-gfx] " Ramalingam C
2018-04-03 13:57 ` [PATCH v3 02/40] drm: HDMI and DP specific HDCP2.2 defines Ramalingam C
2018-05-09 10:06   ` Shankar, Uma
2018-05-14 16:01     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 03/40] mei: bus: whitelist hdcp client Ramalingam C
2018-04-03 13:57 ` [PATCH v3 04/40] misc/mei/hdcp: Client driver for HDCP application Ramalingam C
2018-05-09 10:07   ` Shankar, Uma
2018-04-03 13:57 ` [PATCH v3 05/40] misc/mei/hdcp: Notifier chain for mei cldev state change Ramalingam C
2018-04-03 15:30   ` Daniel Vetter
2018-05-16 14:54     ` Ramalingam C
2018-04-03 20:53   ` kbuild test robot
2018-04-03 23:58   ` [RFC PATCH] misc/mei/hdcp: mei_cldev_state_notify_clients() can be static kbuild test robot
2018-04-04  6:12   ` [PATCH v3 05/40] misc/mei/hdcp: Notifier chain for mei cldev state change Usyskin, Alexander
2018-05-16 13:04     ` Ramalingam C
2018-05-17  5:52       ` Usyskin, Alexander
2018-05-17  6:15         ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 06/40] misc/mei/hdcp: Define ME FW interface for HDCP2.2 Ramalingam C
2018-04-03 13:57 ` [PATCH v3 07/40] linux/mei: Header for mei_hdcp driver interface Ramalingam C
2018-05-09 10:08   ` Shankar, Uma
2018-05-16 15:05     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 08/40] misc/mei/hdcp: Initiate Wired HDCP2.2 Tx Session Ramalingam C
2018-04-03 21:20   ` [Intel-gfx] " kbuild test robot
2018-04-04  6:45   ` Usyskin, Alexander
2018-05-16 15:19     ` Ramalingam C
2018-05-17  5:56       ` Usyskin, Alexander
2018-05-17  6:08         ` Ramalingam C
2018-05-09 10:13   ` Shankar, Uma
2018-05-16 15:26     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 09/40] misc/mei/hdcp: Verify Receiver Cert and prepare km Ramalingam C
2018-04-03 21:44   ` kbuild test robot
2018-04-03 13:57 ` [PATCH v3 10/40] misc/mei/hdcp: Verify H_prime Ramalingam C
2018-04-03 22:12   ` kbuild test robot
2018-05-09 10:16   ` [Intel-gfx] " Shankar, Uma
2018-05-16 15:43     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 11/40] misc/mei/hdcp: Store the HDCP Pairing info Ramalingam C
2018-04-03 22:34   ` kbuild test robot
2018-05-09 10:28   ` Shankar, Uma
2018-05-16 15:53     ` Ramalingam C
2018-05-17  5:59       ` Usyskin, Alexander
2018-05-17  6:03         ` C, Ramalingam
2018-05-17  8:17           ` Jani Nikula
2018-05-21 12:19             ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 12/40] misc/mei/hdcp: Initiate Locality check Ramalingam C
2018-04-03 23:02   ` kbuild test robot
2018-05-09 10:31   ` Shankar, Uma
2018-05-16 16:02     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 13/40] misc/mei/hdcp: Verify L_prime Ramalingam C
2018-05-09 10:36   ` Shankar, Uma
2018-05-16 16:05     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 14/40] misc/mei/hdcp: Prepare Session Key Ramalingam C
2018-05-09 10:59   ` Shankar, Uma
2018-05-16 16:10     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 15/40] misc/mei/hdcp: Repeater topology verifcation and ack Ramalingam C
2018-05-09 11:04   ` Shankar, Uma
2018-05-16 16:32     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 16/40] misc/mei/hdcp: Verify M_prime Ramalingam C
2018-05-09 13:50   ` Shankar, Uma
2018-05-16 16:32     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 17/40] misc/mei/hdcp: Enabling the HDCP authentication Ramalingam C
2018-05-09 13:55   ` Shankar, Uma
2018-05-16 16:40     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 18/40] misc/mei/hdcp: Closing wired HDCP2.2 Tx Session Ramalingam C
2018-05-09 14:02   ` [Intel-gfx] " Shankar, Uma
2018-05-16 16:41     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 19/40] drm/i915: wrapping all hdcp var into intel_hdcp Ramalingam C
2018-05-09 14:11   ` Shankar, Uma
2018-04-03 13:57 ` [PATCH v3 20/40] drm/i915: Define HDCP2.2 related variables Ramalingam C
2018-04-03 20:27   ` kbuild test robot
2018-05-09 14:23   ` Shankar, Uma
2018-04-03 13:57 ` [PATCH v3 21/40] drm/i915: Define Intel HDCP2.2 registers Ramalingam C
2018-05-09 14:59   ` Shankar, Uma
2018-05-17 10:24     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 22/40] drm/i915: Wrappers for mei HDCP2.2 services Ramalingam C
2018-05-09 15:10   ` Shankar, Uma
2018-05-17 10:40     ` [Intel-gfx] " Ramalingam C
2018-04-03 13:57 ` [PATCH v3 23/40] drm/i915: Implement HDCP2.2 receiver authentication Ramalingam C
2018-05-09 15:20   ` Shankar, Uma
2018-04-03 13:57 ` [PATCH v3 24/40] drm/i915: Implement HDCP2.2 repeater authentication Ramalingam C
2018-04-04  1:11   ` kbuild test robot
2018-05-14  9:08   ` Shankar, Uma
2018-05-17 12:38     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 25/40] drm/i915: Enable and Disable HDCP2.2 port encryption Ramalingam C
2018-05-14  9:23   ` Shankar, Uma
2018-05-17 13:01     ` Ramalingam C
2018-05-17 13:14       ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 26/40] drm/i915: Implement HDCP2.2 En/Dis-able Ramalingam C
2018-05-14  9:30   ` Shankar, Uma
2018-05-17 13:16     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 27/40] drm/i915: Implement HDCP2.2 link integrity check Ramalingam C
2018-05-14  9:45   ` Shankar, Uma
2018-05-17 13:31     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 28/40] drm/i915: Handle HDCP2.2 downstream topology change Ramalingam C
2018-05-18 12:09   ` Shankar, Uma
2018-04-03 13:57 ` [PATCH v3 29/40] drm/i915: Pullout the bksv read and validation Ramalingam C
2018-04-03 13:57 ` [PATCH v3 30/40] drm/i915: Initialize HDCP2.2 and its MEI interface Ramalingam C
2018-05-18 12:33   ` [Intel-gfx] " Shankar, Uma
2018-05-18 16:29     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 31/40] drm/i915: Schedule hdcp_check_link in _intel_hdcp_enable Ramalingam C
2018-05-18 12:37   ` [Intel-gfx] " Shankar, Uma
2018-04-03 13:57 ` [PATCH v3 32/40] drm/i915: Enable superior HDCP ver that is capable Ramalingam C
2018-05-18 12:49   ` [Intel-gfx] " Shankar, Uma
2018-05-21  8:29     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 33/40] drm/i915: Enable HDCP1.4 incase of HDCP2.2 failure Ramalingam C
2018-05-18 12:52   ` Shankar, Uma
2018-04-03 13:57 ` [PATCH v3 34/40] drm/i915: hdcp_check_link only on CP_IRQ Ramalingam C
2018-05-18 12:55   ` Shankar, Uma
2018-04-03 13:57 ` [PATCH v3 35/40] drm/i915: Check HDCP 1.4 and 2.2 link " Ramalingam C
2018-05-18 15:59   ` Shankar, Uma
2018-05-21  8:37     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 36/40] drm/i915: Implement gmbus burst read Ramalingam C
2018-04-03 16:40   ` Daniel Vetter
2018-04-05  9:12     ` Jani Nikula
2018-04-05 13:44       ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 37/40] drm/i915: Implement the HDCP2.2 support for DP Ramalingam C
2018-04-03 19:57   ` kbuild test robot
2018-04-03 21:16   ` kbuild test robot
2018-05-18 16:15   ` Shankar, Uma
2018-05-21  8:49     ` Ramalingam C [this message]
2018-04-03 13:57 ` [PATCH v3 38/40] drm/i915: Implement the HDCP2.2 support for HDMI Ramalingam C
2018-05-18 16:29   ` Shankar, Uma
2018-05-21  9:08     ` [Intel-gfx] " Ramalingam C
2018-04-03 13:57 ` [PATCH v3 39/40] drm/i915: Add HDCP2.2 support for DP connectors Ramalingam C
2018-05-18 16:37   ` [Intel-gfx] " Shankar, Uma
2018-05-21  9:14     ` Ramalingam C
2018-04-03 13:57 ` [PATCH v3 40/40] drm/i915: Add HDCP2.2 support for HDMI connectors Ramalingam C
2018-05-18 16:38   ` [Intel-gfx] " Shankar, Uma
2018-04-03 14:26 ` ✗ Fi.CI.BAT: failure for drm/i915: Implement HDCP2.2 (rev3) Patchwork

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