* [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
@ 2011-03-16 1:55 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux, Huang Shijie, linux-mtd, dwmw2, David.Woodhouse
The general-purpose media interface(GPMI) controller is a flexible interface
to up to several NAND flashs.
The Bose Ray-Choudhury Hocquenghem(BCH) module is a hardware ECC accelerator.
With the help of BCH, the GPMI controller can choose to do the hardware ECC or
not.
This driver is based the Shawn Guo's DMA patches for IMX23/IMX28,
please refer to :
http://git.infradead.org/users/vkoul/slave-dma.git/commit/a580b8c5429a624d120cd603e1498bf676e2b4da
add the mtd maillist.
Huang Shijie (7):
ARM: add GPMI support for imx23/imx28
add the common code for GPMI driver
add the database for the NANDs
add GPMI support for imx23
add GPMI support for imx28
dmaengine: change the flags of request_irq()
MTD : add GPMI driver in the config and Makefile
arch/arm/mach-mxs/Kconfig | 2 +
arch/arm/mach-mxs/clock-mx23.c | 3 +
arch/arm/mach-mxs/clock-mx28.c | 3 +
arch/arm/mach-mxs/devices-mx23.h | 3 +
arch/arm/mach-mxs/devices-mx28.h | 3 +
arch/arm/mach-mxs/devices/Kconfig | 3 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-gpmi.c | 144 +++
arch/arm/mach-mxs/include/mach/devices-common.h | 4 +
arch/arm/mach-mxs/include/mach/gpmi-nfc.h | 75 ++
arch/arm/mach-mxs/mach-mx23evk.c | 37 +
arch/arm/mach-mxs/mach-mx28evk.c | 37 +
drivers/dma/mxs-dma.c | 2 +-
drivers/mtd/nand/Kconfig | 10 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/gpmi-nfc/Makefile | 10 +
drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h | 550 +++++++++++
drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h | 557 ++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c | 524 +++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h | 520 +++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h | 416 +++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h | 421 +++++++++
drivers/mtd/nand/gpmi-nfc/hal-common.c | 816 +++++++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-imx23.c | 556 ++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-imx28.c | 503 +++++++++++
drivers/mtd/nand/gpmi-nfc/mil.c | 1104 +++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181 ++++
drivers/mtd/nand/gpmi-nfc/nand_device_info.h | 145 +++
drivers/mtd/nand/gpmi-nfc/rom-common.c | 48 +
drivers/mtd/nand/gpmi-nfc/rom-imx23.c | 300 ++++++
drivers/mtd/nand/gpmi-nfc/rom-imx28.c | 66 ++
31 files changed, 7044 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-gpmi.c
create mode 100644 arch/arm/mach-mxs/include/mach/gpmi-nfc.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/Makefile
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-common.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx23.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx28.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/mil.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-common.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx23.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx28.c
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
@ 2011-03-16 1:55 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel
The general-purpose media interface(GPMI) controller is a flexible interface
to up to several NAND flashs.
The Bose Ray-Choudhury Hocquenghem(BCH) module is a hardware ECC accelerator.
With the help of BCH, the GPMI controller can choose to do the hardware ECC or
not.
This driver is based the Shawn Guo's DMA patches for IMX23/IMX28,
please refer to :
http://git.infradead.org/users/vkoul/slave-dma.git/commit/a580b8c5429a624d120cd603e1498bf676e2b4da
add the mtd maillist.
Huang Shijie (7):
ARM: add GPMI support for imx23/imx28
add the common code for GPMI driver
add the database for the NANDs
add GPMI support for imx23
add GPMI support for imx28
dmaengine: change the flags of request_irq()
MTD : add GPMI driver in the config and Makefile
arch/arm/mach-mxs/Kconfig | 2 +
arch/arm/mach-mxs/clock-mx23.c | 3 +
arch/arm/mach-mxs/clock-mx28.c | 3 +
arch/arm/mach-mxs/devices-mx23.h | 3 +
arch/arm/mach-mxs/devices-mx28.h | 3 +
arch/arm/mach-mxs/devices/Kconfig | 3 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-gpmi.c | 144 +++
arch/arm/mach-mxs/include/mach/devices-common.h | 4 +
arch/arm/mach-mxs/include/mach/gpmi-nfc.h | 75 ++
arch/arm/mach-mxs/mach-mx23evk.c | 37 +
arch/arm/mach-mxs/mach-mx28evk.c | 37 +
drivers/dma/mxs-dma.c | 2 +-
drivers/mtd/nand/Kconfig | 10 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/gpmi-nfc/Makefile | 10 +
drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h | 550 +++++++++++
drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h | 557 ++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c | 524 +++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h | 520 +++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h | 416 +++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h | 421 +++++++++
drivers/mtd/nand/gpmi-nfc/hal-common.c | 816 +++++++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-imx23.c | 556 ++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-imx28.c | 503 +++++++++++
drivers/mtd/nand/gpmi-nfc/mil.c | 1104 +++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181 ++++
drivers/mtd/nand/gpmi-nfc/nand_device_info.h | 145 +++
drivers/mtd/nand/gpmi-nfc/rom-common.c | 48 +
drivers/mtd/nand/gpmi-nfc/rom-imx23.c | 300 ++++++
drivers/mtd/nand/gpmi-nfc/rom-imx28.c | 66 ++
31 files changed, 7044 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-gpmi.c
create mode 100644 arch/arm/mach-mxs/include/mach/gpmi-nfc.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/Makefile
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-common.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx23.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx28.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/mil.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-common.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx23.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx28.c
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 1/7] ARM: add GPMI support for imx23/imx28
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-16 1:55 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux, Huang Shijie, linux-mtd, dwmw2, David.Woodhouse
add the clock and iomux initialization for GPMI in the imx23 and imx28.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
arch/arm/mach-mxs/Kconfig | 2 +
arch/arm/mach-mxs/clock-mx23.c | 3 +
arch/arm/mach-mxs/clock-mx28.c | 3 +
arch/arm/mach-mxs/devices-mx23.h | 3 +
arch/arm/mach-mxs/devices-mx28.h | 3 +
arch/arm/mach-mxs/devices/Kconfig | 3 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-gpmi.c | 144 +++++++++++++++++++++++
arch/arm/mach-mxs/include/mach/devices-common.h | 4 +
arch/arm/mach-mxs/include/mach/gpmi-nfc.h | 75 ++++++++++++
arch/arm/mach-mxs/mach-mx23evk.c | 37 ++++++
arch/arm/mach-mxs/mach-mx28evk.c | 37 ++++++
12 files changed, 315 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-gpmi.c
create mode 100644 arch/arm/mach-mxs/include/mach/gpmi-nfc.h
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4f6f174..8ab0fcb 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -22,6 +22,7 @@ config MACH_MX23EVK
select SOC_IMX23
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_AUART
+ select MXS_HAVE_PLATFORM_GPMI
select MXS_HAVE_PLATFORM_MXSFB
default y
help
@@ -33,6 +34,7 @@ config MACH_MX28EVK
select SOC_IMX28
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_AUART
+ select MXS_HAVE_PLATFORM_GPMI
select MXS_HAVE_PLATFORM_FEC
select MXS_HAVE_PLATFORM_FLEXCAN
select MXS_HAVE_PLATFORM_MXSFB
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index d133c7f..c8ecc1b 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -29,6 +29,7 @@
#include <mach/mx23.h>
#include <mach/common.h>
#include <mach/clock.h>
+#include <mach/gpmi-nfc.h>
#include "regs-clkctrl-mx23.h"
@@ -442,6 +443,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
/* for amba-pl011 driver */
_REGISTER_CLOCK("duart", NULL, uart_clk)
+ _REGISTER_CLOCK(GPMI_NFC_DRIVER_NAME, GPMI_NFC_CLOCK_NAME, gpmi_clk)
_REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
_REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
@@ -533,6 +535,7 @@ int __init mx23_clocks_init(void)
clk_enable(&xbus_clk);
clk_enable(&emi_clk);
clk_enable(&uart_clk);
+ clk_enable(&gpmi_clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5e489a2..5123e32 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -29,6 +29,7 @@
#include <mach/mx28.h>
#include <mach/common.h>
#include <mach/clock.h>
+#include <mach/gpmi-nfc.h>
#include "regs-clkctrl-mx28.h"
@@ -607,6 +608,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
/* for amba-pl011 driver */
_REGISTER_CLOCK("duart", NULL, uart_clk)
+ _REGISTER_CLOCK(GPMI_NFC_DRIVER_NAME, GPMI_NFC_CLOCK_NAME, gpmi_clk)
_REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
_REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
_REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
@@ -749,6 +751,7 @@ int __init mx28_clocks_init(void)
clk_enable(&xbus_clk);
clk_enable(&emi_clk);
clk_enable(&uart_clk);
+ clk_enable(&gpmi_clk);
clk_set_parent(&lcdif_clk, &ref_pix_clk);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index c7e14f4..349fb1d 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -16,6 +16,9 @@ extern const struct amba_device mx23_duart_device __initconst;
#define mx23_add_duart() \
mxs_add_duart(&mx23_duart_device)
+extern const struct gpmi_nfc_platform_data gpmi_platform_data_imx23 __initconst;
+#define mx23_add_gpmi() mxs_add_gpmi(&gpmi_platform_data_imx23)
+
extern const struct mxs_auart_data mx23_auart_data[] __initconst;
#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id])
#define mx23_add_auart0() mx23_add_auart(0)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 9d08555..ed6427b 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -16,6 +16,9 @@ extern const struct amba_device mx28_duart_device __initconst;
#define mx28_add_duart() \
mxs_add_duart(&mx28_duart_device)
+extern const struct gpmi_nfc_platform_data gpmi_platform_data_imx28 __initconst;
+#define mx28_add_gpmi() mxs_add_gpmi(&gpmi_platform_data_imx28)
+
extern const struct mxs_auart_data mx28_auart_data[] __initconst;
#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id])
#define mx28_add_auart0() mx28_add_auart(0)
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 1451ad0..81e99ce 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -5,6 +5,9 @@ config MXS_HAVE_AMBA_DUART
config MXS_HAVE_PLATFORM_AUART
bool
+config MXS_HAVE_PLATFORM_GPMI
+ bool
+
config MXS_HAVE_PLATFORM_FEC
bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index 0d9bea3..8a7c2c8 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
obj-y += platform-dma.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI) += platform-gpmi.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi.c b/arch/arm/mach-mxs/devices/platform-gpmi.c
new file mode 100644
index 0000000..038226b
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-gpmi.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/gpmi-nfc.h>
+#include <mach/devices-common.h>
+
+#ifdef CONFIG_SOC_IMX23
+const struct gpmi_nfc_platform_data gpmi_platform_data_imx23 __initconst = {
+ .chip_version = CHIP_VERSION_IMX23,
+ .clock_name = GPMI_NFC_CLOCK_NAME,
+ .min_prop_delay_in_ns = 5,
+ .max_prop_delay_in_ns = 9,
+ .max_chip_count = 1,
+ .boot_area_size_in_bytes = 20 * SZ_1M,
+};
+
+const struct resource res_imx23[] __initconst = {
+ { /* GPMI */
+ .start = MX23_GPMI_BASE_ADDR,
+ .end = MX23_GPMI_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX23_INT_GPMI_ATTENTION,
+ .end = MX23_INT_GPMI_ATTENTION,
+ .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* BCH */
+ .start = MX23_BCH_BASE_ADDR,
+ .end = MX23_BCH_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX23_INT_BCH,
+ .end = MX23_INT_BCH,
+ .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* DMA */
+ .start = MX23_DMA_GPMI0,
+ .end = MX23_DMA_GPMI3,
+ .name = GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ .flags = IORESOURCE_DMA,
+ }, {
+ .start = MX23_INT_GPMI_DMA,
+ .end = MX23_INT_GPMI_DMA,
+ .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+const struct gpmi_nfc_platform_data gpmi_platform_data_imx28 __initconst = {
+ .chip_version = CHIP_VERSION_IMX28,
+ .clock_name = GPMI_NFC_CLOCK_NAME,
+ .min_prop_delay_in_ns = 5,
+ .max_prop_delay_in_ns = 9,
+ .max_chip_count = 1,
+ .boot_area_size_in_bytes = 20 * SZ_1M,
+};
+
+const struct resource res_imx28[] __initconst = {
+ { /* GPMI */
+ .start = MX28_GPMI_BASE_ADDR,
+ .end = MX28_GPMI_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX28_INT_GPMI,
+ .end = MX28_INT_GPMI,
+ .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* BCH */
+ .start = MX28_BCH_BASE_ADDR,
+ .end = MX28_BCH_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX28_INT_BCH,
+ .end = MX28_INT_BCH,
+ .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* DMA */
+ .start = MX28_DMA_GPMI0,
+ .end = MX28_DMA_GPMI7,
+ .name = GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ .flags = IORESOURCE_DMA,
+ }, {
+ .start = MX28_INT_GPMI_DMA,
+ .end = MX28_INT_GPMI_DMA,
+ .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+#endif
+
+static struct resource *__init get_res(int *res_size)
+{
+#ifdef CONFIG_SOC_IMX23
+ if (cpu_is_mx23()) {
+ *res_size = ARRAY_SIZE(res_imx23);
+ return (struct resource *)res_imx23;
+ }
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+ if (cpu_is_mx28()) {
+ *res_size = ARRAY_SIZE(res_imx28);
+ return (struct resource *)res_imx28;
+ }
+#endif
+ BUG();
+ return NULL;
+}
+
+struct platform_device *__init
+mxs_add_gpmi(const struct gpmi_nfc_platform_data *data)
+{
+ struct resource *res;
+ int res_size;
+
+ res = get_res(&res_size);
+
+ return mxs_add_platform_device_dmamask(GPMI_NFC_DRIVER_NAME, -1,
+ res, res_size,
+ data, sizeof(*data), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 71f2448..1f05503 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -30,6 +30,10 @@ int __init mxs_add_amba_device(const struct amba_device *dev);
/* duart */
int __init mxs_add_duart(const struct amba_device *dev);
+/* GPMI */
+#include <mach/gpmi-nfc.h>
+struct platform_device *__init mxs_add_gpmi(
+ const struct gpmi_nfc_platform_data *data);
/* auart */
struct mxs_auart_data {
int id;
diff --git a/arch/arm/mach-mxs/include/mach/gpmi-nfc.h b/arch/arm/mach-mxs/include/mach/gpmi-nfc.h
new file mode 100644
index 0000000..2f2d663
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/gpmi-nfc.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __INCLUDE_LINUX_DEVICE_H
+#define __INCLUDE_LINUX_DEVICE_H
+
+#define GPMI_NFC_DRIVER_NAME "gpmi-nfc"
+#define GPMI_NFC_CLOCK_NAME "gpmi-clock"
+
+/* Resource names for the GPMI NFC driver. */
+#define GPMI_NFC_GPMI_REGS_ADDR_RES_NAME "GPMI NFC GPMI Registers"
+#define GPMI_NFC_GPMI_INTERRUPT_RES_NAME "GPMI NFC GPMI Interrupt"
+#define GPMI_NFC_BCH_REGS_ADDR_RES_NAME "GPMI NFC BCH Registers"
+#define GPMI_NFC_BCH_INTERRUPT_RES_NAME "GPMI NFC BCH Interrupt"
+#define GPMI_NFC_DMA_CHANNELS_RES_NAME "GPMI NFC DMA Channels"
+#define GPMI_NFC_DMA_INTERRUPT_RES_NAME "GPMI NFC DMA Interrupt"
+
+/**
+ * struct gpmi_nfc_platform_data - GPMI NFC driver platform data.
+ *
+ * This structure communicates platform-specific information to the GPMI NFC
+ * driver that can't be expressed as resources.
+ *
+ * @chip_version: The version of the hardware.
+ * @clock_name: The name of the clock that drives the NFC.
+ * @min_prop_delay_in_ns: Minimum propagation delay of GPMI signals to and
+ * from the NAND Flash device, in nanoseconds.
+ * @max_prop_delay_in_ns: Maximum propagation delay of GPMI signals to and
+ * from the NAND Flash device, in nanoseconds.
+ * @max_chip_count: The maximum number of chips for which the driver
+ * should configure the hardware. This value most
+ * likely reflects the number of pins that are
+ * connected to a NAND Flash device. If this is
+ * greater than the SoC hardware can support, the
+ * driver will print a message and fail to initialize.
+ * @boot_area_size_in_bytes: The amount of space reserved for each boot area.
+ * Note that some Boot ROMs call for multiple boot
+ * areas. If this value is zero, the driver will not
+ * construct special partitions for boot areas.
+ */
+struct gpmi_nfc_platform_data {
+ unsigned int chip_version;
+
+ /* SoC hardware information. */
+ char *clock_name;
+
+ /* NAND Flash information. */
+ unsigned int min_prop_delay_in_ns;
+ unsigned int max_prop_delay_in_ns;
+ unsigned int max_chip_count;
+
+ /* boot area */
+ uint32_t boot_area_size_in_bytes;
+};
+
+enum {
+ CHIP_VERSION_IMX23 = 0,
+ CHIP_VERSION_IMX28,
+};
+#endif
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index a66994f..db715f9 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -34,6 +34,42 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = {
MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+ /* gpmi */
+ MX23_PAD_GPMI_D00__GPMI_D00 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D01__GPMI_D01 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D02__GPMI_D02 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D03__GPMI_D03 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D04__GPMI_D04 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D05__GPMI_D05 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D06__GPMI_D06 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D07__GPMI_D07 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_CLE__GPMI_CLE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_ALE__GPMI_ALE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_WPN__GPMI_WPN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_WRN__GPMI_WRN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_RDY0__GPMI_RDY0 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_RDY1__GPMI_RDY1 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_CE0N__GPMI_CE0N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_CE1N__GPMI_CE1N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
/* auart */
MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
@@ -108,6 +144,7 @@ static void __init mx23evk_init(void)
mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
mx23_add_duart();
+ mx23_add_gpmi();
mx23_add_auart0();
ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 08002d0..cf8ddcb 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -39,6 +39,42 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+ /* gpmi */
+ MX28_PAD_GPMI_D00__GPMI_D0 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D01__GPMI_D1 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D02__GPMI_D2 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D03__GPMI_D3 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D04__GPMI_D4 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D05__GPMI_D5 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D06__GPMI_D6 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D07__GPMI_D7 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_CE1N__GPMI_CE1N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RDY1__GPMI_READY1 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_WRN__GPMI_WRN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_ALE__GPMI_ALE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_CLE__GPMI_CLE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
/* auart0 */
MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
@@ -265,6 +301,7 @@ static void __init mx28evk_init(void)
mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
mx28_add_duart();
+ mx28_add_gpmi();
mx28_add_auart0();
mx28_add_auart3();
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 1/7] ARM: add GPMI support for imx23/imx28
@ 2011-03-16 1:55 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel
add the clock and iomux initialization for GPMI in the imx23 and imx28.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
arch/arm/mach-mxs/Kconfig | 2 +
arch/arm/mach-mxs/clock-mx23.c | 3 +
arch/arm/mach-mxs/clock-mx28.c | 3 +
arch/arm/mach-mxs/devices-mx23.h | 3 +
arch/arm/mach-mxs/devices-mx28.h | 3 +
arch/arm/mach-mxs/devices/Kconfig | 3 +
arch/arm/mach-mxs/devices/Makefile | 1 +
arch/arm/mach-mxs/devices/platform-gpmi.c | 144 +++++++++++++++++++++++
arch/arm/mach-mxs/include/mach/devices-common.h | 4 +
arch/arm/mach-mxs/include/mach/gpmi-nfc.h | 75 ++++++++++++
arch/arm/mach-mxs/mach-mx23evk.c | 37 ++++++
arch/arm/mach-mxs/mach-mx28evk.c | 37 ++++++
12 files changed, 315 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-mxs/devices/platform-gpmi.c
create mode 100644 arch/arm/mach-mxs/include/mach/gpmi-nfc.h
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4f6f174..8ab0fcb 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -22,6 +22,7 @@ config MACH_MX23EVK
select SOC_IMX23
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_AUART
+ select MXS_HAVE_PLATFORM_GPMI
select MXS_HAVE_PLATFORM_MXSFB
default y
help
@@ -33,6 +34,7 @@ config MACH_MX28EVK
select SOC_IMX28
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_AUART
+ select MXS_HAVE_PLATFORM_GPMI
select MXS_HAVE_PLATFORM_FEC
select MXS_HAVE_PLATFORM_FLEXCAN
select MXS_HAVE_PLATFORM_MXSFB
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index d133c7f..c8ecc1b 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -29,6 +29,7 @@
#include <mach/mx23.h>
#include <mach/common.h>
#include <mach/clock.h>
+#include <mach/gpmi-nfc.h>
#include "regs-clkctrl-mx23.h"
@@ -442,6 +443,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
/* for amba-pl011 driver */
_REGISTER_CLOCK("duart", NULL, uart_clk)
+ _REGISTER_CLOCK(GPMI_NFC_DRIVER_NAME, GPMI_NFC_CLOCK_NAME, gpmi_clk)
_REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
_REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
@@ -533,6 +535,7 @@ int __init mx23_clocks_init(void)
clk_enable(&xbus_clk);
clk_enable(&emi_clk);
clk_enable(&uart_clk);
+ clk_enable(&gpmi_clk);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 5e489a2..5123e32 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -29,6 +29,7 @@
#include <mach/mx28.h>
#include <mach/common.h>
#include <mach/clock.h>
+#include <mach/gpmi-nfc.h>
#include "regs-clkctrl-mx28.h"
@@ -607,6 +608,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
/* for amba-pl011 driver */
_REGISTER_CLOCK("duart", NULL, uart_clk)
+ _REGISTER_CLOCK(GPMI_NFC_DRIVER_NAME, GPMI_NFC_CLOCK_NAME, gpmi_clk)
_REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
_REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
_REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
@@ -749,6 +751,7 @@ int __init mx28_clocks_init(void)
clk_enable(&xbus_clk);
clk_enable(&emi_clk);
clk_enable(&uart_clk);
+ clk_enable(&gpmi_clk);
clk_set_parent(&lcdif_clk, &ref_pix_clk);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index c7e14f4..349fb1d 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -16,6 +16,9 @@ extern const struct amba_device mx23_duart_device __initconst;
#define mx23_add_duart() \
mxs_add_duart(&mx23_duart_device)
+extern const struct gpmi_nfc_platform_data gpmi_platform_data_imx23 __initconst;
+#define mx23_add_gpmi() mxs_add_gpmi(&gpmi_platform_data_imx23)
+
extern const struct mxs_auart_data mx23_auart_data[] __initconst;
#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id])
#define mx23_add_auart0() mx23_add_auart(0)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 9d08555..ed6427b 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -16,6 +16,9 @@ extern const struct amba_device mx28_duart_device __initconst;
#define mx28_add_duart() \
mxs_add_duart(&mx28_duart_device)
+extern const struct gpmi_nfc_platform_data gpmi_platform_data_imx28 __initconst;
+#define mx28_add_gpmi() mxs_add_gpmi(&gpmi_platform_data_imx28)
+
extern const struct mxs_auart_data mx28_auart_data[] __initconst;
#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id])
#define mx28_add_auart0() mx28_add_auart(0)
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
index 1451ad0..81e99ce 100644
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -5,6 +5,9 @@ config MXS_HAVE_AMBA_DUART
config MXS_HAVE_PLATFORM_AUART
bool
+config MXS_HAVE_PLATFORM_GPMI
+ bool
+
config MXS_HAVE_PLATFORM_FEC
bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
index 0d9bea3..8a7c2c8 100644
--- a/arch/arm/mach-mxs/devices/Makefile
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
obj-y += platform-dma.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
+obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI) += platform-gpmi.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi.c b/arch/arm/mach-mxs/devices/platform-gpmi.c
new file mode 100644
index 0000000..038226b
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-gpmi.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <asm/sizes.h>
+#include <mach/mx23.h>
+#include <mach/mx28.h>
+#include <mach/gpmi-nfc.h>
+#include <mach/devices-common.h>
+
+#ifdef CONFIG_SOC_IMX23
+const struct gpmi_nfc_platform_data gpmi_platform_data_imx23 __initconst = {
+ .chip_version = CHIP_VERSION_IMX23,
+ .clock_name = GPMI_NFC_CLOCK_NAME,
+ .min_prop_delay_in_ns = 5,
+ .max_prop_delay_in_ns = 9,
+ .max_chip_count = 1,
+ .boot_area_size_in_bytes = 20 * SZ_1M,
+};
+
+const struct resource res_imx23[] __initconst = {
+ { /* GPMI */
+ .start = MX23_GPMI_BASE_ADDR,
+ .end = MX23_GPMI_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX23_INT_GPMI_ATTENTION,
+ .end = MX23_INT_GPMI_ATTENTION,
+ .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* BCH */
+ .start = MX23_BCH_BASE_ADDR,
+ .end = MX23_BCH_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX23_INT_BCH,
+ .end = MX23_INT_BCH,
+ .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* DMA */
+ .start = MX23_DMA_GPMI0,
+ .end = MX23_DMA_GPMI3,
+ .name = GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ .flags = IORESOURCE_DMA,
+ }, {
+ .start = MX23_INT_GPMI_DMA,
+ .end = MX23_INT_GPMI_DMA,
+ .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+const struct gpmi_nfc_platform_data gpmi_platform_data_imx28 __initconst = {
+ .chip_version = CHIP_VERSION_IMX28,
+ .clock_name = GPMI_NFC_CLOCK_NAME,
+ .min_prop_delay_in_ns = 5,
+ .max_prop_delay_in_ns = 9,
+ .max_chip_count = 1,
+ .boot_area_size_in_bytes = 20 * SZ_1M,
+};
+
+const struct resource res_imx28[] __initconst = {
+ { /* GPMI */
+ .start = MX28_GPMI_BASE_ADDR,
+ .end = MX28_GPMI_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX28_INT_GPMI,
+ .end = MX28_INT_GPMI,
+ .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* BCH */
+ .start = MX28_BCH_BASE_ADDR,
+ .end = MX28_BCH_BASE_ADDR + SZ_8K - 1,
+ .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX28_INT_BCH,
+ .end = MX28_INT_BCH,
+ .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ }, { /* DMA */
+ .start = MX28_DMA_GPMI0,
+ .end = MX28_DMA_GPMI7,
+ .name = GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ .flags = IORESOURCE_DMA,
+ }, {
+ .start = MX28_INT_GPMI_DMA,
+ .end = MX28_INT_GPMI_DMA,
+ .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+#endif
+
+static struct resource *__init get_res(int *res_size)
+{
+#ifdef CONFIG_SOC_IMX23
+ if (cpu_is_mx23()) {
+ *res_size = ARRAY_SIZE(res_imx23);
+ return (struct resource *)res_imx23;
+ }
+#endif
+
+#ifdef CONFIG_SOC_IMX28
+ if (cpu_is_mx28()) {
+ *res_size = ARRAY_SIZE(res_imx28);
+ return (struct resource *)res_imx28;
+ }
+#endif
+ BUG();
+ return NULL;
+}
+
+struct platform_device *__init
+mxs_add_gpmi(const struct gpmi_nfc_platform_data *data)
+{
+ struct resource *res;
+ int res_size;
+
+ res = get_res(&res_size);
+
+ return mxs_add_platform_device_dmamask(GPMI_NFC_DRIVER_NAME, -1,
+ res, res_size,
+ data, sizeof(*data), DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index 71f2448..1f05503 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -30,6 +30,10 @@ int __init mxs_add_amba_device(const struct amba_device *dev);
/* duart */
int __init mxs_add_duart(const struct amba_device *dev);
+/* GPMI */
+#include <mach/gpmi-nfc.h>
+struct platform_device *__init mxs_add_gpmi(
+ const struct gpmi_nfc_platform_data *data);
/* auart */
struct mxs_auart_data {
int id;
diff --git a/arch/arm/mach-mxs/include/mach/gpmi-nfc.h b/arch/arm/mach-mxs/include/mach/gpmi-nfc.h
new file mode 100644
index 0000000..2f2d663
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/gpmi-nfc.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __INCLUDE_LINUX_DEVICE_H
+#define __INCLUDE_LINUX_DEVICE_H
+
+#define GPMI_NFC_DRIVER_NAME "gpmi-nfc"
+#define GPMI_NFC_CLOCK_NAME "gpmi-clock"
+
+/* Resource names for the GPMI NFC driver. */
+#define GPMI_NFC_GPMI_REGS_ADDR_RES_NAME "GPMI NFC GPMI Registers"
+#define GPMI_NFC_GPMI_INTERRUPT_RES_NAME "GPMI NFC GPMI Interrupt"
+#define GPMI_NFC_BCH_REGS_ADDR_RES_NAME "GPMI NFC BCH Registers"
+#define GPMI_NFC_BCH_INTERRUPT_RES_NAME "GPMI NFC BCH Interrupt"
+#define GPMI_NFC_DMA_CHANNELS_RES_NAME "GPMI NFC DMA Channels"
+#define GPMI_NFC_DMA_INTERRUPT_RES_NAME "GPMI NFC DMA Interrupt"
+
+/**
+ * struct gpmi_nfc_platform_data - GPMI NFC driver platform data.
+ *
+ * This structure communicates platform-specific information to the GPMI NFC
+ * driver that can't be expressed as resources.
+ *
+ * @chip_version: The version of the hardware.
+ * @clock_name: The name of the clock that drives the NFC.
+ * @min_prop_delay_in_ns: Minimum propagation delay of GPMI signals to and
+ * from the NAND Flash device, in nanoseconds.
+ * @max_prop_delay_in_ns: Maximum propagation delay of GPMI signals to and
+ * from the NAND Flash device, in nanoseconds.
+ * @max_chip_count: The maximum number of chips for which the driver
+ * should configure the hardware. This value most
+ * likely reflects the number of pins that are
+ * connected to a NAND Flash device. If this is
+ * greater than the SoC hardware can support, the
+ * driver will print a message and fail to initialize.
+ * @boot_area_size_in_bytes: The amount of space reserved for each boot area.
+ * Note that some Boot ROMs call for multiple boot
+ * areas. If this value is zero, the driver will not
+ * construct special partitions for boot areas.
+ */
+struct gpmi_nfc_platform_data {
+ unsigned int chip_version;
+
+ /* SoC hardware information. */
+ char *clock_name;
+
+ /* NAND Flash information. */
+ unsigned int min_prop_delay_in_ns;
+ unsigned int max_prop_delay_in_ns;
+ unsigned int max_chip_count;
+
+ /* boot area */
+ uint32_t boot_area_size_in_bytes;
+};
+
+enum {
+ CHIP_VERSION_IMX23 = 0,
+ CHIP_VERSION_IMX28,
+};
+#endif
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index a66994f..db715f9 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -34,6 +34,42 @@ static const iomux_cfg_t mx23evk_pads[] __initconst = {
MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+ /* gpmi */
+ MX23_PAD_GPMI_D00__GPMI_D00 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D01__GPMI_D01 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D02__GPMI_D02 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D03__GPMI_D03 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D04__GPMI_D04 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D05__GPMI_D05 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D06__GPMI_D06 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_D07__GPMI_D07 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_CLE__GPMI_CLE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_ALE__GPMI_ALE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_WPN__GPMI_WPN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_WRN__GPMI_WRN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_RDY0__GPMI_RDY0 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_RDY1__GPMI_RDY1 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_CE0N__GPMI_CE0N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_GPMI_CE1N__GPMI_CE1N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
/* auart */
MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
@@ -108,6 +144,7 @@ static void __init mx23evk_init(void)
mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
mx23_add_duart();
+ mx23_add_gpmi();
mx23_add_auart0();
ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 08002d0..cf8ddcb 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -39,6 +39,42 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
+ /* gpmi */
+ MX28_PAD_GPMI_D00__GPMI_D0 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D01__GPMI_D1 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D02__GPMI_D2 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D03__GPMI_D3 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D04__GPMI_D4 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D05__GPMI_D5 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D06__GPMI_D6 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_D07__GPMI_D7 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_CE0N__GPMI_CE0N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_CE1N__GPMI_CE1N |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RDY0__GPMI_READY0 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RDY1__GPMI_READY1 |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RDN__GPMI_RDN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_WRN__GPMI_WRN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_ALE__GPMI_ALE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_CLE__GPMI_CLE |
+ (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX28_PAD_GPMI_RESETN__GPMI_RESETN |
+ (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
/* auart0 */
MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
@@ -265,6 +301,7 @@ static void __init mx28evk_init(void)
mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
mx28_add_duart();
+ mx28_add_gpmi();
mx28_add_auart0();
mx28_add_auart3();
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 2/7] add the common code for GPMI driver
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-16 1:55 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux, Huang Shijie, linux-mtd, dwmw2, David.Woodhouse
These files contain the common code for the GPMI driver.
gpmi-nfc-main.c : the main file of GPMI
mil.c : the MTD interface layer of GPMI
hal-common.c : the hardware abstract layer of GPMI
rom-common.c : the NAND boot support of GPMI
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/Makefile | 10 +
drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c | 524 ++++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h | 520 ++++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-common.c | 816 +++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/mil.c | 1104 +++++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/rom-common.c | 48 ++
6 files changed, 3022 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/Makefile
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-common.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/mil.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-common.c
diff --git a/drivers/mtd/nand/gpmi-nfc/Makefile b/drivers/mtd/nand/gpmi-nfc/Makefile
new file mode 100644
index 0000000..9026313
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/Makefile
@@ -0,0 +1,10 @@
+obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc.o
+gpmi-nfc-objs += gpmi-nfc-main.o
+gpmi-nfc-objs += hal-common.o
+gpmi-nfc-objs += hal-imx23.o
+gpmi-nfc-objs += hal-imx28.o
+gpmi-nfc-objs += rom-common.o
+gpmi-nfc-objs += rom-imx23.o
+gpmi-nfc-objs += rom-imx28.o
+gpmi-nfc-objs += mil.o
+gpmi-nfc-objs += nand_device_info.o
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
new file mode 100644
index 0000000..f22c9d5
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
@@ -0,0 +1,524 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/slab.h>
+#include "gpmi-nfc.h"
+#include "linux/slab.h"
+
+static ssize_t show_ignorebad(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct gpmi_nfc_data *this = dev_get_drvdata(dev);
+ struct mil *mil = &this->mil;
+
+ return sprintf(buf, "%d\n", mil->ignore_bad_block_marks);
+}
+
+/* Sets the value of the 'ignorebad' flag. */
+static ssize_t
+store_ignorebad(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct gpmi_nfc_data *this = dev_get_drvdata(dev);
+ struct mil *mil = &this->mil;
+ const char *p = buf;
+ unsigned long v;
+
+ /* Try to make sense of what arrived from user space. */
+ if (strict_strtoul(p, 0, &v) < 0)
+ return size;
+
+ if (v > 0)
+ v = 1;
+
+ if (v != mil->ignore_bad_block_marks) {
+ if (v) {
+ /*
+ * If control arrives here, we want to begin ignoring
+ * bad block marks. Reach into the NAND Flash MTD data
+ * structures and set the in-memory BBT pointer to NULL.
+ * This will cause the NAND Flash MTD code to believe
+ * that it never created a BBT and force it to call our
+ * block_bad function.
+ *
+ * See mil_block_bad for more details.
+ */
+ mil->saved_bbt = mil->nand.bbt;
+ mil->nand.bbt = 0;
+ } else {
+ /*
+ * If control arrives here, we want to stop ignoring
+ * bad block marks. Restore the NAND Flash MTD's pointer
+ * to its in-memory BBT.
+ */
+ mil->nand.bbt = mil->saved_bbt;
+ }
+ mil->ignore_bad_block_marks = v;
+ }
+ return size;
+}
+
+/* Device attributes that appear in sysfs. */
+static DEVICE_ATTR(ignorebad, 0644, show_ignorebad, store_ignorebad);
+static struct device_attribute *device_attributes[] = {
+ &dev_attr_ignorebad,
+};
+
+static int acquire_register_block(struct gpmi_nfc_data *this,
+ const char *resource_name, void **reg_block_base)
+{
+ struct platform_device *pdev = this->pdev;
+ struct resource *r;
+ void *p;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, resource_name);
+ if (!r) {
+ log("Can't get resource information for '%s'", resource_name);
+ return -ENXIO;
+ }
+
+ /* remap the register block */
+ p = ioremap(r->start, r->end - r->start + 1);
+ if (!p) {
+ log("Can't remap %s", resource_name);
+ return -EIO;
+ }
+
+ *reg_block_base = p;
+ return 0;
+}
+
+static void release_register_block(struct gpmi_nfc_data *this,
+ void *reg_block_base)
+{
+ iounmap(reg_block_base);
+}
+
+static int acquire_interrupt(struct gpmi_nfc_data *this,
+ const char *resource_name,
+ irq_handler_t interrupt_handler, int *lno, int *hno)
+{
+ struct platform_device *pdev = this->pdev;
+ struct resource *r;
+ int err = 0;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, resource_name);
+ if (!r) {
+ log("Can't get resource information for '%s'", resource_name);
+ return -ENXIO;
+ }
+
+ BUG_ON(r->start != r->end);
+ err = request_irq(r->start, interrupt_handler, 0, resource_name, this);
+ if (err) {
+ log("Can't own %s", resource_name);
+ return -EIO;
+ }
+
+ *lno = r->start;
+ *hno = r->end;
+ return 0;
+}
+
+static void release_interrupt(struct gpmi_nfc_data *this,
+ int low_interrupt_number, int high_interrupt_number)
+{
+ int i;
+ for (i = low_interrupt_number; i <= high_interrupt_number; i++)
+ free_irq(i, this);
+}
+
+static bool gpmi_dma_filter(struct dma_chan *chan, void *param)
+{
+ struct gpmi_nfc_data *this = param;
+ struct resource *r = this->private;
+
+ if (!mxs_dma_is_apbh(chan))
+ return false;
+ /*
+ * only catch the GPMI dma channels :
+ * for mx23 : MX23_DMA_GPMI0 ~ MX23_DMA_GPMI3
+ * (These four channels share the same IRQ!)
+ *
+ * for mx28 : MX28_DMA_GPMI0 ~ MX28_DMA_GPMI7
+ * (These eight channels share the same IRQ!)
+ */
+ if (r->start <= chan->chan_id && chan->chan_id <= r->end) {
+ chan->private = &this->dma_data;
+ return true;
+ }
+ return false;
+}
+
+static void release_dma_channels(struct gpmi_nfc_data *this)
+{
+ unsigned int i;
+ for (i = 0; i <= DMA_CHANS; i++)
+ if (this->dma_chans[i]) {
+ dma_release_channel(this->dma_chans[i]);
+ this->dma_chans[i] = NULL;
+ }
+}
+
+static int acquire_dma_channels(struct gpmi_nfc_data *this,
+ const char *resource_name,
+ unsigned *low_channel, unsigned *high_channel)
+{
+ struct platform_device *pdev = this->pdev;
+ struct resource *r, *r_dma;
+ unsigned int i;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_DMA, resource_name);
+ r_dma = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+ GPMI_NFC_DMA_INTERRUPT_RES_NAME);
+ if (!r || !r_dma) {
+ log("Can't get resource for DMA");
+ return -ENXIO;
+ }
+
+ /* get the DMA interrupt */
+ BUG_ON(r_dma->start != r_dma->end);
+ this->dma_data.chan_irq = r_dma->start;
+
+ /* used in gpmi_dma_filter() */
+ this->private = r;
+
+ for (i = r->start; i <= r->end; i++) {
+ dma_cap_mask_t mask;
+ struct dma_chan *dma_chan;
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ dma_chan = dma_request_channel(mask, gpmi_dma_filter, this);
+ if (!dma_chan)
+ goto acquire_err;
+ /* fill the first empty item */
+ this->dma_chans[i - r->start] = dma_chan;
+ }
+
+ *low_channel = r->start;
+ *high_channel = r->end;
+ return 0;
+
+acquire_err:
+ log("Can't acquire DMA channel %u", i);
+ release_dma_channels(this);
+ return -EINVAL;
+}
+
+
+static inline int acquire_clock(struct gpmi_nfc_data *this,
+ const char *clock_name, struct clk **clock)
+{
+ struct clk *c;
+
+ c = clk_get(this->dev, clock_name);
+ if (IS_ERR(c)) {
+ log("Can't own clock %s", clock_name);
+ return PTR_ERR(c);
+ }
+ *clock = c;
+ return 0;
+}
+
+static void release_clock(struct gpmi_nfc_data *this, struct clk *clock)
+{
+ clk_disable(clock);
+ clk_put(clock);
+}
+
+static int acquire_resources(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct resources *resources = &this->resources;
+ int error = 0;
+
+ /* Attempt to acquire the GPMI register block. */
+ error = acquire_register_block(this,
+ GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ &resources->gpmi_regs);
+ if (error)
+ goto exit_gpmi_regs;
+
+ /* Attempt to acquire the BCH register block. */
+ error = acquire_register_block(this,
+ GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ &resources->bch_regs);
+ if (error)
+ goto exit_bch_regs;
+
+ /* Attempt to acquire the BCH interrupt. */
+ error = acquire_interrupt(this,
+ GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ bch_irq,
+ &resources->bch_low_interrupt,
+ &resources->bch_high_interrupt);
+ if (error)
+ goto exit_bch_interrupt;
+
+ /* Attempt to acquire the DMA channels. */
+ error = acquire_dma_channels(this,
+ GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ &resources->dma_low_channel,
+ &resources->dma_high_channel);
+ if (error)
+ goto exit_dma_channels;
+
+ /* Attempt to acquire our clock. */
+ error = acquire_clock(this, pdata->clock_name, &resources->clock);
+ if (error)
+ goto exit_clock;
+ return 0;
+
+exit_clock:
+ release_dma_channels(this);
+exit_dma_channels:
+ release_interrupt(this, resources->bch_low_interrupt,
+ resources->bch_high_interrupt);
+exit_bch_interrupt:
+ release_register_block(this, resources->bch_regs);
+exit_bch_regs:
+ release_register_block(this, resources->gpmi_regs);
+exit_gpmi_regs:
+ return error;
+}
+
+static void release_resources(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ release_clock(this, resources->clock);
+ release_register_block(this, resources->gpmi_regs);
+ release_register_block(this, resources->bch_regs);
+ release_interrupt(this, resources->bch_low_interrupt,
+ resources->bch_low_interrupt);
+ release_dma_channels(this);
+}
+
+static void exit_nfc_hal(struct gpmi_nfc_data *this)
+{
+ if (this->nfc)
+ this->nfc->exit(this);
+}
+
+static int set_up_nfc_hal(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct nfc_hal *nfc;
+ int error = 0;
+
+ /*
+ * This structure contains the "safe" GPMI timing that should succeed
+ * with any NAND Flash device
+ * (although, with less-than-optimal performance).
+ */
+ static struct nand_timing safe_timing = {
+ .data_setup_in_ns = 80,
+ .data_hold_in_ns = 60,
+ .address_setup_in_ns = 25,
+ .gpmi_sample_delay_in_ns = 6,
+ .tREA_in_ns = -1,
+ .tRLOH_in_ns = -1,
+ .tRHOH_in_ns = -1,
+ };
+
+ switch (pdata->chip_version) {
+ case CHIP_VERSION_IMX23:
+ nfc = &gpmi_nfc_hal_imx23;
+ break;
+ case CHIP_VERSION_IMX28:
+ nfc = &gpmi_nfc_hal_imx28;
+ break;
+ default:
+ log("Unkown NFC version %u", pdata->chip_version);
+ return -ENXIO;
+ }
+
+ this->nfc = nfc;
+
+ /* Initialize the NFC HAL. */
+ error = nfc->init(this);
+ if (error)
+ return error;
+
+ /* Set up safe timing. */
+ nfc->set_timing(this, &safe_timing);
+ return 0;
+}
+
+static int set_up_boot_rom_helper(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct boot_rom_helper *rom;
+
+ switch (pdata->chip_version) {
+ case CHIP_VERSION_IMX23:
+ rom = &gpmi_nfc_boot_rom_imx23;
+ break;
+ case CHIP_VERSION_IMX28:
+ rom = &gpmi_nfc_boot_rom_imx28;
+ break;
+ default:
+ log("Unkown NFC version %u", pdata->chip_version);
+ return -ENXIO;
+ }
+
+ pr_info("Boot ROM: Version %u, %s\n", rom->version, rom->description);
+ this->rom = rom;
+ return 0;
+}
+
+/* Creates/Removes sysfs files for this device.*/
+static void manage_sysfs_files(struct gpmi_nfc_data *this, int create)
+{
+ struct device *dev = this->dev;
+ int error;
+ unsigned int i;
+ struct device_attribute **attr;
+
+ for (i = 0, attr = device_attributes;
+ i < ARRAY_SIZE(device_attributes); i++, attr++) {
+
+ if (create) {
+ error = device_create_file(dev, *attr);
+ if (error) {
+ while (--attr >= device_attributes)
+ device_remove_file(dev, *attr);
+ return;
+ }
+ } else {
+ device_remove_file(dev, *attr);
+ }
+ }
+}
+
+static int gpmi_nfc_probe(struct platform_device *pdev)
+{
+ struct gpmi_nfc_platform_data *pdata = pdev->dev.platform_data;
+ struct gpmi_nfc_data *this = 0;
+ int error = 0;
+
+ this = kzalloc(sizeof(*this), GFP_KERNEL);
+ if (!this) {
+ log("Failed to allocate per-device memory\n");
+ return -ENOMEM;
+ }
+
+ /* Set up our data structures. */
+ platform_set_drvdata(pdev, this);
+ this->pdev = pdev;
+ this->dev = &pdev->dev;
+ this->pdata = pdata;
+
+ /* Acquire the resources we need. */
+ error = acquire_resources(this);
+ if (error)
+ goto exit_acquire_resources;
+
+ /* Set up the NFC. */
+ error = set_up_nfc_hal(this);
+ if (error)
+ goto exit_nfc_init;
+
+ /* Set up the Boot ROM Helper. */
+ error = set_up_boot_rom_helper(this);
+ if (error)
+ goto exit_boot_rom_helper_init;
+
+ /* Initialize the MTD Interface Layer. */
+ error = gpmi_nfc_mil_init(this);
+ if (error)
+ goto exit_mil_init;
+
+ manage_sysfs_files(this, true);
+ return 0;
+
+exit_mil_init:
+exit_boot_rom_helper_init:
+ exit_nfc_hal(this);
+exit_nfc_init:
+ release_resources(this);
+exit_acquire_resources:
+ platform_set_drvdata(pdev, NULL);
+ kfree(this);
+ return error;
+}
+
+static int __exit gpmi_nfc_remove(struct platform_device *pdev)
+{
+ struct gpmi_nfc_data *this = platform_get_drvdata(pdev);
+
+ manage_sysfs_files(this, false);
+ gpmi_nfc_mil_exit(this);
+ exit_nfc_hal(this);
+ release_resources(this);
+ platform_set_drvdata(pdev, NULL);
+ kfree(this);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int gpmi_nfc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ return 0;
+}
+
+static int gpmi_nfc_resume(struct platform_device *pdev)
+{
+ return 0;
+}
+#else
+#define suspend NULL
+#define resume NULL
+#endif
+
+/* This structure represents this driver to the platform management system. */
+static struct platform_driver gpmi_nfc_driver = {
+ .driver = {
+ .name = GPMI_NFC_DRIVER_NAME,
+ },
+ .probe = gpmi_nfc_probe,
+ .remove = __exit_p(gpmi_nfc_remove),
+ .suspend = gpmi_nfc_suspend,
+ .resume = gpmi_nfc_resume,
+};
+
+static int __init gpmi_nfc_init(void)
+{
+ printk(KERN_INFO "GPMI NFC driver registered. (IMX)\n");
+ if (platform_driver_register(&gpmi_nfc_driver) != 0) {
+ pr_err("i.MX GPMI NFC driver registration failed\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+static void __exit gpmi_nfc_exit(void)
+{
+ platform_driver_unregister(&gpmi_nfc_driver);
+}
+
+module_init(gpmi_nfc_init);
+module_exit(gpmi_nfc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
new file mode 100644
index 0000000..b5a2d77
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
@@ -0,0 +1,520 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H
+#define __DRIVERS_MTD_NAND_GPMI_NFC_H
+
+/* Linux header files. */
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/concat.h>
+#include <linux/dmaengine.h>
+#include <asm/sizes.h>
+
+/* Platform header files. */
+#include <mach/mxs.h>
+#include <mach/common.h>
+#include <mach/dma.h>
+#include <mach/gpmi-nfc.h>
+#include <mach/system.h>
+#include <mach/clock.h>
+
+/* Driver header files. */
+#include "nand_device_info.h"
+
+/*
+ *------------------------------------------------------------------------------
+ * Fundamental Data Structures
+ *------------------------------------------------------------------------------
+ */
+
+/**
+ * struct resources - The collection of resources the driver needs.
+ *
+ * @gpmi_regs: A pointer to the GPMI registers.
+ * @bch_regs: A pointer to the BCH registers.
+ * @bch_interrupt: The BCH interrupt number.
+ * @dma_low_channel: The low DMA channel.
+ * @dma_high_channel: The high DMA channel.
+ * @clock: A pointer to the struct clk for the NFC's clock.
+ */
+struct resources {
+ void *gpmi_regs;
+ void *bch_regs;
+ unsigned int bch_low_interrupt;
+ unsigned int bch_high_interrupt;
+ unsigned int dma_low_channel;
+ unsigned int dma_high_channel;
+ struct clk *clock;
+};
+
+/**
+ * struct mil - State for the MTD Interface Layer.
+ *
+ * @nand: The NAND Flash MTD data structure that represents
+ * the NAND Flash medium.
+ * @mtd: The MTD data structure that represents the NAND
+ * Flash medium.
+ * @oob_layout: A structure that describes how bytes are laid out
+ * in the OOB.
+ * @general_use_mtd: A pointer to an MTD we export for general use.
+ * This *may* simply be a pointer to the mtd field, if
+ * we've been instructed NOT to protect the boot
+ * areas.
+ * @partitions: A pointer to a set of partitions applied to the
+ * general use MTD.
+ * @partition_count: The number of partitions.
+ * @current_chip: The chip currently selected by the NAND Fash MTD
+ * code. A negative value indicates that no chip is
+ * selected.
+ * @command_length: The length of the command that appears in the
+ * command buffer (see cmd_virt, below).
+ * @ignore_bad_block_marks: Indicates we are ignoring bad block marks.
+ * @saved_bbt: A saved pointer to the in-memory NAND Flash MTD bad
+ * block table. See show_device_ignorebad() for more
+ * details.
+ * @marking_a_bad_block: Indicates the caller is marking a bad block. See
+ * mil_ecc_write_oob() for details.
+ * @hooked_block_markbad: A pointer to the block_markbad() function we
+ * we "hooked." See mil_ecc_write_oob() for details.
+ * @upper_buf: The buffer passed from upper layer.
+ * @upper_len: The buffer len passed from upper layer.
+ * @direct_dma_map_ok: Is the direct DMA map is good for the upper_buf?
+ * @cmd_sgl/cmd_buffer: For NAND command.
+ * @data_sgl/data_buffer_dma:For NAND DATA ops.
+ * @page_buffer_virt: A pointer to a DMA-coherent buffer we use for
+ * reading and writing pages. This buffer includes
+ * space for both the payload data and the auxiliary
+ * data (including status bytes, but not syndrome
+ * bytes).
+ * @page_buffer_phys: The physical address for the page_buffer_virt
+ * buffer.
+ * @page_buffer_size: The size of the page buffer.
+ * @payload_virt: A pointer to a location in the page buffer used
+ * for payload bytes. The size of this buffer is
+ * determined by struct nfc_geometry.
+ * @payload_phys: The physical address for payload_virt.
+ * @auxiliary_virt: A pointer to a location in the page buffer used
+ * for auxiliary bytes. The size of this buffer is
+ * determined by struct nfc_geometry.
+ * @auxiliary_phys: The physical address for auxiliary_virt.
+ */
+struct mil {
+ /* MTD Data Structures */
+ struct nand_chip nand;
+ struct mtd_info mtd;
+ struct nand_ecclayout oob_layout;
+
+ /* Partitioning and Boot Area Protection */
+ struct mtd_info *general_use_mtd;
+ struct mtd_partition *partitions;
+ unsigned int partition_count;
+
+ /* General-use Variables */
+ int current_chip;
+ unsigned int command_length;
+ int ignore_bad_block_marks;
+ void *saved_bbt;
+
+ /* MTD Function Pointer Hooks */
+ int marking_a_bad_block;
+ int (*hooked_block_markbad)(struct mtd_info *mtd,
+ loff_t ofs);
+
+ /* from upper layer */
+ uint8_t *upper_buf;
+ int upper_len;
+
+ /* DMA */
+ bool direct_dma_map_ok;
+
+ struct scatterlist cmd_sgl;
+ char *cmd_buffer;
+
+ struct scatterlist data_sgl;
+ char *data_buffer_dma;
+
+ void *page_buffer_virt;
+ dma_addr_t page_buffer_phys;
+ unsigned int page_buffer_size;
+
+ void *payload_virt;
+ dma_addr_t payload_phys;
+
+ void *auxiliary_virt;
+ dma_addr_t auxiliary_phys;
+};
+
+/**
+ * struct nfc_geometry - NFC geometry description.
+ *
+ * This structure describes the NFC's view of the medium geometry.
+ *
+ * @ecc_algorithm: The human-readable name of the ECC algorithm
+ * (e.g., "Reed-Solomon" or "BCH").
+ * @ecc_strength: A number that describes the strength of the ECC
+ * algorithm.
+ * @page_size_in_bytes: The size, in bytes, of a physical page, including
+ * both data and OOB.
+ * @metadata_size_in_bytes: The size, in bytes, of the metadata.
+ * @ecc_chunk_size_in_bytes: The size, in bytes, of a single ECC chunk. Note
+ * the first chunk in the page includes both data and
+ * metadata, so it's a bit larger than this value.
+ * @ecc_chunk_count: The number of ECC chunks in the page,
+ * @payload_size_in_bytes: The size, in bytes, of the payload buffer.
+ * @auxiliary_size_in_bytes: The size, in bytes, of the auxiliary buffer.
+ * @auxiliary_status_offset: The offset into the auxiliary buffer at which
+ * the ECC status appears.
+ * @block_mark_byte_offset: The byte offset in the ECC-based page view at
+ * which the underlying physical block mark appears.
+ * @block_mark_bit_offset: The bit offset into the ECC-based page view at
+ * which the underlying physical block mark appears.
+ */
+struct nfc_geometry {
+ char *ecc_algorithm;
+ unsigned int ecc_strength;
+ unsigned int page_size_in_bytes;
+ unsigned int metadata_size_in_bytes;
+ unsigned int ecc_chunk_size_in_bytes;
+ unsigned int ecc_chunk_count;
+ unsigned int payload_size_in_bytes;
+ unsigned int auxiliary_size_in_bytes;
+ unsigned int auxiliary_status_offset;
+ unsigned int block_mark_byte_offset;
+ unsigned int block_mark_bit_offset;
+};
+
+/**
+ * struct boot_rom_geometry - Boot ROM geometry description.
+ *
+ * This structure encapsulates decisions made by the Boot ROM Helper.
+ *
+ * @boot_area_count: The number of boot areas. The first boot area
+ * appears at the beginning of chip 0, the next
+ * at the beginning of chip 1, etc.
+ * @boot_area_size_in_bytes: The size, in bytes, of each boot area.
+ * @stride_size_in_pages: The size of a boot block stride, in pages.
+ * @search_area_stride_exponent: The logarithm to base 2 of the size of a
+ * search area in boot block strides.
+ */
+struct boot_rom_geometry {
+ unsigned int boot_area_count;
+ unsigned int boot_area_size_in_bytes;
+ unsigned int stride_size_in_pages;
+ unsigned int search_area_stride_exponent;
+};
+
+/* DMA operations types */
+enum dma_ops_type {
+ DMA_FOR_COMMAND = 1,
+ DMA_FOR_READ_DATA,
+ DMA_FOR_WRITE_DATA,
+ DMA_FOR_READ_ECC_PAGE,
+ DMA_FOR_WRITE_ECC_PAGE
+};
+
+/**
+ * struct gpmi_nfc_data - i.MX NFC per-device data.
+ *
+ * Note that the "device" managed by this driver represents the NAND Flash
+ * controller *and* the NAND Flash medium behind it. Thus, the per-device data
+ * structure has information about the controller, the chips to which it is
+ * connected, and properties of the medium as a whole.
+ *
+ * @dev: A pointer to the owning struct device.
+ * @pdev: A pointer to the owning struct platform_device.
+ * @pdata: A pointer to the device's platform data.
+ * @resources: Information about system resources used by this driver.
+ * @device_info: A structure that contains detailed information about
+ * the NAND Flash device.
+ * @nfc: A pointer to a structure that represents the underlying
+ * NFC hardware.
+ * @nfc_geometry: A description of the medium geometry as viewed by the
+ * NFC.
+ * @rom: A pointer to a structure that represents the underlying
+ * Boot ROM.
+ * @rom_geometry: A description of the medium geometry as viewed by the
+ * Boot ROM.
+ * @mil: A collection of information used by the MTD Interface
+ * Layer.
+ */
+struct gpmi_nfc_data {
+ /* System Interface */
+ struct device *dev;
+ struct platform_device *pdev;
+ struct gpmi_nfc_platform_data *pdata;
+
+ /* Resources */
+ struct resources resources;
+
+ /* Flash Hardware */
+ struct nand_device_info device_info;
+
+ /* NFC HAL */
+ struct nfc_hal *nfc;
+ struct nfc_geometry nfc_geometry;
+
+ /* Boot ROM Helper */
+ struct boot_rom_helper *rom;
+ struct boot_rom_geometry rom_geometry;
+
+ /* MTD Interface Layer */
+ struct mil mil;
+
+ /* DMA channels */
+#define DMA_CHANS 8
+ struct dma_chan *dma_chans[DMA_CHANS];
+ struct mxs_dma_data dma_data;
+ enum dma_ops_type dma_type;
+
+ /* private */
+ void *private;
+};
+
+/**
+ * struct gpmi_nfc_hardware_timing - GPMI NFC hardware timing parameters.
+ *
+ * This structure contains timing information expressed in a form directly
+ * usable by the GPMI NFC hardware.
+ *
+ * @data_setup_in_cycles: The data setup time, in cycles.
+ * @data_hold_in_cycles: The data hold time, in cycles.
+ * @address_setup_in_cycles: The address setup time, in cycles.
+ * @use_half_periods: Indicates the clock is running slowly, so the
+ * NFC DLL should use half-periods.
+ * @sample_delay_factor: The sample delay factor.
+ */
+struct gpmi_nfc_hardware_timing {
+ uint8_t data_setup_in_cycles;
+ uint8_t data_hold_in_cycles;
+ uint8_t address_setup_in_cycles;
+ bool use_half_periods;
+ uint8_t sample_delay_factor;
+};
+
+/**
+ * struct nfc_hal - GPMI NFC HAL
+ *
+ * This structure embodies an abstract interface to the underlying NFC hardware.
+ *
+ * @version: The NFC hardware version.
+ * @description: A pointer to a human-readable description of
+ * the NFC hardware.
+ * @max_chip_count: The maximum number of chips the NFC can
+ * possibly support (this value is a constant for
+ * each NFC version). This may *not* be the actual
+ * number of chips connected.
+ * @max_data_setup_cycles: The maximum number of data setup cycles that
+ * can be expressed in the hardware.
+ * @internal_data_setup_in_ns: The time, in ns, that the NFC hardware requires
+ * for data read internal setup. In the Reference
+ * Manual, see the chapter "High-Speed NAND
+ * Timing" for more details.
+ * @max_sample_delay_factor: The maximum sample delay factor that can be
+ * expressed in the hardware.
+ * @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the
+ * sample delay DLL hardware can possibly work
+ * with (the DLL is unusable with longer periods).
+ * If the full-cycle period is greater than HALF
+ * this value, the DLL must be configured to use
+ * half-periods.
+ * @max_dll_delay_in_ns: The maximum amount of delay, in ns, that the
+ * DLL can implement.
+ * @dma_descriptors: A pool of DMA descriptors.
+ * @isr_dma_channel: The DMA channel with which the NFC HAL is
+ * working. We record this here so the ISR knows
+ * which DMA channel to acknowledge.
+ * @dma_done: The completion structure used for DMA
+ * interrupts.
+ * @bch_done: The completion structure used for BCH
+ * interrupts.
+ * @timing: The current timing configuration.
+ * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
+ * I/O transaction. If no I/O transaction is in
+ * progress, this is the clock frequency during
+ * the most recent I/O transaction.
+ * @hardware_timing: The hardware timing configuration in effect
+ * during the current I/O transaction. If no I/O
+ * transaction is in progress, this is the
+ * hardware timing configuration during the most
+ * recent I/O transaction.
+ * @init: Initializes the NFC hardware and data
+ * structures. This function will be called after
+ * everything has been set up for communication
+ * with the NFC itself, but before the platform
+ * has set up off-chip communication. Thus, this
+ * function must not attempt to communicate with
+ * the NAND Flash hardware.
+ * @set_geometry: Configures the NFC hardware and data structures
+ * to match the physical NAND Flash geometry.
+ * @set_geometry: Configures the NFC hardware and data structures
+ * to match the physical NAND Flash geometry.
+ * @set_timing: Configures the NFC hardware and data structures
+ * to match the given NAND Flash bus timing.
+ * @get_timing: Returns the the clock frequency, in Hz, and
+ * the hardware timing configuration during the
+ * current I/O transaction. If no I/O transaction
+ * is in progress, this is the timing state during
+ * the most recent I/O transaction.
+ * @exit: Shuts down the NFC hardware and data
+ * structures. This function will be called after
+ * the platform has shut down off-chip
+ * communication but while communication with the
+ * NFC itself still works.
+ * @clear_bch: Clears a BCH interrupt (intended to be called
+ * by a more general interrupt handler to do
+ * device-specific clearing).
+ * @is_ready: Returns true if the given chip is ready.
+ * @begin: Begins an interaction with the NFC. This
+ * function must be called before *any* of the
+ * following functions so the NFC can prepare
+ * itself.
+ * @end: Ends interaction with the NFC. This function
+ * should be called to give the NFC a chance to,
+ * among other things, enter a lower-power state.
+ * @send_command: Sends the given buffer of command bytes.
+ * @send_data: Sends the given buffer of data bytes.
+ * @read_data: Reads data bytes into the given buffer.
+ * @send_page: Sends the given given data and OOB bytes,
+ * using the ECC engine.
+ * @read_page: Reads a page through the ECC engine and
+ * delivers the data and OOB bytes to the given
+ * buffers.
+ */
+struct nfc_hal {
+ /* Hardware attributes. */
+ const unsigned int version;
+ const char *description;
+ const unsigned int max_chip_count;
+ const unsigned int max_data_setup_cycles;
+ const unsigned int internal_data_setup_in_ns;
+ const unsigned int max_sample_delay_factor;
+ const unsigned int max_dll_clock_period_in_ns;
+ const unsigned int max_dll_delay_in_ns;
+
+ int isr_dma_channel;
+ struct completion dma_done;
+ struct completion bch_done;
+ struct nand_timing timing;
+ unsigned long clock_frequency_in_hz;
+
+ /* Configuration functions. */
+ int (*init) (struct gpmi_nfc_data *);
+ int (*extra_init) (struct gpmi_nfc_data *);
+ int (*set_geometry)(struct gpmi_nfc_data *);
+ int (*set_timing) (struct gpmi_nfc_data *,
+ const struct nand_timing *);
+ void (*get_timing) (struct gpmi_nfc_data *,
+ unsigned long *clock_frequency_in_hz,
+ struct gpmi_nfc_hardware_timing *);
+ void (*exit) (struct gpmi_nfc_data *);
+
+ /* Call these functions to begin and end I/O. */
+ void (*begin) (struct gpmi_nfc_data *);
+ void (*end) (struct gpmi_nfc_data *);
+
+ /* Call these I/O functions only between begin() and end(). */
+ void (*clear_bch) (struct gpmi_nfc_data *);
+ int (*is_ready) (struct gpmi_nfc_data *, unsigned chip);
+ int (*send_command)(struct gpmi_nfc_data *);
+ int (*send_data) (struct gpmi_nfc_data *);
+ int (*read_data) (struct gpmi_nfc_data *);
+ int (*send_page) (struct gpmi_nfc_data *,
+ dma_addr_t payload, dma_addr_t auxiliary);
+ int (*read_page) (struct gpmi_nfc_data *,
+ dma_addr_t payload, dma_addr_t auxiliary);
+};
+
+/**
+ * struct boot_rom_helper - Boot ROM Helper
+ *
+ * This structure embodies the interface to an object that assists the driver
+ * in making decisions that relate to the Boot ROM.
+ *
+ * @version: The Boot ROM version.
+ * @description: A pointer to a human-readable description of the
+ * Boot ROM.
+ * @swap_block_mark: Indicates that the Boot ROM will swap the block
+ * mark with the first byte of the OOB.
+ * @set_geometry: Configures the Boot ROM geometry.
+ * @rom_extra_init: Arch-specific init.
+ */
+struct boot_rom_helper {
+ const unsigned int version;
+ const char *description;
+ const int swap_block_mark;
+ int (*set_geometry) (struct gpmi_nfc_data *);
+ int (*rom_extra_init) (struct gpmi_nfc_data *);
+};
+
+/*
+ *------------------------------------------------------------------------------
+ * External Symbols
+ *------------------------------------------------------------------------------
+ */
+
+/* NFC HAL Common Services */
+extern irqreturn_t bch_irq(int irq, void *cookie);
+extern int common_nfc_set_geometry(struct gpmi_nfc_data *this);
+extern int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+ struct gpmi_nfc_hardware_timing *hw);
+extern struct dma_chan *get_dma_chan(struct gpmi_nfc_data *this);
+extern void prepare_data_dma(struct gpmi_nfc_data *this,
+ enum dma_data_direction dr);
+extern int start_dma_without_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc);
+extern int start_dma_with_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc);
+/* NFC HAL Structures */
+extern struct nfc_hal gpmi_nfc_hal_imx23;
+extern struct nfc_hal gpmi_nfc_hal_imx28;
+
+/* Boot ROM Helper Common Services */
+extern int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this);
+
+/* Boot ROM Helper Structures */
+extern struct boot_rom_helper gpmi_nfc_boot_rom_imx23;
+extern struct boot_rom_helper gpmi_nfc_boot_rom_imx28;
+
+/* MTD Interface Layer */
+extern int gpmi_nfc_mil_init(struct gpmi_nfc_data *this);
+extern void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this);
+
+/* for log */
+#define log(a, ...) printk(KERN_INFO "[ %s : %.3d ] "a"\n", \
+ __func__, __LINE__, ## __VA_ARGS__)
+
+/* BCH : Status Block Completion Codes */
+#define STATUS_ERASED (0xff)
+#define STATUS_UNCORRECTABLE (0xfe)
+#define STATUS_GOOD (0x00)
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/hal-common.c b/drivers/mtd/nand/gpmi-nfc/hal-common.c
new file mode 100644
index 0000000..d7e8075
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/hal-common.c
@@ -0,0 +1,816 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+irqreturn_t bch_irq(int irq, void *cookie)
+{
+ struct gpmi_nfc_data *this = cookie;
+ struct nfc_hal *nfc = this->nfc;
+
+ /* Clear the BCH interrupt */
+ nfc->clear_bch(this);
+
+ complete(&nfc->bch_done);
+ return IRQ_HANDLED;
+}
+
+/* calculate the ECC strength by hand */
+static inline int get_ecc_strength(struct gpmi_nfc_data *this)
+{
+ struct mtd_info *mtd = &this->mil.mtd;
+ int ecc_strength = 0;
+
+ switch (mtd->writesize) {
+ case 2048:
+ ecc_strength = 8;
+ break;
+ case 4096:
+ switch (mtd->oobsize) {
+ case 128:
+ ecc_strength = 8;
+ break;
+ case 218:
+ ecc_strength = 16;
+ break;
+ }
+ break;
+ case 8192:
+ ecc_strength = 24;
+ break;
+ }
+
+ return ecc_strength;
+}
+
+int common_nfc_set_geometry(struct gpmi_nfc_data *this)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ struct boot_rom_helper *rom = this->rom;
+ struct mtd_info *mtd = &this->mil.mtd;
+ unsigned int metadata_size;
+ unsigned int status_size;
+ unsigned int chunk_data_size_in_bits;
+ unsigned int chunk_ecc_size_in_bits;
+ unsigned int chunk_total_size_in_bits;
+ unsigned int block_mark_chunk_number;
+ unsigned int block_mark_chunk_bit_offset;
+ unsigned int block_mark_bit_offset;
+
+ /* We only support BCH now. */
+ geo->ecc_algorithm = "BCH";
+
+ /*
+ * We always choose a metadata size of 10. Don't try to make sense of
+ * it -- this is really only for historical compatibility.
+ */
+ geo->metadata_size_in_bytes = 10;
+
+ /* ECC chunks */
+ geo->ecc_chunk_size_in_bytes = 512;
+ if (is_ddr_nand(&this->device_info))
+ geo->ecc_chunk_size_in_bytes = 1024;
+
+ /*
+ * Compute the total number of ECC chunks in a page. This includes the
+ * slightly larger chunk at the beginning of the page, which contains
+ * both data and metadata.
+ */
+ geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size_in_bytes;
+
+ /*
+ * We use the same ECC strength for all chunks, including the first one.
+ * At this writing, we base our ECC strength choice entirely on the
+ * the physical page geo. In the future, this should be changed to
+ * pay attention to the detailed device information we gathered earlier.
+ */
+ geo->ecc_strength = get_ecc_strength(this);
+ if (!geo->ecc_strength) {
+ log("Unsupported page geometry.");
+ return !0;
+ }
+
+ /* Compute the page size, include page and oob. */
+ geo->page_size_in_bytes = mtd->writesize + mtd->oobsize;
+ /*
+ * ONFI/TOGGLE nand needs GF14, so re-culculate DMA page size.
+ * The ONFI nand must do the reculation,
+ * else it will fail in DMA in some platform(such as imx50).
+ */
+ if (is_ddr_nand(&this->device_info))
+ geo->page_size_in_bytes = mtd->writesize +
+ geo->metadata_size_in_bytes +
+ (geo->ecc_strength * 14 * 8 / geo->ecc_chunk_count);
+
+ /*
+ * The payload buffer contains the data area of a page. The ECC engine
+ * only needs what's required to hold the data.
+ */
+ geo->payload_size_in_bytes = mtd->writesize;
+
+ /*
+ * In principle, computing the auxiliary buffer geometry is NFC
+ * version-specific. However, at this writing, all versions share the
+ * same model, so this code can also be shared.
+ *
+ * The auxiliary buffer contains the metadata and the ECC status. The
+ * metadata is padded to the nearest 32-bit boundary. The ECC status
+ * contains one byte for every ECC chunk, and is also padded to the
+ * nearest 32-bit boundary.
+ */
+ metadata_size = (geo->metadata_size_in_bytes + 0x3) & ~0x3;
+ status_size = (geo->ecc_chunk_count + 0x3) & ~0x3;
+
+ geo->auxiliary_size_in_bytes = metadata_size + status_size;
+ geo->auxiliary_status_offset = metadata_size;
+
+ /* Check if we're going to do block mark swapping. */
+ if (!rom->swap_block_mark)
+ return 0;
+
+ /*
+ * If control arrives here, we're doing block mark swapping, so we need
+ * to compute the byte and bit offsets of the physical block mark within
+ * the ECC-based view of the page data. In principle, this isn't a
+ * difficult computation -- but it's very important and it's easy to get
+ * it wrong, so we do it carefully.
+ *
+ * Note that this calculation is simpler because we use the same ECC
+ * strength for all chunks, including the zero'th one, which contains
+ * the metadata. The calculation would be slightly more complicated
+ * otherwise.
+ *
+ * We start by computing the physical bit offset of the block mark. We
+ * then subtract the number of metadata and ECC bits appearing before
+ * the mark to arrive at its bit offset within the data alone.
+ */
+
+ /* Compute some important facts about chunk geometry. */
+ chunk_data_size_in_bits = geo->ecc_chunk_size_in_bytes * 8;
+
+ /* ONFI/TOGGLE nand needs GF14 */
+ if (is_ddr_nand(&this->device_info))
+ chunk_ecc_size_in_bits = geo->ecc_strength * 14;
+ else
+ chunk_ecc_size_in_bits = geo->ecc_strength * 13;
+
+ chunk_total_size_in_bits =
+ chunk_data_size_in_bits + chunk_ecc_size_in_bits;
+
+ /* Compute the bit offset of the block mark within the physical page. */
+ block_mark_bit_offset = mtd->writesize * 8;
+
+ /* Subtract the metadata bits. */
+ block_mark_bit_offset -= geo->metadata_size_in_bytes * 8;
+
+ /*
+ * Compute the chunk number (starting at zero) in which the block mark
+ * appears.
+ */
+ block_mark_chunk_number =
+ block_mark_bit_offset / chunk_total_size_in_bits;
+
+ /*
+ * Compute the bit offset of the block mark within its chunk, and
+ * validate it.
+ */
+ block_mark_chunk_bit_offset =
+ block_mark_bit_offset -
+ (block_mark_chunk_number * chunk_total_size_in_bits);
+
+ if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) {
+ /*
+ * If control arrives here, the block mark actually appears in
+ * the ECC bits of this chunk. This wont' work.
+ */
+ log("Unsupported page geometry (block mark in ECC): %u:%u",
+ mtd->writesize, mtd->oobsize);
+ return !0;
+ }
+
+ /*
+ * Now that we know the chunk number in which the block mark appears,
+ * we can subtract all the ECC bits that appear before it.
+ */
+ block_mark_bit_offset -=
+ block_mark_chunk_number * chunk_ecc_size_in_bits;
+
+ /*
+ * We now know the absolute bit offset of the block mark within the
+ * ECC-based data. We can now compute the byte offset and the bit
+ * offset within the byte.
+ */
+ geo->block_mark_byte_offset = block_mark_bit_offset / 8;
+ geo->block_mark_bit_offset = block_mark_bit_offset % 8;
+
+ return 0;
+}
+
+struct dma_chan *get_dma_chan(struct gpmi_nfc_data *this)
+{
+ int chip = this->mil.current_chip;
+
+ BUG_ON(chip < 0);
+ return this->dma_chans[chip];
+}
+
+/* Can we use the upper's buffer directly for DMA? */
+void prepare_data_dma(struct gpmi_nfc_data *this, enum dma_data_direction dr)
+{
+ struct mil *mil = &this->mil;
+ struct scatterlist *sgl = &mil->data_sgl;
+ int ret = 0;
+
+ mil->direct_dma_map_ok = true;
+
+ /* first try to map the upper buffer directly */
+ sg_init_one(sgl, mil->upper_buf, mil->upper_len);
+ ret = dma_map_sg(this->dev, sgl, 1, dr);
+ if (ret == 0) {
+ /* We have to use our own DMA buffer. */
+ sg_init_one(sgl, mil->data_buffer_dma, PAGE_SIZE);
+ ret = dma_map_sg(this->dev, sgl, 1, dr);
+ BUG_ON(ret == 0);
+
+ if (dr == DMA_TO_DEVICE)
+ memcpy(mil->data_buffer_dma, mil->upper_buf,
+ mil->upper_len);
+ mil->direct_dma_map_ok = false;
+ }
+ sgl->length = mil->upper_len;
+}
+
+/* This will be called after the DMA operation is finished. */
+static void dma_irq_callback(void *param)
+{
+ struct gpmi_nfc_data *this = param;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ complete(&nfc->dma_done);
+
+ switch (this->dma_type) {
+ case DMA_FOR_COMMAND:
+ dma_unmap_sg(this->dev, &mil->cmd_sgl, 1, DMA_TO_DEVICE);
+ break;
+
+ case DMA_FOR_READ_DATA:
+ if (mil->direct_dma_map_ok == false)
+ memcpy(mil->upper_buf, (char *)mil->data_buffer_dma,
+ mil->upper_len);
+ dma_unmap_sg(this->dev, &mil->data_sgl, 1, DMA_FROM_DEVICE);
+ break;
+
+ case DMA_FOR_WRITE_DATA:
+ dma_unmap_sg(this->dev, &mil->data_sgl, 1, DMA_TO_DEVICE);
+ break;
+
+ case DMA_FOR_READ_ECC_PAGE:
+ case DMA_FOR_WRITE_ECC_PAGE:
+ break;
+
+ default:
+ BUG();
+ }
+}
+
+int start_dma_without_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc)
+{
+ struct nfc_hal *nfc = this->nfc;
+ int err;
+
+ init_completion(&nfc->dma_done);
+
+ desc->callback = dma_irq_callback;
+ desc->callback_param = this;
+ dmaengine_submit(desc);
+
+ /* Wait for the interrupt from the DMA block. */
+ err = wait_for_completion_timeout(&nfc->dma_done,
+ msecs_to_jiffies(1000));
+ err = (!err) ? -ETIMEDOUT : 0;
+ if (err)
+ log("DMA timeout!!!");
+ return err;
+}
+
+/*
+ * This function is used in BCH reading or BCH writing pages.
+ * It will wait for the BCH interrupt as long as ONE second.
+ * Actually, we must wait for two interrupts :
+ * [1] firstly the DMA interrupt and
+ * [2] the BCH interrupt.
+ *
+ * @this: Per-device data structure.
+ * @desc: DMA channel
+ */
+int start_dma_with_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc)
+{
+ struct nfc_hal *nfc = this->nfc;
+ int err = 0;
+
+ /* Prepare to receive an interrupt from the BCH block. */
+ init_completion(&nfc->bch_done);
+
+ /* start the DMA */
+ start_dma_without_bch_irq(this, desc);
+
+ /* Wait for the interrupt from the BCH block. */
+ err = wait_for_completion_timeout(&nfc->bch_done,
+ msecs_to_jiffies(1000));
+ err = (!err) ? -ETIMEDOUT : 0;
+ if (err)
+ log("bch timeout!!!");
+ return err;
+}
+
+/**
+ * ns_to_cycles - Converts time in nanoseconds to cycles.
+ *
+ * @ntime: The time, in nanoseconds.
+ * @period: The cycle period, in nanoseconds.
+ * @min: The minimum allowable number of cycles.
+ */
+static unsigned int ns_to_cycles(unsigned int time,
+ unsigned int period, unsigned int min)
+{
+ unsigned int k;
+
+ /*
+ * Compute the minimum number of cycles that entirely contain the
+ * given time.
+ */
+ k = (time + period - 1) / period;
+ return max(k, min);
+}
+
+/**
+ * gpmi_compute_hardware_timing - Apply timing to current hardware conditions.
+ *
+ * @this: Per-device data.
+ * @hardware_timing: A pointer to a hardware timing structure that will receive
+ * the results of our calculations.
+ */
+int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+ struct gpmi_nfc_hardware_timing *hw)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct nfc_hal *nfc = this->nfc;
+ struct nand_chip *nand = &this->mil.nand;
+ struct nand_timing target = nfc->timing;
+ bool improved_timing_is_available;
+ unsigned long clock_frequency_in_hz;
+ unsigned int clock_period_in_ns;
+ bool dll_use_half_periods;
+ unsigned int dll_delay_shift;
+ unsigned int max_sample_delay_in_ns;
+ unsigned int address_setup_in_cycles;
+ unsigned int data_setup_in_ns;
+ unsigned int data_setup_in_cycles;
+ unsigned int data_hold_in_cycles;
+ int ideal_sample_delay_in_ns;
+ unsigned int sample_delay_factor;
+ int tEYE;
+ unsigned int min_prop_delay_in_ns = pdata->min_prop_delay_in_ns;
+ unsigned int max_prop_delay_in_ns = pdata->max_prop_delay_in_ns;
+
+ /*
+ * If there are multiple chips, we need to relax the timings to allow
+ * for signal distortion due to higher capacitance.
+ */
+ if (nand->numchips > 2) {
+ target.data_setup_in_ns += 10;
+ target.data_hold_in_ns += 10;
+ target.address_setup_in_ns += 10;
+ } else if (nand->numchips > 1) {
+ target.data_setup_in_ns += 5;
+ target.data_hold_in_ns += 5;
+ target.address_setup_in_ns += 5;
+ }
+
+ /* Check if improved timing information is available. */
+ improved_timing_is_available =
+ (target.tREA_in_ns >= 0) &&
+ (target.tRLOH_in_ns >= 0) &&
+ (target.tRHOH_in_ns >= 0) ;
+
+ /* Inspect the clock. */
+ clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+ clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
+
+ /*
+ * The NFC quantizes setup and hold parameters in terms of clock cycles.
+ * Here, we quantize the setup and hold timing parameters to the
+ * next-highest clock period to make sure we apply at least the
+ * specified times.
+ *
+ * For data setup and data hold, the hardware interprets a value of zero
+ * as the largest possible delay. This is not what's intended by a zero
+ * in the input parameter, so we impose a minimum of one cycle.
+ */
+ data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns,
+ clock_period_in_ns, 1);
+ data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns,
+ clock_period_in_ns, 1);
+ address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
+ clock_period_in_ns, 0);
+
+ /*
+ * The clock's period affects the sample delay in a number of ways:
+ *
+ * (1) The NFC HAL tells us the maximum clock period the sample delay
+ * DLL can tolerate. If the clock period is greater than half that
+ * maximum, we must configure the DLL to be driven by half periods.
+ *
+ * (2) We need to convert from an ideal sample delay, in ns, to a
+ * "sample delay factor," which the NFC uses. This factor depends on
+ * whether we're driving the DLL with full or half periods.
+ * Paraphrasing the reference manual:
+ *
+ * AD = SDF x 0.125 x RP
+ *
+ * where:
+ *
+ * AD is the applied delay, in ns.
+ * SDF is the sample delay factor, which is dimensionless.
+ * RP is the reference period, in ns, which is a full clock period
+ * if the DLL is being driven by full periods, or half that if
+ * the DLL is being driven by half periods.
+ *
+ * Let's re-arrange this in a way that's more useful to us:
+ *
+ * 8
+ * SDF = AD x ----
+ * RP
+ *
+ * The reference period is either the clock period or half that, so this
+ * is:
+ *
+ * 8 AD x DDF
+ * SDF = AD x ----- = --------
+ * f x P P
+ *
+ * where:
+ *
+ * f is 1 or 1/2, depending on how we're driving the DLL.
+ * P is the clock period.
+ * DDF is the DLL Delay Factor, a dimensionless value that
+ * incorporates all the constants in the conversion.
+ *
+ * DDF will be either 8 or 16, both of which are powers of two. We can
+ * reduce the cost of this conversion by using bit shifts instead of
+ * multiplication or division. Thus:
+ *
+ * AD << DDS
+ * SDF = ---------
+ * P
+ *
+ * or
+ *
+ * AD = (SDF >> DDS) x P
+ *
+ * where:
+ *
+ * DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF.
+ */
+ if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
+ dll_use_half_periods = true;
+ dll_delay_shift = 3 + 1;
+ } else {
+ dll_use_half_periods = false;
+ dll_delay_shift = 3;
+ }
+
+ /*
+ * Compute the maximum sample delay the NFC allows, under current
+ * conditions. If the clock is running too slowly, no sample delay is
+ * possible.
+ */
+ if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
+ max_sample_delay_in_ns = 0;
+ else {
+ /*
+ * Compute the delay implied by the largest sample delay factor
+ * the NFC allows.
+ */
+ max_sample_delay_in_ns =
+ (nfc->max_sample_delay_factor * clock_period_in_ns) >>
+ dll_delay_shift;
+
+ /*
+ * Check if the implied sample delay larger than the NFC
+ * actually allows.
+ */
+ if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
+ max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
+ }
+
+ /*
+ * Check if improved timing information is available. If not, we have to
+ * use a less-sophisticated algorithm.
+ */
+ if (!improved_timing_is_available) {
+ /*
+ * Fold the read setup time required by the NFC into the ideal
+ * sample delay.
+ */
+ ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
+ nfc->internal_data_setup_in_ns;
+
+ /*
+ * The ideal sample delay may be greater than the maximum
+ * allowed by the NFC. If so, we can trade off sample delay time
+ * for more data setup time.
+ *
+ * In each iteration of the following loop, we add a cycle to
+ * the data setup time and subtract a corresponding amount from
+ * the sample delay until we've satisified the constraints or
+ * can't do any better.
+ */
+ while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+ data_setup_in_cycles++;
+ ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+
+ }
+
+ /*
+ * Compute the sample delay factor that corresponds most closely
+ * to the ideal sample delay. If the result is too large for the
+ * NFC, use the maximum value.
+ *
+ * Notice that we use the ns_to_cycles function to compute the
+ * sample delay factor. We do this because the form of the
+ * computation is the same as that for calculating cycles.
+ */
+ sample_delay_factor =
+ ns_to_cycles(
+ ideal_sample_delay_in_ns << dll_delay_shift,
+ clock_period_in_ns, 0);
+
+ if (sample_delay_factor > nfc->max_sample_delay_factor)
+ sample_delay_factor = nfc->max_sample_delay_factor;
+
+ /* Skip to the part where we return our results. */
+ goto return_results;
+ }
+
+ /*
+ * If control arrives here, we have more detailed timing information,
+ * so we can use a better algorithm.
+ */
+
+ /*
+ * Fold the read setup time required by the NFC into the maximum
+ * propagation delay.
+ */
+ max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
+
+ /*
+ * Earlier, we computed the number of clock cycles required to satisfy
+ * the data setup time. Now, we need to know the actual nanoseconds.
+ */
+ data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
+
+ /*
+ * Compute tEYE, the width of the data eye when reading from the NAND
+ * Flash. The eye width is fundamentally determined by the data setup
+ * time, perturbed by propagation delays and some characteristics of the
+ * NAND Flash device.
+ *
+ * start of the eye = max_prop_delay + tREA
+ * end of the eye = min_prop_delay + tRHOH + data_setup
+ */
+ tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
+ (int)data_setup_in_ns;
+
+ tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
+
+ /*
+ * The eye must be open. If it's not, we can try to open it by
+ * increasing its main forcer, the data setup time.
+ *
+ * In each iteration of the following loop, we increase the data setup
+ * time by a single clock cycle. We do this until either the eye is
+ * open or we run into NFC limits.
+ */
+ while ((tEYE <= 0) &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+ /* Give a cycle to data setup. */
+ data_setup_in_cycles++;
+ /* Synchronize the data setup time with the cycles. */
+ data_setup_in_ns += clock_period_in_ns;
+ /* Adjust tEYE accordingly. */
+ tEYE += clock_period_in_ns;
+ }
+
+ /*
+ * When control arrives here, the eye is open. The ideal time to sample
+ * the data is in the center of the eye:
+ *
+ * end of the eye + start of the eye
+ * --------------------------------- - data_setup
+ * 2
+ *
+ * After some algebra, this simplifies to the code immediately below.
+ */
+ ideal_sample_delay_in_ns =
+ ((int)max_prop_delay_in_ns +
+ (int)target.tREA_in_ns +
+ (int)min_prop_delay_in_ns +
+ (int)target.tRHOH_in_ns -
+ (int)data_setup_in_ns) >> 1;
+
+ /*
+ * The following figure illustrates some aspects of a NAND Flash read:
+ *
+ *
+ * __ _____________________________________
+ * RDN \_________________/
+ *
+ * <---- tEYE ----->
+ * /-----------------\
+ * Read Data ----------------------------< >---------
+ * \-----------------/
+ * ^ ^ ^ ^
+ * | | | |
+ * |<--Data Setup -->|<--Delay Time -->| |
+ * | | | |
+ * | | |
+ * | |<-- Quantized Delay Time -->|
+ * | | |
+ *
+ *
+ * We have some issues we must now address:
+ *
+ * (1) The *ideal* sample delay time must not be negative. If it is, we
+ * jam it to zero.
+ *
+ * (2) The *ideal* sample delay time must not be greater than that
+ * allowed by the NFC. If it is, we can increase the data setup
+ * time, which will reduce the delay between the end of the data
+ * setup and the center of the eye. It will also make the eye
+ * larger, which might help with the next issue...
+ *
+ * (3) The *quantized* sample delay time must not fall either before the
+ * eye opens or after it closes (the latter is the problem
+ * illustrated in the above figure).
+ */
+
+ /* Jam a negative ideal sample delay to zero. */
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+
+ /*
+ * Extend the data setup as needed to reduce the ideal sample delay
+ * below the maximum permitted by the NFC.
+ */
+ while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+ /* Give a cycle to data setup. */
+ data_setup_in_cycles++;
+ /* Synchronize the data setup time with the cycles. */
+ data_setup_in_ns += clock_period_in_ns;
+ /* Adjust tEYE accordingly. */
+ tEYE += clock_period_in_ns;
+
+ /*
+ * Decrease the ideal sample delay by one half cycle, to keep it
+ * in the middle of the eye.
+ */
+ ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+ /* Jam a negative ideal sample delay to zero. */
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+ }
+
+ /*
+ * Compute the sample delay factor that corresponds to the ideal sample
+ * delay. If the result is too large, then use the maximum allowed
+ * value.
+ *
+ * Notice that we use the ns_to_cycles function to compute the sample
+ * delay factor. We do this because the form of the computation is the
+ * same as that for calculating cycles.
+ */
+ sample_delay_factor =
+ ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
+ clock_period_in_ns, 0);
+
+ if (sample_delay_factor > nfc->max_sample_delay_factor)
+ sample_delay_factor = nfc->max_sample_delay_factor;
+
+ /*
+ * These macros conveniently encapsulate a computation we'll use to
+ * continuously evaluate whether or not the data sample delay is inside
+ * the eye.
+ */
+ #define IDEAL_DELAY ((int) ideal_sample_delay_in_ns)
+
+ #define QUANTIZED_DELAY \
+ ((int) ((sample_delay_factor * clock_period_in_ns) >> \
+ dll_delay_shift))
+
+ #define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY))
+
+ #define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1))
+
+ /*
+ * While the quantized sample time falls outside the eye, reduce the
+ * sample delay or extend the data setup to move the sampling point back
+ * toward the eye. Do not allow the number of data setup cycles to
+ * exceed the maximum allowed by the NFC.
+ */
+ while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+ /*
+ * If control arrives here, the quantized sample delay falls
+ * outside the eye. Check if it's before the eye opens, or after
+ * the eye closes.
+ */
+ if (QUANTIZED_DELAY > IDEAL_DELAY) {
+ /*
+ * If control arrives here, the quantized sample delay
+ * falls after the eye closes. Decrease the quantized
+ * delay time and then go back to re-evaluate.
+ */
+ if (sample_delay_factor != 0)
+ sample_delay_factor--;
+ continue;
+ }
+
+ /*
+ * If control arrives here, the quantized sample delay falls
+ * before the eye opens. Shift the sample point by increasing
+ * data setup time. This will also make the eye larger.
+ */
+
+ /* Give a cycle to data setup. */
+ data_setup_in_cycles++;
+ /* Synchronize the data setup time with the cycles. */
+ data_setup_in_ns += clock_period_in_ns;
+ /* Adjust tEYE accordingly. */
+ tEYE += clock_period_in_ns;
+
+ /*
+ * Decrease the ideal sample delay by one half cycle, to keep it
+ * in the middle of the eye.
+ */
+ ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+ /* ...and one less period for the delay time. */
+ ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+ /* Jam a negative ideal sample delay to zero. */
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+
+ /*
+ * We have a new ideal sample delay, so re-compute the quantized
+ * delay.
+ */
+ sample_delay_factor =
+ ns_to_cycles(
+ ideal_sample_delay_in_ns << dll_delay_shift,
+ clock_period_in_ns, 0);
+
+ if (sample_delay_factor > nfc->max_sample_delay_factor)
+ sample_delay_factor = nfc->max_sample_delay_factor;
+ }
+
+ /* Control arrives here when we're ready to return our results. */
+return_results:
+ hw->data_setup_in_cycles = data_setup_in_cycles;
+ hw->data_hold_in_cycles = data_hold_in_cycles;
+ hw->address_setup_in_cycles = address_setup_in_cycles;
+ hw->use_half_periods = dll_use_half_periods;
+ hw->sample_delay_factor = sample_delay_factor;
+
+ /* Return success. */
+ return 0;
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/mil.c b/drivers/mtd/nand/gpmi-nfc/mil.c
new file mode 100644
index 0000000..defd19e
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/mil.c
@@ -0,0 +1,1104 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include "gpmi-nfc.h"
+#include "linux/slab.h"
+
+/* add our owner bbt descriptor */
+static uint8_t scan_ff_pattern[] = { 0xff };
+static struct nand_bbt_descr gpmi_bbt_descr = {
+ .options = 0,
+ .offs = 0,
+ .len = 1,
+ .pattern = scan_ff_pattern
+};
+
+static int read_page_prepare(struct gpmi_nfc_data *this,
+ void *destination, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ void **use_virt, dma_addr_t *use_phys)
+{
+ struct device *dev = this->dev;
+ dma_addr_t destination_phys = ~0;
+
+ if (virt_addr_valid(destination))
+ destination_phys = dma_map_single(dev, (void *)destination,
+ length, DMA_FROM_DEVICE);
+
+ if (dma_mapping_error(dev, destination_phys)) {
+ if (alt_size < length) {
+ log("Alternate buffer is too small for incoming I/O.");
+ return -ENOMEM;
+ }
+
+ *use_virt = alt_virt;
+ *use_phys = alt_phys;
+ } else {
+ *use_virt = destination;
+ *use_phys = destination_phys;
+ }
+ return 0;
+}
+
+static void read_page_end(struct gpmi_nfc_data *this,
+ void *destination, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ void *used_virt, dma_addr_t used_phys)
+{
+ struct device *dev = this->dev;
+
+ if (used_virt == destination)
+ dma_unmap_single(dev, used_phys, length, DMA_FROM_DEVICE);
+ else
+ memcpy(destination, alt_virt, length);
+}
+
+static int send_page_prepare(struct gpmi_nfc_data *this,
+ const void *source, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ const void **use_virt, dma_addr_t *use_phys)
+{
+ dma_addr_t source_phys = ~0;
+ struct device *dev = this->dev;
+
+ if (virt_addr_valid(source))
+ source_phys = dma_map_single(dev,
+ (void *)source, length, DMA_TO_DEVICE);
+
+ if (dma_mapping_error(dev, source_phys)) {
+ if (alt_size < length) {
+ log("Alternate buffer is too small for outgoing I/O");
+ return -ENOMEM;
+ }
+
+ /*
+ * Copy the contents of the source buffer into the alternate
+ * buffer and set up the return values accordingly.
+ */
+ memcpy(alt_virt, source, length);
+
+ *use_virt = alt_virt;
+ *use_phys = alt_phys;
+ } else {
+ *use_virt = source;
+ *use_phys = source_phys;
+ }
+ return 0;
+}
+
+static void send_page_end(struct gpmi_nfc_data *this,
+ const void *source, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ const void *used_virt, dma_addr_t used_phys)
+{
+ struct device *dev = this->dev;
+ if (used_virt == source)
+ dma_unmap_single(dev, used_phys, length, DMA_TO_DEVICE);
+}
+
+static void mil_free_dma_buffer(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+
+ if (mil->page_buffer_virt && virt_addr_valid(mil->page_buffer_virt))
+ dma_free_coherent(dev, mil->page_buffer_size,
+ mil->page_buffer_virt,
+ mil->page_buffer_phys);
+ kfree(mil->cmd_buffer);
+ kfree(mil->data_buffer_dma);
+
+ mil->cmd_buffer = NULL;
+ mil->data_buffer_dma = NULL;
+ mil->page_buffer_virt = NULL;
+ mil->page_buffer_size = 0;
+ mil->page_buffer_phys = ~0;
+}
+
+/* Allocate the DMA buffers */
+static int mil_alloc_dma_buffer(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ struct mil *mil = &this->mil;
+
+ /* [1] Allocate a command buffer. PAGE_SIZE is enough. */
+ mil->cmd_buffer = kzalloc(PAGE_SIZE, GFP_DMA);
+ if (mil->cmd_buffer == NULL)
+ goto error_alloc;
+ sg_init_one(&mil->cmd_sgl, mil->cmd_buffer, PAGE_SIZE);
+
+ /* [2] Allocate a read/write data buffer. PAGE_SIZE is enough. */
+ mil->data_buffer_dma = kzalloc(PAGE_SIZE, GFP_DMA);
+ if (mil->data_buffer_dma == NULL)
+ goto error_alloc;
+
+ /*
+ * [3] Allocate the page buffer.
+ *
+ * Both the payload buffer and the auxiliary buffer must appear on
+ * 32-bit boundaries. We presume the size of the payload buffer is a
+ * power of two and is much larger than four, which guarantees the
+ * auxiliary buffer will appear on a 32-bit boundary.
+ */
+ mil->page_buffer_size = geo->payload_size_in_bytes +
+ geo->auxiliary_size_in_bytes;
+
+ mil->page_buffer_virt = dma_alloc_coherent(dev, mil->page_buffer_size,
+ &mil->page_buffer_phys, GFP_DMA);
+ if (!mil->page_buffer_virt)
+ goto error_alloc;
+
+
+ /* Slice up the page buffer. */
+ mil->payload_virt = mil->page_buffer_virt;
+ mil->payload_phys = mil->page_buffer_phys;
+ mil->auxiliary_virt = ((char *) mil->payload_virt) +
+ geo->payload_size_in_bytes;
+ mil->auxiliary_phys = mil->payload_phys +
+ geo->payload_size_in_bytes;
+ return 0;
+
+error_alloc:
+ mil_free_dma_buffer(this);
+ log("allocate DMA buffer error!!");
+ return -ENOMEM;
+}
+
+static void mil_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct mil *mil = &this->mil;
+ struct nfc_hal *nfc = this->nfc;
+ int error;
+
+ /*
+ * Every operation begins with a command byte and a series of zero or
+ * more address bytes. These are distinguished by either the Address
+ * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
+ * asserted. When MTD is ready to execute the command, it will deassert
+ * both latch enables.
+ *
+ * Rather than run a separate DMA operation for every single byte, we
+ * queue them up and run a single DMA operation for the entire series
+ * of command and data bytes. NAND_CMD_NONE means the END of the queue.
+ */
+ if ((ctrl & (NAND_ALE | NAND_CLE))) {
+ if (data != NAND_CMD_NONE)
+ mil->cmd_buffer[mil->command_length++] = data;
+ return;
+ }
+
+ if (!mil->command_length)
+ return;
+
+ error = nfc->send_command(this);
+ if (error)
+ log("Chip: %u, Error %d", mil->current_chip, error);
+
+ mil->command_length = 0;
+}
+
+static int mil_dev_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ return nfc->is_ready(this, mil->current_chip);
+}
+
+static void mil_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct mil *mil = &this->mil;
+ struct nfc_hal *nfc = this->nfc;
+
+ if ((mil->current_chip < 0) && (chip >= 0))
+ nfc->begin(this);
+ else if ((mil->current_chip >= 0) && (chip < 0))
+ nfc->end(this);
+ else
+ ;
+
+ mil->current_chip = chip;
+}
+
+static void mil_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ /* save the info in mil{} for future */
+ mil->upper_buf = buf;
+ mil->upper_len = len;
+
+ nfc->read_data(this);
+}
+
+static void mil_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ /* save the info in mil{} for future */
+ mil->upper_buf = (uint8_t *)buf;
+ mil->upper_len = len;
+
+ nfc->send_data(this);
+}
+
+static uint8_t mil_read_byte(struct mtd_info *mtd)
+{
+ uint8_t byte = 0;
+ mil_read_buf(mtd, (uint8_t *)&byte, 1);
+ return byte;
+}
+
+/**
+ * mil_handle_block_mark_swapping() - Handles block mark swapping.
+ *
+ * Note that, when this function is called, it doesn't know whether it's
+ * swapping the block mark, or swapping it *back* -- but it doesn't matter
+ * because the the operation is the same.
+ *
+ * @this: Per-device data.
+ * @payload: A pointer to the payload buffer.
+ * @auxiliary: A pointer to the auxiliary buffer.
+ */
+static void mil_handle_block_mark_swapping(struct gpmi_nfc_data *this,
+ void *payload, void *auxiliary)
+{
+ struct nfc_geometry *nfc_geo = &this->nfc_geometry;
+ struct boot_rom_helper *rom = this->rom;
+ unsigned char *p;
+ unsigned char *a;
+ unsigned int bit;
+ unsigned char mask;
+ unsigned char from_data;
+ unsigned char from_oob;
+
+ /* Check if we're doing block mark swapping. */
+ if (!rom->swap_block_mark)
+ return;
+
+ /*
+ * If control arrives here, we're swapping. Make some convenience
+ * variables.
+ */
+ bit = nfc_geo->block_mark_bit_offset;
+ p = ((unsigned char *) payload) + nfc_geo->block_mark_byte_offset;
+ a = auxiliary;
+
+ /*
+ * Get the byte from the data area that overlays the block mark. Since
+ * the ECC engine applies its own view to the bits in the page, the
+ * physical block mark won't (in general) appear on a byte boundary in
+ * the data.
+ */
+ from_data = (p[0] >> bit) | (p[1] << (8 - bit));
+
+ /* Get the byte from the OOB. */
+ from_oob = a[0];
+
+ /* Swap them. */
+ a[0] = from_data;
+
+ mask = (0x1 << bit) - 1;
+ p[0] = (p[0] & mask) | (from_oob << bit);
+
+ mask = ~0 << bit;
+ p[1] = (p[1] & mask) | (from_oob >> (8 - bit));
+}
+
+static int mil_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
+ uint8_t *buf, int page)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct nfc_geometry *nfc_geo = &this->nfc_geometry;
+ struct mil *mil = &this->mil;
+ void *payload_virt = 0;
+ dma_addr_t payload_phys = ~0;
+ void *auxiliary_virt = 0;
+ dma_addr_t auxiliary_phys = ~0;
+ unsigned int i;
+ unsigned char *status;
+ unsigned int failed;
+ unsigned int corrected;
+ int error = 0;
+
+ error = read_page_prepare(this, buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ &payload_virt, &payload_phys);
+ if (error) {
+ log("Inadequate DMA buffer");
+ error = -ENOMEM;
+ return error;
+ }
+ auxiliary_virt = mil->auxiliary_virt;
+ auxiliary_phys = mil->auxiliary_phys;
+
+ /* ask the NFC */
+ error = nfc->read_page(this, payload_phys, auxiliary_phys);
+ if (error) {
+ log("Error in ECC-based read: %d", error);
+ goto exit_nfc;
+ }
+
+ /* handle the block mark swapping */
+ mil_handle_block_mark_swapping(this, payload_virt, auxiliary_virt);
+
+ /* Loop over status bytes, accumulating ECC status. */
+ failed = 0;
+ corrected = 0;
+ status = ((unsigned char *) auxiliary_virt) +
+ nfc_geo->auxiliary_status_offset;
+
+ for (i = 0; i < nfc_geo->ecc_chunk_count; i++, status++) {
+ if ((*status == STATUS_GOOD) || (*status == STATUS_ERASED))
+ continue;
+
+ if (*status == STATUS_UNCORRECTABLE) {
+ failed++;
+ continue;
+ }
+ corrected += *status;
+ }
+
+ /*
+ * Propagate ECC status to the owning MTD only when failed or
+ * corrected times nearly reaches our ECC correction threshold.
+ */
+ if (failed || corrected >= (nfc_geo->ecc_strength - 1)) {
+ mtd->ecc_stats.failed += failed;
+ mtd->ecc_stats.corrected += corrected;
+ }
+
+ /*
+ * It's time to deliver the OOB bytes. See mil_ecc_read_oob() for
+ * details about our policy for delivering the OOB.
+ *
+ * We fill the caller's buffer with set bits, and then copy the block
+ * mark to th caller's buffer. Note that, if block mark swapping was
+ * necessary, it has already been done, so we can rely on the first
+ * byte of the auxiliary buffer to contain the block mark.
+ */
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+ nand->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0];
+
+exit_nfc:
+ read_page_end(this, buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ payload_virt, payload_phys);
+ return error;
+}
+
+static void mil_ecc_write_page(struct mtd_info *mtd,
+ struct nand_chip *nand, const uint8_t *buf)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct nfc_geometry *nfc_geo = &this->nfc_geometry;
+ struct boot_rom_helper *rom = this->rom;
+ struct mil *mil = &this->mil;
+ const void *payload_virt = 0;
+ dma_addr_t payload_phys = ~0;
+ const void *auxiliary_virt = 0;
+ dma_addr_t auxiliary_phys = ~0;
+ int error;
+
+ if (rom->swap_block_mark) {
+ /*
+ * If control arrives here, we're doing block mark swapping.
+ * Since we can't modify the caller's buffers, we must copy them
+ * into our own.
+ */
+ memcpy(mil->payload_virt, buf, mtd->writesize);
+ payload_virt = mil->payload_virt;
+ payload_phys = mil->payload_phys;
+
+ memcpy(mil->auxiliary_virt, nand->oob_poi,
+ nfc_geo->auxiliary_size_in_bytes);
+ auxiliary_virt = mil->auxiliary_virt;
+ auxiliary_phys = mil->auxiliary_phys;
+
+ /* Handle block mark swapping. */
+ mil_handle_block_mark_swapping(this,
+ (void *) payload_virt, (void *) auxiliary_virt);
+ } else {
+ /*
+ * If control arrives here, we're not doing block mark swapping,
+ * so we can to try and use the caller's buffers.
+ */
+ error = send_page_prepare(this,
+ buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ &payload_virt, &payload_phys);
+ if (error) {
+ log("Inadequate payload DMA buffer");
+ return;
+ }
+
+ error = send_page_prepare(this,
+ nand->oob_poi, mtd->oobsize,
+ mil->auxiliary_virt, mil->auxiliary_phys,
+ nfc_geo->auxiliary_size_in_bytes,
+ &auxiliary_virt, &auxiliary_phys);
+ if (error) {
+ log("Inadequate auxiliary DMA buffer");
+ goto exit_auxiliary;
+ }
+ }
+
+ /* Ask the NFC. */
+ error = nfc->send_page(this, payload_phys, auxiliary_phys);
+ if (error)
+ log("Error in ECC-based write: %d", error);
+
+ if (!rom->swap_block_mark) {
+ send_page_end(this, nand->oob_poi, mtd->oobsize,
+ mil->auxiliary_virt, mil->auxiliary_phys,
+ nfc_geo->auxiliary_size_in_bytes,
+ auxiliary_virt, auxiliary_phys);
+exit_auxiliary:
+ send_page_end(this, buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ payload_virt, payload_phys);
+ }
+}
+
+/**
+ * mil_hook_block_markbad() - Hooked MTD Interface block_markbad().
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code. See the description of the marking_a_bad_block field
+ * in struct mil for more information about this.
+ *
+ * @mtd: A pointer to the MTD.
+ * @ofs: Byte address of the block to mark.
+ */
+static int mil_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ register struct nand_chip *chip = mtd->priv;
+ struct gpmi_nfc_data *this = chip->priv;
+ struct mil *mil = &this->mil;
+ int ret;
+
+ mil->marking_a_bad_block = true;
+ ret = mil->hooked_block_markbad(mtd, ofs);
+ mil->marking_a_bad_block = false;
+ return ret;
+}
+
+/**
+ * mil_ecc_read_oob() - MTD Interface ecc.read_oob().
+ *
+ * There are several places in this driver where we have to handle the OOB and
+ * block marks. This is the function where things are the most complicated, so
+ * this is where we try to explain it all. All the other places refer back to
+ * here.
+ *
+ * These are the rules, in order of decreasing importance:
+ *
+ * 1) Nothing the caller does can be allowed to imperil the block mark, so all
+ * write operations take measures to protect it.
+ *
+ * 2) In read operations, the first byte of the OOB we return must reflect the
+ * true state of the block mark, no matter where that block mark appears in
+ * the physical page.
+ *
+ * 3) ECC-based read operations return an OOB full of set bits (since we never
+ * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
+ * return).
+ *
+ * 4) "Raw" read operations return a direct view of the physical bytes in the
+ * page, using the conventional definition of which bytes are data and which
+ * are OOB. This gives the caller a way to see the actual, physical bytes
+ * in the page, without the distortions applied by our ECC engine.
+ *
+ *
+ * What we do for this specific read operation depends on two questions:
+ *
+ * 1) Are we doing a "raw" read, or an ECC-based read?
+ *
+ * 2) Are we using block mark swapping or transcription?
+ *
+ * There are four cases, illustrated by the following Karnaugh map:
+ *
+ * | Raw | ECC-based |
+ * -------------+-------------------------+-------------------------+
+ * | Read the conventional | |
+ * | OOB at the end of the | |
+ * Swapping | page and return it. It | |
+ * | contains exactly what | |
+ * | we want. | Read the block mark and |
+ * -------------+-------------------------+ return it in a buffer |
+ * | Read the conventional | full of set bits. |
+ * | OOB at the end of the | |
+ * | page and also the block | |
+ * Transcribing | mark in the metadata. | |
+ * | Copy the block mark | |
+ * | into the first byte of | |
+ * | the OOB. | |
+ * -------------+-------------------------+-------------------------+
+ *
+ * Note that we break rule #4 in the Transcribing/Raw case because we're not
+ * giving an accurate view of the actual, physical bytes in the page (we're
+ * overwriting the block mark). That's OK because it's more important to follow
+ * rule #2.
+ *
+ * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
+ * easy. When reading a page, for example, the NAND Flash MTD code calls our
+ * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
+ * ECC-based or raw view of the page is implicit in which function it calls
+ * (there is a similar pair of ECC-based/raw functions for writing).
+ *
+ * Since MTD assumes the OOB is not covered by ECC, there is no pair of
+ * ECC-based/raw functions for reading or or writing the OOB. The fact that the
+ * caller wants an ECC-based or raw view of the page is not propagated down to
+ * this driver.
+ *
+ * @mtd: A pointer to the owning MTD.
+ * @nand: A pointer to the owning NAND Flash MTD.
+ * @page: The page number to read.
+ * @sndcmd: Indicates this function should send a command to the chip before
+ * reading the out-of-band bytes. This is only false for small page
+ * chips that support auto-increment.
+ */
+static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
+ int page, int sndcmd)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct boot_rom_helper *rom = this->rom;
+
+ /* clear the OOB buffer */
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+
+ /* Read out the conventional OOB. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+ nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
+
+ /*
+ * Now, we want to make sure the block mark is correct. In the
+ * Swapping/Raw case, we already have it. Otherwise, we need to
+ * explicitly read it.
+ */
+ if (!rom->swap_block_mark) {
+ /* Read the block mark into the first byte of the OOB buffer. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+ nand->oob_poi[0] = nand->read_byte(mtd);
+ }
+
+ /*
+ * Return true, indicating that the next call to this function must send
+ * a command.
+ */
+ return true;
+}
+
+static int mil_ecc_write_oob(struct mtd_info *mtd,
+ struct nand_chip *nand, int page)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+ struct boot_rom_helper *rom = this->rom;
+ uint8_t block_mark = 0;
+ int block_mark_column;
+ int status;
+ int error = 0;
+
+ /*
+ * There are fundamental incompatibilities between the i.MX GPMI NFC and
+ * the NAND Flash MTD model that make it essentially impossible to write
+ * the out-of-band bytes.
+ *
+ * We permit *ONE* exception. If the *intent* of writing the OOB is to
+ * mark a block bad, we can do that.
+ */
+ if (!mil->marking_a_bad_block) {
+ dev_emerg(dev, "This driver doesn't support writing the OOB\n");
+ WARN_ON(1);
+ error = -EIO;
+ goto exit;
+ }
+
+ /*
+ * If control arrives here, we're marking a block bad. First, figure out
+ * where the block mark is.
+ *
+ * If we're using swapping, the block mark is in the conventional
+ * location. Otherwise, we're using transcription, and the block mark
+ * appears in the first byte of the page.
+ */
+ if (rom->swap_block_mark)
+ block_mark_column = mtd->writesize;
+ else
+ block_mark_column = 0;
+
+ /* Write the block mark. */
+ nand->cmdfunc(mtd, NAND_CMD_SEQIN, block_mark_column, page);
+ nand->write_buf(mtd, &block_mark, 1);
+ nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = nand->waitfunc(mtd, nand);
+
+ /* Check if it worked. */
+ if (status & NAND_STATUS_FAIL)
+ error = -EIO;
+exit:
+ return error;
+}
+
+/**
+ * mil_block_bad - Claims all blocks are good.
+ *
+ * In principle, this function is *only* called when the NAND Flash MTD system
+ * isn't allowed to keep an in-memory bad block table, so it is forced to ask
+ * the driver for bad block information.
+ *
+ * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
+ * this function is *only* called when we take it away.
+ *
+ * We take away the in-memory BBT when the user sets the "ignorebad" parameter,
+ * which indicates that all blocks should be reported good.
+ *
+ * Thus, this function is only called when we want *all* blocks to look good,
+ * so it *always* return success.
+ *
+ * @mtd: Ignored.
+ * @ofs: Ignored.
+ * @getchip: Ignored.
+ */
+static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+ return 0;
+}
+
+/* Set up the Boot ROM Helper geometry. */
+static int mil_set_boot_rom_helper_geometry(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_helper *rom = this->rom;
+ struct boot_rom_geometry *geo = &this->rom_geometry;
+
+ if (rom->set_geometry(this))
+ return !0;
+
+ pr_info("--------------------------------------------\n");
+ pr_info(" Boot ROM Geometry\n");
+ pr_info("--------------------------------------------\n");
+ pr_info("Boot Area Count : %u\n", geo->boot_area_count);
+ pr_info("Boot Area Size in Bytes : %u (0x%x)\n",
+ geo->boot_area_size_in_bytes,
+ geo->boot_area_size_in_bytes);
+ pr_info("Stride Size in Pages : %u\n", geo->stride_size_in_pages);
+ pr_info("Search Area Stride Exponent: %u\n",
+ geo->search_area_stride_exponent);
+ return 0;
+}
+
+static int mil_set_geometry(struct gpmi_nfc_data *this)
+{
+ struct nfc_hal *nfc = this->nfc;
+ struct nfc_geometry *geo = &this->nfc_geometry;
+
+ /* Free the temporary DMA memory for read ID case */
+ mil_free_dma_buffer(this);
+
+ /* Set up the NFC geometry which is used by BCH. */
+ if (nfc->set_geometry(this))
+ return -ENXIO;
+ pr_info("---------------------------------------\n");
+ pr_info(" NFC Geometry (used by BCH)\n");
+ pr_info("---------------------------------------\n");
+ pr_info("ECC Algorithm : %s\n", geo->ecc_algorithm);
+ pr_info("ECC Strength : %u\n", geo->ecc_strength);
+ pr_info("Page Size in Bytes : %u\n", geo->page_size_in_bytes);
+ pr_info("Metadata Size in Bytes : %u\n", geo->metadata_size_in_bytes);
+ pr_info("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size_in_bytes);
+ pr_info("ECC Chunk Count : %u\n", geo->ecc_chunk_count);
+ pr_info("Payload Size in Bytes : %u\n", geo->payload_size_in_bytes);
+ pr_info("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size_in_bytes);
+ pr_info("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
+ pr_info("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
+ pr_info("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset);
+
+ /* Alloc the new DMA buffers according to the pagesize and oobsize */
+ return mil_alloc_dma_buffer(this);
+}
+
+static int mil_pre_bbt_scan(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_helper *rom = this->rom;
+ int error = 0;
+
+ if (mil_set_boot_rom_helper_geometry(this))
+ return -ENXIO;
+
+ /* This is ROM arch-specific initilization before the BBT scanning. */
+ if (rom->rom_extra_init)
+ error = rom->rom_extra_init(this);
+ return error;
+}
+
+static int mil_scan_bbt(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ int error;
+
+ /* Prepare for the BBT scan. */
+ error = mil_pre_bbt_scan(this);
+ if (error)
+ return error;
+
+ /* use the default BBT implementation */
+ return nand_default_bbt(mtd);
+}
+
+static int mil_boot_areas_init(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+
+ if (rom->boot_area_count == 0) {
+ mil->general_use_mtd = &mil->mtd;
+ pr_info("There is no Boot area.\n");
+ } else if (rom->boot_area_count == 1) {
+ static char *chip_0_boot_name = "gpmi-nfc-0-boot";
+ static char *general_use_name = "gpmi-nfc-general-use";
+ struct mtd_partition partitions[2];
+
+ pr_info("Boot area protection is enabled.\n");
+ /*
+ * We partition the medium like so:
+ *
+ * +------+----------------------------------------------------+
+ * | Boot | General Use |
+ * +------+----------------------------------------------------+
+ */
+
+ /* Chip 0 Boot */
+ partitions[0].name = chip_0_boot_name;
+ partitions[0].offset = 0;
+ partitions[0].size = rom->boot_area_size_in_bytes;
+ partitions[0].mask_flags = 0;
+
+ /* General Use */
+ partitions[1].name = general_use_name;
+ partitions[1].offset = rom->boot_area_size_in_bytes;
+ partitions[1].size = MTDPART_SIZ_FULL;
+ partitions[1].mask_flags = 0;
+
+ /* Construct and register the partitions. */
+ add_mtd_partitions(mtd, partitions, 2);
+
+ /* Find the general use MTD. */
+ mil->general_use_mtd = get_mtd_device_nm(general_use_name);
+ if (IS_ERR(mil->general_use_mtd)) {
+ log("Can't find general use MTD");
+ BUG();
+ }
+ } else {
+ log("Boot area count greater than one is unimplemented.");
+ return -ENXIO;
+ }
+ return 0;
+}
+
+static void mil_boot_areas_exit(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+
+ if (!rom->boot_area_count) {
+ mil->general_use_mtd = NULL;
+ return;
+ }
+ del_mtd_partitions(mtd);
+ mil->general_use_mtd = NULL;
+}
+
+static int construct_general_use_partitions(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+ unsigned int partition_count;
+ struct mtd_partition *partitions;
+ unsigned int name_size;
+ char *names;
+ unsigned int size;
+ unsigned int i;
+ static const char *name_prefix = "gpmi-nfc-ubi-";
+
+ /* Only handle the MTD which is larger than 2GiB. */
+ if (mil->general_use_mtd->size <= SZ_2G)
+ return 0;
+
+ /* Split it by 2G for historical reason*/
+ partition_count = mil->general_use_mtd->size >> 31;
+ if (mil->general_use_mtd->size & ((1 << 30) - 1))
+ partition_count++;
+
+ /* construct the partitions */
+ name_size = strlen(name_prefix) + 4;
+ size = (sizeof(*partitions) + name_size) * partition_count;
+ partitions = kzalloc(size, GFP_KERNEL);
+ if (!partitions) {
+ log("Could not allocate memory for UBI partitions.");
+ return -ENOMEM;
+ }
+
+ names = (char *)(partitions + partition_count);
+ for (i = 0; i < partition_count; i++) {
+ partitions[i].name = names;
+ partitions[i].size = SZ_2G;
+ partitions[i].offset = MTDPART_OFS_NXTBLK;
+
+ sprintf(names, "%s%u", name_prefix, i);
+ names += name_size;
+ }
+ /* Adjust the last partition to take up the remainder. */
+ partitions[i - 1].size = MTDPART_SIZ_FULL;
+
+ mil->partitions = partitions;
+ mil->partition_count = partition_count;
+ return 0;
+}
+
+static int mil_partitions_init(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+ int error;
+
+ error = mil_boot_areas_init(this);
+ if (error)
+ return error;
+
+ /* Construct partitions */
+ error = construct_general_use_partitions(this);
+ if (error) {
+ log("error : %d", error);
+ return error;
+ }
+ if (mil->partition_count)
+ add_mtd_partitions(mil->general_use_mtd, mil->partitions,
+ mil->partition_count);
+ return 0;
+}
+
+static void mil_partitions_exit(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+
+ if (mil->partition_count) {
+ del_mtd_partitions(mil->general_use_mtd);
+ kfree(mil->partitions);
+ mil->partition_count = 0;
+ }
+ mil_boot_areas_exit(this);
+}
+
+/*
+ * This function is used to set the mtd->pagesize, mtd->oobsize,
+ * mtd->erasesize. Yes, we also do some initialization.
+ *
+ * Return with the bus width. 0 for 8-bit, -1 for error.
+ */
+static int gpmi_init_size(struct mtd_info *mtd, struct nand_chip *nand,
+ u8 *id_bytes)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+ struct nand_ecclayout *layout = &mil->oob_layout;
+ struct nand_device_info *info;
+ struct nand_attr *attr;
+ int error;
+
+ /* Look up this device in our own database. */
+ info = nand_device_get_info(id_bytes);
+ if (!info) {
+ pr_err("Unrecognized NAND Flash device.\n");
+ return -1;
+ }
+
+ attr = &info->attr;
+ /*
+ * Init the right NAND/MTD parameters which will be used
+ * in the following mil_set_geometry().
+ */
+ mtd->writesize = 1 << (fls(attr->page_total_size_in_bytes) - 1);
+ mtd->erasesize = mtd->writesize * attr->block_size_in_pages;
+ mtd->oobsize = attr->page_total_size_in_bytes - mtd->writesize;
+ nand->chipsize = attr->chip_size_in_bytes;
+
+ /* Configure the struct nand_ecclayout. */
+ layout->eccbytes = 0;
+ layout->oobavail = mtd->oobsize;
+ layout->oobfree[0].offset = 0;
+ layout->oobfree[0].length = mtd->oobsize;
+
+ nand->ecc.layout = layout;
+
+ /*
+ * Copy the device info into the per-device data. We can't just keep
+ * the pointer because that storage is reclaimed after initialization.
+ */
+ this->device_info = *info;
+ this->device_info.desc = kstrdup(info->desc, GFP_KERNEL);
+
+ /* Set up the medium geometry */
+ error = mil_set_geometry(this);
+ if (error)
+ return -1;
+
+ /* Set up timing. */
+ error = nfc->set_timing(this, &info->timing);
+ if (error)
+ return -1;
+
+ if (nfc->extra_init) {
+ error = nfc->extra_init(this);
+ if (error != 0)
+ return -1;
+ }
+
+ /* We only use 8-bit bus now, not 16-bit. */
+ return 0;
+}
+
+/* Initializes the MTD Interface Layer */
+int gpmi_nfc_mil_init(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ int error = 0;
+
+ /* Initialize MIL data */
+ mil->current_chip = -1;
+ mil->command_length = 0;
+ mil->page_buffer_virt = 0;
+ mil->page_buffer_phys = ~0;
+ mil->page_buffer_size = 0;
+
+ /* Initialize the MTD data structures */
+ mtd->priv = nand;
+ mtd->name = "gpmi-nfc-main";
+ mtd->owner = THIS_MODULE;
+ nand->priv = this;
+
+ /* Controls */
+ nand->select_chip = mil_select_chip;
+ nand->cmd_ctrl = mil_cmd_ctrl;
+ nand->dev_ready = mil_dev_ready;
+
+ /*
+ * Low-level I/O :
+ * We don't support a 16-bit NAND Flash bus,
+ * so we don't implement read_word.
+ */
+ nand->read_byte = mil_read_byte;
+ nand->read_buf = mil_read_buf;
+ nand->write_buf = mil_write_buf;
+
+ /* ECC-aware I/O */
+ nand->ecc.read_page = mil_ecc_read_page;
+ nand->ecc.write_page = mil_ecc_write_page;
+
+ /* High-level I/O */
+ nand->ecc.read_oob = mil_ecc_read_oob;
+ nand->ecc.write_oob = mil_ecc_write_oob;
+
+ /* Bad Block Management */
+ nand->block_bad = mil_block_bad;
+ nand->scan_bbt = mil_scan_bbt;
+ nand->init_size = gpmi_init_size;
+ nand->badblock_pattern = &gpmi_bbt_descr;
+
+ /* Disallow partial page writes */
+ nand->options |= NAND_NO_SUBPAGE_WRITE;
+
+ /*
+ * Tell the NAND Flash MTD system that we'll be handling ECC with our
+ * own hardware. It turns out that we still have to fill in the ECC size
+ * because the MTD code will divide by it -- even though it doesn't
+ * actually care.
+ */
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.size = 1;
+
+ /* Allocate a temporary DMA buffer for reading ID in the nand_scan() */
+ this->nfc_geometry.payload_size_in_bytes = 1024;
+ this->nfc_geometry.auxiliary_size_in_bytes = 128;
+ error = mil_alloc_dma_buffer(this);
+ if (error)
+ goto exit_dma_allocation;
+
+ pr_info("Scanning for NAND Flash chips...\n");
+ error = nand_scan(mtd, pdata->max_chip_count);
+ if (error) {
+ log("Chip scan failed");
+ goto exit_nand_scan;
+ }
+
+ /* Take over the management of the OOB */
+ mil->hooked_block_markbad = mtd->block_markbad;
+ mtd->block_markbad = mil_hook_block_markbad;
+
+ /* Construct partitions as necessary. */
+ error = mil_partitions_init(this);
+ if (error)
+ goto exit_partitions;
+ return 0;
+
+exit_partitions:
+ nand_release(&mil->mtd);
+exit_nand_scan:
+ mil_free_dma_buffer(this);
+exit_dma_allocation:
+ return error;
+}
+
+void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+
+ mil_partitions_exit(this);
+ nand_release(&mil->mtd);
+ mil_free_dma_buffer(this);
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-common.c b/drivers/mtd/nand/gpmi-nfc/rom-common.c
new file mode 100644
index 0000000..6d11447
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-common.c
@@ -0,0 +1,48 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+
+ /*
+ * Set the boot block stride size.
+ *
+ * In principle, we should be reading this from the OTP bits, since
+ * that's where the ROM is going to get it. In fact, we don't have any
+ * way to read the OTP bits, so we go with the default and hope for the
+ * best.
+ */
+ geometry->stride_size_in_pages = 64;
+
+ /*
+ * Set the search area stride exponent.
+ *
+ * In principle, we should be reading this from the OTP bits, since
+ * that's where the ROM is going to get it. In fact, we don't have any
+ * way to read the OTP bits, so we go with the default and hope for the
+ * best.
+ */
+ geometry->search_area_stride_exponent = 2;
+
+ return 0;
+}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 2/7] add the common code for GPMI driver
@ 2011-03-16 1:55 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel
These files contain the common code for the GPMI driver.
gpmi-nfc-main.c : the main file of GPMI
mil.c : the MTD interface layer of GPMI
hal-common.c : the hardware abstract layer of GPMI
rom-common.c : the NAND boot support of GPMI
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/Makefile | 10 +
drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c | 524 ++++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h | 520 ++++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-common.c | 816 +++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/mil.c | 1104 +++++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/rom-common.c | 48 ++
6 files changed, 3022 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/Makefile
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-common.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/mil.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-common.c
diff --git a/drivers/mtd/nand/gpmi-nfc/Makefile b/drivers/mtd/nand/gpmi-nfc/Makefile
new file mode 100644
index 0000000..9026313
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/Makefile
@@ -0,0 +1,10 @@
+obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc.o
+gpmi-nfc-objs += gpmi-nfc-main.o
+gpmi-nfc-objs += hal-common.o
+gpmi-nfc-objs += hal-imx23.o
+gpmi-nfc-objs += hal-imx28.o
+gpmi-nfc-objs += rom-common.o
+gpmi-nfc-objs += rom-imx23.o
+gpmi-nfc-objs += rom-imx28.o
+gpmi-nfc-objs += mil.o
+gpmi-nfc-objs += nand_device_info.o
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
new file mode 100644
index 0000000..f22c9d5
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc-main.c
@@ -0,0 +1,524 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/slab.h>
+#include "gpmi-nfc.h"
+#include "linux/slab.h"
+
+static ssize_t show_ignorebad(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct gpmi_nfc_data *this = dev_get_drvdata(dev);
+ struct mil *mil = &this->mil;
+
+ return sprintf(buf, "%d\n", mil->ignore_bad_block_marks);
+}
+
+/* Sets the value of the 'ignorebad' flag. */
+static ssize_t
+store_ignorebad(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ struct gpmi_nfc_data *this = dev_get_drvdata(dev);
+ struct mil *mil = &this->mil;
+ const char *p = buf;
+ unsigned long v;
+
+ /* Try to make sense of what arrived from user space. */
+ if (strict_strtoul(p, 0, &v) < 0)
+ return size;
+
+ if (v > 0)
+ v = 1;
+
+ if (v != mil->ignore_bad_block_marks) {
+ if (v) {
+ /*
+ * If control arrives here, we want to begin ignoring
+ * bad block marks. Reach into the NAND Flash MTD data
+ * structures and set the in-memory BBT pointer to NULL.
+ * This will cause the NAND Flash MTD code to believe
+ * that it never created a BBT and force it to call our
+ * block_bad function.
+ *
+ * See mil_block_bad for more details.
+ */
+ mil->saved_bbt = mil->nand.bbt;
+ mil->nand.bbt = 0;
+ } else {
+ /*
+ * If control arrives here, we want to stop ignoring
+ * bad block marks. Restore the NAND Flash MTD's pointer
+ * to its in-memory BBT.
+ */
+ mil->nand.bbt = mil->saved_bbt;
+ }
+ mil->ignore_bad_block_marks = v;
+ }
+ return size;
+}
+
+/* Device attributes that appear in sysfs. */
+static DEVICE_ATTR(ignorebad, 0644, show_ignorebad, store_ignorebad);
+static struct device_attribute *device_attributes[] = {
+ &dev_attr_ignorebad,
+};
+
+static int acquire_register_block(struct gpmi_nfc_data *this,
+ const char *resource_name, void **reg_block_base)
+{
+ struct platform_device *pdev = this->pdev;
+ struct resource *r;
+ void *p;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, resource_name);
+ if (!r) {
+ log("Can't get resource information for '%s'", resource_name);
+ return -ENXIO;
+ }
+
+ /* remap the register block */
+ p = ioremap(r->start, r->end - r->start + 1);
+ if (!p) {
+ log("Can't remap %s", resource_name);
+ return -EIO;
+ }
+
+ *reg_block_base = p;
+ return 0;
+}
+
+static void release_register_block(struct gpmi_nfc_data *this,
+ void *reg_block_base)
+{
+ iounmap(reg_block_base);
+}
+
+static int acquire_interrupt(struct gpmi_nfc_data *this,
+ const char *resource_name,
+ irq_handler_t interrupt_handler, int *lno, int *hno)
+{
+ struct platform_device *pdev = this->pdev;
+ struct resource *r;
+ int err = 0;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, resource_name);
+ if (!r) {
+ log("Can't get resource information for '%s'", resource_name);
+ return -ENXIO;
+ }
+
+ BUG_ON(r->start != r->end);
+ err = request_irq(r->start, interrupt_handler, 0, resource_name, this);
+ if (err) {
+ log("Can't own %s", resource_name);
+ return -EIO;
+ }
+
+ *lno = r->start;
+ *hno = r->end;
+ return 0;
+}
+
+static void release_interrupt(struct gpmi_nfc_data *this,
+ int low_interrupt_number, int high_interrupt_number)
+{
+ int i;
+ for (i = low_interrupt_number; i <= high_interrupt_number; i++)
+ free_irq(i, this);
+}
+
+static bool gpmi_dma_filter(struct dma_chan *chan, void *param)
+{
+ struct gpmi_nfc_data *this = param;
+ struct resource *r = this->private;
+
+ if (!mxs_dma_is_apbh(chan))
+ return false;
+ /*
+ * only catch the GPMI dma channels :
+ * for mx23 : MX23_DMA_GPMI0 ~ MX23_DMA_GPMI3
+ * (These four channels share the same IRQ!)
+ *
+ * for mx28 : MX28_DMA_GPMI0 ~ MX28_DMA_GPMI7
+ * (These eight channels share the same IRQ!)
+ */
+ if (r->start <= chan->chan_id && chan->chan_id <= r->end) {
+ chan->private = &this->dma_data;
+ return true;
+ }
+ return false;
+}
+
+static void release_dma_channels(struct gpmi_nfc_data *this)
+{
+ unsigned int i;
+ for (i = 0; i <= DMA_CHANS; i++)
+ if (this->dma_chans[i]) {
+ dma_release_channel(this->dma_chans[i]);
+ this->dma_chans[i] = NULL;
+ }
+}
+
+static int acquire_dma_channels(struct gpmi_nfc_data *this,
+ const char *resource_name,
+ unsigned *low_channel, unsigned *high_channel)
+{
+ struct platform_device *pdev = this->pdev;
+ struct resource *r, *r_dma;
+ unsigned int i;
+
+ r = platform_get_resource_byname(pdev, IORESOURCE_DMA, resource_name);
+ r_dma = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+ GPMI_NFC_DMA_INTERRUPT_RES_NAME);
+ if (!r || !r_dma) {
+ log("Can't get resource for DMA");
+ return -ENXIO;
+ }
+
+ /* get the DMA interrupt */
+ BUG_ON(r_dma->start != r_dma->end);
+ this->dma_data.chan_irq = r_dma->start;
+
+ /* used in gpmi_dma_filter() */
+ this->private = r;
+
+ for (i = r->start; i <= r->end; i++) {
+ dma_cap_mask_t mask;
+ struct dma_chan *dma_chan;
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ dma_chan = dma_request_channel(mask, gpmi_dma_filter, this);
+ if (!dma_chan)
+ goto acquire_err;
+ /* fill the first empty item */
+ this->dma_chans[i - r->start] = dma_chan;
+ }
+
+ *low_channel = r->start;
+ *high_channel = r->end;
+ return 0;
+
+acquire_err:
+ log("Can't acquire DMA channel %u", i);
+ release_dma_channels(this);
+ return -EINVAL;
+}
+
+
+static inline int acquire_clock(struct gpmi_nfc_data *this,
+ const char *clock_name, struct clk **clock)
+{
+ struct clk *c;
+
+ c = clk_get(this->dev, clock_name);
+ if (IS_ERR(c)) {
+ log("Can't own clock %s", clock_name);
+ return PTR_ERR(c);
+ }
+ *clock = c;
+ return 0;
+}
+
+static void release_clock(struct gpmi_nfc_data *this, struct clk *clock)
+{
+ clk_disable(clock);
+ clk_put(clock);
+}
+
+static int acquire_resources(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct resources *resources = &this->resources;
+ int error = 0;
+
+ /* Attempt to acquire the GPMI register block. */
+ error = acquire_register_block(this,
+ GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ &resources->gpmi_regs);
+ if (error)
+ goto exit_gpmi_regs;
+
+ /* Attempt to acquire the BCH register block. */
+ error = acquire_register_block(this,
+ GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ &resources->bch_regs);
+ if (error)
+ goto exit_bch_regs;
+
+ /* Attempt to acquire the BCH interrupt. */
+ error = acquire_interrupt(this,
+ GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ bch_irq,
+ &resources->bch_low_interrupt,
+ &resources->bch_high_interrupt);
+ if (error)
+ goto exit_bch_interrupt;
+
+ /* Attempt to acquire the DMA channels. */
+ error = acquire_dma_channels(this,
+ GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ &resources->dma_low_channel,
+ &resources->dma_high_channel);
+ if (error)
+ goto exit_dma_channels;
+
+ /* Attempt to acquire our clock. */
+ error = acquire_clock(this, pdata->clock_name, &resources->clock);
+ if (error)
+ goto exit_clock;
+ return 0;
+
+exit_clock:
+ release_dma_channels(this);
+exit_dma_channels:
+ release_interrupt(this, resources->bch_low_interrupt,
+ resources->bch_high_interrupt);
+exit_bch_interrupt:
+ release_register_block(this, resources->bch_regs);
+exit_bch_regs:
+ release_register_block(this, resources->gpmi_regs);
+exit_gpmi_regs:
+ return error;
+}
+
+static void release_resources(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ release_clock(this, resources->clock);
+ release_register_block(this, resources->gpmi_regs);
+ release_register_block(this, resources->bch_regs);
+ release_interrupt(this, resources->bch_low_interrupt,
+ resources->bch_low_interrupt);
+ release_dma_channels(this);
+}
+
+static void exit_nfc_hal(struct gpmi_nfc_data *this)
+{
+ if (this->nfc)
+ this->nfc->exit(this);
+}
+
+static int set_up_nfc_hal(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct nfc_hal *nfc;
+ int error = 0;
+
+ /*
+ * This structure contains the "safe" GPMI timing that should succeed
+ * with any NAND Flash device
+ * (although, with less-than-optimal performance).
+ */
+ static struct nand_timing safe_timing = {
+ .data_setup_in_ns = 80,
+ .data_hold_in_ns = 60,
+ .address_setup_in_ns = 25,
+ .gpmi_sample_delay_in_ns = 6,
+ .tREA_in_ns = -1,
+ .tRLOH_in_ns = -1,
+ .tRHOH_in_ns = -1,
+ };
+
+ switch (pdata->chip_version) {
+ case CHIP_VERSION_IMX23:
+ nfc = &gpmi_nfc_hal_imx23;
+ break;
+ case CHIP_VERSION_IMX28:
+ nfc = &gpmi_nfc_hal_imx28;
+ break;
+ default:
+ log("Unkown NFC version %u", pdata->chip_version);
+ return -ENXIO;
+ }
+
+ this->nfc = nfc;
+
+ /* Initialize the NFC HAL. */
+ error = nfc->init(this);
+ if (error)
+ return error;
+
+ /* Set up safe timing. */
+ nfc->set_timing(this, &safe_timing);
+ return 0;
+}
+
+static int set_up_boot_rom_helper(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct boot_rom_helper *rom;
+
+ switch (pdata->chip_version) {
+ case CHIP_VERSION_IMX23:
+ rom = &gpmi_nfc_boot_rom_imx23;
+ break;
+ case CHIP_VERSION_IMX28:
+ rom = &gpmi_nfc_boot_rom_imx28;
+ break;
+ default:
+ log("Unkown NFC version %u", pdata->chip_version);
+ return -ENXIO;
+ }
+
+ pr_info("Boot ROM: Version %u, %s\n", rom->version, rom->description);
+ this->rom = rom;
+ return 0;
+}
+
+/* Creates/Removes sysfs files for this device.*/
+static void manage_sysfs_files(struct gpmi_nfc_data *this, int create)
+{
+ struct device *dev = this->dev;
+ int error;
+ unsigned int i;
+ struct device_attribute **attr;
+
+ for (i = 0, attr = device_attributes;
+ i < ARRAY_SIZE(device_attributes); i++, attr++) {
+
+ if (create) {
+ error = device_create_file(dev, *attr);
+ if (error) {
+ while (--attr >= device_attributes)
+ device_remove_file(dev, *attr);
+ return;
+ }
+ } else {
+ device_remove_file(dev, *attr);
+ }
+ }
+}
+
+static int gpmi_nfc_probe(struct platform_device *pdev)
+{
+ struct gpmi_nfc_platform_data *pdata = pdev->dev.platform_data;
+ struct gpmi_nfc_data *this = 0;
+ int error = 0;
+
+ this = kzalloc(sizeof(*this), GFP_KERNEL);
+ if (!this) {
+ log("Failed to allocate per-device memory\n");
+ return -ENOMEM;
+ }
+
+ /* Set up our data structures. */
+ platform_set_drvdata(pdev, this);
+ this->pdev = pdev;
+ this->dev = &pdev->dev;
+ this->pdata = pdata;
+
+ /* Acquire the resources we need. */
+ error = acquire_resources(this);
+ if (error)
+ goto exit_acquire_resources;
+
+ /* Set up the NFC. */
+ error = set_up_nfc_hal(this);
+ if (error)
+ goto exit_nfc_init;
+
+ /* Set up the Boot ROM Helper. */
+ error = set_up_boot_rom_helper(this);
+ if (error)
+ goto exit_boot_rom_helper_init;
+
+ /* Initialize the MTD Interface Layer. */
+ error = gpmi_nfc_mil_init(this);
+ if (error)
+ goto exit_mil_init;
+
+ manage_sysfs_files(this, true);
+ return 0;
+
+exit_mil_init:
+exit_boot_rom_helper_init:
+ exit_nfc_hal(this);
+exit_nfc_init:
+ release_resources(this);
+exit_acquire_resources:
+ platform_set_drvdata(pdev, NULL);
+ kfree(this);
+ return error;
+}
+
+static int __exit gpmi_nfc_remove(struct platform_device *pdev)
+{
+ struct gpmi_nfc_data *this = platform_get_drvdata(pdev);
+
+ manage_sysfs_files(this, false);
+ gpmi_nfc_mil_exit(this);
+ exit_nfc_hal(this);
+ release_resources(this);
+ platform_set_drvdata(pdev, NULL);
+ kfree(this);
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int gpmi_nfc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ return 0;
+}
+
+static int gpmi_nfc_resume(struct platform_device *pdev)
+{
+ return 0;
+}
+#else
+#define suspend NULL
+#define resume NULL
+#endif
+
+/* This structure represents this driver to the platform management system. */
+static struct platform_driver gpmi_nfc_driver = {
+ .driver = {
+ .name = GPMI_NFC_DRIVER_NAME,
+ },
+ .probe = gpmi_nfc_probe,
+ .remove = __exit_p(gpmi_nfc_remove),
+ .suspend = gpmi_nfc_suspend,
+ .resume = gpmi_nfc_resume,
+};
+
+static int __init gpmi_nfc_init(void)
+{
+ printk(KERN_INFO "GPMI NFC driver registered. (IMX)\n");
+ if (platform_driver_register(&gpmi_nfc_driver) != 0) {
+ pr_err("i.MX GPMI NFC driver registration failed\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
+static void __exit gpmi_nfc_exit(void)
+{
+ platform_driver_unregister(&gpmi_nfc_driver);
+}
+
+module_init(gpmi_nfc_init);
+module_exit(gpmi_nfc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
new file mode 100644
index 0000000..b5a2d77
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-nfc.h
@@ -0,0 +1,520 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __DRIVERS_MTD_NAND_GPMI_NFC_H
+#define __DRIVERS_MTD_NAND_GPMI_NFC_H
+
+/* Linux header files. */
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/concat.h>
+#include <linux/dmaengine.h>
+#include <asm/sizes.h>
+
+/* Platform header files. */
+#include <mach/mxs.h>
+#include <mach/common.h>
+#include <mach/dma.h>
+#include <mach/gpmi-nfc.h>
+#include <mach/system.h>
+#include <mach/clock.h>
+
+/* Driver header files. */
+#include "nand_device_info.h"
+
+/*
+ *------------------------------------------------------------------------------
+ * Fundamental Data Structures
+ *------------------------------------------------------------------------------
+ */
+
+/**
+ * struct resources - The collection of resources the driver needs.
+ *
+ * @gpmi_regs: A pointer to the GPMI registers.
+ * @bch_regs: A pointer to the BCH registers.
+ * @bch_interrupt: The BCH interrupt number.
+ * @dma_low_channel: The low DMA channel.
+ * @dma_high_channel: The high DMA channel.
+ * @clock: A pointer to the struct clk for the NFC's clock.
+ */
+struct resources {
+ void *gpmi_regs;
+ void *bch_regs;
+ unsigned int bch_low_interrupt;
+ unsigned int bch_high_interrupt;
+ unsigned int dma_low_channel;
+ unsigned int dma_high_channel;
+ struct clk *clock;
+};
+
+/**
+ * struct mil - State for the MTD Interface Layer.
+ *
+ * @nand: The NAND Flash MTD data structure that represents
+ * the NAND Flash medium.
+ * @mtd: The MTD data structure that represents the NAND
+ * Flash medium.
+ * @oob_layout: A structure that describes how bytes are laid out
+ * in the OOB.
+ * @general_use_mtd: A pointer to an MTD we export for general use.
+ * This *may* simply be a pointer to the mtd field, if
+ * we've been instructed NOT to protect the boot
+ * areas.
+ * @partitions: A pointer to a set of partitions applied to the
+ * general use MTD.
+ * @partition_count: The number of partitions.
+ * @current_chip: The chip currently selected by the NAND Fash MTD
+ * code. A negative value indicates that no chip is
+ * selected.
+ * @command_length: The length of the command that appears in the
+ * command buffer (see cmd_virt, below).
+ * @ignore_bad_block_marks: Indicates we are ignoring bad block marks.
+ * @saved_bbt: A saved pointer to the in-memory NAND Flash MTD bad
+ * block table. See show_device_ignorebad() for more
+ * details.
+ * @marking_a_bad_block: Indicates the caller is marking a bad block. See
+ * mil_ecc_write_oob() for details.
+ * @hooked_block_markbad: A pointer to the block_markbad() function we
+ * we "hooked." See mil_ecc_write_oob() for details.
+ * @upper_buf: The buffer passed from upper layer.
+ * @upper_len: The buffer len passed from upper layer.
+ * @direct_dma_map_ok: Is the direct DMA map is good for the upper_buf?
+ * @cmd_sgl/cmd_buffer: For NAND command.
+ * @data_sgl/data_buffer_dma:For NAND DATA ops.
+ * @page_buffer_virt: A pointer to a DMA-coherent buffer we use for
+ * reading and writing pages. This buffer includes
+ * space for both the payload data and the auxiliary
+ * data (including status bytes, but not syndrome
+ * bytes).
+ * @page_buffer_phys: The physical address for the page_buffer_virt
+ * buffer.
+ * @page_buffer_size: The size of the page buffer.
+ * @payload_virt: A pointer to a location in the page buffer used
+ * for payload bytes. The size of this buffer is
+ * determined by struct nfc_geometry.
+ * @payload_phys: The physical address for payload_virt.
+ * @auxiliary_virt: A pointer to a location in the page buffer used
+ * for auxiliary bytes. The size of this buffer is
+ * determined by struct nfc_geometry.
+ * @auxiliary_phys: The physical address for auxiliary_virt.
+ */
+struct mil {
+ /* MTD Data Structures */
+ struct nand_chip nand;
+ struct mtd_info mtd;
+ struct nand_ecclayout oob_layout;
+
+ /* Partitioning and Boot Area Protection */
+ struct mtd_info *general_use_mtd;
+ struct mtd_partition *partitions;
+ unsigned int partition_count;
+
+ /* General-use Variables */
+ int current_chip;
+ unsigned int command_length;
+ int ignore_bad_block_marks;
+ void *saved_bbt;
+
+ /* MTD Function Pointer Hooks */
+ int marking_a_bad_block;
+ int (*hooked_block_markbad)(struct mtd_info *mtd,
+ loff_t ofs);
+
+ /* from upper layer */
+ uint8_t *upper_buf;
+ int upper_len;
+
+ /* DMA */
+ bool direct_dma_map_ok;
+
+ struct scatterlist cmd_sgl;
+ char *cmd_buffer;
+
+ struct scatterlist data_sgl;
+ char *data_buffer_dma;
+
+ void *page_buffer_virt;
+ dma_addr_t page_buffer_phys;
+ unsigned int page_buffer_size;
+
+ void *payload_virt;
+ dma_addr_t payload_phys;
+
+ void *auxiliary_virt;
+ dma_addr_t auxiliary_phys;
+};
+
+/**
+ * struct nfc_geometry - NFC geometry description.
+ *
+ * This structure describes the NFC's view of the medium geometry.
+ *
+ * @ecc_algorithm: The human-readable name of the ECC algorithm
+ * (e.g., "Reed-Solomon" or "BCH").
+ * @ecc_strength: A number that describes the strength of the ECC
+ * algorithm.
+ * @page_size_in_bytes: The size, in bytes, of a physical page, including
+ * both data and OOB.
+ * @metadata_size_in_bytes: The size, in bytes, of the metadata.
+ * @ecc_chunk_size_in_bytes: The size, in bytes, of a single ECC chunk. Note
+ * the first chunk in the page includes both data and
+ * metadata, so it's a bit larger than this value.
+ * @ecc_chunk_count: The number of ECC chunks in the page,
+ * @payload_size_in_bytes: The size, in bytes, of the payload buffer.
+ * @auxiliary_size_in_bytes: The size, in bytes, of the auxiliary buffer.
+ * @auxiliary_status_offset: The offset into the auxiliary buffer at which
+ * the ECC status appears.
+ * @block_mark_byte_offset: The byte offset in the ECC-based page view at
+ * which the underlying physical block mark appears.
+ * @block_mark_bit_offset: The bit offset into the ECC-based page view at
+ * which the underlying physical block mark appears.
+ */
+struct nfc_geometry {
+ char *ecc_algorithm;
+ unsigned int ecc_strength;
+ unsigned int page_size_in_bytes;
+ unsigned int metadata_size_in_bytes;
+ unsigned int ecc_chunk_size_in_bytes;
+ unsigned int ecc_chunk_count;
+ unsigned int payload_size_in_bytes;
+ unsigned int auxiliary_size_in_bytes;
+ unsigned int auxiliary_status_offset;
+ unsigned int block_mark_byte_offset;
+ unsigned int block_mark_bit_offset;
+};
+
+/**
+ * struct boot_rom_geometry - Boot ROM geometry description.
+ *
+ * This structure encapsulates decisions made by the Boot ROM Helper.
+ *
+ * @boot_area_count: The number of boot areas. The first boot area
+ * appears at the beginning of chip 0, the next
+ * at the beginning of chip 1, etc.
+ * @boot_area_size_in_bytes: The size, in bytes, of each boot area.
+ * @stride_size_in_pages: The size of a boot block stride, in pages.
+ * @search_area_stride_exponent: The logarithm to base 2 of the size of a
+ * search area in boot block strides.
+ */
+struct boot_rom_geometry {
+ unsigned int boot_area_count;
+ unsigned int boot_area_size_in_bytes;
+ unsigned int stride_size_in_pages;
+ unsigned int search_area_stride_exponent;
+};
+
+/* DMA operations types */
+enum dma_ops_type {
+ DMA_FOR_COMMAND = 1,
+ DMA_FOR_READ_DATA,
+ DMA_FOR_WRITE_DATA,
+ DMA_FOR_READ_ECC_PAGE,
+ DMA_FOR_WRITE_ECC_PAGE
+};
+
+/**
+ * struct gpmi_nfc_data - i.MX NFC per-device data.
+ *
+ * Note that the "device" managed by this driver represents the NAND Flash
+ * controller *and* the NAND Flash medium behind it. Thus, the per-device data
+ * structure has information about the controller, the chips to which it is
+ * connected, and properties of the medium as a whole.
+ *
+ * @dev: A pointer to the owning struct device.
+ * @pdev: A pointer to the owning struct platform_device.
+ * @pdata: A pointer to the device's platform data.
+ * @resources: Information about system resources used by this driver.
+ * @device_info: A structure that contains detailed information about
+ * the NAND Flash device.
+ * @nfc: A pointer to a structure that represents the underlying
+ * NFC hardware.
+ * @nfc_geometry: A description of the medium geometry as viewed by the
+ * NFC.
+ * @rom: A pointer to a structure that represents the underlying
+ * Boot ROM.
+ * @rom_geometry: A description of the medium geometry as viewed by the
+ * Boot ROM.
+ * @mil: A collection of information used by the MTD Interface
+ * Layer.
+ */
+struct gpmi_nfc_data {
+ /* System Interface */
+ struct device *dev;
+ struct platform_device *pdev;
+ struct gpmi_nfc_platform_data *pdata;
+
+ /* Resources */
+ struct resources resources;
+
+ /* Flash Hardware */
+ struct nand_device_info device_info;
+
+ /* NFC HAL */
+ struct nfc_hal *nfc;
+ struct nfc_geometry nfc_geometry;
+
+ /* Boot ROM Helper */
+ struct boot_rom_helper *rom;
+ struct boot_rom_geometry rom_geometry;
+
+ /* MTD Interface Layer */
+ struct mil mil;
+
+ /* DMA channels */
+#define DMA_CHANS 8
+ struct dma_chan *dma_chans[DMA_CHANS];
+ struct mxs_dma_data dma_data;
+ enum dma_ops_type dma_type;
+
+ /* private */
+ void *private;
+};
+
+/**
+ * struct gpmi_nfc_hardware_timing - GPMI NFC hardware timing parameters.
+ *
+ * This structure contains timing information expressed in a form directly
+ * usable by the GPMI NFC hardware.
+ *
+ * @data_setup_in_cycles: The data setup time, in cycles.
+ * @data_hold_in_cycles: The data hold time, in cycles.
+ * @address_setup_in_cycles: The address setup time, in cycles.
+ * @use_half_periods: Indicates the clock is running slowly, so the
+ * NFC DLL should use half-periods.
+ * @sample_delay_factor: The sample delay factor.
+ */
+struct gpmi_nfc_hardware_timing {
+ uint8_t data_setup_in_cycles;
+ uint8_t data_hold_in_cycles;
+ uint8_t address_setup_in_cycles;
+ bool use_half_periods;
+ uint8_t sample_delay_factor;
+};
+
+/**
+ * struct nfc_hal - GPMI NFC HAL
+ *
+ * This structure embodies an abstract interface to the underlying NFC hardware.
+ *
+ * @version: The NFC hardware version.
+ * @description: A pointer to a human-readable description of
+ * the NFC hardware.
+ * @max_chip_count: The maximum number of chips the NFC can
+ * possibly support (this value is a constant for
+ * each NFC version). This may *not* be the actual
+ * number of chips connected.
+ * @max_data_setup_cycles: The maximum number of data setup cycles that
+ * can be expressed in the hardware.
+ * @internal_data_setup_in_ns: The time, in ns, that the NFC hardware requires
+ * for data read internal setup. In the Reference
+ * Manual, see the chapter "High-Speed NAND
+ * Timing" for more details.
+ * @max_sample_delay_factor: The maximum sample delay factor that can be
+ * expressed in the hardware.
+ * @max_dll_clock_period_in_ns: The maximum period of the GPMI clock that the
+ * sample delay DLL hardware can possibly work
+ * with (the DLL is unusable with longer periods).
+ * If the full-cycle period is greater than HALF
+ * this value, the DLL must be configured to use
+ * half-periods.
+ * @max_dll_delay_in_ns: The maximum amount of delay, in ns, that the
+ * DLL can implement.
+ * @dma_descriptors: A pool of DMA descriptors.
+ * @isr_dma_channel: The DMA channel with which the NFC HAL is
+ * working. We record this here so the ISR knows
+ * which DMA channel to acknowledge.
+ * @dma_done: The completion structure used for DMA
+ * interrupts.
+ * @bch_done: The completion structure used for BCH
+ * interrupts.
+ * @timing: The current timing configuration.
+ * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
+ * I/O transaction. If no I/O transaction is in
+ * progress, this is the clock frequency during
+ * the most recent I/O transaction.
+ * @hardware_timing: The hardware timing configuration in effect
+ * during the current I/O transaction. If no I/O
+ * transaction is in progress, this is the
+ * hardware timing configuration during the most
+ * recent I/O transaction.
+ * @init: Initializes the NFC hardware and data
+ * structures. This function will be called after
+ * everything has been set up for communication
+ * with the NFC itself, but before the platform
+ * has set up off-chip communication. Thus, this
+ * function must not attempt to communicate with
+ * the NAND Flash hardware.
+ * @set_geometry: Configures the NFC hardware and data structures
+ * to match the physical NAND Flash geometry.
+ * @set_geometry: Configures the NFC hardware and data structures
+ * to match the physical NAND Flash geometry.
+ * @set_timing: Configures the NFC hardware and data structures
+ * to match the given NAND Flash bus timing.
+ * @get_timing: Returns the the clock frequency, in Hz, and
+ * the hardware timing configuration during the
+ * current I/O transaction. If no I/O transaction
+ * is in progress, this is the timing state during
+ * the most recent I/O transaction.
+ * @exit: Shuts down the NFC hardware and data
+ * structures. This function will be called after
+ * the platform has shut down off-chip
+ * communication but while communication with the
+ * NFC itself still works.
+ * @clear_bch: Clears a BCH interrupt (intended to be called
+ * by a more general interrupt handler to do
+ * device-specific clearing).
+ * @is_ready: Returns true if the given chip is ready.
+ * @begin: Begins an interaction with the NFC. This
+ * function must be called before *any* of the
+ * following functions so the NFC can prepare
+ * itself.
+ * @end: Ends interaction with the NFC. This function
+ * should be called to give the NFC a chance to,
+ * among other things, enter a lower-power state.
+ * @send_command: Sends the given buffer of command bytes.
+ * @send_data: Sends the given buffer of data bytes.
+ * @read_data: Reads data bytes into the given buffer.
+ * @send_page: Sends the given given data and OOB bytes,
+ * using the ECC engine.
+ * @read_page: Reads a page through the ECC engine and
+ * delivers the data and OOB bytes to the given
+ * buffers.
+ */
+struct nfc_hal {
+ /* Hardware attributes. */
+ const unsigned int version;
+ const char *description;
+ const unsigned int max_chip_count;
+ const unsigned int max_data_setup_cycles;
+ const unsigned int internal_data_setup_in_ns;
+ const unsigned int max_sample_delay_factor;
+ const unsigned int max_dll_clock_period_in_ns;
+ const unsigned int max_dll_delay_in_ns;
+
+ int isr_dma_channel;
+ struct completion dma_done;
+ struct completion bch_done;
+ struct nand_timing timing;
+ unsigned long clock_frequency_in_hz;
+
+ /* Configuration functions. */
+ int (*init) (struct gpmi_nfc_data *);
+ int (*extra_init) (struct gpmi_nfc_data *);
+ int (*set_geometry)(struct gpmi_nfc_data *);
+ int (*set_timing) (struct gpmi_nfc_data *,
+ const struct nand_timing *);
+ void (*get_timing) (struct gpmi_nfc_data *,
+ unsigned long *clock_frequency_in_hz,
+ struct gpmi_nfc_hardware_timing *);
+ void (*exit) (struct gpmi_nfc_data *);
+
+ /* Call these functions to begin and end I/O. */
+ void (*begin) (struct gpmi_nfc_data *);
+ void (*end) (struct gpmi_nfc_data *);
+
+ /* Call these I/O functions only between begin() and end(). */
+ void (*clear_bch) (struct gpmi_nfc_data *);
+ int (*is_ready) (struct gpmi_nfc_data *, unsigned chip);
+ int (*send_command)(struct gpmi_nfc_data *);
+ int (*send_data) (struct gpmi_nfc_data *);
+ int (*read_data) (struct gpmi_nfc_data *);
+ int (*send_page) (struct gpmi_nfc_data *,
+ dma_addr_t payload, dma_addr_t auxiliary);
+ int (*read_page) (struct gpmi_nfc_data *,
+ dma_addr_t payload, dma_addr_t auxiliary);
+};
+
+/**
+ * struct boot_rom_helper - Boot ROM Helper
+ *
+ * This structure embodies the interface to an object that assists the driver
+ * in making decisions that relate to the Boot ROM.
+ *
+ * @version: The Boot ROM version.
+ * @description: A pointer to a human-readable description of the
+ * Boot ROM.
+ * @swap_block_mark: Indicates that the Boot ROM will swap the block
+ * mark with the first byte of the OOB.
+ * @set_geometry: Configures the Boot ROM geometry.
+ * @rom_extra_init: Arch-specific init.
+ */
+struct boot_rom_helper {
+ const unsigned int version;
+ const char *description;
+ const int swap_block_mark;
+ int (*set_geometry) (struct gpmi_nfc_data *);
+ int (*rom_extra_init) (struct gpmi_nfc_data *);
+};
+
+/*
+ *------------------------------------------------------------------------------
+ * External Symbols
+ *------------------------------------------------------------------------------
+ */
+
+/* NFC HAL Common Services */
+extern irqreturn_t bch_irq(int irq, void *cookie);
+extern int common_nfc_set_geometry(struct gpmi_nfc_data *this);
+extern int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+ struct gpmi_nfc_hardware_timing *hw);
+extern struct dma_chan *get_dma_chan(struct gpmi_nfc_data *this);
+extern void prepare_data_dma(struct gpmi_nfc_data *this,
+ enum dma_data_direction dr);
+extern int start_dma_without_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc);
+extern int start_dma_with_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc);
+/* NFC HAL Structures */
+extern struct nfc_hal gpmi_nfc_hal_imx23;
+extern struct nfc_hal gpmi_nfc_hal_imx28;
+
+/* Boot ROM Helper Common Services */
+extern int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this);
+
+/* Boot ROM Helper Structures */
+extern struct boot_rom_helper gpmi_nfc_boot_rom_imx23;
+extern struct boot_rom_helper gpmi_nfc_boot_rom_imx28;
+
+/* MTD Interface Layer */
+extern int gpmi_nfc_mil_init(struct gpmi_nfc_data *this);
+extern void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this);
+
+/* for log */
+#define log(a, ...) printk(KERN_INFO "[ %s : %.3d ] "a"\n", \
+ __func__, __LINE__, ## __VA_ARGS__)
+
+/* BCH : Status Block Completion Codes */
+#define STATUS_ERASED (0xff)
+#define STATUS_UNCORRECTABLE (0xfe)
+#define STATUS_GOOD (0x00)
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/hal-common.c b/drivers/mtd/nand/gpmi-nfc/hal-common.c
new file mode 100644
index 0000000..d7e8075
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/hal-common.c
@@ -0,0 +1,816 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+irqreturn_t bch_irq(int irq, void *cookie)
+{
+ struct gpmi_nfc_data *this = cookie;
+ struct nfc_hal *nfc = this->nfc;
+
+ /* Clear the BCH interrupt */
+ nfc->clear_bch(this);
+
+ complete(&nfc->bch_done);
+ return IRQ_HANDLED;
+}
+
+/* calculate the ECC strength by hand */
+static inline int get_ecc_strength(struct gpmi_nfc_data *this)
+{
+ struct mtd_info *mtd = &this->mil.mtd;
+ int ecc_strength = 0;
+
+ switch (mtd->writesize) {
+ case 2048:
+ ecc_strength = 8;
+ break;
+ case 4096:
+ switch (mtd->oobsize) {
+ case 128:
+ ecc_strength = 8;
+ break;
+ case 218:
+ ecc_strength = 16;
+ break;
+ }
+ break;
+ case 8192:
+ ecc_strength = 24;
+ break;
+ }
+
+ return ecc_strength;
+}
+
+int common_nfc_set_geometry(struct gpmi_nfc_data *this)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ struct boot_rom_helper *rom = this->rom;
+ struct mtd_info *mtd = &this->mil.mtd;
+ unsigned int metadata_size;
+ unsigned int status_size;
+ unsigned int chunk_data_size_in_bits;
+ unsigned int chunk_ecc_size_in_bits;
+ unsigned int chunk_total_size_in_bits;
+ unsigned int block_mark_chunk_number;
+ unsigned int block_mark_chunk_bit_offset;
+ unsigned int block_mark_bit_offset;
+
+ /* We only support BCH now. */
+ geo->ecc_algorithm = "BCH";
+
+ /*
+ * We always choose a metadata size of 10. Don't try to make sense of
+ * it -- this is really only for historical compatibility.
+ */
+ geo->metadata_size_in_bytes = 10;
+
+ /* ECC chunks */
+ geo->ecc_chunk_size_in_bytes = 512;
+ if (is_ddr_nand(&this->device_info))
+ geo->ecc_chunk_size_in_bytes = 1024;
+
+ /*
+ * Compute the total number of ECC chunks in a page. This includes the
+ * slightly larger chunk at the beginning of the page, which contains
+ * both data and metadata.
+ */
+ geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size_in_bytes;
+
+ /*
+ * We use the same ECC strength for all chunks, including the first one.
+ * At this writing, we base our ECC strength choice entirely on the
+ * the physical page geo. In the future, this should be changed to
+ * pay attention to the detailed device information we gathered earlier.
+ */
+ geo->ecc_strength = get_ecc_strength(this);
+ if (!geo->ecc_strength) {
+ log("Unsupported page geometry.");
+ return !0;
+ }
+
+ /* Compute the page size, include page and oob. */
+ geo->page_size_in_bytes = mtd->writesize + mtd->oobsize;
+ /*
+ * ONFI/TOGGLE nand needs GF14, so re-culculate DMA page size.
+ * The ONFI nand must do the reculation,
+ * else it will fail in DMA in some platform(such as imx50).
+ */
+ if (is_ddr_nand(&this->device_info))
+ geo->page_size_in_bytes = mtd->writesize +
+ geo->metadata_size_in_bytes +
+ (geo->ecc_strength * 14 * 8 / geo->ecc_chunk_count);
+
+ /*
+ * The payload buffer contains the data area of a page. The ECC engine
+ * only needs what's required to hold the data.
+ */
+ geo->payload_size_in_bytes = mtd->writesize;
+
+ /*
+ * In principle, computing the auxiliary buffer geometry is NFC
+ * version-specific. However, at this writing, all versions share the
+ * same model, so this code can also be shared.
+ *
+ * The auxiliary buffer contains the metadata and the ECC status. The
+ * metadata is padded to the nearest 32-bit boundary. The ECC status
+ * contains one byte for every ECC chunk, and is also padded to the
+ * nearest 32-bit boundary.
+ */
+ metadata_size = (geo->metadata_size_in_bytes + 0x3) & ~0x3;
+ status_size = (geo->ecc_chunk_count + 0x3) & ~0x3;
+
+ geo->auxiliary_size_in_bytes = metadata_size + status_size;
+ geo->auxiliary_status_offset = metadata_size;
+
+ /* Check if we're going to do block mark swapping. */
+ if (!rom->swap_block_mark)
+ return 0;
+
+ /*
+ * If control arrives here, we're doing block mark swapping, so we need
+ * to compute the byte and bit offsets of the physical block mark within
+ * the ECC-based view of the page data. In principle, this isn't a
+ * difficult computation -- but it's very important and it's easy to get
+ * it wrong, so we do it carefully.
+ *
+ * Note that this calculation is simpler because we use the same ECC
+ * strength for all chunks, including the zero'th one, which contains
+ * the metadata. The calculation would be slightly more complicated
+ * otherwise.
+ *
+ * We start by computing the physical bit offset of the block mark. We
+ * then subtract the number of metadata and ECC bits appearing before
+ * the mark to arrive at its bit offset within the data alone.
+ */
+
+ /* Compute some important facts about chunk geometry. */
+ chunk_data_size_in_bits = geo->ecc_chunk_size_in_bytes * 8;
+
+ /* ONFI/TOGGLE nand needs GF14 */
+ if (is_ddr_nand(&this->device_info))
+ chunk_ecc_size_in_bits = geo->ecc_strength * 14;
+ else
+ chunk_ecc_size_in_bits = geo->ecc_strength * 13;
+
+ chunk_total_size_in_bits =
+ chunk_data_size_in_bits + chunk_ecc_size_in_bits;
+
+ /* Compute the bit offset of the block mark within the physical page. */
+ block_mark_bit_offset = mtd->writesize * 8;
+
+ /* Subtract the metadata bits. */
+ block_mark_bit_offset -= geo->metadata_size_in_bytes * 8;
+
+ /*
+ * Compute the chunk number (starting at zero) in which the block mark
+ * appears.
+ */
+ block_mark_chunk_number =
+ block_mark_bit_offset / chunk_total_size_in_bits;
+
+ /*
+ * Compute the bit offset of the block mark within its chunk, and
+ * validate it.
+ */
+ block_mark_chunk_bit_offset =
+ block_mark_bit_offset -
+ (block_mark_chunk_number * chunk_total_size_in_bits);
+
+ if (block_mark_chunk_bit_offset > chunk_data_size_in_bits) {
+ /*
+ * If control arrives here, the block mark actually appears in
+ * the ECC bits of this chunk. This wont' work.
+ */
+ log("Unsupported page geometry (block mark in ECC): %u:%u",
+ mtd->writesize, mtd->oobsize);
+ return !0;
+ }
+
+ /*
+ * Now that we know the chunk number in which the block mark appears,
+ * we can subtract all the ECC bits that appear before it.
+ */
+ block_mark_bit_offset -=
+ block_mark_chunk_number * chunk_ecc_size_in_bits;
+
+ /*
+ * We now know the absolute bit offset of the block mark within the
+ * ECC-based data. We can now compute the byte offset and the bit
+ * offset within the byte.
+ */
+ geo->block_mark_byte_offset = block_mark_bit_offset / 8;
+ geo->block_mark_bit_offset = block_mark_bit_offset % 8;
+
+ return 0;
+}
+
+struct dma_chan *get_dma_chan(struct gpmi_nfc_data *this)
+{
+ int chip = this->mil.current_chip;
+
+ BUG_ON(chip < 0);
+ return this->dma_chans[chip];
+}
+
+/* Can we use the upper's buffer directly for DMA? */
+void prepare_data_dma(struct gpmi_nfc_data *this, enum dma_data_direction dr)
+{
+ struct mil *mil = &this->mil;
+ struct scatterlist *sgl = &mil->data_sgl;
+ int ret = 0;
+
+ mil->direct_dma_map_ok = true;
+
+ /* first try to map the upper buffer directly */
+ sg_init_one(sgl, mil->upper_buf, mil->upper_len);
+ ret = dma_map_sg(this->dev, sgl, 1, dr);
+ if (ret == 0) {
+ /* We have to use our own DMA buffer. */
+ sg_init_one(sgl, mil->data_buffer_dma, PAGE_SIZE);
+ ret = dma_map_sg(this->dev, sgl, 1, dr);
+ BUG_ON(ret == 0);
+
+ if (dr == DMA_TO_DEVICE)
+ memcpy(mil->data_buffer_dma, mil->upper_buf,
+ mil->upper_len);
+ mil->direct_dma_map_ok = false;
+ }
+ sgl->length = mil->upper_len;
+}
+
+/* This will be called after the DMA operation is finished. */
+static void dma_irq_callback(void *param)
+{
+ struct gpmi_nfc_data *this = param;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ complete(&nfc->dma_done);
+
+ switch (this->dma_type) {
+ case DMA_FOR_COMMAND:
+ dma_unmap_sg(this->dev, &mil->cmd_sgl, 1, DMA_TO_DEVICE);
+ break;
+
+ case DMA_FOR_READ_DATA:
+ if (mil->direct_dma_map_ok == false)
+ memcpy(mil->upper_buf, (char *)mil->data_buffer_dma,
+ mil->upper_len);
+ dma_unmap_sg(this->dev, &mil->data_sgl, 1, DMA_FROM_DEVICE);
+ break;
+
+ case DMA_FOR_WRITE_DATA:
+ dma_unmap_sg(this->dev, &mil->data_sgl, 1, DMA_TO_DEVICE);
+ break;
+
+ case DMA_FOR_READ_ECC_PAGE:
+ case DMA_FOR_WRITE_ECC_PAGE:
+ break;
+
+ default:
+ BUG();
+ }
+}
+
+int start_dma_without_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc)
+{
+ struct nfc_hal *nfc = this->nfc;
+ int err;
+
+ init_completion(&nfc->dma_done);
+
+ desc->callback = dma_irq_callback;
+ desc->callback_param = this;
+ dmaengine_submit(desc);
+
+ /* Wait for the interrupt from the DMA block. */
+ err = wait_for_completion_timeout(&nfc->dma_done,
+ msecs_to_jiffies(1000));
+ err = (!err) ? -ETIMEDOUT : 0;
+ if (err)
+ log("DMA timeout!!!");
+ return err;
+}
+
+/*
+ * This function is used in BCH reading or BCH writing pages.
+ * It will wait for the BCH interrupt as long as ONE second.
+ * Actually, we must wait for two interrupts :
+ * [1] firstly the DMA interrupt and
+ * [2] the BCH interrupt.
+ *
+ * @this: Per-device data structure.
+ * @desc: DMA channel
+ */
+int start_dma_with_bch_irq(struct gpmi_nfc_data *this,
+ struct dma_async_tx_descriptor *desc)
+{
+ struct nfc_hal *nfc = this->nfc;
+ int err = 0;
+
+ /* Prepare to receive an interrupt from the BCH block. */
+ init_completion(&nfc->bch_done);
+
+ /* start the DMA */
+ start_dma_without_bch_irq(this, desc);
+
+ /* Wait for the interrupt from the BCH block. */
+ err = wait_for_completion_timeout(&nfc->bch_done,
+ msecs_to_jiffies(1000));
+ err = (!err) ? -ETIMEDOUT : 0;
+ if (err)
+ log("bch timeout!!!");
+ return err;
+}
+
+/**
+ * ns_to_cycles - Converts time in nanoseconds to cycles.
+ *
+ * @ntime: The time, in nanoseconds.
+ * @period: The cycle period, in nanoseconds.
+ * @min: The minimum allowable number of cycles.
+ */
+static unsigned int ns_to_cycles(unsigned int time,
+ unsigned int period, unsigned int min)
+{
+ unsigned int k;
+
+ /*
+ * Compute the minimum number of cycles that entirely contain the
+ * given time.
+ */
+ k = (time + period - 1) / period;
+ return max(k, min);
+}
+
+/**
+ * gpmi_compute_hardware_timing - Apply timing to current hardware conditions.
+ *
+ * @this: Per-device data.
+ * @hardware_timing: A pointer to a hardware timing structure that will receive
+ * the results of our calculations.
+ */
+int gpmi_nfc_compute_hardware_timing(struct gpmi_nfc_data *this,
+ struct gpmi_nfc_hardware_timing *hw)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct nfc_hal *nfc = this->nfc;
+ struct nand_chip *nand = &this->mil.nand;
+ struct nand_timing target = nfc->timing;
+ bool improved_timing_is_available;
+ unsigned long clock_frequency_in_hz;
+ unsigned int clock_period_in_ns;
+ bool dll_use_half_periods;
+ unsigned int dll_delay_shift;
+ unsigned int max_sample_delay_in_ns;
+ unsigned int address_setup_in_cycles;
+ unsigned int data_setup_in_ns;
+ unsigned int data_setup_in_cycles;
+ unsigned int data_hold_in_cycles;
+ int ideal_sample_delay_in_ns;
+ unsigned int sample_delay_factor;
+ int tEYE;
+ unsigned int min_prop_delay_in_ns = pdata->min_prop_delay_in_ns;
+ unsigned int max_prop_delay_in_ns = pdata->max_prop_delay_in_ns;
+
+ /*
+ * If there are multiple chips, we need to relax the timings to allow
+ * for signal distortion due to higher capacitance.
+ */
+ if (nand->numchips > 2) {
+ target.data_setup_in_ns += 10;
+ target.data_hold_in_ns += 10;
+ target.address_setup_in_ns += 10;
+ } else if (nand->numchips > 1) {
+ target.data_setup_in_ns += 5;
+ target.data_hold_in_ns += 5;
+ target.address_setup_in_ns += 5;
+ }
+
+ /* Check if improved timing information is available. */
+ improved_timing_is_available =
+ (target.tREA_in_ns >= 0) &&
+ (target.tRLOH_in_ns >= 0) &&
+ (target.tRHOH_in_ns >= 0) ;
+
+ /* Inspect the clock. */
+ clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+ clock_period_in_ns = 1000000000 / clock_frequency_in_hz;
+
+ /*
+ * The NFC quantizes setup and hold parameters in terms of clock cycles.
+ * Here, we quantize the setup and hold timing parameters to the
+ * next-highest clock period to make sure we apply at least the
+ * specified times.
+ *
+ * For data setup and data hold, the hardware interprets a value of zero
+ * as the largest possible delay. This is not what's intended by a zero
+ * in the input parameter, so we impose a minimum of one cycle.
+ */
+ data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns,
+ clock_period_in_ns, 1);
+ data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns,
+ clock_period_in_ns, 1);
+ address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
+ clock_period_in_ns, 0);
+
+ /*
+ * The clock's period affects the sample delay in a number of ways:
+ *
+ * (1) The NFC HAL tells us the maximum clock period the sample delay
+ * DLL can tolerate. If the clock period is greater than half that
+ * maximum, we must configure the DLL to be driven by half periods.
+ *
+ * (2) We need to convert from an ideal sample delay, in ns, to a
+ * "sample delay factor," which the NFC uses. This factor depends on
+ * whether we're driving the DLL with full or half periods.
+ * Paraphrasing the reference manual:
+ *
+ * AD = SDF x 0.125 x RP
+ *
+ * where:
+ *
+ * AD is the applied delay, in ns.
+ * SDF is the sample delay factor, which is dimensionless.
+ * RP is the reference period, in ns, which is a full clock period
+ * if the DLL is being driven by full periods, or half that if
+ * the DLL is being driven by half periods.
+ *
+ * Let's re-arrange this in a way that's more useful to us:
+ *
+ * 8
+ * SDF = AD x ----
+ * RP
+ *
+ * The reference period is either the clock period or half that, so this
+ * is:
+ *
+ * 8 AD x DDF
+ * SDF = AD x ----- = --------
+ * f x P P
+ *
+ * where:
+ *
+ * f is 1 or 1/2, depending on how we're driving the DLL.
+ * P is the clock period.
+ * DDF is the DLL Delay Factor, a dimensionless value that
+ * incorporates all the constants in the conversion.
+ *
+ * DDF will be either 8 or 16, both of which are powers of two. We can
+ * reduce the cost of this conversion by using bit shifts instead of
+ * multiplication or division. Thus:
+ *
+ * AD << DDS
+ * SDF = ---------
+ * P
+ *
+ * or
+ *
+ * AD = (SDF >> DDS) x P
+ *
+ * where:
+ *
+ * DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF.
+ */
+ if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
+ dll_use_half_periods = true;
+ dll_delay_shift = 3 + 1;
+ } else {
+ dll_use_half_periods = false;
+ dll_delay_shift = 3;
+ }
+
+ /*
+ * Compute the maximum sample delay the NFC allows, under current
+ * conditions. If the clock is running too slowly, no sample delay is
+ * possible.
+ */
+ if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
+ max_sample_delay_in_ns = 0;
+ else {
+ /*
+ * Compute the delay implied by the largest sample delay factor
+ * the NFC allows.
+ */
+ max_sample_delay_in_ns =
+ (nfc->max_sample_delay_factor * clock_period_in_ns) >>
+ dll_delay_shift;
+
+ /*
+ * Check if the implied sample delay larger than the NFC
+ * actually allows.
+ */
+ if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
+ max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
+ }
+
+ /*
+ * Check if improved timing information is available. If not, we have to
+ * use a less-sophisticated algorithm.
+ */
+ if (!improved_timing_is_available) {
+ /*
+ * Fold the read setup time required by the NFC into the ideal
+ * sample delay.
+ */
+ ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
+ nfc->internal_data_setup_in_ns;
+
+ /*
+ * The ideal sample delay may be greater than the maximum
+ * allowed by the NFC. If so, we can trade off sample delay time
+ * for more data setup time.
+ *
+ * In each iteration of the following loop, we add a cycle to
+ * the data setup time and subtract a corresponding amount from
+ * the sample delay until we've satisified the constraints or
+ * can't do any better.
+ */
+ while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+ data_setup_in_cycles++;
+ ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+
+ }
+
+ /*
+ * Compute the sample delay factor that corresponds most closely
+ * to the ideal sample delay. If the result is too large for the
+ * NFC, use the maximum value.
+ *
+ * Notice that we use the ns_to_cycles function to compute the
+ * sample delay factor. We do this because the form of the
+ * computation is the same as that for calculating cycles.
+ */
+ sample_delay_factor =
+ ns_to_cycles(
+ ideal_sample_delay_in_ns << dll_delay_shift,
+ clock_period_in_ns, 0);
+
+ if (sample_delay_factor > nfc->max_sample_delay_factor)
+ sample_delay_factor = nfc->max_sample_delay_factor;
+
+ /* Skip to the part where we return our results. */
+ goto return_results;
+ }
+
+ /*
+ * If control arrives here, we have more detailed timing information,
+ * so we can use a better algorithm.
+ */
+
+ /*
+ * Fold the read setup time required by the NFC into the maximum
+ * propagation delay.
+ */
+ max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
+
+ /*
+ * Earlier, we computed the number of clock cycles required to satisfy
+ * the data setup time. Now, we need to know the actual nanoseconds.
+ */
+ data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
+
+ /*
+ * Compute tEYE, the width of the data eye when reading from the NAND
+ * Flash. The eye width is fundamentally determined by the data setup
+ * time, perturbed by propagation delays and some characteristics of the
+ * NAND Flash device.
+ *
+ * start of the eye = max_prop_delay + tREA
+ * end of the eye = min_prop_delay + tRHOH + data_setup
+ */
+ tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
+ (int)data_setup_in_ns;
+
+ tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
+
+ /*
+ * The eye must be open. If it's not, we can try to open it by
+ * increasing its main forcer, the data setup time.
+ *
+ * In each iteration of the following loop, we increase the data setup
+ * time by a single clock cycle. We do this until either the eye is
+ * open or we run into NFC limits.
+ */
+ while ((tEYE <= 0) &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+ /* Give a cycle to data setup. */
+ data_setup_in_cycles++;
+ /* Synchronize the data setup time with the cycles. */
+ data_setup_in_ns += clock_period_in_ns;
+ /* Adjust tEYE accordingly. */
+ tEYE += clock_period_in_ns;
+ }
+
+ /*
+ * When control arrives here, the eye is open. The ideal time to sample
+ * the data is in the center of the eye:
+ *
+ * end of the eye + start of the eye
+ * --------------------------------- - data_setup
+ * 2
+ *
+ * After some algebra, this simplifies to the code immediately below.
+ */
+ ideal_sample_delay_in_ns =
+ ((int)max_prop_delay_in_ns +
+ (int)target.tREA_in_ns +
+ (int)min_prop_delay_in_ns +
+ (int)target.tRHOH_in_ns -
+ (int)data_setup_in_ns) >> 1;
+
+ /*
+ * The following figure illustrates some aspects of a NAND Flash read:
+ *
+ *
+ * __ _____________________________________
+ * RDN \_________________/
+ *
+ * <---- tEYE ----->
+ * /-----------------\
+ * Read Data ----------------------------< >---------
+ * \-----------------/
+ * ^ ^ ^ ^
+ * | | | |
+ * |<--Data Setup -->|<--Delay Time -->| |
+ * | | | |
+ * | | |
+ * | |<-- Quantized Delay Time -->|
+ * | | |
+ *
+ *
+ * We have some issues we must now address:
+ *
+ * (1) The *ideal* sample delay time must not be negative. If it is, we
+ * jam it to zero.
+ *
+ * (2) The *ideal* sample delay time must not be greater than that
+ * allowed by the NFC. If it is, we can increase the data setup
+ * time, which will reduce the delay between the end of the data
+ * setup and the center of the eye. It will also make the eye
+ * larger, which might help with the next issue...
+ *
+ * (3) The *quantized* sample delay time must not fall either before the
+ * eye opens or after it closes (the latter is the problem
+ * illustrated in the above figure).
+ */
+
+ /* Jam a negative ideal sample delay to zero. */
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+
+ /*
+ * Extend the data setup as needed to reduce the ideal sample delay
+ * below the maximum permitted by the NFC.
+ */
+ while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+
+ /* Give a cycle to data setup. */
+ data_setup_in_cycles++;
+ /* Synchronize the data setup time with the cycles. */
+ data_setup_in_ns += clock_period_in_ns;
+ /* Adjust tEYE accordingly. */
+ tEYE += clock_period_in_ns;
+
+ /*
+ * Decrease the ideal sample delay by one half cycle, to keep it
+ * in the middle of the eye.
+ */
+ ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+ /* Jam a negative ideal sample delay to zero. */
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+ }
+
+ /*
+ * Compute the sample delay factor that corresponds to the ideal sample
+ * delay. If the result is too large, then use the maximum allowed
+ * value.
+ *
+ * Notice that we use the ns_to_cycles function to compute the sample
+ * delay factor. We do this because the form of the computation is the
+ * same as that for calculating cycles.
+ */
+ sample_delay_factor =
+ ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
+ clock_period_in_ns, 0);
+
+ if (sample_delay_factor > nfc->max_sample_delay_factor)
+ sample_delay_factor = nfc->max_sample_delay_factor;
+
+ /*
+ * These macros conveniently encapsulate a computation we'll use to
+ * continuously evaluate whether or not the data sample delay is inside
+ * the eye.
+ */
+ #define IDEAL_DELAY ((int) ideal_sample_delay_in_ns)
+
+ #define QUANTIZED_DELAY \
+ ((int) ((sample_delay_factor * clock_period_in_ns) >> \
+ dll_delay_shift))
+
+ #define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY))
+
+ #define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1))
+
+ /*
+ * While the quantized sample time falls outside the eye, reduce the
+ * sample delay or extend the data setup to move the sampling point back
+ * toward the eye. Do not allow the number of data setup cycles to
+ * exceed the maximum allowed by the NFC.
+ */
+ while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
+ (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
+ /*
+ * If control arrives here, the quantized sample delay falls
+ * outside the eye. Check if it's before the eye opens, or after
+ * the eye closes.
+ */
+ if (QUANTIZED_DELAY > IDEAL_DELAY) {
+ /*
+ * If control arrives here, the quantized sample delay
+ * falls after the eye closes. Decrease the quantized
+ * delay time and then go back to re-evaluate.
+ */
+ if (sample_delay_factor != 0)
+ sample_delay_factor--;
+ continue;
+ }
+
+ /*
+ * If control arrives here, the quantized sample delay falls
+ * before the eye opens. Shift the sample point by increasing
+ * data setup time. This will also make the eye larger.
+ */
+
+ /* Give a cycle to data setup. */
+ data_setup_in_cycles++;
+ /* Synchronize the data setup time with the cycles. */
+ data_setup_in_ns += clock_period_in_ns;
+ /* Adjust tEYE accordingly. */
+ tEYE += clock_period_in_ns;
+
+ /*
+ * Decrease the ideal sample delay by one half cycle, to keep it
+ * in the middle of the eye.
+ */
+ ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
+
+ /* ...and one less period for the delay time. */
+ ideal_sample_delay_in_ns -= clock_period_in_ns;
+
+ /* Jam a negative ideal sample delay to zero. */
+ if (ideal_sample_delay_in_ns < 0)
+ ideal_sample_delay_in_ns = 0;
+
+ /*
+ * We have a new ideal sample delay, so re-compute the quantized
+ * delay.
+ */
+ sample_delay_factor =
+ ns_to_cycles(
+ ideal_sample_delay_in_ns << dll_delay_shift,
+ clock_period_in_ns, 0);
+
+ if (sample_delay_factor > nfc->max_sample_delay_factor)
+ sample_delay_factor = nfc->max_sample_delay_factor;
+ }
+
+ /* Control arrives here when we're ready to return our results. */
+return_results:
+ hw->data_setup_in_cycles = data_setup_in_cycles;
+ hw->data_hold_in_cycles = data_hold_in_cycles;
+ hw->address_setup_in_cycles = address_setup_in_cycles;
+ hw->use_half_periods = dll_use_half_periods;
+ hw->sample_delay_factor = sample_delay_factor;
+
+ /* Return success. */
+ return 0;
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/mil.c b/drivers/mtd/nand/gpmi-nfc/mil.c
new file mode 100644
index 0000000..defd19e
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/mil.c
@@ -0,0 +1,1104 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/slab.h>
+#include "gpmi-nfc.h"
+#include "linux/slab.h"
+
+/* add our owner bbt descriptor */
+static uint8_t scan_ff_pattern[] = { 0xff };
+static struct nand_bbt_descr gpmi_bbt_descr = {
+ .options = 0,
+ .offs = 0,
+ .len = 1,
+ .pattern = scan_ff_pattern
+};
+
+static int read_page_prepare(struct gpmi_nfc_data *this,
+ void *destination, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ void **use_virt, dma_addr_t *use_phys)
+{
+ struct device *dev = this->dev;
+ dma_addr_t destination_phys = ~0;
+
+ if (virt_addr_valid(destination))
+ destination_phys = dma_map_single(dev, (void *)destination,
+ length, DMA_FROM_DEVICE);
+
+ if (dma_mapping_error(dev, destination_phys)) {
+ if (alt_size < length) {
+ log("Alternate buffer is too small for incoming I/O.");
+ return -ENOMEM;
+ }
+
+ *use_virt = alt_virt;
+ *use_phys = alt_phys;
+ } else {
+ *use_virt = destination;
+ *use_phys = destination_phys;
+ }
+ return 0;
+}
+
+static void read_page_end(struct gpmi_nfc_data *this,
+ void *destination, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ void *used_virt, dma_addr_t used_phys)
+{
+ struct device *dev = this->dev;
+
+ if (used_virt == destination)
+ dma_unmap_single(dev, used_phys, length, DMA_FROM_DEVICE);
+ else
+ memcpy(destination, alt_virt, length);
+}
+
+static int send_page_prepare(struct gpmi_nfc_data *this,
+ const void *source, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ const void **use_virt, dma_addr_t *use_phys)
+{
+ dma_addr_t source_phys = ~0;
+ struct device *dev = this->dev;
+
+ if (virt_addr_valid(source))
+ source_phys = dma_map_single(dev,
+ (void *)source, length, DMA_TO_DEVICE);
+
+ if (dma_mapping_error(dev, source_phys)) {
+ if (alt_size < length) {
+ log("Alternate buffer is too small for outgoing I/O");
+ return -ENOMEM;
+ }
+
+ /*
+ * Copy the contents of the source buffer into the alternate
+ * buffer and set up the return values accordingly.
+ */
+ memcpy(alt_virt, source, length);
+
+ *use_virt = alt_virt;
+ *use_phys = alt_phys;
+ } else {
+ *use_virt = source;
+ *use_phys = source_phys;
+ }
+ return 0;
+}
+
+static void send_page_end(struct gpmi_nfc_data *this,
+ const void *source, unsigned length,
+ void *alt_virt, dma_addr_t alt_phys, unsigned alt_size,
+ const void *used_virt, dma_addr_t used_phys)
+{
+ struct device *dev = this->dev;
+ if (used_virt == source)
+ dma_unmap_single(dev, used_phys, length, DMA_TO_DEVICE);
+}
+
+static void mil_free_dma_buffer(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+
+ if (mil->page_buffer_virt && virt_addr_valid(mil->page_buffer_virt))
+ dma_free_coherent(dev, mil->page_buffer_size,
+ mil->page_buffer_virt,
+ mil->page_buffer_phys);
+ kfree(mil->cmd_buffer);
+ kfree(mil->data_buffer_dma);
+
+ mil->cmd_buffer = NULL;
+ mil->data_buffer_dma = NULL;
+ mil->page_buffer_virt = NULL;
+ mil->page_buffer_size = 0;
+ mil->page_buffer_phys = ~0;
+}
+
+/* Allocate the DMA buffers */
+static int mil_alloc_dma_buffer(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ struct mil *mil = &this->mil;
+
+ /* [1] Allocate a command buffer. PAGE_SIZE is enough. */
+ mil->cmd_buffer = kzalloc(PAGE_SIZE, GFP_DMA);
+ if (mil->cmd_buffer == NULL)
+ goto error_alloc;
+ sg_init_one(&mil->cmd_sgl, mil->cmd_buffer, PAGE_SIZE);
+
+ /* [2] Allocate a read/write data buffer. PAGE_SIZE is enough. */
+ mil->data_buffer_dma = kzalloc(PAGE_SIZE, GFP_DMA);
+ if (mil->data_buffer_dma == NULL)
+ goto error_alloc;
+
+ /*
+ * [3] Allocate the page buffer.
+ *
+ * Both the payload buffer and the auxiliary buffer must appear on
+ * 32-bit boundaries. We presume the size of the payload buffer is a
+ * power of two and is much larger than four, which guarantees the
+ * auxiliary buffer will appear on a 32-bit boundary.
+ */
+ mil->page_buffer_size = geo->payload_size_in_bytes +
+ geo->auxiliary_size_in_bytes;
+
+ mil->page_buffer_virt = dma_alloc_coherent(dev, mil->page_buffer_size,
+ &mil->page_buffer_phys, GFP_DMA);
+ if (!mil->page_buffer_virt)
+ goto error_alloc;
+
+
+ /* Slice up the page buffer. */
+ mil->payload_virt = mil->page_buffer_virt;
+ mil->payload_phys = mil->page_buffer_phys;
+ mil->auxiliary_virt = ((char *) mil->payload_virt) +
+ geo->payload_size_in_bytes;
+ mil->auxiliary_phys = mil->payload_phys +
+ geo->payload_size_in_bytes;
+ return 0;
+
+error_alloc:
+ mil_free_dma_buffer(this);
+ log("allocate DMA buffer error!!");
+ return -ENOMEM;
+}
+
+static void mil_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct mil *mil = &this->mil;
+ struct nfc_hal *nfc = this->nfc;
+ int error;
+
+ /*
+ * Every operation begins with a command byte and a series of zero or
+ * more address bytes. These are distinguished by either the Address
+ * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
+ * asserted. When MTD is ready to execute the command, it will deassert
+ * both latch enables.
+ *
+ * Rather than run a separate DMA operation for every single byte, we
+ * queue them up and run a single DMA operation for the entire series
+ * of command and data bytes. NAND_CMD_NONE means the END of the queue.
+ */
+ if ((ctrl & (NAND_ALE | NAND_CLE))) {
+ if (data != NAND_CMD_NONE)
+ mil->cmd_buffer[mil->command_length++] = data;
+ return;
+ }
+
+ if (!mil->command_length)
+ return;
+
+ error = nfc->send_command(this);
+ if (error)
+ log("Chip: %u, Error %d", mil->current_chip, error);
+
+ mil->command_length = 0;
+}
+
+static int mil_dev_ready(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ return nfc->is_ready(this, mil->current_chip);
+}
+
+static void mil_select_chip(struct mtd_info *mtd, int chip)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct mil *mil = &this->mil;
+ struct nfc_hal *nfc = this->nfc;
+
+ if ((mil->current_chip < 0) && (chip >= 0))
+ nfc->begin(this);
+ else if ((mil->current_chip >= 0) && (chip < 0))
+ nfc->end(this);
+ else
+ ;
+
+ mil->current_chip = chip;
+}
+
+static void mil_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ /* save the info in mil{} for future */
+ mil->upper_buf = buf;
+ mil->upper_len = len;
+
+ nfc->read_data(this);
+}
+
+static void mil_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+
+ /* save the info in mil{} for future */
+ mil->upper_buf = (uint8_t *)buf;
+ mil->upper_len = len;
+
+ nfc->send_data(this);
+}
+
+static uint8_t mil_read_byte(struct mtd_info *mtd)
+{
+ uint8_t byte = 0;
+ mil_read_buf(mtd, (uint8_t *)&byte, 1);
+ return byte;
+}
+
+/**
+ * mil_handle_block_mark_swapping() - Handles block mark swapping.
+ *
+ * Note that, when this function is called, it doesn't know whether it's
+ * swapping the block mark, or swapping it *back* -- but it doesn't matter
+ * because the the operation is the same.
+ *
+ * @this: Per-device data.
+ * @payload: A pointer to the payload buffer.
+ * @auxiliary: A pointer to the auxiliary buffer.
+ */
+static void mil_handle_block_mark_swapping(struct gpmi_nfc_data *this,
+ void *payload, void *auxiliary)
+{
+ struct nfc_geometry *nfc_geo = &this->nfc_geometry;
+ struct boot_rom_helper *rom = this->rom;
+ unsigned char *p;
+ unsigned char *a;
+ unsigned int bit;
+ unsigned char mask;
+ unsigned char from_data;
+ unsigned char from_oob;
+
+ /* Check if we're doing block mark swapping. */
+ if (!rom->swap_block_mark)
+ return;
+
+ /*
+ * If control arrives here, we're swapping. Make some convenience
+ * variables.
+ */
+ bit = nfc_geo->block_mark_bit_offset;
+ p = ((unsigned char *) payload) + nfc_geo->block_mark_byte_offset;
+ a = auxiliary;
+
+ /*
+ * Get the byte from the data area that overlays the block mark. Since
+ * the ECC engine applies its own view to the bits in the page, the
+ * physical block mark won't (in general) appear on a byte boundary in
+ * the data.
+ */
+ from_data = (p[0] >> bit) | (p[1] << (8 - bit));
+
+ /* Get the byte from the OOB. */
+ from_oob = a[0];
+
+ /* Swap them. */
+ a[0] = from_data;
+
+ mask = (0x1 << bit) - 1;
+ p[0] = (p[0] & mask) | (from_oob << bit);
+
+ mask = ~0 << bit;
+ p[1] = (p[1] & mask) | (from_oob >> (8 - bit));
+}
+
+static int mil_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
+ uint8_t *buf, int page)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct nfc_geometry *nfc_geo = &this->nfc_geometry;
+ struct mil *mil = &this->mil;
+ void *payload_virt = 0;
+ dma_addr_t payload_phys = ~0;
+ void *auxiliary_virt = 0;
+ dma_addr_t auxiliary_phys = ~0;
+ unsigned int i;
+ unsigned char *status;
+ unsigned int failed;
+ unsigned int corrected;
+ int error = 0;
+
+ error = read_page_prepare(this, buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ &payload_virt, &payload_phys);
+ if (error) {
+ log("Inadequate DMA buffer");
+ error = -ENOMEM;
+ return error;
+ }
+ auxiliary_virt = mil->auxiliary_virt;
+ auxiliary_phys = mil->auxiliary_phys;
+
+ /* ask the NFC */
+ error = nfc->read_page(this, payload_phys, auxiliary_phys);
+ if (error) {
+ log("Error in ECC-based read: %d", error);
+ goto exit_nfc;
+ }
+
+ /* handle the block mark swapping */
+ mil_handle_block_mark_swapping(this, payload_virt, auxiliary_virt);
+
+ /* Loop over status bytes, accumulating ECC status. */
+ failed = 0;
+ corrected = 0;
+ status = ((unsigned char *) auxiliary_virt) +
+ nfc_geo->auxiliary_status_offset;
+
+ for (i = 0; i < nfc_geo->ecc_chunk_count; i++, status++) {
+ if ((*status == STATUS_GOOD) || (*status == STATUS_ERASED))
+ continue;
+
+ if (*status == STATUS_UNCORRECTABLE) {
+ failed++;
+ continue;
+ }
+ corrected += *status;
+ }
+
+ /*
+ * Propagate ECC status to the owning MTD only when failed or
+ * corrected times nearly reaches our ECC correction threshold.
+ */
+ if (failed || corrected >= (nfc_geo->ecc_strength - 1)) {
+ mtd->ecc_stats.failed += failed;
+ mtd->ecc_stats.corrected += corrected;
+ }
+
+ /*
+ * It's time to deliver the OOB bytes. See mil_ecc_read_oob() for
+ * details about our policy for delivering the OOB.
+ *
+ * We fill the caller's buffer with set bits, and then copy the block
+ * mark to th caller's buffer. Note that, if block mark swapping was
+ * necessary, it has already been done, so we can rely on the first
+ * byte of the auxiliary buffer to contain the block mark.
+ */
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+ nand->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0];
+
+exit_nfc:
+ read_page_end(this, buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ payload_virt, payload_phys);
+ return error;
+}
+
+static void mil_ecc_write_page(struct mtd_info *mtd,
+ struct nand_chip *nand, const uint8_t *buf)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct nfc_geometry *nfc_geo = &this->nfc_geometry;
+ struct boot_rom_helper *rom = this->rom;
+ struct mil *mil = &this->mil;
+ const void *payload_virt = 0;
+ dma_addr_t payload_phys = ~0;
+ const void *auxiliary_virt = 0;
+ dma_addr_t auxiliary_phys = ~0;
+ int error;
+
+ if (rom->swap_block_mark) {
+ /*
+ * If control arrives here, we're doing block mark swapping.
+ * Since we can't modify the caller's buffers, we must copy them
+ * into our own.
+ */
+ memcpy(mil->payload_virt, buf, mtd->writesize);
+ payload_virt = mil->payload_virt;
+ payload_phys = mil->payload_phys;
+
+ memcpy(mil->auxiliary_virt, nand->oob_poi,
+ nfc_geo->auxiliary_size_in_bytes);
+ auxiliary_virt = mil->auxiliary_virt;
+ auxiliary_phys = mil->auxiliary_phys;
+
+ /* Handle block mark swapping. */
+ mil_handle_block_mark_swapping(this,
+ (void *) payload_virt, (void *) auxiliary_virt);
+ } else {
+ /*
+ * If control arrives here, we're not doing block mark swapping,
+ * so we can to try and use the caller's buffers.
+ */
+ error = send_page_prepare(this,
+ buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ &payload_virt, &payload_phys);
+ if (error) {
+ log("Inadequate payload DMA buffer");
+ return;
+ }
+
+ error = send_page_prepare(this,
+ nand->oob_poi, mtd->oobsize,
+ mil->auxiliary_virt, mil->auxiliary_phys,
+ nfc_geo->auxiliary_size_in_bytes,
+ &auxiliary_virt, &auxiliary_phys);
+ if (error) {
+ log("Inadequate auxiliary DMA buffer");
+ goto exit_auxiliary;
+ }
+ }
+
+ /* Ask the NFC. */
+ error = nfc->send_page(this, payload_phys, auxiliary_phys);
+ if (error)
+ log("Error in ECC-based write: %d", error);
+
+ if (!rom->swap_block_mark) {
+ send_page_end(this, nand->oob_poi, mtd->oobsize,
+ mil->auxiliary_virt, mil->auxiliary_phys,
+ nfc_geo->auxiliary_size_in_bytes,
+ auxiliary_virt, auxiliary_phys);
+exit_auxiliary:
+ send_page_end(this, buf, mtd->writesize,
+ mil->payload_virt, mil->payload_phys,
+ nfc_geo->payload_size_in_bytes,
+ payload_virt, payload_phys);
+ }
+}
+
+/**
+ * mil_hook_block_markbad() - Hooked MTD Interface block_markbad().
+ *
+ * This function is a veneer that replaces the function originally installed by
+ * the NAND Flash MTD code. See the description of the marking_a_bad_block field
+ * in struct mil for more information about this.
+ *
+ * @mtd: A pointer to the MTD.
+ * @ofs: Byte address of the block to mark.
+ */
+static int mil_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ register struct nand_chip *chip = mtd->priv;
+ struct gpmi_nfc_data *this = chip->priv;
+ struct mil *mil = &this->mil;
+ int ret;
+
+ mil->marking_a_bad_block = true;
+ ret = mil->hooked_block_markbad(mtd, ofs);
+ mil->marking_a_bad_block = false;
+ return ret;
+}
+
+/**
+ * mil_ecc_read_oob() - MTD Interface ecc.read_oob().
+ *
+ * There are several places in this driver where we have to handle the OOB and
+ * block marks. This is the function where things are the most complicated, so
+ * this is where we try to explain it all. All the other places refer back to
+ * here.
+ *
+ * These are the rules, in order of decreasing importance:
+ *
+ * 1) Nothing the caller does can be allowed to imperil the block mark, so all
+ * write operations take measures to protect it.
+ *
+ * 2) In read operations, the first byte of the OOB we return must reflect the
+ * true state of the block mark, no matter where that block mark appears in
+ * the physical page.
+ *
+ * 3) ECC-based read operations return an OOB full of set bits (since we never
+ * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
+ * return).
+ *
+ * 4) "Raw" read operations return a direct view of the physical bytes in the
+ * page, using the conventional definition of which bytes are data and which
+ * are OOB. This gives the caller a way to see the actual, physical bytes
+ * in the page, without the distortions applied by our ECC engine.
+ *
+ *
+ * What we do for this specific read operation depends on two questions:
+ *
+ * 1) Are we doing a "raw" read, or an ECC-based read?
+ *
+ * 2) Are we using block mark swapping or transcription?
+ *
+ * There are four cases, illustrated by the following Karnaugh map:
+ *
+ * | Raw | ECC-based |
+ * -------------+-------------------------+-------------------------+
+ * | Read the conventional | |
+ * | OOB at the end of the | |
+ * Swapping | page and return it. It | |
+ * | contains exactly what | |
+ * | we want. | Read the block mark and |
+ * -------------+-------------------------+ return it in a buffer |
+ * | Read the conventional | full of set bits. |
+ * | OOB at the end of the | |
+ * | page and also the block | |
+ * Transcribing | mark in the metadata. | |
+ * | Copy the block mark | |
+ * | into the first byte of | |
+ * | the OOB. | |
+ * -------------+-------------------------+-------------------------+
+ *
+ * Note that we break rule #4 in the Transcribing/Raw case because we're not
+ * giving an accurate view of the actual, physical bytes in the page (we're
+ * overwriting the block mark). That's OK because it's more important to follow
+ * rule #2.
+ *
+ * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
+ * easy. When reading a page, for example, the NAND Flash MTD code calls our
+ * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
+ * ECC-based or raw view of the page is implicit in which function it calls
+ * (there is a similar pair of ECC-based/raw functions for writing).
+ *
+ * Since MTD assumes the OOB is not covered by ECC, there is no pair of
+ * ECC-based/raw functions for reading or or writing the OOB. The fact that the
+ * caller wants an ECC-based or raw view of the page is not propagated down to
+ * this driver.
+ *
+ * @mtd: A pointer to the owning MTD.
+ * @nand: A pointer to the owning NAND Flash MTD.
+ * @page: The page number to read.
+ * @sndcmd: Indicates this function should send a command to the chip before
+ * reading the out-of-band bytes. This is only false for small page
+ * chips that support auto-increment.
+ */
+static int mil_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
+ int page, int sndcmd)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct boot_rom_helper *rom = this->rom;
+
+ /* clear the OOB buffer */
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+
+ /* Read out the conventional OOB. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+ nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
+
+ /*
+ * Now, we want to make sure the block mark is correct. In the
+ * Swapping/Raw case, we already have it. Otherwise, we need to
+ * explicitly read it.
+ */
+ if (!rom->swap_block_mark) {
+ /* Read the block mark into the first byte of the OOB buffer. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+ nand->oob_poi[0] = nand->read_byte(mtd);
+ }
+
+ /*
+ * Return true, indicating that the next call to this function must send
+ * a command.
+ */
+ return true;
+}
+
+static int mil_ecc_write_oob(struct mtd_info *mtd,
+ struct nand_chip *nand, int page)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+ struct boot_rom_helper *rom = this->rom;
+ uint8_t block_mark = 0;
+ int block_mark_column;
+ int status;
+ int error = 0;
+
+ /*
+ * There are fundamental incompatibilities between the i.MX GPMI NFC and
+ * the NAND Flash MTD model that make it essentially impossible to write
+ * the out-of-band bytes.
+ *
+ * We permit *ONE* exception. If the *intent* of writing the OOB is to
+ * mark a block bad, we can do that.
+ */
+ if (!mil->marking_a_bad_block) {
+ dev_emerg(dev, "This driver doesn't support writing the OOB\n");
+ WARN_ON(1);
+ error = -EIO;
+ goto exit;
+ }
+
+ /*
+ * If control arrives here, we're marking a block bad. First, figure out
+ * where the block mark is.
+ *
+ * If we're using swapping, the block mark is in the conventional
+ * location. Otherwise, we're using transcription, and the block mark
+ * appears in the first byte of the page.
+ */
+ if (rom->swap_block_mark)
+ block_mark_column = mtd->writesize;
+ else
+ block_mark_column = 0;
+
+ /* Write the block mark. */
+ nand->cmdfunc(mtd, NAND_CMD_SEQIN, block_mark_column, page);
+ nand->write_buf(mtd, &block_mark, 1);
+ nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = nand->waitfunc(mtd, nand);
+
+ /* Check if it worked. */
+ if (status & NAND_STATUS_FAIL)
+ error = -EIO;
+exit:
+ return error;
+}
+
+/**
+ * mil_block_bad - Claims all blocks are good.
+ *
+ * In principle, this function is *only* called when the NAND Flash MTD system
+ * isn't allowed to keep an in-memory bad block table, so it is forced to ask
+ * the driver for bad block information.
+ *
+ * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
+ * this function is *only* called when we take it away.
+ *
+ * We take away the in-memory BBT when the user sets the "ignorebad" parameter,
+ * which indicates that all blocks should be reported good.
+ *
+ * Thus, this function is only called when we want *all* blocks to look good,
+ * so it *always* return success.
+ *
+ * @mtd: Ignored.
+ * @ofs: Ignored.
+ * @getchip: Ignored.
+ */
+static int mil_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
+{
+ return 0;
+}
+
+/* Set up the Boot ROM Helper geometry. */
+static int mil_set_boot_rom_helper_geometry(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_helper *rom = this->rom;
+ struct boot_rom_geometry *geo = &this->rom_geometry;
+
+ if (rom->set_geometry(this))
+ return !0;
+
+ pr_info("--------------------------------------------\n");
+ pr_info(" Boot ROM Geometry\n");
+ pr_info("--------------------------------------------\n");
+ pr_info("Boot Area Count : %u\n", geo->boot_area_count);
+ pr_info("Boot Area Size in Bytes : %u (0x%x)\n",
+ geo->boot_area_size_in_bytes,
+ geo->boot_area_size_in_bytes);
+ pr_info("Stride Size in Pages : %u\n", geo->stride_size_in_pages);
+ pr_info("Search Area Stride Exponent: %u\n",
+ geo->search_area_stride_exponent);
+ return 0;
+}
+
+static int mil_set_geometry(struct gpmi_nfc_data *this)
+{
+ struct nfc_hal *nfc = this->nfc;
+ struct nfc_geometry *geo = &this->nfc_geometry;
+
+ /* Free the temporary DMA memory for read ID case */
+ mil_free_dma_buffer(this);
+
+ /* Set up the NFC geometry which is used by BCH. */
+ if (nfc->set_geometry(this))
+ return -ENXIO;
+ pr_info("---------------------------------------\n");
+ pr_info(" NFC Geometry (used by BCH)\n");
+ pr_info("---------------------------------------\n");
+ pr_info("ECC Algorithm : %s\n", geo->ecc_algorithm);
+ pr_info("ECC Strength : %u\n", geo->ecc_strength);
+ pr_info("Page Size in Bytes : %u\n", geo->page_size_in_bytes);
+ pr_info("Metadata Size in Bytes : %u\n", geo->metadata_size_in_bytes);
+ pr_info("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size_in_bytes);
+ pr_info("ECC Chunk Count : %u\n", geo->ecc_chunk_count);
+ pr_info("Payload Size in Bytes : %u\n", geo->payload_size_in_bytes);
+ pr_info("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size_in_bytes);
+ pr_info("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
+ pr_info("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
+ pr_info("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset);
+
+ /* Alloc the new DMA buffers according to the pagesize and oobsize */
+ return mil_alloc_dma_buffer(this);
+}
+
+static int mil_pre_bbt_scan(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_helper *rom = this->rom;
+ int error = 0;
+
+ if (mil_set_boot_rom_helper_geometry(this))
+ return -ENXIO;
+
+ /* This is ROM arch-specific initilization before the BBT scanning. */
+ if (rom->rom_extra_init)
+ error = rom->rom_extra_init(this);
+ return error;
+}
+
+static int mil_scan_bbt(struct mtd_info *mtd)
+{
+ struct nand_chip *nand = mtd->priv;
+ struct gpmi_nfc_data *this = nand->priv;
+ int error;
+
+ /* Prepare for the BBT scan. */
+ error = mil_pre_bbt_scan(this);
+ if (error)
+ return error;
+
+ /* use the default BBT implementation */
+ return nand_default_bbt(mtd);
+}
+
+static int mil_boot_areas_init(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+
+ if (rom->boot_area_count == 0) {
+ mil->general_use_mtd = &mil->mtd;
+ pr_info("There is no Boot area.\n");
+ } else if (rom->boot_area_count == 1) {
+ static char *chip_0_boot_name = "gpmi-nfc-0-boot";
+ static char *general_use_name = "gpmi-nfc-general-use";
+ struct mtd_partition partitions[2];
+
+ pr_info("Boot area protection is enabled.\n");
+ /*
+ * We partition the medium like so:
+ *
+ * +------+----------------------------------------------------+
+ * | Boot | General Use |
+ * +------+----------------------------------------------------+
+ */
+
+ /* Chip 0 Boot */
+ partitions[0].name = chip_0_boot_name;
+ partitions[0].offset = 0;
+ partitions[0].size = rom->boot_area_size_in_bytes;
+ partitions[0].mask_flags = 0;
+
+ /* General Use */
+ partitions[1].name = general_use_name;
+ partitions[1].offset = rom->boot_area_size_in_bytes;
+ partitions[1].size = MTDPART_SIZ_FULL;
+ partitions[1].mask_flags = 0;
+
+ /* Construct and register the partitions. */
+ add_mtd_partitions(mtd, partitions, 2);
+
+ /* Find the general use MTD. */
+ mil->general_use_mtd = get_mtd_device_nm(general_use_name);
+ if (IS_ERR(mil->general_use_mtd)) {
+ log("Can't find general use MTD");
+ BUG();
+ }
+ } else {
+ log("Boot area count greater than one is unimplemented.");
+ return -ENXIO;
+ }
+ return 0;
+}
+
+static void mil_boot_areas_exit(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+
+ if (!rom->boot_area_count) {
+ mil->general_use_mtd = NULL;
+ return;
+ }
+ del_mtd_partitions(mtd);
+ mil->general_use_mtd = NULL;
+}
+
+static int construct_general_use_partitions(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+ unsigned int partition_count;
+ struct mtd_partition *partitions;
+ unsigned int name_size;
+ char *names;
+ unsigned int size;
+ unsigned int i;
+ static const char *name_prefix = "gpmi-nfc-ubi-";
+
+ /* Only handle the MTD which is larger than 2GiB. */
+ if (mil->general_use_mtd->size <= SZ_2G)
+ return 0;
+
+ /* Split it by 2G for historical reason*/
+ partition_count = mil->general_use_mtd->size >> 31;
+ if (mil->general_use_mtd->size & ((1 << 30) - 1))
+ partition_count++;
+
+ /* construct the partitions */
+ name_size = strlen(name_prefix) + 4;
+ size = (sizeof(*partitions) + name_size) * partition_count;
+ partitions = kzalloc(size, GFP_KERNEL);
+ if (!partitions) {
+ log("Could not allocate memory for UBI partitions.");
+ return -ENOMEM;
+ }
+
+ names = (char *)(partitions + partition_count);
+ for (i = 0; i < partition_count; i++) {
+ partitions[i].name = names;
+ partitions[i].size = SZ_2G;
+ partitions[i].offset = MTDPART_OFS_NXTBLK;
+
+ sprintf(names, "%s%u", name_prefix, i);
+ names += name_size;
+ }
+ /* Adjust the last partition to take up the remainder. */
+ partitions[i - 1].size = MTDPART_SIZ_FULL;
+
+ mil->partitions = partitions;
+ mil->partition_count = partition_count;
+ return 0;
+}
+
+static int mil_partitions_init(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+ int error;
+
+ error = mil_boot_areas_init(this);
+ if (error)
+ return error;
+
+ /* Construct partitions */
+ error = construct_general_use_partitions(this);
+ if (error) {
+ log("error : %d", error);
+ return error;
+ }
+ if (mil->partition_count)
+ add_mtd_partitions(mil->general_use_mtd, mil->partitions,
+ mil->partition_count);
+ return 0;
+}
+
+static void mil_partitions_exit(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+
+ if (mil->partition_count) {
+ del_mtd_partitions(mil->general_use_mtd);
+ kfree(mil->partitions);
+ mil->partition_count = 0;
+ }
+ mil_boot_areas_exit(this);
+}
+
+/*
+ * This function is used to set the mtd->pagesize, mtd->oobsize,
+ * mtd->erasesize. Yes, we also do some initialization.
+ *
+ * Return with the bus width. 0 for 8-bit, -1 for error.
+ */
+static int gpmi_init_size(struct mtd_info *mtd, struct nand_chip *nand,
+ u8 *id_bytes)
+{
+ struct gpmi_nfc_data *this = nand->priv;
+ struct nfc_hal *nfc = this->nfc;
+ struct mil *mil = &this->mil;
+ struct nand_ecclayout *layout = &mil->oob_layout;
+ struct nand_device_info *info;
+ struct nand_attr *attr;
+ int error;
+
+ /* Look up this device in our own database. */
+ info = nand_device_get_info(id_bytes);
+ if (!info) {
+ pr_err("Unrecognized NAND Flash device.\n");
+ return -1;
+ }
+
+ attr = &info->attr;
+ /*
+ * Init the right NAND/MTD parameters which will be used
+ * in the following mil_set_geometry().
+ */
+ mtd->writesize = 1 << (fls(attr->page_total_size_in_bytes) - 1);
+ mtd->erasesize = mtd->writesize * attr->block_size_in_pages;
+ mtd->oobsize = attr->page_total_size_in_bytes - mtd->writesize;
+ nand->chipsize = attr->chip_size_in_bytes;
+
+ /* Configure the struct nand_ecclayout. */
+ layout->eccbytes = 0;
+ layout->oobavail = mtd->oobsize;
+ layout->oobfree[0].offset = 0;
+ layout->oobfree[0].length = mtd->oobsize;
+
+ nand->ecc.layout = layout;
+
+ /*
+ * Copy the device info into the per-device data. We can't just keep
+ * the pointer because that storage is reclaimed after initialization.
+ */
+ this->device_info = *info;
+ this->device_info.desc = kstrdup(info->desc, GFP_KERNEL);
+
+ /* Set up the medium geometry */
+ error = mil_set_geometry(this);
+ if (error)
+ return -1;
+
+ /* Set up timing. */
+ error = nfc->set_timing(this, &info->timing);
+ if (error)
+ return -1;
+
+ if (nfc->extra_init) {
+ error = nfc->extra_init(this);
+ if (error != 0)
+ return -1;
+ }
+
+ /* We only use 8-bit bus now, not 16-bit. */
+ return 0;
+}
+
+/* Initializes the MTD Interface Layer */
+int gpmi_nfc_mil_init(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ int error = 0;
+
+ /* Initialize MIL data */
+ mil->current_chip = -1;
+ mil->command_length = 0;
+ mil->page_buffer_virt = 0;
+ mil->page_buffer_phys = ~0;
+ mil->page_buffer_size = 0;
+
+ /* Initialize the MTD data structures */
+ mtd->priv = nand;
+ mtd->name = "gpmi-nfc-main";
+ mtd->owner = THIS_MODULE;
+ nand->priv = this;
+
+ /* Controls */
+ nand->select_chip = mil_select_chip;
+ nand->cmd_ctrl = mil_cmd_ctrl;
+ nand->dev_ready = mil_dev_ready;
+
+ /*
+ * Low-level I/O :
+ * We don't support a 16-bit NAND Flash bus,
+ * so we don't implement read_word.
+ */
+ nand->read_byte = mil_read_byte;
+ nand->read_buf = mil_read_buf;
+ nand->write_buf = mil_write_buf;
+
+ /* ECC-aware I/O */
+ nand->ecc.read_page = mil_ecc_read_page;
+ nand->ecc.write_page = mil_ecc_write_page;
+
+ /* High-level I/O */
+ nand->ecc.read_oob = mil_ecc_read_oob;
+ nand->ecc.write_oob = mil_ecc_write_oob;
+
+ /* Bad Block Management */
+ nand->block_bad = mil_block_bad;
+ nand->scan_bbt = mil_scan_bbt;
+ nand->init_size = gpmi_init_size;
+ nand->badblock_pattern = &gpmi_bbt_descr;
+
+ /* Disallow partial page writes */
+ nand->options |= NAND_NO_SUBPAGE_WRITE;
+
+ /*
+ * Tell the NAND Flash MTD system that we'll be handling ECC with our
+ * own hardware. It turns out that we still have to fill in the ECC size
+ * because the MTD code will divide by it -- even though it doesn't
+ * actually care.
+ */
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.size = 1;
+
+ /* Allocate a temporary DMA buffer for reading ID in the nand_scan() */
+ this->nfc_geometry.payload_size_in_bytes = 1024;
+ this->nfc_geometry.auxiliary_size_in_bytes = 128;
+ error = mil_alloc_dma_buffer(this);
+ if (error)
+ goto exit_dma_allocation;
+
+ pr_info("Scanning for NAND Flash chips...\n");
+ error = nand_scan(mtd, pdata->max_chip_count);
+ if (error) {
+ log("Chip scan failed");
+ goto exit_nand_scan;
+ }
+
+ /* Take over the management of the OOB */
+ mil->hooked_block_markbad = mtd->block_markbad;
+ mtd->block_markbad = mil_hook_block_markbad;
+
+ /* Construct partitions as necessary. */
+ error = mil_partitions_init(this);
+ if (error)
+ goto exit_partitions;
+ return 0;
+
+exit_partitions:
+ nand_release(&mil->mtd);
+exit_nand_scan:
+ mil_free_dma_buffer(this);
+exit_dma_allocation:
+ return error;
+}
+
+void gpmi_nfc_mil_exit(struct gpmi_nfc_data *this)
+{
+ struct mil *mil = &this->mil;
+
+ mil_partitions_exit(this);
+ nand_release(&mil->mtd);
+ mil_free_dma_buffer(this);
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-common.c b/drivers/mtd/nand/gpmi-nfc/rom-common.c
new file mode 100644
index 0000000..6d11447
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-common.c
@@ -0,0 +1,48 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+int gpmi_nfc_rom_helper_set_geometry(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+
+ /*
+ * Set the boot block stride size.
+ *
+ * In principle, we should be reading this from the OTP bits, since
+ * that's where the ROM is going to get it. In fact, we don't have any
+ * way to read the OTP bits, so we go with the default and hope for the
+ * best.
+ */
+ geometry->stride_size_in_pages = 64;
+
+ /*
+ * Set the search area stride exponent.
+ *
+ * In principle, we should be reading this from the OTP bits, since
+ * that's where the ROM is going to get it. In fact, we don't have any
+ * way to read the OTP bits, so we go with the default and hope for the
+ * best.
+ */
+ geometry->search_area_stride_exponent = 2;
+
+ return 0;
+}
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-16 1:55 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux, Huang Shijie, linux-mtd, dwmw2, David.Woodhouse
This is a database for the NANDs which is now supported by imx23 and imx28.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181 ++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/nand_device_info.h | 145 +++++++++++++++++++++
2 files changed, 326 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.c b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
new file mode 100644
index 0000000..aa0813a
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <asm/sizes.h>
+#include <linux/mtd/nand.h>
+
+#include "nand_device_info.h"
+
+static struct nand_device_info samsung_nand[] __initdata = {
+ {
+ .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
+ .desc = "K9G8G08U0M, K9HAG08U1M",
+ .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
+ .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
+ }, {
+ .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
+ .desc = "K9LBG08U0D",
+ .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
+ .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
+ }, {
+ .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
+ .desc = "K9GAG08U0M",
+ .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
+ .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
+ }, {
+ /* end of the table. */
+ .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ },
+};
+
+/* macro to get the id bytes */
+#define ID_GET_MFR_CODE(id) ((id)[0])
+
+void nand_device_print_info(struct nand_device_info *info)
+{
+ unsigned i;
+ const char *mfr_name;
+ const char *cell_technology_name;
+ uint64_t chip_size;
+ const char *chip_size_units;
+ unsigned page_data_size_in_bytes;
+ unsigned page_oob_size_in_bytes;
+ struct nand_attr *attr = &info->attr;
+ struct nand_timing *timing = &info->timing;
+
+ /* Prepare the manufacturer name. */
+ mfr_name = "Unknown";
+ for (i = 0; nand_manuf_ids[i].id; i++) {
+ if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
+ mfr_name = nand_manuf_ids[i].name;
+ break;
+ }
+ }
+
+ /* Prepare the name of the cell technology. */
+ switch (attr->cell_technology) {
+ case SLC:
+ cell_technology_name = "SLC";
+ break;
+ case MLC:
+ cell_technology_name = "MLC";
+ break;
+ default:
+ cell_technology_name = "Unknown";
+ break;
+ }
+
+ /* Prepare the chip size. */
+ if ((attr->chip_size_in_bytes >= SZ_1G) &&
+ !(attr->chip_size_in_bytes % SZ_1G)) {
+ chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1G);
+ chip_size_units = "GiB";
+ } else if ((attr->chip_size_in_bytes >= SZ_1M) &&
+ !(attr->chip_size_in_bytes % SZ_1M)) {
+ chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1M);
+ chip_size_units = "MiB";
+ } else {
+ chip_size = attr->chip_size_in_bytes;
+ chip_size_units = "B";
+ }
+
+ /* Prepare the page geometry. */
+ page_data_size_in_bytes = (1<<(fls(attr->page_total_size_in_bytes)-1));
+ page_oob_size_in_bytes = attr->page_total_size_in_bytes -
+ page_data_size_in_bytes;
+
+ /* Print the infomation. */
+ printk(KERN_INFO "--------------------------------------\n");
+ printk(KERN_INFO " NAND device infomation (RAW)\n");
+ printk(KERN_INFO "--------------------------------------\n");
+ printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
+ info->id[0]);
+ printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
+ printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
+ printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
+ chip_size_units);
+ printk(KERN_INFO "Pages per Block : %u\n", attr->block_size_in_pages);
+ printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes,
+ page_oob_size_in_bytes);
+ printk(KERN_INFO "ECC Strength : %u bits\n",
+ attr->ecc_strength_in_bits);
+ printk(KERN_INFO "ECC Size : %u B\n", attr->ecc_size_in_bytes);
+ printk(KERN_INFO "Data Setup Time : %u ns\n",
+ timing->data_setup_in_ns);
+ printk(KERN_INFO "Data Hold Time : %u ns\n",
+ timing->data_hold_in_ns);
+ printk(KERN_INFO "Address Setup Time: %u ns\n",
+ timing->address_setup_in_ns);
+ printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
+ timing->gpmi_sample_delay_in_ns);
+ printk(KERN_INFO "tREA : %d ns\n",
+ (timing->tREA_in_ns >= 0 ?
+ timing->tREA_in_ns : -1));
+ printk(KERN_INFO "tRLOH : %d ns\n",
+ (timing->tRLOH_in_ns >= 0 ?
+ timing->tRLOH_in_ns : -1));
+ printk(KERN_INFO "tRHOH : %d ns\n",
+ (timing->tRHOH_in_ns >= 0 ?
+ timing->tRHOH_in_ns : -1));
+ printk(KERN_INFO "Description : %s\n", info->desc);
+}
+
+static struct nand_device_info * __init
+search_table(struct nand_device_info *table, const uint8_t id[])
+{
+ struct nand_device_info *info = table;
+
+ while (ID_GET_MFR_CODE(info->id)) {
+ int i;
+
+ /* match all the ids. Is it too strict? */
+ for (i = 0; i < ID_BYTES; i++)
+ if (info->id[i] != id[i])
+ break;
+
+ /* found it */
+ if (i == ID_BYTES) {
+ nand_device_print_info(info);
+ return info;
+ }
+
+ info++;
+ }
+ return NULL;
+}
+
+struct nand_device_mfr_info {
+ uint8_t id;
+ struct nand_device_info *table;
+};
+
+static struct nand_device_mfr_info nand_device_mfr_directory[] __initdata = {
+ { NAND_MFR_SAMSUNG, samsung_nand },
+ { 0, NULL },
+};
+
+struct nand_device_info * __init nand_device_get_info(const uint8_t id[])
+{
+ uint8_t mfr_id = ID_GET_MFR_CODE(id);
+ unsigned i;
+
+ for (i = 0; nand_device_mfr_directory[i].id; i++) {
+ if (nand_device_mfr_directory[i].id == mfr_id) {
+ struct nand_device_info *table;
+
+ table = nand_device_mfr_directory[i].table;
+ return search_table(table, id);
+ }
+ }
+ return NULL;
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
new file mode 100644
index 0000000..e606705
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __DRIVERS_NAND_DEVICE_INFO_H
+#define __DRIVERS_NAND_DEVICE_INFO_H
+
+enum nand_device_cell_technology {
+ SLC = 0,
+ MLC = 1,
+};
+
+/**
+ *
+ *
+ * @cell_technology: The storage cell technology.
+ * @chip_size_in_bytes: The total size of the storage behind a single
+ * chip select, in bytes. Notice that this is *not*
+ * necessarily the total size of the storage in a
+ * *package*, which may contain several chips.
+ * @block_size_in_pages: The number of pages in a block.
+ * @page_total_size_in_bytes: The total size of a page, in bytes, including
+ * both the data and the OOB.
+ * @ecc_strength_in_bits: The strength of the ECC called for by the
+ * manufacturer, in number of correctable bits.
+ * @ecc_size_in_bytes: The size of the data block over which the
+ * manufacturer calls for the given ECC algorithm
+ * and strength.
+ * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE nand ?
+ */
+struct nand_attr {
+ /* Technology */
+ enum nand_device_cell_technology cell_technology;
+
+ /* Geometry */
+ uint64_t chip_size_in_bytes;
+ uint32_t block_size_in_pages;
+ uint32_t page_total_size_in_bytes;
+
+ /* ECC */
+ uint16_t ecc_size_in_bytes;
+ uint16_t ecc_strength_in_bits;
+
+ /* Does the nand support DDR? (ONFI or TOGGLE) */
+ bool is_ddr_ok;
+};
+
+/**
+ * This structure contains the fundamental timing attributes for NAND.
+ *
+ * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
+ * maximum of tDS and tWP. A negative value
+ * indicates this characteristic isn't known.
+ * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
+ * maximum of tDH, tWH and tREH. A negative value
+ * indicates this characteristic isn't known.
+ * @address_setup_in_ns: The address setup time, in nanoseconds. Usually
+ * the maximum of tCLS, tCS and tALS. A negative
+ * value indicates this characteristic isn't known.
+ * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value
+ * indicates this characteristic isn't known.
+ * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
+ * negative value indicates this characteristic isn't
+ * known.
+ * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
+ * negative value indicates this characteristic isn't
+ * known.
+ * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
+ * negative value indicates this characteristic isn't
+ * known.
+ */
+struct nand_timing {
+ int8_t data_setup_in_ns;
+ int8_t data_hold_in_ns;
+ int8_t address_setup_in_ns;
+ int8_t gpmi_sample_delay_in_ns;
+ int8_t tREA_in_ns;
+ int8_t tRLOH_in_ns;
+ int8_t tRHOH_in_ns;
+};
+
+#define ID_BYTES (8)
+/*
+ * struct nand_device_info - Information about a single NAND Flash device.
+ *
+ * This structure contains all the *essential* information about a NAND Flash
+ * device, derived from the device's data sheet.
+ */
+struct nand_device_info {
+ /* id */
+ uint8_t id[ID_BYTES];
+
+ /* Description */
+ const char *desc;
+
+ /* attribute*/
+ struct nand_attr attr;
+
+ /* timing */
+ struct nand_timing timing;
+};
+
+/* macro for the NAND attribute */
+#define ATTR(_a, _b, _c, _d, _e, _f) \
+ { \
+ .cell_technology = (_a), \
+ .chip_size_in_bytes = (_b), \
+ .block_size_in_pages = (_c), \
+ .page_total_size_in_bytes = (_d), \
+ .ecc_strength_in_bits = (_e), \
+ .ecc_size_in_bytes = (_f), \
+ }
+
+/* macro for the NAND timing */
+#define TIMING(_a, _b, _c, _d, _e, _f, _h) \
+ { \
+ .data_setup_in_ns = (_a), \
+ .data_hold_in_ns = (_b), \
+ .address_setup_in_ns = (_c), \
+ .gpmi_sample_delay_in_ns = (_d), \
+ .tREA_in_ns = (_e), \
+ .tRLOH_in_ns = (_f), \
+ .tRHOH_in_ns = (_h), \
+ }
+
+struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
+void nand_device_print_info(struct nand_device_info *info);
+
+/*
+ * Check the NAND whether it supports the DDR mode.
+ * Only the ONFI nand and TOGGLE nand support the DDR now.
+ */
+static inline bool is_ddr_nand(struct nand_device_info *info)
+{
+ return info->attr.is_ddr_ok;
+}
+#endif
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
@ 2011-03-16 1:55 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel
This is a database for the NANDs which is now supported by imx23 and imx28.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181 ++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/nand_device_info.h | 145 +++++++++++++++++++++
2 files changed, 326 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.c b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
new file mode 100644
index 0000000..aa0813a
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <asm/sizes.h>
+#include <linux/mtd/nand.h>
+
+#include "nand_device_info.h"
+
+static struct nand_device_info samsung_nand[] __initdata = {
+ {
+ .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
+ .desc = "K9G8G08U0M, K9HAG08U1M",
+ .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
+ .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
+ }, {
+ .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
+ .desc = "K9LBG08U0D",
+ .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
+ .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
+ }, {
+ .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
+ .desc = "K9GAG08U0M",
+ .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
+ .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
+ }, {
+ /* end of the table. */
+ .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ },
+};
+
+/* macro to get the id bytes */
+#define ID_GET_MFR_CODE(id) ((id)[0])
+
+void nand_device_print_info(struct nand_device_info *info)
+{
+ unsigned i;
+ const char *mfr_name;
+ const char *cell_technology_name;
+ uint64_t chip_size;
+ const char *chip_size_units;
+ unsigned page_data_size_in_bytes;
+ unsigned page_oob_size_in_bytes;
+ struct nand_attr *attr = &info->attr;
+ struct nand_timing *timing = &info->timing;
+
+ /* Prepare the manufacturer name. */
+ mfr_name = "Unknown";
+ for (i = 0; nand_manuf_ids[i].id; i++) {
+ if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
+ mfr_name = nand_manuf_ids[i].name;
+ break;
+ }
+ }
+
+ /* Prepare the name of the cell technology. */
+ switch (attr->cell_technology) {
+ case SLC:
+ cell_technology_name = "SLC";
+ break;
+ case MLC:
+ cell_technology_name = "MLC";
+ break;
+ default:
+ cell_technology_name = "Unknown";
+ break;
+ }
+
+ /* Prepare the chip size. */
+ if ((attr->chip_size_in_bytes >= SZ_1G) &&
+ !(attr->chip_size_in_bytes % SZ_1G)) {
+ chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1G);
+ chip_size_units = "GiB";
+ } else if ((attr->chip_size_in_bytes >= SZ_1M) &&
+ !(attr->chip_size_in_bytes % SZ_1M)) {
+ chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1M);
+ chip_size_units = "MiB";
+ } else {
+ chip_size = attr->chip_size_in_bytes;
+ chip_size_units = "B";
+ }
+
+ /* Prepare the page geometry. */
+ page_data_size_in_bytes = (1<<(fls(attr->page_total_size_in_bytes)-1));
+ page_oob_size_in_bytes = attr->page_total_size_in_bytes -
+ page_data_size_in_bytes;
+
+ /* Print the infomation. */
+ printk(KERN_INFO "--------------------------------------\n");
+ printk(KERN_INFO " NAND device infomation (RAW)\n");
+ printk(KERN_INFO "--------------------------------------\n");
+ printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
+ info->id[0]);
+ printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
+ printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
+ printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
+ chip_size_units);
+ printk(KERN_INFO "Pages per Block : %u\n", attr->block_size_in_pages);
+ printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes,
+ page_oob_size_in_bytes);
+ printk(KERN_INFO "ECC Strength : %u bits\n",
+ attr->ecc_strength_in_bits);
+ printk(KERN_INFO "ECC Size : %u B\n", attr->ecc_size_in_bytes);
+ printk(KERN_INFO "Data Setup Time : %u ns\n",
+ timing->data_setup_in_ns);
+ printk(KERN_INFO "Data Hold Time : %u ns\n",
+ timing->data_hold_in_ns);
+ printk(KERN_INFO "Address Setup Time: %u ns\n",
+ timing->address_setup_in_ns);
+ printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
+ timing->gpmi_sample_delay_in_ns);
+ printk(KERN_INFO "tREA : %d ns\n",
+ (timing->tREA_in_ns >= 0 ?
+ timing->tREA_in_ns : -1));
+ printk(KERN_INFO "tRLOH : %d ns\n",
+ (timing->tRLOH_in_ns >= 0 ?
+ timing->tRLOH_in_ns : -1));
+ printk(KERN_INFO "tRHOH : %d ns\n",
+ (timing->tRHOH_in_ns >= 0 ?
+ timing->tRHOH_in_ns : -1));
+ printk(KERN_INFO "Description : %s\n", info->desc);
+}
+
+static struct nand_device_info * __init
+search_table(struct nand_device_info *table, const uint8_t id[])
+{
+ struct nand_device_info *info = table;
+
+ while (ID_GET_MFR_CODE(info->id)) {
+ int i;
+
+ /* match all the ids. Is it too strict? */
+ for (i = 0; i < ID_BYTES; i++)
+ if (info->id[i] != id[i])
+ break;
+
+ /* found it */
+ if (i == ID_BYTES) {
+ nand_device_print_info(info);
+ return info;
+ }
+
+ info++;
+ }
+ return NULL;
+}
+
+struct nand_device_mfr_info {
+ uint8_t id;
+ struct nand_device_info *table;
+};
+
+static struct nand_device_mfr_info nand_device_mfr_directory[] __initdata = {
+ { NAND_MFR_SAMSUNG, samsung_nand },
+ { 0, NULL },
+};
+
+struct nand_device_info * __init nand_device_get_info(const uint8_t id[])
+{
+ uint8_t mfr_id = ID_GET_MFR_CODE(id);
+ unsigned i;
+
+ for (i = 0; nand_device_mfr_directory[i].id; i++) {
+ if (nand_device_mfr_directory[i].id == mfr_id) {
+ struct nand_device_info *table;
+
+ table = nand_device_mfr_directory[i].table;
+ return search_table(table, id);
+ }
+ }
+ return NULL;
+}
diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
new file mode 100644
index 0000000..e606705
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __DRIVERS_NAND_DEVICE_INFO_H
+#define __DRIVERS_NAND_DEVICE_INFO_H
+
+enum nand_device_cell_technology {
+ SLC = 0,
+ MLC = 1,
+};
+
+/**
+ *
+ *
+ * @cell_technology: The storage cell technology.
+ * @chip_size_in_bytes: The total size of the storage behind a single
+ * chip select, in bytes. Notice that this is *not*
+ * necessarily the total size of the storage in a
+ * *package*, which may contain several chips.
+ * @block_size_in_pages: The number of pages in a block.
+ * @page_total_size_in_bytes: The total size of a page, in bytes, including
+ * both the data and the OOB.
+ * @ecc_strength_in_bits: The strength of the ECC called for by the
+ * manufacturer, in number of correctable bits.
+ * @ecc_size_in_bytes: The size of the data block over which the
+ * manufacturer calls for the given ECC algorithm
+ * and strength.
+ * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE nand ?
+ */
+struct nand_attr {
+ /* Technology */
+ enum nand_device_cell_technology cell_technology;
+
+ /* Geometry */
+ uint64_t chip_size_in_bytes;
+ uint32_t block_size_in_pages;
+ uint32_t page_total_size_in_bytes;
+
+ /* ECC */
+ uint16_t ecc_size_in_bytes;
+ uint16_t ecc_strength_in_bits;
+
+ /* Does the nand support DDR? (ONFI or TOGGLE) */
+ bool is_ddr_ok;
+};
+
+/**
+ * This structure contains the fundamental timing attributes for NAND.
+ *
+ * @data_setup_in_ns: The data setup time, in nanoseconds. Usually the
+ * maximum of tDS and tWP. A negative value
+ * indicates this characteristic isn't known.
+ * @data_hold_in_ns: The data hold time, in nanoseconds. Usually the
+ * maximum of tDH, tWH and tREH. A negative value
+ * indicates this characteristic isn't known.
+ * @address_setup_in_ns: The address setup time, in nanoseconds. Usually
+ * the maximum of tCLS, tCS and tALS. A negative
+ * value indicates this characteristic isn't known.
+ * @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative value
+ * indicates this characteristic isn't known.
+ * @tREA_in_ns: tREA, in nanoseconds, from the data sheet. A
+ * negative value indicates this characteristic isn't
+ * known.
+ * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet. A
+ * negative value indicates this characteristic isn't
+ * known.
+ * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet. A
+ * negative value indicates this characteristic isn't
+ * known.
+ */
+struct nand_timing {
+ int8_t data_setup_in_ns;
+ int8_t data_hold_in_ns;
+ int8_t address_setup_in_ns;
+ int8_t gpmi_sample_delay_in_ns;
+ int8_t tREA_in_ns;
+ int8_t tRLOH_in_ns;
+ int8_t tRHOH_in_ns;
+};
+
+#define ID_BYTES (8)
+/*
+ * struct nand_device_info - Information about a single NAND Flash device.
+ *
+ * This structure contains all the *essential* information about a NAND Flash
+ * device, derived from the device's data sheet.
+ */
+struct nand_device_info {
+ /* id */
+ uint8_t id[ID_BYTES];
+
+ /* Description */
+ const char *desc;
+
+ /* attribute*/
+ struct nand_attr attr;
+
+ /* timing */
+ struct nand_timing timing;
+};
+
+/* macro for the NAND attribute */
+#define ATTR(_a, _b, _c, _d, _e, _f) \
+ { \
+ .cell_technology = (_a), \
+ .chip_size_in_bytes = (_b), \
+ .block_size_in_pages = (_c), \
+ .page_total_size_in_bytes = (_d), \
+ .ecc_strength_in_bits = (_e), \
+ .ecc_size_in_bytes = (_f), \
+ }
+
+/* macro for the NAND timing */
+#define TIMING(_a, _b, _c, _d, _e, _f, _h) \
+ { \
+ .data_setup_in_ns = (_a), \
+ .data_hold_in_ns = (_b), \
+ .address_setup_in_ns = (_c), \
+ .gpmi_sample_delay_in_ns = (_d), \
+ .tREA_in_ns = (_e), \
+ .tRLOH_in_ns = (_f), \
+ .tRHOH_in_ns = (_h), \
+ }
+
+struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
+void nand_device_print_info(struct nand_device_info *info);
+
+/*
+ * Check the NAND whether it supports the DDR mode.
+ * Only the ONFI nand and TOGGLE nand support the DDR now.
+ */
+static inline bool is_ddr_nand(struct nand_device_info *info)
+{
+ return info->attr.is_ddr_ok;
+}
+#endif
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 4/7] add GPMI support for imx23
2011-03-16 1:55 ` Huang Shijie
@ 2011-07-08 16:42 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux, Huang Shijie, linux-mtd, dwmw2, David.Woodhouse
These files contain the code to implement the GPMI in the imx23.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h | 550 ++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h | 416 ++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-imx23.c | 556 +++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/rom-imx23.c | 300 +++++++++++++++
4 files changed, 1822 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx23.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx23.c
diff --git a/drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
new file mode 100644
index 0000000..9af4feb
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
@@ -0,0 +1,550 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL (0x00000000)
+#define HW_BCH_CTRL_SET (0x00000004)
+#define HW_BCH_CTRL_CLR (0x00000008)
+#define HW_BCH_CTRL_TOG (0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST 0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN 0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE 0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN 0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5 23
+#define BM_BCH_CTRL_RSVD5 0x3F800000
+#define BF_BCH_CTRL_RSVD5(v) (((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000
+#define BP_BCH_CTRL_RSVD4 20
+#define BM_BCH_CTRL_RSVD4 0x00300000
+#define BF_BCH_CTRL_RSVD4(v) (((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT 18
+#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE 0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE 0x00010000
+#define BP_BCH_CTRL_RSVD3 11
+#define BM_BCH_CTRL_RSVD3 0x0000F800
+#define BF_BCH_CTRL_RSVD3(v) (((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400
+#define BM_BCH_CTRL_RSVD2 0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
+#define BP_BCH_CTRL_RSVD1 4
+#define BM_BCH_CTRL_RSVD1 0x000000F0
+#define BF_BCH_CTRL_RSVD1(v) (((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004
+#define BM_BCH_CTRL_RSVD0 0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0 (0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE 20
+#define BM_BCH_STATUS0_HANDLE 0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+ (((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE 16
+#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v) \
+ (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0 8
+#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v) \
+ (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF
+#define BP_BCH_STATUS0_RSVD1 5
+#define BM_BCH_STATUS0_RSVD1 0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v) \
+ (((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES 0x00000010
+#define BM_BCH_STATUS0_CORRECTED 0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
+#define BP_BCH_STATUS0_RSVD0 0
+#define BM_BCH_STATUS0_RSVD0 0x00000003
+#define BF_BCH_STATUS0_RSVD0(v) \
+ (((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE (0x00000020)
+
+#define BP_BCH_MODE_RSVD 8
+#define BM_BCH_MODE_RSVD 0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+ (((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD 0
+#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v) \
+ (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR (0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR 0
+#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR (0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR 0
+#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR (0x00000050)
+
+#define BP_BCH_METAPTR_ADDR 0
+#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT (0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+ (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \
+ (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \
+ (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \
+ (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \
+ (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \
+ (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \
+ (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \
+ (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \
+ (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \
+ (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \
+ (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \
+ (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \
+ (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \
+ (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \
+ (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \
+ (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0 (0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0 12
+#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1 (0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN 12
+#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0 (0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0 12
+#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1 (0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN 12
+#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0 (0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0 12
+#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1 (0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN 12
+#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0 (0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0 12
+#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1 (0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN 12
+#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0 (0x00000100)
+#define HW_BCH_DEBUG0_SET (0x00000104)
+#define HW_BCH_DEBUG0_CLR (0x00000108)
+#define HW_BCH_DEBUG0_TOG (0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1 27
+#define BM_BCH_DEBUG0_RSVD1 0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+ (((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \
+ (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0 6
+#define BM_BCH_DEBUG0_RSVD0 0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v) \
+ (((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \
+ (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD (0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES 0
+#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD (0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES 0
+#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD (0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES 0
+#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD (0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES 0
+#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME (0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME 0
+#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION (0x00000160)
+
+#define BP_BCH_VERSION_MAJOR 24
+#define BM_BCH_VERSION_MAJOR 0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR 16
+#define BM_BCH_VERSION_MINOR 0x00FF0000
+#define BF_BCH_VERSION_MINOR(v) \
+ (((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP 0
+#define BM_BCH_VERSION_STEP 0x0000FFFF
+#define BF_BCH_VERSION_STEP(v) \
+ (((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
new file mode 100644
index 0000000..2f9fce6
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
@@ -0,0 +1,416 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0 (0x00000000)
+#define HW_GPMI_CTRL0_SET (0x00000004)
+#define HW_GPMI_CTRL0_CLR (0x00000008)
+#define HW_GPMI_CTRL0_TOG (0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST 0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN 0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
+#define BM_GPMI_CTRL0_CLKGATE 0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_GPMI_CTRL0_RUN 0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE 0x0
+#define BV_GPMI_CTRL0_RUN__BUSY 0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x08000000
+#define BM_GPMI_CTRL0_UDMA 0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE 24
+#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
+ (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
+#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1
+#define BP_GPMI_CTRL0_CS 20
+#define BM_GPMI_CTRL0_CS 0x00300000
+#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS 17
+#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
+#define BP_GPMI_CTRL0_XFER_COUNT 0
+#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v) \
+ (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE (0x00000010)
+
+#define BP_GPMI_COMPARE_MASK 16
+#define BM_GPMI_COMPARE_MASK 0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE 0
+#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v) \
+ (((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL (0x00000020)
+#define HW_GPMI_ECCCTRL_SET (0x00000024)
+#define HW_GPMI_ECCCTRL_CLR (0x00000028)
+#define HW_GPMI_ECCCTRL_TOG (0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE 16
+#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2 0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD 13
+#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
+#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+#define BP_GPMI_ECCCTRL_RSVD1 9
+#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v) (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \
+ (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x080
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x040
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x020
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x010
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x008
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x004
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x002
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x001
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT (0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2 16
+#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v) (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT 0
+#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD (0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS 2
+#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0 0
+#define BM_GPMI_PAYLOAD_RSVD0 0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v) (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY (0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS 2
+#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+ (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0 0
+#define BM_GPMI_AUXILIARY_RSVD0 0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v) (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1 (0x00000060)
+#define HW_GPMI_CTRL1_SET (0x00000064)
+#define HW_GPMI_CTRL1_CLR (0x00000068)
+#define HW_GPMI_CTRL1_TOG (0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2 24
+#define BM_GPMI_CTRL1_RSVD2 0xFF000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+ (((v) << 24) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_CE3_SEL 0x00800000
+#define BM_GPMI_CTRL1_CE2_SEL 0x00400000
+#define BM_GPMI_CTRL1_CE1_SEL 0x00200000
+#define BM_GPMI_CTRL1_CE0_SEL 0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BP_GPMI_CTRL1_GPMI_MODE 0
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE 17
+#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD 16
+#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v) \
+ (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_BURST_EN 0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x00000080
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x00000040
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x00000020
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x00000010
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0 (0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1 24
+#define BM_GPMI_TIMING0_RSVD1 0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+ (((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
+ (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD 8
+#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP 0
+#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1 (0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+ (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1 0
+#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v) \
+ (((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2 (0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP 24
+#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+ (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV 16
+#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v) \
+ (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD 8
+#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP 0
+#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA (0x000000a0)
+
+#define BP_GPMI_DATA_DATA 0
+#define BM_GPMI_DATA_DATA 0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v) (v)
+
+/*============================================================================*/
+
+#define HW_GPMI_STAT (0x000000b0)
+
+#define BM_GPMI_STAT_PRESENT 0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1
+#define BP_GPMI_STAT_RSVD1 12
+#define BM_GPMI_STAT_RSVD1 0x7FFFF000
+#define BF_GPMI_STAT_RSVD1(v) \
+ (((v) << 12) & BM_GPMI_STAT_RSVD1)
+#define BP_GPMI_STAT_RDY_TIMEOUT 8
+#define BM_GPMI_STAT_RDY_TIMEOUT 0x00000F00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v) \
+ (((v) << 8) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_ATA_IRQ 0x00000080
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000040
+#define BM_GPMI_STAT_FIFO_EMPTY 0x00000020
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1
+#define BM_GPMI_STAT_FIFO_FULL 0x00000010
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1
+#define BM_GPMI_STAT_DEV3_ERROR 0x00000008
+#define BM_GPMI_STAT_DEV2_ERROR 0x00000004
+#define BM_GPMI_STAT_DEV1_ERROR 0x00000002
+#define BM_GPMI_STAT_DEERROR 0x00000001
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG (0x000000c0)
+
+#define BM_GPMI_DEBUG_READY3 0x80000000
+#define BM_GPMI_DEBUG_READY2 0x40000000
+#define BM_GPMI_DEBUG_READY1 0x20000000
+#define BM_GPMI_DEBUG_READY0 0x10000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x08000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x04000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x02000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x01000000
+#define BM_GPMI_DEBUG_SENSE3 0x00800000
+#define BM_GPMI_DEBUG_SENSE2 0x00400000
+#define BM_GPMI_DEBUG_SENSE1 0x00200000
+#define BM_GPMI_DEBUG_SENSE0 0x00100000
+#define BM_GPMI_DEBUG_DMAREQ3 0x00080000
+#define BM_GPMI_DEBUG_DMAREQ2 0x00040000
+#define BM_GPMI_DEBUG_DMAREQ1 0x00020000
+#define BM_GPMI_DEBUG_DMAREQ0 0x00010000
+#define BP_GPMI_DEBUG_CMD_END 12
+#define BM_GPMI_DEBUG_CMD_END 0x0000F000
+#define BF_GPMI_DEBUG_CMD_END(v) \
+ (((v) << 12) & BM_GPMI_DEBUG_CMD_END)
+#define BP_GPMI_DEBUG_UDMA_STATE 8
+#define BM_GPMI_DEBUG_UDMA_STATE 0x00000F00
+#define BF_GPMI_DEBUG_UDMA_STATE(v) \
+ (((v) << 8) & BM_GPMI_DEBUG_UDMA_STATE)
+#define BM_GPMI_DEBUG_BUSY 0x00000080
+#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED 0x1
+#define BP_GPMI_DEBUG_PIN_STATE 4
+#define BM_GPMI_DEBUG_PIN_STATE 0x00000070
+#define BF_GPMI_DEBUG_PIN_STATE(v) \
+ (((v) << 4) & BM_GPMI_DEBUG_PIN_STATE)
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7
+#define BP_GPMI_DEBUG_MAIN_STATE 0
+#define BM_GPMI_DEBUG_MAIN_STATE 0x0000000F
+#define BF_GPMI_DEBUG_MAIN_STATE(v) \
+ (((v) << 0) & BM_GPMI_DEBUG_MAIN_STATE)
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xA
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION (0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR 24
+#define BM_GPMI_VERSION_MAJOR 0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR 16
+#define BM_GPMI_VERSION_MINOR 0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP 0
+#define BM_GPMI_VERSION_STEP 0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v) (((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2 (0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1 16
+#define BM_GPMI_DEBUG2_RSVD1 0xFFFF0000
+#define BF_GPMI_DEBUG2_RSVD1(v) (((v) << 16) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \
+ (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP 0
+#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3 (0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+ (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \
+ (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/hal-imx23.c b/drivers/mtd/nand/gpmi-nfc/hal-imx23.c
new file mode 100644
index 0000000..155ad67
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/hal-imx23.c
@@ -0,0 +1,556 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+#include "gpmi-regs-imx23.h"
+#include "bch-regs-imx23.h"
+
+static int init_hal_imx23(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ /* Enable the clock */
+ clk_enable(resources->clock);
+
+ /* Reset the GPMI block. */
+ mxs_reset_block(resources->gpmi_regs);
+
+ /* Choose NAND mode. */
+ __raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Set the IRQ polarity. */
+ __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable write protection. */
+ __raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Select BCH ECC. */
+ __raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable the clock. */
+ clk_disable(resources->clock);
+ return 0;
+}
+
+/* Configures the NFC geometry for BCH. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_geometry *nfc = &this->nfc_geometry;
+ unsigned int block_count;
+ unsigned int block_size;
+ unsigned int metadata_size;
+ unsigned int ecc_strength;
+ unsigned int page_size;
+
+ if (common_nfc_set_geometry(this))
+ return !0;
+
+ block_count = nfc->ecc_chunk_count - 1;
+ block_size = nfc->ecc_chunk_size_in_bytes;
+ metadata_size = nfc->metadata_size_in_bytes;
+ ecc_strength = nfc->ecc_strength >> 1;
+ page_size = nfc->page_size_in_bytes;
+
+ clk_enable(resources->clock);
+
+ /*
+ * Reset the BCH block. Notice that we pass in true for the just_enable
+ * flag. This is because the soft reset for the version 0 BCH block
+ * doesn't work. If you try to soft reset the BCH block, it becomes
+ * unusable until the next hard reset.
+ */
+ mxs_reset_block(resources->bch_regs);
+
+ /* Configure layout 0. */
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) |
+ BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+ BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) |
+ BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+ /* Set *all* chip selects to use layout 0. */
+ __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+ /* Enable interrupts. */
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+ resources->bch_regs + HW_BCH_CTRL_SET);
+
+ clk_disable(resources->clock);
+ return 0;
+}
+
+static int set_timing(struct gpmi_nfc_data *this,
+ const struct nand_timing *timing)
+{
+ struct nfc_hal *nfc = this->nfc;
+
+ nfc->timing = *timing;
+ return 0;
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this: Per-device data.
+ * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
+ * I/O transaction. If no I/O transaction is in
+ * progress, this is the clock frequency during the
+ * most recent I/O transaction.
+ * @hardware_timing: The hardware timing configuration in effect during
+ * the current I/O transaction. If no I/O transaction
+ * is in progress, this is the hardware timing
+ * configuration during the most recent I/O
+ * transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+ unsigned long *clock_frequency_in_hz,
+ struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ uint32_t register_image;
+
+ /* Return the clock frequency. */
+ *clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+ /* We'll be reading the hardware, so let's enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Retrieve the hardware timing. */
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+ hardware_timing->data_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+ BP_GPMI_TIMING0_DATA_SETUP;
+
+ hardware_timing->data_hold_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+ BP_GPMI_TIMING0_DATA_HOLD;
+
+ hardware_timing->address_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+ BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+ hardware_timing->use_half_periods =
+ (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+ BP_GPMI_CTRL1_HALF_PERIOD;
+
+ hardware_timing->sample_delay_factor =
+ (register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+ BP_GPMI_CTRL1_RDN_DELAY;
+
+ /* We're done reading the hardware, so disable the clock. */
+ clk_disable(resources->clock);
+}
+
+static void exit(struct gpmi_nfc_data *this)
+{
+}
+
+/* Begin the I/O */
+static void begin(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ struct gpmi_nfc_hardware_timing hw;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ unsigned int clock_period_in_ns;
+ uint32_t register_image;
+ unsigned int dll_wait_time_in_us;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Get the timing information we need. */
+ nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
+ clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
+
+ gpmi_nfc_compute_hardware_timing(this, &hw);
+
+ /* Set up all the simple timing parameters. */
+ register_image =
+ BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
+ BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
+ BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
+
+ __raw_writel(register_image, gpmi_regs + HW_GPMI_TIMING0);
+
+ /*
+ * HEY - PAY ATTENTION!
+ *
+ * DLL_ENABLE must be set to zero when setting RDN_DELAY or HALF_PERIOD.
+ */
+ __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Clear out the DLL control fields. */
+ __raw_writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR);
+ __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* If no sample delay is called for, return immediately. */
+ if (!hw.sample_delay_factor)
+ return;
+
+ /* Configure the HALF_PERIOD flag. */
+
+ if (hw.use_half_periods)
+ __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD,
+ gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Set the delay factor. */
+ __raw_writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
+ gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Enable the DLL. */
+ __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /*
+ * After we enable the GPMI DLL, we have to wait 64 clock cycles before
+ * we can use the GPMI.
+ *
+ * Calculate the amount of time we need to wait, in microseconds.
+ */
+ dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
+
+ if (!dll_wait_time_in_us)
+ dll_wait_time_in_us = 1;
+
+ /* Wait for the DLL to settle. */
+ udelay(dll_wait_time_in_us);
+}
+
+static void end(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ clk_disable(resources->clock);
+}
+
+/* Clears a BCH interrupt. */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+ struct resources *r = &this->resources;
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
+}
+
+/* Returns the Ready/Busy status of the given chip. */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+ struct resources *resources = &this->resources;
+ uint32_t mask;
+ uint32_t register_image;
+
+ mask = BM_GPMI_DEBUG_READY0 << chip;
+ register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_DEBUG);
+ return !!(register_image & mask);
+}
+
+static int send_command(struct gpmi_nfc_data *this)
+{
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ struct dma_async_tx_descriptor *desc;
+ struct scatterlist *sgl;
+ u32 pio[3];
+
+ /* [1] send out the PIO words */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
+ | BM_GPMI_CTRL0_ADDRESS_INCREMENT
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->command_length);
+ pio[1] = pio[2] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
+ sgl = &mil->cmd_sgl;
+
+ dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
+ sgl->length = mil->command_length;
+ desc = channel->device->device_prep_slave_sg(channel,
+ sgl, 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("error");
+ return -1;
+ }
+
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_COMMAND;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ uint32_t command_mode;
+ uint32_t address;
+ u32 pio[2];
+
+ log();
+ /* [1] PIO */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(mil->current_chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* step 2 : send DMA request */
+ prepare_data_dma(this, DMA_TO_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ /* [2] submit the DMA */
+ this->dma_type = DMA_FOR_WRITE_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int read_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ u32 pio[2];
+
+ /* step 1 : send PIO */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* step 2 : send DMA request */
+ prepare_data_dma(this, DMA_FROM_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_FROM_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_READ_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* A DMA descriptor that does an ECC page read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+ BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(0) ;
+ pio[1] = 0;
+ pio[2] =
+ BM_GPMI_ECCCTRL_ENABLE_ECC |
+ BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) |
+ BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ this->dma_type = DMA_FOR_WRITE_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+static int read_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* [1] Wait for the chip to report ready. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(0);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] Enable the BCH block and read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
+ | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes);
+
+ pio[1] = 0;
+ pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
+ | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
+ | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] Disable the BCH block */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes) ;
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 1);
+ if (!desc) {
+ log("step 3 error");
+ return -1;
+ }
+
+ /* [4] submit the DMA */
+ this->dma_type = DMA_FOR_READ_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+/* The NFC HAL for IMX23 */
+struct nfc_hal gpmi_nfc_hal_imx23 = {
+ .version = 0,
+ .description = "4-chip GPMI and BCH for IMX23",
+ .max_chip_count = 4,
+ .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
+ BP_GPMI_TIMING0_DATA_SETUP),
+ .internal_data_setup_in_ns = 0,
+ .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
+ BP_GPMI_CTRL1_RDN_DELAY),
+ .max_dll_clock_period_in_ns = 32,
+ .max_dll_delay_in_ns = 16,
+ .init = init_hal_imx23,
+ .set_geometry = set_geometry,
+ .set_timing = set_timing,
+ .get_timing = get_timing,
+ .exit = exit,
+ .begin = begin,
+ .end = end,
+ .clear_bch = clear_bch,
+ .is_ready = is_ready,
+ .send_command = send_command,
+ .read_data = read_data,
+ .send_data = send_data,
+ .read_page = read_page,
+ .send_page = send_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-imx23.c b/drivers/mtd/nand/gpmi-nfc/rom-imx23.c
new file mode 100644
index 0000000..8193874
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-imx23.c
@@ -0,0 +1,300 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+/* Useful variables for Boot ROM Helper version 0. */
+static const char *fingerprint = "STMP";
+
+/* Sets geometry for the Boot ROM Helper. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+ struct nand_chip *nand = &this->mil.nand;
+ int error;
+
+ error = gpmi_nfc_rom_helper_set_geometry(this);
+ if (error)
+ return error;
+
+ if (!pdata->boot_area_size_in_bytes) {
+ geometry->boot_area_count = 0;
+ geometry->boot_area_size_in_bytes = 0;
+ return 0;
+ }
+
+ if (nand->numchips == 1) {
+ geometry->boot_area_count = 1;
+ geometry->boot_area_size_in_bytes =
+ pdata->boot_area_size_in_bytes * 2;
+ } else {
+ geometry->boot_area_count = 2;
+ geometry->boot_area_size_in_bytes =
+ pdata->boot_area_size_in_bytes;
+ }
+ return 0;
+}
+
+static int check_transcription_stamp(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom_geo = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ unsigned int search_area_size_in_strides;
+ unsigned int stride;
+ unsigned int page;
+ loff_t byte;
+ uint8_t *buffer = nand->buffers->databuf;
+ int saved_chip_number;
+ int found_an_ncb_fingerprint = false;
+
+ /* Compute the number of strides in a search area. */
+ search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+
+ /* Select chip 0. */
+ saved_chip_number = mil->current_chip;
+ nand->select_chip(mtd, 0);
+
+ /*
+ * Loop through the first search area, looking for the NCB fingerprint.
+ */
+ pr_info("Scanning for an NCB fingerprint...\n");
+
+ for (stride = 0; stride < search_area_size_in_strides; stride++) {
+ /* Compute the page and byte addresses. */
+ page = stride * rom_geo->stride_size_in_pages;
+ byte = page * mtd->writesize;
+
+ pr_info(" Looking for a fingerprint in page 0x%x\n", page);
+
+ /*
+ * Read the NCB fingerprint. The fingerprint is four bytes long
+ * and starts in the 12th byte of the page.
+ */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, 12, page);
+ nand->read_buf(mtd, buffer, strlen(fingerprint));
+
+ /* Look for the fingerprint. */
+ if (!memcmp(buffer, fingerprint, strlen(fingerprint))) {
+ found_an_ncb_fingerprint = true;
+ break;
+ }
+
+ }
+
+ /* Deselect chip 0. */
+ nand->select_chip(mtd, saved_chip_number);
+
+ if (found_an_ncb_fingerprint)
+ pr_info(" Found a fingerprint\n");
+ else
+ pr_info(" No fingerprint found\n");
+ return found_an_ncb_fingerprint;
+}
+
+/* Writes a transcription stamp. */
+static int write_transcription_stamp(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct boot_rom_geometry *rom_geo = &this->rom_geometry;
+ struct nand_device_info *info = &this->device_info;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ unsigned int block_size_in_pages;
+ unsigned int search_area_size_in_strides;
+ unsigned int search_area_size_in_pages;
+ unsigned int search_area_size_in_blocks;
+ unsigned int block;
+ unsigned int stride;
+ unsigned int page;
+ loff_t byte;
+ uint8_t *buffer = nand->buffers->databuf;
+ int saved_chip_number;
+ int status;
+
+ /* Compute the search area geometry. */
+ block_size_in_pages = info->attr.block_size_in_pages;
+ search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+ search_area_size_in_pages = search_area_size_in_strides *
+ rom_geo->stride_size_in_pages;
+ search_area_size_in_blocks =
+ (search_area_size_in_pages + (block_size_in_pages - 1)) /
+ block_size_in_pages;
+
+ pr_info("-------------------------------------------\n");
+ pr_info("Search Area Geometry\n");
+ pr_info("-------------------------------------------\n");
+ pr_info("Search Area Size in Blocks : %u", search_area_size_in_blocks);
+ pr_info("Search Area Size in Strides: %u", search_area_size_in_strides);
+ pr_info("Search Area Size in Pages : %u", search_area_size_in_pages);
+
+ /* Select chip 0. */
+ saved_chip_number = mil->current_chip;
+ nand->select_chip(mtd, 0);
+
+ /* Loop over blocks in the first search area, erasing them. */
+ pr_info("Erasing the search area...\n");
+
+ for (block = 0; block < search_area_size_in_blocks; block++) {
+ /* Compute the page address. */
+ page = block * block_size_in_pages;
+
+ /* Erase this block. */
+ pr_info(" Erasing block 0x%x\n", block);
+ nand->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+ nand->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+
+ /* Wait for the erase to finish. */
+ status = nand->waitfunc(mtd, nand);
+ if (status & NAND_STATUS_FAIL)
+ dev_err(dev, "[%s] Erase failed.\n", __func__);
+ }
+
+ /* Write the NCB fingerprint into the page buffer. */
+ memset(buffer, ~0, mtd->writesize);
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+ memcpy(buffer + 12, fingerprint, strlen(fingerprint));
+
+ /* Loop through the first search area, writing NCB fingerprints. */
+ pr_info("Writing NCB fingerprints...\n");
+ for (stride = 0; stride < search_area_size_in_strides; stride++) {
+ /* Compute the page and byte addresses. */
+ page = stride * rom_geo->stride_size_in_pages;
+ byte = page * mtd->writesize;
+
+ /* Write the first page of the current stride. */
+ pr_info(" Writing an NCB fingerprint in page 0x%x\n", page);
+ nand->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+ nand->ecc.write_page_raw(mtd, nand, buffer);
+ nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ /* Wait for the write to finish. */
+ status = nand->waitfunc(mtd, nand);
+ if (status & NAND_STATUS_FAIL)
+ dev_err(dev, "[%s] Write failed.\n", __func__);
+ }
+
+ /* Deselect chip 0. */
+ nand->select_chip(mtd, saved_chip_number);
+ return 0;
+}
+
+static int imx23_rom_extra_init(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+ struct nand_chip *nand = &mil->nand;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_device_info *info = &this->device_info;
+ unsigned int block_count;
+ unsigned int block;
+ int chip;
+ int page;
+ loff_t byte;
+ uint8_t block_mark;
+ int error = 0;
+
+ /*
+ * If control arrives here, we can't use block mark swapping, which
+ * means we're forced to use transcription. First, scan for the
+ * transcription stamp. If we find it, then we don't have to do
+ * anything -- the block marks are already transcribed.
+ */
+ if (check_transcription_stamp(this))
+ return 0;
+
+ /*
+ * If control arrives here, we couldn't find a transcription stamp, so
+ * so we presume the block marks are in the conventional location.
+ */
+ pr_info("Transcribing bad block marks...\n");
+
+ /* Compute the number of blocks in the entire medium. */
+ block_count = info->attr.chip_size_in_bytes >> nand->phys_erase_shift;
+
+ /*
+ * Loop over all the blocks in the medium, transcribing block marks as
+ * we go.
+ */
+ for (block = 0; block < block_count; block++) {
+ /*
+ * Compute the chip, page and byte addresses for this block's
+ * conventional mark.
+ */
+ chip = block >> (nand->chip_shift - nand->phys_erase_shift);
+ page = block << (nand->phys_erase_shift - nand->page_shift);
+ byte = block << nand->phys_erase_shift;
+
+ /* Select the chip. */
+ nand->select_chip(mtd, chip);
+
+ /* Send the command to read the conventional block mark. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+
+ /* Read the conventional block mark. */
+ block_mark = nand->read_byte(mtd);
+
+ /*
+ * Check if the block is marked bad. If so, we need to mark it
+ * again, but this time the result will be a mark in the
+ * location where we transcribe block marks.
+ *
+ * Notice that we have to explicitly set the marking_a_bad_block
+ * member before we call through the block_markbad function
+ * pointer in the owning struct nand_chip. If we could call
+ * though the block_markbad function pointer in the owning
+ * struct mtd_info, which we have hooked, then this would be
+ * taken care of for us. Unfortunately, we can't because that
+ * higher-level code path will do things like consulting the
+ * in-memory bad block table -- which doesn't even exist yet!
+ * So, we have to call at a lower level and handle some details
+ * ourselves.
+ */
+ if (block_mark != 0xff) {
+ pr_info("Transcribing mark in block %u\n", block);
+ mil->marking_a_bad_block = true;
+ error = nand->block_markbad(mtd, byte);
+ mil->marking_a_bad_block = false;
+ if (error)
+ dev_err(dev, "Failed to mark block bad with "
+ "error %d\n", error);
+ }
+
+ /* Deselect the chip. */
+ nand->select_chip(mtd, -1);
+ }
+
+ /* Write the stamp that indicates we've transcribed the block marks. */
+ write_transcription_stamp(this);
+ return 0;
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+struct boot_rom_helper gpmi_nfc_boot_rom_imx23 = {
+ .version = 0,
+ .description = "Single/dual-chip boot area, "
+ "no block mark swapping",
+ .swap_block_mark = false,
+ .set_geometry = set_geometry,
+ .rom_extra_init = imx23_rom_extra_init,
+};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 5/7] add GPMI support for imx28
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-16 1:55 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux, Huang Shijie, linux-mtd, dwmw2, David.Woodhouse
These files contain the code to implement the GPMI in the imx28.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h | 557 +++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h | 421 ++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-imx28.c | 503 ++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/rom-imx28.c | 66 ++++
4 files changed, 1547 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx28.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx28.c
diff --git a/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
new file mode 100644
index 0000000..692db08
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
@@ -0,0 +1,557 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Xml Revision: 2.5
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL (0x00000000)
+#define HW_BCH_CTRL_SET (0x00000004)
+#define HW_BCH_CTRL_CLR (0x00000008)
+#define HW_BCH_CTRL_TOG (0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST 0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN 0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE 0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN 0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5 23
+#define BM_BCH_CTRL_RSVD5 0x3F800000
+#define BF_BCH_CTRL_RSVD5(v) \
+ (((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000
+#define BP_BCH_CTRL_RSVD4 20
+#define BM_BCH_CTRL_RSVD4 0x00300000
+#define BF_BCH_CTRL_RSVD4(v) \
+ (((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT 18
+#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v) \
+ (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE 0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE 0x00010000
+#define BP_BCH_CTRL_RSVD3 11
+#define BM_BCH_CTRL_RSVD3 0x0000F800
+#define BF_BCH_CTRL_RSVD3(v) \
+ (((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400
+#define BM_BCH_CTRL_RSVD2 0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
+#define BP_BCH_CTRL_RSVD1 4
+#define BM_BCH_CTRL_RSVD1 0x000000F0
+#define BF_BCH_CTRL_RSVD1(v) \
+ (((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004
+#define BM_BCH_CTRL_RSVD0 0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0 (0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE 20
+#define BM_BCH_STATUS0_HANDLE 0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+ (((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE 16
+#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v) \
+ (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0 8
+#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v) \
+ (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF
+#define BP_BCH_STATUS0_RSVD1 5
+#define BM_BCH_STATUS0_RSVD1 0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v) \
+ (((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES 0x00000010
+#define BM_BCH_STATUS0_CORRECTED 0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
+#define BP_BCH_STATUS0_RSVD0 0
+#define BM_BCH_STATUS0_RSVD0 0x00000003
+#define BF_BCH_STATUS0_RSVD0(v) \
+ (((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE (0x00000020)
+
+#define BP_BCH_MODE_RSVD 8
+#define BM_BCH_MODE_RSVD 0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+ (((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD 0
+#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v) \
+ (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR (0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR 0
+#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR (0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR 0
+#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR (0x00000050)
+
+#define BP_BCH_METAPTR_ADDR 0
+#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT (0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+ (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \
+ (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \
+ (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \
+ (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \
+ (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \
+ (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \
+ (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \
+ (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \
+ (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \
+ (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \
+ (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \
+ (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \
+ (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \
+ (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \
+ (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \
+ (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0 (0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0 12
+#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1 (0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN 12
+#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0 (0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0 12
+#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1 (0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN 12
+#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0 (0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0 12
+#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1 (0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN 12
+#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0 (0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0 12
+#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1 (0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN 12
+#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0 (0x00000100)
+#define HW_BCH_DEBUG0_SET (0x00000104)
+#define HW_BCH_DEBUG0_CLR (0x00000108)
+#define HW_BCH_DEBUG0_TOG (0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1 27
+#define BM_BCH_DEBUG0_RSVD1 0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+ (((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \
+ (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0 6
+#define BM_BCH_DEBUG0_RSVD0 0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v) \
+ (((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \
+ (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD (0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES 0
+#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD (0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES 0
+#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD (0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES 0
+#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD (0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES 0
+#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME (0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME 0
+#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION (0x00000160)
+
+#define BP_BCH_VERSION_MAJOR 24
+#define BM_BCH_VERSION_MAJOR 0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR 16
+#define BM_BCH_VERSION_MINOR 0x00FF0000
+#define BF_BCH_VERSION_MINOR(v) \
+ (((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP 0
+#define BM_BCH_VERSION_STEP 0x0000FFFF
+#define BF_BCH_VERSION_STEP(v) \
+ (((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
new file mode 100644
index 0000000..dcb3b7d
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
@@ -0,0 +1,421 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Xml Revision: 2.2
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0 (0x00000000)
+#define HW_GPMI_CTRL0_SET (0x00000004)
+#define HW_GPMI_CTRL0_CLR (0x00000008)
+#define HW_GPMI_CTRL0_TOG (0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST 0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN 0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
+#define BM_GPMI_CTRL0_CLKGATE 0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_GPMI_CTRL0_RUN 0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE 0x0
+#define BV_GPMI_CTRL0_RUN__BUSY 0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000
+#define BM_GPMI_CTRL0_LOCK_CS 0x08000000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1
+#define BM_GPMI_CTRL0_UDMA 0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE 24
+#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
+ (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
+#define BP_GPMI_CTRL0_CS 20
+#define BM_GPMI_CTRL0_CS 0x00700000
+#define BF_GPMI_CTRL0_CS(v) \
+ (((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS 17
+#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v) \
+ (((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
+#define BP_GPMI_CTRL0_XFER_COUNT 0
+#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v) \
+ (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE (0x00000010)
+
+#define BP_GPMI_COMPARE_MASK 16
+#define BM_GPMI_COMPARE_MASK 0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v) \
+ (((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE 0
+#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v) \
+ (((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL (0x00000020)
+#define HW_GPMI_ECCCTRL_SET (0x00000024)
+#define HW_GPMI_ECCCTRL_CLR (0x00000028)
+#define HW_GPMI_ECCCTRL_TOG (0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE 16
+#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v) \
+ (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2 0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD 13
+#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v) \
+ (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3
+#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+#define BP_GPMI_ECCCTRL_RSVD1 9
+#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v) \
+ (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \
+ (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT (0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2 16
+#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v) \
+ (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT 0
+#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v) \
+ (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD (0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS 2
+#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v) \
+ (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0 0
+#define BM_GPMI_PAYLOAD_RSVD0 0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v) \
+ (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY (0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS 2
+#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+ (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0 0
+#define BM_GPMI_AUXILIARY_RSVD0 0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v) \
+ (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1 (0x00000060)
+#define HW_GPMI_CTRL1_SET (0x00000064)
+#define HW_GPMI_CTRL1_CLR (0x00000068)
+#define HW_GPMI_CTRL1_TOG (0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2 25
+#define BM_GPMI_CTRL1_RSVD2 0xFE000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+ (((v) << 25) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000
+#define BP_GPMI_CTRL1_WRN_DLY_SEL 22
+#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000
+#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \
+ (((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL)
+#define BM_GPMI_CTRL1_RSVD1 0x00200000
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000
+#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE 17
+#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD 16
+#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v) \
+ (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_BURST_EN 0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) \
+ (((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL)
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0 (0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1 24
+#define BM_GPMI_TIMING0_RSVD1 0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+ (((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
+ (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD 8
+#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP 0
+#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1 (0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+ (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1 0
+#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v) \
+ (((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2 (0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP 24
+#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+ (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV 16
+#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v) \
+ (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD 8
+#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP 0
+#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA (0x000000a0)
+
+#define BP_GPMI_DATA_DATA 0
+#define BM_GPMI_DATA_DATA 0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v) (v)
+
+#define HW_GPMI_STAT (0x000000b0)
+
+#define BP_GPMI_STAT_READY_BUSY 24
+#define BM_GPMI_STAT_READY_BUSY 0xFF000000
+#define BF_GPMI_STAT_READY_BUSY(v) \
+ (((v) << 24) & BM_GPMI_STAT_READY_BUSY)
+#define BP_GPMI_STAT_RDY_TIMEOUT 16
+#define BM_GPMI_STAT_RDY_TIMEOUT 0x00FF0000
+#define BF_GPMI_STAT_RDY_TIMEOUT(v) \
+ (((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_DEV7_ERROR 0x00008000
+#define BM_GPMI_STAT_DEV6_ERROR 0x00004000
+#define BM_GPMI_STAT_DEV5_ERROR 0x00002000
+#define BM_GPMI_STAT_DEV4_ERROR 0x00001000
+#define BM_GPMI_STAT_DEV3_ERROR 0x00000800
+#define BM_GPMI_STAT_DEV2_ERROR 0x00000400
+#define BM_GPMI_STAT_DEERROR 0x00000200
+#define BM_GPMI_STAT_DEV0_ERROR 0x00000100
+#define BP_GPMI_STAT_RSVD1 5
+#define BM_GPMI_STAT_RSVD1 0x000000E0
+#define BF_GPMI_STAT_RSVD1(v) \
+ (((v) << 5) & BM_GPMI_STAT_RSVD1)
+#define BM_GPMI_STAT_ATA_IRQ 0x00000010
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000008
+#define BM_GPMI_STAT_FIFO_EMPTY 0x00000004
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1
+#define BM_GPMI_STAT_FIFO_FULL 0x00000002
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1
+#define BM_GPMI_STAT_PRESENT 0x00000001
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG (0x000000c0)
+
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END 0xFF000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \
+ (((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END)
+#define BP_GPMI_DEBUG_DMA_SENSE 16
+#define BM_GPMI_DEBUG_DMA_SENSE 0x00FF0000
+#define BF_GPMI_DEBUG_DMA_SENSE(v) \
+ (((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE)
+#define BP_GPMI_DEBUG_DMAREQ 8
+#define BM_GPMI_DEBUG_DMAREQ 0x0000FF00
+#define BF_GPMI_DEBUG_DMAREQ(v) \
+ (((v) << 8) & BM_GPMI_DEBUG_DMAREQ)
+#define BP_GPMI_DEBUG_CMD_END 0
+#define BM_GPMI_DEBUG_CMD_END 0x000000FF
+#define BF_GPMI_DEBUG_CMD_END(v) \
+ (((v) << 0) & BM_GPMI_DEBUG_CMD_END)
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION (0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR 24
+#define BM_GPMI_VERSION_MAJOR 0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR 16
+#define BM_GPMI_VERSION_MINOR 0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v) \
+ (((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP 0
+#define BM_GPMI_VERSION_STEP 0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v) \
+ (((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2 (0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1 28
+#define BM_GPMI_DEBUG2_RSVD1 0xF0000000
+#define BF_GPMI_DEBUG2_RSVD1(v) \
+ (((v) << 28) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_UDMA_STATE 24
+#define BM_GPMI_DEBUG2_UDMA_STATE 0x0F000000
+#define BF_GPMI_DEBUG2_UDMA_STATE(v) \
+ (((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE)
+#define BM_GPMI_DEBUG2_BUSY 0x00800000
+#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG2_BUSY__ENABLED 0x1
+#define BP_GPMI_DEBUG2_PIN_STATE 20
+#define BM_GPMI_DEBUG2_PIN_STATE 0x00700000
+#define BF_GPMI_DEBUG2_PIN_STATE(v) \
+ (((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE)
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7
+#define BP_GPMI_DEBUG2_MAIN_STATE 16
+#define BM_GPMI_DEBUG2_MAIN_STATE 0x000F0000
+#define BF_GPMI_DEBUG2_MAIN_STATE(v) \
+ (((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE)
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \
+ (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP 0
+#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v) \
+ (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3 (0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+ (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \
+ (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/hal-imx28.c b/drivers/mtd/nand/gpmi-nfc/hal-imx28.c
new file mode 100644
index 0000000..ff87d7f
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/hal-imx28.c
@@ -0,0 +1,503 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+#include "gpmi-regs-imx28.h"
+#include "bch-regs-imx28.h"
+
+static int init_hal_imx28(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Reset the GPMI block. */
+ mxs_reset_block(resources->gpmi_regs);
+
+ /* Choose NAND mode. */
+ __raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Set the IRQ polarity. */
+ __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable write protection. */
+ __raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Select BCH ECC. */
+ __raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable the clock. */
+ clk_disable(resources->clock);
+
+ return 0;
+}
+
+/* Configures the NFC geometry for BCH. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_geometry *nfc = &this->nfc_geometry;
+ unsigned int block_count;
+ unsigned int block_size;
+ unsigned int metadata_size;
+ unsigned int ecc_strength;
+ unsigned int page_size;
+
+ /* We make the abstract choices in a common function. */
+ if (common_nfc_set_geometry(this))
+ return !0;
+
+ /* Translate the abstract choices into register fields. */
+ block_count = nfc->ecc_chunk_count - 1;
+ block_size = nfc->ecc_chunk_size_in_bytes;
+ metadata_size = nfc->metadata_size_in_bytes;
+ ecc_strength = nfc->ecc_strength >> 1;
+ page_size = nfc->page_size_in_bytes;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+
+ /*
+ * Reset the BCH block. Notice that we pass in true for the just_enable
+ * flag. This is because the soft reset for the version 0 BCH block
+ * doesn't work and the version 1 BCH block is similar enough that we
+ * suspect the same (though this has not been officially tested). If you
+ * try to soft reset a version 0 BCH block, it becomes unusable until
+ * the next hard reset.
+ */
+ mxs_reset_block(resources->bch_regs);
+
+ /* Configure layout 0. */
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) |
+ BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+ BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) |
+ BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+ /* Set *all* chip selects to use layout 0. */
+ __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+ /* Enable interrupts. */
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+ resources->bch_regs + HW_BCH_CTRL_SET);
+
+ /* Disable the clock. */
+ clk_disable(resources->clock);
+
+ return 0;
+}
+
+static int set_timing(struct gpmi_nfc_data *this,
+ const struct nand_timing *timing)
+{
+ struct nfc_hal *nfc = this->nfc;
+
+ nfc->timing = *timing;
+ return 0;
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this: Per-device data.
+ * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
+ * I/O transaction. If no I/O transaction is in
+ * progress, this is the clock frequency during the
+ * most recent I/O transaction.
+ * @hardware_timing: The hardware timing configuration in effect during
+ * the current I/O transaction. If no I/O transaction
+ * is in progress, this is the hardware timing
+ * configuration during the most recent I/O
+ * transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+ unsigned long *clock_frequency_in_hz,
+ struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ uint32_t register_image;
+
+ /* Return the clock frequency. */
+ *clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+ /* We'll be reading the hardware, so let's enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Retrieve the hardware timing. */
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+ hardware_timing->data_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+ BP_GPMI_TIMING0_DATA_SETUP;
+
+ hardware_timing->data_hold_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+ BP_GPMI_TIMING0_DATA_HOLD;
+
+ hardware_timing->address_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+ BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+ hardware_timing->use_half_periods =
+ (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+ BP_GPMI_CTRL1_HALF_PERIOD;
+
+ hardware_timing->sample_delay_factor =
+ (register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+ BP_GPMI_CTRL1_RDN_DELAY;
+
+ /* We're done reading the hardware, so disable the clock. */
+ clk_disable(resources->clock);
+}
+
+static void exit(struct gpmi_nfc_data *this)
+{
+}
+
+static void begin(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+}
+
+static void end(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ clk_disable(resources->clock);
+}
+
+/* Clears a BCH interrupt. */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+ struct resources *r = &this->resources;
+
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
+}
+
+/* Returns the Ready/Busy status of the given chip. */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+ struct resources *resources = &this->resources;
+ uint32_t mask;
+ uint32_t register_image;
+
+ /* Extract and return the status. */
+ mask = BF_GPMI_STAT_READY_BUSY(1 << chip);
+ register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT);
+ return !!(register_image & mask);
+}
+
+/* Sends a command and associated addresses. */
+static int send_command(struct gpmi_nfc_data *this)
+{
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ struct dma_async_tx_descriptor *desc;
+ struct scatterlist *sgl;
+ u32 pio[3];
+
+ /* [1] send out the PIO words */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
+ | BM_GPMI_CTRL0_ADDRESS_INCREMENT
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->command_length);
+ pio[1] = pio[2] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
+ sgl = &mil->cmd_sgl;
+
+ dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
+ sgl->length = mil->command_length;
+ desc = channel->device->device_prep_slave_sg(channel,
+ sgl, 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("error");
+ return -1;
+ }
+
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_COMMAND;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ uint32_t command_mode;
+ uint32_t address;
+ u32 pio[2];
+
+ /* [1] PIO */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(mil->current_chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] : send DMA request */
+ prepare_data_dma(this, DMA_TO_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_WRITE_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int read_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ u32 pio[2];
+
+ /* [1] : send PIO */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] : setup DMA buffer */
+ prepare_data_dma(this, DMA_FROM_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_FROM_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] : submit the DMA */
+ this->dma_type = DMA_FOR_READ_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* A DMA descriptor that does an ECC page read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+ BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(0) ;
+ pio[1] = 0;
+ pio[2] =
+ BM_GPMI_ECCCTRL_ENABLE_ECC |
+ BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) |
+ BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ this->dma_type = DMA_FOR_WRITE_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+static int read_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* [1] Wait for the chip to report ready. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(0);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] Enable the BCH block and read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__DECODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
+ | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes);
+
+ pio[1] = 0;
+ pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
+ | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
+ | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] Disable the BCH block */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes) ;
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 1);
+ if (!desc) {
+ log("step 3 error");
+ return -1;
+ }
+
+ /* [4] submit the DMA */
+ this->dma_type = DMA_FOR_READ_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+/* This structure represents the NFC HAL for this version of the hardware. */
+struct nfc_hal gpmi_nfc_hal_imx28 = {
+ .version = 1,
+ .description = "8-chip GPMI and BCH",
+ .max_chip_count = 8,
+ .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
+ BP_GPMI_TIMING0_DATA_SETUP),
+ .internal_data_setup_in_ns = 0,
+ .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
+ BP_GPMI_CTRL1_RDN_DELAY),
+ .max_dll_clock_period_in_ns = 32,
+ .max_dll_delay_in_ns = 16,
+ .init = init_hal_imx28,
+ .set_geometry = set_geometry,
+ .set_timing = set_timing,
+ .get_timing = get_timing,
+ .exit = exit,
+ .begin = begin,
+ .end = end,
+ .clear_bch = clear_bch,
+ .is_ready = is_ready,
+ .send_command = send_command,
+ .read_data = read_data,
+ .send_data = send_data,
+ .send_page = send_page,
+ .read_page = read_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-imx28.c b/drivers/mtd/nand/gpmi-nfc/rom-imx28.c
new file mode 100644
index 0000000..03be07f
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-imx28.c
@@ -0,0 +1,66 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+/* Sets geometry for the Boot ROM Helper. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+ int error;
+
+ /* Version-independent geometry. */
+ error = gpmi_nfc_rom_helper_set_geometry(this);
+ if (error)
+ return error;
+
+ /*
+ * Check if the platform data indicates we are to protect the boot area.
+ */
+ if (!pdata->boot_area_size_in_bytes) {
+ geometry->boot_area_count = 0;
+ geometry->boot_area_size_in_bytes = 0;
+ return 0;
+ }
+
+ /*
+ * If control arrives here, we are supposed to set up partitions to
+ * protect the boot areas. In this version of the ROM, we support only
+ * one boot area.
+ */
+ geometry->boot_area_count = 1;
+
+ /*
+ * Use the platform's boot area size.
+ */
+ geometry->boot_area_size_in_bytes = pdata->boot_area_size_in_bytes;
+
+ return 0;
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+struct boot_rom_helper gpmi_nfc_boot_rom_imx28 = {
+ .version = 1,
+ .description = "Single-chip boot area, "
+ "block mark swapping supported",
+ .swap_block_mark = true,
+ .set_geometry = set_geometry,
+};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 5/7] add GPMI support for imx28
@ 2011-03-16 1:55 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel
These files contain the code to implement the GPMI in the imx28.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h | 557 +++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h | 421 ++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-imx28.c | 503 ++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/rom-imx28.c | 66 ++++
4 files changed, 1547 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx28.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx28.c
diff --git a/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
new file mode 100644
index 0000000..692db08
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx28.h
@@ -0,0 +1,557 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Xml Revision: 2.5
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL (0x00000000)
+#define HW_BCH_CTRL_SET (0x00000004)
+#define HW_BCH_CTRL_CLR (0x00000008)
+#define HW_BCH_CTRL_TOG (0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST 0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN 0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE 0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN 0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5 23
+#define BM_BCH_CTRL_RSVD5 0x3F800000
+#define BF_BCH_CTRL_RSVD5(v) \
+ (((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000
+#define BP_BCH_CTRL_RSVD4 20
+#define BM_BCH_CTRL_RSVD4 0x00300000
+#define BF_BCH_CTRL_RSVD4(v) \
+ (((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT 18
+#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v) \
+ (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE 0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE 0x00010000
+#define BP_BCH_CTRL_RSVD3 11
+#define BM_BCH_CTRL_RSVD3 0x0000F800
+#define BF_BCH_CTRL_RSVD3(v) \
+ (((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400
+#define BM_BCH_CTRL_RSVD2 0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
+#define BP_BCH_CTRL_RSVD1 4
+#define BM_BCH_CTRL_RSVD1 0x000000F0
+#define BF_BCH_CTRL_RSVD1(v) \
+ (((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004
+#define BM_BCH_CTRL_RSVD0 0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0 (0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE 20
+#define BM_BCH_STATUS0_HANDLE 0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+ (((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE 16
+#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v) \
+ (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0 8
+#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v) \
+ (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF
+#define BP_BCH_STATUS0_RSVD1 5
+#define BM_BCH_STATUS0_RSVD1 0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v) \
+ (((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES 0x00000010
+#define BM_BCH_STATUS0_CORRECTED 0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
+#define BP_BCH_STATUS0_RSVD0 0
+#define BM_BCH_STATUS0_RSVD0 0x00000003
+#define BF_BCH_STATUS0_RSVD0(v) \
+ (((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE (0x00000020)
+
+#define BP_BCH_MODE_RSVD 8
+#define BM_BCH_MODE_RSVD 0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+ (((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD 0
+#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v) \
+ (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR (0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR 0
+#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR (0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR 0
+#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR (0x00000050)
+
+#define BP_BCH_METAPTR_ADDR 0
+#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT (0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+ (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \
+ (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \
+ (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \
+ (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \
+ (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \
+ (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \
+ (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \
+ (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \
+ (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \
+ (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \
+ (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \
+ (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \
+ (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \
+ (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \
+ (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \
+ (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0 (0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0 12
+#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1 (0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN 12
+#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0 (0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0 12
+#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1 (0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN 12
+#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0 (0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0 12
+#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1 (0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN 12
+#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0 (0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0 12
+#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1 (0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN 12
+#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0 (0x00000100)
+#define HW_BCH_DEBUG0_SET (0x00000104)
+#define HW_BCH_DEBUG0_CLR (0x00000108)
+#define HW_BCH_DEBUG0_TOG (0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1 27
+#define BM_BCH_DEBUG0_RSVD1 0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+ (((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \
+ (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0 6
+#define BM_BCH_DEBUG0_RSVD0 0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v) \
+ (((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \
+ (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD (0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES 0
+#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD (0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES 0
+#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD (0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES 0
+#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD (0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES 0
+#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME (0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME 0
+#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION (0x00000160)
+
+#define BP_BCH_VERSION_MAJOR 24
+#define BM_BCH_VERSION_MAJOR 0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR 16
+#define BM_BCH_VERSION_MINOR 0x00FF0000
+#define BF_BCH_VERSION_MINOR(v) \
+ (((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP 0
+#define BM_BCH_VERSION_STEP 0x0000FFFF
+#define BF_BCH_VERSION_STEP(v) \
+ (((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
new file mode 100644
index 0000000..dcb3b7d
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx28.h
@@ -0,0 +1,421 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Xml Revision: 2.2
+ * Template revision: 26195
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0 (0x00000000)
+#define HW_GPMI_CTRL0_SET (0x00000004)
+#define HW_GPMI_CTRL0_CLR (0x00000008)
+#define HW_GPMI_CTRL0_TOG (0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST 0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN 0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
+#define BM_GPMI_CTRL0_CLKGATE 0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_GPMI_CTRL0_RUN 0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE 0x0
+#define BV_GPMI_CTRL0_RUN__BUSY 0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000
+#define BM_GPMI_CTRL0_LOCK_CS 0x08000000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1
+#define BM_GPMI_CTRL0_UDMA 0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE 24
+#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
+ (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
+#define BP_GPMI_CTRL0_CS 20
+#define BM_GPMI_CTRL0_CS 0x00700000
+#define BF_GPMI_CTRL0_CS(v) \
+ (((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS 17
+#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v) \
+ (((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
+#define BP_GPMI_CTRL0_XFER_COUNT 0
+#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v) \
+ (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE (0x00000010)
+
+#define BP_GPMI_COMPARE_MASK 16
+#define BM_GPMI_COMPARE_MASK 0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v) \
+ (((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE 0
+#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v) \
+ (((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL (0x00000020)
+#define HW_GPMI_ECCCTRL_SET (0x00000024)
+#define HW_GPMI_ECCCTRL_CLR (0x00000028)
+#define HW_GPMI_ECCCTRL_TOG (0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE 16
+#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v) \
+ (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2 0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD 13
+#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v) \
+ (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE 0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE2 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__RESERVE3 0x3
+#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+#define BP_GPMI_ECCCTRL_RSVD1 9
+#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v) \
+ (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \
+ (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT (0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2 16
+#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v) \
+ (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT 0
+#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v) \
+ (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD (0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS 2
+#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v) \
+ (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0 0
+#define BM_GPMI_PAYLOAD_RSVD0 0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v) \
+ (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY (0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS 2
+#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+ (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0 0
+#define BM_GPMI_AUXILIARY_RSVD0 0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v) \
+ (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1 (0x00000060)
+#define HW_GPMI_CTRL1_SET (0x00000064)
+#define HW_GPMI_CTRL1_CLR (0x00000068)
+#define HW_GPMI_CTRL1_TOG (0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2 25
+#define BM_GPMI_CTRL1_RSVD2 0xFE000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+ (((v) << 25) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_DECOUPLE_CS 0x01000000
+#define BP_GPMI_CTRL1_WRN_DLY_SEL 22
+#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000
+#define BF_GPMI_CTRL1_WRN_DLY_SEL(v) \
+ (((v) << 22) & BM_GPMI_CTRL1_WRN_DLY_SEL)
+#define BM_GPMI_CTRL1_RSVD1 0x00200000
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ_EN 0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000
+#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE 17
+#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD 16
+#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v) \
+ (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_BURST_EN 0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_REQUEST 0x00000080
+#define BP_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 4
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL 0x00000070
+#define BF_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(v) \
+ (((v) << 4) & BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL)
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0 (0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1 24
+#define BM_GPMI_TIMING0_RSVD1 0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+ (((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
+ (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD 8
+#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP 0
+#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1 (0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+ (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1 0
+#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v) \
+ (((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2 (0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP 24
+#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+ (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV 16
+#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v) \
+ (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD 8
+#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP 0
+#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA (0x000000a0)
+
+#define BP_GPMI_DATA_DATA 0
+#define BM_GPMI_DATA_DATA 0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v) (v)
+
+#define HW_GPMI_STAT (0x000000b0)
+
+#define BP_GPMI_STAT_READY_BUSY 24
+#define BM_GPMI_STAT_READY_BUSY 0xFF000000
+#define BF_GPMI_STAT_READY_BUSY(v) \
+ (((v) << 24) & BM_GPMI_STAT_READY_BUSY)
+#define BP_GPMI_STAT_RDY_TIMEOUT 16
+#define BM_GPMI_STAT_RDY_TIMEOUT 0x00FF0000
+#define BF_GPMI_STAT_RDY_TIMEOUT(v) \
+ (((v) << 16) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_DEV7_ERROR 0x00008000
+#define BM_GPMI_STAT_DEV6_ERROR 0x00004000
+#define BM_GPMI_STAT_DEV5_ERROR 0x00002000
+#define BM_GPMI_STAT_DEV4_ERROR 0x00001000
+#define BM_GPMI_STAT_DEV3_ERROR 0x00000800
+#define BM_GPMI_STAT_DEV2_ERROR 0x00000400
+#define BM_GPMI_STAT_DEERROR 0x00000200
+#define BM_GPMI_STAT_DEV0_ERROR 0x00000100
+#define BP_GPMI_STAT_RSVD1 5
+#define BM_GPMI_STAT_RSVD1 0x000000E0
+#define BF_GPMI_STAT_RSVD1(v) \
+ (((v) << 5) & BM_GPMI_STAT_RSVD1)
+#define BM_GPMI_STAT_ATA_IRQ 0x00000010
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000008
+#define BM_GPMI_STAT_FIFO_EMPTY 0x00000004
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1
+#define BM_GPMI_STAT_FIFO_FULL 0x00000002
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1
+#define BM_GPMI_STAT_PRESENT 0x00000001
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG (0x000000c0)
+
+#define BP_GPMI_DEBUG_WAIT_FOR_READY_END 24
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END 0xFF000000
+#define BF_GPMI_DEBUG_WAIT_FOR_READY_END(v) \
+ (((v) << 24) & BM_GPMI_DEBUG_WAIT_FOR_READY_END)
+#define BP_GPMI_DEBUG_DMA_SENSE 16
+#define BM_GPMI_DEBUG_DMA_SENSE 0x00FF0000
+#define BF_GPMI_DEBUG_DMA_SENSE(v) \
+ (((v) << 16) & BM_GPMI_DEBUG_DMA_SENSE)
+#define BP_GPMI_DEBUG_DMAREQ 8
+#define BM_GPMI_DEBUG_DMAREQ 0x0000FF00
+#define BF_GPMI_DEBUG_DMAREQ(v) \
+ (((v) << 8) & BM_GPMI_DEBUG_DMAREQ)
+#define BP_GPMI_DEBUG_CMD_END 0
+#define BM_GPMI_DEBUG_CMD_END 0x000000FF
+#define BF_GPMI_DEBUG_CMD_END(v) \
+ (((v) << 0) & BM_GPMI_DEBUG_CMD_END)
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION (0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR 24
+#define BM_GPMI_VERSION_MAJOR 0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR 16
+#define BM_GPMI_VERSION_MINOR 0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v) \
+ (((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP 0
+#define BM_GPMI_VERSION_STEP 0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v) \
+ (((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2 (0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1 28
+#define BM_GPMI_DEBUG2_RSVD1 0xF0000000
+#define BF_GPMI_DEBUG2_RSVD1(v) \
+ (((v) << 28) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_UDMA_STATE 24
+#define BM_GPMI_DEBUG2_UDMA_STATE 0x0F000000
+#define BF_GPMI_DEBUG2_UDMA_STATE(v) \
+ (((v) << 24) & BM_GPMI_DEBUG2_UDMA_STATE)
+#define BM_GPMI_DEBUG2_BUSY 0x00800000
+#define BV_GPMI_DEBUG2_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG2_BUSY__ENABLED 0x1
+#define BP_GPMI_DEBUG2_PIN_STATE 20
+#define BM_GPMI_DEBUG2_PIN_STATE 0x00700000
+#define BF_GPMI_DEBUG2_PIN_STATE(v) \
+ (((v) << 20) & BM_GPMI_DEBUG2_PIN_STATE)
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_IDLE 0x0
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ADDR 0x2
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STALL 0x3
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DHOLD 0x6
+#define BV_GPMI_DEBUG2_PIN_STATE__PSM_DONE 0x7
+#define BP_GPMI_DEBUG2_MAIN_STATE 16
+#define BM_GPMI_DEBUG2_MAIN_STATE 0x000F0000
+#define BF_GPMI_DEBUG2_MAIN_STATE(v) \
+ (((v) << 16) & BM_GPMI_DEBUG2_MAIN_STATE)
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_IDLE 0x0
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_RDCMP 0x9
+#define BV_GPMI_DEBUG2_MAIN_STATE__MSM_DONE 0xA
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \
+ (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP 0
+#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v) \
+ (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3 (0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+ (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \
+ (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/hal-imx28.c b/drivers/mtd/nand/gpmi-nfc/hal-imx28.c
new file mode 100644
index 0000000..ff87d7f
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/hal-imx28.c
@@ -0,0 +1,503 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+#include "gpmi-regs-imx28.h"
+#include "bch-regs-imx28.h"
+
+static int init_hal_imx28(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Reset the GPMI block. */
+ mxs_reset_block(resources->gpmi_regs);
+
+ /* Choose NAND mode. */
+ __raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Set the IRQ polarity. */
+ __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable write protection. */
+ __raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Select BCH ECC. */
+ __raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable the clock. */
+ clk_disable(resources->clock);
+
+ return 0;
+}
+
+/* Configures the NFC geometry for BCH. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_geometry *nfc = &this->nfc_geometry;
+ unsigned int block_count;
+ unsigned int block_size;
+ unsigned int metadata_size;
+ unsigned int ecc_strength;
+ unsigned int page_size;
+
+ /* We make the abstract choices in a common function. */
+ if (common_nfc_set_geometry(this))
+ return !0;
+
+ /* Translate the abstract choices into register fields. */
+ block_count = nfc->ecc_chunk_count - 1;
+ block_size = nfc->ecc_chunk_size_in_bytes;
+ metadata_size = nfc->metadata_size_in_bytes;
+ ecc_strength = nfc->ecc_strength >> 1;
+ page_size = nfc->page_size_in_bytes;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+
+ /*
+ * Reset the BCH block. Notice that we pass in true for the just_enable
+ * flag. This is because the soft reset for the version 0 BCH block
+ * doesn't work and the version 1 BCH block is similar enough that we
+ * suspect the same (though this has not been officially tested). If you
+ * try to soft reset a version 0 BCH block, it becomes unusable until
+ * the next hard reset.
+ */
+ mxs_reset_block(resources->bch_regs);
+
+ /* Configure layout 0. */
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) |
+ BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+ BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) |
+ BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+ /* Set *all* chip selects to use layout 0. */
+ __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+ /* Enable interrupts. */
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+ resources->bch_regs + HW_BCH_CTRL_SET);
+
+ /* Disable the clock. */
+ clk_disable(resources->clock);
+
+ return 0;
+}
+
+static int set_timing(struct gpmi_nfc_data *this,
+ const struct nand_timing *timing)
+{
+ struct nfc_hal *nfc = this->nfc;
+
+ nfc->timing = *timing;
+ return 0;
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this: Per-device data.
+ * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
+ * I/O transaction. If no I/O transaction is in
+ * progress, this is the clock frequency during the
+ * most recent I/O transaction.
+ * @hardware_timing: The hardware timing configuration in effect during
+ * the current I/O transaction. If no I/O transaction
+ * is in progress, this is the hardware timing
+ * configuration during the most recent I/O
+ * transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+ unsigned long *clock_frequency_in_hz,
+ struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ uint32_t register_image;
+
+ /* Return the clock frequency. */
+ *clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+ /* We'll be reading the hardware, so let's enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Retrieve the hardware timing. */
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+ hardware_timing->data_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+ BP_GPMI_TIMING0_DATA_SETUP;
+
+ hardware_timing->data_hold_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+ BP_GPMI_TIMING0_DATA_HOLD;
+
+ hardware_timing->address_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+ BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+ hardware_timing->use_half_periods =
+ (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+ BP_GPMI_CTRL1_HALF_PERIOD;
+
+ hardware_timing->sample_delay_factor =
+ (register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+ BP_GPMI_CTRL1_RDN_DELAY;
+
+ /* We're done reading the hardware, so disable the clock. */
+ clk_disable(resources->clock);
+}
+
+static void exit(struct gpmi_nfc_data *this)
+{
+}
+
+static void begin(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+}
+
+static void end(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ clk_disable(resources->clock);
+}
+
+/* Clears a BCH interrupt. */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+ struct resources *r = &this->resources;
+
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
+}
+
+/* Returns the Ready/Busy status of the given chip. */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+ struct resources *resources = &this->resources;
+ uint32_t mask;
+ uint32_t register_image;
+
+ /* Extract and return the status. */
+ mask = BF_GPMI_STAT_READY_BUSY(1 << chip);
+ register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_STAT);
+ return !!(register_image & mask);
+}
+
+/* Sends a command and associated addresses. */
+static int send_command(struct gpmi_nfc_data *this)
+{
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ struct dma_async_tx_descriptor *desc;
+ struct scatterlist *sgl;
+ u32 pio[3];
+
+ /* [1] send out the PIO words */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
+ | BM_GPMI_CTRL0_ADDRESS_INCREMENT
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->command_length);
+ pio[1] = pio[2] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
+ sgl = &mil->cmd_sgl;
+
+ dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
+ sgl->length = mil->command_length;
+ desc = channel->device->device_prep_slave_sg(channel,
+ sgl, 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("error");
+ return -1;
+ }
+
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_COMMAND;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ uint32_t command_mode;
+ uint32_t address;
+ u32 pio[2];
+
+ /* [1] PIO */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(mil->current_chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] : send DMA request */
+ prepare_data_dma(this, DMA_TO_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_WRITE_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int read_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ u32 pio[2];
+
+ /* [1] : send PIO */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] : setup DMA buffer */
+ prepare_data_dma(this, DMA_FROM_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_FROM_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] : submit the DMA */
+ this->dma_type = DMA_FOR_READ_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* A DMA descriptor that does an ECC page read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__ENCODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+ BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(0) ;
+ pio[1] = 0;
+ pio[2] =
+ BM_GPMI_ECCCTRL_ENABLE_ECC |
+ BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) |
+ BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ this->dma_type = DMA_FOR_WRITE_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+static int read_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* [1] Wait for the chip to report ready. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(0);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] Enable the BCH block and read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__DECODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
+ | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes);
+
+ pio[1] = 0;
+ pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
+ | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
+ | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] Disable the BCH block */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes) ;
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 1);
+ if (!desc) {
+ log("step 3 error");
+ return -1;
+ }
+
+ /* [4] submit the DMA */
+ this->dma_type = DMA_FOR_READ_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+/* This structure represents the NFC HAL for this version of the hardware. */
+struct nfc_hal gpmi_nfc_hal_imx28 = {
+ .version = 1,
+ .description = "8-chip GPMI and BCH",
+ .max_chip_count = 8,
+ .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
+ BP_GPMI_TIMING0_DATA_SETUP),
+ .internal_data_setup_in_ns = 0,
+ .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
+ BP_GPMI_CTRL1_RDN_DELAY),
+ .max_dll_clock_period_in_ns = 32,
+ .max_dll_delay_in_ns = 16,
+ .init = init_hal_imx28,
+ .set_geometry = set_geometry,
+ .set_timing = set_timing,
+ .get_timing = get_timing,
+ .exit = exit,
+ .begin = begin,
+ .end = end,
+ .clear_bch = clear_bch,
+ .is_ready = is_ready,
+ .send_command = send_command,
+ .read_data = read_data,
+ .send_data = send_data,
+ .send_page = send_page,
+ .read_page = read_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-imx28.c b/drivers/mtd/nand/gpmi-nfc/rom-imx28.c
new file mode 100644
index 0000000..03be07f
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-imx28.c
@@ -0,0 +1,66 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+/* Sets geometry for the Boot ROM Helper. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+ int error;
+
+ /* Version-independent geometry. */
+ error = gpmi_nfc_rom_helper_set_geometry(this);
+ if (error)
+ return error;
+
+ /*
+ * Check if the platform data indicates we are to protect the boot area.
+ */
+ if (!pdata->boot_area_size_in_bytes) {
+ geometry->boot_area_count = 0;
+ geometry->boot_area_size_in_bytes = 0;
+ return 0;
+ }
+
+ /*
+ * If control arrives here, we are supposed to set up partitions to
+ * protect the boot areas. In this version of the ROM, we support only
+ * one boot area.
+ */
+ geometry->boot_area_count = 1;
+
+ /*
+ * Use the platform's boot area size.
+ */
+ geometry->boot_area_size_in_bytes = pdata->boot_area_size_in_bytes;
+
+ return 0;
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+struct boot_rom_helper gpmi_nfc_boot_rom_imx28 = {
+ .version = 1,
+ .description = "Single-chip boot area, "
+ "block mark swapping supported",
+ .swap_block_mark = true,
+ .set_geometry = set_geometry,
+};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 6/7] dmaengine: change the flags of request_irq()
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-16 1:55 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux, Huang Shijie, linux-mtd, dwmw2, David.Woodhouse
The GPMI may have many DMA channels, such as the imx23 has
four DMA channels. All these DMA channels share the same interrupt.
So change the flags from '0' to IRQF_SHARED, else there will be
an EBUSY error returns.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/dma/mxs-dma.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 88aad4f..0ee5b52 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -328,7 +328,7 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
memset(mxs_chan->ccw, 0, PAGE_SIZE);
ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
- 0, "mxs-dma", mxs_dma);
+ IRQF_SHARED, "mxs-dma", mxs_dma);
if (ret)
goto err_irq;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 6/7] dmaengine: change the flags of request_irq()
@ 2011-03-16 1:55 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel
The GPMI may have many DMA channels, such as the imx23 has
four DMA channels. All these DMA channels share the same interrupt.
So change the flags from '0' to IRQF_SHARED, else there will be
an EBUSY error returns.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/dma/mxs-dma.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/dma/mxs-dma.c b/drivers/dma/mxs-dma.c
index 88aad4f..0ee5b52 100644
--- a/drivers/dma/mxs-dma.c
+++ b/drivers/dma/mxs-dma.c
@@ -328,7 +328,7 @@ static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
memset(mxs_chan->ccw, 0, PAGE_SIZE);
ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
- 0, "mxs-dma", mxs_dma);
+ IRQF_SHARED, "mxs-dma", mxs_dma);
if (ret)
goto err_irq;
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 7/7] MTD : add GPMI driver in the config and Makefile
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-16 1:55 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: linux, Huang Shijie, linux-mtd, dwmw2, David.Woodhouse
add the GPMI driver in the relevant Kconfig and Makefile in the MTD.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/Kconfig | 10 ++++++++++
drivers/mtd/nand/Makefile | 1 +
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 450afc5..86effe8 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -426,6 +426,16 @@ config MTD_NAND_NANDSIM
The simulator may simulate various NAND flash chips for the
MTD nand layer.
+config MTD_NAND_GPMI_NFC
+ bool "GPMI NAND Flash Controller driver"
+ depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28)
+ select MTD_PARTITIONS
+ help
+ Enables NAND Flash support for IMX23 or IMX28.
+ The GPMI controller is very powerful, with the help of BCH
+ module, it can do the hardware ECC. The GPMI supports several
+ NAND flashs at the same time.
+
config MTD_NAND_PLATFORM
tristate "Support for generic platform NAND driver"
help
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8ad6fae..80d1f08 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -48,5 +48,6 @@ obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o
obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
+obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc/
nand-objs := nand_base.o nand_bbt.o
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 7/7] MTD : add GPMI driver in the config and Makefile
@ 2011-03-16 1:55 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:55 UTC (permalink / raw)
To: linux-arm-kernel
add the GPMI driver in the relevant Kconfig and Makefile in the MTD.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/Kconfig | 10 ++++++++++
drivers/mtd/nand/Makefile | 1 +
2 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 450afc5..86effe8 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -426,6 +426,16 @@ config MTD_NAND_NANDSIM
The simulator may simulate various NAND flash chips for the
MTD nand layer.
+config MTD_NAND_GPMI_NFC
+ bool "GPMI NAND Flash Controller driver"
+ depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28)
+ select MTD_PARTITIONS
+ help
+ Enables NAND Flash support for IMX23 or IMX28.
+ The GPMI controller is very powerful, with the help of BCH
+ module, it can do the hardware ECC. The GPMI supports several
+ NAND flashs at the same time.
+
config MTD_NAND_PLATFORM
tristate "Support for generic platform NAND driver"
help
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8ad6fae..80d1f08 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -48,5 +48,6 @@ obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o
obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
+obj-$(CONFIG_MTD_NAND_GPMI_NFC) += gpmi-nfc/
nand-objs := nand_base.o nand_bbt.o
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-16 7:12 ` Artem Bityutskiy
-1 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-16 7:12 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> The general-purpose media interface(GPMI) controller is a flexible interface
> to up to several NAND flashs.
Is there any public documentation for this controller?
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
@ 2011-03-16 7:12 ` Artem Bityutskiy
0 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-16 7:12 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> The general-purpose media interface(GPMI) controller is a flexible interface
> to up to several NAND flashs.
Is there any public documentation for this controller?
--
Best Regards,
Artem Bityutskiy (????? ????????)
^ permalink raw reply [flat|nested] 49+ messages in thread
* RE: [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
2011-03-16 7:12 ` Artem Bityutskiy
@ 2011-03-16 7:30 ` Huang Shijie-B32955
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie-B32955 @ 2011-03-16 7:30 UTC (permalink / raw)
To: dedekind1; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
Hi:
Yes.
You can download the documents for imx23/imx28 in the following links:
FOR IMX23:
http://www.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf?fpsp=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation
FOR IMX28:
http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf?fr=g
You can find the relevant chapters about the GPMI in the documents.
Best Regards
Huang Shijie
-----Original Message-----
From: Artem Bityutskiy [mailto:dedekind1@gmail.com]
Sent: Wednesday, March 16, 2011 3:12 PM
To: Huang Shijie-B32955
Cc: linux-arm-kernel@lists.infradead.org; linux@arm.linux.org.uk; linux-mtd@lists.infradead.org; dwmw2@infradead.org; David.Woodhouse@intel.com
Subject: Re: [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> The general-purpose media interface(GPMI) controller is a flexible
> interface to up to several NAND flashs.
Is there any public documentation for this controller?
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
@ 2011-03-16 7:30 ` Huang Shijie-B32955
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie-B32955 @ 2011-03-16 7:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi:
Yes.
You can download the documents for imx23/imx28 in the following links:
FOR IMX23:
http://www.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf?fpsp=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation
FOR IMX28:
http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf?fr=g
You can find the relevant chapters about the GPMI in the documents.
Best Regards
Huang Shijie
-----Original Message-----
From: Artem Bityutskiy [mailto:dedekind1 at gmail.com]
Sent: Wednesday, March 16, 2011 3:12 PM
To: Huang Shijie-B32955
Cc: linux-arm-kernel at lists.infradead.org; linux at arm.linux.org.uk; linux-mtd at lists.infradead.org; dwmw2 at infradead.org; David.Woodhouse at intel.com
Subject: Re: [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> The general-purpose media interface(GPMI) controller is a flexible
> interface to up to several NAND flashs.
Is there any public documentation for this controller?
--
Best Regards,
Artem Bityutskiy (????? ????????)
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
2011-03-16 7:12 ` Artem Bityutskiy
@ 2011-03-22 10:23 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-22 10:23 UTC (permalink / raw)
To: dedekind1; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
Hi Artem:
Do you have any comments about this driver?
thanks.
Huang Shijie
> On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
>> The general-purpose media interface(GPMI) controller is a flexible interface
>> to up to several NAND flashs.
> Is there any public documentation for this controller?
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28
@ 2011-03-22 10:23 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-22 10:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi Artem:
Do you have any comments about this driver?
thanks.
Huang Shijie
> On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
>> The general-purpose media interface(GPMI) controller is a flexible interface
>> to up to several NAND flashs.
> Is there any public documentation for this controller?
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 3/7] add the database for the NANDs
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-23 15:29 ` Florian Fainelli
-1 siblings, 0 replies; 49+ messages in thread
From: Florian Fainelli @ 2011-03-23 15:29 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Huang Shijie, linux, dwmw2, linux-mtd, David.Woodhouse
Hello Huang,
On Wednesday 16 March 2011 02:55:17 Huang Shijie wrote:
> This is a database for the NANDs which is now supported by imx23 and imx28.
>
> Signed-off-by: Huang Shijie <b32955@freescale.com>
> ---
> drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181
> ++++++++++++++++++++++++++ drivers/mtd/nand/gpmi-nfc/nand_device_info.h |
> 145 +++++++++++++++++++++ 2 files changed, 326 insertions(+), 0
> deletions(-)
> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>
> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c new file mode 100644
> index 0000000..aa0813a
> --- /dev/null
> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> @@ -0,0 +1,181 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <asm/sizes.h>
> +#include <linux/mtd/nand.h>
> +
> +#include "nand_device_info.h"
> +
> +static struct nand_device_info samsung_nand[] __initdata = {
> + {
> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
> + .desc = "K9G8G08U0M, K9HAG08U1M",
> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
> + }, {
> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
> + .desc = "K9LBG08U0D",
> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
> + }, {
> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
> + .desc = "K9GAG08U0M",
> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
> + }, {
> + /* end of the table. */
> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
> + },
> +};
Such information should be set in platform code, because it is specific to your
controller and most likely to a particular board design.
> +
> +/* macro to get the id bytes */
> +#define ID_GET_MFR_CODE(id) ((id)[0])
> +
> +void nand_device_print_info(struct nand_device_info *info)
> +{
> + unsigned i;
> + const char *mfr_name;
> + const char *cell_technology_name;
> + uint64_t chip_size;
> + const char *chip_size_units;
> + unsigned page_data_size_in_bytes;
> + unsigned page_oob_size_in_bytes;
> + struct nand_attr *attr = &info->attr;
> + struct nand_timing *timing = &info->timing;
> +
> + /* Prepare the manufacturer name. */
> + mfr_name = "Unknown";
> + for (i = 0; nand_manuf_ids[i].id; i++) {
> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
> + mfr_name = nand_manuf_ids[i].name;
> + break;
> + }
> + }
> +
> + /* Prepare the name of the cell technology. */
> + switch (attr->cell_technology) {
> + case SLC:
> + cell_technology_name = "SLC";
> + break;
> + case MLC:
> + cell_technology_name = "MLC";
> + break;
> + default:
> + cell_technology_name = "Unknown";
> + break;
> + }
> +
> + /* Prepare the chip size. */
> + if ((attr->chip_size_in_bytes >= SZ_1G) &&
> + !(attr->chip_size_in_bytes % SZ_1G)) {
> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1G);
> + chip_size_units = "GiB";
> + } else if ((attr->chip_size_in_bytes >= SZ_1M) &&
> + !(attr->chip_size_in_bytes % SZ_1M)) {
> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1M);
> + chip_size_units = "MiB";
> + } else {
> + chip_size = attr->chip_size_in_bytes;
> + chip_size_units = "B";
> + }
> +
> + /* Prepare the page geometry. */
> + page_data_size_in_bytes = (1<<(fls(attr->page_total_size_in_bytes)-1));
> + page_oob_size_in_bytes = attr->page_total_size_in_bytes -
> + page_data_size_in_bytes;
> +
> + /* Print the infomation. */
> + printk(KERN_INFO "--------------------------------------\n");
> + printk(KERN_INFO " NAND device infomation (RAW)\n");
> + printk(KERN_INFO "--------------------------------------\n");
> + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
> + info->id[0]);
> + printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
> + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
> + printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
> + chip_size_units);
> + printk(KERN_INFO "Pages per Block : %u\n", attr->block_size_in_pages);
> + printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes,
> + page_oob_size_in_bytes);
> + printk(KERN_INFO "ECC Strength : %u bits\n",
> + attr->ecc_strength_in_bits);
> + printk(KERN_INFO "ECC Size : %u B\n", attr->ecc_size_in_bytes);
> + printk(KERN_INFO "Data Setup Time : %u ns\n",
> + timing->data_setup_in_ns);
> + printk(KERN_INFO "Data Hold Time : %u ns\n",
> + timing->data_hold_in_ns);
> + printk(KERN_INFO "Address Setup Time: %u ns\n",
> + timing->address_setup_in_ns);
> + printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
> + timing->gpmi_sample_delay_in_ns);
> + printk(KERN_INFO "tREA : %d ns\n",
> + (timing->tREA_in_ns >= 0 ?
> + timing->tREA_in_ns : -1));
> + printk(KERN_INFO "tRLOH : %d ns\n",
> + (timing->tRLOH_in_ns >= 0 ?
> + timing->tRLOH_in_ns : -1));
> + printk(KERN_INFO "tRHOH : %d ns\n",
> + (timing->tRHOH_in_ns >= 0 ?
> + timing->tRHOH_in_ns : -1));
> + printk(KERN_INFO "Description : %s\n", info->desc);
> +}
What is the purpose of printing all these informations? If it is for debugging
purposes, use dev_dbg().
> +
> +static struct nand_device_info * __init
> +search_table(struct nand_device_info *table, const uint8_t id[])
> +{
> + struct nand_device_info *info = table;
> +
> + while (ID_GET_MFR_CODE(info->id)) {
> + int i;
> +
> + /* match all the ids. Is it too strict? */
> + for (i = 0; i < ID_BYTES; i++)
> + if (info->id[i] != id[i])
> + break;
> +
> + /* found it */
> + if (i == ID_BYTES) {
> + nand_device_print_info(info);
> + return info;
> + }
> +
> + info++;
> + }
> + return NULL;
> +}
> +
> +struct nand_device_mfr_info {
> + uint8_t id;
> + struct nand_device_info *table;
> +};
> +
> +static struct nand_device_mfr_info nand_device_mfr_directory[] __initdata
> = { + { NAND_MFR_SAMSUNG, samsung_nand },
> + { 0, NULL },
> +};
> +
> +struct nand_device_info * __init nand_device_get_info(const uint8_t id[])
> +{
> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
> + unsigned i;
> +
> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
> + if (nand_device_mfr_directory[i].id == mfr_id) {
> + struct nand_device_info *table;
> +
> + table = nand_device_mfr_directory[i].table;
> + return search_table(table, id);
> + }
> + }
> + return NULL;
> +}
> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h new file mode 100644
> index 0000000..e606705
> --- /dev/null
> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> @@ -0,0 +1,145 @@
> +/*
> + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
> +#define __DRIVERS_NAND_DEVICE_INFO_H
> +
> +enum nand_device_cell_technology {
> + SLC = 0,
> + MLC = 1,
> +};
> +
> +/**
> + *
> + *
> + * @cell_technology: The storage cell technology.
> + * @chip_size_in_bytes: The total size of the storage behind a
> single + * chip select, in bytes. Notice that
> this is *not* + * necessarily the total size
> of the storage in a + * *package*, which may
> contain several chips. + * @block_size_in_pages: The number of pages
> in a block.
> + * @page_total_size_in_bytes: The total size of a page, in bytes,
> including + * both the data and the OOB.
> + * @ecc_strength_in_bits: The strength of the ECC called for by the
> + * manufacturer, in number of correctable
> bits. + * @ecc_size_in_bytes: The size of the data block over
> which the + * manufacturer calls for the given
> ECC algorithm + * and strength.
> + * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE nand
> ? + */
> +struct nand_attr {
> + /* Technology */
> + enum nand_device_cell_technology cell_technology;
> +
> + /* Geometry */
> + uint64_t chip_size_in_bytes;
> + uint32_t block_size_in_pages;
> + uint32_t page_total_size_in_bytes;
> +
> + /* ECC */
> + uint16_t ecc_size_in_bytes;
> + uint16_t ecc_strength_in_bits;
> +
> + /* Does the nand support DDR? (ONFI or TOGGLE) */
> + bool is_ddr_ok;
> +};
The generic NAND code already supports reading a NAND chip ONFI page, and will
return the supported ONFI page, you can get all of these parameters from it,
no need to have this duplicated in your driver.
> +
> +/**
> + * This structure contains the fundamental timing attributes for NAND.
> + *
> + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually
> the + * maximum of tDS and tWP. A negative
> value + * indicates this characteristic isn't
> known. + * @data_hold_in_ns: The data hold time, in nanoseconds.
> Usually the + * maximum of tDH, tWH and tREH. A
> negative value + * indicates this
> characteristic isn't known. + * @address_setup_in_ns: The address
> setup time, in nanoseconds. Usually + * the
> maximum of tCLS, tCS and tALS. A negative + *
> value indicates this characteristic isn't known. + *
> @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative
> value + * indicates this characteristic isn't
> known. + * @tREA_in_ns: tREA, in nanoseconds, from the data
> sheet. A + * negative value indicates this
> characteristic isn't + * known.
> + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet.
> A + * negative value indicates this
> characteristic isn't + * known.
> + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet.
> A + * negative value indicates this
> characteristic isn't + * known.
> + */
> +struct nand_timing {
> + int8_t data_setup_in_ns;
> + int8_t data_hold_in_ns;
> + int8_t address_setup_in_ns;
> + int8_t gpmi_sample_delay_in_ns;
> + int8_t tREA_in_ns;
> + int8_t tRLOH_in_ns;
> + int8_t tRHOH_in_ns;
> +};
> +
> +#define ID_BYTES (8)
> +/*
> + * struct nand_device_info - Information about a single NAND Flash device.
> + *
> + * This structure contains all the *essential* information about a NAND
> Flash + * device, derived from the device's data sheet.
> + */
> +struct nand_device_info {
> + /* id */
> + uint8_t id[ID_BYTES];
> +
> + /* Description */
> + const char *desc;
> +
> + /* attribute*/
> + struct nand_attr attr;
> +
> + /* timing */
> + struct nand_timing timing;
> +};
> +
> +/* macro for the NAND attribute */
> +#define ATTR(_a, _b, _c, _d, _e, _f) \
> + { \
> + .cell_technology = (_a), \
> + .chip_size_in_bytes = (_b), \
> + .block_size_in_pages = (_c), \
> + .page_total_size_in_bytes = (_d), \
> + .ecc_strength_in_bits = (_e), \
> + .ecc_size_in_bytes = (_f), \
> + }
> +
> +/* macro for the NAND timing */
> +#define TIMING(_a, _b, _c, _d, _e, _f, _h) \
> + { \
> + .data_setup_in_ns = (_a), \
> + .data_hold_in_ns = (_b), \
> + .address_setup_in_ns = (_c), \
> + .gpmi_sample_delay_in_ns = (_d), \
> + .tREA_in_ns = (_e), \
> + .tRLOH_in_ns = (_f), \
> + .tRHOH_in_ns = (_h), \
> + }
> +
> +struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
> +void nand_device_print_info(struct nand_device_info *info);
> +
> +/*
> + * Check the NAND whether it supports the DDR mode.
> + * Only the ONFI nand and TOGGLE nand support the DDR now.
> + */
> +static inline bool is_ddr_nand(struct nand_device_info *info)
> +{
> + return info->attr.is_ddr_ok;
> +}
> +#endif
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
@ 2011-03-23 15:29 ` Florian Fainelli
0 siblings, 0 replies; 49+ messages in thread
From: Florian Fainelli @ 2011-03-23 15:29 UTC (permalink / raw)
To: linux-arm-kernel
Hello Huang,
On Wednesday 16 March 2011 02:55:17 Huang Shijie wrote:
> This is a database for the NANDs which is now supported by imx23 and imx28.
>
> Signed-off-by: Huang Shijie <b32955@freescale.com>
> ---
> drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181
> ++++++++++++++++++++++++++ drivers/mtd/nand/gpmi-nfc/nand_device_info.h |
> 145 +++++++++++++++++++++ 2 files changed, 326 insertions(+), 0
> deletions(-)
> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>
> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c new file mode 100644
> index 0000000..aa0813a
> --- /dev/null
> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> @@ -0,0 +1,181 @@
> +/*
> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <asm/sizes.h>
> +#include <linux/mtd/nand.h>
> +
> +#include "nand_device_info.h"
> +
> +static struct nand_device_info samsung_nand[] __initdata = {
> + {
> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
> + .desc = "K9G8G08U0M, K9HAG08U1M",
> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
> + }, {
> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
> + .desc = "K9LBG08U0D",
> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
> + }, {
> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
> + .desc = "K9GAG08U0M",
> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
> + }, {
> + /* end of the table. */
> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
> + },
> +};
Such information should be set in platform code, because it is specific to your
controller and most likely to a particular board design.
> +
> +/* macro to get the id bytes */
> +#define ID_GET_MFR_CODE(id) ((id)[0])
> +
> +void nand_device_print_info(struct nand_device_info *info)
> +{
> + unsigned i;
> + const char *mfr_name;
> + const char *cell_technology_name;
> + uint64_t chip_size;
> + const char *chip_size_units;
> + unsigned page_data_size_in_bytes;
> + unsigned page_oob_size_in_bytes;
> + struct nand_attr *attr = &info->attr;
> + struct nand_timing *timing = &info->timing;
> +
> + /* Prepare the manufacturer name. */
> + mfr_name = "Unknown";
> + for (i = 0; nand_manuf_ids[i].id; i++) {
> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
> + mfr_name = nand_manuf_ids[i].name;
> + break;
> + }
> + }
> +
> + /* Prepare the name of the cell technology. */
> + switch (attr->cell_technology) {
> + case SLC:
> + cell_technology_name = "SLC";
> + break;
> + case MLC:
> + cell_technology_name = "MLC";
> + break;
> + default:
> + cell_technology_name = "Unknown";
> + break;
> + }
> +
> + /* Prepare the chip size. */
> + if ((attr->chip_size_in_bytes >= SZ_1G) &&
> + !(attr->chip_size_in_bytes % SZ_1G)) {
> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1G);
> + chip_size_units = "GiB";
> + } else if ((attr->chip_size_in_bytes >= SZ_1M) &&
> + !(attr->chip_size_in_bytes % SZ_1M)) {
> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1M);
> + chip_size_units = "MiB";
> + } else {
> + chip_size = attr->chip_size_in_bytes;
> + chip_size_units = "B";
> + }
> +
> + /* Prepare the page geometry. */
> + page_data_size_in_bytes = (1<<(fls(attr->page_total_size_in_bytes)-1));
> + page_oob_size_in_bytes = attr->page_total_size_in_bytes -
> + page_data_size_in_bytes;
> +
> + /* Print the infomation. */
> + printk(KERN_INFO "--------------------------------------\n");
> + printk(KERN_INFO " NAND device infomation (RAW)\n");
> + printk(KERN_INFO "--------------------------------------\n");
> + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
> + info->id[0]);
> + printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
> + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
> + printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
> + chip_size_units);
> + printk(KERN_INFO "Pages per Block : %u\n", attr->block_size_in_pages);
> + printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes,
> + page_oob_size_in_bytes);
> + printk(KERN_INFO "ECC Strength : %u bits\n",
> + attr->ecc_strength_in_bits);
> + printk(KERN_INFO "ECC Size : %u B\n", attr->ecc_size_in_bytes);
> + printk(KERN_INFO "Data Setup Time : %u ns\n",
> + timing->data_setup_in_ns);
> + printk(KERN_INFO "Data Hold Time : %u ns\n",
> + timing->data_hold_in_ns);
> + printk(KERN_INFO "Address Setup Time: %u ns\n",
> + timing->address_setup_in_ns);
> + printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
> + timing->gpmi_sample_delay_in_ns);
> + printk(KERN_INFO "tREA : %d ns\n",
> + (timing->tREA_in_ns >= 0 ?
> + timing->tREA_in_ns : -1));
> + printk(KERN_INFO "tRLOH : %d ns\n",
> + (timing->tRLOH_in_ns >= 0 ?
> + timing->tRLOH_in_ns : -1));
> + printk(KERN_INFO "tRHOH : %d ns\n",
> + (timing->tRHOH_in_ns >= 0 ?
> + timing->tRHOH_in_ns : -1));
> + printk(KERN_INFO "Description : %s\n", info->desc);
> +}
What is the purpose of printing all these informations? If it is for debugging
purposes, use dev_dbg().
> +
> +static struct nand_device_info * __init
> +search_table(struct nand_device_info *table, const uint8_t id[])
> +{
> + struct nand_device_info *info = table;
> +
> + while (ID_GET_MFR_CODE(info->id)) {
> + int i;
> +
> + /* match all the ids. Is it too strict? */
> + for (i = 0; i < ID_BYTES; i++)
> + if (info->id[i] != id[i])
> + break;
> +
> + /* found it */
> + if (i == ID_BYTES) {
> + nand_device_print_info(info);
> + return info;
> + }
> +
> + info++;
> + }
> + return NULL;
> +}
> +
> +struct nand_device_mfr_info {
> + uint8_t id;
> + struct nand_device_info *table;
> +};
> +
> +static struct nand_device_mfr_info nand_device_mfr_directory[] __initdata
> = { + { NAND_MFR_SAMSUNG, samsung_nand },
> + { 0, NULL },
> +};
> +
> +struct nand_device_info * __init nand_device_get_info(const uint8_t id[])
> +{
> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
> + unsigned i;
> +
> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
> + if (nand_device_mfr_directory[i].id == mfr_id) {
> + struct nand_device_info *table;
> +
> + table = nand_device_mfr_directory[i].table;
> + return search_table(table, id);
> + }
> + }
> + return NULL;
> +}
> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h new file mode 100644
> index 0000000..e606705
> --- /dev/null
> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> @@ -0,0 +1,145 @@
> +/*
> + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
> +#define __DRIVERS_NAND_DEVICE_INFO_H
> +
> +enum nand_device_cell_technology {
> + SLC = 0,
> + MLC = 1,
> +};
> +
> +/**
> + *
> + *
> + * @cell_technology: The storage cell technology.
> + * @chip_size_in_bytes: The total size of the storage behind a
> single + * chip select, in bytes. Notice that
> this is *not* + * necessarily the total size
> of the storage in a + * *package*, which may
> contain several chips. + * @block_size_in_pages: The number of pages
> in a block.
> + * @page_total_size_in_bytes: The total size of a page, in bytes,
> including + * both the data and the OOB.
> + * @ecc_strength_in_bits: The strength of the ECC called for by the
> + * manufacturer, in number of correctable
> bits. + * @ecc_size_in_bytes: The size of the data block over
> which the + * manufacturer calls for the given
> ECC algorithm + * and strength.
> + * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE nand
> ? + */
> +struct nand_attr {
> + /* Technology */
> + enum nand_device_cell_technology cell_technology;
> +
> + /* Geometry */
> + uint64_t chip_size_in_bytes;
> + uint32_t block_size_in_pages;
> + uint32_t page_total_size_in_bytes;
> +
> + /* ECC */
> + uint16_t ecc_size_in_bytes;
> + uint16_t ecc_strength_in_bits;
> +
> + /* Does the nand support DDR? (ONFI or TOGGLE) */
> + bool is_ddr_ok;
> +};
The generic NAND code already supports reading a NAND chip ONFI page, and will
return the supported ONFI page, you can get all of these parameters from it,
no need to have this duplicated in your driver.
> +
> +/**
> + * This structure contains the fundamental timing attributes for NAND.
> + *
> + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually
> the + * maximum of tDS and tWP. A negative
> value + * indicates this characteristic isn't
> known. + * @data_hold_in_ns: The data hold time, in nanoseconds.
> Usually the + * maximum of tDH, tWH and tREH. A
> negative value + * indicates this
> characteristic isn't known. + * @address_setup_in_ns: The address
> setup time, in nanoseconds. Usually + * the
> maximum of tCLS, tCS and tALS. A negative + *
> value indicates this characteristic isn't known. + *
> @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative
> value + * indicates this characteristic isn't
> known. + * @tREA_in_ns: tREA, in nanoseconds, from the data
> sheet. A + * negative value indicates this
> characteristic isn't + * known.
> + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet.
> A + * negative value indicates this
> characteristic isn't + * known.
> + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet.
> A + * negative value indicates this
> characteristic isn't + * known.
> + */
> +struct nand_timing {
> + int8_t data_setup_in_ns;
> + int8_t data_hold_in_ns;
> + int8_t address_setup_in_ns;
> + int8_t gpmi_sample_delay_in_ns;
> + int8_t tREA_in_ns;
> + int8_t tRLOH_in_ns;
> + int8_t tRHOH_in_ns;
> +};
> +
> +#define ID_BYTES (8)
> +/*
> + * struct nand_device_info - Information about a single NAND Flash device.
> + *
> + * This structure contains all the *essential* information about a NAND
> Flash + * device, derived from the device's data sheet.
> + */
> +struct nand_device_info {
> + /* id */
> + uint8_t id[ID_BYTES];
> +
> + /* Description */
> + const char *desc;
> +
> + /* attribute*/
> + struct nand_attr attr;
> +
> + /* timing */
> + struct nand_timing timing;
> +};
> +
> +/* macro for the NAND attribute */
> +#define ATTR(_a, _b, _c, _d, _e, _f) \
> + { \
> + .cell_technology = (_a), \
> + .chip_size_in_bytes = (_b), \
> + .block_size_in_pages = (_c), \
> + .page_total_size_in_bytes = (_d), \
> + .ecc_strength_in_bits = (_e), \
> + .ecc_size_in_bytes = (_f), \
> + }
> +
> +/* macro for the NAND timing */
> +#define TIMING(_a, _b, _c, _d, _e, _f, _h) \
> + { \
> + .data_setup_in_ns = (_a), \
> + .data_hold_in_ns = (_b), \
> + .address_setup_in_ns = (_c), \
> + .gpmi_sample_delay_in_ns = (_d), \
> + .tREA_in_ns = (_e), \
> + .tRLOH_in_ns = (_f), \
> + .tRHOH_in_ns = (_h), \
> + }
> +
> +struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
> +void nand_device_print_info(struct nand_device_info *info);
> +
> +/*
> + * Check the NAND whether it supports the DDR mode.
> + * Only the ONFI nand and TOGGLE nand support the DDR now.
> + */
> +static inline bool is_ddr_nand(struct nand_device_info *info)
> +{
> + return info->attr.is_ddr_ok;
> +}
> +#endif
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 3/7] add the database for the NANDs
2011-03-23 15:29 ` Florian Fainelli
@ 2011-03-24 2:27 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-24 2:27 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
Hi Florian:
thanks a lot for your review.
> Hello Huang,
>
> On Wednesday 16 March 2011 02:55:17 Huang Shijie wrote:
>> This is a database for the NANDs which is now supported by imx23 and imx28.
>>
>> Signed-off-by: Huang Shijie<b32955@freescale.com>
>> ---
>> drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181
>> ++++++++++++++++++++++++++ drivers/mtd/nand/gpmi-nfc/nand_device_info.h |
>> 145 +++++++++++++++++++++ 2 files changed, 326 insertions(+), 0
>> deletions(-)
>> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
>> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>>
>> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
>> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c new file mode 100644
>> index 0000000..aa0813a
>> --- /dev/null
>> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
>> @@ -0,0 +1,181 @@
>> +/*
>> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
>> + */
>> +
>> +/*
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +#include<asm/sizes.h>
>> +#include<linux/mtd/nand.h>
>> +
>> +#include "nand_device_info.h"
>> +
>> +static struct nand_device_info samsung_nand[] __initdata = {
>> + {
>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
>> + .desc = "K9G8G08U0M, K9HAG08U1M",
>> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
>> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
>> + }, {
>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
>> + .desc = "K9LBG08U0D",
>> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
>> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
>> + }, {
>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
>> + .desc = "K9GAG08U0M",
>> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
>> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
>> + }, {
>> + /* end of the table. */
>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
>> + },
>> +};
> Such information should be set in platform code, because it is specific to your
> controller and most likely to a particular board design.
>
I prefer to place it here.
If I move the code to arch/arm/mach-mxs, it will make the arch/ much
bigger.
I have nearly 50 different nands information by hand, I will add it
gradually in later patches.
>> +
>> +/* macro to get the id bytes */
>> +#define ID_GET_MFR_CODE(id) ((id)[0])
>> +
>> +void nand_device_print_info(struct nand_device_info *info)
>> +{
>> + unsigned i;
>> + const char *mfr_name;
>> + const char *cell_technology_name;
>> + uint64_t chip_size;
>> + const char *chip_size_units;
>> + unsigned page_data_size_in_bytes;
>> + unsigned page_oob_size_in_bytes;
>> + struct nand_attr *attr =&info->attr;
>> + struct nand_timing *timing =&info->timing;
>> +
>> + /* Prepare the manufacturer name. */
>> + mfr_name = "Unknown";
>> + for (i = 0; nand_manuf_ids[i].id; i++) {
>> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
>> + mfr_name = nand_manuf_ids[i].name;
>> + break;
>> + }
>> + }
>> +
>> + /* Prepare the name of the cell technology. */
>> + switch (attr->cell_technology) {
>> + case SLC:
>> + cell_technology_name = "SLC";
>> + break;
>> + case MLC:
>> + cell_technology_name = "MLC";
>> + break;
>> + default:
>> + cell_technology_name = "Unknown";
>> + break;
>> + }
>> +
>> + /* Prepare the chip size. */
>> + if ((attr->chip_size_in_bytes>= SZ_1G)&&
>> + !(attr->chip_size_in_bytes % SZ_1G)) {
>> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1G);
>> + chip_size_units = "GiB";
>> + } else if ((attr->chip_size_in_bytes>= SZ_1M)&&
>> + !(attr->chip_size_in_bytes % SZ_1M)) {
>> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1M);
>> + chip_size_units = "MiB";
>> + } else {
>> + chip_size = attr->chip_size_in_bytes;
>> + chip_size_units = "B";
>> + }
>> +
>> + /* Prepare the page geometry. */
>> + page_data_size_in_bytes = (1<<(fls(attr->page_total_size_in_bytes)-1));
>> + page_oob_size_in_bytes = attr->page_total_size_in_bytes -
>> + page_data_size_in_bytes;
>> +
>> + /* Print the infomation. */
>> + printk(KERN_INFO "--------------------------------------\n");
>> + printk(KERN_INFO " NAND device infomation (RAW)\n");
>> + printk(KERN_INFO "--------------------------------------\n");
>> + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
>> + info->id[0]);
>> + printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
>> + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
>> + printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
>> + chip_size_units);
>> + printk(KERN_INFO "Pages per Block : %u\n", attr->block_size_in_pages);
>> + printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes,
>> + page_oob_size_in_bytes);
>> + printk(KERN_INFO "ECC Strength : %u bits\n",
>> + attr->ecc_strength_in_bits);
>> + printk(KERN_INFO "ECC Size : %u B\n", attr->ecc_size_in_bytes);
>> + printk(KERN_INFO "Data Setup Time : %u ns\n",
>> + timing->data_setup_in_ns);
>> + printk(KERN_INFO "Data Hold Time : %u ns\n",
>> + timing->data_hold_in_ns);
>> + printk(KERN_INFO "Address Setup Time: %u ns\n",
>> + timing->address_setup_in_ns);
>> + printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
>> + timing->gpmi_sample_delay_in_ns);
>> + printk(KERN_INFO "tREA : %d ns\n",
>> + (timing->tREA_in_ns>= 0 ?
>> + timing->tREA_in_ns : -1));
>> + printk(KERN_INFO "tRLOH : %d ns\n",
>> + (timing->tRLOH_in_ns>= 0 ?
>> + timing->tRLOH_in_ns : -1));
>> + printk(KERN_INFO "tRHOH : %d ns\n",
>> + (timing->tRHOH_in_ns>= 0 ?
>> + timing->tRHOH_in_ns : -1));
>> + printk(KERN_INFO "Description : %s\n", info->desc);
>> +}
> What is the purpose of printing all these informations? If it is for debugging
> purposes, use dev_dbg().
>
I do not treat this as debugging information.
I print it out for showing the detail of a NAND.
>> +
>> +static struct nand_device_info * __init
>> +search_table(struct nand_device_info *table, const uint8_t id[])
>> +{
>> + struct nand_device_info *info = table;
>> +
>> + while (ID_GET_MFR_CODE(info->id)) {
>> + int i;
>> +
>> + /* match all the ids. Is it too strict? */
>> + for (i = 0; i< ID_BYTES; i++)
>> + if (info->id[i] != id[i])
>> + break;
>> +
>> + /* found it */
>> + if (i == ID_BYTES) {
>> + nand_device_print_info(info);
>> + return info;
>> + }
>> +
>> + info++;
>> + }
>> + return NULL;
>> +}
>> +
>> +struct nand_device_mfr_info {
>> + uint8_t id;
>> + struct nand_device_info *table;
>> +};
>> +
>> +static struct nand_device_mfr_info nand_device_mfr_directory[] __initdata
>> = { + { NAND_MFR_SAMSUNG, samsung_nand },
>> + { 0, NULL },
>> +};
>> +
>> +struct nand_device_info * __init nand_device_get_info(const uint8_t id[])
>> +{
>> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
>> + unsigned i;
>> +
>> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
>> + if (nand_device_mfr_directory[i].id == mfr_id) {
>> + struct nand_device_info *table;
>> +
>> + table = nand_device_mfr_directory[i].table;
>> + return search_table(table, id);
>> + }
>> + }
>> + return NULL;
>> +}
>> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h new file mode 100644
>> index 0000000..e606705
>> --- /dev/null
>> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>> @@ -0,0 +1,145 @@
>> +/*
>> + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
>> + */
>> +
>> +/*
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
>> +#define __DRIVERS_NAND_DEVICE_INFO_H
>> +
>> +enum nand_device_cell_technology {
>> + SLC = 0,
>> + MLC = 1,
>> +};
>> +
>> +/**
>> + *
>> + *
>> + * @cell_technology: The storage cell technology.
>> + * @chip_size_in_bytes: The total size of the storage behind a
>> single + * chip select, in bytes. Notice that
>> this is *not* + * necessarily the total size
>> of the storage in a + * *package*, which may
>> contain several chips. + * @block_size_in_pages: The number of pages
>> in a block.
>> + * @page_total_size_in_bytes: The total size of a page, in bytes,
>> including + * both the data and the OOB.
>> + * @ecc_strength_in_bits: The strength of the ECC called for by the
>> + * manufacturer, in number of correctable
>> bits. + * @ecc_size_in_bytes: The size of the data block over
>> which the + * manufacturer calls for the given
>> ECC algorithm + * and strength.
>> + * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE nand
>> ? + */
>> +struct nand_attr {
>> + /* Technology */
>> + enum nand_device_cell_technology cell_technology;
>> +
>> + /* Geometry */
>> + uint64_t chip_size_in_bytes;
>> + uint32_t block_size_in_pages;
>> + uint32_t page_total_size_in_bytes;
>> +
>> + /* ECC */
>> + uint16_t ecc_size_in_bytes;
>> + uint16_t ecc_strength_in_bits;
>> +
>> + /* Does the nand support DDR? (ONFI or TOGGLE) */
>> + bool is_ddr_ok;
>> +};
> The generic NAND code already supports reading a NAND chip ONFI page, and will
> return the supported ONFI page, you can get all of these parameters from it,
> no need to have this duplicated in your driver.
>
Yes. But the generic code dose not support the TOGGLE nand now.
But I think you are right, maybe I should remove the code now.
>> +
>> +/**
>> + * This structure contains the fundamental timing attributes for NAND.
>> + *
>> + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually
>> the + * maximum of tDS and tWP. A negative
>> value + * indicates this characteristic isn't
>> known. + * @data_hold_in_ns: The data hold time, in nanoseconds.
>> Usually the + * maximum of tDH, tWH and tREH. A
>> negative value + * indicates this
>> characteristic isn't known. + * @address_setup_in_ns: The address
>> setup time, in nanoseconds. Usually + * the
>> maximum of tCLS, tCS and tALS. A negative + *
>> value indicates this characteristic isn't known. + *
>> @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative
>> value + * indicates this characteristic isn't
>> known. + * @tREA_in_ns: tREA, in nanoseconds, from the data
>> sheet. A + * negative value indicates this
>> characteristic isn't + * known.
>> + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet.
>> A + * negative value indicates this
>> characteristic isn't + * known.
>> + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet.
>> A + * negative value indicates this
>> characteristic isn't + * known.
>> + */
>> +struct nand_timing {
>> + int8_t data_setup_in_ns;
>> + int8_t data_hold_in_ns;
>> + int8_t address_setup_in_ns;
>> + int8_t gpmi_sample_delay_in_ns;
>> + int8_t tREA_in_ns;
>> + int8_t tRLOH_in_ns;
>> + int8_t tRHOH_in_ns;
>> +};
>> +
>> +#define ID_BYTES (8)
>> +/*
>> + * struct nand_device_info - Information about a single NAND Flash device.
>> + *
>> + * This structure contains all the *essential* information about a NAND
>> Flash + * device, derived from the device's data sheet.
>> + */
>> +struct nand_device_info {
>> + /* id */
>> + uint8_t id[ID_BYTES];
>> +
>> + /* Description */
>> + const char *desc;
>> +
>> + /* attribute*/
>> + struct nand_attr attr;
>> +
>> + /* timing */
>> + struct nand_timing timing;
>> +};
>> +
>> +/* macro for the NAND attribute */
>> +#define ATTR(_a, _b, _c, _d, _e, _f) \
>> + { \
>> + .cell_technology = (_a), \
>> + .chip_size_in_bytes = (_b), \
>> + .block_size_in_pages = (_c), \
>> + .page_total_size_in_bytes = (_d), \
>> + .ecc_strength_in_bits = (_e), \
>> + .ecc_size_in_bytes = (_f), \
>> + }
>> +
>> +/* macro for the NAND timing */
>> +#define TIMING(_a, _b, _c, _d, _e, _f, _h) \
>> + { \
>> + .data_setup_in_ns = (_a), \
>> + .data_hold_in_ns = (_b), \
>> + .address_setup_in_ns = (_c), \
>> + .gpmi_sample_delay_in_ns = (_d), \
>> + .tREA_in_ns = (_e), \
>> + .tRLOH_in_ns = (_f), \
>> + .tRHOH_in_ns = (_h), \
>> + }
>> +
>> +struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
>> +void nand_device_print_info(struct nand_device_info *info);
>> +
>> +/*
>> + * Check the NAND whether it supports the DDR mode.
>> + * Only the ONFI nand and TOGGLE nand support the DDR now.
>> + */
>> +static inline bool is_ddr_nand(struct nand_device_info *info)
>> +{
>> + return info->attr.is_ddr_ok;
>> +}
>> +#endif
Best Regards
Huang Shijie
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
@ 2011-03-24 2:27 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-24 2:27 UTC (permalink / raw)
To: linux-arm-kernel
Hi Florian:
thanks a lot for your review.
> Hello Huang,
>
> On Wednesday 16 March 2011 02:55:17 Huang Shijie wrote:
>> This is a database for the NANDs which is now supported by imx23 and imx28.
>>
>> Signed-off-by: Huang Shijie<b32955@freescale.com>
>> ---
>> drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181
>> ++++++++++++++++++++++++++ drivers/mtd/nand/gpmi-nfc/nand_device_info.h |
>> 145 +++++++++++++++++++++ 2 files changed, 326 insertions(+), 0
>> deletions(-)
>> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
>> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>>
>> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
>> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c new file mode 100644
>> index 0000000..aa0813a
>> --- /dev/null
>> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
>> @@ -0,0 +1,181 @@
>> +/*
>> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
>> + */
>> +
>> +/*
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +#include<asm/sizes.h>
>> +#include<linux/mtd/nand.h>
>> +
>> +#include "nand_device_info.h"
>> +
>> +static struct nand_device_info samsung_nand[] __initdata = {
>> + {
>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
>> + .desc = "K9G8G08U0M, K9HAG08U1M",
>> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
>> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
>> + }, {
>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
>> + .desc = "K9LBG08U0D",
>> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
>> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
>> + }, {
>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
>> + .desc = "K9GAG08U0M",
>> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
>> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
>> + }, {
>> + /* end of the table. */
>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
>> + },
>> +};
> Such information should be set in platform code, because it is specific to your
> controller and most likely to a particular board design.
>
I prefer to place it here.
If I move the code to arch/arm/mach-mxs, it will make the arch/ much
bigger.
I have nearly 50 different nands information by hand, I will add it
gradually in later patches.
>> +
>> +/* macro to get the id bytes */
>> +#define ID_GET_MFR_CODE(id) ((id)[0])
>> +
>> +void nand_device_print_info(struct nand_device_info *info)
>> +{
>> + unsigned i;
>> + const char *mfr_name;
>> + const char *cell_technology_name;
>> + uint64_t chip_size;
>> + const char *chip_size_units;
>> + unsigned page_data_size_in_bytes;
>> + unsigned page_oob_size_in_bytes;
>> + struct nand_attr *attr =&info->attr;
>> + struct nand_timing *timing =&info->timing;
>> +
>> + /* Prepare the manufacturer name. */
>> + mfr_name = "Unknown";
>> + for (i = 0; nand_manuf_ids[i].id; i++) {
>> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
>> + mfr_name = nand_manuf_ids[i].name;
>> + break;
>> + }
>> + }
>> +
>> + /* Prepare the name of the cell technology. */
>> + switch (attr->cell_technology) {
>> + case SLC:
>> + cell_technology_name = "SLC";
>> + break;
>> + case MLC:
>> + cell_technology_name = "MLC";
>> + break;
>> + default:
>> + cell_technology_name = "Unknown";
>> + break;
>> + }
>> +
>> + /* Prepare the chip size. */
>> + if ((attr->chip_size_in_bytes>= SZ_1G)&&
>> + !(attr->chip_size_in_bytes % SZ_1G)) {
>> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1G);
>> + chip_size_units = "GiB";
>> + } else if ((attr->chip_size_in_bytes>= SZ_1M)&&
>> + !(attr->chip_size_in_bytes % SZ_1M)) {
>> + chip_size = attr->chip_size_in_bytes / ((uint64_t) SZ_1M);
>> + chip_size_units = "MiB";
>> + } else {
>> + chip_size = attr->chip_size_in_bytes;
>> + chip_size_units = "B";
>> + }
>> +
>> + /* Prepare the page geometry. */
>> + page_data_size_in_bytes = (1<<(fls(attr->page_total_size_in_bytes)-1));
>> + page_oob_size_in_bytes = attr->page_total_size_in_bytes -
>> + page_data_size_in_bytes;
>> +
>> + /* Print the infomation. */
>> + printk(KERN_INFO "--------------------------------------\n");
>> + printk(KERN_INFO " NAND device infomation (RAW)\n");
>> + printk(KERN_INFO "--------------------------------------\n");
>> + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
>> + info->id[0]);
>> + printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
>> + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
>> + printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
>> + chip_size_units);
>> + printk(KERN_INFO "Pages per Block : %u\n", attr->block_size_in_pages);
>> + printk(KERN_INFO "Page Geometry : %u+%u\n", page_data_size_in_bytes,
>> + page_oob_size_in_bytes);
>> + printk(KERN_INFO "ECC Strength : %u bits\n",
>> + attr->ecc_strength_in_bits);
>> + printk(KERN_INFO "ECC Size : %u B\n", attr->ecc_size_in_bytes);
>> + printk(KERN_INFO "Data Setup Time : %u ns\n",
>> + timing->data_setup_in_ns);
>> + printk(KERN_INFO "Data Hold Time : %u ns\n",
>> + timing->data_hold_in_ns);
>> + printk(KERN_INFO "Address Setup Time: %u ns\n",
>> + timing->address_setup_in_ns);
>> + printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
>> + timing->gpmi_sample_delay_in_ns);
>> + printk(KERN_INFO "tREA : %d ns\n",
>> + (timing->tREA_in_ns>= 0 ?
>> + timing->tREA_in_ns : -1));
>> + printk(KERN_INFO "tRLOH : %d ns\n",
>> + (timing->tRLOH_in_ns>= 0 ?
>> + timing->tRLOH_in_ns : -1));
>> + printk(KERN_INFO "tRHOH : %d ns\n",
>> + (timing->tRHOH_in_ns>= 0 ?
>> + timing->tRHOH_in_ns : -1));
>> + printk(KERN_INFO "Description : %s\n", info->desc);
>> +}
> What is the purpose of printing all these informations? If it is for debugging
> purposes, use dev_dbg().
>
I do not treat this as debugging information.
I print it out for showing the detail of a NAND.
>> +
>> +static struct nand_device_info * __init
>> +search_table(struct nand_device_info *table, const uint8_t id[])
>> +{
>> + struct nand_device_info *info = table;
>> +
>> + while (ID_GET_MFR_CODE(info->id)) {
>> + int i;
>> +
>> + /* match all the ids. Is it too strict? */
>> + for (i = 0; i< ID_BYTES; i++)
>> + if (info->id[i] != id[i])
>> + break;
>> +
>> + /* found it */
>> + if (i == ID_BYTES) {
>> + nand_device_print_info(info);
>> + return info;
>> + }
>> +
>> + info++;
>> + }
>> + return NULL;
>> +}
>> +
>> +struct nand_device_mfr_info {
>> + uint8_t id;
>> + struct nand_device_info *table;
>> +};
>> +
>> +static struct nand_device_mfr_info nand_device_mfr_directory[] __initdata
>> = { + { NAND_MFR_SAMSUNG, samsung_nand },
>> + { 0, NULL },
>> +};
>> +
>> +struct nand_device_info * __init nand_device_get_info(const uint8_t id[])
>> +{
>> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
>> + unsigned i;
>> +
>> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
>> + if (nand_device_mfr_directory[i].id == mfr_id) {
>> + struct nand_device_info *table;
>> +
>> + table = nand_device_mfr_directory[i].table;
>> + return search_table(table, id);
>> + }
>> + }
>> + return NULL;
>> +}
>> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h new file mode 100644
>> index 0000000..e606705
>> --- /dev/null
>> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>> @@ -0,0 +1,145 @@
>> +/*
>> + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
>> + */
>> +
>> +/*
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
>> +#define __DRIVERS_NAND_DEVICE_INFO_H
>> +
>> +enum nand_device_cell_technology {
>> + SLC = 0,
>> + MLC = 1,
>> +};
>> +
>> +/**
>> + *
>> + *
>> + * @cell_technology: The storage cell technology.
>> + * @chip_size_in_bytes: The total size of the storage behind a
>> single + * chip select, in bytes. Notice that
>> this is *not* + * necessarily the total size
>> of the storage in a + * *package*, which may
>> contain several chips. + * @block_size_in_pages: The number of pages
>> in a block.
>> + * @page_total_size_in_bytes: The total size of a page, in bytes,
>> including + * both the data and the OOB.
>> + * @ecc_strength_in_bits: The strength of the ECC called for by the
>> + * manufacturer, in number of correctable
>> bits. + * @ecc_size_in_bytes: The size of the data block over
>> which the + * manufacturer calls for the given
>> ECC algorithm + * and strength.
>> + * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE nand
>> ? + */
>> +struct nand_attr {
>> + /* Technology */
>> + enum nand_device_cell_technology cell_technology;
>> +
>> + /* Geometry */
>> + uint64_t chip_size_in_bytes;
>> + uint32_t block_size_in_pages;
>> + uint32_t page_total_size_in_bytes;
>> +
>> + /* ECC */
>> + uint16_t ecc_size_in_bytes;
>> + uint16_t ecc_strength_in_bits;
>> +
>> + /* Does the nand support DDR? (ONFI or TOGGLE) */
>> + bool is_ddr_ok;
>> +};
> The generic NAND code already supports reading a NAND chip ONFI page, and will
> return the supported ONFI page, you can get all of these parameters from it,
> no need to have this duplicated in your driver.
>
Yes. But the generic code dose not support the TOGGLE nand now.
But I think you are right, maybe I should remove the code now.
>> +
>> +/**
>> + * This structure contains the fundamental timing attributes for NAND.
>> + *
>> + * @data_setup_in_ns: The data setup time, in nanoseconds. Usually
>> the + * maximum of tDS and tWP. A negative
>> value + * indicates this characteristic isn't
>> known. + * @data_hold_in_ns: The data hold time, in nanoseconds.
>> Usually the + * maximum of tDH, tWH and tREH. A
>> negative value + * indicates this
>> characteristic isn't known. + * @address_setup_in_ns: The address
>> setup time, in nanoseconds. Usually + * the
>> maximum of tCLS, tCS and tALS. A negative + *
>> value indicates this characteristic isn't known. + *
>> @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative
>> value + * indicates this characteristic isn't
>> known. + * @tREA_in_ns: tREA, in nanoseconds, from the data
>> sheet. A + * negative value indicates this
>> characteristic isn't + * known.
>> + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data sheet.
>> A + * negative value indicates this
>> characteristic isn't + * known.
>> + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data sheet.
>> A + * negative value indicates this
>> characteristic isn't + * known.
>> + */
>> +struct nand_timing {
>> + int8_t data_setup_in_ns;
>> + int8_t data_hold_in_ns;
>> + int8_t address_setup_in_ns;
>> + int8_t gpmi_sample_delay_in_ns;
>> + int8_t tREA_in_ns;
>> + int8_t tRLOH_in_ns;
>> + int8_t tRHOH_in_ns;
>> +};
>> +
>> +#define ID_BYTES (8)
>> +/*
>> + * struct nand_device_info - Information about a single NAND Flash device.
>> + *
>> + * This structure contains all the *essential* information about a NAND
>> Flash + * device, derived from the device's data sheet.
>> + */
>> +struct nand_device_info {
>> + /* id */
>> + uint8_t id[ID_BYTES];
>> +
>> + /* Description */
>> + const char *desc;
>> +
>> + /* attribute*/
>> + struct nand_attr attr;
>> +
>> + /* timing */
>> + struct nand_timing timing;
>> +};
>> +
>> +/* macro for the NAND attribute */
>> +#define ATTR(_a, _b, _c, _d, _e, _f) \
>> + { \
>> + .cell_technology = (_a), \
>> + .chip_size_in_bytes = (_b), \
>> + .block_size_in_pages = (_c), \
>> + .page_total_size_in_bytes = (_d), \
>> + .ecc_strength_in_bits = (_e), \
>> + .ecc_size_in_bytes = (_f), \
>> + }
>> +
>> +/* macro for the NAND timing */
>> +#define TIMING(_a, _b, _c, _d, _e, _f, _h) \
>> + { \
>> + .data_setup_in_ns = (_a), \
>> + .data_hold_in_ns = (_b), \
>> + .address_setup_in_ns = (_c), \
>> + .gpmi_sample_delay_in_ns = (_d), \
>> + .tREA_in_ns = (_e), \
>> + .tRLOH_in_ns = (_f), \
>> + .tRHOH_in_ns = (_h), \
>> + }
>> +
>> +struct nand_device_info *nand_device_get_info(const uint8_t id_bytes[]);
>> +void nand_device_print_info(struct nand_device_info *info);
>> +
>> +/*
>> + * Check the NAND whether it supports the DDR mode.
>> + * Only the ONFI nand and TOGGLE nand support the DDR now.
>> + */
>> +static inline bool is_ddr_nand(struct nand_device_info *info)
>> +{
>> + return info->attr.is_ddr_ok;
>> +}
>> +#endif
Best Regards
Huang Shijie
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 3/7] add the database for the NANDs
2011-03-24 2:27 ` Huang Shijie
@ 2011-03-24 13:50 ` Florian Fainelli
-1 siblings, 0 replies; 49+ messages in thread
From: Florian Fainelli @ 2011-03-24 13:50 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: David.Woodhouse, Huang Shijie, linux-mtd, dwmw2, linux
Hello Huang,
On Thursday 24 March 2011 03:27:40 Huang Shijie wrote:
> Hi Florian:
> thanks a lot for your review.
>
> > Hello Huang,
> >
> > On Wednesday 16 March 2011 02:55:17 Huang Shijie wrote:
> >> This is a database for the NANDs which is now supported by imx23 and
> >> imx28.
> >>
> >> Signed-off-by: Huang Shijie<b32955@freescale.com>
> >> ---
> >>
> >> drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181
> >>
> >> ++++++++++++++++++++++++++ drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> >> | 145 +++++++++++++++++++++ 2 files changed, 326 insertions(+), 0
> >> deletions(-)
> >>
> >> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> >> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> >>
> >> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> >> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c new file mode 100644
> >> index 0000000..aa0813a
> >> --- /dev/null
> >> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> >> @@ -0,0 +1,181 @@
> >> +/*
> >> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights
> >> Reserved. + */
> >> +
> >> +/*
> >> + * The code contained herein is licensed under the GNU General Public
> >> + * License. You may obtain a copy of the GNU General Public License
> >> + * Version 2 or later at the following locations:
> >> + *
> >> + * http://www.opensource.org/licenses/gpl-license.html
> >> + * http://www.gnu.org/copyleft/gpl.html
> >> + */
> >> +
> >> +#include<asm/sizes.h>
> >> +#include<linux/mtd/nand.h>
> >> +
> >> +#include "nand_device_info.h"
> >> +
> >> +static struct nand_device_info samsung_nand[] __initdata = {
> >> + {
> >> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
> >> + .desc = "K9G8G08U0M, K9HAG08U1M",
> >> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
> >> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
> >> + }, {
> >> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
> >> + .desc = "K9LBG08U0D",
> >> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
> >> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
> >> + }, {
> >> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
> >> + .desc = "K9GAG08U0M",
> >> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
> >> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
> >> + }, {
> >> + /* end of the table. */
> >> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
> >> + },
> >> +};
> >
> > Such information should be set in platform code, because it is specific
> > to your controller and most likely to a particular board design.
>
> I prefer to place it here.
>
> If I move the code to arch/arm/mach-mxs, it will make the arch/ much
> bigger.
> I have nearly 50 different nands information by hand, I will add it
> gradually in later patches.
This certainly makes the code bigger, but this is also the place where the
code belongs. Also, if you mark your structures with __initdata, such memory
can be freed later by the kernel, so I would rather go into that direction.
>
> >> +
> >> +/* macro to get the id bytes */
> >> +#define ID_GET_MFR_CODE(id) ((id)[0])
> >> +
> >> +void nand_device_print_info(struct nand_device_info *info)
> >> +{
> >> + unsigned i;
> >> + const char *mfr_name;
> >> + const char *cell_technology_name;
> >> + uint64_t chip_size;
> >> + const char *chip_size_units;
> >> + unsigned page_data_size_in_bytes;
> >> + unsigned page_oob_size_in_bytes;
> >> + struct nand_attr *attr =&info->attr;
> >> + struct nand_timing *timing =&info->timing;
> >> +
> >> + /* Prepare the manufacturer name. */
> >> + mfr_name = "Unknown";
> >> + for (i = 0; nand_manuf_ids[i].id; i++) {
> >> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
> >> + mfr_name = nand_manuf_ids[i].name;
> >> + break;
> >> + }
> >> + }
> >> +
> >> + /* Prepare the name of the cell technology. */
> >> + switch (attr->cell_technology) {
> >> + case SLC:
> >> + cell_technology_name = "SLC";
> >> + break;
> >> + case MLC:
> >> + cell_technology_name = "MLC";
> >> + break;
> >> + default:
> >> + cell_technology_name = "Unknown";
> >> + break;
> >> + }
> >> +
> >> + /* Prepare the chip size. */
> >> + if ((attr->chip_size_in_bytes>= SZ_1G)&&
> >> + !(attr->chip_size_in_bytes % SZ_1G)) {
> >> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
SZ_1G);
> >> + chip_size_units = "GiB";
> >> + } else if ((attr->chip_size_in_bytes>= SZ_1M)&&
> >> + !(attr->chip_size_in_bytes % SZ_1M)) {
> >> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
SZ_1M);
> >> + chip_size_units = "MiB";
> >> + } else {
> >> + chip_size = attr->chip_size_in_bytes;
> >> + chip_size_units = "B";
> >> + }
> >> +
> >> + /* Prepare the page geometry. */
> >> + page_data_size_in_bytes =
> >> (1<<(fls(attr->page_total_size_in_bytes)-1)); + page_oob_size_in_bytes
> >> = attr->page_total_size_in_bytes -
> >> + page_data_size_in_bytes;
> >> +
> >> + /* Print the infomation. */
> >> + printk(KERN_INFO "--------------------------------------\n");
> >> + printk(KERN_INFO " NAND device infomation (RAW)\n");
> >> + printk(KERN_INFO "--------------------------------------\n");
> >> + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
> >> + info->id[0]);
> >> + printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
> >> + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
> >> + printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
> >> + chip_size_units);
> >> + printk(KERN_INFO "Pages per Block : %u\n",
> >> attr->block_size_in_pages); + printk(KERN_INFO "Page Geometry :
> >> %u+%u\n", page_data_size_in_bytes, +
page_oob_size_in_bytes);
> >> + printk(KERN_INFO "ECC Strength : %u bits\n",
> >> + attr->ecc_strength_in_bits);
> >> + printk(KERN_INFO "ECC Size : %u B\n",
> >> attr->ecc_size_in_bytes); + printk(KERN_INFO "Data Setup Time : %u
> >> ns\n",
> >> + timing->data_setup_in_ns);
> >> + printk(KERN_INFO "Data Hold Time : %u ns\n",
> >> + timing->data_hold_in_ns);
> >> + printk(KERN_INFO "Address Setup Time: %u ns\n",
> >> + timing->address_setup_in_ns);
> >> + printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
> >> + timing->gpmi_sample_delay_in_ns);
> >> + printk(KERN_INFO "tREA : %d ns\n",
> >> + (timing->tREA_in_ns>= 0 ?
> >> + timing->tREA_in_ns : -1));
> >> + printk(KERN_INFO "tRLOH : %d ns\n",
> >> + (timing->tRLOH_in_ns>= 0 ?
> >> + timing->tRLOH_in_ns : -1));
> >> + printk(KERN_INFO "tRHOH : %d ns\n",
> >> + (timing->tRHOH_in_ns>= 0 ?
> >> + timing->tRHOH_in_ns : -1));
> >> + printk(KERN_INFO "Description : %s\n", info->desc);
> >> +}
> >
> > What is the purpose of printing all these informations? If it is for
> > debugging purposes, use dev_dbg().
>
> I do not treat this as debugging information.
> I print it out for showing the detail of a NAND.
This is not required, if you need informations about your nand chip, you'd
better use an user-space tool such as nanddump.
>
> >> +
> >> +static struct nand_device_info * __init
> >> +search_table(struct nand_device_info *table, const uint8_t id[])
> >> +{
> >> + struct nand_device_info *info = table;
> >> +
> >> + while (ID_GET_MFR_CODE(info->id)) {
> >> + int i;
> >> +
> >> + /* match all the ids. Is it too strict? */
> >> + for (i = 0; i< ID_BYTES; i++)
> >> + if (info->id[i] != id[i])
> >> + break;
> >> +
> >> + /* found it */
> >> + if (i == ID_BYTES) {
> >> + nand_device_print_info(info);
> >> + return info;
> >> + }
> >> +
> >> + info++;
> >> + }
> >> + return NULL;
> >> +}
> >> +
> >> +struct nand_device_mfr_info {
> >> + uint8_t id;
> >> + struct nand_device_info *table;
> >> +};
> >> +
> >> +static struct nand_device_mfr_info nand_device_mfr_directory[]
> >> __initdata = { + { NAND_MFR_SAMSUNG, samsung_nand },
> >> + { 0, NULL },
> >> +};
> >> +
> >> +struct nand_device_info * __init nand_device_get_info(const uint8_t
> >> id[]) +{
> >> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
> >> + unsigned i;
> >> +
> >> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
> >> + if (nand_device_mfr_directory[i].id == mfr_id) {
> >> + struct nand_device_info *table;
> >> +
> >> + table = nand_device_mfr_directory[i].table;
> >> + return search_table(table, id);
> >> + }
> >> + }
> >> + return NULL;
> >> +}
> >> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> >> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h new file mode 100644
> >> index 0000000..e606705
> >> --- /dev/null
> >> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> >> @@ -0,0 +1,145 @@
> >> +/*
> >> + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights
> >> Reserved. + */
> >> +
> >> +/*
> >> + * The code contained herein is licensed under the GNU General Public
> >> + * License. You may obtain a copy of the GNU General Public License
> >> + * Version 2 or later at the following locations:
> >> + *
> >> + * http://www.opensource.org/licenses/gpl-license.html
> >> + * http://www.gnu.org/copyleft/gpl.html
> >> + */
> >> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
> >> +#define __DRIVERS_NAND_DEVICE_INFO_H
> >> +
> >> +enum nand_device_cell_technology {
> >> + SLC = 0,
> >> + MLC = 1,
> >> +};
> >> +
> >> +/**
> >> + *
> >> + *
> >> + * @cell_technology: The storage cell technology.
> >> + * @chip_size_in_bytes: The total size of the storage behind a
> >> single + * chip select, in bytes. Notice
> >> that this is *not* + * necessarily the
> >> total size of the storage in a + *
> >> *package*, which may contain several chips. + * @block_size_in_pages:
> >> The number of pages in a block.
> >> + * @page_total_size_in_bytes: The total size of a page, in bytes,
> >> including + * both the data and the OOB.
> >> + * @ecc_strength_in_bits: The strength of the ECC called for by
> >> the + * manufacturer, in number of
> >> correctable bits. + * @ecc_size_in_bytes: The size of the data
> >> block over which the + * manufacturer calls
> >> for the given ECC algorithm + * and
> >> strength.
> >> + * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE
> >> nand ? + */
> >> +struct nand_attr {
> >> + /* Technology */
> >> + enum nand_device_cell_technology cell_technology;
> >> +
> >> + /* Geometry */
> >> + uint64_t chip_size_in_bytes;
> >> + uint32_t block_size_in_pages;
> >> + uint32_t page_total_size_in_bytes;
> >> +
> >> + /* ECC */
> >> + uint16_t ecc_size_in_bytes;
> >> + uint16_t ecc_strength_in_bits;
> >> +
> >> + /* Does the nand support DDR? (ONFI or TOGGLE) */
> >> + bool is_ddr_ok;
> >> +};
> >
> > The generic NAND code already supports reading a NAND chip ONFI page, and
> > will return the supported ONFI page, you can get all of these parameters
> > from it, no need to have this duplicated in your driver.
>
> Yes. But the generic code dose not support the TOGGLE nand now.
>
> But I think you are right, maybe I should remove the code now.
I think so, and while using generic code, take advantage of that rework to
introduce TOGGLE support in a generic manner.
>
> >> +
> >> +/**
> >> + * This structure contains the fundamental timing attributes for NAND.
> >> + *
> >> + * @data_setup_in_ns: The data setup time, in nanoseconds.
> >> Usually the + * maximum of tDS and tWP. A
> >> negative value + * indicates this
> >> characteristic isn't known. + * @data_hold_in_ns: The data
> >> hold time, in nanoseconds. Usually the + *
> >> maximum of tDH, tWH and tREH. A negative value + *
> >> indicates this
> >> characteristic isn't known. + * @address_setup_in_ns: The address
> >> setup time, in nanoseconds. Usually + * the
> >> maximum of tCLS, tCS and tALS. A negative + *
> >> value indicates this characteristic isn't known. + *
> >> @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative
> >> value + * indicates this characteristic isn't
> >> known. + * @tREA_in_ns: tREA, in nanoseconds, from the
> >> data sheet. A + * negative value indicates
> >> this characteristic isn't + * known.
> >> + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data
> >> sheet. A + * negative value indicates this
> >> characteristic isn't + * known.
> >> + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data
> >> sheet. A + * negative value indicates this
> >> characteristic isn't + * known.
> >> + */
> >> +struct nand_timing {
> >> + int8_t data_setup_in_ns;
> >> + int8_t data_hold_in_ns;
> >> + int8_t address_setup_in_ns;
> >> + int8_t gpmi_sample_delay_in_ns;
> >> + int8_t tREA_in_ns;
> >> + int8_t tRLOH_in_ns;
> >> + int8_t tRHOH_in_ns;
> >> +};
> >> +
> >> +#define ID_BYTES (8)
> >> +/*
> >> + * struct nand_device_info - Information about a single NAND Flash
> >> device. + *
> >> + * This structure contains all the *essential* information about a NAND
> >> Flash + * device, derived from the device's data sheet.
> >> + */
> >> +struct nand_device_info {
> >> + /* id */
> >> + uint8_t id[ID_BYTES];
> >> +
> >> + /* Description */
> >> + const char *desc;
> >> +
> >> + /* attribute*/
> >> + struct nand_attr attr;
> >> +
> >> + /* timing */
> >> + struct nand_timing timing;
> >> +};
> >> +
> >> +/* macro for the NAND attribute */
> >> +#define ATTR(_a, _b, _c, _d, _e, _f) \
> >> + { \
> >> + .cell_technology = (_a), \
> >> + .chip_size_in_bytes = (_b), \
> >> + .block_size_in_pages = (_c), \
> >> + .page_total_size_in_bytes = (_d), \
> >> + .ecc_strength_in_bits = (_e), \
> >> + .ecc_size_in_bytes = (_f), \
> >> + }
> >> +
> >> +/* macro for the NAND timing */
> >> +#define TIMING(_a, _b, _c, _d, _e, _f, _h) \
> >> + { \
> >> + .data_setup_in_ns = (_a), \
> >> + .data_hold_in_ns = (_b), \
> >> + .address_setup_in_ns = (_c), \
> >> + .gpmi_sample_delay_in_ns = (_d), \
> >> + .tREA_in_ns = (_e), \
> >> + .tRLOH_in_ns = (_f), \
> >> + .tRHOH_in_ns = (_h), \
> >> + }
> >> +
> >> +struct nand_device_info *nand_device_get_info(const uint8_t
> >> id_bytes[]); +void nand_device_print_info(struct nand_device_info
> >> *info);
> >> +
> >> +/*
> >> + * Check the NAND whether it supports the DDR mode.
> >> + * Only the ONFI nand and TOGGLE nand support the DDR now.
> >> + */
> >> +static inline bool is_ddr_nand(struct nand_device_info *info)
> >> +{
> >> + return info->attr.is_ddr_ok;
> >> +}
> >> +#endif
>
> Best Regards
> Huang Shijie
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
@ 2011-03-24 13:50 ` Florian Fainelli
0 siblings, 0 replies; 49+ messages in thread
From: Florian Fainelli @ 2011-03-24 13:50 UTC (permalink / raw)
To: linux-arm-kernel
Hello Huang,
On Thursday 24 March 2011 03:27:40 Huang Shijie wrote:
> Hi Florian:
> thanks a lot for your review.
>
> > Hello Huang,
> >
> > On Wednesday 16 March 2011 02:55:17 Huang Shijie wrote:
> >> This is a database for the NANDs which is now supported by imx23 and
> >> imx28.
> >>
> >> Signed-off-by: Huang Shijie<b32955@freescale.com>
> >> ---
> >>
> >> drivers/mtd/nand/gpmi-nfc/nand_device_info.c | 181
> >>
> >> ++++++++++++++++++++++++++ drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> >> | 145 +++++++++++++++++++++ 2 files changed, 326 insertions(+), 0
> >> deletions(-)
> >>
> >> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> >> create mode 100644 drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> >>
> >> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> >> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c new file mode 100644
> >> index 0000000..aa0813a
> >> --- /dev/null
> >> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.c
> >> @@ -0,0 +1,181 @@
> >> +/*
> >> + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights
> >> Reserved. + */
> >> +
> >> +/*
> >> + * The code contained herein is licensed under the GNU General Public
> >> + * License. You may obtain a copy of the GNU General Public License
> >> + * Version 2 or later at the following locations:
> >> + *
> >> + * http://www.opensource.org/licenses/gpl-license.html
> >> + * http://www.gnu.org/copyleft/gpl.html
> >> + */
> >> +
> >> +#include<asm/sizes.h>
> >> +#include<linux/mtd/nand.h>
> >> +
> >> +#include "nand_device_info.h"
> >> +
> >> +static struct nand_device_info samsung_nand[] __initdata = {
> >> + {
> >> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
> >> + .desc = "K9G8G08U0M, K9HAG08U1M",
> >> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
> >> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
> >> + }, {
> >> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
> >> + .desc = "K9LBG08U0D",
> >> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
> >> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
> >> + }, {
> >> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
> >> + .desc = "K9GAG08U0M",
> >> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
> >> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
> >> + }, {
> >> + /* end of the table. */
> >> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
> >> + },
> >> +};
> >
> > Such information should be set in platform code, because it is specific
> > to your controller and most likely to a particular board design.
>
> I prefer to place it here.
>
> If I move the code to arch/arm/mach-mxs, it will make the arch/ much
> bigger.
> I have nearly 50 different nands information by hand, I will add it
> gradually in later patches.
This certainly makes the code bigger, but this is also the place where the
code belongs. Also, if you mark your structures with __initdata, such memory
can be freed later by the kernel, so I would rather go into that direction.
>
> >> +
> >> +/* macro to get the id bytes */
> >> +#define ID_GET_MFR_CODE(id) ((id)[0])
> >> +
> >> +void nand_device_print_info(struct nand_device_info *info)
> >> +{
> >> + unsigned i;
> >> + const char *mfr_name;
> >> + const char *cell_technology_name;
> >> + uint64_t chip_size;
> >> + const char *chip_size_units;
> >> + unsigned page_data_size_in_bytes;
> >> + unsigned page_oob_size_in_bytes;
> >> + struct nand_attr *attr =&info->attr;
> >> + struct nand_timing *timing =&info->timing;
> >> +
> >> + /* Prepare the manufacturer name. */
> >> + mfr_name = "Unknown";
> >> + for (i = 0; nand_manuf_ids[i].id; i++) {
> >> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
> >> + mfr_name = nand_manuf_ids[i].name;
> >> + break;
> >> + }
> >> + }
> >> +
> >> + /* Prepare the name of the cell technology. */
> >> + switch (attr->cell_technology) {
> >> + case SLC:
> >> + cell_technology_name = "SLC";
> >> + break;
> >> + case MLC:
> >> + cell_technology_name = "MLC";
> >> + break;
> >> + default:
> >> + cell_technology_name = "Unknown";
> >> + break;
> >> + }
> >> +
> >> + /* Prepare the chip size. */
> >> + if ((attr->chip_size_in_bytes>= SZ_1G)&&
> >> + !(attr->chip_size_in_bytes % SZ_1G)) {
> >> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
SZ_1G);
> >> + chip_size_units = "GiB";
> >> + } else if ((attr->chip_size_in_bytes>= SZ_1M)&&
> >> + !(attr->chip_size_in_bytes % SZ_1M)) {
> >> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
SZ_1M);
> >> + chip_size_units = "MiB";
> >> + } else {
> >> + chip_size = attr->chip_size_in_bytes;
> >> + chip_size_units = "B";
> >> + }
> >> +
> >> + /* Prepare the page geometry. */
> >> + page_data_size_in_bytes =
> >> (1<<(fls(attr->page_total_size_in_bytes)-1)); + page_oob_size_in_bytes
> >> = attr->page_total_size_in_bytes -
> >> + page_data_size_in_bytes;
> >> +
> >> + /* Print the infomation. */
> >> + printk(KERN_INFO "--------------------------------------\n");
> >> + printk(KERN_INFO " NAND device infomation (RAW)\n");
> >> + printk(KERN_INFO "--------------------------------------\n");
> >> + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
> >> + info->id[0]);
> >> + printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
> >> + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
> >> + printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
> >> + chip_size_units);
> >> + printk(KERN_INFO "Pages per Block : %u\n",
> >> attr->block_size_in_pages); + printk(KERN_INFO "Page Geometry :
> >> %u+%u\n", page_data_size_in_bytes, +
page_oob_size_in_bytes);
> >> + printk(KERN_INFO "ECC Strength : %u bits\n",
> >> + attr->ecc_strength_in_bits);
> >> + printk(KERN_INFO "ECC Size : %u B\n",
> >> attr->ecc_size_in_bytes); + printk(KERN_INFO "Data Setup Time : %u
> >> ns\n",
> >> + timing->data_setup_in_ns);
> >> + printk(KERN_INFO "Data Hold Time : %u ns\n",
> >> + timing->data_hold_in_ns);
> >> + printk(KERN_INFO "Address Setup Time: %u ns\n",
> >> + timing->address_setup_in_ns);
> >> + printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
> >> + timing->gpmi_sample_delay_in_ns);
> >> + printk(KERN_INFO "tREA : %d ns\n",
> >> + (timing->tREA_in_ns>= 0 ?
> >> + timing->tREA_in_ns : -1));
> >> + printk(KERN_INFO "tRLOH : %d ns\n",
> >> + (timing->tRLOH_in_ns>= 0 ?
> >> + timing->tRLOH_in_ns : -1));
> >> + printk(KERN_INFO "tRHOH : %d ns\n",
> >> + (timing->tRHOH_in_ns>= 0 ?
> >> + timing->tRHOH_in_ns : -1));
> >> + printk(KERN_INFO "Description : %s\n", info->desc);
> >> +}
> >
> > What is the purpose of printing all these informations? If it is for
> > debugging purposes, use dev_dbg().
>
> I do not treat this as debugging information.
> I print it out for showing the detail of a NAND.
This is not required, if you need informations about your nand chip, you'd
better use an user-space tool such as nanddump.
>
> >> +
> >> +static struct nand_device_info * __init
> >> +search_table(struct nand_device_info *table, const uint8_t id[])
> >> +{
> >> + struct nand_device_info *info = table;
> >> +
> >> + while (ID_GET_MFR_CODE(info->id)) {
> >> + int i;
> >> +
> >> + /* match all the ids. Is it too strict? */
> >> + for (i = 0; i< ID_BYTES; i++)
> >> + if (info->id[i] != id[i])
> >> + break;
> >> +
> >> + /* found it */
> >> + if (i == ID_BYTES) {
> >> + nand_device_print_info(info);
> >> + return info;
> >> + }
> >> +
> >> + info++;
> >> + }
> >> + return NULL;
> >> +}
> >> +
> >> +struct nand_device_mfr_info {
> >> + uint8_t id;
> >> + struct nand_device_info *table;
> >> +};
> >> +
> >> +static struct nand_device_mfr_info nand_device_mfr_directory[]
> >> __initdata = { + { NAND_MFR_SAMSUNG, samsung_nand },
> >> + { 0, NULL },
> >> +};
> >> +
> >> +struct nand_device_info * __init nand_device_get_info(const uint8_t
> >> id[]) +{
> >> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
> >> + unsigned i;
> >> +
> >> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
> >> + if (nand_device_mfr_directory[i].id == mfr_id) {
> >> + struct nand_device_info *table;
> >> +
> >> + table = nand_device_mfr_directory[i].table;
> >> + return search_table(table, id);
> >> + }
> >> + }
> >> + return NULL;
> >> +}
> >> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> >> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h new file mode 100644
> >> index 0000000..e606705
> >> --- /dev/null
> >> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
> >> @@ -0,0 +1,145 @@
> >> +/*
> >> + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights
> >> Reserved. + */
> >> +
> >> +/*
> >> + * The code contained herein is licensed under the GNU General Public
> >> + * License. You may obtain a copy of the GNU General Public License
> >> + * Version 2 or later at the following locations:
> >> + *
> >> + * http://www.opensource.org/licenses/gpl-license.html
> >> + * http://www.gnu.org/copyleft/gpl.html
> >> + */
> >> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
> >> +#define __DRIVERS_NAND_DEVICE_INFO_H
> >> +
> >> +enum nand_device_cell_technology {
> >> + SLC = 0,
> >> + MLC = 1,
> >> +};
> >> +
> >> +/**
> >> + *
> >> + *
> >> + * @cell_technology: The storage cell technology.
> >> + * @chip_size_in_bytes: The total size of the storage behind a
> >> single + * chip select, in bytes. Notice
> >> that this is *not* + * necessarily the
> >> total size of the storage in a + *
> >> *package*, which may contain several chips. + * @block_size_in_pages:
> >> The number of pages in a block.
> >> + * @page_total_size_in_bytes: The total size of a page, in bytes,
> >> including + * both the data and the OOB.
> >> + * @ecc_strength_in_bits: The strength of the ECC called for by
> >> the + * manufacturer, in number of
> >> correctable bits. + * @ecc_size_in_bytes: The size of the data
> >> block over which the + * manufacturer calls
> >> for the given ECC algorithm + * and
> >> strength.
> >> + * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE
> >> nand ? + */
> >> +struct nand_attr {
> >> + /* Technology */
> >> + enum nand_device_cell_technology cell_technology;
> >> +
> >> + /* Geometry */
> >> + uint64_t chip_size_in_bytes;
> >> + uint32_t block_size_in_pages;
> >> + uint32_t page_total_size_in_bytes;
> >> +
> >> + /* ECC */
> >> + uint16_t ecc_size_in_bytes;
> >> + uint16_t ecc_strength_in_bits;
> >> +
> >> + /* Does the nand support DDR? (ONFI or TOGGLE) */
> >> + bool is_ddr_ok;
> >> +};
> >
> > The generic NAND code already supports reading a NAND chip ONFI page, and
> > will return the supported ONFI page, you can get all of these parameters
> > from it, no need to have this duplicated in your driver.
>
> Yes. But the generic code dose not support the TOGGLE nand now.
>
> But I think you are right, maybe I should remove the code now.
I think so, and while using generic code, take advantage of that rework to
introduce TOGGLE support in a generic manner.
>
> >> +
> >> +/**
> >> + * This structure contains the fundamental timing attributes for NAND.
> >> + *
> >> + * @data_setup_in_ns: The data setup time, in nanoseconds.
> >> Usually the + * maximum of tDS and tWP. A
> >> negative value + * indicates this
> >> characteristic isn't known. + * @data_hold_in_ns: The data
> >> hold time, in nanoseconds. Usually the + *
> >> maximum of tDH, tWH and tREH. A negative value + *
> >> indicates this
> >> characteristic isn't known. + * @address_setup_in_ns: The address
> >> setup time, in nanoseconds. Usually + * the
> >> maximum of tCLS, tCS and tALS. A negative + *
> >> value indicates this characteristic isn't known. + *
> >> @gpmi_sample_delay_in_ns: A GPMI-specific timing parameter. A negative
> >> value + * indicates this characteristic isn't
> >> known. + * @tREA_in_ns: tREA, in nanoseconds, from the
> >> data sheet. A + * negative value indicates
> >> this characteristic isn't + * known.
> >> + * @tRLOH_in_ns: tRLOH, in nanoseconds, from the data
> >> sheet. A + * negative value indicates this
> >> characteristic isn't + * known.
> >> + * @tRHOH_in_ns: tRHOH, in nanoseconds, from the data
> >> sheet. A + * negative value indicates this
> >> characteristic isn't + * known.
> >> + */
> >> +struct nand_timing {
> >> + int8_t data_setup_in_ns;
> >> + int8_t data_hold_in_ns;
> >> + int8_t address_setup_in_ns;
> >> + int8_t gpmi_sample_delay_in_ns;
> >> + int8_t tREA_in_ns;
> >> + int8_t tRLOH_in_ns;
> >> + int8_t tRHOH_in_ns;
> >> +};
> >> +
> >> +#define ID_BYTES (8)
> >> +/*
> >> + * struct nand_device_info - Information about a single NAND Flash
> >> device. + *
> >> + * This structure contains all the *essential* information about a NAND
> >> Flash + * device, derived from the device's data sheet.
> >> + */
> >> +struct nand_device_info {
> >> + /* id */
> >> + uint8_t id[ID_BYTES];
> >> +
> >> + /* Description */
> >> + const char *desc;
> >> +
> >> + /* attribute*/
> >> + struct nand_attr attr;
> >> +
> >> + /* timing */
> >> + struct nand_timing timing;
> >> +};
> >> +
> >> +/* macro for the NAND attribute */
> >> +#define ATTR(_a, _b, _c, _d, _e, _f) \
> >> + { \
> >> + .cell_technology = (_a), \
> >> + .chip_size_in_bytes = (_b), \
> >> + .block_size_in_pages = (_c), \
> >> + .page_total_size_in_bytes = (_d), \
> >> + .ecc_strength_in_bits = (_e), \
> >> + .ecc_size_in_bytes = (_f), \
> >> + }
> >> +
> >> +/* macro for the NAND timing */
> >> +#define TIMING(_a, _b, _c, _d, _e, _f, _h) \
> >> + { \
> >> + .data_setup_in_ns = (_a), \
> >> + .data_hold_in_ns = (_b), \
> >> + .address_setup_in_ns = (_c), \
> >> + .gpmi_sample_delay_in_ns = (_d), \
> >> + .tREA_in_ns = (_e), \
> >> + .tRLOH_in_ns = (_f), \
> >> + .tRHOH_in_ns = (_h), \
> >> + }
> >> +
> >> +struct nand_device_info *nand_device_get_info(const uint8_t
> >> id_bytes[]); +void nand_device_print_info(struct nand_device_info
> >> *info);
> >> +
> >> +/*
> >> + * Check the NAND whether it supports the DDR mode.
> >> + * Only the ONFI nand and TOGGLE nand support the DDR now.
> >> + */
> >> +static inline bool is_ddr_nand(struct nand_device_info *info)
> >> +{
> >> + return info->attr.is_ddr_ok;
> >> +}
> >> +#endif
>
> Best Regards
> Huang Shijie
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 3/7] add the database for the NANDs
2011-03-24 13:50 ` Florian Fainelli
@ 2011-03-25 2:47 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-25 2:47 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux, linux-mtd, dwmw2, linux-arm-kernel, David.Woodhouse
Hi Florian:
>>>> +#include "nand_device_info.h"
>>>> +
>>>> +static struct nand_device_info samsung_nand[] __initdata = {
>>>> + {
>>>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
>>>> + .desc = "K9G8G08U0M, K9HAG08U1M",
>>>> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
>>>> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
>>>> + }, {
>>>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
>>>> + .desc = "K9LBG08U0D",
>>>> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
>>>> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
>>>> + }, {
>>>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
>>>> + .desc = "K9GAG08U0M",
>>>> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
>>>> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
>>>> + }, {
>>>> + /* end of the table. */
>>>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
>>>> + },
>>>> +};
>>> Such information should be set in platform code, because it is specific
>>> to your controller and most likely to a particular board design.
>> I prefer to place it here.
>>
>> If I move the code to arch/arm/mach-mxs, it will make the arch/ much
>> bigger.
>> I have nearly 50 different nands information by hand, I will add it
>> gradually in later patches.
> This certainly makes the code bigger, but this is also the place where the
> code belongs. Also, if you mark your structures with __initdata, such memory
> can be freed later by the kernel, so I would rather go into that direction.
>
Please check the emails i talked with Lothar.
thanks.
>>>> +
>>>> +/* macro to get the id bytes */
>>>> +#define ID_GET_MFR_CODE(id) ((id)[0])
>>>> +
>>>> +void nand_device_print_info(struct nand_device_info *info)
>>>> +{
>>>> + unsigned i;
>>>> + const char *mfr_name;
>>>> + const char *cell_technology_name;
>>>> + uint64_t chip_size;
>>>> + const char *chip_size_units;
>>>> + unsigned page_data_size_in_bytes;
>>>> + unsigned page_oob_size_in_bytes;
>>>> + struct nand_attr *attr =&info->attr;
>>>> + struct nand_timing *timing =&info->timing;
>>>> +
>>>> + /* Prepare the manufacturer name. */
>>>> + mfr_name = "Unknown";
>>>> + for (i = 0; nand_manuf_ids[i].id; i++) {
>>>> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
>>>> + mfr_name = nand_manuf_ids[i].name;
>>>> + break;
>>>> + }
>>>> + }
>>>> +
>>>> + /* Prepare the name of the cell technology. */
>>>> + switch (attr->cell_technology) {
>>>> + case SLC:
>>>> + cell_technology_name = "SLC";
>>>> + break;
>>>> + case MLC:
>>>> + cell_technology_name = "MLC";
>>>> + break;
>>>> + default:
>>>> + cell_technology_name = "Unknown";
>>>> + break;
>>>> + }
>>>> +
>>>> + /* Prepare the chip size. */
>>>> + if ((attr->chip_size_in_bytes>= SZ_1G)&&
>>>> + !(attr->chip_size_in_bytes % SZ_1G)) {
>>>> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
> SZ_1G);
>>>> + chip_size_units = "GiB";
>>>> + } else if ((attr->chip_size_in_bytes>= SZ_1M)&&
>>>> + !(attr->chip_size_in_bytes % SZ_1M)) {
>>>> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
> SZ_1M);
>>>> + chip_size_units = "MiB";
>>>> + } else {
>>>> + chip_size = attr->chip_size_in_bytes;
>>>> + chip_size_units = "B";
>>>> + }
>>>> +
>>>> + /* Prepare the page geometry. */
>>>> + page_data_size_in_bytes =
>>>> (1<<(fls(attr->page_total_size_in_bytes)-1)); + page_oob_size_in_bytes
>>>> = attr->page_total_size_in_bytes -
>>>> + page_data_size_in_bytes;
>>>> +
>>>> + /* Print the infomation. */
>>>> + printk(KERN_INFO "--------------------------------------\n");
>>>> + printk(KERN_INFO " NAND device infomation (RAW)\n");
>>>> + printk(KERN_INFO "--------------------------------------\n");
>>>> + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
>>>> + info->id[0]);
>>>> + printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
>>>> + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
>>>> + printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
>>>> + chip_size_units);
>>>> + printk(KERN_INFO "Pages per Block : %u\n",
>>>> attr->block_size_in_pages); + printk(KERN_INFO "Page Geometry :
>>>> %u+%u\n", page_data_size_in_bytes, +
> page_oob_size_in_bytes);
>>>> + printk(KERN_INFO "ECC Strength : %u bits\n",
>>>> + attr->ecc_strength_in_bits);
>>>> + printk(KERN_INFO "ECC Size : %u B\n",
>>>> attr->ecc_size_in_bytes); + printk(KERN_INFO "Data Setup Time : %u
>>>> ns\n",
>>>> + timing->data_setup_in_ns);
>>>> + printk(KERN_INFO "Data Hold Time : %u ns\n",
>>>> + timing->data_hold_in_ns);
>>>> + printk(KERN_INFO "Address Setup Time: %u ns\n",
>>>> + timing->address_setup_in_ns);
>>>> + printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
>>>> + timing->gpmi_sample_delay_in_ns);
>>>> + printk(KERN_INFO "tREA : %d ns\n",
>>>> + (timing->tREA_in_ns>= 0 ?
>>>> + timing->tREA_in_ns : -1));
>>>> + printk(KERN_INFO "tRLOH : %d ns\n",
>>>> + (timing->tRLOH_in_ns>= 0 ?
>>>> + timing->tRLOH_in_ns : -1));
>>>> + printk(KERN_INFO "tRHOH : %d ns\n",
>>>> + (timing->tRHOH_in_ns>= 0 ?
>>>> + timing->tRHOH_in_ns : -1));
>>>> + printk(KERN_INFO "Description : %s\n", info->desc);
>>>> +}
>>> What is the purpose of printing all these informations? If it is for
>>> debugging purposes, use dev_dbg().
>> I do not treat this as debugging information.
>> I print it out for showing the detail of a NAND.
> This is not required, if you need informations about your nand chip, you'd
> better use an user-space tool such as nanddump.
>
ok. I will add a debug control for the log.
>>>> +
>>>> +static struct nand_device_info * __init
>>>> +search_table(struct nand_device_info *table, const uint8_t id[])
>>>> +{
>>>> + struct nand_device_info *info = table;
>>>> +
>>>> + while (ID_GET_MFR_CODE(info->id)) {
>>>> + int i;
>>>> +
>>>> + /* match all the ids. Is it too strict? */
>>>> + for (i = 0; i< ID_BYTES; i++)
>>>> + if (info->id[i] != id[i])
>>>> + break;
>>>> +
>>>> + /* found it */
>>>> + if (i == ID_BYTES) {
>>>> + nand_device_print_info(info);
>>>> + return info;
>>>> + }
>>>> +
>>>> + info++;
>>>> + }
>>>> + return NULL;
>>>> +}
>>>> +
>>>> +struct nand_device_mfr_info {
>>>> + uint8_t id;
>>>> + struct nand_device_info *table;
>>>> +};
>>>> +
>>>> +static struct nand_device_mfr_info nand_device_mfr_directory[]
>>>> __initdata = { + { NAND_MFR_SAMSUNG, samsung_nand },
>>>> + { 0, NULL },
>>>> +};
>>>> +
>>>> +struct nand_device_info * __init nand_device_get_info(const uint8_t
>>>> id[]) +{
>>>> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
>>>> + unsigned i;
>>>> +
>>>> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
>>>> + if (nand_device_mfr_directory[i].id == mfr_id) {
>>>> + struct nand_device_info *table;
>>>> +
>>>> + table = nand_device_mfr_directory[i].table;
>>>> + return search_table(table, id);
>>>> + }
>>>> + }
>>>> + return NULL;
>>>> +}
>>>> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>>>> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h new file mode 100644
>>>> index 0000000..e606705
>>>> --- /dev/null
>>>> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>>>> @@ -0,0 +1,145 @@
>>>> +/*
>>>> + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights
>>>> Reserved. + */
>>>> +
>>>> +/*
>>>> + * The code contained herein is licensed under the GNU General Public
>>>> + * License. You may obtain a copy of the GNU General Public License
>>>> + * Version 2 or later at the following locations:
>>>> + *
>>>> + * http://www.opensource.org/licenses/gpl-license.html
>>>> + * http://www.gnu.org/copyleft/gpl.html
>>>> + */
>>>> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
>>>> +#define __DRIVERS_NAND_DEVICE_INFO_H
>>>> +
>>>> +enum nand_device_cell_technology {
>>>> + SLC = 0,
>>>> + MLC = 1,
>>>> +};
>>>> +
>>>> +/**
>>>> + *
>>>> + *
>>>> + * @cell_technology: The storage cell technology.
>>>> + * @chip_size_in_bytes: The total size of the storage behind a
>>>> single + * chip select, in bytes. Notice
>>>> that this is *not* + * necessarily the
>>>> total size of the storage in a + *
>>>> *package*, which may contain several chips. + * @block_size_in_pages:
>>>> The number of pages in a block.
>>>> + * @page_total_size_in_bytes: The total size of a page, in bytes,
>>>> including + * both the data and the OOB.
>>>> + * @ecc_strength_in_bits: The strength of the ECC called for by
>>>> the + * manufacturer, in number of
>>>> correctable bits. + * @ecc_size_in_bytes: The size of the data
>>>> block over which the + * manufacturer calls
>>>> for the given ECC algorithm + * and
>>>> strength.
>>>> + * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE
>>>> nand ? + */
>>>> +struct nand_attr {
>>>> + /* Technology */
>>>> + enum nand_device_cell_technology cell_technology;
>>>> +
>>>> + /* Geometry */
>>>> + uint64_t chip_size_in_bytes;
>>>> + uint32_t block_size_in_pages;
>>>> + uint32_t page_total_size_in_bytes;
>>>> +
>>>> + /* ECC */
>>>> + uint16_t ecc_size_in_bytes;
>>>> + uint16_t ecc_strength_in_bits;
>>>> +
>>>> + /* Does the nand support DDR? (ONFI or TOGGLE) */
>>>> + bool is_ddr_ok;
>>>> +};
>>> The generic NAND code already supports reading a NAND chip ONFI page, and
>>> will return the supported ONFI page, you can get all of these parameters
>>> from it, no need to have this duplicated in your driver.
>> Yes. But the generic code dose not support the TOGGLE nand now.
>>
>> But I think you are right, maybe I should remove the code now.
> I think so, and while using generic code, take advantage of that rework to
> introduce TOGGLE support in a generic manner.
>
thanks.
Best Regards
Huang Shijie
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
@ 2011-03-25 2:47 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-25 2:47 UTC (permalink / raw)
To: linux-arm-kernel
Hi Florian:
>>>> +#include "nand_device_info.h"
>>>> +
>>>> +static struct nand_device_info samsung_nand[] __initdata = {
>>>> + {
>>>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
>>>> + .desc = "K9G8G08U0M, K9HAG08U1M",
>>>> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
>>>> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
>>>> + }, {
>>>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
>>>> + .desc = "K9LBG08U0D",
>>>> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
>>>> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
>>>> + }, {
>>>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
>>>> + .desc = "K9GAG08U0M",
>>>> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
>>>> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
>>>> + }, {
>>>> + /* end of the table. */
>>>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
>>>> + },
>>>> +};
>>> Such information should be set in platform code, because it is specific
>>> to your controller and most likely to a particular board design.
>> I prefer to place it here.
>>
>> If I move the code to arch/arm/mach-mxs, it will make the arch/ much
>> bigger.
>> I have nearly 50 different nands information by hand, I will add it
>> gradually in later patches.
> This certainly makes the code bigger, but this is also the place where the
> code belongs. Also, if you mark your structures with __initdata, such memory
> can be freed later by the kernel, so I would rather go into that direction.
>
Please check the emails i talked with Lothar.
thanks.
>>>> +
>>>> +/* macro to get the id bytes */
>>>> +#define ID_GET_MFR_CODE(id) ((id)[0])
>>>> +
>>>> +void nand_device_print_info(struct nand_device_info *info)
>>>> +{
>>>> + unsigned i;
>>>> + const char *mfr_name;
>>>> + const char *cell_technology_name;
>>>> + uint64_t chip_size;
>>>> + const char *chip_size_units;
>>>> + unsigned page_data_size_in_bytes;
>>>> + unsigned page_oob_size_in_bytes;
>>>> + struct nand_attr *attr =&info->attr;
>>>> + struct nand_timing *timing =&info->timing;
>>>> +
>>>> + /* Prepare the manufacturer name. */
>>>> + mfr_name = "Unknown";
>>>> + for (i = 0; nand_manuf_ids[i].id; i++) {
>>>> + if (nand_manuf_ids[i].id == ID_GET_MFR_CODE(info->id)) {
>>>> + mfr_name = nand_manuf_ids[i].name;
>>>> + break;
>>>> + }
>>>> + }
>>>> +
>>>> + /* Prepare the name of the cell technology. */
>>>> + switch (attr->cell_technology) {
>>>> + case SLC:
>>>> + cell_technology_name = "SLC";
>>>> + break;
>>>> + case MLC:
>>>> + cell_technology_name = "MLC";
>>>> + break;
>>>> + default:
>>>> + cell_technology_name = "Unknown";
>>>> + break;
>>>> + }
>>>> +
>>>> + /* Prepare the chip size. */
>>>> + if ((attr->chip_size_in_bytes>= SZ_1G)&&
>>>> + !(attr->chip_size_in_bytes % SZ_1G)) {
>>>> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
> SZ_1G);
>>>> + chip_size_units = "GiB";
>>>> + } else if ((attr->chip_size_in_bytes>= SZ_1M)&&
>>>> + !(attr->chip_size_in_bytes % SZ_1M)) {
>>>> + chip_size = attr->chip_size_in_bytes / ((uint64_t)
> SZ_1M);
>>>> + chip_size_units = "MiB";
>>>> + } else {
>>>> + chip_size = attr->chip_size_in_bytes;
>>>> + chip_size_units = "B";
>>>> + }
>>>> +
>>>> + /* Prepare the page geometry. */
>>>> + page_data_size_in_bytes =
>>>> (1<<(fls(attr->page_total_size_in_bytes)-1)); + page_oob_size_in_bytes
>>>> = attr->page_total_size_in_bytes -
>>>> + page_data_size_in_bytes;
>>>> +
>>>> + /* Print the infomation. */
>>>> + printk(KERN_INFO "--------------------------------------\n");
>>>> + printk(KERN_INFO " NAND device infomation (RAW)\n");
>>>> + printk(KERN_INFO "--------------------------------------\n");
>>>> + printk(KERN_INFO "Manufacturer : %s (0x%02x)\n", mfr_name,
>>>> + info->id[0]);
>>>> + printk(KERN_INFO "Device Code : 0x%02x\n", info->id[1]);
>>>> + printk(KERN_INFO "Cell Technology : %s\n", cell_technology_name);
>>>> + printk(KERN_INFO "Chip Size : %llu %s\n", chip_size,
>>>> + chip_size_units);
>>>> + printk(KERN_INFO "Pages per Block : %u\n",
>>>> attr->block_size_in_pages); + printk(KERN_INFO "Page Geometry :
>>>> %u+%u\n", page_data_size_in_bytes, +
> page_oob_size_in_bytes);
>>>> + printk(KERN_INFO "ECC Strength : %u bits\n",
>>>> + attr->ecc_strength_in_bits);
>>>> + printk(KERN_INFO "ECC Size : %u B\n",
>>>> attr->ecc_size_in_bytes); + printk(KERN_INFO "Data Setup Time : %u
>>>> ns\n",
>>>> + timing->data_setup_in_ns);
>>>> + printk(KERN_INFO "Data Hold Time : %u ns\n",
>>>> + timing->data_hold_in_ns);
>>>> + printk(KERN_INFO "Address Setup Time: %u ns\n",
>>>> + timing->address_setup_in_ns);
>>>> + printk(KERN_INFO "GPMI Sample Delay : %u ns\n",
>>>> + timing->gpmi_sample_delay_in_ns);
>>>> + printk(KERN_INFO "tREA : %d ns\n",
>>>> + (timing->tREA_in_ns>= 0 ?
>>>> + timing->tREA_in_ns : -1));
>>>> + printk(KERN_INFO "tRLOH : %d ns\n",
>>>> + (timing->tRLOH_in_ns>= 0 ?
>>>> + timing->tRLOH_in_ns : -1));
>>>> + printk(KERN_INFO "tRHOH : %d ns\n",
>>>> + (timing->tRHOH_in_ns>= 0 ?
>>>> + timing->tRHOH_in_ns : -1));
>>>> + printk(KERN_INFO "Description : %s\n", info->desc);
>>>> +}
>>> What is the purpose of printing all these informations? If it is for
>>> debugging purposes, use dev_dbg().
>> I do not treat this as debugging information.
>> I print it out for showing the detail of a NAND.
> This is not required, if you need informations about your nand chip, you'd
> better use an user-space tool such as nanddump.
>
ok. I will add a debug control for the log.
>>>> +
>>>> +static struct nand_device_info * __init
>>>> +search_table(struct nand_device_info *table, const uint8_t id[])
>>>> +{
>>>> + struct nand_device_info *info = table;
>>>> +
>>>> + while (ID_GET_MFR_CODE(info->id)) {
>>>> + int i;
>>>> +
>>>> + /* match all the ids. Is it too strict? */
>>>> + for (i = 0; i< ID_BYTES; i++)
>>>> + if (info->id[i] != id[i])
>>>> + break;
>>>> +
>>>> + /* found it */
>>>> + if (i == ID_BYTES) {
>>>> + nand_device_print_info(info);
>>>> + return info;
>>>> + }
>>>> +
>>>> + info++;
>>>> + }
>>>> + return NULL;
>>>> +}
>>>> +
>>>> +struct nand_device_mfr_info {
>>>> + uint8_t id;
>>>> + struct nand_device_info *table;
>>>> +};
>>>> +
>>>> +static struct nand_device_mfr_info nand_device_mfr_directory[]
>>>> __initdata = { + { NAND_MFR_SAMSUNG, samsung_nand },
>>>> + { 0, NULL },
>>>> +};
>>>> +
>>>> +struct nand_device_info * __init nand_device_get_info(const uint8_t
>>>> id[]) +{
>>>> + uint8_t mfr_id = ID_GET_MFR_CODE(id);
>>>> + unsigned i;
>>>> +
>>>> + for (i = 0; nand_device_mfr_directory[i].id; i++) {
>>>> + if (nand_device_mfr_directory[i].id == mfr_id) {
>>>> + struct nand_device_info *table;
>>>> +
>>>> + table = nand_device_mfr_directory[i].table;
>>>> + return search_table(table, id);
>>>> + }
>>>> + }
>>>> + return NULL;
>>>> +}
>>>> diff --git a/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>>>> b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h new file mode 100644
>>>> index 0000000..e606705
>>>> --- /dev/null
>>>> +++ b/drivers/mtd/nand/gpmi-nfc/nand_device_info.h
>>>> @@ -0,0 +1,145 @@
>>>> +/*
>>>> + * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights
>>>> Reserved. + */
>>>> +
>>>> +/*
>>>> + * The code contained herein is licensed under the GNU General Public
>>>> + * License. You may obtain a copy of the GNU General Public License
>>>> + * Version 2 or later at the following locations:
>>>> + *
>>>> + * http://www.opensource.org/licenses/gpl-license.html
>>>> + * http://www.gnu.org/copyleft/gpl.html
>>>> + */
>>>> +#ifndef __DRIVERS_NAND_DEVICE_INFO_H
>>>> +#define __DRIVERS_NAND_DEVICE_INFO_H
>>>> +
>>>> +enum nand_device_cell_technology {
>>>> + SLC = 0,
>>>> + MLC = 1,
>>>> +};
>>>> +
>>>> +/**
>>>> + *
>>>> + *
>>>> + * @cell_technology: The storage cell technology.
>>>> + * @chip_size_in_bytes: The total size of the storage behind a
>>>> single + * chip select, in bytes. Notice
>>>> that this is *not* + * necessarily the
>>>> total size of the storage in a + *
>>>> *package*, which may contain several chips. + * @block_size_in_pages:
>>>> The number of pages in a block.
>>>> + * @page_total_size_in_bytes: The total size of a page, in bytes,
>>>> including + * both the data and the OOB.
>>>> + * @ecc_strength_in_bits: The strength of the ECC called for by
>>>> the + * manufacturer, in number of
>>>> correctable bits. + * @ecc_size_in_bytes: The size of the data
>>>> block over which the + * manufacturer calls
>>>> for the given ECC algorithm + * and
>>>> strength.
>>>> + * @is_ddr_ok: Is this nand an ONFI nand or a TOGGLE
>>>> nand ? + */
>>>> +struct nand_attr {
>>>> + /* Technology */
>>>> + enum nand_device_cell_technology cell_technology;
>>>> +
>>>> + /* Geometry */
>>>> + uint64_t chip_size_in_bytes;
>>>> + uint32_t block_size_in_pages;
>>>> + uint32_t page_total_size_in_bytes;
>>>> +
>>>> + /* ECC */
>>>> + uint16_t ecc_size_in_bytes;
>>>> + uint16_t ecc_strength_in_bits;
>>>> +
>>>> + /* Does the nand support DDR? (ONFI or TOGGLE) */
>>>> + bool is_ddr_ok;
>>>> +};
>>> The generic NAND code already supports reading a NAND chip ONFI page, and
>>> will return the supported ONFI page, you can get all of these parameters
>>> from it, no need to have this duplicated in your driver.
>> Yes. But the generic code dose not support the TOGGLE nand now.
>>
>> But I think you are right, maybe I should remove the code now.
> I think so, and while using generic code, take advantage of that rework to
> introduce TOGGLE support in a generic manner.
>
thanks.
Best Regards
Huang Shijie
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 3/7] add the database for the NANDs
2011-03-25 2:47 ` Huang Shijie
@ 2011-03-25 6:48 ` Lothar Waßmann
-1 siblings, 0 replies; 49+ messages in thread
From: Lothar Waßmann @ 2011-03-25 6:48 UTC (permalink / raw)
To: Huang Shijie
Cc: linux, David.Woodhouse, linux-mtd, Florian Fainelli, dwmw2,
linux-arm-kernel
Hi,
Huang Shijie writes:
> Hi Florian:
>
>
> >>>> +#include "nand_device_info.h"
> >>>> +
> >>>> +static struct nand_device_info samsung_nand[] __initdata = {
> >>>> + {
> >>>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
> >>>> + .desc = "K9G8G08U0M, K9HAG08U1M",
> >>>> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
> >>>> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
> >>>> + }, {
> >>>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
> >>>> + .desc = "K9LBG08U0D",
> >>>> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
> >>>> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
> >>>> + }, {
> >>>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
> >>>> + .desc = "K9GAG08U0M",
> >>>> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
> >>>> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
> >>>> + }, {
> >>>> + /* end of the table. */
> >>>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
> >>>> + },
> >>>> +};
> >>> Such information should be set in platform code, because it is specific
> >>> to your controller and most likely to a particular board design.
> >> I prefer to place it here.
> >>
> >> If I move the code to arch/arm/mach-mxs, it will make the arch/ much
> >> bigger.
> >> I have nearly 50 different nands information by hand, I will add it
> >> gradually in later patches.
> > This certainly makes the code bigger, but this is also the place where the
> > code belongs. Also, if you mark your structures with __initdata, such memory
> > can be freed later by the kernel, so I would rather go into that direction.
> >
> Please check the emails i talked with Lothar.
>
Maybe you should separate the database from the driver and build it as
a separate entity, so that other chip drivers can take advantage of it
and in the long run it might replace the current nand_ids database.
Lothar Waßmann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
@ 2011-03-25 6:48 ` Lothar Waßmann
0 siblings, 0 replies; 49+ messages in thread
From: Lothar Waßmann @ 2011-03-25 6:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Huang Shijie writes:
> Hi Florian:
>
>
> >>>> +#include "nand_device_info.h"
> >>>> +
> >>>> +static struct nand_device_info samsung_nand[] __initdata = {
> >>>> + {
> >>>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
> >>>> + .desc = "K9G8G08U0M, K9HAG08U1M",
> >>>> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
> >>>> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
> >>>> + }, {
> >>>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
> >>>> + .desc = "K9LBG08U0D",
> >>>> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
> >>>> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
> >>>> + }, {
> >>>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
> >>>> + .desc = "K9GAG08U0M",
> >>>> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
> >>>> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
> >>>> + }, {
> >>>> + /* end of the table. */
> >>>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
> >>>> + },
> >>>> +};
> >>> Such information should be set in platform code, because it is specific
> >>> to your controller and most likely to a particular board design.
> >> I prefer to place it here.
> >>
> >> If I move the code to arch/arm/mach-mxs, it will make the arch/ much
> >> bigger.
> >> I have nearly 50 different nands information by hand, I will add it
> >> gradually in later patches.
> > This certainly makes the code bigger, but this is also the place where the
> > code belongs. Also, if you mark your structures with __initdata, such memory
> > can be freed later by the kernel, so I would rather go into that direction.
> >
> Please check the emails i talked with Lothar.
>
Maybe you should separate the database from the driver and build it as
a separate entity, so that other chip drivers can take advantage of it
and in the long run it might replace the current nand_ids database.
Lothar Wa?mann
--
___________________________________________________________
Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996
www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 3/7] add the database for the NANDs
2011-03-25 6:48 ` Lothar Waßmann
@ 2011-03-25 6:59 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-25 6:59 UTC (permalink / raw)
To: Lothar Waßmann
Cc: linux, David.Woodhouse, linux-mtd, Florian Fainelli, dwmw2,
linux-arm-kernel
Hi:
> Hi,
>
> Huang Shijie writes:
>> Hi Florian:
>>
>>
>>>>>> +#include "nand_device_info.h"
>>>>>> +
>>>>>> +static struct nand_device_info samsung_nand[] __initdata = {
>>>>>> + {
>>>>>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
>>>>>> + .desc = "K9G8G08U0M, K9HAG08U1M",
>>>>>> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
>>>>>> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
>>>>>> + }, {
>>>>>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
>>>>>> + .desc = "K9LBG08U0D",
>>>>>> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
>>>>>> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
>>>>>> + }, {
>>>>>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
>>>>>> + .desc = "K9GAG08U0M",
>>>>>> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
>>>>>> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
>>>>>> + }, {
>>>>>> + /* end of the table. */
>>>>>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
>>>>>> + },
>>>>>> +};
>>>>> Such information should be set in platform code, because it is specific
>>>>> to your controller and most likely to a particular board design.
>>>> I prefer to place it here.
>>>>
>>>> If I move the code to arch/arm/mach-mxs, it will make the arch/ much
>>>> bigger.
>>>> I have nearly 50 different nands information by hand, I will add it
>>>> gradually in later patches.
>>> This certainly makes the code bigger, but this is also the place where the
>>> code belongs. Also, if you mark your structures with __initdata, such memory
>>> can be freed later by the kernel, so I would rather go into that direction.
>>>
>> Please check the emails i talked with Lothar.
>>
> Maybe you should separate the database from the driver and build it as
> a separate entity, so that other chip drivers can take advantage of it
> and in the long run it might replace the current nand_ids database.
>
ok. a good idea. I will try it.
Huang Shijie
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
@ 2011-03-25 6:59 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-25 6:59 UTC (permalink / raw)
To: linux-arm-kernel
Hi:
> Hi,
>
> Huang Shijie writes:
>> Hi Florian:
>>
>>
>>>>>> +#include "nand_device_info.h"
>>>>>> +
>>>>>> +static struct nand_device_info samsung_nand[] __initdata = {
>>>>>> + {
>>>>>> + .id = { 0xec, 0xd3, 0x14, 0x25, 0x64, 0xec, 0xd3, 0x14 },
>>>>>> + .desc = "K9G8G08U0M, K9HAG08U1M",
>>>>>> + .attr = ATTR(MLC, 1LL * SZ_1G, 128, 2 * SZ_1K + 64, 4, 512),
>>>>>> + .timing = TIMING(20, 15, 20, 6, -1, -1, -1),
>>>>>> + }, {
>>>>>> + .id = { 0xec, 0xd7, 0xd5, 0x29, 0x38, 0x41, 0xec, 0xd7 },
>>>>>> + .desc = "K9LBG08U0D",
>>>>>> + .attr = ATTR(MLC, 4LL * SZ_1G, 128, 4 * SZ_1K + 218, 8, 512),
>>>>>> + .timing = TIMING(20, 10, 25, 6, 20, 5, 15),
>>>>>> + }, {
>>>>>> + .id = { 0xec, 0xd5, 0x14, 0xb6, 0x74, 0xec, 0xd5, 0x14 },
>>>>>> + .desc = "K9GAG08U0M",
>>>>>> + .attr = ATTR(MLC, 2LL * SZ_1G, 128, 4 * SZ_1K + 218, 4, 512),
>>>>>> + .timing = TIMING(15, 10, 20, 6, -1, -1, -1),
>>>>>> + }, {
>>>>>> + /* end of the table. */
>>>>>> + .id = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
>>>>>> + },
>>>>>> +};
>>>>> Such information should be set in platform code, because it is specific
>>>>> to your controller and most likely to a particular board design.
>>>> I prefer to place it here.
>>>>
>>>> If I move the code to arch/arm/mach-mxs, it will make the arch/ much
>>>> bigger.
>>>> I have nearly 50 different nands information by hand, I will add it
>>>> gradually in later patches.
>>> This certainly makes the code bigger, but this is also the place where the
>>> code belongs. Also, if you mark your structures with __initdata, such memory
>>> can be freed later by the kernel, so I would rather go into that direction.
>>>
>> Please check the emails i talked with Lothar.
>>
> Maybe you should separate the database from the driver and build it as
> a separate entity, so that other chip drivers can take advantage of it
> and in the long run it might replace the current nand_ids database.
>
ok. a good idea. I will try it.
Huang Shijie
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 7/7] MTD : add GPMI driver in the config and Makefile
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-31 9:44 ` Artem Bityutskiy
-1 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:44 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> +config MTD_NAND_GPMI_NFC
> + bool "GPMI NAND Flash Controller driver"
> + depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28)
> + select MTD_PARTITIONS
> + help
> + Enables NAND Flash support for IMX23 or IMX28.
> + The GPMI controller is very powerful, with the help of BCH
> + module, it can do the hardware ECC. The GPMI supports several
> + NAND flashs at the same time.
Please, fix the indentation here. Look at other entries in this file and
format the same way. Also, a bit write more text. Use word "freescale"
somewhere.
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 7/7] MTD : add GPMI driver in the config and Makefile
@ 2011-03-31 9:44 ` Artem Bityutskiy
0 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:44 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> +config MTD_NAND_GPMI_NFC
> + bool "GPMI NAND Flash Controller driver"
> + depends on MTD_NAND && (SOC_IMX23 || SOC_IMX28)
> + select MTD_PARTITIONS
> + help
> + Enables NAND Flash support for IMX23 or IMX28.
> + The GPMI controller is very powerful, with the help of BCH
> + module, it can do the hardware ECC. The GPMI supports several
> + NAND flashs at the same time.
Please, fix the indentation here. Look at other entries in this file and
format the same way. Also, a bit write more text. Use word "freescale"
somewhere.
--
Best Regards,
Artem Bityutskiy (????? ????????)
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 5/7] add GPMI support for imx28
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-31 9:47 ` Artem Bityutskiy
-1 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:47 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> +#define BF_BCH_CTRL_RSVD5(v) \
> + (((v) << 23) & BM_BCH_CTRL_RSVD5)
Many lines where you used "\" fit 80 lines. Just do not use tabs between
name and value (which is ugly, imo), use a space and then it fits 80
lines. This neater than splitting things on 2 lines.
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 5/7] add GPMI support for imx28
@ 2011-03-31 9:47 ` Artem Bityutskiy
0 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:47 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> +#define BF_BCH_CTRL_RSVD5(v) \
> + (((v) << 23) & BM_BCH_CTRL_RSVD5)
Many lines where you used "\" fit 80 lines. Just do not use tabs between
name and value (which is ugly, imo), use a space and then it fits 80
lines. This neater than splitting things on 2 lines.
--
Best Regards,
Artem Bityutskiy (????? ????????)
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 5/7] add GPMI support for imx28
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-31 9:49 ` Artem Bityutskiy
-1 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:49 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> + pio[0] =
> + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
> + BM_GPMI_CTRL0_WORD_LENGTH |
> + BF_GPMI_CTRL0_CS(mil->current_chip) |
> + BF_GPMI_CTRL0_ADDRESS(address) |
> + BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
Strange way to format the code ...
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 5/7] add GPMI support for imx28
@ 2011-03-31 9:49 ` Artem Bityutskiy
0 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:49 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> + pio[0] =
> + BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
> + BM_GPMI_CTRL0_WORD_LENGTH |
> + BF_GPMI_CTRL0_CS(mil->current_chip) |
> + BF_GPMI_CTRL0_ADDRESS(address) |
> + BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
Strange way to format the code ...
--
Best Regards,
Artem Bityutskiy (????? ????????)
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 5/7] add GPMI support for imx28
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-31 9:49 ` Artem Bityutskiy
-1 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:49 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> + .description = "Single-chip boot area, "
> + "block mark swapping
> supported",
Because you love tabs so much, you have to do this strange splitting of
strings. Just use normal spaces and you'll fit many things in one line.
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 5/7] add GPMI support for imx28
@ 2011-03-31 9:49 ` Artem Bityutskiy
0 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:49 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> + .description = "Single-chip boot area, "
> + "block mark swapping
> supported",
Because you love tabs so much, you have to do this strange splitting of
strings. Just use normal spaces and you'll fit many things in one line.
--
Best Regards,
Artem Bityutskiy (????? ????????)
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 3/7] add the database for the NANDs
2011-03-16 1:55 ` Huang Shijie
@ 2011-03-31 9:54 ` Artem Bityutskiy
-1 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:54 UTC (permalink / raw)
To: Huang Shijie; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> This is a database for the NANDs which is now supported by imx23 and imx28.
>
> Signed-off-by: Huang Shijie <b32955@freescale.com>
I agree GPMI is a great and powerful controller. But it is not the only
cotroller out there, and we obviously should not have NAND device data
bases for each nice NAND controller, righ? So we obviously have to have
only one single data-base.
--
Best Regards,
Artem Bityutskiy (Артём Битюцкий)
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
@ 2011-03-31 9:54 ` Artem Bityutskiy
0 siblings, 0 replies; 49+ messages in thread
From: Artem Bityutskiy @ 2011-03-31 9:54 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
> This is a database for the NANDs which is now supported by imx23 and imx28.
>
> Signed-off-by: Huang Shijie <b32955@freescale.com>
I agree GPMI is a great and powerful controller. But it is not the only
cotroller out there, and we obviously should not have NAND device data
bases for each nice NAND controller, righ? So we obviously have to have
only one single data-base.
--
Best Regards,
Artem Bityutskiy (????? ????????)
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 5/7] add GPMI support for imx28
2011-03-31 9:47 ` Artem Bityutskiy
@ 2011-03-31 10:09 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-31 10:09 UTC (permalink / raw)
To: dedekind1; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
Hi:
> On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
>> +#define BF_BCH_CTRL_RSVD5(v) \
>> + (((v)<< 23)& BM_BCH_CTRL_RSVD5)
> Many lines where you used "\" fit 80 lines. Just do not use tabs between
> name and value (which is ugly, imo), use a space and then it fits 80
> lines. This neater than splitting things on 2 lines.
>
Please check the latest version of the driver.
The code has been remove in new version.
Best Regards
Huang Shijie
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 5/7] add GPMI support for imx28
@ 2011-03-31 10:09 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-31 10:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi:
> On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
>> +#define BF_BCH_CTRL_RSVD5(v) \
>> + (((v)<< 23)& BM_BCH_CTRL_RSVD5)
> Many lines where you used "\" fit 80 lines. Just do not use tabs between
> name and value (which is ugly, imo), use a space and then it fits 80
> lines. This neater than splitting things on 2 lines.
>
Please check the latest version of the driver.
The code has been remove in new version.
Best Regards
Huang Shijie
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 3/7] add the database for the NANDs
2011-03-31 9:54 ` Artem Bityutskiy
@ 2011-03-31 10:09 ` Huang Shijie
-1 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-31 10:09 UTC (permalink / raw)
To: dedekind1; +Cc: linux-mtd, linux, dwmw2, linux-arm-kernel, David.Woodhouse
hi:
> On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
>> This is a database for the NANDs which is now supported by imx23 and imx28.
>>
>> Signed-off-by: Huang Shijie<b32955@freescale.com>
> I agree GPMI is a great and powerful controller. But it is not the only
> cotroller out there, and we obviously should not have NAND device data
> bases for each nice NAND controller, righ? So we obviously have to have
> only one single data-base.
>
Please check the latest driver.
thanks.
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 3/7] add the database for the NANDs
@ 2011-03-31 10:09 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-31 10:09 UTC (permalink / raw)
To: linux-arm-kernel
hi:
> On Wed, 2011-03-16 at 09:55 +0800, Huang Shijie wrote:
>> This is a database for the NANDs which is now supported by imx23 and imx28.
>>
>> Signed-off-by: Huang Shijie<b32955@freescale.com>
> I agree GPMI is a great and powerful controller. But it is not the only
> cotroller out there, and we obviously should not have NAND device data
> bases for each nice NAND controller, righ? So we obviously have to have
> only one single data-base.
>
Please check the latest driver.
thanks.
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 4/7] add GPMI support for imx23
@ 2011-07-08 16:42 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-07-08 16:42 UTC (permalink / raw)
To: linux-arm-kernel
These files contain the code to implement the GPMI in the imx23.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h | 550 ++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h | 416 ++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-imx23.c | 556 +++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/rom-imx23.c | 300 +++++++++++++++
4 files changed, 1822 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx23.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx23.c
diff --git a/drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
new file mode 100644
index 0000000..9af4feb
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
@@ -0,0 +1,550 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL (0x00000000)
+#define HW_BCH_CTRL_SET (0x00000004)
+#define HW_BCH_CTRL_CLR (0x00000008)
+#define HW_BCH_CTRL_TOG (0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST 0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN 0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE 0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN 0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5 23
+#define BM_BCH_CTRL_RSVD5 0x3F800000
+#define BF_BCH_CTRL_RSVD5(v) (((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000
+#define BP_BCH_CTRL_RSVD4 20
+#define BM_BCH_CTRL_RSVD4 0x00300000
+#define BF_BCH_CTRL_RSVD4(v) (((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT 18
+#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE 0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE 0x00010000
+#define BP_BCH_CTRL_RSVD3 11
+#define BM_BCH_CTRL_RSVD3 0x0000F800
+#define BF_BCH_CTRL_RSVD3(v) (((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400
+#define BM_BCH_CTRL_RSVD2 0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
+#define BP_BCH_CTRL_RSVD1 4
+#define BM_BCH_CTRL_RSVD1 0x000000F0
+#define BF_BCH_CTRL_RSVD1(v) (((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004
+#define BM_BCH_CTRL_RSVD0 0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0 (0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE 20
+#define BM_BCH_STATUS0_HANDLE 0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+ (((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE 16
+#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v) \
+ (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0 8
+#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v) \
+ (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF
+#define BP_BCH_STATUS0_RSVD1 5
+#define BM_BCH_STATUS0_RSVD1 0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v) \
+ (((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES 0x00000010
+#define BM_BCH_STATUS0_CORRECTED 0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
+#define BP_BCH_STATUS0_RSVD0 0
+#define BM_BCH_STATUS0_RSVD0 0x00000003
+#define BF_BCH_STATUS0_RSVD0(v) \
+ (((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE (0x00000020)
+
+#define BP_BCH_MODE_RSVD 8
+#define BM_BCH_MODE_RSVD 0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+ (((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD 0
+#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v) \
+ (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR (0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR 0
+#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR (0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR 0
+#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR (0x00000050)
+
+#define BP_BCH_METAPTR_ADDR 0
+#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT (0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+ (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \
+ (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \
+ (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \
+ (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \
+ (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \
+ (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \
+ (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \
+ (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \
+ (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \
+ (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \
+ (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \
+ (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \
+ (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \
+ (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \
+ (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \
+ (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0 (0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0 12
+#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1 (0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN 12
+#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0 (0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0 12
+#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1 (0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN 12
+#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0 (0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0 12
+#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1 (0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN 12
+#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0 (0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0 12
+#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1 (0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN 12
+#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0 (0x00000100)
+#define HW_BCH_DEBUG0_SET (0x00000104)
+#define HW_BCH_DEBUG0_CLR (0x00000108)
+#define HW_BCH_DEBUG0_TOG (0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1 27
+#define BM_BCH_DEBUG0_RSVD1 0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+ (((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \
+ (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0 6
+#define BM_BCH_DEBUG0_RSVD0 0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v) \
+ (((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \
+ (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD (0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES 0
+#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD (0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES 0
+#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD (0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES 0
+#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD (0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES 0
+#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME (0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME 0
+#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION (0x00000160)
+
+#define BP_BCH_VERSION_MAJOR 24
+#define BM_BCH_VERSION_MAJOR 0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR 16
+#define BM_BCH_VERSION_MINOR 0x00FF0000
+#define BF_BCH_VERSION_MINOR(v) \
+ (((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP 0
+#define BM_BCH_VERSION_STEP 0x0000FFFF
+#define BF_BCH_VERSION_STEP(v) \
+ (((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
new file mode 100644
index 0000000..2f9fce6
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
@@ -0,0 +1,416 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0 (0x00000000)
+#define HW_GPMI_CTRL0_SET (0x00000004)
+#define HW_GPMI_CTRL0_CLR (0x00000008)
+#define HW_GPMI_CTRL0_TOG (0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST 0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN 0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
+#define BM_GPMI_CTRL0_CLKGATE 0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_GPMI_CTRL0_RUN 0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE 0x0
+#define BV_GPMI_CTRL0_RUN__BUSY 0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x08000000
+#define BM_GPMI_CTRL0_UDMA 0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE 24
+#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
+ (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
+#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1
+#define BP_GPMI_CTRL0_CS 20
+#define BM_GPMI_CTRL0_CS 0x00300000
+#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS 17
+#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
+#define BP_GPMI_CTRL0_XFER_COUNT 0
+#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v) \
+ (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE (0x00000010)
+
+#define BP_GPMI_COMPARE_MASK 16
+#define BM_GPMI_COMPARE_MASK 0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE 0
+#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v) \
+ (((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL (0x00000020)
+#define HW_GPMI_ECCCTRL_SET (0x00000024)
+#define HW_GPMI_ECCCTRL_CLR (0x00000028)
+#define HW_GPMI_ECCCTRL_TOG (0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE 16
+#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2 0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD 13
+#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
+#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+#define BP_GPMI_ECCCTRL_RSVD1 9
+#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v) (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \
+ (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x080
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x040
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x020
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x010
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x008
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x004
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x002
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x001
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT (0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2 16
+#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v) (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT 0
+#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD (0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS 2
+#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0 0
+#define BM_GPMI_PAYLOAD_RSVD0 0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v) (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY (0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS 2
+#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+ (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0 0
+#define BM_GPMI_AUXILIARY_RSVD0 0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v) (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1 (0x00000060)
+#define HW_GPMI_CTRL1_SET (0x00000064)
+#define HW_GPMI_CTRL1_CLR (0x00000068)
+#define HW_GPMI_CTRL1_TOG (0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2 24
+#define BM_GPMI_CTRL1_RSVD2 0xFF000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+ (((v) << 24) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_CE3_SEL 0x00800000
+#define BM_GPMI_CTRL1_CE2_SEL 0x00400000
+#define BM_GPMI_CTRL1_CE1_SEL 0x00200000
+#define BM_GPMI_CTRL1_CE0_SEL 0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BP_GPMI_CTRL1_GPMI_MODE 0
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE 17
+#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD 16
+#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v) \
+ (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_BURST_EN 0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x00000080
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x00000040
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x00000020
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x00000010
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0 (0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1 24
+#define BM_GPMI_TIMING0_RSVD1 0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+ (((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
+ (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD 8
+#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP 0
+#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1 (0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+ (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1 0
+#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v) \
+ (((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2 (0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP 24
+#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+ (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV 16
+#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v) \
+ (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD 8
+#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP 0
+#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA (0x000000a0)
+
+#define BP_GPMI_DATA_DATA 0
+#define BM_GPMI_DATA_DATA 0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v) (v)
+
+/*============================================================================*/
+
+#define HW_GPMI_STAT (0x000000b0)
+
+#define BM_GPMI_STAT_PRESENT 0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1
+#define BP_GPMI_STAT_RSVD1 12
+#define BM_GPMI_STAT_RSVD1 0x7FFFF000
+#define BF_GPMI_STAT_RSVD1(v) \
+ (((v) << 12) & BM_GPMI_STAT_RSVD1)
+#define BP_GPMI_STAT_RDY_TIMEOUT 8
+#define BM_GPMI_STAT_RDY_TIMEOUT 0x00000F00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v) \
+ (((v) << 8) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_ATA_IRQ 0x00000080
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000040
+#define BM_GPMI_STAT_FIFO_EMPTY 0x00000020
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1
+#define BM_GPMI_STAT_FIFO_FULL 0x00000010
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1
+#define BM_GPMI_STAT_DEV3_ERROR 0x00000008
+#define BM_GPMI_STAT_DEV2_ERROR 0x00000004
+#define BM_GPMI_STAT_DEV1_ERROR 0x00000002
+#define BM_GPMI_STAT_DEERROR 0x00000001
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG (0x000000c0)
+
+#define BM_GPMI_DEBUG_READY3 0x80000000
+#define BM_GPMI_DEBUG_READY2 0x40000000
+#define BM_GPMI_DEBUG_READY1 0x20000000
+#define BM_GPMI_DEBUG_READY0 0x10000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x08000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x04000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x02000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x01000000
+#define BM_GPMI_DEBUG_SENSE3 0x00800000
+#define BM_GPMI_DEBUG_SENSE2 0x00400000
+#define BM_GPMI_DEBUG_SENSE1 0x00200000
+#define BM_GPMI_DEBUG_SENSE0 0x00100000
+#define BM_GPMI_DEBUG_DMAREQ3 0x00080000
+#define BM_GPMI_DEBUG_DMAREQ2 0x00040000
+#define BM_GPMI_DEBUG_DMAREQ1 0x00020000
+#define BM_GPMI_DEBUG_DMAREQ0 0x00010000
+#define BP_GPMI_DEBUG_CMD_END 12
+#define BM_GPMI_DEBUG_CMD_END 0x0000F000
+#define BF_GPMI_DEBUG_CMD_END(v) \
+ (((v) << 12) & BM_GPMI_DEBUG_CMD_END)
+#define BP_GPMI_DEBUG_UDMA_STATE 8
+#define BM_GPMI_DEBUG_UDMA_STATE 0x00000F00
+#define BF_GPMI_DEBUG_UDMA_STATE(v) \
+ (((v) << 8) & BM_GPMI_DEBUG_UDMA_STATE)
+#define BM_GPMI_DEBUG_BUSY 0x00000080
+#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED 0x1
+#define BP_GPMI_DEBUG_PIN_STATE 4
+#define BM_GPMI_DEBUG_PIN_STATE 0x00000070
+#define BF_GPMI_DEBUG_PIN_STATE(v) \
+ (((v) << 4) & BM_GPMI_DEBUG_PIN_STATE)
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7
+#define BP_GPMI_DEBUG_MAIN_STATE 0
+#define BM_GPMI_DEBUG_MAIN_STATE 0x0000000F
+#define BF_GPMI_DEBUG_MAIN_STATE(v) \
+ (((v) << 0) & BM_GPMI_DEBUG_MAIN_STATE)
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xA
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION (0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR 24
+#define BM_GPMI_VERSION_MAJOR 0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR 16
+#define BM_GPMI_VERSION_MINOR 0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP 0
+#define BM_GPMI_VERSION_STEP 0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v) (((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2 (0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1 16
+#define BM_GPMI_DEBUG2_RSVD1 0xFFFF0000
+#define BF_GPMI_DEBUG2_RSVD1(v) (((v) << 16) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \
+ (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP 0
+#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3 (0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+ (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \
+ (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/hal-imx23.c b/drivers/mtd/nand/gpmi-nfc/hal-imx23.c
new file mode 100644
index 0000000..155ad67
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/hal-imx23.c
@@ -0,0 +1,556 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+#include "gpmi-regs-imx23.h"
+#include "bch-regs-imx23.h"
+
+static int init_hal_imx23(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ /* Enable the clock */
+ clk_enable(resources->clock);
+
+ /* Reset the GPMI block. */
+ mxs_reset_block(resources->gpmi_regs);
+
+ /* Choose NAND mode. */
+ __raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Set the IRQ polarity. */
+ __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable write protection. */
+ __raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Select BCH ECC. */
+ __raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable the clock. */
+ clk_disable(resources->clock);
+ return 0;
+}
+
+/* Configures the NFC geometry for BCH. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_geometry *nfc = &this->nfc_geometry;
+ unsigned int block_count;
+ unsigned int block_size;
+ unsigned int metadata_size;
+ unsigned int ecc_strength;
+ unsigned int page_size;
+
+ if (common_nfc_set_geometry(this))
+ return !0;
+
+ block_count = nfc->ecc_chunk_count - 1;
+ block_size = nfc->ecc_chunk_size_in_bytes;
+ metadata_size = nfc->metadata_size_in_bytes;
+ ecc_strength = nfc->ecc_strength >> 1;
+ page_size = nfc->page_size_in_bytes;
+
+ clk_enable(resources->clock);
+
+ /*
+ * Reset the BCH block. Notice that we pass in true for the just_enable
+ * flag. This is because the soft reset for the version 0 BCH block
+ * doesn't work. If you try to soft reset the BCH block, it becomes
+ * unusable until the next hard reset.
+ */
+ mxs_reset_block(resources->bch_regs);
+
+ /* Configure layout 0. */
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) |
+ BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+ BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) |
+ BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+ /* Set *all* chip selects to use layout 0. */
+ __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+ /* Enable interrupts. */
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+ resources->bch_regs + HW_BCH_CTRL_SET);
+
+ clk_disable(resources->clock);
+ return 0;
+}
+
+static int set_timing(struct gpmi_nfc_data *this,
+ const struct nand_timing *timing)
+{
+ struct nfc_hal *nfc = this->nfc;
+
+ nfc->timing = *timing;
+ return 0;
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this: Per-device data.
+ * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
+ * I/O transaction. If no I/O transaction is in
+ * progress, this is the clock frequency during the
+ * most recent I/O transaction.
+ * @hardware_timing: The hardware timing configuration in effect during
+ * the current I/O transaction. If no I/O transaction
+ * is in progress, this is the hardware timing
+ * configuration during the most recent I/O
+ * transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+ unsigned long *clock_frequency_in_hz,
+ struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ uint32_t register_image;
+
+ /* Return the clock frequency. */
+ *clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+ /* We'll be reading the hardware, so let's enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Retrieve the hardware timing. */
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+ hardware_timing->data_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+ BP_GPMI_TIMING0_DATA_SETUP;
+
+ hardware_timing->data_hold_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+ BP_GPMI_TIMING0_DATA_HOLD;
+
+ hardware_timing->address_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+ BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+ hardware_timing->use_half_periods =
+ (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+ BP_GPMI_CTRL1_HALF_PERIOD;
+
+ hardware_timing->sample_delay_factor =
+ (register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+ BP_GPMI_CTRL1_RDN_DELAY;
+
+ /* We're done reading the hardware, so disable the clock. */
+ clk_disable(resources->clock);
+}
+
+static void exit(struct gpmi_nfc_data *this)
+{
+}
+
+/* Begin the I/O */
+static void begin(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ struct gpmi_nfc_hardware_timing hw;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ unsigned int clock_period_in_ns;
+ uint32_t register_image;
+ unsigned int dll_wait_time_in_us;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Get the timing information we need. */
+ nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
+ clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
+
+ gpmi_nfc_compute_hardware_timing(this, &hw);
+
+ /* Set up all the simple timing parameters. */
+ register_image =
+ BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
+ BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
+ BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
+
+ __raw_writel(register_image, gpmi_regs + HW_GPMI_TIMING0);
+
+ /*
+ * HEY - PAY ATTENTION!
+ *
+ * DLL_ENABLE must be set to zero when setting RDN_DELAY or HALF_PERIOD.
+ */
+ __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Clear out the DLL control fields. */
+ __raw_writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR);
+ __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* If no sample delay is called for, return immediately. */
+ if (!hw.sample_delay_factor)
+ return;
+
+ /* Configure the HALF_PERIOD flag. */
+
+ if (hw.use_half_periods)
+ __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD,
+ gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Set the delay factor. */
+ __raw_writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
+ gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Enable the DLL. */
+ __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /*
+ * After we enable the GPMI DLL, we have to wait 64 clock cycles before
+ * we can use the GPMI.
+ *
+ * Calculate the amount of time we need to wait, in microseconds.
+ */
+ dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
+
+ if (!dll_wait_time_in_us)
+ dll_wait_time_in_us = 1;
+
+ /* Wait for the DLL to settle. */
+ udelay(dll_wait_time_in_us);
+}
+
+static void end(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ clk_disable(resources->clock);
+}
+
+/* Clears a BCH interrupt. */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+ struct resources *r = &this->resources;
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
+}
+
+/* Returns the Ready/Busy status of the given chip. */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+ struct resources *resources = &this->resources;
+ uint32_t mask;
+ uint32_t register_image;
+
+ mask = BM_GPMI_DEBUG_READY0 << chip;
+ register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_DEBUG);
+ return !!(register_image & mask);
+}
+
+static int send_command(struct gpmi_nfc_data *this)
+{
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ struct dma_async_tx_descriptor *desc;
+ struct scatterlist *sgl;
+ u32 pio[3];
+
+ /* [1] send out the PIO words */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
+ | BM_GPMI_CTRL0_ADDRESS_INCREMENT
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->command_length);
+ pio[1] = pio[2] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
+ sgl = &mil->cmd_sgl;
+
+ dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
+ sgl->length = mil->command_length;
+ desc = channel->device->device_prep_slave_sg(channel,
+ sgl, 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("error");
+ return -1;
+ }
+
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_COMMAND;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ uint32_t command_mode;
+ uint32_t address;
+ u32 pio[2];
+
+ log();
+ /* [1] PIO */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(mil->current_chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* step 2 : send DMA request */
+ prepare_data_dma(this, DMA_TO_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ /* [2] submit the DMA */
+ this->dma_type = DMA_FOR_WRITE_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int read_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ u32 pio[2];
+
+ /* step 1 : send PIO */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* step 2 : send DMA request */
+ prepare_data_dma(this, DMA_FROM_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_FROM_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_READ_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* A DMA descriptor that does an ECC page read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+ BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(0) ;
+ pio[1] = 0;
+ pio[2] =
+ BM_GPMI_ECCCTRL_ENABLE_ECC |
+ BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) |
+ BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ this->dma_type = DMA_FOR_WRITE_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+static int read_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* [1] Wait for the chip to report ready. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(0);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] Enable the BCH block and read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
+ | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes);
+
+ pio[1] = 0;
+ pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
+ | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
+ | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] Disable the BCH block */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes) ;
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 1);
+ if (!desc) {
+ log("step 3 error");
+ return -1;
+ }
+
+ /* [4] submit the DMA */
+ this->dma_type = DMA_FOR_READ_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+/* The NFC HAL for IMX23 */
+struct nfc_hal gpmi_nfc_hal_imx23 = {
+ .version = 0,
+ .description = "4-chip GPMI and BCH for IMX23",
+ .max_chip_count = 4,
+ .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
+ BP_GPMI_TIMING0_DATA_SETUP),
+ .internal_data_setup_in_ns = 0,
+ .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
+ BP_GPMI_CTRL1_RDN_DELAY),
+ .max_dll_clock_period_in_ns = 32,
+ .max_dll_delay_in_ns = 16,
+ .init = init_hal_imx23,
+ .set_geometry = set_geometry,
+ .set_timing = set_timing,
+ .get_timing = get_timing,
+ .exit = exit,
+ .begin = begin,
+ .end = end,
+ .clear_bch = clear_bch,
+ .is_ready = is_ready,
+ .send_command = send_command,
+ .read_data = read_data,
+ .send_data = send_data,
+ .read_page = read_page,
+ .send_page = send_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-imx23.c b/drivers/mtd/nand/gpmi-nfc/rom-imx23.c
new file mode 100644
index 0000000..8193874
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-imx23.c
@@ -0,0 +1,300 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+/* Useful variables for Boot ROM Helper version 0. */
+static const char *fingerprint = "STMP";
+
+/* Sets geometry for the Boot ROM Helper. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+ struct nand_chip *nand = &this->mil.nand;
+ int error;
+
+ error = gpmi_nfc_rom_helper_set_geometry(this);
+ if (error)
+ return error;
+
+ if (!pdata->boot_area_size_in_bytes) {
+ geometry->boot_area_count = 0;
+ geometry->boot_area_size_in_bytes = 0;
+ return 0;
+ }
+
+ if (nand->numchips == 1) {
+ geometry->boot_area_count = 1;
+ geometry->boot_area_size_in_bytes =
+ pdata->boot_area_size_in_bytes * 2;
+ } else {
+ geometry->boot_area_count = 2;
+ geometry->boot_area_size_in_bytes =
+ pdata->boot_area_size_in_bytes;
+ }
+ return 0;
+}
+
+static int check_transcription_stamp(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom_geo = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ unsigned int search_area_size_in_strides;
+ unsigned int stride;
+ unsigned int page;
+ loff_t byte;
+ uint8_t *buffer = nand->buffers->databuf;
+ int saved_chip_number;
+ int found_an_ncb_fingerprint = false;
+
+ /* Compute the number of strides in a search area. */
+ search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+
+ /* Select chip 0. */
+ saved_chip_number = mil->current_chip;
+ nand->select_chip(mtd, 0);
+
+ /*
+ * Loop through the first search area, looking for the NCB fingerprint.
+ */
+ pr_info("Scanning for an NCB fingerprint...\n");
+
+ for (stride = 0; stride < search_area_size_in_strides; stride++) {
+ /* Compute the page and byte addresses. */
+ page = stride * rom_geo->stride_size_in_pages;
+ byte = page * mtd->writesize;
+
+ pr_info(" Looking for a fingerprint in page 0x%x\n", page);
+
+ /*
+ * Read the NCB fingerprint. The fingerprint is four bytes long
+ * and starts in the 12th byte of the page.
+ */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, 12, page);
+ nand->read_buf(mtd, buffer, strlen(fingerprint));
+
+ /* Look for the fingerprint. */
+ if (!memcmp(buffer, fingerprint, strlen(fingerprint))) {
+ found_an_ncb_fingerprint = true;
+ break;
+ }
+
+ }
+
+ /* Deselect chip 0. */
+ nand->select_chip(mtd, saved_chip_number);
+
+ if (found_an_ncb_fingerprint)
+ pr_info(" Found a fingerprint\n");
+ else
+ pr_info(" No fingerprint found\n");
+ return found_an_ncb_fingerprint;
+}
+
+/* Writes a transcription stamp. */
+static int write_transcription_stamp(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct boot_rom_geometry *rom_geo = &this->rom_geometry;
+ struct nand_device_info *info = &this->device_info;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ unsigned int block_size_in_pages;
+ unsigned int search_area_size_in_strides;
+ unsigned int search_area_size_in_pages;
+ unsigned int search_area_size_in_blocks;
+ unsigned int block;
+ unsigned int stride;
+ unsigned int page;
+ loff_t byte;
+ uint8_t *buffer = nand->buffers->databuf;
+ int saved_chip_number;
+ int status;
+
+ /* Compute the search area geometry. */
+ block_size_in_pages = info->attr.block_size_in_pages;
+ search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+ search_area_size_in_pages = search_area_size_in_strides *
+ rom_geo->stride_size_in_pages;
+ search_area_size_in_blocks =
+ (search_area_size_in_pages + (block_size_in_pages - 1)) /
+ block_size_in_pages;
+
+ pr_info("-------------------------------------------\n");
+ pr_info("Search Area Geometry\n");
+ pr_info("-------------------------------------------\n");
+ pr_info("Search Area Size in Blocks : %u", search_area_size_in_blocks);
+ pr_info("Search Area Size in Strides: %u", search_area_size_in_strides);
+ pr_info("Search Area Size in Pages : %u", search_area_size_in_pages);
+
+ /* Select chip 0. */
+ saved_chip_number = mil->current_chip;
+ nand->select_chip(mtd, 0);
+
+ /* Loop over blocks in the first search area, erasing them. */
+ pr_info("Erasing the search area...\n");
+
+ for (block = 0; block < search_area_size_in_blocks; block++) {
+ /* Compute the page address. */
+ page = block * block_size_in_pages;
+
+ /* Erase this block. */
+ pr_info(" Erasing block 0x%x\n", block);
+ nand->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+ nand->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+
+ /* Wait for the erase to finish. */
+ status = nand->waitfunc(mtd, nand);
+ if (status & NAND_STATUS_FAIL)
+ dev_err(dev, "[%s] Erase failed.\n", __func__);
+ }
+
+ /* Write the NCB fingerprint into the page buffer. */
+ memset(buffer, ~0, mtd->writesize);
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+ memcpy(buffer + 12, fingerprint, strlen(fingerprint));
+
+ /* Loop through the first search area, writing NCB fingerprints. */
+ pr_info("Writing NCB fingerprints...\n");
+ for (stride = 0; stride < search_area_size_in_strides; stride++) {
+ /* Compute the page and byte addresses. */
+ page = stride * rom_geo->stride_size_in_pages;
+ byte = page * mtd->writesize;
+
+ /* Write the first page of the current stride. */
+ pr_info(" Writing an NCB fingerprint in page 0x%x\n", page);
+ nand->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+ nand->ecc.write_page_raw(mtd, nand, buffer);
+ nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ /* Wait for the write to finish. */
+ status = nand->waitfunc(mtd, nand);
+ if (status & NAND_STATUS_FAIL)
+ dev_err(dev, "[%s] Write failed.\n", __func__);
+ }
+
+ /* Deselect chip 0. */
+ nand->select_chip(mtd, saved_chip_number);
+ return 0;
+}
+
+static int imx23_rom_extra_init(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+ struct nand_chip *nand = &mil->nand;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_device_info *info = &this->device_info;
+ unsigned int block_count;
+ unsigned int block;
+ int chip;
+ int page;
+ loff_t byte;
+ uint8_t block_mark;
+ int error = 0;
+
+ /*
+ * If control arrives here, we can't use block mark swapping, which
+ * means we're forced to use transcription. First, scan for the
+ * transcription stamp. If we find it, then we don't have to do
+ * anything -- the block marks are already transcribed.
+ */
+ if (check_transcription_stamp(this))
+ return 0;
+
+ /*
+ * If control arrives here, we couldn't find a transcription stamp, so
+ * so we presume the block marks are in the conventional location.
+ */
+ pr_info("Transcribing bad block marks...\n");
+
+ /* Compute the number of blocks in the entire medium. */
+ block_count = info->attr.chip_size_in_bytes >> nand->phys_erase_shift;
+
+ /*
+ * Loop over all the blocks in the medium, transcribing block marks as
+ * we go.
+ */
+ for (block = 0; block < block_count; block++) {
+ /*
+ * Compute the chip, page and byte addresses for this block's
+ * conventional mark.
+ */
+ chip = block >> (nand->chip_shift - nand->phys_erase_shift);
+ page = block << (nand->phys_erase_shift - nand->page_shift);
+ byte = block << nand->phys_erase_shift;
+
+ /* Select the chip. */
+ nand->select_chip(mtd, chip);
+
+ /* Send the command to read the conventional block mark. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+
+ /* Read the conventional block mark. */
+ block_mark = nand->read_byte(mtd);
+
+ /*
+ * Check if the block is marked bad. If so, we need to mark it
+ * again, but this time the result will be a mark in the
+ * location where we transcribe block marks.
+ *
+ * Notice that we have to explicitly set the marking_a_bad_block
+ * member before we call through the block_markbad function
+ * pointer in the owning struct nand_chip. If we could call
+ * though the block_markbad function pointer in the owning
+ * struct mtd_info, which we have hooked, then this would be
+ * taken care of for us. Unfortunately, we can't because that
+ * higher-level code path will do things like consulting the
+ * in-memory bad block table -- which doesn't even exist yet!
+ * So, we have to call at a lower level and handle some details
+ * ourselves.
+ */
+ if (block_mark != 0xff) {
+ pr_info("Transcribing mark in block %u\n", block);
+ mil->marking_a_bad_block = true;
+ error = nand->block_markbad(mtd, byte);
+ mil->marking_a_bad_block = false;
+ if (error)
+ dev_err(dev, "Failed to mark block bad with "
+ "error %d\n", error);
+ }
+
+ /* Deselect the chip. */
+ nand->select_chip(mtd, -1);
+ }
+
+ /* Write the stamp that indicates we've transcribed the block marks. */
+ write_transcription_stamp(this);
+ return 0;
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+struct boot_rom_helper gpmi_nfc_boot_rom_imx23 = {
+ .version = 0,
+ .description = "Single/dual-chip boot area, "
+ "no block mark swapping",
+ .swap_block_mark = false,
+ .set_geometry = set_geometry,
+ .rom_extra_init = imx23_rom_extra_init,
+};
--
1.7.0.4
______________________________________________________
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^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 4/7] add GPMI support for imx23
2011-03-16 1:42 Huang Shijie
@ 2011-03-16 1:42 ` Huang Shijie
0 siblings, 0 replies; 49+ messages in thread
From: Huang Shijie @ 2011-03-16 1:42 UTC (permalink / raw)
To: linux-arm-kernel
These files contain the code to implement the GPMI in the imx23.
Signed-off-by: Huang Shijie <b32955@freescale.com>
---
drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h | 550 ++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h | 416 ++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/hal-imx23.c | 556 +++++++++++++++++++++++++++
drivers/mtd/nand/gpmi-nfc/rom-imx23.c | 300 +++++++++++++++
4 files changed, 1822 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
create mode 100644 drivers/mtd/nand/gpmi-nfc/hal-imx23.c
create mode 100644 drivers/mtd/nand/gpmi-nfc/rom-imx23.c
diff --git a/drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
new file mode 100644
index 0000000..9af4feb
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/bch-regs-imx23.h
@@ -0,0 +1,550 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_BCH_REGS_H
+#define __GPMI_NFC_BCH_REGS_H
+
+/*============================================================================*/
+
+#define HW_BCH_CTRL (0x00000000)
+#define HW_BCH_CTRL_SET (0x00000004)
+#define HW_BCH_CTRL_CLR (0x00000008)
+#define HW_BCH_CTRL_TOG (0x0000000c)
+
+#define BM_BCH_CTRL_SFTRST 0x80000000
+#define BV_BCH_CTRL_SFTRST__RUN 0x0
+#define BV_BCH_CTRL_SFTRST__RESET 0x1
+#define BM_BCH_CTRL_CLKGATE 0x40000000
+#define BV_BCH_CTRL_CLKGATE__RUN 0x0
+#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1
+#define BP_BCH_CTRL_RSVD5 23
+#define BM_BCH_CTRL_RSVD5 0x3F800000
+#define BF_BCH_CTRL_RSVD5(v) (((v) << 23) & BM_BCH_CTRL_RSVD5)
+#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000
+#define BP_BCH_CTRL_RSVD4 20
+#define BM_BCH_CTRL_RSVD4 0x00300000
+#define BF_BCH_CTRL_RSVD4(v) (((v) << 20) & BM_BCH_CTRL_RSVD4)
+#define BP_BCH_CTRL_M2M_LAYOUT 18
+#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000
+#define BF_BCH_CTRL_M2M_LAYOUT(v) (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT)
+#define BM_BCH_CTRL_M2M_ENCODE 0x00020000
+#define BM_BCH_CTRL_M2M_ENABLE 0x00010000
+#define BP_BCH_CTRL_RSVD3 11
+#define BM_BCH_CTRL_RSVD3 0x0000F800
+#define BF_BCH_CTRL_RSVD3(v) (((v) << 11) & BM_BCH_CTRL_RSVD3)
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400
+#define BM_BCH_CTRL_RSVD2 0x00000200
+#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
+#define BP_BCH_CTRL_RSVD1 4
+#define BM_BCH_CTRL_RSVD1 0x000000F0
+#define BF_BCH_CTRL_RSVD1(v) (((v) << 4) & BM_BCH_CTRL_RSVD1)
+#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008
+#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004
+#define BM_BCH_CTRL_RSVD0 0x00000002
+#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
+
+/*============================================================================*/
+
+#define HW_BCH_STATUS0 (0x00000010)
+
+#define BP_BCH_STATUS0_HANDLE 20
+#define BM_BCH_STATUS0_HANDLE 0xFFF00000
+#define BF_BCH_STATUS0_HANDLE(v) \
+ (((v) << 20) & BM_BCH_STATUS0_HANDLE)
+#define BP_BCH_STATUS0_COMPLETED_CE 16
+#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
+#define BF_BCH_STATUS0_COMPLETED_CE(v) \
+ (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE)
+#define BP_BCH_STATUS0_STATUS_BLK0 8
+#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
+#define BF_BCH_STATUS0_STATUS_BLK0(v) \
+ (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0)
+#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03
+#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04
+#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE
+#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF
+#define BP_BCH_STATUS0_RSVD1 5
+#define BM_BCH_STATUS0_RSVD1 0x000000E0
+#define BF_BCH_STATUS0_RSVD1(v) \
+ (((v) << 5) & BM_BCH_STATUS0_RSVD1)
+#define BM_BCH_STATUS0_ALLONES 0x00000010
+#define BM_BCH_STATUS0_CORRECTED 0x00000008
+#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
+#define BP_BCH_STATUS0_RSVD0 0
+#define BM_BCH_STATUS0_RSVD0 0x00000003
+#define BF_BCH_STATUS0_RSVD0(v) \
+ (((v) << 0) & BM_BCH_STATUS0_RSVD0)
+
+/*============================================================================*/
+
+#define HW_BCH_MODE (0x00000020)
+
+#define BP_BCH_MODE_RSVD 8
+#define BM_BCH_MODE_RSVD 0xFFFFFF00
+#define BF_BCH_MODE_RSVD(v) \
+ (((v) << 8) & BM_BCH_MODE_RSVD)
+#define BP_BCH_MODE_ERASE_THRESHOLD 0
+#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF
+#define BF_BCH_MODE_ERASE_THRESHOLD(v) \
+ (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD)
+
+/*============================================================================*/
+
+#define HW_BCH_ENCODEPTR (0x00000030)
+
+#define BP_BCH_ENCODEPTR_ADDR 0
+#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_ENCODEPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DATAPTR (0x00000040)
+
+#define BP_BCH_DATAPTR_ADDR 0
+#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_DATAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_METAPTR (0x00000050)
+
+#define BP_BCH_METAPTR_ADDR 0
+#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF
+#define BF_BCH_METAPTR_ADDR(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_LAYOUTSELECT (0x00000070)
+
+#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30
+#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000
+#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \
+ (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28
+#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000
+#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \
+ (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26
+#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000
+#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \
+ (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24
+#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000
+#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \
+ (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22
+#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000
+#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \
+ (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20
+#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000
+#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \
+ (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18
+#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000
+#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \
+ (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16
+#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000
+#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \
+ (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14
+#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000
+#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \
+ (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12
+#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000
+#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \
+ (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10
+#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00
+#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \
+ (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8
+#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300
+#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \
+ (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6
+#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0
+#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \
+ (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4
+#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030
+#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \
+ (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2
+#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C
+#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \
+ (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT)
+#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0
+#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003
+#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \
+ (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT0 (0x00000080)
+
+#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH0LAYOUT0_ECC0 12
+#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0)
+#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH0LAYOUT1 (0x00000090)
+
+#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH0LAYOUT1_ECCN 12
+#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN)
+#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT0 (0x000000a0)
+
+#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH1LAYOUT0_ECC0 12
+#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0)
+#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH1LAYOUT1 (0x000000b0)
+
+#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH1LAYOUT1_ECCN 12
+#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN)
+#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT0 (0x000000c0)
+
+#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH2LAYOUT0_ECC0 12
+#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0)
+#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH2LAYOUT1 (0x000000d0)
+
+#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH2LAYOUT1_ECCN 12
+#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN)
+#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT0 (0x000000e0)
+
+#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24
+#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000
+#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \
+ (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS)
+#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16
+#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000
+#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE)
+#define BP_BCH_FLASH3LAYOUT0_ECC0 12
+#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000
+#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0)
+#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0
+#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_FLASH3LAYOUT1 (0x000000f0)
+
+#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16
+#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000
+#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \
+ (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE)
+#define BP_BCH_FLASH3LAYOUT1_ECCN 12
+#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000
+#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \
+ (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN)
+#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9
+#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA
+#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0
+#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF
+#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \
+ (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE)
+
+/*============================================================================*/
+
+#define HW_BCH_DEBUG0 (0x00000100)
+#define HW_BCH_DEBUG0_SET (0x00000104)
+#define HW_BCH_DEBUG0_CLR (0x00000108)
+#define HW_BCH_DEBUG0_TOG (0x0000010c)
+
+#define BP_BCH_DEBUG0_RSVD1 27
+#define BM_BCH_DEBUG0_RSVD1 0xF8000000
+#define BF_BCH_DEBUG0_RSVD1(v) \
+ (((v) << 27) & BM_BCH_DEBUG0_RSVD1)
+#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000
+#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000
+#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16
+#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000
+#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \
+ (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL)
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000
+#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1
+#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000
+#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800
+#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1
+#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400
+#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0
+#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1
+#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0
+#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1
+#define BP_BCH_DEBUG0_RSVD0 6
+#define BM_BCH_DEBUG0_RSVD0 0x000000C0
+#define BF_BCH_DEBUG0_RSVD0(v) \
+ (((v) << 6) & BM_BCH_DEBUG0_RSVD0)
+#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0
+#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F
+#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \
+ (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGKESREAD (0x00000110)
+
+#define BP_BCH_DBGKESREAD_VALUES 0
+#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGKESREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGCSFEREAD (0x00000120)
+
+#define BP_BCH_DBGCSFEREAD_VALUES 0
+#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGCSFEREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGSYNDGENREAD (0x00000130)
+
+#define BP_BCH_DBGSYNDGENREAD_VALUES 0
+#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_DBGAHBMREAD (0x00000140)
+
+#define BP_BCH_DBGAHBMREAD_VALUES 0
+#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF
+#define BF_BCH_DBGAHBMREAD_VALUES(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_BLOCKNAME (0x00000150)
+
+#define BP_BCH_BLOCKNAME_NAME 0
+#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF
+#define BF_BCH_BLOCKNAME_NAME(v) (v)
+
+/*============================================================================*/
+
+#define HW_BCH_VERSION (0x00000160)
+
+#define BP_BCH_VERSION_MAJOR 24
+#define BM_BCH_VERSION_MAJOR 0xFF000000
+#define BF_BCH_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_BCH_VERSION_MAJOR)
+#define BP_BCH_VERSION_MINOR 16
+#define BM_BCH_VERSION_MINOR 0x00FF0000
+#define BF_BCH_VERSION_MINOR(v) \
+ (((v) << 16) & BM_BCH_VERSION_MINOR)
+#define BP_BCH_VERSION_STEP 0
+#define BM_BCH_VERSION_STEP 0x0000FFFF
+#define BF_BCH_VERSION_STEP(v) \
+ (((v) << 0) & BM_BCH_VERSION_STEP)
+
+/*============================================================================*/
+
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
new file mode 100644
index 0000000..2f9fce6
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/gpmi-regs-imx23.h
@@ -0,0 +1,416 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GPMI_NFC_GPMI_REGS_H
+#define __GPMI_NFC_GPMI_REGS_H
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL0 (0x00000000)
+#define HW_GPMI_CTRL0_SET (0x00000004)
+#define HW_GPMI_CTRL0_CLR (0x00000008)
+#define HW_GPMI_CTRL0_TOG (0x0000000c)
+
+#define BM_GPMI_CTRL0_SFTRST 0x80000000
+#define BV_GPMI_CTRL0_SFTRST__RUN 0x0
+#define BV_GPMI_CTRL0_SFTRST__RESET 0x1
+#define BM_GPMI_CTRL0_CLKGATE 0x40000000
+#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0
+#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_GPMI_CTRL0_RUN 0x20000000
+#define BV_GPMI_CTRL0_RUN__IDLE 0x0
+#define BV_GPMI_CTRL0_RUN__BUSY 0x1
+#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000
+#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x08000000
+#define BM_GPMI_CTRL0_UDMA 0x04000000
+#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0
+#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1
+#define BP_GPMI_CTRL0_COMMAND_MODE 24
+#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
+#define BF_GPMI_CTRL0_COMMAND_MODE(v) \
+ (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE)
+#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
+#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
+#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
+#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
+#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0
+#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1
+#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
+#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0
+#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1
+#define BP_GPMI_CTRL0_CS 20
+#define BM_GPMI_CTRL0_CS 0x00300000
+#define BF_GPMI_CTRL0_CS(v) (((v) << 20) & BM_GPMI_CTRL0_CS)
+#define BP_GPMI_CTRL0_ADDRESS 17
+#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
+#define BF_GPMI_CTRL0_ADDRESS(v) (((v) << 17) & BM_GPMI_CTRL0_ADDRESS)
+#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
+#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
+#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
+#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0
+#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1
+#define BP_GPMI_CTRL0_XFER_COUNT 0
+#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
+#define BF_GPMI_CTRL0_XFER_COUNT(v) \
+ (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_COMPARE (0x00000010)
+
+#define BP_GPMI_COMPARE_MASK 16
+#define BM_GPMI_COMPARE_MASK 0xFFFF0000
+#define BF_GPMI_COMPARE_MASK(v) (((v) << 16) & BM_GPMI_COMPARE_MASK)
+#define BP_GPMI_COMPARE_REFERENCE 0
+#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF
+#define BF_GPMI_COMPARE_REFERENCE(v) \
+ (((v) << 0) & BM_GPMI_COMPARE_REFERENCE)
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCTRL (0x00000020)
+#define HW_GPMI_ECCCTRL_SET (0x00000024)
+#define HW_GPMI_ECCCTRL_CLR (0x00000028)
+#define HW_GPMI_ECCCTRL_TOG (0x0000002c)
+
+#define BP_GPMI_ECCCTRL_HANDLE 16
+#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000
+#define BF_GPMI_ECCCTRL_HANDLE(v) (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE)
+#define BM_GPMI_ECCCTRL_RSVD2 0x00008000
+#define BP_GPMI_ECCCTRL_ECC_CMD 13
+#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
+#define BF_GPMI_ECCCTRL_ECC_CMD(v) (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD)
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1
+#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2
+#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE 0x0
+#define BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE 0x1
+#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1
+#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0
+#define BP_GPMI_ECCCTRL_RSVD1 9
+#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00
+#define BF_GPMI_ECCCTRL_RSVD1(v) (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1)
+#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
+#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
+#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \
+ (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK)
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x080
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x040
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x020
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x010
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x008
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x004
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x002
+#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x001
+
+/*============================================================================*/
+
+#define HW_GPMI_ECCCOUNT (0x00000030)
+
+#define BP_GPMI_ECCCOUNT_RSVD2 16
+#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000
+#define BF_GPMI_ECCCOUNT_RSVD2(v) (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2)
+#define BP_GPMI_ECCCOUNT_COUNT 0
+#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF
+#define BF_GPMI_ECCCOUNT_COUNT(v) (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT)
+
+/*============================================================================*/
+
+#define HW_GPMI_PAYLOAD (0x00000040)
+
+#define BP_GPMI_PAYLOAD_ADDRESS 2
+#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_PAYLOAD_ADDRESS(v) (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS)
+#define BP_GPMI_PAYLOAD_RSVD0 0
+#define BM_GPMI_PAYLOAD_RSVD0 0x00000003
+#define BF_GPMI_PAYLOAD_RSVD0(v) (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_AUXILIARY (0x00000050)
+
+#define BP_GPMI_AUXILIARY_ADDRESS 2
+#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC
+#define BF_GPMI_AUXILIARY_ADDRESS(v) \
+ (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS)
+#define BP_GPMI_AUXILIARY_RSVD0 0
+#define BM_GPMI_AUXILIARY_RSVD0 0x00000003
+#define BF_GPMI_AUXILIARY_RSVD0(v) (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0)
+
+/*============================================================================*/
+
+#define HW_GPMI_CTRL1 (0x00000060)
+#define HW_GPMI_CTRL1_SET (0x00000064)
+#define HW_GPMI_CTRL1_CLR (0x00000068)
+#define HW_GPMI_CTRL1_TOG (0x0000006c)
+
+#define BP_GPMI_CTRL1_RSVD2 24
+#define BM_GPMI_CTRL1_RSVD2 0xFF000000
+#define BF_GPMI_CTRL1_RSVD2(v) \
+ (((v) << 24) & BM_GPMI_CTRL1_RSVD2)
+#define BM_GPMI_CTRL1_CE3_SEL 0x00800000
+#define BM_GPMI_CTRL1_CE2_SEL 0x00400000
+#define BM_GPMI_CTRL1_CE1_SEL 0x00200000
+#define BM_GPMI_CTRL1_CE0_SEL 0x00100000
+#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BP_GPMI_CTRL1_GPMI_MODE 0
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
+#define BP_GPMI_CTRL1_DLL_ENABLE 17
+#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000
+#define BP_GPMI_CTRL1_HALF_PERIOD 16
+#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000
+#define BP_GPMI_CTRL1_RDN_DELAY 12
+#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
+#define BF_GPMI_CTRL1_RDN_DELAY(v) \
+ (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY)
+#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800
+#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
+#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
+#define BM_GPMI_CTRL1_BURST_EN 0x00000100
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x00000080
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x00000040
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x00000020
+#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x00000010
+#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
+#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0
+#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1
+#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0
+#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1
+#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002
+#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
+#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0
+#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING0 (0x00000070)
+
+#define BP_GPMI_TIMING0_RSVD1 24
+#define BM_GPMI_TIMING0_RSVD1 0xFF000000
+#define BF_GPMI_TIMING0_RSVD1(v) \
+ (((v) << 24) & BM_GPMI_TIMING0_RSVD1)
+#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
+#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
+#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \
+ (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP)
+#define BP_GPMI_TIMING0_DATA_HOLD 8
+#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING0_DATA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD)
+#define BP_GPMI_TIMING0_DATA_SETUP 0
+#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
+#define BF_GPMI_TIMING0_DATA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING1 (0x00000080)
+
+#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
+#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
+#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \
+ (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT)
+#define BP_GPMI_TIMING1_RSVD1 0
+#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF
+#define BF_GPMI_TIMING1_RSVD1(v) \
+ (((v) << 0) & BM_GPMI_TIMING1_RSVD1)
+
+/*============================================================================*/
+
+#define HW_GPMI_TIMING2 (0x00000090)
+
+#define BP_GPMI_TIMING2_UDMA_TRP 24
+#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000
+#define BF_GPMI_TIMING2_UDMA_TRP(v) \
+ (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP)
+#define BP_GPMI_TIMING2_UDMA_ENV 16
+#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000
+#define BF_GPMI_TIMING2_UDMA_ENV(v) \
+ (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV)
+#define BP_GPMI_TIMING2_UDMA_HOLD 8
+#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00
+#define BF_GPMI_TIMING2_UDMA_HOLD(v) \
+ (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD)
+#define BP_GPMI_TIMING2_UDMA_SETUP 0
+#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF
+#define BF_GPMI_TIMING2_UDMA_SETUP(v) \
+ (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DATA (0x000000a0)
+
+#define BP_GPMI_DATA_DATA 0
+#define BM_GPMI_DATA_DATA 0xFFFFFFFF
+#define BF_GPMI_DATA_DATA(v) (v)
+
+/*============================================================================*/
+
+#define HW_GPMI_STAT (0x000000b0)
+
+#define BM_GPMI_STAT_PRESENT 0x80000000
+#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0
+#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1
+#define BP_GPMI_STAT_RSVD1 12
+#define BM_GPMI_STAT_RSVD1 0x7FFFF000
+#define BF_GPMI_STAT_RSVD1(v) \
+ (((v) << 12) & BM_GPMI_STAT_RSVD1)
+#define BP_GPMI_STAT_RDY_TIMEOUT 8
+#define BM_GPMI_STAT_RDY_TIMEOUT 0x00000F00
+#define BF_GPMI_STAT_RDY_TIMEOUT(v) \
+ (((v) << 8) & BM_GPMI_STAT_RDY_TIMEOUT)
+#define BM_GPMI_STAT_ATA_IRQ 0x00000080
+#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000040
+#define BM_GPMI_STAT_FIFO_EMPTY 0x00000020
+#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0
+#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1
+#define BM_GPMI_STAT_FIFO_FULL 0x00000010
+#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0
+#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1
+#define BM_GPMI_STAT_DEV3_ERROR 0x00000008
+#define BM_GPMI_STAT_DEV2_ERROR 0x00000004
+#define BM_GPMI_STAT_DEV1_ERROR 0x00000002
+#define BM_GPMI_STAT_DEERROR 0x00000001
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG (0x000000c0)
+
+#define BM_GPMI_DEBUG_READY3 0x80000000
+#define BM_GPMI_DEBUG_READY2 0x40000000
+#define BM_GPMI_DEBUG_READY1 0x20000000
+#define BM_GPMI_DEBUG_READY0 0x10000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x08000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x04000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x02000000
+#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x01000000
+#define BM_GPMI_DEBUG_SENSE3 0x00800000
+#define BM_GPMI_DEBUG_SENSE2 0x00400000
+#define BM_GPMI_DEBUG_SENSE1 0x00200000
+#define BM_GPMI_DEBUG_SENSE0 0x00100000
+#define BM_GPMI_DEBUG_DMAREQ3 0x00080000
+#define BM_GPMI_DEBUG_DMAREQ2 0x00040000
+#define BM_GPMI_DEBUG_DMAREQ1 0x00020000
+#define BM_GPMI_DEBUG_DMAREQ0 0x00010000
+#define BP_GPMI_DEBUG_CMD_END 12
+#define BM_GPMI_DEBUG_CMD_END 0x0000F000
+#define BF_GPMI_DEBUG_CMD_END(v) \
+ (((v) << 12) & BM_GPMI_DEBUG_CMD_END)
+#define BP_GPMI_DEBUG_UDMA_STATE 8
+#define BM_GPMI_DEBUG_UDMA_STATE 0x00000F00
+#define BF_GPMI_DEBUG_UDMA_STATE(v) \
+ (((v) << 8) & BM_GPMI_DEBUG_UDMA_STATE)
+#define BM_GPMI_DEBUG_BUSY 0x00000080
+#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0
+#define BV_GPMI_DEBUG_BUSY__ENABLED 0x1
+#define BP_GPMI_DEBUG_PIN_STATE 4
+#define BM_GPMI_DEBUG_PIN_STATE 0x00000070
+#define BF_GPMI_DEBUG_PIN_STATE(v) \
+ (((v) << 4) & BM_GPMI_DEBUG_PIN_STATE)
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6
+#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7
+#define BP_GPMI_DEBUG_MAIN_STATE 0
+#define BM_GPMI_DEBUG_MAIN_STATE 0x0000000F
+#define BF_GPMI_DEBUG_MAIN_STATE(v) \
+ (((v) << 0) & BM_GPMI_DEBUG_MAIN_STATE)
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9
+#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xA
+
+/*============================================================================*/
+
+#define HW_GPMI_VERSION (0x000000d0)
+
+#define BP_GPMI_VERSION_MAJOR 24
+#define BM_GPMI_VERSION_MAJOR 0xFF000000
+#define BF_GPMI_VERSION_MAJOR(v) (((v) << 24) & BM_GPMI_VERSION_MAJOR)
+#define BP_GPMI_VERSION_MINOR 16
+#define BM_GPMI_VERSION_MINOR 0x00FF0000
+#define BF_GPMI_VERSION_MINOR(v) (((v) << 16) & BM_GPMI_VERSION_MINOR)
+#define BP_GPMI_VERSION_STEP 0
+#define BM_GPMI_VERSION_STEP 0x0000FFFF
+#define BF_GPMI_VERSION_STEP(v) (((v) << 0) & BM_GPMI_VERSION_STEP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG2 (0x000000e0)
+
+#define BP_GPMI_DEBUG2_RSVD1 16
+#define BM_GPMI_DEBUG2_RSVD1 0xFFFF0000
+#define BF_GPMI_DEBUG2_RSVD1(v) (((v) << 16) & BM_GPMI_DEBUG2_RSVD1)
+#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12
+#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000
+#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \
+ (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE)
+#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800
+#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400
+#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200
+#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100
+#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080
+#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040
+#define BP_GPMI_DEBUG2_RDN_TAP 0
+#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F
+#define BF_GPMI_DEBUG2_RDN_TAP(v) (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP)
+
+/*============================================================================*/
+
+#define HW_GPMI_DEBUG3 (0x000000f0)
+
+#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16
+#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000
+#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \
+ (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR)
+#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0
+#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF
+#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \
+ (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR)
+
+/*============================================================================*/
+#endif
diff --git a/drivers/mtd/nand/gpmi-nfc/hal-imx23.c b/drivers/mtd/nand/gpmi-nfc/hal-imx23.c
new file mode 100644
index 0000000..155ad67
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/hal-imx23.c
@@ -0,0 +1,556 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+#include "gpmi-regs-imx23.h"
+#include "bch-regs-imx23.h"
+
+static int init_hal_imx23(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+
+ /* Enable the clock */
+ clk_enable(resources->clock);
+
+ /* Reset the GPMI block. */
+ mxs_reset_block(resources->gpmi_regs);
+
+ /* Choose NAND mode. */
+ __raw_writel(BM_GPMI_CTRL1_GPMI_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Set the IRQ polarity. */
+ __raw_writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable write protection. */
+ __raw_writel(BM_GPMI_CTRL1_DEV_RESET,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Select BCH ECC. */
+ __raw_writel(BM_GPMI_CTRL1_BCH_MODE,
+ resources->gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Disable the clock. */
+ clk_disable(resources->clock);
+ return 0;
+}
+
+/* Configures the NFC geometry for BCH. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_geometry *nfc = &this->nfc_geometry;
+ unsigned int block_count;
+ unsigned int block_size;
+ unsigned int metadata_size;
+ unsigned int ecc_strength;
+ unsigned int page_size;
+
+ if (common_nfc_set_geometry(this))
+ return !0;
+
+ block_count = nfc->ecc_chunk_count - 1;
+ block_size = nfc->ecc_chunk_size_in_bytes;
+ metadata_size = nfc->metadata_size_in_bytes;
+ ecc_strength = nfc->ecc_strength >> 1;
+ page_size = nfc->page_size_in_bytes;
+
+ clk_enable(resources->clock);
+
+ /*
+ * Reset the BCH block. Notice that we pass in true for the just_enable
+ * flag. This is because the soft reset for the version 0 BCH block
+ * doesn't work. If you try to soft reset the BCH block, it becomes
+ * unusable until the next hard reset.
+ */
+ mxs_reset_block(resources->bch_regs);
+
+ /* Configure layout 0. */
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count) |
+ BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size) |
+ BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT0);
+
+ __raw_writel(
+ BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) |
+ BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength) |
+ BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size) ,
+ resources->bch_regs + HW_BCH_FLASH0LAYOUT1);
+
+ /* Set *all* chip selects to use layout 0. */
+ __raw_writel(0, resources->bch_regs + HW_BCH_LAYOUTSELECT);
+
+ /* Enable interrupts. */
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
+ resources->bch_regs + HW_BCH_CTRL_SET);
+
+ clk_disable(resources->clock);
+ return 0;
+}
+
+static int set_timing(struct gpmi_nfc_data *this,
+ const struct nand_timing *timing)
+{
+ struct nfc_hal *nfc = this->nfc;
+
+ nfc->timing = *timing;
+ return 0;
+}
+
+/**
+ * get_timing() - Retrieves the NFC hardware timing.
+ *
+ * @this: Per-device data.
+ * @clock_frequency_in_hz: The clock frequency, in Hz, during the current
+ * I/O transaction. If no I/O transaction is in
+ * progress, this is the clock frequency during the
+ * most recent I/O transaction.
+ * @hardware_timing: The hardware timing configuration in effect during
+ * the current I/O transaction. If no I/O transaction
+ * is in progress, this is the hardware timing
+ * configuration during the most recent I/O
+ * transaction.
+ */
+static void get_timing(struct gpmi_nfc_data *this,
+ unsigned long *clock_frequency_in_hz,
+ struct gpmi_nfc_hardware_timing *hardware_timing)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ uint32_t register_image;
+
+ /* Return the clock frequency. */
+ *clock_frequency_in_hz = nfc->clock_frequency_in_hz;
+
+ /* We'll be reading the hardware, so let's enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Retrieve the hardware timing. */
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_TIMING0);
+
+ hardware_timing->data_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_SETUP) >>
+ BP_GPMI_TIMING0_DATA_SETUP;
+
+ hardware_timing->data_hold_in_cycles =
+ (register_image & BM_GPMI_TIMING0_DATA_HOLD) >>
+ BP_GPMI_TIMING0_DATA_HOLD;
+
+ hardware_timing->address_setup_in_cycles =
+ (register_image & BM_GPMI_TIMING0_ADDRESS_SETUP) >>
+ BP_GPMI_TIMING0_ADDRESS_SETUP;
+
+ register_image = __raw_readl(gpmi_regs + HW_GPMI_CTRL1);
+
+ hardware_timing->use_half_periods =
+ (register_image & BM_GPMI_CTRL1_HALF_PERIOD) >>
+ BP_GPMI_CTRL1_HALF_PERIOD;
+
+ hardware_timing->sample_delay_factor =
+ (register_image & BM_GPMI_CTRL1_RDN_DELAY) >>
+ BP_GPMI_CTRL1_RDN_DELAY;
+
+ /* We're done reading the hardware, so disable the clock. */
+ clk_disable(resources->clock);
+}
+
+static void exit(struct gpmi_nfc_data *this)
+{
+}
+
+/* Begin the I/O */
+static void begin(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ struct nfc_hal *nfc = this->nfc;
+ struct gpmi_nfc_hardware_timing hw;
+ unsigned char *gpmi_regs = resources->gpmi_regs;
+ unsigned int clock_period_in_ns;
+ uint32_t register_image;
+ unsigned int dll_wait_time_in_us;
+
+ /* Enable the clock. */
+ clk_enable(resources->clock);
+
+ /* Get the timing information we need. */
+ nfc->clock_frequency_in_hz = clk_get_rate(resources->clock);
+ clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
+
+ gpmi_nfc_compute_hardware_timing(this, &hw);
+
+ /* Set up all the simple timing parameters. */
+ register_image =
+ BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
+ BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
+ BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
+
+ __raw_writel(register_image, gpmi_regs + HW_GPMI_TIMING0);
+
+ /*
+ * HEY - PAY ATTENTION!
+ *
+ * DLL_ENABLE must be set to zero when setting RDN_DELAY or HALF_PERIOD.
+ */
+ __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* Clear out the DLL control fields. */
+ __raw_writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR);
+ __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
+
+ /* If no sample delay is called for, return immediately. */
+ if (!hw.sample_delay_factor)
+ return;
+
+ /* Configure the HALF_PERIOD flag. */
+
+ if (hw.use_half_periods)
+ __raw_writel(BM_GPMI_CTRL1_HALF_PERIOD,
+ gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Set the delay factor. */
+ __raw_writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
+ gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /* Enable the DLL. */
+ __raw_writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
+
+ /*
+ * After we enable the GPMI DLL, we have to wait 64 clock cycles before
+ * we can use the GPMI.
+ *
+ * Calculate the amount of time we need to wait, in microseconds.
+ */
+ dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
+
+ if (!dll_wait_time_in_us)
+ dll_wait_time_in_us = 1;
+
+ /* Wait for the DLL to settle. */
+ udelay(dll_wait_time_in_us);
+}
+
+static void end(struct gpmi_nfc_data *this)
+{
+ struct resources *resources = &this->resources;
+ clk_disable(resources->clock);
+}
+
+/* Clears a BCH interrupt. */
+static void clear_bch(struct gpmi_nfc_data *this)
+{
+ struct resources *r = &this->resources;
+ __raw_writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
+}
+
+/* Returns the Ready/Busy status of the given chip. */
+static int is_ready(struct gpmi_nfc_data *this, unsigned chip)
+{
+ struct resources *resources = &this->resources;
+ uint32_t mask;
+ uint32_t register_image;
+
+ mask = BM_GPMI_DEBUG_READY0 << chip;
+ register_image = __raw_readl(resources->gpmi_regs + HW_GPMI_DEBUG);
+ return !!(register_image & mask);
+}
+
+static int send_command(struct gpmi_nfc_data *this)
+{
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ struct dma_async_tx_descriptor *desc;
+ struct scatterlist *sgl;
+ u32 pio[3];
+
+ /* [1] send out the PIO words */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
+ | BM_GPMI_CTRL0_ADDRESS_INCREMENT
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->command_length);
+ pio[1] = pio[2] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
+ sgl = &mil->cmd_sgl;
+
+ dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
+ sgl->length = mil->command_length;
+ desc = channel->device->device_prep_slave_sg(channel,
+ sgl, 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("error");
+ return -1;
+ }
+
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_COMMAND;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ uint32_t command_mode;
+ uint32_t address;
+ u32 pio[2];
+
+ log();
+ /* [1] PIO */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(mil->current_chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* step 2 : send DMA request */
+ prepare_data_dma(this, DMA_TO_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_TO_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ /* [2] submit the DMA */
+ this->dma_type = DMA_FOR_WRITE_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int read_data(struct gpmi_nfc_data *this)
+{
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ u32 pio[2];
+
+ /* step 1 : send PIO */
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(mil->current_chip)
+ | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
+ | BF_GPMI_CTRL0_XFER_COUNT(mil->upper_len);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* step 2 : send DMA request */
+ prepare_data_dma(this, DMA_FROM_DEVICE);
+ desc = channel->device->device_prep_slave_sg(channel, &mil->data_sgl,
+ 1, DMA_FROM_DEVICE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] submit the DMA */
+ this->dma_type = DMA_FOR_READ_DATA;
+ start_dma_without_bch_irq(this, desc);
+ return 0;
+}
+
+static int send_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* A DMA descriptor that does an ECC page read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
+ BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(0) ;
+ pio[1] = 0;
+ pio[2] =
+ BM_GPMI_ECCCTRL_ENABLE_ECC |
+ BF_GPMI_ECCCTRL_ECC_CMD(ecc_command) |
+ BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask) ;
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 0);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+ this->dma_type = DMA_FOR_WRITE_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+static int read_page(struct gpmi_nfc_data *this,
+ dma_addr_t payload, dma_addr_t auxiliary)
+{
+ struct nfc_geometry *geo = &this->nfc_geometry;
+ uint32_t command_mode;
+ uint32_t address;
+ uint32_t ecc_command;
+ uint32_t buffer_mask;
+
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *channel = get_dma_chan(this);
+ struct mil *mil = &this->mil;
+ int chip = mil->current_chip;
+ u32 pio[6];
+
+ /* [1] Wait for the chip to report ready. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(0);
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 0);
+ if (!desc) {
+ log("step 1 error");
+ return -1;
+ }
+
+ /* [2] Enable the BCH block and read. */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+ ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
+ buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
+ | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
+
+ pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
+ | BM_GPMI_CTRL0_WORD_LENGTH
+ | BF_GPMI_CTRL0_CS(chip)
+ | BF_GPMI_CTRL0_ADDRESS(address)
+ | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes);
+
+ pio[1] = 0;
+ pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
+ | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
+ | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
+ pio[3] = geo->page_size_in_bytes;
+ pio[4] = payload;
+ pio[5] = auxiliary;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio,
+ ARRAY_SIZE(pio), DMA_NONE, 1);
+ if (!desc) {
+ log("step 2 error");
+ return -1;
+ }
+
+ /* [3] Disable the BCH block */
+ command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
+ address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
+
+ pio[0] =
+ BF_GPMI_CTRL0_COMMAND_MODE(command_mode) |
+ BM_GPMI_CTRL0_WORD_LENGTH |
+ BF_GPMI_CTRL0_CS(chip) |
+ BF_GPMI_CTRL0_ADDRESS(address) |
+ BF_GPMI_CTRL0_XFER_COUNT(geo->page_size_in_bytes) ;
+ pio[1] = 0;
+ desc = channel->device->device_prep_slave_sg(channel,
+ (struct scatterlist *)pio, 2, DMA_NONE, 1);
+ if (!desc) {
+ log("step 3 error");
+ return -1;
+ }
+
+ /* [4] submit the DMA */
+ this->dma_type = DMA_FOR_READ_ECC_PAGE;
+ return start_dma_with_bch_irq(this, desc);
+}
+
+/* The NFC HAL for IMX23 */
+struct nfc_hal gpmi_nfc_hal_imx23 = {
+ .version = 0,
+ .description = "4-chip GPMI and BCH for IMX23",
+ .max_chip_count = 4,
+ .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
+ BP_GPMI_TIMING0_DATA_SETUP),
+ .internal_data_setup_in_ns = 0,
+ .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
+ BP_GPMI_CTRL1_RDN_DELAY),
+ .max_dll_clock_period_in_ns = 32,
+ .max_dll_delay_in_ns = 16,
+ .init = init_hal_imx23,
+ .set_geometry = set_geometry,
+ .set_timing = set_timing,
+ .get_timing = get_timing,
+ .exit = exit,
+ .begin = begin,
+ .end = end,
+ .clear_bch = clear_bch,
+ .is_ready = is_ready,
+ .send_command = send_command,
+ .read_data = read_data,
+ .send_data = send_data,
+ .read_page = read_page,
+ .send_page = send_page,
+};
diff --git a/drivers/mtd/nand/gpmi-nfc/rom-imx23.c b/drivers/mtd/nand/gpmi-nfc/rom-imx23.c
new file mode 100644
index 0000000..8193874
--- /dev/null
+++ b/drivers/mtd/nand/gpmi-nfc/rom-imx23.c
@@ -0,0 +1,300 @@
+/*
+ * Freescale GPMI NFC NAND Flash Driver
+ *
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include "gpmi-nfc.h"
+
+/* Useful variables for Boot ROM Helper version 0. */
+static const char *fingerprint = "STMP";
+
+/* Sets geometry for the Boot ROM Helper. */
+static int set_geometry(struct gpmi_nfc_data *this)
+{
+ struct gpmi_nfc_platform_data *pdata = this->pdata;
+ struct boot_rom_geometry *geometry = &this->rom_geometry;
+ struct nand_chip *nand = &this->mil.nand;
+ int error;
+
+ error = gpmi_nfc_rom_helper_set_geometry(this);
+ if (error)
+ return error;
+
+ if (!pdata->boot_area_size_in_bytes) {
+ geometry->boot_area_count = 0;
+ geometry->boot_area_size_in_bytes = 0;
+ return 0;
+ }
+
+ if (nand->numchips == 1) {
+ geometry->boot_area_count = 1;
+ geometry->boot_area_size_in_bytes =
+ pdata->boot_area_size_in_bytes * 2;
+ } else {
+ geometry->boot_area_count = 2;
+ geometry->boot_area_size_in_bytes =
+ pdata->boot_area_size_in_bytes;
+ }
+ return 0;
+}
+
+static int check_transcription_stamp(struct gpmi_nfc_data *this)
+{
+ struct boot_rom_geometry *rom_geo = &this->rom_geometry;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ unsigned int search_area_size_in_strides;
+ unsigned int stride;
+ unsigned int page;
+ loff_t byte;
+ uint8_t *buffer = nand->buffers->databuf;
+ int saved_chip_number;
+ int found_an_ncb_fingerprint = false;
+
+ /* Compute the number of strides in a search area. */
+ search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+
+ /* Select chip 0. */
+ saved_chip_number = mil->current_chip;
+ nand->select_chip(mtd, 0);
+
+ /*
+ * Loop through the first search area, looking for the NCB fingerprint.
+ */
+ pr_info("Scanning for an NCB fingerprint...\n");
+
+ for (stride = 0; stride < search_area_size_in_strides; stride++) {
+ /* Compute the page and byte addresses. */
+ page = stride * rom_geo->stride_size_in_pages;
+ byte = page * mtd->writesize;
+
+ pr_info(" Looking for a fingerprint in page 0x%x\n", page);
+
+ /*
+ * Read the NCB fingerprint. The fingerprint is four bytes long
+ * and starts in the 12th byte of the page.
+ */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, 12, page);
+ nand->read_buf(mtd, buffer, strlen(fingerprint));
+
+ /* Look for the fingerprint. */
+ if (!memcmp(buffer, fingerprint, strlen(fingerprint))) {
+ found_an_ncb_fingerprint = true;
+ break;
+ }
+
+ }
+
+ /* Deselect chip 0. */
+ nand->select_chip(mtd, saved_chip_number);
+
+ if (found_an_ncb_fingerprint)
+ pr_info(" Found a fingerprint\n");
+ else
+ pr_info(" No fingerprint found\n");
+ return found_an_ncb_fingerprint;
+}
+
+/* Writes a transcription stamp. */
+static int write_transcription_stamp(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct boot_rom_geometry *rom_geo = &this->rom_geometry;
+ struct nand_device_info *info = &this->device_info;
+ struct mil *mil = &this->mil;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_chip *nand = &mil->nand;
+ unsigned int block_size_in_pages;
+ unsigned int search_area_size_in_strides;
+ unsigned int search_area_size_in_pages;
+ unsigned int search_area_size_in_blocks;
+ unsigned int block;
+ unsigned int stride;
+ unsigned int page;
+ loff_t byte;
+ uint8_t *buffer = nand->buffers->databuf;
+ int saved_chip_number;
+ int status;
+
+ /* Compute the search area geometry. */
+ block_size_in_pages = info->attr.block_size_in_pages;
+ search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
+ search_area_size_in_pages = search_area_size_in_strides *
+ rom_geo->stride_size_in_pages;
+ search_area_size_in_blocks =
+ (search_area_size_in_pages + (block_size_in_pages - 1)) /
+ block_size_in_pages;
+
+ pr_info("-------------------------------------------\n");
+ pr_info("Search Area Geometry\n");
+ pr_info("-------------------------------------------\n");
+ pr_info("Search Area Size in Blocks : %u", search_area_size_in_blocks);
+ pr_info("Search Area Size in Strides: %u", search_area_size_in_strides);
+ pr_info("Search Area Size in Pages : %u", search_area_size_in_pages);
+
+ /* Select chip 0. */
+ saved_chip_number = mil->current_chip;
+ nand->select_chip(mtd, 0);
+
+ /* Loop over blocks in the first search area, erasing them. */
+ pr_info("Erasing the search area...\n");
+
+ for (block = 0; block < search_area_size_in_blocks; block++) {
+ /* Compute the page address. */
+ page = block * block_size_in_pages;
+
+ /* Erase this block. */
+ pr_info(" Erasing block 0x%x\n", block);
+ nand->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+ nand->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
+
+ /* Wait for the erase to finish. */
+ status = nand->waitfunc(mtd, nand);
+ if (status & NAND_STATUS_FAIL)
+ dev_err(dev, "[%s] Erase failed.\n", __func__);
+ }
+
+ /* Write the NCB fingerprint into the page buffer. */
+ memset(buffer, ~0, mtd->writesize);
+ memset(nand->oob_poi, ~0, mtd->oobsize);
+ memcpy(buffer + 12, fingerprint, strlen(fingerprint));
+
+ /* Loop through the first search area, writing NCB fingerprints. */
+ pr_info("Writing NCB fingerprints...\n");
+ for (stride = 0; stride < search_area_size_in_strides; stride++) {
+ /* Compute the page and byte addresses. */
+ page = stride * rom_geo->stride_size_in_pages;
+ byte = page * mtd->writesize;
+
+ /* Write the first page of the current stride. */
+ pr_info(" Writing an NCB fingerprint in page 0x%x\n", page);
+ nand->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+ nand->ecc.write_page_raw(mtd, nand, buffer);
+ nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ /* Wait for the write to finish. */
+ status = nand->waitfunc(mtd, nand);
+ if (status & NAND_STATUS_FAIL)
+ dev_err(dev, "[%s] Write failed.\n", __func__);
+ }
+
+ /* Deselect chip 0. */
+ nand->select_chip(mtd, saved_chip_number);
+ return 0;
+}
+
+static int imx23_rom_extra_init(struct gpmi_nfc_data *this)
+{
+ struct device *dev = this->dev;
+ struct mil *mil = &this->mil;
+ struct nand_chip *nand = &mil->nand;
+ struct mtd_info *mtd = &mil->mtd;
+ struct nand_device_info *info = &this->device_info;
+ unsigned int block_count;
+ unsigned int block;
+ int chip;
+ int page;
+ loff_t byte;
+ uint8_t block_mark;
+ int error = 0;
+
+ /*
+ * If control arrives here, we can't use block mark swapping, which
+ * means we're forced to use transcription. First, scan for the
+ * transcription stamp. If we find it, then we don't have to do
+ * anything -- the block marks are already transcribed.
+ */
+ if (check_transcription_stamp(this))
+ return 0;
+
+ /*
+ * If control arrives here, we couldn't find a transcription stamp, so
+ * so we presume the block marks are in the conventional location.
+ */
+ pr_info("Transcribing bad block marks...\n");
+
+ /* Compute the number of blocks in the entire medium. */
+ block_count = info->attr.chip_size_in_bytes >> nand->phys_erase_shift;
+
+ /*
+ * Loop over all the blocks in the medium, transcribing block marks as
+ * we go.
+ */
+ for (block = 0; block < block_count; block++) {
+ /*
+ * Compute the chip, page and byte addresses for this block's
+ * conventional mark.
+ */
+ chip = block >> (nand->chip_shift - nand->phys_erase_shift);
+ page = block << (nand->phys_erase_shift - nand->page_shift);
+ byte = block << nand->phys_erase_shift;
+
+ /* Select the chip. */
+ nand->select_chip(mtd, chip);
+
+ /* Send the command to read the conventional block mark. */
+ nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+
+ /* Read the conventional block mark. */
+ block_mark = nand->read_byte(mtd);
+
+ /*
+ * Check if the block is marked bad. If so, we need to mark it
+ * again, but this time the result will be a mark in the
+ * location where we transcribe block marks.
+ *
+ * Notice that we have to explicitly set the marking_a_bad_block
+ * member before we call through the block_markbad function
+ * pointer in the owning struct nand_chip. If we could call
+ * though the block_markbad function pointer in the owning
+ * struct mtd_info, which we have hooked, then this would be
+ * taken care of for us. Unfortunately, we can't because that
+ * higher-level code path will do things like consulting the
+ * in-memory bad block table -- which doesn't even exist yet!
+ * So, we have to call at a lower level and handle some details
+ * ourselves.
+ */
+ if (block_mark != 0xff) {
+ pr_info("Transcribing mark in block %u\n", block);
+ mil->marking_a_bad_block = true;
+ error = nand->block_markbad(mtd, byte);
+ mil->marking_a_bad_block = false;
+ if (error)
+ dev_err(dev, "Failed to mark block bad with "
+ "error %d\n", error);
+ }
+
+ /* Deselect the chip. */
+ nand->select_chip(mtd, -1);
+ }
+
+ /* Write the stamp that indicates we've transcribed the block marks. */
+ write_transcription_stamp(this);
+ return 0;
+}
+
+/* This structure represents the Boot ROM Helper for this version. */
+struct boot_rom_helper gpmi_nfc_boot_rom_imx23 = {
+ .version = 0,
+ .description = "Single/dual-chip boot area, "
+ "no block mark swapping",
+ .swap_block_mark = false,
+ .set_geometry = set_geometry,
+ .rom_extra_init = imx23_rom_extra_init,
+};
--
1.7.0.4
^ permalink raw reply related [flat|nested] 49+ messages in thread
end of thread, other threads:[~2011-07-08 16:42 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-03-16 1:55 [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28 Huang Shijie
2011-03-16 1:55 ` Huang Shijie
2011-03-16 1:55 ` [PATCH 1/7] ARM: add GPMI support for imx23/imx28 Huang Shijie
2011-03-16 1:55 ` Huang Shijie
2011-03-16 1:55 ` [PATCH 2/7] add the common code for GPMI driver Huang Shijie
2011-03-16 1:55 ` Huang Shijie
2011-03-16 1:55 ` [PATCH 3/7] add the database for the NANDs Huang Shijie
2011-03-16 1:55 ` Huang Shijie
2011-03-23 15:29 ` Florian Fainelli
2011-03-23 15:29 ` Florian Fainelli
2011-03-24 2:27 ` Huang Shijie
2011-03-24 2:27 ` Huang Shijie
2011-03-24 13:50 ` Florian Fainelli
2011-03-24 13:50 ` Florian Fainelli
2011-03-25 2:47 ` Huang Shijie
2011-03-25 2:47 ` Huang Shijie
2011-03-25 6:48 ` Lothar Waßmann
2011-03-25 6:48 ` Lothar Waßmann
2011-03-25 6:59 ` Huang Shijie
2011-03-25 6:59 ` Huang Shijie
2011-03-31 9:54 ` Artem Bityutskiy
2011-03-31 9:54 ` Artem Bityutskiy
2011-03-31 10:09 ` Huang Shijie
2011-03-31 10:09 ` Huang Shijie
2011-03-16 1:55 ` [PATCH 4/7] add GPMI support for imx23 Huang Shijie
2011-07-08 16:42 ` Huang Shijie
2011-03-16 1:55 ` [PATCH 5/7] add GPMI support for imx28 Huang Shijie
2011-03-16 1:55 ` Huang Shijie
2011-03-31 9:47 ` Artem Bityutskiy
2011-03-31 9:47 ` Artem Bityutskiy
2011-03-31 10:09 ` Huang Shijie
2011-03-31 10:09 ` Huang Shijie
2011-03-31 9:49 ` Artem Bityutskiy
2011-03-31 9:49 ` Artem Bityutskiy
2011-03-31 9:49 ` Artem Bityutskiy
2011-03-31 9:49 ` Artem Bityutskiy
2011-03-16 1:55 ` [PATCH 6/7] dmaengine: change the flags of request_irq() Huang Shijie
2011-03-16 1:55 ` Huang Shijie
2011-03-16 1:55 ` [PATCH 7/7] MTD : add GPMI driver in the config and Makefile Huang Shijie
2011-03-16 1:55 ` Huang Shijie
2011-03-31 9:44 ` Artem Bityutskiy
2011-03-31 9:44 ` Artem Bityutskiy
2011-03-16 7:12 ` [PATCH 0/7] add the GPMI controller driver for IMX23/IMX28 Artem Bityutskiy
2011-03-16 7:12 ` Artem Bityutskiy
2011-03-16 7:30 ` Huang Shijie-B32955
2011-03-16 7:30 ` Huang Shijie-B32955
2011-03-22 10:23 ` Huang Shijie
2011-03-22 10:23 ` Huang Shijie
-- strict thread matches above, loose matches on Subject: below --
2011-03-16 1:42 Huang Shijie
2011-03-16 1:42 ` [PATCH 4/7] add GPMI support for imx23 Huang Shijie
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